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8bae0a0c JSC |
1 | /*> interp.c <*/ |
2 | /* Simulator for the MIPS architecture. | |
3 | ||
4 | This file is part of the MIPS sim | |
5 | ||
6 | THIS SOFTWARE IS NOT COPYRIGHTED | |
7 | ||
8 | Cygnus offers the following for use in the public domain. Cygnus | |
9 | makes no warranty with regard to the software or it's performance | |
10 | and the user accepts the software "AS IS" with all faults. | |
11 | ||
12 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
13 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
14 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
15 | ||
16 | $Revision$ | |
17 | $Author$ | |
e3d12c65 | 18 | $Date$ |
8bae0a0c JSC |
19 | |
20 | NOTEs: | |
21 | ||
22 | We only need to take account of the target endianness when moving data | |
23 | between the simulator and the host. We do not need to worry about the | |
24 | endianness of the host, since this sim code and GDB are executing in | |
25 | the same process. | |
26 | ||
27 | The IDT monitor (found on the VR4300 board), seems to lie about | |
28 | register contents. It seems to treat the registers as sign-extended | |
29 | 32-bit values. This cause *REAL* problems when single-stepping 64-bit | |
30 | code on the hardware. | |
31 | ||
32 | */ | |
33 | ||
34 | /* The TRACE and PROFILE manifests enable the provision of extra | |
35 | features. If they are not defined then a simpler (quicker) | |
36 | simulator is constructed without the required run-time checks, | |
37 | etc. */ | |
38 | #if 1 /* 0 to allow user build selection, 1 to force inclusion */ | |
39 | #define TRACE (1) | |
40 | #define PROFILE (1) | |
41 | #endif | |
42 | ||
4fa134be ILT |
43 | #include "config.h" |
44 | ||
8bae0a0c JSC |
45 | #include <stdio.h> |
46 | #include <stdarg.h> | |
47 | #include <ansidecl.h> | |
48 | #include <signal.h> | |
49 | #include <ctype.h> | |
50 | #include <limits.h> | |
51 | #include <math.h> | |
4fa134be ILT |
52 | #ifdef HAVE_STDLIB_H |
53 | #include <stdlib.h> | |
54 | #endif | |
55 | #ifdef HAVE_STRING_H | |
56 | #include <string.h> | |
57 | #else | |
58 | #ifdef HAVE_STRINGS_H | |
59 | #include <strings.h> | |
60 | #endif | |
61 | #endif | |
8bae0a0c JSC |
62 | |
63 | #include "getopt.h" | |
64 | #include "libiberty.h" | |
9d52bcb7 | 65 | #include "bfd.h" |
8bae0a0c | 66 | #include "callback.h" /* GDB simulator callback interface */ |
e3d12c65 | 67 | #include "remote-sim.h" /* GDB simulator interface */ |
8bae0a0c JSC |
68 | |
69 | #include "support.h" /* internal support manifests */ | |
70 | ||
f24b7b69 JSC |
71 | #include "sysdep.h" |
72 | ||
53b9417e DE |
73 | #ifndef PARAMS |
74 | #define PARAMS(x) | |
75 | #endif | |
76 | ||
77 | char* pr_addr PARAMS ((SIM_ADDR addr)); | |
87e43259 | 78 | char* pr_uword64 PARAMS ((uword64 addr)); |
53b9417e | 79 | |
f24b7b69 JSC |
80 | #ifndef SIGBUS |
81 | #define SIGBUS SIGSEGV | |
82 | #endif | |
83 | ||
8bae0a0c JSC |
84 | /* Get the simulator engine description, without including the code: */ |
85 | #define SIM_MANIFESTS | |
86 | #include "engine.c" | |
87 | #undef SIM_MANIFESTS | |
88 | ||
9d52bcb7 DE |
89 | static SIM_OPEN_KIND sim_kind; |
90 | static char *myname; | |
91 | static int big_endian_p; | |
f7481d45 | 92 | |
8bae0a0c JSC |
93 | /* The following reserved instruction value is used when a simulator |
94 | trap is required. NOTE: Care must be taken, since this value may be | |
95 | used in later revisions of the MIPS ISA. */ | |
53b9417e DE |
96 | #define RSVD_INSTRUCTION (0x00000005) |
97 | #define RSVD_INSTRUCTION_MASK (0xFC00003F) | |
98 | ||
99 | #define RSVD_INSTRUCTION_ARG_SHIFT 6 | |
100 | #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF | |
101 | ||
8bae0a0c JSC |
102 | |
103 | /* NOTE: These numbers depend on the processor architecture being | |
104 | simulated: */ | |
105 | #define Interrupt (0) | |
106 | #define TLBModification (1) | |
107 | #define TLBLoad (2) | |
108 | #define TLBStore (3) | |
109 | #define AddressLoad (4) | |
110 | #define AddressStore (5) | |
111 | #define InstructionFetch (6) | |
112 | #define DataReference (7) | |
113 | #define SystemCall (8) | |
114 | #define BreakPoint (9) | |
115 | #define ReservedInstruction (10) | |
116 | #define CoProcessorUnusable (11) | |
117 | #define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */ | |
118 | #define Trap (13) | |
119 | #define FPE (15) | |
120 | #define Watch (23) | |
121 | ||
122 | /* The following exception code is actually private to the simulator | |
123 | world. It is *NOT* a processor feature, and is used to signal | |
124 | run-time errors in the simulator. */ | |
125 | #define SimulatorFault (0xFFFFFFFF) | |
126 | ||
127 | /* The following are generic to all versions of the MIPS architecture | |
128 | to date: */ | |
129 | /* Memory Access Types (for CCA): */ | |
130 | #define Uncached (0) | |
131 | #define CachedNoncoherent (1) | |
132 | #define CachedCoherent (2) | |
133 | #define Cached (3) | |
134 | ||
135 | #define isINSTRUCTION (1 == 0) /* FALSE */ | |
136 | #define isDATA (1 == 1) /* TRUE */ | |
137 | ||
138 | #define isLOAD (1 == 0) /* FALSE */ | |
139 | #define isSTORE (1 == 1) /* TRUE */ | |
140 | ||
141 | #define isREAL (1 == 0) /* FALSE */ | |
142 | #define isRAW (1 == 1) /* TRUE */ | |
143 | ||
144 | #define isTARGET (1 == 0) /* FALSE */ | |
145 | #define isHOST (1 == 1) /* TRUE */ | |
146 | ||
147 | /* The "AccessLength" specifications for Loads and Stores. NOTE: This | |
148 | is the number of bytes minus 1. */ | |
149 | #define AccessLength_BYTE (0) | |
150 | #define AccessLength_HALFWORD (1) | |
151 | #define AccessLength_TRIPLEBYTE (2) | |
152 | #define AccessLength_WORD (3) | |
153 | #define AccessLength_QUINTIBYTE (4) | |
154 | #define AccessLength_SEXTIBYTE (5) | |
155 | #define AccessLength_SEPTIBYTE (6) | |
156 | #define AccessLength_DOUBLEWORD (7) | |
53b9417e | 157 | #define AccessLength_QUADWORD (15) |
8bae0a0c JSC |
158 | |
159 | #if defined(HASFPU) | |
160 | /* FPU registers must be one of the following types. All other values | |
161 | are reserved (and undefined). */ | |
162 | typedef enum { | |
163 | fmt_single = 0, | |
164 | fmt_double = 1, | |
165 | fmt_word = 4, | |
166 | fmt_long = 5, | |
167 | /* The following are well outside the normal acceptable format | |
168 | range, and are used in the register status vector. */ | |
169 | fmt_unknown = 0x10000000, | |
170 | fmt_uninterpreted = 0x20000000, | |
171 | } FP_formats; | |
172 | #endif /* HASFPU */ | |
173 | ||
174 | /* NOTE: We cannot avoid globals, since the GDB "sim_" interface does | |
175 | not allow a private variable to be passed around. This means that | |
176 | simulators under GDB can only be single-threaded. However, it would | |
177 | be possible for the simulators to be multi-threaded if GDB allowed | |
178 | for a private pointer to be maintained. i.e. a general "void **ptr" | |
179 | variable that GDB passed around in the argument list to all of | |
180 | sim_xxx() routines. It could be initialised to NULL by GDB, and | |
181 | then updated by sim_open() and used by the other sim_xxx() support | |
182 | functions. This would allow new features in the simulator world, | |
183 | like storing a context - continuing execution to gather a result, | |
184 | and then going back to the point where the context was saved and | |
185 | changing some state before continuing. i.e. the ability to perform | |
186 | UNDOs on simulations. It would also allow the simulation of | |
187 | shared-memory multi-processor systems. */ | |
188 | ||
189 | static host_callback *callback = NULL; /* handle onto the current callback structure */ | |
190 | ||
8bae0a0c JSC |
191 | /* This is nasty, since we have to rely on matching the register |
192 | numbers used by GDB. Unfortunately, depending on the MIPS target | |
193 | GDB uses different register numbers. We cannot just include the | |
194 | relevant "gdb/tm.h" link, since GDB may not be configured before | |
195 | the sim world, and also the GDB header file requires too much other | |
196 | state. */ | |
197 | /* TODO: Sort out a scheme for *KNOWING* the mapping between real | |
198 | registers, and the numbers that GDB uses. At the moment due to the | |
199 | order that the tools are built, we cannot rely on a configured GDB | |
200 | world whilst constructing the simulator. This means we have to | |
201 | assume the GDB register number mapping. */ | |
e3d12c65 | 202 | #ifndef TM_MIPS_H |
8bae0a0c | 203 | #define LAST_EMBED_REGNUM (89) |
e3d12c65 | 204 | #endif |
8bae0a0c JSC |
205 | |
206 | /* To keep this default simulator simple, and fast, we use a direct | |
207 | vector of registers. The internal simulator engine then uses | |
208 | manifests to access the correct slot. */ | |
4fa134be ILT |
209 | static ut_reg registers[LAST_EMBED_REGNUM + 1]; |
210 | static int register_widths[LAST_EMBED_REGNUM + 1]; | |
8bae0a0c JSC |
211 | |
212 | #define GPR (®isters[0]) | |
213 | #if defined(HASFPU) | |
214 | #define FGRIDX (38) | |
215 | #define FGR (®isters[FGRIDX]) | |
216 | #endif /* HASFPU */ | |
217 | #define LO (registers[33]) | |
218 | #define HI (registers[34]) | |
219 | #define PC (registers[37]) | |
220 | #define CAUSE (registers[36]) | |
221 | #define SRIDX (32) | |
222 | #define SR (registers[SRIDX]) /* CPU status register */ | |
223 | #define FCR0IDX (71) | |
224 | #define FCR0 (registers[FCR0IDX]) /* really a 32bit register */ | |
225 | #define FCR31IDX (70) | |
226 | #define FCR31 (registers[FCR31IDX]) /* really a 32bit register */ | |
227 | #define FCSR (FCR31) | |
228 | #define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */ | |
229 | ||
230 | /* The following are pseudonyms for standard registers */ | |
231 | #define ZERO (registers[0]) | |
232 | #define V0 (registers[2]) | |
233 | #define A0 (registers[4]) | |
234 | #define A1 (registers[5]) | |
235 | #define A2 (registers[6]) | |
236 | #define A3 (registers[7]) | |
237 | #define SP (registers[29]) | |
238 | #define RA (registers[31]) | |
239 | ||
53b9417e DE |
240 | |
241 | /* start-sanitize-r5900 */ | |
242 | /* | |
243 | The R5900 has 128 bit registers, but the hi 64 bits are only touched by | |
244 | multimedia (MMI) instructions. The normal mips instructions just use the | |
245 | lower 64 bits. To avoid changing the older parts of the simulator to | |
246 | handle this weirdness, the high 64 bits of each register are kept in | |
247 | a separate array (registers1). The high 64 bits of any register are by | |
248 | convention refered by adding a '1' to the end of the normal register's | |
249 | name. So LO still refers to the low 64 bits of the LO register, LO1 | |
250 | refers to the high 64 bits of that same register. | |
251 | */ | |
252 | ||
253 | /* The high part of each register */ | |
254 | static ut_reg registers1[LAST_EMBED_REGNUM + 1]; | |
255 | ||
256 | #define GPR1 (®isters1[0]) | |
257 | ||
258 | #define LO1 (registers1[33]) | |
259 | #define HI1 (registers1[34]) | |
260 | ||
261 | #define BYTES_IN_MMI_REGS (sizeof(registers[0])+sizeof(registers1[0])) | |
262 | #define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2) | |
263 | #define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4) | |
264 | #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8) | |
265 | ||
266 | #define BYTES_IN_MIPS_REGS (sizeof(registers[0])) | |
267 | #define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2) | |
268 | #define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4) | |
269 | #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8) | |
270 | ||
271 | ||
272 | /* | |
273 | SUB_REG_FETCH - return as lvalue some sub-part of a "register" | |
274 | T - type of the sub part | |
275 | TC - # of T's in the mips part of the "register" | |
276 | I - index (from 0) of desired sub part | |
277 | A - low part of "register" | |
278 | A1 - high part of register | |
279 | */ | |
280 | #define SUB_REG_FETCH(T,TC,A,A1,I) (*(((T*)(((I) < (TC)) ? (A) : (A1))) + ((I) % (TC)))) | |
281 | ||
282 | /* | |
283 | GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R | |
284 | where <type> has two letters: | |
285 | 1 is S=signed or U=unsigned | |
286 | 2 is B=byte H=halfword W=word D=doubleword | |
287 | */ | |
288 | ||
289 | #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed char, BYTES_IN_MIPS_REGS, A, A1, I) | |
290 | #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed short, HALFWORDS_IN_MIPS_REGS, A, A1, I) | |
291 | #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed int, WORDS_IN_MIPS_REGS, A, A1, I) | |
292 | #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed long long, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I) | |
293 | ||
294 | #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned char, BYTES_IN_MIPS_REGS, A, A1, I) | |
295 | #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned short, HALFWORDS_IN_MIPS_REGS, A, A1, I) | |
296 | #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned int, WORDS_IN_MIPS_REGS, A, A1, I) | |
297 | #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned long long,DOUBLEWORDS_IN_MIPS_REGS, A, A1, I) | |
298 | ||
299 | ||
300 | ||
301 | #define GPR_SB(R,I) SUB_REG_SB(®isters[R], ®isters1[R], I) | |
302 | #define GPR_SH(R,I) SUB_REG_SH(®isters[R], ®isters1[R], I) | |
303 | #define GPR_SW(R,I) SUB_REG_SW(®isters[R], ®isters1[R], I) | |
304 | #define GPR_SD(R,I) SUB_REG_SD(®isters[R], ®isters1[R], I) | |
305 | ||
306 | #define GPR_UB(R,I) SUB_REG_UB(®isters[R], ®isters1[R], I) | |
307 | #define GPR_UH(R,I) SUB_REG_UH(®isters[R], ®isters1[R], I) | |
308 | #define GPR_UW(R,I) SUB_REG_UW(®isters[R], ®isters1[R], I) | |
309 | #define GPR_UD(R,I) SUB_REG_UD(®isters[R], ®isters1[R], I) | |
310 | ||
311 | ||
312 | #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I) | |
313 | #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I) | |
314 | #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I) | |
315 | #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I) | |
316 | ||
317 | #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I) | |
318 | #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I) | |
319 | #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I) | |
320 | #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I) | |
321 | ||
322 | #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I) | |
323 | #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I) | |
324 | #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I) | |
325 | #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I) | |
326 | ||
327 | #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I) | |
328 | #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I) | |
329 | #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I) | |
330 | #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I) | |
331 | ||
332 | ||
333 | ||
334 | #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I) | |
335 | #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I) | |
336 | #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I) | |
337 | #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I) | |
338 | ||
339 | #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I) | |
340 | #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I) | |
341 | #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I) | |
342 | #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I) | |
343 | ||
344 | #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I) | |
345 | #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I) | |
346 | #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I) | |
347 | #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I) | |
348 | ||
349 | #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I) | |
350 | #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I) | |
351 | #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I) | |
352 | #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I) | |
353 | /* end-sanitize-r5900 */ | |
354 | ||
355 | ||
356 | /* start-sanitize-r5900 */ | |
357 | static ut_reg SA; /* the shift amount register */ | |
358 | /* end-sanitize-r5900 */ | |
359 | ||
4fa134be | 360 | static ut_reg EPC = 0; /* Exception PC */ |
8bae0a0c JSC |
361 | |
362 | #if defined(HASFPU) | |
363 | /* Keep the current format state for each register: */ | |
4fa134be | 364 | static FP_formats fpr_state[32]; |
8bae0a0c JSC |
365 | #endif /* HASFPU */ |
366 | ||
8bae0a0c | 367 | /* The following are internal simulator state variables: */ |
4fa134be ILT |
368 | static ut_reg IPC = 0; /* internal Instruction PC */ |
369 | static ut_reg DSPC = 0; /* delay-slot PC */ | |
8bae0a0c JSC |
370 | |
371 | ||
372 | /* TODO : these should be the bitmasks for these bits within the | |
373 | status register. At the moment the following are VR4300 | |
374 | bit-positions: */ | |
375 | #define status_KSU_mask (0x3) /* mask for KSU bits */ | |
376 | #define status_KSU_shift (3) /* shift for field */ | |
377 | #define ksu_kernel (0x0) | |
378 | #define ksu_supervisor (0x1) | |
379 | #define ksu_user (0x2) | |
380 | #define ksu_unknown (0x3) | |
381 | ||
382 | #define status_RE (1 << 25) /* Reverse Endian in user mode */ | |
383 | #define status_FR (1 << 26) /* enables MIPS III additional FP registers */ | |
384 | #define status_SR (1 << 20) /* soft reset or NMI */ | |
385 | #define status_BEV (1 << 22) /* Location of general exception vectors */ | |
386 | #define status_TS (1 << 21) /* TLB shutdown has occurred */ | |
387 | #define status_ERL (1 << 2) /* Error level */ | |
388 | #define status_RP (1 << 27) /* Reduced Power mode */ | |
389 | ||
8bae0a0c JSC |
390 | #define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */ |
391 | ||
392 | #if defined(HASFPU) | |
393 | /* Macro to update FPSR condition-code field. This is complicated by | |
394 | the fact that there is a hole in the index range of the bits within | |
395 | the FCSR register. Also, the number of bits visible depends on the | |
396 | MIPS ISA version being supported. */ | |
397 | #define SETFCC(cc,v) {\ | |
398 | int bit = ((cc == 0) ? 23 : (24 + (cc)));\ | |
399 | FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\ | |
400 | } | |
401 | #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0) | |
402 | ||
403 | /* This should be the COC1 value at the start of the preceding | |
404 | instruction: */ | |
405 | #define PREVCOC1() ((state & simPCOC1) ? 1 : 0) | |
406 | #endif /* HASFPU */ | |
407 | ||
408 | /* Standard FCRS bits: */ | |
409 | #define IR (0) /* Inexact Result */ | |
410 | #define UF (1) /* UnderFlow */ | |
411 | #define OF (2) /* OverFlow */ | |
412 | #define DZ (3) /* Division by Zero */ | |
413 | #define IO (4) /* Invalid Operation */ | |
414 | #define UO (5) /* Unimplemented Operation */ | |
415 | ||
416 | /* Get masks for individual flags: */ | |
417 | #if 1 /* SAFE version */ | |
418 | #define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0) | |
419 | #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0) | |
420 | #define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0) | |
421 | #else | |
422 | #define FP_FLAGS(b) (1 << ((b) + 2)) | |
423 | #define FP_ENABLE(b) (1 << ((b) + 7)) | |
424 | #define FP_CAUSE(b) (1 << ((b) + 12)) | |
425 | #endif | |
426 | ||
427 | #define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */ | |
428 | ||
429 | #define FP_MASK_RM (0x3) | |
430 | #define FP_SH_RM (0) | |
431 | #define FP_RM_NEAREST (0) /* Round to nearest (Round) */ | |
432 | #define FP_RM_TOZERO (1) /* Round to zero (Trunc) */ | |
433 | #define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */ | |
434 | #define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */ | |
435 | #define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM) | |
436 | ||
437 | /* Slots for delayed register updates. For the moment we just have a | |
438 | fixed number of slots (rather than a more generic, dynamic | |
439 | system). This keeps the simulator fast. However, we only allow for | |
440 | the register update to be delayed for a single instruction | |
441 | cycle. */ | |
442 | #define PSLOTS (5) /* Maximum number of instruction cycles */ | |
4fa134be ILT |
443 | static int pending_in; |
444 | static int pending_out; | |
445 | static int pending_total; | |
446 | static int pending_slot_count[PSLOTS]; | |
447 | static int pending_slot_reg[PSLOTS]; | |
448 | static ut_reg pending_slot_value[PSLOTS]; | |
8bae0a0c | 449 | |
e3d12c65 DE |
450 | /*---------------------------------------------------------------------------*/ |
451 | /*-- GDB simulator interface ------------------------------------------------*/ | |
452 | /*---------------------------------------------------------------------------*/ | |
453 | ||
454 | static void dotrace PARAMS((FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...)); | |
455 | static void sim_warning PARAMS((char *fmt,...)); | |
456 | extern void sim_error PARAMS((char *fmt,...)); | |
aaff8437 | 457 | static void set_endianness PARAMS((void)); |
e3d12c65 DE |
458 | static void ColdReset PARAMS((void)); |
459 | static int AddressTranslation PARAMS((uword64 vAddr,int IorD,int LorS,uword64 *pAddr,int *CCA,int host,int raw)); | |
53b9417e DE |
460 | static void StoreMemory PARAMS((int CCA,int AccessLength,uword64 MemElem,uword64 MemElem1,uword64 pAddr,uword64 vAddr,int raw)); |
461 | static void LoadMemory PARAMS((uword64*memvalp,uword64*memval1p,int CCA,int AccessLength,uword64 pAddr,uword64 vAddr,int IorD,int raw)); | |
e3d12c65 DE |
462 | static void SignalException PARAMS((int exception,...)); |
463 | static void simulate PARAMS((void)); | |
464 | static long getnum PARAMS((char *value)); | |
e3d12c65 DE |
465 | extern void sim_set_profile PARAMS((int frequency)); |
466 | static unsigned int power2 PARAMS((unsigned int value)); | |
467 | ||
468 | /*---------------------------------------------------------------------------*/ | |
469 | ||
8bae0a0c JSC |
470 | /* The following are not used for MIPS IV onwards: */ |
471 | #define PENDING_FILL(r,v) {\ | |
f24b7b69 | 472 | /* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total); */\ |
8bae0a0c | 473 | if (pending_slot_reg[pending_in] != (LAST_EMBED_REGNUM + 1))\ |
f24b7b69 | 474 | sim_warning("Attempt to over-write pending value");\ |
8bae0a0c JSC |
475 | pending_slot_count[pending_in] = 2;\ |
476 | pending_slot_reg[pending_in] = (r);\ | |
e871dd18 | 477 | pending_slot_value[pending_in] = (uword64)(v);\ |
53b9417e | 478 | /*printf("DBG: FILL reg %d value = 0x%s\n",(r),pr_addr(v));*/\ |
8bae0a0c JSC |
479 | pending_total++;\ |
480 | pending_in++;\ | |
481 | if (pending_in == PSLOTS)\ | |
482 | pending_in = 0;\ | |
f24b7b69 | 483 | /*printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);*/\ |
8bae0a0c JSC |
484 | } |
485 | ||
4fa134be | 486 | static int LLBIT = 0; |
8bae0a0c JSC |
487 | /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic |
488 | read-write instructions. It is set when a linked load occurs. It is | |
489 | tested and cleared by the conditional store. It is cleared (during | |
490 | other CPU operations) when a store to the location would no longer | |
491 | be atomic. In particular, it is cleared by exception return | |
492 | instructions. */ | |
493 | ||
4fa134be ILT |
494 | static int HIACCESS = 0; |
495 | static int LOACCESS = 0; | |
53b9417e DE |
496 | static int HI1ACCESS = 0; |
497 | static int LO1ACCESS = 0; | |
8bae0a0c JSC |
498 | /* The HIACCESS and LOACCESS counts are used to ensure that |
499 | corruptions caused by using the HI or LO register to close to a | |
500 | following operation are spotted. */ | |
f24b7b69 | 501 | static ut_reg HLPC = 0; |
8bae0a0c | 502 | |
6429b296 JW |
503 | /* ??? The 4300 and a few other processors have interlocks on hi/lo register |
504 | reads, and hence do not have this problem. To avoid spurious warnings, | |
505 | we just disable this always. */ | |
506 | #if 1 | |
507 | #define CHECKHILO(s) | |
508 | #else | |
8bae0a0c JSC |
509 | /* If either of the preceding two instructions have accessed the HI or |
510 | LO registers, then the values they see should be | |
511 | undefined. However, to keep the simulator world simple, we just let | |
512 | them use the value read and raise a warning to notify the user: */ | |
513 | #define CHECKHILO(s) {\ | |
53b9417e DE |
514 | if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\ |
515 | sim_warning("%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\ | |
8bae0a0c | 516 | } |
6429b296 | 517 | #endif |
8bae0a0c JSC |
518 | |
519 | /* NOTE: We keep the following status flags as bit values (1 for true, | |
520 | 0 for false). This allows them to be used in binary boolean | |
521 | operations without worrying about what exactly the non-zero true | |
522 | value is. */ | |
523 | ||
524 | /* UserMode */ | |
525 | #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0) | |
526 | ||
0049ba7a MA |
527 | /* BigEndianMem */ |
528 | /* Hardware configuration. Affects endianness of LoadMemory and | |
529 | StoreMemory and the endianness of Kernel and Supervisor mode | |
530 | execution. The value is 0 for little-endian; 1 for big-endian. */ | |
531 | #define BigEndianMem ((state & simBE) ? 1 : 0) | |
532 | ||
aaff8437 ILT |
533 | /* ByteSwapMem */ |
534 | /* This is true if the host and target have different endianness. */ | |
535 | #define ByteSwapMem (!(state & simHOSTBE) != !(state & simBE)) | |
8bae0a0c JSC |
536 | |
537 | /* ReverseEndian */ | |
538 | /* This mode is selected if in User mode with the RE bit being set in | |
539 | SR (Status Register). It reverses the endianness of load and store | |
540 | instructions. */ | |
541 | #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0) | |
542 | ||
543 | /* BigEndianCPU */ | |
544 | /* The endianness for load and store instructions (0=little;1=big). In | |
545 | User mode this endianness may be switched by setting the state_RE | |
546 | bit in the SR register. Thus, BigEndianCPU may be computed as | |
0049ba7a MA |
547 | (BigEndianMem EOR ReverseEndian). */ |
548 | #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */ | |
8bae0a0c JSC |
549 | |
550 | #if !defined(FASTSIM) || defined(PROFILE) | |
551 | /* At the moment these values will be the same, since we do not have | |
552 | access to the pipeline cycle count information from the simulator | |
553 | engine. */ | |
4fa134be ILT |
554 | static unsigned int instruction_fetches = 0; |
555 | static unsigned int instruction_fetch_overflow = 0; | |
556 | static unsigned int pipeline_ticks = 0; | |
8bae0a0c JSC |
557 | #endif |
558 | ||
559 | /* Flags in the "state" variable: */ | |
560 | #define simSTOP (1 << 0) /* 0 = execute; 1 = stop simulation */ | |
561 | #define simSTEP (1 << 1) /* 0 = run; 1 = single-step */ | |
562 | #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */ | |
563 | #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */ | |
564 | #define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */ | |
565 | #define simPROFILE (1 << 9) /* 0 = do nothing; 1 = gather profiling samples */ | |
566 | #define simHOSTBE (1 << 10) /* 0 = little-endian; 1 = big-endian (host endianness) */ | |
567 | /* Whilst simSTOP is not set, the simulator control loop should just | |
568 | keep simulating instructions. The simSTEP flag is used to force | |
569 | single-step execution. */ | |
570 | #define simBE (1 << 16) /* 0 = little-endian; 1 = big-endian (target endianness) */ | |
571 | #define simPCOC0 (1 << 17) /* COC[1] from current */ | |
572 | #define simPCOC1 (1 << 18) /* COC[1] from previous */ | |
573 | #define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */ | |
574 | #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */ | |
575 | #define simEXCEPTION (1 << 26) /* 0 = no exception; 1 = exception has occurred */ | |
576 | #define simEXIT (1 << 27) /* 0 = do nothing; 1 = run-time exit() processing */ | |
6429b296 | 577 | #define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */ |
aaff8437 | 578 | #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */ |
8bae0a0c | 579 | |
4fa134be ILT |
580 | static unsigned int state = 0; |
581 | static unsigned int rcexit = 0; /* _exit() reason code holder */ | |
8bae0a0c JSC |
582 | |
583 | #define DELAYSLOT() {\ | |
f24b7b69 JSC |
584 | if (state & simDELAYSLOT)\ |
585 | sim_warning("Delay slot already activated (branch in delay slot?)");\ | |
8bae0a0c JSC |
586 | state |= simDELAYSLOT;\ |
587 | } | |
588 | ||
aaff8437 ILT |
589 | #define JALDELAYSLOT() {\ |
590 | DELAYSLOT ();\ | |
591 | state |= simJALDELAYSLOT;\ | |
592 | } | |
593 | ||
8bae0a0c JSC |
594 | #define NULLIFY() {\ |
595 | state &= ~simDELAYSLOT;\ | |
596 | state |= simSKIPNEXT;\ | |
597 | } | |
598 | ||
aaff8437 ILT |
599 | #define INDELAYSLOT() ((state & simDELAYSLOT) != 0) |
600 | #define INJALDELAYSLOT() ((state & simJALDELAYSLOT) != 0) | |
601 | ||
a9f7253f JSC |
602 | #define K0BASE (0x80000000) |
603 | #define K0SIZE (0x20000000) | |
604 | #define K1BASE (0xA0000000) | |
605 | #define K1SIZE (0x20000000) | |
606 | ||
8bae0a0c | 607 | /* Very simple memory model to start with: */ |
4fa134be ILT |
608 | static unsigned char *membank = NULL; |
609 | static ut_reg membank_base = K1BASE; | |
6429b296 JW |
610 | /* The ddb.ld linker script loads text at K1BASE+1MB, and the idt.ld linker |
611 | script loads text at K1BASE+128KB. We allocate 2MB, so that we have a | |
612 | minimum of 1 MB available for the user process. We must have memory | |
613 | above _end in order for sbrk to work. */ | |
614 | static unsigned membank_size = (2 << 20); | |
8bae0a0c JSC |
615 | |
616 | /* Simple run-time monitor support */ | |
4fa134be ILT |
617 | static unsigned char *monitor = NULL; |
618 | static ut_reg monitor_base = 0xBFC00000; | |
619 | static unsigned monitor_size = (1 << 11); /* power-of-2 */ | |
8bae0a0c | 620 | |
f24b7b69 JSC |
621 | static char *logfile = NULL; /* logging disabled by default */ |
622 | static FILE *logfh = NULL; | |
623 | ||
8bae0a0c | 624 | #if defined(TRACE) |
4fa134be ILT |
625 | static char *tracefile = "trace.din"; /* default filename for trace log */ |
626 | static FILE *tracefh = NULL; | |
6429b296 | 627 | static void open_trace PARAMS((void)); |
8bae0a0c JSC |
628 | #endif /* TRACE */ |
629 | ||
630 | #if defined(PROFILE) | |
4fa134be ILT |
631 | static unsigned profile_frequency = 256; |
632 | static unsigned profile_nsamples = (128 << 10); | |
633 | static unsigned short *profile_hist = NULL; | |
634 | static ut_reg profile_minpc; | |
635 | static ut_reg profile_maxpc; | |
636 | static int profile_shift = 0; /* address shift amount */ | |
8bae0a0c JSC |
637 | #endif /* PROFILE */ |
638 | ||
f7481d45 JSC |
639 | /* The following are used to provide shortcuts to the required version |
640 | of host<->target copying. This avoids run-time conditionals, which | |
641 | would slow the simulator throughput. */ | |
642 | typedef unsigned int (*fnptr_read_word) PARAMS((unsigned char *memory)); | |
643 | typedef unsigned int (*fnptr_swap_word) PARAMS((unsigned int data)); | |
644 | typedef uword64 (*fnptr_read_long) PARAMS((unsigned char *memory)); | |
645 | typedef uword64 (*fnptr_swap_long) PARAMS((uword64 data)); | |
646 | ||
4fa134be ILT |
647 | static fnptr_read_word host_read_word; |
648 | static fnptr_read_long host_read_long; | |
649 | static fnptr_swap_word host_swap_word; | |
650 | static fnptr_swap_long host_swap_long; | |
f7481d45 | 651 | |
8bae0a0c JSC |
652 | /*---------------------------------------------------------------------------*/ |
653 | /*-- GDB simulator interface ------------------------------------------------*/ | |
654 | /*---------------------------------------------------------------------------*/ | |
655 | ||
53b9417e | 656 | SIM_DESC |
87e43259 AC |
657 | sim_open (kind,argv) |
658 | SIM_OPEN_KIND kind; | |
53b9417e | 659 | char **argv; |
8bae0a0c JSC |
660 | { |
661 | if (callback == NULL) { | |
662 | fprintf(stderr,"SIM Error: sim_open() called without callbacks attached\n"); | |
53b9417e | 663 | return 0; |
8bae0a0c JSC |
664 | } |
665 | ||
666 | /* The following ensures that the standard file handles for stdin, | |
667 | stdout and stderr are initialised: */ | |
668 | callback->init(callback); | |
669 | ||
9d52bcb7 DE |
670 | sim_kind = kind; |
671 | myname = argv[0]; | |
672 | ||
8bae0a0c JSC |
673 | state = 0; |
674 | CHECKSIM(); | |
675 | if (state & simEXCEPTION) { | |
676 | fprintf(stderr,"This simulator is not suitable for this host configuration\n"); | |
677 | exit(1); | |
678 | } | |
679 | ||
680 | { | |
681 | int data = 0x12; | |
682 | if (*((char *)&data) != 0x12) | |
683 | state |= simHOSTBE; /* big-endian host */ | |
684 | } | |
685 | ||
686 | #if defined(HASFPU) | |
687 | /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE | |
688 | and DOUBLE binary formats. This is a bit nasty, requiring that we | |
689 | trust the explicit manifests held in the source: */ | |
690 | { | |
691 | unsigned int s[2]; | |
a9f7253f JSC |
692 | s[state & simHOSTBE ? 0 : 1] = 0x40805A5A; |
693 | s[state & simHOSTBE ? 1 : 0] = 0x00000000; | |
694 | ||
695 | /* TODO: We need to cope with the simulated target and the host | |
696 | not having the same endianness. This will require the high and | |
697 | low words of a (double) to be swapped when converting between | |
698 | the host and the simulated target. */ | |
699 | ||
700 | if (((float)4.01102924346923828125 != *(float *)(s + ((state & simHOSTBE) ? 0 : 1))) || ((double)523.2939453125 != *(double *)s)) { | |
8bae0a0c | 701 | fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n"); |
a9f7253f JSC |
702 | fprintf(stderr,"*(float *)s = %.20f (4.01102924346923828125)\n",*(float *)s); |
703 | fprintf(stderr,"*(double *)s = %.20f (523.2939453125)\n",*(double *)s); | |
8bae0a0c JSC |
704 | exit(1); |
705 | } | |
706 | } | |
707 | #endif /* HASFPU */ | |
708 | ||
709 | /* This is NASTY, in that we are assuming the size of specific | |
710 | registers: */ | |
711 | { | |
712 | int rn; | |
713 | for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) { | |
714 | if (rn < 32) | |
715 | register_widths[rn] = GPRLEN; | |
716 | else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32))) | |
717 | register_widths[rn] = GPRLEN; | |
718 | else if ((rn >= 33) && (rn <= 37)) | |
719 | register_widths[rn] = GPRLEN; | |
720 | else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89))) | |
721 | register_widths[rn] = 32; | |
722 | else | |
723 | register_widths[rn] = 0; | |
724 | } | |
725 | } | |
726 | ||
727 | /* It would be good if we could select particular named MIPS | |
728 | architecture simulators. However, having a pre-built, fixed | |
729 | engine would mean including multiple engines. If the simulator is | |
730 | changed to a run-time conditional version, then the ability to | |
731 | select a particular architecture would be straightforward. */ | |
53b9417e | 732 | { |
8bae0a0c JSC |
733 | int c; |
734 | char *cline; | |
8bae0a0c JSC |
735 | int argc; |
736 | static struct option cmdline[] = { | |
737 | {"help", 0,0,'h'}, | |
f24b7b69 | 738 | {"log", 1,0,'l'}, |
8bae0a0c JSC |
739 | {"name", 1,0,'n'}, |
740 | {"profile", 0,0,'p'}, | |
741 | {"size", 1,0,'s'}, | |
742 | {"trace", 0,0,'t'}, | |
743 | {"tracefile",1,0,'z'}, | |
744 | {"frequency",1,0,'y'}, | |
745 | {"samples", 1,0,'x'}, | |
746 | {0, 0,0,0} | |
747 | }; | |
748 | ||
8bae0a0c JSC |
749 | for (argc = 0; argv[argc]; argc++); |
750 | ||
87e43259 AC |
751 | /* Ensure getopt is reset [don't know whether caller used it]. */ |
752 | optind = 0; | |
753 | ||
8bae0a0c JSC |
754 | while (1) { |
755 | int option_index = 0; | |
756 | ||
9d52bcb7 | 757 | c = getopt_long(argc,argv,"E:hn:s:tp",cmdline,&option_index); |
8bae0a0c JSC |
758 | if (c == -1) |
759 | break; | |
760 | ||
761 | switch (c) { | |
9d52bcb7 DE |
762 | case 'E' : |
763 | big_endian_p = strcmp (optarg, "big") == 0; | |
764 | break; | |
765 | ||
8bae0a0c JSC |
766 | case 'h': |
767 | callback->printf_filtered(callback,"Usage:\n\t\ | |
f24b7b69 | 768 | target sim [-h] [--log=<file>] [--name=<model>] [--size=<amount>]"); |
8bae0a0c JSC |
769 | #if defined(TRACE) |
770 | callback->printf_filtered(callback," [-t [--tracefile=<name>]]"); | |
771 | #endif /* TRACE */ | |
772 | #if defined(PROFILE) | |
773 | callback->printf_filtered(callback," [-p [--frequency=<count>] [--samples=<count>]]"); | |
774 | #endif /* PROFILE */ | |
775 | callback->printf_filtered(callback,"\n"); | |
776 | break; | |
777 | ||
f24b7b69 JSC |
778 | case 'l': |
779 | if (optarg != NULL) { | |
780 | char *tmp; | |
781 | tmp = (char *)malloc(strlen(optarg) + 1); | |
782 | if (tmp == NULL) | |
783 | callback->printf_filtered(callback,"Failed to allocate buffer for logfile name \"%s\"\n",optarg); | |
784 | else { | |
785 | strcpy(tmp,optarg); | |
786 | logfile = tmp; | |
787 | } | |
788 | } | |
789 | break; | |
790 | ||
8bae0a0c JSC |
791 | case 'n': |
792 | callback->printf_filtered(callback,"Explicit model selection not yet available (Ignoring \"%s\")\n",optarg); | |
793 | break; | |
794 | ||
795 | case 's': | |
796 | membank_size = (unsigned)getnum(optarg); | |
797 | break; | |
798 | ||
799 | case 't': | |
800 | #if defined(TRACE) | |
801 | /* Eventually the simTRACE flag could be treated as a toggle, to | |
802 | allow external control of the program points being traced | |
803 | (i.e. only from main onwards, excluding the run-time setup, | |
804 | etc.). */ | |
805 | state |= simTRACE; | |
806 | #else /* !TRACE */ | |
807 | fprintf(stderr,"\ | |
808 | Simulator constructed without tracing support (for performance).\n\ | |
809 | Re-compile simulator with \"-DTRACE\" to enable this option.\n"); | |
810 | #endif /* !TRACE */ | |
811 | break; | |
812 | ||
813 | case 'z': | |
814 | #if defined(TRACE) | |
815 | if (optarg != NULL) { | |
816 | char *tmp; | |
817 | tmp = (char *)malloc(strlen(optarg) + 1); | |
818 | if (tmp == NULL) | |
819 | callback->printf_filtered(callback,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg); | |
820 | else { | |
821 | strcpy(tmp,optarg); | |
822 | tracefile = tmp; | |
823 | callback->printf_filtered(callback,"Placing trace information into file \"%s\"\n",tracefile); | |
824 | } | |
825 | } | |
826 | #endif /* TRACE */ | |
827 | break; | |
828 | ||
829 | case 'p': | |
830 | #if defined(PROFILE) | |
831 | state |= simPROFILE; | |
832 | #else /* !PROFILE */ | |
833 | fprintf(stderr,"\ | |
834 | Simulator constructed without profiling support (for performance).\n\ | |
835 | Re-compile simulator with \"-DPROFILE\" to enable this option.\n"); | |
836 | #endif /* !PROFILE */ | |
837 | break; | |
838 | ||
839 | case 'x': | |
840 | #if defined(PROFILE) | |
841 | profile_nsamples = (unsigned)getnum(optarg); | |
842 | #endif /* PROFILE */ | |
843 | break; | |
844 | ||
845 | case 'y': | |
846 | #if defined(PROFILE) | |
847 | sim_set_profile((int)getnum(optarg)); | |
848 | #endif /* PROFILE */ | |
849 | break; | |
850 | ||
851 | default: | |
852 | callback->printf_filtered(callback,"Warning: Simulator getopt returned unrecognised code 0x%08X\n",c); | |
853 | case '?': | |
854 | break; | |
855 | } | |
856 | } | |
857 | ||
f24b7b69 | 858 | #if 0 |
8bae0a0c JSC |
859 | if (optind < argc) { |
860 | callback->printf_filtered(callback,"Warning: Ignoring spurious non-option arguments "); | |
861 | while (optind < argc) | |
862 | callback->printf_filtered(callback,"\"%s\" ",argv[optind++]); | |
863 | callback->printf_filtered(callback,"\n"); | |
864 | } | |
f24b7b69 | 865 | #endif |
8bae0a0c JSC |
866 | } |
867 | ||
f24b7b69 JSC |
868 | if (logfile != NULL) { |
869 | if (strcmp(logfile,"-") == 0) | |
870 | logfh = stdout; | |
871 | else { | |
872 | logfh = fopen(logfile,"wb+"); | |
873 | if (logfh == NULL) { | |
874 | callback->printf_filtered(callback,"Failed to create file \"%s\", writing log information to stderr.\n",tracefile); | |
875 | logfh = stderr; | |
876 | } | |
877 | } | |
878 | } | |
879 | ||
9d52bcb7 DE |
880 | set_endianness (); |
881 | ||
8bae0a0c JSC |
882 | /* If the host has "mmap" available we could use it to provide a |
883 | very large virtual address space for the simulator, since memory | |
884 | would only be allocated within the "mmap" space as it is | |
885 | accessed. This can also be linked to the architecture specific | |
886 | support, required to simulate the MMU. */ | |
887 | sim_size(membank_size); | |
888 | /* NOTE: The above will also have enabled any profiling state */ | |
889 | ||
890 | ColdReset(); | |
891 | /* If we were providing a more complete I/O, co-processor or memory | |
892 | simulation, we should perform any "device" initialisation at this | |
893 | point. This can include pre-loading memory areas with particular | |
894 | patterns (e.g. simulating ROM monitors). */ | |
895 | ||
896 | /* We can start writing to the memory, now that the processor has | |
897 | been reset: */ | |
898 | monitor = (unsigned char *)calloc(1,monitor_size); | |
899 | if (!monitor) { | |
900 | fprintf(stderr,"Not enough VM for monitor simulation (%d bytes)\n",monitor_size); | |
901 | } else { | |
e3d12c65 | 902 | unsigned loop; |
8bae0a0c JSC |
903 | /* Entry into the IDT monitor is via fixed address vectors, and |
904 | not using machine instructions. To avoid clashing with use of | |
905 | the MIPS TRAP system, we place our own (simulator specific) | |
906 | "undefined" instructions into the relevant vector slots. */ | |
907 | for (loop = 0; (loop < monitor_size); loop += 4) { | |
e871dd18 JSC |
908 | uword64 vaddr = (monitor_base + loop); |
909 | uword64 paddr; | |
8bae0a0c JSC |
910 | int cca; |
911 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) | |
53b9417e | 912 | StoreMemory(cca,AccessLength_WORD,(RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT)),0,paddr,vaddr,isRAW); |
8bae0a0c | 913 | } |
a9f7253f JSC |
914 | /* The PMON monitor uses the same address space, but rather than |
915 | branching into it the address of a routine is loaded. We can | |
916 | cheat for the moment, and direct the PMON routine to IDT style | |
917 | instructions within the monitor space. This relies on the IDT | |
918 | monitor not using the locations from 0xBFC00500 onwards as its | |
919 | entry points.*/ | |
920 | for (loop = 0; (loop < 24); loop++) | |
921 | { | |
922 | uword64 vaddr = (monitor_base + 0x500 + (loop * 4)); | |
923 | uword64 paddr; | |
924 | int cca; | |
925 | unsigned int value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */ | |
926 | switch (loop) | |
927 | { | |
928 | case 0: /* read */ | |
929 | value = 7; | |
930 | break; | |
931 | ||
932 | case 1: /* write */ | |
933 | value = 8; | |
934 | break; | |
935 | ||
936 | case 2: /* open */ | |
937 | value = 6; | |
938 | break; | |
939 | ||
940 | case 3: /* close */ | |
941 | value = 10; | |
942 | break; | |
943 | ||
944 | case 5: /* printf */ | |
945 | value = ((0x500 - 16) / 8); /* not an IDT reason code */ | |
946 | break; | |
947 | ||
948 | case 8: /* cliexit */ | |
949 | value = 17; | |
950 | break; | |
280f90e1 AMT |
951 | |
952 | case 11: /* flush_cache */ | |
953 | value = 28; | |
954 | break; | |
a9f7253f | 955 | } |
e3d12c65 DE |
956 | /* FIXME - should monitor_base be SIM_ADDR?? */ |
957 | value = ((unsigned int)monitor_base + (value * 8)); | |
a9f7253f | 958 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) |
53b9417e DE |
959 | StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW); |
960 | else | |
961 | sim_error("Failed to write to monitor space 0x%s",pr_addr(vaddr)); | |
962 | ||
963 | /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */ | |
964 | vaddr -= 0x300; | |
965 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) | |
966 | StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW); | |
a9f7253f | 967 | else |
53b9417e | 968 | sim_error("Failed to write to monitor space 0x%s",pr_addr(vaddr)); |
a9f7253f | 969 | } |
8bae0a0c JSC |
970 | } |
971 | ||
972 | #if defined(TRACE) | |
6429b296 JW |
973 | if (state & simTRACE) |
974 | open_trace(); | |
8bae0a0c JSC |
975 | #endif /* TRACE */ |
976 | ||
53b9417e DE |
977 | /* fudge our descriptor for now */ |
978 | return (SIM_DESC) 1; | |
8bae0a0c JSC |
979 | } |
980 | ||
6429b296 JW |
981 | #if defined(TRACE) |
982 | static void | |
983 | open_trace() | |
984 | { | |
985 | tracefh = fopen(tracefile,"wb+"); | |
986 | if (tracefh == NULL) | |
987 | { | |
988 | sim_warning("Failed to create file \"%s\", writing trace information to stderr.",tracefile); | |
989 | tracefh = stderr; | |
990 | } | |
991 | } | |
992 | #endif /* TRACE */ | |
993 | ||
8bae0a0c JSC |
994 | /* For the profile writing, we write the data in the host |
995 | endianness. This unfortunately means we are assuming that the | |
996 | profile file we create is processed on the same host executing the | |
997 | simulator. The gmon.out file format should either have an explicit | |
998 | endianness, or a method of encoding the endianness in the file | |
999 | header. */ | |
1000 | static int | |
1001 | writeout32(fh,val) | |
1002 | FILE *fh; | |
1003 | unsigned int val; | |
1004 | { | |
1005 | char buff[4]; | |
1006 | int res = 1; | |
1007 | ||
1008 | if (state & simHOSTBE) { | |
1009 | buff[3] = ((val >> 0) & 0xFF); | |
1010 | buff[2] = ((val >> 8) & 0xFF); | |
1011 | buff[1] = ((val >> 16) & 0xFF); | |
1012 | buff[0] = ((val >> 24) & 0xFF); | |
1013 | } else { | |
1014 | buff[0] = ((val >> 0) & 0xFF); | |
1015 | buff[1] = ((val >> 8) & 0xFF); | |
1016 | buff[2] = ((val >> 16) & 0xFF); | |
1017 | buff[3] = ((val >> 24) & 0xFF); | |
1018 | } | |
1019 | if (fwrite(buff,4,1,fh) != 1) { | |
f24b7b69 | 1020 | sim_warning("Failed to write 4bytes to the profile file"); |
8bae0a0c JSC |
1021 | res = 0; |
1022 | } | |
1023 | return(res); | |
1024 | } | |
1025 | ||
1026 | static int | |
1027 | writeout16(fh,val) | |
1028 | FILE *fh; | |
1029 | unsigned short val; | |
1030 | { | |
1031 | char buff[2]; | |
1032 | int res = 1; | |
1033 | if (state & simHOSTBE) { | |
1034 | buff[1] = ((val >> 0) & 0xFF); | |
1035 | buff[0] = ((val >> 8) & 0xFF); | |
1036 | } else { | |
1037 | buff[0] = ((val >> 0) & 0xFF); | |
1038 | buff[1] = ((val >> 8) & 0xFF); | |
1039 | } | |
1040 | if (fwrite(buff,2,1,fh) != 1) { | |
f24b7b69 | 1041 | sim_warning("Failed to write 2bytes to the profile file"); |
8bae0a0c JSC |
1042 | res = 0; |
1043 | } | |
1044 | return(res); | |
1045 | } | |
1046 | ||
1047 | void | |
53b9417e DE |
1048 | sim_close (sd, quitting) |
1049 | SIM_DESC sd; | |
8bae0a0c JSC |
1050 | int quitting; |
1051 | { | |
1052 | #ifdef DEBUG | |
1053 | printf("DBG: sim_close: entered (quitting = %d)\n",quitting); | |
1054 | #endif | |
1055 | ||
1056 | /* Cannot assume sim_kill() has been called */ | |
1057 | /* "quitting" is non-zero if we cannot hang on errors */ | |
1058 | ||
1059 | /* Ensure that any resources allocated through the callback | |
1060 | mechanism are released: */ | |
1061 | callback->shutdown(callback); | |
1062 | ||
1063 | #if defined(PROFILE) | |
1064 | if ((state & simPROFILE) && (profile_hist != NULL)) { | |
1065 | unsigned short *p = profile_hist; | |
1066 | FILE *pf = fopen("gmon.out","wb"); | |
e3d12c65 | 1067 | unsigned loop; |
8bae0a0c JSC |
1068 | |
1069 | if (pf == NULL) | |
f24b7b69 | 1070 | sim_warning("Failed to open \"gmon.out\" profile file"); |
8bae0a0c JSC |
1071 | else { |
1072 | int ok; | |
1073 | #ifdef DEBUG | |
53b9417e DE |
1074 | printf("DBG: minpc = 0x%s\n",pr_addr(profile_minpc)); |
1075 | printf("DBG: maxpc = 0x%s\n",pr_addr(profile_maxpc)); | |
8bae0a0c JSC |
1076 | #endif /* DEBUG */ |
1077 | ok = writeout32(pf,(unsigned int)profile_minpc); | |
1078 | if (ok) | |
1079 | ok = writeout32(pf,(unsigned int)profile_maxpc); | |
1080 | if (ok) | |
1081 | ok = writeout32(pf,(profile_nsamples * 2) + 12); /* size of sample buffer (+ header) */ | |
1082 | #ifdef DEBUG | |
1083 | printf("DBG: nsamples = %d (size = 0x%08X)\n",profile_nsamples,((profile_nsamples * 2) + 12)); | |
1084 | #endif /* DEBUG */ | |
1085 | for (loop = 0; (ok && (loop < profile_nsamples)); loop++) { | |
1086 | ok = writeout16(pf,profile_hist[loop]); | |
1087 | if (!ok) | |
1088 | break; | |
1089 | } | |
1090 | ||
1091 | fclose(pf); | |
1092 | } | |
1093 | ||
1094 | free(profile_hist); | |
1095 | profile_hist = NULL; | |
1096 | state &= ~simPROFILE; | |
1097 | } | |
1098 | #endif /* PROFILE */ | |
1099 | ||
1100 | #if defined(TRACE) | |
e3d12c65 | 1101 | if (tracefh != NULL && tracefh != stderr) |
8bae0a0c | 1102 | fclose(tracefh); |
e3d12c65 | 1103 | tracefh = NULL; |
8bae0a0c JSC |
1104 | state &= ~simTRACE; |
1105 | #endif /* TRACE */ | |
1106 | ||
f24b7b69 JSC |
1107 | if (logfh != NULL && logfh != stdout && logfh != stderr) |
1108 | fclose(logfh); | |
1109 | logfh = NULL; | |
1110 | ||
8bae0a0c | 1111 | if (membank) |
d0757082 | 1112 | free(membank); /* cfree not available on all hosts */ |
8bae0a0c JSC |
1113 | membank = NULL; |
1114 | ||
1115 | return; | |
1116 | } | |
1117 | ||
1118 | void | |
6429b296 JW |
1119 | control_c (sig, code, scp, addr) |
1120 | int sig; | |
1121 | int code; | |
1122 | char *scp; | |
1123 | char *addr; | |
8bae0a0c | 1124 | { |
6429b296 JW |
1125 | state |= (simSTOP | simSIGINT); |
1126 | } | |
1127 | ||
1128 | void | |
53b9417e DE |
1129 | sim_resume (sd,step,signal_number) |
1130 | SIM_DESC sd; | |
6429b296 JW |
1131 | int step, signal_number; |
1132 | { | |
1133 | void (*prev) (); | |
1134 | ||
8bae0a0c | 1135 | #ifdef DEBUG |
6429b296 | 1136 | printf("DBG: sim_resume entered: step = %d, signal = %d (membank = 0x%08X)\n",step,signal_number,membank); |
8bae0a0c JSC |
1137 | #endif /* DEBUG */ |
1138 | ||
1139 | if (step) | |
1140 | state |= simSTEP; /* execute only a single instruction */ | |
1141 | else | |
1142 | state &= ~(simSTOP | simSTEP); /* execute until event */ | |
1143 | ||
1144 | state |= (simHALTEX | simHALTIN); /* treat interrupt event as exception */ | |
1145 | ||
1146 | /* Start executing instructions from the current state (set | |
1147 | explicitly by register updates, or by sim_create_inferior): */ | |
1148 | ||
6429b296 JW |
1149 | prev = signal (SIGINT, control_c); |
1150 | ||
8bae0a0c | 1151 | simulate(); |
6429b296 JW |
1152 | |
1153 | signal (SIGINT, prev); | |
1154 | ||
8bae0a0c JSC |
1155 | return; |
1156 | } | |
1157 | ||
1158 | int | |
53b9417e DE |
1159 | sim_write (sd,addr,buffer,size) |
1160 | SIM_DESC sd; | |
8bae0a0c JSC |
1161 | SIM_ADDR addr; |
1162 | unsigned char *buffer; | |
1163 | int size; | |
1164 | { | |
1165 | int index = size; | |
e871dd18 | 1166 | uword64 vaddr = (uword64)addr; |
8bae0a0c JSC |
1167 | |
1168 | /* Return the number of bytes written, or zero if error. */ | |
1169 | #ifdef DEBUG | |
53b9417e | 1170 | callback->printf_filtered(callback,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
1171 | #endif |
1172 | ||
1173 | /* We provide raw read and write routines, since we do not want to | |
1174 | count the GDB memory accesses in our statistics gathering. */ | |
1175 | ||
1176 | /* There is a lot of code duplication in the individual blocks | |
1177 | below, but the variables are declared locally to a block to give | |
1178 | the optimiser the best chance of improving the code. We have to | |
1179 | perform slow byte reads from the host memory, to ensure that we | |
1180 | get the data into the correct endianness for the (simulated) | |
1181 | target memory world. */ | |
1182 | ||
1183 | /* Mask count to get odd byte, odd halfword, and odd word out of the | |
1184 | way. We can then perform doubleword transfers to and from the | |
1185 | simulator memory for optimum performance. */ | |
1186 | if (index && (index & 1)) { | |
e871dd18 | 1187 | uword64 paddr; |
8bae0a0c JSC |
1188 | int cca; |
1189 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) { | |
e871dd18 | 1190 | uword64 value = ((uword64)(*buffer++)); |
53b9417e | 1191 | StoreMemory(cca,AccessLength_BYTE,value,0,paddr,vaddr,isRAW); |
8bae0a0c JSC |
1192 | } |
1193 | vaddr++; | |
1194 | index &= ~1; /* logical operations usually quicker than arithmetic on RISC systems */ | |
1195 | } | |
1196 | if (index && (index & 2)) { | |
e871dd18 | 1197 | uword64 paddr; |
8bae0a0c JSC |
1198 | int cca; |
1199 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) { | |
e871dd18 | 1200 | uword64 value; |
8bae0a0c JSC |
1201 | /* We need to perform the following magic to ensure that that |
1202 | bytes are written into same byte positions in the target memory | |
1203 | world, regardless of the endianness of the host. */ | |
0049ba7a | 1204 | if (BigEndianMem) { |
e871dd18 JSC |
1205 | value = ((uword64)(*buffer++) << 8); |
1206 | value |= ((uword64)(*buffer++) << 0); | |
8bae0a0c | 1207 | } else { |
e871dd18 JSC |
1208 | value = ((uword64)(*buffer++) << 0); |
1209 | value |= ((uword64)(*buffer++) << 8); | |
8bae0a0c | 1210 | } |
53b9417e | 1211 | StoreMemory(cca,AccessLength_HALFWORD,value,0,paddr,vaddr,isRAW); |
8bae0a0c JSC |
1212 | } |
1213 | vaddr += 2; | |
1214 | index &= ~2; | |
1215 | } | |
1216 | if (index && (index & 4)) { | |
e871dd18 | 1217 | uword64 paddr; |
8bae0a0c JSC |
1218 | int cca; |
1219 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) { | |
e871dd18 | 1220 | uword64 value; |
0049ba7a | 1221 | if (BigEndianMem) { |
e871dd18 JSC |
1222 | value = ((uword64)(*buffer++) << 24); |
1223 | value |= ((uword64)(*buffer++) << 16); | |
1224 | value |= ((uword64)(*buffer++) << 8); | |
1225 | value |= ((uword64)(*buffer++) << 0); | |
8bae0a0c | 1226 | } else { |
e871dd18 JSC |
1227 | value = ((uword64)(*buffer++) << 0); |
1228 | value |= ((uword64)(*buffer++) << 8); | |
1229 | value |= ((uword64)(*buffer++) << 16); | |
1230 | value |= ((uword64)(*buffer++) << 24); | |
8bae0a0c | 1231 | } |
53b9417e | 1232 | StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW); |
8bae0a0c JSC |
1233 | } |
1234 | vaddr += 4; | |
1235 | index &= ~4; | |
1236 | } | |
1237 | for (;index; index -= 8) { | |
e871dd18 | 1238 | uword64 paddr; |
8bae0a0c JSC |
1239 | int cca; |
1240 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) { | |
e871dd18 | 1241 | uword64 value; |
0049ba7a | 1242 | if (BigEndianMem) { |
e871dd18 JSC |
1243 | value = ((uword64)(*buffer++) << 56); |
1244 | value |= ((uword64)(*buffer++) << 48); | |
1245 | value |= ((uword64)(*buffer++) << 40); | |
1246 | value |= ((uword64)(*buffer++) << 32); | |
1247 | value |= ((uword64)(*buffer++) << 24); | |
1248 | value |= ((uword64)(*buffer++) << 16); | |
1249 | value |= ((uword64)(*buffer++) << 8); | |
1250 | value |= ((uword64)(*buffer++) << 0); | |
8bae0a0c | 1251 | } else { |
e871dd18 JSC |
1252 | value = ((uword64)(*buffer++) << 0); |
1253 | value |= ((uword64)(*buffer++) << 8); | |
1254 | value |= ((uword64)(*buffer++) << 16); | |
1255 | value |= ((uword64)(*buffer++) << 24); | |
1256 | value |= ((uword64)(*buffer++) << 32); | |
1257 | value |= ((uword64)(*buffer++) << 40); | |
1258 | value |= ((uword64)(*buffer++) << 48); | |
1259 | value |= ((uword64)(*buffer++) << 56); | |
8bae0a0c | 1260 | } |
53b9417e | 1261 | StoreMemory(cca,AccessLength_DOUBLEWORD,value,0,paddr,vaddr,isRAW); |
8bae0a0c JSC |
1262 | } |
1263 | vaddr += 8; | |
1264 | } | |
1265 | ||
1266 | return(size); | |
1267 | } | |
1268 | ||
1269 | int | |
53b9417e DE |
1270 | sim_read (sd,addr,buffer,size) |
1271 | SIM_DESC sd; | |
8bae0a0c JSC |
1272 | SIM_ADDR addr; |
1273 | unsigned char *buffer; | |
1274 | int size; | |
1275 | { | |
1276 | int index; | |
1277 | ||
1278 | /* Return the number of bytes read, or zero if error. */ | |
1279 | #ifdef DEBUG | |
53b9417e | 1280 | callback->printf_filtered(callback,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
1281 | #endif /* DEBUG */ |
1282 | ||
1283 | /* TODO: Perform same optimisation as the sim_write() code | |
1284 | above. NOTE: This will require a bit more work since we will need | |
1285 | to ensure that the source physical address is doubleword aligned | |
1286 | before, and then deal with trailing bytes. */ | |
1287 | for (index = 0; (index < size); index++) { | |
e871dd18 | 1288 | uword64 vaddr,paddr,value; |
8bae0a0c | 1289 | int cca; |
e871dd18 | 1290 | vaddr = (uword64)addr + index; |
8bae0a0c | 1291 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&cca,isTARGET,isRAW)) { |
53b9417e | 1292 | LoadMemory(&value,NULL,cca,AccessLength_BYTE,paddr,vaddr,isDATA,isRAW); |
8bae0a0c JSC |
1293 | buffer[index] = (unsigned char)(value&0xFF); |
1294 | } else | |
1295 | break; | |
1296 | } | |
1297 | ||
1298 | return(index); | |
1299 | } | |
1300 | ||
1301 | void | |
53b9417e DE |
1302 | sim_store_register (sd,rn,memory) |
1303 | SIM_DESC sd; | |
8bae0a0c JSC |
1304 | int rn; |
1305 | unsigned char *memory; | |
1306 | { | |
1307 | #ifdef DEBUG | |
53b9417e | 1308 | callback->printf_filtered(callback,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory))); |
8bae0a0c JSC |
1309 | #endif /* DEBUG */ |
1310 | ||
1311 | /* Unfortunately this suffers from the same problem as the register | |
1312 | numbering one. We need to know what the width of each logical | |
1313 | register number is for the architecture being simulated. */ | |
1314 | if (register_widths[rn] == 0) | |
f24b7b69 | 1315 | sim_warning("Invalid register width for %d (register store ignored)",rn); |
8bae0a0c JSC |
1316 | else { |
1317 | if (register_widths[rn] == 32) | |
f7481d45 | 1318 | registers[rn] = host_read_word(memory); |
8bae0a0c | 1319 | else |
f7481d45 | 1320 | registers[rn] = host_read_long(memory); |
8bae0a0c JSC |
1321 | } |
1322 | ||
1323 | return; | |
1324 | } | |
1325 | ||
1326 | void | |
53b9417e DE |
1327 | sim_fetch_register (sd,rn,memory) |
1328 | SIM_DESC sd; | |
8bae0a0c JSC |
1329 | int rn; |
1330 | unsigned char *memory; | |
1331 | { | |
1332 | #ifdef DEBUG | |
53b9417e | 1333 | callback->printf_filtered(callback,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn])); |
8bae0a0c JSC |
1334 | #endif /* DEBUG */ |
1335 | ||
1336 | if (register_widths[rn] == 0) | |
f24b7b69 | 1337 | sim_warning("Invalid register width for %d (register fetch ignored)",rn); |
8bae0a0c JSC |
1338 | else { |
1339 | if (register_widths[rn] == 32) | |
e3d12c65 | 1340 | *((unsigned int *)memory) = host_swap_word((unsigned int)(registers[rn] & 0xFFFFFFFF)); |
8bae0a0c | 1341 | else /* 64bit register */ |
f7481d45 | 1342 | *((uword64 *)memory) = host_swap_long(registers[rn]); |
8bae0a0c JSC |
1343 | } |
1344 | return; | |
1345 | } | |
1346 | ||
1347 | void | |
53b9417e DE |
1348 | sim_stop_reason (sd,reason,sigrc) |
1349 | SIM_DESC sd; | |
8bae0a0c JSC |
1350 | enum sim_stop *reason; |
1351 | int *sigrc; | |
1352 | { | |
1353 | /* We can have "*reason = {sim_exited, sim_stopped, sim_signalled}", so | |
1354 | sim_exited *sigrc = argument to exit() | |
1355 | sim_stopped *sigrc = exception number | |
1356 | sim_signalled *sigrc = signal number | |
1357 | */ | |
1358 | if (state & simEXCEPTION) { | |
1359 | /* If "sim_signalled" is used, GDB expects normal SIGNAL numbers, | |
1360 | and not the MIPS specific exception codes. */ | |
1361 | #if 1 | |
1362 | /* For some reason, sending GDB a sim_signalled reason cause it to | |
1363 | terminate out. */ | |
1364 | *reason = sim_stopped; | |
1365 | #else | |
1366 | *reason = sim_signalled; | |
1367 | #endif | |
1368 | switch ((CAUSE >> 2) & 0x1F) { | |
1369 | case Interrupt: | |
1370 | *sigrc = SIGINT; /* wrong type of interrupt, but it will do for the moment */ | |
1371 | break; | |
1372 | ||
1373 | case TLBModification: | |
1374 | case TLBLoad: | |
1375 | case TLBStore: | |
1376 | case AddressLoad: | |
1377 | case AddressStore: | |
1378 | case InstructionFetch: | |
1379 | case DataReference: | |
1380 | *sigrc = SIGBUS; | |
1381 | break; | |
1382 | ||
1383 | case ReservedInstruction: | |
1384 | case CoProcessorUnusable: | |
1385 | *sigrc = SIGILL; | |
1386 | break; | |
1387 | ||
1388 | case IntegerOverflow: | |
1389 | case FPE: | |
1390 | *sigrc = SIGFPE; | |
1391 | break; | |
1392 | ||
1393 | case Trap: | |
1394 | case Watch: | |
1395 | case SystemCall: | |
1396 | case BreakPoint: | |
1397 | *sigrc = SIGTRAP; | |
1398 | break; | |
1399 | ||
1400 | default : /* Unknown internal exception */ | |
1401 | *sigrc = SIGQUIT; | |
1402 | break; | |
1403 | } | |
1404 | } else if (state & simEXIT) { | |
53b9417e | 1405 | #if DEBUG |
8bae0a0c | 1406 | printf("DBG: simEXIT (%d)\n",rcexit); |
f24b7b69 | 1407 | #endif |
8bae0a0c JSC |
1408 | *reason = sim_exited; |
1409 | *sigrc = rcexit; | |
6429b296 JW |
1410 | } else if (state & simSIGINT) { |
1411 | *reason = sim_stopped; | |
1412 | *sigrc = SIGINT; | |
8bae0a0c JSC |
1413 | } else { /* assume single-stepping */ |
1414 | *reason = sim_stopped; | |
1415 | *sigrc = SIGTRAP; | |
1416 | } | |
6429b296 | 1417 | state &= ~(simEXCEPTION | simEXIT | simSIGINT); |
8bae0a0c JSC |
1418 | return; |
1419 | } | |
1420 | ||
1421 | void | |
53b9417e DE |
1422 | sim_info (sd,verbose) |
1423 | SIM_DESC sd; | |
8bae0a0c JSC |
1424 | int verbose; |
1425 | { | |
1426 | /* Accessed from the GDB "info files" command: */ | |
1427 | ||
1428 | callback->printf_filtered(callback,"MIPS %d-bit simulator\n",(PROCESSOR_64BIT ? 64 : 32)); | |
1429 | ||
aaff8437 | 1430 | callback->printf_filtered(callback,"%s endian memory model\n",(state & simBE ? "Big" : "Little")); |
8bae0a0c | 1431 | |
53b9417e | 1432 | callback->printf_filtered(callback,"0x%08X bytes of memory at 0x%s\n",(unsigned int)membank_size,pr_addr(membank_base)); |
8bae0a0c JSC |
1433 | |
1434 | #if !defined(FASTSIM) | |
a9f7253f JSC |
1435 | if (instruction_fetch_overflow != 0) |
1436 | callback->printf_filtered(callback,"Instruction fetches = 0x%08X%08X\n",instruction_fetch_overflow,instruction_fetches); | |
1437 | else | |
1438 | callback->printf_filtered(callback,"Instruction fetches = %d\n",instruction_fetches); | |
8bae0a0c JSC |
1439 | callback->printf_filtered(callback,"Pipeline ticks = %d\n",pipeline_ticks); |
1440 | /* It would be a useful feature, if when performing multi-cycle | |
1441 | simulations (rather than single-stepping) we keep the start and | |
1442 | end times of the execution, so that we can give a performance | |
1443 | figure for the simulator. */ | |
1444 | #endif /* !FASTSIM */ | |
1445 | ||
1446 | /* print information pertaining to MIPS ISA and architecture being simulated */ | |
1447 | /* things that may be interesting */ | |
1448 | /* instructions executed - if available */ | |
1449 | /* cycles executed - if available */ | |
1450 | /* pipeline stalls - if available */ | |
1451 | /* virtual time taken */ | |
1452 | /* profiling size */ | |
1453 | /* profiling frequency */ | |
1454 | /* profile minpc */ | |
1455 | /* profile maxpc */ | |
1456 | ||
1457 | return; | |
1458 | } | |
1459 | ||
9d52bcb7 DE |
1460 | SIM_RC |
1461 | sim_load (sd,prog,abfd,from_tty) | |
53b9417e | 1462 | SIM_DESC sd; |
8bae0a0c | 1463 | char *prog; |
9d52bcb7 | 1464 | bfd *abfd; |
8bae0a0c JSC |
1465 | int from_tty; |
1466 | { | |
9d52bcb7 DE |
1467 | extern bfd *sim_load_file (); /* ??? Don't know where this should live. */ |
1468 | bfd *prog_bfd; | |
1469 | ||
1470 | prog_bfd = sim_load_file (sd, myname, callback, prog, abfd, | |
1471 | sim_kind == SIM_OPEN_DEBUG); | |
1472 | if (prog_bfd == NULL) | |
1473 | return SIM_RC_FAIL; | |
1474 | #if 1 | |
1475 | PC = (uword64) bfd_get_start_address (prog_bfd); | |
1476 | #else | |
1477 | /* TODO: Sort this properly. SIM_ADDR may already be a 64bit value: */ | |
1478 | PC = SIGNEXTEND(bfd_get_start_address(prog_bfd),32); | |
1479 | #endif | |
1480 | if (abfd == NULL) | |
1481 | bfd_close (prog_bfd); | |
1482 | return SIM_RC_OK; | |
8bae0a0c JSC |
1483 | } |
1484 | ||
9d52bcb7 DE |
1485 | SIM_RC |
1486 | sim_create_inferior (sd, argv,env) | |
53b9417e | 1487 | SIM_DESC sd; |
8bae0a0c JSC |
1488 | char **argv; |
1489 | char **env; | |
1490 | { | |
1491 | #ifdef DEBUG | |
9d52bcb7 DE |
1492 | printf("DBG: sim_create_inferior entered: start_address = 0x%s\n", |
1493 | pr_addr(PC)); | |
8bae0a0c JSC |
1494 | #endif /* DEBUG */ |
1495 | ||
1496 | /* Prepare to execute the program to be simulated */ | |
1497 | /* argv and env are NULL terminated lists of pointers */ | |
1498 | ||
8bae0a0c | 1499 | if (argv || env) { |
f24b7b69 | 1500 | #if 0 /* def DEBUG */ |
8bae0a0c | 1501 | callback->printf_filtered(callback,"sim_create_inferior() : passed arguments ignored\n"); |
8bae0a0c JSC |
1502 | { |
1503 | char **cptr; | |
1504 | for (cptr = argv; (cptr && *cptr); cptr++) | |
1505 | printf("DBG: arg \"%s\"\n",*cptr); | |
1506 | } | |
1507 | #endif /* DEBUG */ | |
1508 | /* We should really place the argv slot values into the argument | |
1509 | registers, and onto the stack as required. However, this | |
1510 | assumes that we have a stack defined, which is not necessarily | |
1511 | true at the moment. */ | |
1512 | } | |
1513 | ||
9d52bcb7 | 1514 | return SIM_RC_OK; |
8bae0a0c JSC |
1515 | } |
1516 | ||
1517 | void | |
53b9417e DE |
1518 | sim_kill (sd) |
1519 | SIM_DESC sd; | |
8bae0a0c JSC |
1520 | { |
1521 | #if 1 | |
1522 | /* This routine should be for terminating any existing simulation | |
1523 | thread. Since we are single-threaded only at the moment, this is | |
1524 | not an issue. It should *NOT* be used to terminate the | |
1525 | simulator. */ | |
1526 | #else /* do *NOT* call sim_close */ | |
53b9417e | 1527 | sim_close(sd, 1); /* Do not hang on errors */ |
8bae0a0c JSC |
1528 | /* This would also be the point where any memory mapped areas used |
1529 | by the simulator should be released. */ | |
1530 | #endif | |
1531 | return; | |
1532 | } | |
1533 | ||
e3d12c65 | 1534 | ut_reg |
8bae0a0c JSC |
1535 | sim_get_quit_code () |
1536 | { | |
1537 | /* The standard MIPS PCS (Procedure Calling Standard) uses V0(r2) as | |
1538 | the function return value. However, it may be more correct for | |
1539 | this to return the argument to the exit() function (if | |
1540 | called). */ | |
1541 | return(V0); | |
1542 | } | |
1543 | ||
1544 | void | |
53b9417e DE |
1545 | sim_set_callbacks (sd,p) |
1546 | SIM_DESC sd; | |
8bae0a0c JSC |
1547 | host_callback *p; |
1548 | { | |
1549 | callback = p; | |
1550 | return; | |
1551 | } | |
1552 | ||
1553 | typedef enum {e_terminate,e_help,e_setmemsize,e_reset} e_cmds; | |
1554 | ||
1555 | static struct t_sim_command { | |
1556 | e_cmds id; | |
1557 | const char *name; | |
1558 | const char *help; | |
1559 | } sim_commands[] = { | |
1560 | {e_help, "help", ": Show MIPS simulator private commands"}, | |
1561 | {e_setmemsize,"set-memory-size","<n> : Specify amount of memory simulated"}, | |
1562 | {e_reset, "reset-system", ": Reset the simulated processor"}, | |
1563 | {e_terminate, NULL} | |
1564 | }; | |
1565 | ||
1566 | void | |
53b9417e DE |
1567 | sim_do_command (sd,cmd) |
1568 | SIM_DESC sd; | |
8bae0a0c JSC |
1569 | char *cmd; |
1570 | { | |
1571 | struct t_sim_command *cptr; | |
1572 | ||
8b554809 JSC |
1573 | if (callback == NULL) { |
1574 | fprintf(stderr,"Simulator not enabled: \"target sim\" should be used to activate\n"); | |
1575 | return; | |
1576 | } | |
1577 | ||
8bae0a0c JSC |
1578 | if (!(cmd && *cmd != '\0')) |
1579 | cmd = "help"; | |
1580 | ||
1581 | /* NOTE: Accessed from the GDB "sim" commmand: */ | |
1582 | for (cptr = sim_commands; cptr && cptr->name; cptr++) | |
1583 | if (strncmp(cmd,cptr->name,strlen(cptr->name)) == 0) { | |
1584 | cmd += strlen(cptr->name); | |
1585 | switch (cptr->id) { | |
1586 | case e_help: /* no arguments */ | |
1587 | { /* no arguments */ | |
1588 | struct t_sim_command *lptr; | |
1589 | callback->printf_filtered(callback,"List of MIPS simulator commands:\n"); | |
1590 | for (lptr = sim_commands; lptr->name; lptr++) | |
1591 | callback->printf_filtered(callback,"%s %s\n",lptr->name,lptr->help); | |
1592 | } | |
1593 | break; | |
1594 | ||
1595 | case e_setmemsize: /* memory size argument */ | |
1596 | { | |
1597 | unsigned int newsize = (unsigned int)getnum(cmd); | |
1598 | sim_size(newsize); | |
1599 | } | |
1600 | break; | |
1601 | ||
1602 | case e_reset: /* no arguments */ | |
1603 | ColdReset(); | |
1604 | /* NOTE: See the comments in sim_open() relating to device | |
1605 | initialisation. */ | |
1606 | break; | |
1607 | ||
1608 | default: | |
1609 | callback->printf_filtered(callback,"FATAL: Matched \"%s\", but failed to match command id %d.\n",cmd,cptr->id); | |
1610 | break; | |
1611 | } | |
1612 | break; | |
1613 | } | |
1614 | ||
1615 | if (!(cptr->name)) | |
1616 | callback->printf_filtered(callback,"Error: \"%s\" is not a valid MIPS simulator command.\n",cmd); | |
1617 | ||
1618 | return; | |
1619 | } | |
1620 | ||
1621 | /*---------------------------------------------------------------------------*/ | |
1622 | /* NOTE: The following routines do not seem to be used by GDB at the | |
1623 | moment. However, they may be useful to the standalone simulator | |
1624 | world. */ | |
1625 | ||
1626 | ||
1627 | /* The profiling format is described in the "gmon_out.h" header file */ | |
1628 | void | |
1629 | sim_set_profile (n) | |
1630 | int n; | |
1631 | { | |
1632 | #if defined(PROFILE) | |
1633 | profile_frequency = n; | |
1634 | state |= simPROFILE; | |
1635 | #endif /* PROFILE */ | |
1636 | return; | |
1637 | } | |
1638 | ||
1639 | void | |
1640 | sim_set_profile_size (n) | |
1641 | int n; | |
1642 | { | |
1643 | #if defined(PROFILE) | |
1644 | if (state & simPROFILE) { | |
1645 | int bsize; | |
1646 | ||
1647 | /* Since we KNOW that the memory banks are a power-of-2 in size: */ | |
1648 | profile_nsamples = power2(n); | |
1649 | profile_minpc = membank_base; | |
1650 | profile_maxpc = (membank_base + membank_size); | |
1651 | ||
1652 | /* Just in-case we are sampling every address: NOTE: The shift | |
1653 | right of 2 is because we only have word-aligned PC addresses. */ | |
1654 | if (profile_nsamples > (membank_size >> 2)) | |
1655 | profile_nsamples = (membank_size >> 2); | |
1656 | ||
1657 | /* Since we are dealing with power-of-2 values: */ | |
1658 | profile_shift = (((membank_size >> 2) / profile_nsamples) - 1); | |
1659 | ||
1660 | bsize = (profile_nsamples * sizeof(unsigned short)); | |
1661 | if (profile_hist == NULL) | |
1662 | profile_hist = (unsigned short *)calloc(64,(bsize / 64)); | |
1663 | else | |
1664 | profile_hist = (unsigned short *)realloc(profile_hist,bsize); | |
1665 | if (profile_hist == NULL) { | |
f24b7b69 | 1666 | sim_warning("Failed to allocate VM for profiling buffer (0x%08X bytes)",bsize); |
8bae0a0c JSC |
1667 | state &= ~simPROFILE; |
1668 | } | |
1669 | } | |
1670 | #endif /* PROFILE */ | |
1671 | ||
1672 | return; | |
1673 | } | |
1674 | ||
1675 | void | |
1676 | sim_size(newsize) | |
87e43259 | 1677 | int newsize; |
8bae0a0c JSC |
1678 | { |
1679 | char *new; | |
1680 | /* Used by "run", and internally, to set the simulated memory size */ | |
f24b7b69 JSC |
1681 | if (newsize == 0) { |
1682 | callback->printf_filtered(callback,"Zero not valid: Memory size still 0x%08X bytes\n",membank_size); | |
1683 | return; | |
1684 | } | |
8bae0a0c JSC |
1685 | newsize = power2(newsize); |
1686 | if (membank == NULL) | |
1687 | new = (char *)calloc(64,(membank_size / 64)); | |
1688 | else | |
1689 | new = (char *)realloc(membank,newsize); | |
1690 | if (new == NULL) { | |
1691 | if (membank == NULL) | |
f24b7b69 | 1692 | sim_error("Not enough VM for simulation memory of 0x%08X bytes",membank_size); |
8bae0a0c | 1693 | else |
f24b7b69 | 1694 | sim_warning("Failed to resize memory (still 0x%08X bytes)",membank_size); |
8bae0a0c JSC |
1695 | } else { |
1696 | membank_size = (unsigned)newsize; | |
1697 | membank = new; | |
8bae0a0c JSC |
1698 | #if defined(PROFILE) |
1699 | /* Ensure that we sample across the new memory range */ | |
1700 | sim_set_profile_size(profile_nsamples); | |
1701 | #endif /* PROFILE */ | |
1702 | } | |
1703 | ||
1704 | return; | |
1705 | } | |
1706 | ||
1707 | int | |
53b9417e DE |
1708 | sim_trace(sd) |
1709 | SIM_DESC sd; | |
8bae0a0c JSC |
1710 | { |
1711 | /* This routine is called by the "run" program, when detailed | |
1712 | execution information is required. Rather than executing a single | |
1713 | instruction, and looping around externally... we just start | |
1714 | simulating, returning TRUE when the simulator stops (for whatever | |
1715 | reason). */ | |
1716 | ||
1717 | #if defined(TRACE) | |
1718 | /* Ensure tracing is enabled, if available */ | |
6429b296 JW |
1719 | if (tracefh == NULL) |
1720 | { | |
1721 | open_trace(); | |
1722 | state |= simTRACE; | |
1723 | } | |
8bae0a0c JSC |
1724 | #endif /* TRACE */ |
1725 | ||
1726 | state &= ~(simSTOP | simSTEP); /* execute until event */ | |
1727 | state |= (simHALTEX | simHALTIN); /* treat interrupt event as exception */ | |
1728 | /* Start executing instructions from the current state (set | |
1729 | explicitly by register updates, or by sim_create_inferior): */ | |
1730 | simulate(); | |
1731 | ||
1732 | return(1); | |
1733 | } | |
1734 | ||
1735 | /*---------------------------------------------------------------------------*/ | |
1736 | /*-- Private simulator support interface ------------------------------------*/ | |
1737 | /*---------------------------------------------------------------------------*/ | |
1738 | ||
a9f7253f | 1739 | /* Simple monitor interface (currently setup for the IDT and PMON monitors) */ |
8bae0a0c JSC |
1740 | static void |
1741 | sim_monitor(reason) | |
1742 | unsigned int reason; | |
1743 | { | |
53b9417e DE |
1744 | #ifdef DEBUG |
1745 | printf("DBG: sim_monitor: entered (reason = %d)\n",reason); | |
1746 | #endif /* DEBUG */ | |
1747 | ||
8bae0a0c JSC |
1748 | /* The IDT monitor actually allows two instructions per vector |
1749 | slot. However, the simulator currently causes a trap on each | |
1750 | individual instruction. We cheat, and lose the bottom bit. */ | |
1751 | reason >>= 1; | |
1752 | ||
1753 | /* The following callback functions are available, however the | |
1754 | monitor we are simulating does not make use of them: get_errno, | |
1755 | isatty, lseek, rename, system, time and unlink */ | |
1756 | switch (reason) { | |
1757 | case 6: /* int open(char *path,int flags) */ | |
1758 | { | |
e871dd18 | 1759 | uword64 paddr; |
8bae0a0c JSC |
1760 | int cca; |
1761 | if (AddressTranslation(A0,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) | |
1762 | V0 = callback->open(callback,(char *)((int)paddr),(int)A1); | |
1763 | else | |
f24b7b69 | 1764 | sim_error("Attempt to pass pointer that does not reference simulated memory"); |
8bae0a0c JSC |
1765 | } |
1766 | break; | |
1767 | ||
1768 | case 7: /* int read(int file,char *ptr,int len) */ | |
1769 | { | |
e871dd18 | 1770 | uword64 paddr; |
8bae0a0c JSC |
1771 | int cca; |
1772 | if (AddressTranslation(A1,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) | |
1773 | V0 = callback->read(callback,(int)A0,(char *)((int)paddr),(int)A2); | |
1774 | else | |
f24b7b69 | 1775 | sim_error("Attempt to pass pointer that does not reference simulated memory"); |
8bae0a0c JSC |
1776 | } |
1777 | break; | |
1778 | ||
1779 | case 8: /* int write(int file,char *ptr,int len) */ | |
1780 | { | |
e871dd18 | 1781 | uword64 paddr; |
8bae0a0c JSC |
1782 | int cca; |
1783 | if (AddressTranslation(A1,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) | |
53b9417e | 1784 | V0 = callback->write(callback,(int)A0,(const char *)((int)paddr),(int)A2); |
8bae0a0c | 1785 | else |
f24b7b69 | 1786 | sim_error("Attempt to pass pointer that does not reference simulated memory"); |
8bae0a0c JSC |
1787 | } |
1788 | break; | |
1789 | ||
1790 | case 10: /* int close(int file) */ | |
1791 | V0 = callback->close(callback,(int)A0); | |
1792 | break; | |
1793 | ||
1794 | case 11: /* char inbyte(void) */ | |
1795 | { | |
1796 | char tmp; | |
1797 | if (callback->read_stdin(callback,&tmp,sizeof(char)) != sizeof(char)) { | |
f24b7b69 | 1798 | sim_error("Invalid return from character read"); |
e3d12c65 | 1799 | V0 = (ut_reg)-1; |
8bae0a0c JSC |
1800 | } |
1801 | else | |
e3d12c65 | 1802 | V0 = (ut_reg)tmp; |
8bae0a0c JSC |
1803 | } |
1804 | break; | |
1805 | ||
1806 | case 12: /* void outbyte(char chr) : write a byte to "stdout" */ | |
1807 | { | |
1808 | char tmp = (char)(A0 & 0xFF); | |
1809 | callback->write_stdout(callback,&tmp,sizeof(char)); | |
1810 | } | |
1811 | break; | |
1812 | ||
1813 | case 17: /* void _exit() */ | |
f24b7b69 | 1814 | sim_warning("sim_monitor(17): _exit(int reason) to be coded"); |
8bae0a0c JSC |
1815 | state |= (simSTOP | simEXIT); /* stop executing code */ |
1816 | rcexit = (unsigned int)(A0 & 0xFFFFFFFF); | |
1817 | break; | |
1818 | ||
280f90e1 AMT |
1819 | case 28 : /* PMON flush_cache */ |
1820 | break; | |
1821 | ||
8bae0a0c JSC |
1822 | case 55: /* void get_mem_info(unsigned int *ptr) */ |
1823 | /* in: A0 = pointer to three word memory location */ | |
1824 | /* out: [A0 + 0] = size */ | |
1825 | /* [A0 + 4] = instruction cache size */ | |
1826 | /* [A0 + 8] = data cache size */ | |
1827 | { | |
e871dd18 JSC |
1828 | uword64 vaddr = A0; |
1829 | uword64 paddr, value; | |
8bae0a0c JSC |
1830 | int cca; |
1831 | int failed = 0; | |
1832 | ||
1833 | /* NOTE: We use RAW memory writes here, but since we are not | |
1834 | gathering statistics for the monitor calls we are simulating, | |
1835 | it is not an issue. */ | |
1836 | ||
1837 | /* Memory size */ | |
1838 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL)) { | |
e871dd18 | 1839 | value = (uword64)membank_size; |
53b9417e | 1840 | StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW); |
8bae0a0c JSC |
1841 | /* We re-do the address translations, in-case the block |
1842 | overlaps a memory boundary: */ | |
1843 | value = 0; | |
1844 | vaddr += (AccessLength_WORD + 1); | |
1845 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL)) { | |
53b9417e | 1846 | StoreMemory(cca,AccessLength_WORD,0,value,paddr,vaddr,isRAW); |
8bae0a0c JSC |
1847 | vaddr += (AccessLength_WORD + 1); |
1848 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL)) | |
53b9417e | 1849 | StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW); |
8bae0a0c JSC |
1850 | else |
1851 | failed = -1; | |
1852 | } else | |
1853 | failed = -1; | |
1854 | } else | |
1855 | failed = -1; | |
1856 | ||
1857 | if (failed) | |
f24b7b69 | 1858 | sim_error("Invalid pointer passed into monitor call"); |
8bae0a0c JSC |
1859 | } |
1860 | break; | |
1861 | ||
a9f7253f JSC |
1862 | case 158 : /* PMON printf */ |
1863 | /* in: A0 = pointer to format string */ | |
1864 | /* A1 = optional argument 1 */ | |
1865 | /* A2 = optional argument 2 */ | |
1866 | /* A3 = optional argument 3 */ | |
1867 | /* out: void */ | |
f24b7b69 | 1868 | /* The following is based on the PMON printf source */ |
a9f7253f JSC |
1869 | { |
1870 | uword64 paddr; | |
1871 | int cca; | |
f24b7b69 JSC |
1872 | /* This isn't the quickest way, since we call the host print |
1873 | routine for every character almost. But it does avoid | |
1874 | having to allocate and manage a temporary string buffer. */ | |
1875 | if (AddressTranslation(A0,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) { | |
1876 | char *s = (char *)((int)paddr); | |
1877 | ut_reg *ap = &A1; /* 1st argument */ | |
1878 | /* TODO: Include check that we only use three arguments (A1, A2 and A3) */ | |
1879 | for (; *s;) { | |
1880 | if (*s == '%') { | |
1881 | char tmp[40]; | |
1882 | enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST; | |
1883 | int width = 0, trunc = 0, haddot = 0, longlong = 0; | |
1884 | int base = 10; | |
1885 | s++; | |
1886 | for (; *s; s++) { | |
1887 | if (strchr ("dobxXulscefg%", *s)) | |
1888 | break; | |
1889 | else if (*s == '-') | |
1890 | fmt = FMT_LJUST; | |
1891 | else if (*s == '0') | |
1892 | fmt = FMT_RJUST0; | |
1893 | else if (*s == '~') | |
1894 | fmt = FMT_CENTER; | |
1895 | else if (*s == '*') { | |
1896 | if (haddot) | |
1897 | trunc = (int)*ap++; | |
1898 | else | |
1899 | width = (int)*ap++; | |
1900 | } else if (*s >= '1' && *s <= '9') { | |
1901 | char *t; | |
1902 | unsigned int n; | |
1903 | for (t = s; isdigit (*s); s++); | |
1904 | strncpy (tmp, t, s - t); | |
1905 | tmp[s - t] = '\0'; | |
1906 | n = (unsigned int)strtol(tmp,NULL,10); | |
1907 | if (haddot) | |
1908 | trunc = n; | |
1909 | else | |
1910 | width = n; | |
1911 | s--; | |
1912 | } else if (*s == '.') | |
1913 | haddot = 1; | |
1914 | } | |
1915 | if (*s == '%') { | |
1916 | callback->printf_filtered(callback,"%%"); | |
1917 | } else if (*s == 's') { | |
1918 | if ((int)*ap != 0) { | |
1919 | if (AddressTranslation(*ap++,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) { | |
1920 | char *p = (char *)((int)paddr);; | |
1921 | callback->printf_filtered(callback,p); | |
1922 | } else { | |
1923 | ap++; | |
1924 | sim_error("Attempt to pass pointer that does not reference simulated memory"); | |
1925 | } | |
1926 | } | |
1927 | else | |
1928 | callback->printf_filtered(callback,"(null)"); | |
1929 | } else if (*s == 'c') { | |
1930 | int n = (int)*ap++; | |
1931 | callback->printf_filtered(callback,"%c",n); | |
1932 | } else { | |
1933 | if (*s == 'l') { | |
1934 | if (*++s == 'l') { | |
1935 | longlong = 1; | |
1936 | ++s; | |
1937 | } | |
1938 | } | |
1939 | if (strchr ("dobxXu", *s)) { | |
e3d12c65 | 1940 | word64 lv = (word64) *ap++; |
f24b7b69 JSC |
1941 | if (*s == 'b') |
1942 | callback->printf_filtered(callback,"<binary not supported>"); | |
1943 | else { | |
1944 | sprintf(tmp,"%%%s%c",longlong ? "ll" : "",*s); | |
1945 | if (longlong) | |
1946 | callback->printf_filtered(callback,tmp,lv); | |
1947 | else | |
1948 | callback->printf_filtered(callback,tmp,(int)lv); | |
1949 | } | |
1950 | } else if (strchr ("eEfgG", *s)) { | |
e3d12c65 DE |
1951 | #ifdef _MSC_VER /* MSVC version 2.x can't convert from uword64 directly */ |
1952 | double dbl = (double)((word64)*ap++); | |
1953 | #else | |
f24b7b69 | 1954 | double dbl = (double)*ap++; |
e3d12c65 | 1955 | #endif |
f24b7b69 JSC |
1956 | sprintf(tmp,"%%%d.%d%c",width,trunc,*s); |
1957 | callback->printf_filtered(callback,tmp,dbl); | |
1958 | trunc = 0; | |
1959 | } | |
1960 | } | |
1961 | s++; | |
1962 | } else | |
1963 | callback->printf_filtered(callback,"%c",*s++); | |
1964 | } | |
1965 | } else | |
1966 | sim_error("Attempt to pass pointer that does not reference simulated memory"); | |
a9f7253f JSC |
1967 | } |
1968 | break; | |
1969 | ||
8bae0a0c | 1970 | default: |
53b9417e DE |
1971 | sim_warning("TODO: sim_monitor(%d) : PC = 0x%s",reason,pr_addr(IPC)); |
1972 | sim_warning("(Arguments : A0 = 0x%s : A1 = 0x%s : A2 = 0x%s : A3 = 0x%s)",pr_addr(A0),pr_addr(A1),pr_addr(A2),pr_addr(A3)); | |
8bae0a0c JSC |
1973 | break; |
1974 | } | |
1975 | return; | |
1976 | } | |
1977 | ||
7e6c297e ILT |
1978 | /* Store a word into memory. */ |
1979 | ||
1980 | static void | |
1981 | store_word (vaddr, val) | |
1982 | uword64 vaddr; | |
1983 | t_reg val; | |
1984 | { | |
1985 | uword64 paddr; | |
1986 | int uncached; | |
1987 | ||
1988 | if ((vaddr & 3) != 0) | |
1989 | SignalException (AddressStore); | |
1990 | else | |
1991 | { | |
1992 | if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, | |
1993 | isTARGET, isREAL)) | |
1994 | { | |
1995 | const uword64 mask = 7; | |
1996 | uword64 memval; | |
1997 | unsigned int byte; | |
1998 | ||
1999 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)); | |
2000 | byte = (vaddr & mask) ^ (BigEndianCPU << 2); | |
2001 | memval = ((uword64) val) << (8 * byte); | |
53b9417e | 2002 | StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, |
7e6c297e ILT |
2003 | isREAL); |
2004 | } | |
2005 | } | |
2006 | } | |
2007 | ||
2008 | /* Load a word from memory. */ | |
2009 | ||
2010 | static t_reg | |
2011 | load_word (vaddr) | |
2012 | uword64 vaddr; | |
2013 | { | |
2014 | if ((vaddr & 3) != 0) | |
2015 | SignalException (AddressLoad); | |
2016 | else | |
2017 | { | |
2018 | uword64 paddr; | |
2019 | int uncached; | |
2020 | ||
2021 | if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, | |
2022 | isTARGET, isREAL)) | |
2023 | { | |
2024 | const uword64 mask = 0x7; | |
2025 | const unsigned int reverse = ReverseEndian ? 1 : 0; | |
2026 | const unsigned int bigend = BigEndianCPU ? 1 : 0; | |
2027 | uword64 memval; | |
2028 | unsigned int byte; | |
2029 | ||
2030 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2)); | |
53b9417e | 2031 | LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr, |
7e6c297e ILT |
2032 | isDATA, isREAL); |
2033 | byte = (vaddr & mask) ^ (bigend << 2); | |
2034 | return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32); | |
2035 | } | |
2036 | } | |
2037 | ||
2038 | return 0; | |
2039 | } | |
2040 | ||
2041 | /* Simulate the mips16 entry and exit pseudo-instructions. These | |
2042 | would normally be handled by the reserved instruction exception | |
2043 | code, but for ease of simulation we just handle them directly. */ | |
2044 | ||
2045 | static void | |
2046 | mips16_entry (insn) | |
2047 | unsigned int insn; | |
2048 | { | |
2049 | int aregs, sregs, rreg; | |
2050 | ||
53b9417e DE |
2051 | #ifdef DEBUG |
2052 | printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn); | |
2053 | #endif /* DEBUG */ | |
2054 | ||
7e6c297e ILT |
2055 | aregs = (insn & 0x700) >> 8; |
2056 | sregs = (insn & 0x0c0) >> 6; | |
2057 | rreg = (insn & 0x020) >> 5; | |
2058 | ||
da0bce9c ILT |
2059 | /* This should be checked by the caller. */ |
2060 | if (sregs == 3) | |
7e6c297e ILT |
2061 | abort (); |
2062 | ||
da0bce9c | 2063 | if (aregs < 5) |
7e6c297e ILT |
2064 | { |
2065 | int i; | |
2066 | t_reg tsp; | |
2067 | ||
2068 | /* This is the entry pseudo-instruction. */ | |
2069 | ||
2070 | for (i = 0; i < aregs; i++) | |
2071 | store_word ((uword64) (SP + 4 * i), registers[i + 4]); | |
2072 | ||
2073 | tsp = SP; | |
2074 | SP -= 32; | |
2075 | ||
2076 | if (rreg) | |
2077 | { | |
2078 | tsp -= 4; | |
2079 | store_word ((uword64) tsp, RA); | |
2080 | } | |
2081 | ||
2082 | for (i = 0; i < sregs; i++) | |
2083 | { | |
2084 | tsp -= 4; | |
2085 | store_word ((uword64) tsp, registers[16 + i]); | |
2086 | } | |
2087 | } | |
2088 | else | |
2089 | { | |
2090 | int i; | |
2091 | t_reg tsp; | |
2092 | ||
2093 | /* This is the exit pseudo-instruction. */ | |
2094 | ||
2095 | tsp = SP + 32; | |
2096 | ||
2097 | if (rreg) | |
2098 | { | |
2099 | tsp -= 4; | |
2100 | RA = load_word ((uword64) tsp); | |
2101 | } | |
2102 | ||
2103 | for (i = 0; i < sregs; i++) | |
2104 | { | |
2105 | tsp -= 4; | |
2106 | registers[i + 16] = load_word ((uword64) tsp); | |
2107 | } | |
2108 | ||
2109 | SP += 32; | |
2110 | ||
da0bce9c ILT |
2111 | if (aregs == 5) |
2112 | { | |
2113 | FGR[0] = WORD64LO (GPR[4]); | |
2114 | fpr_state[0] = fmt_uninterpreted; | |
2115 | } | |
2116 | else if (aregs == 6) | |
2117 | { | |
2118 | FGR[0] = WORD64LO (GPR[5]); | |
2119 | FGR[1] = WORD64LO (GPR[4]); | |
2120 | fpr_state[0] = fmt_uninterpreted; | |
2121 | fpr_state[1] = fmt_uninterpreted; | |
2122 | } | |
2123 | ||
7e6c297e ILT |
2124 | PC = RA; |
2125 | } | |
2126 | } | |
2127 | ||
f24b7b69 | 2128 | void |
e3d12c65 | 2129 | sim_warning(char *fmt,...) |
f24b7b69 | 2130 | { |
6429b296 | 2131 | char buf[256]; |
f24b7b69 | 2132 | va_list ap; |
6429b296 JW |
2133 | |
2134 | va_start (ap,fmt); | |
2135 | vsprintf (buf, fmt, ap); | |
2136 | va_end (ap); | |
2137 | ||
f24b7b69 | 2138 | if (logfh != NULL) { |
6429b296 JW |
2139 | fprintf(logfh,"SIM Warning: %s\n", buf); |
2140 | } else { | |
2141 | callback->printf_filtered(callback,"SIM Warning: %s\n", buf); | |
f24b7b69 | 2142 | } |
6429b296 JW |
2143 | /* This used to call SignalException with a SimulatorFault, but that causes |
2144 | the simulator to exit, and that is inappropriate for a warning. */ | |
f24b7b69 JSC |
2145 | return; |
2146 | } | |
2147 | ||
8bae0a0c | 2148 | void |
e3d12c65 | 2149 | sim_error(char *fmt,...) |
8bae0a0c | 2150 | { |
6429b296 | 2151 | char buf[256]; |
8bae0a0c | 2152 | va_list ap; |
6429b296 JW |
2153 | |
2154 | va_start (ap,fmt); | |
2155 | vsprintf (buf, fmt, ap); | |
2156 | va_end (ap); | |
2157 | ||
2158 | callback->printf_filtered(callback,"SIM Error: %s", buf); | |
2159 | SignalException (SimulatorFault, buf); | |
8bae0a0c JSC |
2160 | return; |
2161 | } | |
2162 | ||
2163 | static unsigned int | |
2164 | power2(value) | |
2165 | unsigned int value; | |
2166 | { | |
2167 | int loop,tmp; | |
2168 | ||
2169 | /* Round *UP* to the nearest power-of-2 if not already one */ | |
2170 | if (value != (value & ~(value - 1))) { | |
2171 | for (tmp = value, loop = 0; (tmp != 0); loop++) | |
2172 | tmp >>= 1; | |
2173 | value = (1 << loop); | |
2174 | } | |
2175 | ||
2176 | return(value); | |
2177 | } | |
2178 | ||
2179 | static long | |
2180 | getnum(value) | |
2181 | char *value; | |
2182 | { | |
2183 | long num; | |
2184 | char *end; | |
2185 | ||
2186 | num = strtol(value,&end,10); | |
2187 | if (end == value) | |
2188 | callback->printf_filtered(callback,"Warning: Invalid number \"%s\" ignored, using zero\n",value); | |
2189 | else { | |
2190 | if (*end && ((tolower(*end) == 'k') || (tolower(*end) == 'm'))) { | |
2191 | if (tolower(*end) == 'k') | |
2192 | num *= (1 << 10); | |
2193 | else | |
2194 | num *= (1 << 20); | |
2195 | end++; | |
2196 | } | |
2197 | if (*end) | |
2198 | callback->printf_filtered(callback,"Warning: Spurious characters \"%s\" at end of number ignored\n",end); | |
2199 | } | |
2200 | ||
2201 | return(num); | |
2202 | } | |
2203 | ||
2204 | /*-- trace support ----------------------------------------------------------*/ | |
2205 | ||
2206 | /* The TRACE support is provided (if required) in the memory accessing | |
2207 | routines. Since we are also providing the architecture specific | |
2208 | features, the architecture simulation code can also deal with | |
2209 | notifying the TRACE world of cache flushes, etc. Similarly we do | |
2210 | not need to provide profiling support in the simulator engine, | |
2211 | since we can sample in the instruction fetch control loop. By | |
2212 | defining the TRACE manifest, we add tracing as a run-time | |
2213 | option. */ | |
2214 | ||
2215 | #if defined(TRACE) | |
2216 | /* Tracing by default produces "din" format (as required by | |
2217 | dineroIII). Each line of such a trace file *MUST* have a din label | |
2218 | and address field. The rest of the line is ignored, so comments can | |
2219 | be included if desired. The first field is the label which must be | |
2220 | one of the following values: | |
2221 | ||
2222 | 0 read data | |
2223 | 1 write data | |
2224 | 2 instruction fetch | |
2225 | 3 escape record (treated as unknown access type) | |
2226 | 4 escape record (causes cache flush) | |
2227 | ||
2228 | The address field is a 32bit (lower-case) hexadecimal address | |
2229 | value. The address should *NOT* be preceded by "0x". | |
2230 | ||
2231 | The size of the memory transfer is not important when dealing with | |
2232 | cache lines (as long as no more than a cache line can be | |
2233 | transferred in a single operation :-), however more information | |
2234 | could be given following the dineroIII requirement to allow more | |
2235 | complete memory and cache simulators to provide better | |
2236 | results. i.e. the University of Pisa has a cache simulator that can | |
2237 | also take bus size and speed as (variable) inputs to calculate | |
2238 | complete system performance (a much more useful ability when trying | |
2239 | to construct an end product, rather than a processor). They | |
2240 | currently have an ARM version of their tool called ChARM. */ | |
2241 | ||
e3d12c65 | 2242 | |
8bae0a0c | 2243 | static |
e3d12c65 | 2244 | void dotrace(FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...) |
8bae0a0c JSC |
2245 | { |
2246 | if (state & simTRACE) { | |
2247 | va_list ap; | |
53b9417e | 2248 | fprintf(tracefh,"%d %s ; width %d ; ", |
6429b296 | 2249 | type, |
53b9417e DE |
2250 | pr_addr(address), |
2251 | width); | |
8bae0a0c | 2252 | va_start(ap,comment); |
6429b296 | 2253 | vfprintf(tracefh,comment,ap); |
8bae0a0c JSC |
2254 | va_end(ap); |
2255 | fprintf(tracefh,"\n"); | |
2256 | } | |
2257 | /* NOTE: Since the "din" format will only accept 32bit addresses, and | |
2258 | we may be generating 64bit ones, we should put the hi-32bits of the | |
2259 | address into the comment field. */ | |
2260 | ||
2261 | /* TODO: Provide a buffer for the trace lines. We can then avoid | |
2262 | performing writes until the buffer is filled, or the file is | |
2263 | being closed. */ | |
2264 | ||
2265 | /* NOTE: We could consider adding a comment field to the "din" file | |
2266 | produced using type 3 markers (unknown access). This would then | |
2267 | allow information about the program that the "din" is for, and | |
2268 | the MIPs world that was being simulated, to be placed into the | |
2269 | trace file. */ | |
2270 | ||
2271 | return; | |
2272 | } | |
2273 | #endif /* TRACE */ | |
2274 | ||
f7481d45 JSC |
2275 | /*---------------------------------------------------------------------------*/ |
2276 | /*-- host<->target transfers ------------------------------------------------*/ | |
2277 | /*---------------------------------------------------------------------------*/ | |
2278 | /* The following routines allow conditionals to be avoided during the | |
2279 | simulation, at the cost of increasing the image and source size. */ | |
2280 | ||
2281 | static unsigned int | |
e3d12c65 | 2282 | xfer_direct_word(unsigned char *memory) |
f7481d45 JSC |
2283 | { |
2284 | return *((unsigned int *)memory); | |
2285 | } | |
2286 | ||
2287 | static uword64 | |
e3d12c65 | 2288 | xfer_direct_long(unsigned char *memory) |
f7481d45 JSC |
2289 | { |
2290 | return *((uword64 *)memory); | |
2291 | } | |
2292 | ||
2293 | static unsigned int | |
e3d12c65 | 2294 | swap_direct_word(unsigned int data) |
f7481d45 JSC |
2295 | { |
2296 | return data; | |
2297 | } | |
2298 | ||
2299 | static uword64 | |
e3d12c65 | 2300 | swap_direct_long(uword64 data) |
f7481d45 JSC |
2301 | { |
2302 | return data; | |
2303 | } | |
2304 | ||
2305 | static unsigned int | |
e3d12c65 | 2306 | xfer_big_word(unsigned char *memory) |
f7481d45 JSC |
2307 | { |
2308 | return ((memory[0] << 24) | (memory[1] << 16) | (memory[2] << 8) | memory[3]); | |
2309 | } | |
2310 | ||
2311 | static uword64 | |
e3d12c65 | 2312 | xfer_big_long(unsigned char *memory) |
f7481d45 JSC |
2313 | { |
2314 | return (((uword64)memory[0] << 56) | ((uword64)memory[1] << 48) | |
2315 | | ((uword64)memory[2] << 40) | ((uword64)memory[3] << 32) | |
e3d12c65 DE |
2316 | | ((uword64)memory[4] << 24) | ((uword64)memory[5] << 16) |
2317 | | ((uword64)memory[6] << 8) | ((uword64)memory[7])); | |
f7481d45 JSC |
2318 | } |
2319 | ||
2320 | static unsigned int | |
e3d12c65 | 2321 | xfer_little_word(unsigned char *memory) |
f7481d45 JSC |
2322 | { |
2323 | return ((memory[3] << 24) | (memory[2] << 16) | (memory[1] << 8) | memory[0]); | |
2324 | } | |
2325 | ||
2326 | static uword64 | |
e3d12c65 | 2327 | xfer_little_long(unsigned char *memory) |
f7481d45 JSC |
2328 | { |
2329 | return (((uword64)memory[7] << 56) | ((uword64)memory[6] << 48) | |
2330 | | ((uword64)memory[5] << 40) | ((uword64)memory[4] << 32) | |
e3d12c65 DE |
2331 | | ((uword64)memory[3] << 24) | ((uword64)memory[2] << 16) |
2332 | | ((uword64)memory[1] << 8) | (uword64)memory[0]); | |
f7481d45 JSC |
2333 | } |
2334 | ||
2335 | static unsigned int | |
e3d12c65 | 2336 | swap_word(unsigned int data) |
f7481d45 JSC |
2337 | { |
2338 | unsigned int result; | |
aaff8437 ILT |
2339 | result = (((data & 0xff) << 24) | ((data & 0xff00) << 8) |
2340 | | ((data >> 8) & 0xff00) | ((data >> 24) & 0xff)); | |
2341 | return result; | |
f7481d45 JSC |
2342 | } |
2343 | ||
2344 | static uword64 | |
e3d12c65 | 2345 | swap_long(uword64 data) |
f7481d45 JSC |
2346 | { |
2347 | unsigned int tmphi = WORD64HI(data); | |
2348 | unsigned int tmplo = WORD64LO(data); | |
2349 | tmphi = swap_word(tmphi); | |
2350 | tmplo = swap_word(tmplo); | |
2351 | /* Now swap the HI and LO parts */ | |
2352 | return SET64LO(tmphi) | SET64HI(tmplo); | |
2353 | } | |
2354 | ||
8bae0a0c JSC |
2355 | /*---------------------------------------------------------------------------*/ |
2356 | /*-- simulator engine -------------------------------------------------------*/ | |
2357 | /*---------------------------------------------------------------------------*/ | |
2358 | ||
aaff8437 ILT |
2359 | static void |
2360 | set_endianness () | |
2361 | { | |
2362 | /* In reality this check should be performed at various points | |
2363 | within the simulation, since it is possible to change the | |
2364 | endianness of user programs. However, we perform the check here | |
2365 | to ensure that the start-of-day values agree. */ | |
9d52bcb7 | 2366 | if (big_endian_p) |
aaff8437 ILT |
2367 | state |= simBE; |
2368 | ||
2369 | /* ??? This is a lot more code than is necessary to solve the problem. | |
2370 | It would be simpler to handle this like the SH simulator. */ | |
2371 | if (!ByteSwapMem) { | |
2372 | host_read_word = xfer_direct_word; | |
2373 | host_read_long = xfer_direct_long; | |
2374 | host_swap_word = swap_direct_word; | |
2375 | host_swap_long = swap_direct_long; | |
2376 | } else if (state & simHOSTBE) { | |
2377 | host_read_word = xfer_little_word; | |
2378 | host_read_long = xfer_little_long; | |
2379 | host_swap_word = swap_word; | |
2380 | host_swap_long = swap_long; | |
2381 | } else { /* HOST little-endian */ | |
2382 | host_read_word = xfer_big_word; | |
2383 | host_read_long = xfer_big_long; | |
2384 | host_swap_word = swap_word; | |
2385 | host_swap_long = swap_long; | |
2386 | } | |
2387 | } | |
2388 | ||
8bae0a0c JSC |
2389 | static void |
2390 | ColdReset() | |
2391 | { | |
2392 | /* RESET: Fixed PC address: */ | |
e871dd18 | 2393 | PC = (((uword64)0xFFFFFFFF<<32) | 0xBFC00000); |
8bae0a0c JSC |
2394 | /* The reset vector address is in the unmapped, uncached memory space. */ |
2395 | ||
2396 | SR &= ~(status_SR | status_TS | status_RP); | |
2397 | SR |= (status_ERL | status_BEV); | |
8bae0a0c JSC |
2398 | |
2399 | #if defined(HASFPU) && (GPRLEN == (64)) | |
2400 | /* Cheat and allow access to the complete register set immediately: */ | |
2401 | SR |= status_FR; /* 64bit registers */ | |
2402 | #endif /* HASFPU and 64bit FP registers */ | |
2403 | ||
2404 | /* Ensure that any instructions with pending register updates are | |
2405 | cleared: */ | |
2406 | { | |
2407 | int loop; | |
2408 | for (loop = 0; (loop < PSLOTS); loop++) | |
2409 | pending_slot_reg[loop] = (LAST_EMBED_REGNUM + 1); | |
2410 | pending_in = pending_out = pending_total = 0; | |
2411 | } | |
2412 | ||
2413 | #if defined(HASFPU) | |
2414 | /* Initialise the FPU registers to the unknown state */ | |
2415 | { | |
2416 | int rn; | |
2417 | for (rn = 0; (rn < 32); rn++) | |
2418 | fpr_state[rn] = fmt_uninterpreted; | |
2419 | } | |
2420 | #endif /* HASFPU */ | |
2421 | ||
2422 | return; | |
2423 | } | |
2424 | ||
2425 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
2426 | /* Translate a virtual address to a physical address and cache | |
2427 | coherence algorithm describing the mechanism used to resolve the | |
2428 | memory reference. Given the virtual address vAddr, and whether the | |
2429 | reference is to Instructions ot Data (IorD), find the corresponding | |
2430 | physical address (pAddr) and the cache coherence algorithm (CCA) | |
2431 | used to resolve the reference. If the virtual address is in one of | |
2432 | the unmapped address spaces the physical address and the CCA are | |
2433 | determined directly by the virtual address. If the virtual address | |
2434 | is in one of the mapped address spaces then the TLB is used to | |
2435 | determine the physical address and access type; if the required | |
2436 | translation is not present in the TLB or the desired access is not | |
2437 | permitted the function fails and an exception is taken. | |
2438 | ||
2439 | NOTE: This function is extended to return an exception state. This, | |
2440 | along with the exception generation is used to notify whether a | |
2441 | valid address translation occured */ | |
2442 | ||
2443 | static int | |
2444 | AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) | |
e871dd18 | 2445 | uword64 vAddr; |
8bae0a0c JSC |
2446 | int IorD; |
2447 | int LorS; | |
e871dd18 | 2448 | uword64 *pAddr; |
8bae0a0c JSC |
2449 | int *CCA; |
2450 | int host; | |
2451 | int raw; | |
2452 | { | |
2453 | int res = -1; /* TRUE : Assume good return */ | |
2454 | ||
2455 | #ifdef DEBUG | |
53b9417e | 2456 | callback->printf_filtered(callback,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD")); |
8bae0a0c JSC |
2457 | #endif |
2458 | ||
2459 | /* Check that the address is valid for this memory model */ | |
2460 | ||
2461 | /* For a simple (flat) memory model, we simply pass virtual | |
2462 | addressess through (mostly) unchanged. */ | |
2463 | vAddr &= 0xFFFFFFFF; | |
a9f7253f JSC |
2464 | |
2465 | /* Treat the kernel memory spaces identically for the moment: */ | |
2466 | if ((membank_base == K1BASE) && (vAddr >= K0BASE) && (vAddr < (K0BASE + K0SIZE))) | |
2467 | vAddr += (K1BASE - K0BASE); | |
2468 | ||
2469 | /* Also assume that the K1BASE memory wraps. This is required to | |
2470 | allow the PMON run-time __sizemem() routine to function (without | |
2471 | having to provide exception simulation). NOTE: A kludge to work | |
2472 | around the fact that the monitor memory is currently held in the | |
2473 | K1BASE space. */ | |
2474 | if (((vAddr < monitor_base) || (vAddr >= (monitor_base + monitor_size))) && (vAddr >= K1BASE && vAddr < (K1BASE + K1SIZE))) | |
2475 | vAddr = (K1BASE | (vAddr & (membank_size - 1))); | |
2476 | ||
8bae0a0c JSC |
2477 | *pAddr = vAddr; /* default for isTARGET */ |
2478 | *CCA = Uncached; /* not used for isHOST */ | |
2479 | ||
2480 | /* NOTE: This is a duplicate of the code that appears in the | |
2481 | LoadMemory and StoreMemory functions. They should be merged into | |
2482 | a single function (that can be in-lined if required). */ | |
2483 | if ((vAddr >= membank_base) && (vAddr < (membank_base + membank_size))) { | |
2484 | if (host) | |
2485 | *pAddr = (int)&membank[((unsigned int)(vAddr - membank_base) & (membank_size - 1))]; | |
2486 | } else if ((vAddr >= monitor_base) && (vAddr < (monitor_base + monitor_size))) { | |
2487 | if (host) | |
2488 | *pAddr = (int)&monitor[((unsigned int)(vAddr - monitor_base) & (monitor_size - 1))]; | |
2489 | } else { | |
6429b296 | 2490 | #ifdef DEBUG |
53b9417e | 2491 | sim_warning("Failed: AddressTranslation(0x%s,%s,%s,...) IPC = 0x%s",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "isSTORE" : "isLOAD"),pr_addr(IPC)); |
8bae0a0c JSC |
2492 | #endif /* DEBUG */ |
2493 | res = 0; /* AddressTranslation has failed */ | |
e3d12c65 | 2494 | *pAddr = (SIM_ADDR)-1; |
8bae0a0c JSC |
2495 | if (!raw) /* only generate exceptions on real memory transfers */ |
2496 | SignalException((LorS == isSTORE) ? AddressStore : AddressLoad); | |
6429b296 | 2497 | #ifdef DEBUG |
8bae0a0c | 2498 | else |
6429b296 JW |
2499 | /* This is a normal occurance during gdb operation, for instance trying |
2500 | to print parameters at function start before they have been setup, | |
2501 | and hence we should not print a warning except when debugging the | |
2502 | simulator. */ | |
53b9417e | 2503 | sim_warning("AddressTranslation for %s %s from 0x%s failed",(IorD ? "data" : "instruction"),(LorS ? "store" : "load"),pr_addr(vAddr)); |
6429b296 | 2504 | #endif |
8bae0a0c JSC |
2505 | } |
2506 | ||
2507 | return(res); | |
2508 | } | |
2509 | ||
2510 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
2511 | /* Prefetch data from memory. Prefetch is an advisory instruction for | |
2512 | which an implementation specific action is taken. The action taken | |
2513 | may increase performance, but must not change the meaning of the | |
2514 | program, or alter architecturally-visible state. */ | |
2515 | static void | |
2516 | Prefetch(CCA,pAddr,vAddr,DATA,hint) | |
2517 | int CCA; | |
e871dd18 JSC |
2518 | uword64 pAddr; |
2519 | uword64 vAddr; | |
8bae0a0c JSC |
2520 | int DATA; |
2521 | int hint; | |
2522 | { | |
2523 | #ifdef DEBUG | |
53b9417e | 2524 | callback->printf_filtered(callback,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint); |
8bae0a0c JSC |
2525 | #endif /* DEBUG */ |
2526 | ||
2527 | /* For our simple memory model we do nothing */ | |
2528 | return; | |
2529 | } | |
2530 | ||
2531 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
2532 | /* Load a value from memory. Use the cache and main memory as | |
2533 | specified in the Cache Coherence Algorithm (CCA) and the sort of | |
2534 | access (IorD) to find the contents of AccessLength memory bytes | |
2535 | starting at physical location pAddr. The data is returned in the | |
2536 | fixed width naturally-aligned memory element (MemElem). The | |
2537 | low-order two (or three) bits of the address and the AccessLength | |
2538 | indicate which of the bytes within MemElem needs to be given to the | |
2539 | processor. If the memory access type of the reference is uncached | |
2540 | then only the referenced bytes are read from memory and valid | |
2541 | within the memory element. If the access type is cached, and the | |
2542 | data is not present in cache, an implementation specific size and | |
2543 | alignment block of memory is read and loaded into the cache to | |
2544 | satisfy a load reference. At a minimum, the block is the entire | |
2545 | memory element. */ | |
53b9417e DE |
2546 | static void |
2547 | LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) | |
2548 | uword64* memvalp; | |
2549 | uword64* memval1p; | |
8bae0a0c JSC |
2550 | int CCA; |
2551 | int AccessLength; | |
e871dd18 JSC |
2552 | uword64 pAddr; |
2553 | uword64 vAddr; | |
8bae0a0c JSC |
2554 | int IorD; |
2555 | int raw; | |
2556 | { | |
e871dd18 | 2557 | uword64 value; |
53b9417e | 2558 | uword64 value1; |
8bae0a0c JSC |
2559 | |
2560 | #ifdef DEBUG | |
2561 | if (membank == NULL) | |
53b9417e | 2562 | callback->printf_filtered(callback,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(raw ? "isRAW" : "isREAL")); |
8bae0a0c JSC |
2563 | #endif /* DEBUG */ |
2564 | ||
2565 | #if defined(WARN_MEM) | |
2566 | if (CCA != uncached) | |
f24b7b69 | 2567 | sim_warning("LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)",CCA); |
8bae0a0c JSC |
2568 | |
2569 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) { | |
2570 | /* In reality this should be a Bus Error */ | |
53b9417e | 2571 | sim_error("AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr)); |
8bae0a0c JSC |
2572 | } |
2573 | #endif /* WARN_MEM */ | |
2574 | ||
2575 | /* Decide which physical memory locations are being dealt with. At | |
2576 | this point we should be able to split the pAddr bits into the | |
2577 | relevant address map being simulated. If the "raw" variable is | |
2578 | set, the memory read being performed should *NOT* update any I/O | |
2579 | state or affect the CPU state. This also includes avoiding | |
2580 | affecting statistics gathering. */ | |
2581 | ||
2582 | /* If instruction fetch then we need to check that the two lo-order | |
2583 | bits are zero, otherwise raise a InstructionFetch exception: */ | |
6429b296 JW |
2584 | if ((IorD == isINSTRUCTION) |
2585 | && ((pAddr & 0x3) != 0) | |
2586 | && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0))) | |
8bae0a0c JSC |
2587 | SignalException(InstructionFetch); |
2588 | else { | |
2589 | unsigned int index; | |
2590 | unsigned char *mem = NULL; | |
2591 | ||
8bae0a0c JSC |
2592 | #if defined(TRACE) |
2593 | if (!raw) | |
2594 | dotrace(tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); | |
2595 | #endif /* TRACE */ | |
2596 | ||
2597 | /* NOTE: Quicker methods of decoding the address space can be used | |
2598 | when a real memory map is being simulated (i.e. using hi-order | |
2599 | address bits to select device). */ | |
2600 | if ((pAddr >= membank_base) && (pAddr < (membank_base + membank_size))) { | |
2601 | index = ((unsigned int)(pAddr - membank_base) & (membank_size - 1)); | |
2602 | mem = membank; | |
2603 | } else if ((pAddr >= monitor_base) && (pAddr < (monitor_base + monitor_size))) { | |
2604 | index = ((unsigned int)(pAddr - monitor_base) & (monitor_size - 1)); | |
2605 | mem = monitor; | |
2606 | } | |
2607 | if (mem == NULL) | |
53b9417e | 2608 | sim_error("Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr)); |
8bae0a0c JSC |
2609 | else { |
2610 | /* If we obtained the endianness of the host, and it is the same | |
2611 | as the target memory system we can optimise the memory | |
2612 | accesses. However, without that information we must perform | |
2613 | slow transfer, and hope that the compiler optimisation will | |
2614 | merge successive loads. */ | |
2615 | value = 0; /* no data loaded yet */ | |
53b9417e | 2616 | value1 = 0; |
8bae0a0c JSC |
2617 | |
2618 | /* In reality we should always be loading a doubleword value (or | |
2619 | word value in 32bit memory worlds). The external code then | |
2620 | extracts the required bytes. However, to keep performance | |
2621 | high we only load the required bytes into the relevant | |
2622 | slots. */ | |
0049ba7a | 2623 | if (BigEndianMem) |
8bae0a0c | 2624 | switch (AccessLength) { /* big-endian memory */ |
53b9417e DE |
2625 | case AccessLength_QUADWORD : |
2626 | value1 |= ((uword64)mem[index++] << 56); | |
2627 | case 14: /* AccessLength is one less than datalen */ | |
2628 | value1 |= ((uword64)mem[index++] << 48); | |
2629 | case 13: | |
2630 | value1 |= ((uword64)mem[index++] << 40); | |
2631 | case 12: | |
2632 | value1 |= ((uword64)mem[index++] << 32); | |
2633 | case 11: | |
2634 | value1 |= ((unsigned int)mem[index++] << 24); | |
2635 | case 10: | |
2636 | value1 |= ((unsigned int)mem[index++] << 16); | |
2637 | case 9: | |
2638 | value1 |= ((unsigned int)mem[index++] << 8); | |
2639 | case 8: | |
2640 | value1 |= mem[index]; | |
2641 | ||
8bae0a0c | 2642 | case AccessLength_DOUBLEWORD : |
e871dd18 | 2643 | value |= ((uword64)mem[index++] << 56); |
8bae0a0c | 2644 | case AccessLength_SEPTIBYTE : |
e871dd18 | 2645 | value |= ((uword64)mem[index++] << 48); |
8bae0a0c | 2646 | case AccessLength_SEXTIBYTE : |
e871dd18 | 2647 | value |= ((uword64)mem[index++] << 40); |
8bae0a0c | 2648 | case AccessLength_QUINTIBYTE : |
e871dd18 | 2649 | value |= ((uword64)mem[index++] << 32); |
8bae0a0c JSC |
2650 | case AccessLength_WORD : |
2651 | value |= ((unsigned int)mem[index++] << 24); | |
2652 | case AccessLength_TRIPLEBYTE : | |
2653 | value |= ((unsigned int)mem[index++] << 16); | |
2654 | case AccessLength_HALFWORD : | |
2655 | value |= ((unsigned int)mem[index++] << 8); | |
2656 | case AccessLength_BYTE : | |
2657 | value |= mem[index]; | |
2658 | break; | |
2659 | } | |
2660 | else { | |
2661 | index += (AccessLength + 1); | |
2662 | switch (AccessLength) { /* little-endian memory */ | |
53b9417e DE |
2663 | case AccessLength_QUADWORD : |
2664 | value1 |= ((uword64)mem[--index] << 56); | |
2665 | case 14: /* AccessLength is one less than datalen */ | |
2666 | value1 |= ((uword64)mem[--index] << 48); | |
2667 | case 13: | |
2668 | value1 |= ((uword64)mem[--index] << 40); | |
2669 | case 12: | |
2670 | value1 |= ((uword64)mem[--index] << 32); | |
2671 | case 11: | |
2672 | value1 |= ((uword64)mem[--index] << 24); | |
2673 | case 10: | |
2674 | value1 |= ((uword64)mem[--index] << 16); | |
2675 | case 9: | |
2676 | value1 |= ((uword64)mem[--index] << 8); | |
2677 | case 8: | |
2678 | value1 |= ((uword64)mem[--index] << 0); | |
2679 | ||
8bae0a0c | 2680 | case AccessLength_DOUBLEWORD : |
e871dd18 | 2681 | value |= ((uword64)mem[--index] << 56); |
8bae0a0c | 2682 | case AccessLength_SEPTIBYTE : |
e871dd18 | 2683 | value |= ((uword64)mem[--index] << 48); |
8bae0a0c | 2684 | case AccessLength_SEXTIBYTE : |
e871dd18 | 2685 | value |= ((uword64)mem[--index] << 40); |
8bae0a0c | 2686 | case AccessLength_QUINTIBYTE : |
e871dd18 | 2687 | value |= ((uword64)mem[--index] << 32); |
8bae0a0c | 2688 | case AccessLength_WORD : |
e871dd18 | 2689 | value |= ((uword64)mem[--index] << 24); |
8bae0a0c | 2690 | case AccessLength_TRIPLEBYTE : |
e871dd18 | 2691 | value |= ((uword64)mem[--index] << 16); |
8bae0a0c | 2692 | case AccessLength_HALFWORD : |
e871dd18 | 2693 | value |= ((uword64)mem[--index] << 8); |
8bae0a0c | 2694 | case AccessLength_BYTE : |
e871dd18 | 2695 | value |= ((uword64)mem[--index] << 0); |
8bae0a0c JSC |
2696 | break; |
2697 | } | |
2698 | } | |
2699 | ||
2700 | #ifdef DEBUG | |
53b9417e | 2701 | printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n", |
87e43259 | 2702 | (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value)); |
8bae0a0c JSC |
2703 | #endif /* DEBUG */ |
2704 | ||
2705 | /* TODO: We could try and avoid the shifts when dealing with raw | |
2706 | memory accesses. This would mean updating the LoadMemory and | |
2707 | StoreMemory routines to avoid shifting the data before | |
2708 | returning or using it. */ | |
53b9417e DE |
2709 | if (AccessLength <= AccessLength_DOUBLEWORD) { |
2710 | if (!raw) { /* do nothing for raw accessess */ | |
2711 | if (BigEndianMem) | |
2712 | value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
2713 | else /* little-endian only needs to be shifted up to the correct byte offset */ | |
2714 | value <<= ((pAddr & LOADDRMASK) * 8); | |
2715 | } | |
8bae0a0c JSC |
2716 | } |
2717 | ||
2718 | #ifdef DEBUG | |
53b9417e | 2719 | printf("DBG: LoadMemory() : shifted value = 0x%s%s\n", |
87e43259 | 2720 | pr_uword64(value1),pr_uword64(value)); |
e871dd18 | 2721 | #endif /* DEBUG */ |
8bae0a0c JSC |
2722 | } |
2723 | } | |
2724 | ||
53b9417e DE |
2725 | *memvalp = value; |
2726 | if (memval1p) *memval1p = value1; | |
8bae0a0c JSC |
2727 | } |
2728 | ||
53b9417e | 2729 | |
8bae0a0c JSC |
2730 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */ |
2731 | /* Store a value to memory. The specified data is stored into the | |
2732 | physical location pAddr using the memory hierarchy (data caches and | |
2733 | main memory) as specified by the Cache Coherence Algorithm | |
2734 | (CCA). The MemElem contains the data for an aligned, fixed-width | |
2735 | memory element (word for 32-bit processors, doubleword for 64-bit | |
2736 | processors), though only the bytes that will actually be stored to | |
2737 | memory need to be valid. The low-order two (or three) bits of pAddr | |
2738 | and the AccessLength field indicates which of the bytes within the | |
2739 | MemElem data should actually be stored; only these bytes in memory | |
2740 | will be changed. */ | |
53b9417e | 2741 | |
8bae0a0c | 2742 | static void |
53b9417e | 2743 | StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) |
8bae0a0c JSC |
2744 | int CCA; |
2745 | int AccessLength; | |
e871dd18 | 2746 | uword64 MemElem; |
53b9417e | 2747 | uword64 MemElem1; /* High order 64 bits */ |
e871dd18 JSC |
2748 | uword64 pAddr; |
2749 | uword64 vAddr; | |
8bae0a0c JSC |
2750 | int raw; |
2751 | { | |
2752 | #ifdef DEBUG | |
87e43259 | 2753 | callback->printf_filtered(callback,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s,%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr),(raw ? "isRAW" : "isREAL")); |
8bae0a0c JSC |
2754 | #endif /* DEBUG */ |
2755 | ||
2756 | #if defined(WARN_MEM) | |
2757 | if (CCA != uncached) | |
f24b7b69 | 2758 | sim_warning("StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)",CCA); |
8bae0a0c JSC |
2759 | |
2760 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
53b9417e | 2761 | sim_error("AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr)); |
8bae0a0c JSC |
2762 | #endif /* WARN_MEM */ |
2763 | ||
2764 | #if defined(TRACE) | |
2765 | if (!raw) | |
2766 | dotrace(tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store"); | |
2767 | #endif /* TRACE */ | |
2768 | ||
2769 | /* See the comments in the LoadMemory routine about optimising | |
2770 | memory accesses. Also if we wanted to make the simulator smaller, | |
2771 | we could merge a lot of this code with the LoadMemory | |
2772 | routine. However, this would slow the simulator down with | |
2773 | run-time conditionals. */ | |
2774 | { | |
2775 | unsigned int index; | |
2776 | unsigned char *mem = NULL; | |
2777 | ||
2778 | if ((pAddr >= membank_base) && (pAddr < (membank_base + membank_size))) { | |
2779 | index = ((unsigned int)(pAddr - membank_base) & (membank_size - 1)); | |
2780 | mem = membank; | |
2781 | } else if ((pAddr >= monitor_base) && (pAddr < (monitor_base + monitor_size))) { | |
2782 | index = ((unsigned int)(pAddr - monitor_base) & (monitor_size - 1)); | |
2783 | mem = monitor; | |
2784 | } | |
2785 | ||
2786 | if (mem == NULL) | |
53b9417e | 2787 | sim_error("Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr)); |
8bae0a0c JSC |
2788 | else { |
2789 | int shift = 0; | |
2790 | ||
2791 | #ifdef DEBUG | |
87e43259 | 2792 | printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c JSC |
2793 | #endif /* DEBUG */ |
2794 | ||
53b9417e DE |
2795 | if (AccessLength <= AccessLength_DOUBLEWORD) { |
2796 | if (BigEndianMem) { | |
2797 | if (raw) | |
2798 | shift = ((7 - AccessLength) * 8); | |
2799 | else /* real memory access */ | |
2800 | shift = ((pAddr & LOADDRMASK) * 8); | |
2801 | MemElem <<= shift; | |
2802 | } else { | |
2803 | /* no need to shift raw little-endian data */ | |
2804 | if (!raw) | |
2805 | MemElem >>= ((pAddr & LOADDRMASK) * 8); | |
2806 | } | |
8bae0a0c JSC |
2807 | } |
2808 | ||
2809 | #ifdef DEBUG | |
87e43259 | 2810 | printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c JSC |
2811 | #endif /* DEBUG */ |
2812 | ||
0049ba7a | 2813 | if (BigEndianMem) { |
8bae0a0c | 2814 | switch (AccessLength) { /* big-endian memory */ |
53b9417e DE |
2815 | case AccessLength_QUADWORD : |
2816 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
2817 | MemElem1 <<= 8; | |
2818 | case 14 : | |
2819 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
2820 | MemElem1 <<= 8; | |
2821 | case 13 : | |
2822 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
2823 | MemElem1 <<= 8; | |
2824 | case 12 : | |
2825 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
2826 | MemElem1 <<= 8; | |
2827 | case 11 : | |
2828 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
2829 | MemElem1 <<= 8; | |
2830 | case 10 : | |
2831 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
2832 | MemElem1 <<= 8; | |
2833 | case 9 : | |
2834 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
2835 | MemElem1 <<= 8; | |
2836 | case 8 : | |
2837 | mem[index++] = (unsigned char)(MemElem1 >> 56); | |
2838 | ||
8bae0a0c JSC |
2839 | case AccessLength_DOUBLEWORD : |
2840 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2841 | MemElem <<= 8; | |
2842 | case AccessLength_SEPTIBYTE : | |
2843 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2844 | MemElem <<= 8; | |
2845 | case AccessLength_SEXTIBYTE : | |
2846 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2847 | MemElem <<= 8; | |
2848 | case AccessLength_QUINTIBYTE : | |
2849 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2850 | MemElem <<= 8; | |
2851 | case AccessLength_WORD : | |
2852 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2853 | MemElem <<= 8; | |
2854 | case AccessLength_TRIPLEBYTE : | |
2855 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2856 | MemElem <<= 8; | |
2857 | case AccessLength_HALFWORD : | |
2858 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2859 | MemElem <<= 8; | |
2860 | case AccessLength_BYTE : | |
2861 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2862 | break; | |
2863 | } | |
2864 | } else { | |
2865 | index += (AccessLength + 1); | |
2866 | switch (AccessLength) { /* little-endian memory */ | |
53b9417e DE |
2867 | case AccessLength_QUADWORD : |
2868 | mem[--index] = (unsigned char)(MemElem1 >> 56); | |
2869 | case 14 : | |
2870 | mem[--index] = (unsigned char)(MemElem1 >> 48); | |
2871 | case 13 : | |
2872 | mem[--index] = (unsigned char)(MemElem1 >> 40); | |
2873 | case 12 : | |
2874 | mem[--index] = (unsigned char)(MemElem1 >> 32); | |
2875 | case 11 : | |
2876 | mem[--index] = (unsigned char)(MemElem1 >> 24); | |
2877 | case 10 : | |
2878 | mem[--index] = (unsigned char)(MemElem1 >> 16); | |
2879 | case 9 : | |
2880 | mem[--index] = (unsigned char)(MemElem1 >> 8); | |
2881 | case 8 : | |
2882 | mem[--index] = (unsigned char)(MemElem1 >> 0); | |
2883 | ||
8bae0a0c JSC |
2884 | case AccessLength_DOUBLEWORD : |
2885 | mem[--index] = (unsigned char)(MemElem >> 56); | |
2886 | case AccessLength_SEPTIBYTE : | |
2887 | mem[--index] = (unsigned char)(MemElem >> 48); | |
2888 | case AccessLength_SEXTIBYTE : | |
2889 | mem[--index] = (unsigned char)(MemElem >> 40); | |
2890 | case AccessLength_QUINTIBYTE : | |
2891 | mem[--index] = (unsigned char)(MemElem >> 32); | |
2892 | case AccessLength_WORD : | |
2893 | mem[--index] = (unsigned char)(MemElem >> 24); | |
2894 | case AccessLength_TRIPLEBYTE : | |
2895 | mem[--index] = (unsigned char)(MemElem >> 16); | |
2896 | case AccessLength_HALFWORD : | |
2897 | mem[--index] = (unsigned char)(MemElem >> 8); | |
2898 | case AccessLength_BYTE : | |
2899 | mem[--index] = (unsigned char)(MemElem >> 0); | |
2900 | break; | |
2901 | } | |
2902 | } | |
2903 | } | |
2904 | } | |
2905 | ||
2906 | return; | |
2907 | } | |
2908 | ||
53b9417e | 2909 | |
8bae0a0c JSC |
2910 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ |
2911 | /* Order loads and stores to synchronise shared memory. Perform the | |
2912 | action necessary to make the effects of groups of synchronizable | |
2913 | loads and stores indicated by stype occur in the same order for all | |
2914 | processors. */ | |
2915 | static void | |
2916 | SyncOperation(stype) | |
2917 | int stype; | |
2918 | { | |
2919 | #ifdef DEBUG | |
2920 | callback->printf_filtered(callback,"SyncOperation(%d) : TODO\n",stype); | |
2921 | #endif /* DEBUG */ | |
2922 | return; | |
2923 | } | |
2924 | ||
2925 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
2926 | /* Signal an exception condition. This will result in an exception | |
2927 | that aborts the instruction. The instruction operation pseudocode | |
2928 | will never see a return from this function call. */ | |
2929 | static void | |
e3d12c65 | 2930 | SignalException (int exception,...) |
8bae0a0c JSC |
2931 | { |
2932 | /* Ensure that any active atomic read/modify/write operation will fail: */ | |
2933 | LLBIT = 0; | |
2934 | ||
2935 | switch (exception) { | |
2936 | /* TODO: For testing purposes I have been ignoring TRAPs. In | |
2937 | reality we should either simulate them, or allow the user to | |
2938 | ignore them at run-time. */ | |
2939 | case Trap : | |
53b9417e | 2940 | sim_warning("Ignoring instruction TRAP (PC 0x%s)",pr_addr(IPC)); |
8bae0a0c JSC |
2941 | break; |
2942 | ||
2943 | case ReservedInstruction : | |
2944 | { | |
2945 | va_list ap; | |
2946 | unsigned int instruction; | |
2947 | va_start(ap,exception); | |
2948 | instruction = va_arg(ap,unsigned int); | |
2949 | va_end(ap); | |
2950 | /* Provide simple monitor support using ReservedInstruction | |
2951 | exceptions. The following code simulates the fixed vector | |
2952 | entry points into the IDT monitor by causing a simulator | |
2953 | trap, performing the monitor operation, and returning to | |
2954 | the address held in the $ra register (standard PCS return | |
2955 | address). This means we only need to pre-load the vector | |
2956 | space with suitable instruction values. For systems were | |
2957 | actual trap instructions are used, we would not need to | |
2958 | perform this magic. */ | |
53b9417e DE |
2959 | if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION) { |
2960 | sim_monitor( ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) ); | |
8bae0a0c JSC |
2961 | PC = RA; /* simulate the return from the vector entry */ |
2962 | /* NOTE: This assumes that a branch-and-link style | |
2963 | instruction was used to enter the vector (which is the | |
2964 | case with the current IDT monitor). */ | |
2965 | break; /* out of the switch statement */ | |
7e6c297e ILT |
2966 | } |
2967 | /* Look for the mips16 entry and exit instructions, and | |
2968 | simulate a handler for them. */ | |
2969 | else if ((IPC & 1) != 0 | |
2970 | && (instruction & 0xf81f) == 0xe809 | |
7e6c297e ILT |
2971 | && (instruction & 0x0c0) != 0x0c0) { |
2972 | mips16_entry (instruction); | |
2973 | break; | |
8bae0a0c | 2974 | } /* else fall through to normal exception processing */ |
53b9417e | 2975 | sim_warning("ReservedInstruction 0x%08X at IPC = 0x%s",instruction,pr_addr(IPC)); |
8bae0a0c JSC |
2976 | } |
2977 | ||
2978 | default: | |
e3d12c65 | 2979 | #ifdef DEBUG |
f24b7b69 | 2980 | if (exception != BreakPoint) |
53b9417e | 2981 | callback->printf_filtered(callback,"DBG: SignalException(%d) IPC = 0x%s\n",exception,pr_addr(IPC)); |
8bae0a0c JSC |
2982 | #endif /* DEBUG */ |
2983 | /* Store exception code into current exception id variable (used | |
2984 | by exit code): */ | |
2985 | ||
2986 | /* TODO: If not simulating exceptions then stop the simulator | |
2987 | execution. At the moment we always stop the simulation. */ | |
2988 | state |= (simSTOP | simEXCEPTION); | |
e3d12c65 DE |
2989 | |
2990 | /* Keep a copy of the current A0 in-case this is the program exit | |
2991 | breakpoint: */ | |
2992 | if (exception == BreakPoint) { | |
2993 | va_list ap; | |
2994 | unsigned int instruction; | |
2995 | va_start(ap,exception); | |
2996 | instruction = va_arg(ap,unsigned int); | |
2997 | va_end(ap); | |
2998 | /* Check for our special terminating BREAK: */ | |
2999 | if ((instruction & 0x03FFFFC0) == 0x03ff0000) { | |
3000 | rcexit = (unsigned int)(A0 & 0xFFFFFFFF); | |
3001 | state &= ~simEXCEPTION; | |
3002 | state |= simEXIT; | |
3003 | } | |
3004 | } | |
3005 | ||
3006 | /* Store exception code into current exception id variable (used | |
3007 | by exit code): */ | |
8bae0a0c JSC |
3008 | CAUSE = (exception << 2); |
3009 | if (state & simDELAYSLOT) { | |
3010 | CAUSE |= cause_BD; | |
3011 | EPC = (IPC - 4); /* reference the branch instruction */ | |
3012 | } else | |
3013 | EPC = IPC; | |
3014 | /* The following is so that the simulator will continue from the | |
3015 | exception address on breakpoint operations. */ | |
3016 | PC = EPC; | |
3017 | break; | |
3018 | ||
3019 | case SimulatorFault: | |
3020 | { | |
3021 | va_list ap; | |
3022 | char *msg; | |
3023 | va_start(ap,exception); | |
3024 | msg = va_arg(ap,char *); | |
3025 | fprintf(stderr,"FATAL: Simulator error \"%s\"\n",msg); | |
3026 | va_end(ap); | |
3027 | } | |
3028 | exit(1); | |
3029 | } | |
3030 | ||
3031 | return; | |
3032 | } | |
3033 | ||
3034 | #if defined(WARN_RESULT) | |
3035 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
3036 | /* This function indicates that the result of the operation is | |
3037 | undefined. However, this should not affect the instruction | |
3038 | stream. All that is meant to happen is that the destination | |
3039 | register is set to an undefined result. To keep the simulator | |
3040 | simple, we just don't bother updating the destination register, so | |
3041 | the overall result will be undefined. If desired we can stop the | |
3042 | simulator by raising a pseudo-exception. */ | |
3043 | static void | |
3044 | UndefinedResult() | |
3045 | { | |
53b9417e | 3046 | sim_warning("UndefinedResult: IPC = 0x%s",pr_addr(IPC)); |
8bae0a0c JSC |
3047 | #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */ |
3048 | state |= simSTOP; | |
3049 | #endif | |
3050 | return; | |
3051 | } | |
3052 | #endif /* WARN_RESULT */ | |
3053 | ||
3054 | static void | |
3055 | CacheOp(op,pAddr,vAddr,instruction) | |
3056 | int op; | |
e871dd18 JSC |
3057 | uword64 pAddr; |
3058 | uword64 vAddr; | |
8bae0a0c JSC |
3059 | unsigned int instruction; |
3060 | { | |
f24b7b69 JSC |
3061 | #if 1 /* stop warning message being displayed (we should really just remove the code) */ |
3062 | static int icache_warning = 1; | |
3063 | static int dcache_warning = 1; | |
3064 | #else | |
a9f7253f JSC |
3065 | static int icache_warning = 0; |
3066 | static int dcache_warning = 0; | |
f24b7b69 | 3067 | #endif |
a9f7253f | 3068 | |
8bae0a0c JSC |
3069 | /* If CP0 is not useable (User or Supervisor mode) and the CP0 |
3070 | enable bit in the Status Register is clear - a coprocessor | |
3071 | unusable exception is taken. */ | |
a9f7253f | 3072 | #if 0 |
53b9417e | 3073 | callback->printf_filtered(callback,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(IPC)); |
a9f7253f | 3074 | #endif |
8bae0a0c JSC |
3075 | |
3076 | switch (op & 0x3) { | |
3077 | case 0: /* instruction cache */ | |
3078 | switch (op >> 2) { | |
3079 | case 0: /* Index Invalidate */ | |
3080 | case 1: /* Index Load Tag */ | |
3081 | case 2: /* Index Store Tag */ | |
3082 | case 4: /* Hit Invalidate */ | |
3083 | case 5: /* Fill */ | |
3084 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
3085 | if (!icache_warning) |
3086 | { | |
f24b7b69 | 3087 | sim_warning("Instruction CACHE operation %d to be coded",(op >> 2)); |
a9f7253f JSC |
3088 | icache_warning = 1; |
3089 | } | |
8bae0a0c JSC |
3090 | break; |
3091 | ||
3092 | default: | |
3093 | SignalException(ReservedInstruction,instruction); | |
3094 | break; | |
3095 | } | |
3096 | break; | |
3097 | ||
3098 | case 1: /* data cache */ | |
3099 | switch (op >> 2) { | |
3100 | case 0: /* Index Writeback Invalidate */ | |
3101 | case 1: /* Index Load Tag */ | |
3102 | case 2: /* Index Store Tag */ | |
3103 | case 3: /* Create Dirty */ | |
3104 | case 4: /* Hit Invalidate */ | |
3105 | case 5: /* Hit Writeback Invalidate */ | |
3106 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
3107 | if (!dcache_warning) |
3108 | { | |
f24b7b69 | 3109 | sim_warning("Data CACHE operation %d to be coded",(op >> 2)); |
a9f7253f JSC |
3110 | dcache_warning = 1; |
3111 | } | |
8bae0a0c JSC |
3112 | break; |
3113 | ||
3114 | default: | |
3115 | SignalException(ReservedInstruction,instruction); | |
3116 | break; | |
3117 | } | |
3118 | break; | |
3119 | ||
3120 | default: /* unrecognised cache ID */ | |
3121 | SignalException(ReservedInstruction,instruction); | |
3122 | break; | |
3123 | } | |
3124 | ||
3125 | return; | |
3126 | } | |
3127 | ||
3128 | /*-- FPU support routines ---------------------------------------------------*/ | |
3129 | ||
3130 | #if defined(HASFPU) /* Only needed when building FPU aware simulators */ | |
3131 | ||
3132 | #if 1 | |
3133 | #define SizeFGR() (GPRLEN) | |
3134 | #else | |
3135 | /* They depend on the CPU being simulated */ | |
3136 | #define SizeFGR() ((PROCESSOR_64BIT && ((SR & status_FR) == 1)) ? 64 : 32) | |
3137 | #endif | |
3138 | ||
3139 | /* Numbers are held in normalized form. The SINGLE and DOUBLE binary | |
3140 | formats conform to ANSI/IEEE Std 754-1985. */ | |
3141 | /* SINGLE precision floating: | |
3142 | * seeeeeeeefffffffffffffffffffffff | |
3143 | * s = 1bit = sign | |
3144 | * e = 8bits = exponent | |
3145 | * f = 23bits = fraction | |
3146 | */ | |
3147 | /* SINGLE precision fixed: | |
3148 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
3149 | * s = 1bit = sign | |
3150 | * i = 31bits = integer | |
3151 | */ | |
3152 | /* DOUBLE precision floating: | |
3153 | * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff | |
3154 | * s = 1bit = sign | |
3155 | * e = 11bits = exponent | |
3156 | * f = 52bits = fraction | |
3157 | */ | |
3158 | /* DOUBLE precision fixed: | |
3159 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
3160 | * s = 1bit = sign | |
3161 | * i = 63bits = integer | |
3162 | */ | |
3163 | ||
3164 | /* Extract sign-bit: */ | |
3165 | #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0) | |
e871dd18 | 3166 | #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0) |
8bae0a0c JSC |
3167 | /* Extract biased exponent: */ |
3168 | #define FP_S_be(v) (((v) >> 23) & 0xFF) | |
3169 | #define FP_D_be(v) (((v) >> 52) & 0x7FF) | |
3170 | /* Extract unbiased Exponent: */ | |
3171 | #define FP_S_e(v) (FP_S_be(v) - 0x7F) | |
3172 | #define FP_D_e(v) (FP_D_be(v) - 0x3FF) | |
3173 | /* Extract complete fraction field: */ | |
3174 | #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23)) | |
e871dd18 | 3175 | #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52)) |
8bae0a0c JSC |
3176 | /* Extract numbered fraction bit: */ |
3177 | #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0) | |
3178 | #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0) | |
3179 | ||
3180 | /* Explicit QNaN values used when value required: */ | |
3181 | #define FPQNaN_SINGLE (0x7FBFFFFF) | |
3182 | #define FPQNaN_WORD (0x7FFFFFFF) | |
e871dd18 JSC |
3183 | #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF) |
3184 | #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF) | |
8bae0a0c JSC |
3185 | |
3186 | /* Explicit Infinity values used when required: */ | |
3187 | #define FPINF_SINGLE (0x7F800000) | |
e871dd18 | 3188 | #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000) |
8bae0a0c JSC |
3189 | |
3190 | #if 1 /* def DEBUG */ | |
3191 | #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor"))) | |
3192 | #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>")))))) | |
3193 | #endif /* DEBUG */ | |
3194 | ||
e871dd18 | 3195 | static uword64 |
8bae0a0c JSC |
3196 | ValueFPR(fpr,fmt) |
3197 | int fpr; | |
3198 | FP_formats fmt; | |
3199 | { | |
e871dd18 | 3200 | uword64 value; |
8bae0a0c JSC |
3201 | int err = 0; |
3202 | ||
3203 | /* Treat unused register values, as fixed-point 64bit values: */ | |
3204 | if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown)) | |
3205 | #if 1 | |
3206 | /* If request to read data as "uninterpreted", then use the current | |
3207 | encoding: */ | |
3208 | fmt = fpr_state[fpr]; | |
3209 | #else | |
3210 | fmt = fmt_long; | |
3211 | #endif | |
3212 | ||
3213 | /* For values not yet accessed, set to the desired format: */ | |
3214 | if (fpr_state[fpr] == fmt_uninterpreted) { | |
3215 | fpr_state[fpr] = fmt; | |
3216 | #ifdef DEBUG | |
3217 | printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt)); | |
3218 | #endif /* DEBUG */ | |
3219 | } | |
3220 | if (fmt != fpr_state[fpr]) { | |
53b9417e | 3221 | sim_warning("FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)",fpr,DOFMT(fpr_state[fpr]),DOFMT(fmt),pr_addr(IPC)); |
8bae0a0c JSC |
3222 | fpr_state[fpr] = fmt_unknown; |
3223 | } | |
3224 | ||
3225 | if (fpr_state[fpr] == fmt_unknown) { | |
3226 | /* Set QNaN value: */ | |
3227 | switch (fmt) { | |
3228 | case fmt_single: | |
3229 | value = FPQNaN_SINGLE; | |
3230 | break; | |
3231 | ||
3232 | case fmt_double: | |
3233 | value = FPQNaN_DOUBLE; | |
3234 | break; | |
3235 | ||
3236 | case fmt_word: | |
3237 | value = FPQNaN_WORD; | |
3238 | break; | |
3239 | ||
3240 | case fmt_long: | |
3241 | value = FPQNaN_LONG; | |
3242 | break; | |
3243 | ||
3244 | default: | |
3245 | err = -1; | |
3246 | break; | |
3247 | } | |
3248 | } else if (SizeFGR() == 64) { | |
3249 | switch (fmt) { | |
3250 | case fmt_single: | |
3251 | case fmt_word: | |
3252 | value = (FGR[fpr] & 0xFFFFFFFF); | |
3253 | break; | |
3254 | ||
3255 | case fmt_uninterpreted: | |
3256 | case fmt_double: | |
3257 | case fmt_long: | |
3258 | value = FGR[fpr]; | |
3259 | break; | |
3260 | ||
3261 | default : | |
3262 | err = -1; | |
3263 | break; | |
3264 | } | |
da0bce9c | 3265 | } else { |
8bae0a0c JSC |
3266 | switch (fmt) { |
3267 | case fmt_single: | |
3268 | case fmt_word: | |
3269 | value = (FGR[fpr] & 0xFFFFFFFF); | |
3270 | break; | |
3271 | ||
3272 | case fmt_uninterpreted: | |
3273 | case fmt_double: | |
3274 | case fmt_long: | |
da0bce9c ILT |
3275 | if ((fpr & 1) == 0) { /* even registers only */ |
3276 | value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF)); | |
3277 | } else { | |
3278 | SignalException (ReservedInstruction, 0); | |
3279 | } | |
8bae0a0c JSC |
3280 | break; |
3281 | ||
3282 | default : | |
3283 | err = -1; | |
3284 | break; | |
3285 | } | |
3286 | } | |
3287 | ||
3288 | if (err) | |
3289 | SignalException(SimulatorFault,"Unrecognised FP format in ValueFPR()"); | |
3290 | ||
3291 | #ifdef DEBUG | |
53b9417e | 3292 | printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(IPC),SizeFGR()); |
8bae0a0c JSC |
3293 | #endif /* DEBUG */ |
3294 | ||
3295 | return(value); | |
3296 | } | |
3297 | ||
3298 | static void | |
3299 | StoreFPR(fpr,fmt,value) | |
3300 | int fpr; | |
3301 | FP_formats fmt; | |
e871dd18 | 3302 | uword64 value; |
8bae0a0c JSC |
3303 | { |
3304 | int err = 0; | |
3305 | ||
3306 | #ifdef DEBUG | |
53b9417e | 3307 | printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(IPC),SizeFGR()); |
8bae0a0c JSC |
3308 | #endif /* DEBUG */ |
3309 | ||
3310 | if (SizeFGR() == 64) { | |
3311 | switch (fmt) { | |
3312 | case fmt_single : | |
3313 | case fmt_word : | |
e871dd18 | 3314 | FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF)); |
8bae0a0c JSC |
3315 | fpr_state[fpr] = fmt; |
3316 | break; | |
3317 | ||
3318 | case fmt_uninterpreted: | |
3319 | case fmt_double : | |
3320 | case fmt_long : | |
3321 | FGR[fpr] = value; | |
3322 | fpr_state[fpr] = fmt; | |
3323 | break; | |
3324 | ||
3325 | default : | |
3326 | fpr_state[fpr] = fmt_unknown; | |
3327 | err = -1; | |
3328 | break; | |
3329 | } | |
da0bce9c | 3330 | } else { |
8bae0a0c JSC |
3331 | switch (fmt) { |
3332 | case fmt_single : | |
3333 | case fmt_word : | |
8bae0a0c | 3334 | FGR[fpr] = (value & 0xFFFFFFFF); |
8bae0a0c JSC |
3335 | fpr_state[fpr] = fmt; |
3336 | break; | |
3337 | ||
3338 | case fmt_uninterpreted: | |
3339 | case fmt_double : | |
3340 | case fmt_long : | |
da0bce9c ILT |
3341 | if ((fpr & 1) == 0) { /* even register number only */ |
3342 | FGR[fpr+1] = (value >> 32); | |
3343 | FGR[fpr] = (value & 0xFFFFFFFF); | |
3344 | fpr_state[fpr + 1] = fmt; | |
3345 | fpr_state[fpr] = fmt; | |
3346 | } else { | |
3347 | fpr_state[fpr] = fmt_unknown; | |
3348 | fpr_state[fpr + 1] = fmt_unknown; | |
3349 | SignalException (ReservedInstruction, 0); | |
3350 | } | |
8bae0a0c JSC |
3351 | break; |
3352 | ||
3353 | default : | |
3354 | fpr_state[fpr] = fmt_unknown; | |
3355 | err = -1; | |
3356 | break; | |
3357 | } | |
e871dd18 JSC |
3358 | } |
3359 | #if defined(WARN_RESULT) | |
3360 | else | |
3361 | UndefinedResult(); | |
3362 | #endif /* WARN_RESULT */ | |
8bae0a0c JSC |
3363 | |
3364 | if (err) | |
3365 | SignalException(SimulatorFault,"Unrecognised FP format in StoreFPR()"); | |
3366 | ||
3367 | #ifdef DEBUG | |
53b9417e | 3368 | printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt)); |
8bae0a0c JSC |
3369 | #endif /* DEBUG */ |
3370 | ||
3371 | return; | |
3372 | } | |
3373 | ||
3374 | static int | |
3375 | NaN(op,fmt) | |
e871dd18 | 3376 | uword64 op; |
8bae0a0c JSC |
3377 | FP_formats fmt; |
3378 | { | |
3379 | int boolean = 0; | |
3380 | ||
3381 | /* Check if (((E - bias) == (E_max + 1)) && (fraction != 0)). We | |
3382 | know that the exponent field is biased... we we cheat and avoid | |
3383 | removing the bias value. */ | |
3384 | switch (fmt) { | |
3385 | case fmt_single: | |
3386 | boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) != 0)); | |
3387 | /* We could use "FP_S_fb(1,op)" to ascertain whether we are | |
3388 | dealing with a SNaN or QNaN */ | |
3389 | break; | |
3390 | case fmt_double: | |
3391 | boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) != 0)); | |
3392 | /* We could use "FP_S_fb(1,op)" to ascertain whether we are | |
3393 | dealing with a SNaN or QNaN */ | |
3394 | break; | |
3395 | case fmt_word: | |
3396 | boolean = (op == FPQNaN_WORD); | |
3397 | break; | |
3398 | case fmt_long: | |
3399 | boolean = (op == FPQNaN_LONG); | |
3400 | break; | |
3401 | } | |
3402 | ||
3403 | #ifdef DEBUG | |
53b9417e | 3404 | printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
3405 | #endif /* DEBUG */ |
3406 | ||
3407 | return(boolean); | |
3408 | } | |
3409 | ||
3410 | static int | |
3411 | Infinity(op,fmt) | |
e871dd18 | 3412 | uword64 op; |
8bae0a0c JSC |
3413 | FP_formats fmt; |
3414 | { | |
3415 | int boolean = 0; | |
3416 | ||
3417 | #ifdef DEBUG | |
53b9417e | 3418 | printf("DBG: Infinity: format %s 0x%s (PC = 0x%s)\n",DOFMT(fmt),pr_addr(op),pr_addr(IPC)); |
8bae0a0c JSC |
3419 | #endif /* DEBUG */ |
3420 | ||
3421 | /* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We | |
3422 | know that the exponent field is biased... we we cheat and avoid | |
3423 | removing the bias value. */ | |
3424 | switch (fmt) { | |
3425 | case fmt_single: | |
3426 | boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) == 0)); | |
3427 | break; | |
3428 | case fmt_double: | |
3429 | boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) == 0)); | |
3430 | break; | |
3431 | default: | |
3432 | printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt)); | |
3433 | break; | |
3434 | } | |
3435 | ||
3436 | #ifdef DEBUG | |
53b9417e | 3437 | printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
3438 | #endif /* DEBUG */ |
3439 | ||
3440 | return(boolean); | |
3441 | } | |
3442 | ||
3443 | static int | |
3444 | Less(op1,op2,fmt) | |
e871dd18 JSC |
3445 | uword64 op1; |
3446 | uword64 op2; | |
8bae0a0c JSC |
3447 | FP_formats fmt; |
3448 | { | |
3449 | int boolean = 0; | |
3450 | ||
e871dd18 JSC |
3451 | /* Argument checking already performed by the FPCOMPARE code */ |
3452 | ||
8bae0a0c | 3453 | #ifdef DEBUG |
53b9417e | 3454 | printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
3455 | #endif /* DEBUG */ |
3456 | ||
8bae0a0c JSC |
3457 | /* The format type should already have been checked: */ |
3458 | switch (fmt) { | |
3459 | case fmt_single: | |
3460 | { | |
3461 | unsigned int wop1 = (unsigned int)op1; | |
3462 | unsigned int wop2 = (unsigned int)op2; | |
3463 | boolean = (*(float *)&wop1 < *(float *)&wop2); | |
3464 | } | |
3465 | break; | |
3466 | case fmt_double: | |
3467 | boolean = (*(double *)&op1 < *(double *)&op2); | |
3468 | break; | |
3469 | } | |
3470 | ||
3471 | #ifdef DEBUG | |
3472 | printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
3473 | #endif /* DEBUG */ | |
3474 | ||
3475 | return(boolean); | |
3476 | } | |
3477 | ||
3478 | static int | |
3479 | Equal(op1,op2,fmt) | |
e871dd18 JSC |
3480 | uword64 op1; |
3481 | uword64 op2; | |
8bae0a0c JSC |
3482 | FP_formats fmt; |
3483 | { | |
3484 | int boolean = 0; | |
3485 | ||
e871dd18 JSC |
3486 | /* Argument checking already performed by the FPCOMPARE code */ |
3487 | ||
8bae0a0c | 3488 | #ifdef DEBUG |
53b9417e | 3489 | printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
3490 | #endif /* DEBUG */ |
3491 | ||
8bae0a0c JSC |
3492 | /* The format type should already have been checked: */ |
3493 | switch (fmt) { | |
3494 | case fmt_single: | |
3495 | boolean = ((op1 & 0xFFFFFFFF) == (op2 & 0xFFFFFFFF)); | |
3496 | break; | |
3497 | case fmt_double: | |
3498 | boolean = (op1 == op2); | |
3499 | break; | |
3500 | } | |
3501 | ||
3502 | #ifdef DEBUG | |
3503 | printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
3504 | #endif /* DEBUG */ | |
3505 | ||
3506 | return(boolean); | |
3507 | } | |
3508 | ||
a9f7253f JSC |
3509 | static uword64 |
3510 | AbsoluteValue(op,fmt) | |
3511 | uword64 op; | |
3512 | FP_formats fmt; | |
3513 | { | |
3514 | uword64 result; | |
3515 | ||
3516 | #ifdef DEBUG | |
53b9417e | 3517 | printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
a9f7253f JSC |
3518 | #endif /* DEBUG */ |
3519 | ||
3520 | /* The format type should already have been checked: */ | |
3521 | switch (fmt) { | |
3522 | case fmt_single: | |
3523 | { | |
3524 | unsigned int wop = (unsigned int)op; | |
3525 | float tmp = ((float)fabs((double)*(float *)&wop)); | |
3526 | result = (uword64)*(unsigned int *)&tmp; | |
3527 | } | |
3528 | break; | |
3529 | case fmt_double: | |
3530 | { | |
3531 | double tmp = (fabs(*(double *)&op)); | |
3532 | result = *(uword64 *)&tmp; | |
3533 | } | |
3534 | } | |
3535 | ||
3536 | return(result); | |
3537 | } | |
3538 | ||
e871dd18 | 3539 | static uword64 |
8bae0a0c | 3540 | Negate(op,fmt) |
e871dd18 | 3541 | uword64 op; |
8bae0a0c JSC |
3542 | FP_formats fmt; |
3543 | { | |
e871dd18 | 3544 | uword64 result; |
8bae0a0c JSC |
3545 | |
3546 | #ifdef DEBUG | |
53b9417e | 3547 | printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
3548 | #endif /* DEBUG */ |
3549 | ||
3550 | /* The format type should already have been checked: */ | |
3551 | switch (fmt) { | |
3552 | case fmt_single: | |
3553 | { | |
3554 | unsigned int wop = (unsigned int)op; | |
3555 | float tmp = ((float)0.0 - *(float *)&wop); | |
e871dd18 | 3556 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
3557 | } |
3558 | break; | |
3559 | case fmt_double: | |
3560 | { | |
3561 | double tmp = ((double)0.0 - *(double *)&op); | |
e871dd18 | 3562 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
3563 | } |
3564 | break; | |
3565 | } | |
3566 | ||
3567 | return(result); | |
3568 | } | |
3569 | ||
e871dd18 | 3570 | static uword64 |
8bae0a0c | 3571 | Add(op1,op2,fmt) |
e871dd18 JSC |
3572 | uword64 op1; |
3573 | uword64 op2; | |
8bae0a0c JSC |
3574 | FP_formats fmt; |
3575 | { | |
e871dd18 | 3576 | uword64 result; |
8bae0a0c JSC |
3577 | |
3578 | #ifdef DEBUG | |
53b9417e | 3579 | printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
3580 | #endif /* DEBUG */ |
3581 | ||
e871dd18 JSC |
3582 | /* The registers must specify FPRs valid for operands of type |
3583 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
3584 | |
3585 | /* The format type should already have been checked: */ | |
3586 | switch (fmt) { | |
3587 | case fmt_single: | |
3588 | { | |
3589 | unsigned int wop1 = (unsigned int)op1; | |
3590 | unsigned int wop2 = (unsigned int)op2; | |
3591 | float tmp = (*(float *)&wop1 + *(float *)&wop2); | |
e871dd18 | 3592 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
3593 | } |
3594 | break; | |
3595 | case fmt_double: | |
3596 | { | |
3597 | double tmp = (*(double *)&op1 + *(double *)&op2); | |
e871dd18 | 3598 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
3599 | } |
3600 | break; | |
3601 | } | |
3602 | ||
3603 | #ifdef DEBUG | |
53b9417e | 3604 | printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
3605 | #endif /* DEBUG */ |
3606 | ||
3607 | return(result); | |
3608 | } | |
3609 | ||
e871dd18 | 3610 | static uword64 |
8bae0a0c | 3611 | Sub(op1,op2,fmt) |
e871dd18 JSC |
3612 | uword64 op1; |
3613 | uword64 op2; | |
8bae0a0c JSC |
3614 | FP_formats fmt; |
3615 | { | |
e871dd18 | 3616 | uword64 result; |
8bae0a0c JSC |
3617 | |
3618 | #ifdef DEBUG | |
53b9417e | 3619 | printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
3620 | #endif /* DEBUG */ |
3621 | ||
e871dd18 JSC |
3622 | /* The registers must specify FPRs valid for operands of type |
3623 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
3624 | |
3625 | /* The format type should already have been checked: */ | |
3626 | switch (fmt) { | |
3627 | case fmt_single: | |
3628 | { | |
3629 | unsigned int wop1 = (unsigned int)op1; | |
3630 | unsigned int wop2 = (unsigned int)op2; | |
3631 | float tmp = (*(float *)&wop1 - *(float *)&wop2); | |
e871dd18 | 3632 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
3633 | } |
3634 | break; | |
3635 | case fmt_double: | |
3636 | { | |
3637 | double tmp = (*(double *)&op1 - *(double *)&op2); | |
e871dd18 | 3638 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
3639 | } |
3640 | break; | |
3641 | } | |
3642 | ||
3643 | #ifdef DEBUG | |
53b9417e | 3644 | printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
3645 | #endif /* DEBUG */ |
3646 | ||
3647 | return(result); | |
3648 | } | |
3649 | ||
e871dd18 | 3650 | static uword64 |
8bae0a0c | 3651 | Multiply(op1,op2,fmt) |
e871dd18 JSC |
3652 | uword64 op1; |
3653 | uword64 op2; | |
8bae0a0c JSC |
3654 | FP_formats fmt; |
3655 | { | |
e871dd18 | 3656 | uword64 result; |
8bae0a0c JSC |
3657 | |
3658 | #ifdef DEBUG | |
53b9417e | 3659 | printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
3660 | #endif /* DEBUG */ |
3661 | ||
e871dd18 JSC |
3662 | /* The registers must specify FPRs valid for operands of type |
3663 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
3664 | |
3665 | /* The format type should already have been checked: */ | |
3666 | switch (fmt) { | |
3667 | case fmt_single: | |
3668 | { | |
3669 | unsigned int wop1 = (unsigned int)op1; | |
3670 | unsigned int wop2 = (unsigned int)op2; | |
3671 | float tmp = (*(float *)&wop1 * *(float *)&wop2); | |
e871dd18 | 3672 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
3673 | } |
3674 | break; | |
3675 | case fmt_double: | |
3676 | { | |
3677 | double tmp = (*(double *)&op1 * *(double *)&op2); | |
e871dd18 | 3678 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
3679 | } |
3680 | break; | |
3681 | } | |
3682 | ||
3683 | #ifdef DEBUG | |
53b9417e | 3684 | printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
3685 | #endif /* DEBUG */ |
3686 | ||
3687 | return(result); | |
3688 | } | |
3689 | ||
e871dd18 | 3690 | static uword64 |
8bae0a0c | 3691 | Divide(op1,op2,fmt) |
e871dd18 JSC |
3692 | uword64 op1; |
3693 | uword64 op2; | |
8bae0a0c JSC |
3694 | FP_formats fmt; |
3695 | { | |
e871dd18 | 3696 | uword64 result; |
8bae0a0c JSC |
3697 | |
3698 | #ifdef DEBUG | |
53b9417e | 3699 | printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
3700 | #endif /* DEBUG */ |
3701 | ||
e871dd18 JSC |
3702 | /* The registers must specify FPRs valid for operands of type |
3703 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
3704 | |
3705 | /* The format type should already have been checked: */ | |
3706 | switch (fmt) { | |
3707 | case fmt_single: | |
3708 | { | |
3709 | unsigned int wop1 = (unsigned int)op1; | |
3710 | unsigned int wop2 = (unsigned int)op2; | |
3711 | float tmp = (*(float *)&wop1 / *(float *)&wop2); | |
e871dd18 | 3712 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
3713 | } |
3714 | break; | |
3715 | case fmt_double: | |
3716 | { | |
3717 | double tmp = (*(double *)&op1 / *(double *)&op2); | |
e871dd18 | 3718 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
3719 | } |
3720 | break; | |
3721 | } | |
3722 | ||
3723 | #ifdef DEBUG | |
53b9417e | 3724 | printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
3725 | #endif /* DEBUG */ |
3726 | ||
3727 | return(result); | |
3728 | } | |
3729 | ||
e871dd18 | 3730 | static uword64 |
8bae0a0c | 3731 | Recip(op,fmt) |
e871dd18 | 3732 | uword64 op; |
8bae0a0c JSC |
3733 | FP_formats fmt; |
3734 | { | |
e871dd18 | 3735 | uword64 result; |
8bae0a0c JSC |
3736 | |
3737 | #ifdef DEBUG | |
53b9417e | 3738 | printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
3739 | #endif /* DEBUG */ |
3740 | ||
e871dd18 JSC |
3741 | /* The registers must specify FPRs valid for operands of type |
3742 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
3743 | |
3744 | /* The format type should already have been checked: */ | |
3745 | switch (fmt) { | |
3746 | case fmt_single: | |
3747 | { | |
3748 | unsigned int wop = (unsigned int)op; | |
3749 | float tmp = ((float)1.0 / *(float *)&wop); | |
e871dd18 | 3750 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
3751 | } |
3752 | break; | |
3753 | case fmt_double: | |
3754 | { | |
3755 | double tmp = ((double)1.0 / *(double *)&op); | |
e871dd18 | 3756 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
3757 | } |
3758 | break; | |
3759 | } | |
3760 | ||
3761 | #ifdef DEBUG | |
53b9417e | 3762 | printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
3763 | #endif /* DEBUG */ |
3764 | ||
3765 | return(result); | |
3766 | } | |
3767 | ||
e871dd18 | 3768 | static uword64 |
8bae0a0c | 3769 | SquareRoot(op,fmt) |
e871dd18 | 3770 | uword64 op; |
8bae0a0c JSC |
3771 | FP_formats fmt; |
3772 | { | |
e871dd18 | 3773 | uword64 result; |
8bae0a0c JSC |
3774 | |
3775 | #ifdef DEBUG | |
53b9417e | 3776 | printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
3777 | #endif /* DEBUG */ |
3778 | ||
e871dd18 JSC |
3779 | /* The registers must specify FPRs valid for operands of type |
3780 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
3781 | |
3782 | /* The format type should already have been checked: */ | |
3783 | switch (fmt) { | |
3784 | case fmt_single: | |
3785 | { | |
3786 | unsigned int wop = (unsigned int)op; | |
e3d12c65 | 3787 | #ifdef HAVE_SQRT |
8bae0a0c | 3788 | float tmp = ((float)sqrt((double)*(float *)&wop)); |
e871dd18 | 3789 | result = (uword64)*(unsigned int *)&tmp; |
e3d12c65 DE |
3790 | #else |
3791 | /* TODO: Provide square-root */ | |
3792 | result = (uword64)0; | |
3793 | #endif | |
8bae0a0c JSC |
3794 | } |
3795 | break; | |
3796 | case fmt_double: | |
3797 | { | |
e3d12c65 | 3798 | #ifdef HAVE_SQRT |
8bae0a0c | 3799 | double tmp = (sqrt(*(double *)&op)); |
e871dd18 | 3800 | result = *(uword64 *)&tmp; |
e3d12c65 DE |
3801 | #else |
3802 | /* TODO: Provide square-root */ | |
3803 | result = (uword64)0; | |
3804 | #endif | |
8bae0a0c JSC |
3805 | } |
3806 | break; | |
3807 | } | |
3808 | ||
3809 | #ifdef DEBUG | |
53b9417e | 3810 | printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
3811 | #endif /* DEBUG */ |
3812 | ||
3813 | return(result); | |
3814 | } | |
3815 | ||
e871dd18 | 3816 | static uword64 |
8bae0a0c JSC |
3817 | Convert(rm,op,from,to) |
3818 | int rm; | |
e871dd18 | 3819 | uword64 op; |
8bae0a0c JSC |
3820 | FP_formats from; |
3821 | FP_formats to; | |
3822 | { | |
e871dd18 | 3823 | uword64 result; |
8bae0a0c JSC |
3824 | |
3825 | #ifdef DEBUG | |
53b9417e | 3826 | printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC)); |
8bae0a0c JSC |
3827 | #endif /* DEBUG */ |
3828 | ||
3829 | /* The value "op" is converted to the destination format, rounding | |
3830 | using mode "rm". When the destination is a fixed-point format, | |
3831 | then a source value of Infinity, NaN or one which would round to | |
3832 | an integer outside the fixed point range then an IEEE Invalid | |
3833 | Operation condition is raised. */ | |
3834 | switch (to) { | |
3835 | case fmt_single: | |
3836 | { | |
3837 | float tmp; | |
3838 | switch (from) { | |
3839 | case fmt_double: | |
3840 | tmp = (float)(*(double *)&op); | |
3841 | break; | |
3842 | ||
3843 | case fmt_word: | |
3844 | tmp = (float)((int)(op & 0xFFFFFFFF)); | |
3845 | break; | |
3846 | ||
3847 | case fmt_long: | |
e3d12c65 | 3848 | tmp = (float)((word64)op); |
8bae0a0c JSC |
3849 | break; |
3850 | } | |
3851 | ||
458e1f58 ILT |
3852 | #if 0 |
3853 | /* FIXME: This code is incorrect. The rounding mode does not | |
3854 | round to integral values; it rounds to the nearest | |
3855 | representable value in the format. */ | |
3856 | ||
8bae0a0c JSC |
3857 | switch (rm) { |
3858 | case FP_RM_NEAREST: | |
e871dd18 JSC |
3859 | /* Round result to nearest representable value. When two |
3860 | representable values are equally near, round to the value | |
3861 | that has a least significant bit of zero (i.e. is even). */ | |
4fa134be | 3862 | #ifdef HAVE_ANINT |
e871dd18 | 3863 | tmp = (float)anint((double)tmp); |
d0757082 JSC |
3864 | #else |
3865 | /* TODO: Provide round-to-nearest */ | |
3866 | #endif | |
8bae0a0c JSC |
3867 | break; |
3868 | ||
3869 | case FP_RM_TOZERO: | |
e871dd18 JSC |
3870 | /* Round result to the value closest to, and not greater in |
3871 | magnitude than, the result. */ | |
4fa134be | 3872 | #ifdef HAVE_AINT |
e871dd18 | 3873 | tmp = (float)aint((double)tmp); |
d0757082 JSC |
3874 | #else |
3875 | /* TODO: Provide round-to-zero */ | |
3876 | #endif | |
8bae0a0c JSC |
3877 | break; |
3878 | ||
3879 | case FP_RM_TOPINF: | |
e871dd18 JSC |
3880 | /* Round result to the value closest to, and not less than, |
3881 | the result. */ | |
3882 | tmp = (float)ceil((double)tmp); | |
8bae0a0c JSC |
3883 | break; |
3884 | ||
3885 | case FP_RM_TOMINF: | |
e871dd18 JSC |
3886 | /* Round result to the value closest to, and not greater than, |
3887 | the result. */ | |
3888 | tmp = (float)floor((double)tmp); | |
8bae0a0c JSC |
3889 | break; |
3890 | } | |
458e1f58 ILT |
3891 | #endif /* 0 */ |
3892 | ||
e871dd18 | 3893 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
3894 | } |
3895 | break; | |
3896 | ||
3897 | case fmt_double: | |
3898 | { | |
3899 | double tmp; | |
f24b7b69 | 3900 | word64 xxx; |
8bae0a0c JSC |
3901 | |
3902 | switch (from) { | |
3903 | case fmt_single: | |
3904 | { | |
3905 | unsigned int wop = (unsigned int)op; | |
3906 | tmp = (double)(*(float *)&wop); | |
3907 | } | |
3908 | break; | |
3909 | ||
3910 | case fmt_word: | |
f24b7b69 | 3911 | xxx = SIGNEXTEND((op & 0xFFFFFFFF),32); |
e3d12c65 | 3912 | tmp = (double)xxx; |
8bae0a0c JSC |
3913 | break; |
3914 | ||
3915 | case fmt_long: | |
e871dd18 | 3916 | tmp = (double)((word64)op); |
8bae0a0c JSC |
3917 | break; |
3918 | } | |
e871dd18 | 3919 | |
458e1f58 ILT |
3920 | #if 0 |
3921 | /* FIXME: This code is incorrect. The rounding mode does not | |
3922 | round to integral values; it rounds to the nearest | |
3923 | representable value in the format. */ | |
3924 | ||
8bae0a0c JSC |
3925 | switch (rm) { |
3926 | case FP_RM_NEAREST: | |
4fa134be | 3927 | #ifdef HAVE_ANINT |
e871dd18 | 3928 | tmp = anint(*(double *)&tmp); |
d0757082 JSC |
3929 | #else |
3930 | /* TODO: Provide round-to-nearest */ | |
3931 | #endif | |
8bae0a0c JSC |
3932 | break; |
3933 | ||
3934 | case FP_RM_TOZERO: | |
4fa134be | 3935 | #ifdef HAVE_AINT |
e871dd18 | 3936 | tmp = aint(*(double *)&tmp); |
d0757082 JSC |
3937 | #else |
3938 | /* TODO: Provide round-to-zero */ | |
3939 | #endif | |
8bae0a0c JSC |
3940 | break; |
3941 | ||
3942 | case FP_RM_TOPINF: | |
3943 | tmp = ceil(*(double *)&tmp); | |
3944 | break; | |
3945 | ||
3946 | case FP_RM_TOMINF: | |
3947 | tmp = floor(*(double *)&tmp); | |
3948 | break; | |
3949 | } | |
458e1f58 ILT |
3950 | #endif /* 0 */ |
3951 | ||
e871dd18 | 3952 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
3953 | } |
3954 | break; | |
3955 | ||
3956 | case fmt_word: | |
3957 | case fmt_long: | |
3958 | if (Infinity(op,from) || NaN(op,from) || (1 == 0/*TODO: check range */)) { | |
3959 | printf("DBG: TODO: update FCSR\n"); | |
3960 | SignalException(FPE); | |
3961 | } else { | |
3962 | if (to == fmt_word) { | |
e3d12c65 | 3963 | int tmp; |
8bae0a0c JSC |
3964 | switch (from) { |
3965 | case fmt_single: | |
3966 | { | |
3967 | unsigned int wop = (unsigned int)op; | |
e3d12c65 | 3968 | tmp = (int)*((float *)&wop); |
8bae0a0c JSC |
3969 | } |
3970 | break; | |
3971 | case fmt_double: | |
e3d12c65 | 3972 | tmp = (int)*((double *)&op); |
8bae0a0c | 3973 | #ifdef DEBUG |
53b9417e | 3974 | printf("DBG: from double %.30f (0x%s) to word: 0x%08X\n",*((double *)&op),pr_addr(op),tmp); |
8bae0a0c JSC |
3975 | #endif /* DEBUG */ |
3976 | break; | |
3977 | } | |
e871dd18 | 3978 | result = (uword64)tmp; |
8bae0a0c | 3979 | } else { /* fmt_long */ |
e3d12c65 | 3980 | word64 tmp; |
8bae0a0c JSC |
3981 | switch (from) { |
3982 | case fmt_single: | |
3983 | { | |
3984 | unsigned int wop = (unsigned int)op; | |
e3d12c65 | 3985 | tmp = (word64)*((float *)&wop); |
8bae0a0c JSC |
3986 | } |
3987 | break; | |
3988 | case fmt_double: | |
e3d12c65 | 3989 | tmp = (word64)*((double *)&op); |
8bae0a0c JSC |
3990 | break; |
3991 | } | |
e3d12c65 | 3992 | result = (uword64)tmp; |
8bae0a0c JSC |
3993 | } |
3994 | } | |
3995 | break; | |
3996 | } | |
3997 | ||
3998 | #ifdef DEBUG | |
53b9417e | 3999 | printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result),DOFMT(to)); |
8bae0a0c JSC |
4000 | #endif /* DEBUG */ |
4001 | ||
4002 | return(result); | |
4003 | } | |
4004 | #endif /* HASFPU */ | |
4005 | ||
4006 | /*-- co-processor support routines ------------------------------------------*/ | |
4007 | ||
4008 | static int | |
4009 | CoProcPresent(coproc_number) | |
4010 | unsigned int coproc_number; | |
4011 | { | |
4012 | /* Return TRUE if simulator provides a model for the given co-processor number */ | |
4013 | return(0); | |
4014 | } | |
4015 | ||
4016 | static void | |
4017 | COP_LW(coproc_num,coproc_reg,memword) | |
4018 | int coproc_num, coproc_reg; | |
4019 | unsigned int memword; | |
4020 | { | |
4021 | switch (coproc_num) { | |
4022 | #if defined(HASFPU) | |
4023 | case 1: | |
4024 | #ifdef DEBUG | |
53b9417e | 4025 | printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword)); |
8bae0a0c | 4026 | #endif |
da0bce9c ILT |
4027 | StoreFPR(coproc_reg,fmt_word,(uword64)memword); |
4028 | fpr_state[coproc_reg] = fmt_uninterpreted; | |
8bae0a0c JSC |
4029 | break; |
4030 | #endif /* HASFPU */ | |
4031 | ||
4032 | default: | |
f24b7b69 | 4033 | #if 0 /* this should be controlled by a configuration option */ |
53b9417e | 4034 | callback->printf_filtered(callback,"COP_LW(%d,%d,0x%08X) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(IPC)); |
f24b7b69 | 4035 | #endif |
8bae0a0c JSC |
4036 | break; |
4037 | } | |
4038 | ||
4039 | return; | |
4040 | } | |
4041 | ||
4042 | static void | |
4043 | COP_LD(coproc_num,coproc_reg,memword) | |
4044 | int coproc_num, coproc_reg; | |
e871dd18 | 4045 | uword64 memword; |
8bae0a0c JSC |
4046 | { |
4047 | switch (coproc_num) { | |
4048 | #if defined(HASFPU) | |
4049 | case 1: | |
4050 | StoreFPR(coproc_reg,fmt_uninterpreted,memword); | |
4051 | break; | |
4052 | #endif /* HASFPU */ | |
4053 | ||
4054 | default: | |
f24b7b69 | 4055 | #if 0 /* this message should be controlled by a configuration option */ |
53b9417e | 4056 | callback->printf_filtered(callback,"COP_LD(%d,%d,0x%s) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(IPC)); |
f24b7b69 | 4057 | #endif |
8bae0a0c JSC |
4058 | break; |
4059 | } | |
4060 | ||
4061 | return; | |
4062 | } | |
4063 | ||
4064 | static unsigned int | |
4065 | COP_SW(coproc_num,coproc_reg) | |
4066 | int coproc_num, coproc_reg; | |
4067 | { | |
4068 | unsigned int value = 0; | |
da0bce9c ILT |
4069 | FP_formats hold; |
4070 | ||
8bae0a0c JSC |
4071 | switch (coproc_num) { |
4072 | #if defined(HASFPU) | |
4073 | case 1: | |
4074 | #if 1 | |
da0bce9c ILT |
4075 | hold = fpr_state[coproc_reg]; |
4076 | fpr_state[coproc_reg] = fmt_word; | |
8bae0a0c | 4077 | value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted); |
da0bce9c | 4078 | fpr_state[coproc_reg] = hold; |
8bae0a0c JSC |
4079 | #else |
4080 | #if 1 | |
4081 | value = (unsigned int)ValueFPR(coproc_reg,fpr_state[coproc_reg]); | |
4082 | #else | |
4083 | #ifdef DEBUG | |
4084 | printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(fpr_state[coproc_reg])); | |
4085 | #endif /* DEBUG */ | |
4086 | value = (unsigned int)ValueFPR(coproc_reg,fmt_single); | |
4087 | #endif | |
4088 | #endif | |
4089 | break; | |
4090 | #endif /* HASFPU */ | |
4091 | ||
4092 | default: | |
f24b7b69 | 4093 | #if 0 /* should be controlled by configuration option */ |
53b9417e | 4094 | callback->printf_filtered(callback,"COP_SW(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(IPC)); |
f24b7b69 | 4095 | #endif |
8bae0a0c JSC |
4096 | break; |
4097 | } | |
4098 | ||
4099 | return(value); | |
4100 | } | |
4101 | ||
e871dd18 | 4102 | static uword64 |
8bae0a0c JSC |
4103 | COP_SD(coproc_num,coproc_reg) |
4104 | int coproc_num, coproc_reg; | |
4105 | { | |
e871dd18 | 4106 | uword64 value = 0; |
8bae0a0c JSC |
4107 | switch (coproc_num) { |
4108 | #if defined(HASFPU) | |
4109 | case 1: | |
4110 | #if 1 | |
4111 | value = ValueFPR(coproc_reg,fmt_uninterpreted); | |
4112 | #else | |
4113 | #if 1 | |
4114 | value = ValueFPR(coproc_reg,fpr_state[coproc_reg]); | |
4115 | #else | |
4116 | #ifdef DEBUG | |
4117 | printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(fpr_state[coproc_reg])); | |
4118 | #endif /* DEBUG */ | |
4119 | value = ValueFPR(coproc_reg,fmt_double); | |
4120 | #endif | |
4121 | #endif | |
4122 | break; | |
4123 | #endif /* HASFPU */ | |
4124 | ||
4125 | default: | |
f24b7b69 | 4126 | #if 0 /* should be controlled by configuration option */ |
53b9417e | 4127 | callback->printf_filtered(callback,"COP_SD(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(IPC)); |
f24b7b69 | 4128 | #endif |
8bae0a0c JSC |
4129 | break; |
4130 | } | |
4131 | ||
4132 | return(value); | |
4133 | } | |
4134 | ||
4135 | static void | |
4136 | decode_coproc(instruction) | |
4137 | unsigned int instruction; | |
4138 | { | |
4139 | int coprocnum = ((instruction >> 26) & 3); | |
4140 | ||
4141 | switch (coprocnum) { | |
4142 | case 0: /* standard CPU control and cache registers */ | |
4143 | { | |
4144 | /* NOTEs: | |
4145 | Standard CP0 registers | |
4146 | 0 = Index R4000 VR4100 VR4300 | |
4147 | 1 = Random R4000 VR4100 VR4300 | |
4148 | 2 = EntryLo0 R4000 VR4100 VR4300 | |
4149 | 3 = EntryLo1 R4000 VR4100 VR4300 | |
4150 | 4 = Context R4000 VR4100 VR4300 | |
4151 | 5 = PageMask R4000 VR4100 VR4300 | |
4152 | 6 = Wired R4000 VR4100 VR4300 | |
4153 | 8 = BadVAddr R4000 VR4100 VR4300 | |
4154 | 9 = Count R4000 VR4100 VR4300 | |
4155 | 10 = EntryHi R4000 VR4100 VR4300 | |
4156 | 11 = Compare R4000 VR4100 VR4300 | |
4157 | 12 = SR R4000 VR4100 VR4300 | |
4158 | 13 = Cause R4000 VR4100 VR4300 | |
4159 | 14 = EPC R4000 VR4100 VR4300 | |
4160 | 15 = PRId R4000 VR4100 VR4300 | |
4161 | 16 = Config R4000 VR4100 VR4300 | |
4162 | 17 = LLAddr R4000 VR4100 VR4300 | |
4163 | 18 = WatchLo R4000 VR4100 VR4300 | |
4164 | 19 = WatchHi R4000 VR4100 VR4300 | |
4165 | 20 = XContext R4000 VR4100 VR4300 | |
4166 | 26 = PErr or ECC R4000 VR4100 VR4300 | |
4167 | 27 = CacheErr R4000 VR4100 | |
4168 | 28 = TagLo R4000 VR4100 VR4300 | |
4169 | 29 = TagHi R4000 VR4100 VR4300 | |
4170 | 30 = ErrorEPC R4000 VR4100 VR4300 | |
4171 | */ | |
4172 | int code = ((instruction >> 21) & 0x1F); | |
4173 | /* R4000 Users Manual (second edition) lists the following CP0 | |
4174 | instructions: | |
4175 | DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000) | |
4176 | DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000) | |
4177 | MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000) | |
4178 | MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000) | |
4179 | TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001) | |
4180 | TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010) | |
4181 | TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110) | |
4182 | TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000) | |
4183 | CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii) | |
4184 | ERET Exception return (VR4100 = 01000010000000000000000000011000) | |
4185 | */ | |
4186 | if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0)) { | |
4187 | int rt = ((instruction >> 16) & 0x1F); | |
4188 | int rd = ((instruction >> 11) & 0x1F); | |
4189 | if (code == 0x00) { /* MF : move from */ | |
f24b7b69 | 4190 | #if 0 /* message should be controlled by configuration option */ |
8bae0a0c | 4191 | callback->printf_filtered(callback,"Warning: MFC0 %d,%d not handled yet (architecture specific)\n",rt,rd); |
f24b7b69 | 4192 | #endif |
8bae0a0c JSC |
4193 | GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */ |
4194 | } else { /* MT : move to */ | |
4195 | /* CPR[0,rd] = GPR[rt]; */ | |
f24b7b69 | 4196 | #if 0 /* should be controlled by configuration option */ |
8bae0a0c | 4197 | callback->printf_filtered(callback,"Warning: MTC0 %d,%d not handled yet (architecture specific)\n",rt,rd); |
f24b7b69 | 4198 | #endif |
8bae0a0c JSC |
4199 | } |
4200 | } else | |
53b9417e | 4201 | sim_warning("Unrecognised COP0 instruction 0x%08X at IPC = 0x%s : No handler present",instruction,pr_addr(IPC)); |
e871dd18 | 4202 | /* TODO: When executing an ERET or RFE instruction we should |
8bae0a0c JSC |
4203 | clear LLBIT, to ensure that any out-standing atomic |
4204 | read/modify/write sequence fails. */ | |
4205 | } | |
4206 | break; | |
4207 | ||
4208 | case 2: /* undefined co-processor */ | |
53b9417e | 4209 | sim_warning("COP2 instruction 0x%08X at IPC = 0x%s : No handler present",instruction,pr_addr(IPC)); |
8bae0a0c JSC |
4210 | break; |
4211 | ||
4212 | case 1: /* should not occur (FPU co-processor) */ | |
4213 | case 3: /* should not occur (FPU co-processor) */ | |
4214 | SignalException(ReservedInstruction,instruction); | |
4215 | break; | |
4216 | } | |
4217 | ||
4218 | return; | |
4219 | } | |
4220 | ||
4221 | /*-- instruction simulation -------------------------------------------------*/ | |
4222 | ||
4223 | static void | |
4224 | simulate () | |
4225 | { | |
4226 | unsigned int pipeline_count = 1; | |
4227 | ||
4228 | #ifdef DEBUG | |
4229 | if (membank == NULL) { | |
4230 | printf("DBG: simulate() entered with no memory\n"); | |
4231 | exit(1); | |
4232 | } | |
4233 | #endif /* DEBUG */ | |
4234 | ||
4235 | #if 0 /* Disabled to check that everything works OK */ | |
4236 | /* The VR4300 seems to sign-extend the PC on its first | |
4237 | access. However, this may just be because it is currently | |
4238 | configured in 32bit mode. However... */ | |
4239 | PC = SIGNEXTEND(PC,32); | |
4240 | #endif | |
4241 | ||
4242 | /* main controlling loop */ | |
4243 | do { | |
4244 | /* Fetch the next instruction from the simulator memory: */ | |
e871dd18 JSC |
4245 | uword64 vaddr = (uword64)PC; |
4246 | uword64 paddr; | |
8bae0a0c | 4247 | int cca; |
53b9417e | 4248 | unsigned int instruction; /* uword64? what's this used for? FIXME! */ |
8bae0a0c JSC |
4249 | int dsstate = (state & simDELAYSLOT); |
4250 | ||
4251 | #ifdef DEBUG | |
4252 | { | |
4253 | printf("DBG: state = 0x%08X :",state); | |
4254 | if (state & simSTOP) printf(" simSTOP"); | |
4255 | if (state & simSTEP) printf(" simSTEP"); | |
4256 | if (state & simHALTEX) printf(" simHALTEX"); | |
4257 | if (state & simHALTIN) printf(" simHALTIN"); | |
4258 | if (state & simBE) printf(" simBE"); | |
53b9417e | 4259 | printf("\n"); |
8bae0a0c JSC |
4260 | } |
4261 | #endif /* DEBUG */ | |
4262 | ||
4263 | #ifdef DEBUG | |
4264 | if (dsstate) | |
53b9417e | 4265 | callback->printf_filtered(callback,"DBG: DSPC = 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
4266 | #endif /* DEBUG */ |
4267 | ||
6429b296 JW |
4268 | if (AddressTranslation(PC,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { |
4269 | if ((vaddr & 1) == 0) { | |
4270 | /* Copy the action of the LW instruction */ | |
4271 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
4272 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
4273 | uword64 value; | |
4274 | unsigned int byte; | |
4275 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
53b9417e | 4276 | LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL); |
6429b296 JW |
4277 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); |
4278 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
4279 | } else { | |
4280 | /* Copy the action of the LH instruction */ | |
4281 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0); | |
4282 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0); | |
4283 | uword64 value; | |
4284 | unsigned int byte; | |
4285 | paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK) | |
4286 | | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1))); | |
53b9417e | 4287 | LoadMemory(&value,NULL,cca, AccessLength_HALFWORD, |
6429b296 JW |
4288 | paddr & ~ (uword64) 1, |
4289 | vaddr, isINSTRUCTION, isREAL); | |
4290 | byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1)); | |
4291 | instruction = ((value >> (8 * byte)) & 0xFFFF); | |
4292 | } | |
8bae0a0c | 4293 | } else { |
53b9417e | 4294 | fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC)); |
8bae0a0c JSC |
4295 | exit(1); |
4296 | } | |
4297 | ||
4298 | #ifdef DEBUG | |
53b9417e | 4299 | callback->printf_filtered(callback,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC)); |
8bae0a0c JSC |
4300 | #endif /* DEBUG */ |
4301 | ||
4302 | #if !defined(FASTSIM) || defined(PROFILE) | |
4303 | instruction_fetches++; | |
a9f7253f JSC |
4304 | /* Since we increment above, the value should only ever be zero if |
4305 | we have just overflowed: */ | |
4306 | if (instruction_fetches == 0) | |
4307 | instruction_fetch_overflow++; | |
8bae0a0c JSC |
4308 | #if defined(PROFILE) |
4309 | if ((state & simPROFILE) && ((instruction_fetches % profile_frequency) == 0) && profile_hist) { | |
e3d12c65 | 4310 | unsigned n = ((unsigned int)(PC - profile_minpc) >> (profile_shift + 2)); |
8bae0a0c JSC |
4311 | if (n < profile_nsamples) { |
4312 | /* NOTE: The counts for the profiling bins are only 16bits wide */ | |
4313 | if (profile_hist[n] != USHRT_MAX) | |
4314 | (profile_hist[n])++; | |
4315 | } | |
4316 | } | |
4317 | #endif /* PROFILE */ | |
4318 | #endif /* !FASTSIM && PROFILE */ | |
4319 | ||
4320 | IPC = PC; /* copy PC for this instruction */ | |
4321 | /* This is required by exception processing, to ensure that we can | |
4322 | cope with exceptions in the delay slots of branches that may | |
4323 | already have changed the PC. */ | |
6429b296 JW |
4324 | if ((vaddr & 1) == 0) |
4325 | PC += 4; /* increment ready for the next fetch */ | |
4326 | else | |
4327 | PC += 2; | |
8bae0a0c JSC |
4328 | /* NOTE: If we perform a delay slot change to the PC, this |
4329 | increment is not requuired. However, it would make the | |
4330 | simulator more complicated to try and avoid this small hit. */ | |
4331 | ||
4332 | /* Currently this code provides a simple model. For more | |
4333 | complicated models we could perform exception status checks at | |
4334 | this point, and set the simSTOP state as required. This could | |
4335 | also include processing any hardware interrupts raised by any | |
4336 | I/O model attached to the simulator context. | |
4337 | ||
4338 | Support for "asynchronous" I/O events within the simulated world | |
4339 | could be providing by managing a counter, and calling a I/O | |
4340 | specific handler when a particular threshold is reached. On most | |
4341 | architectures a decrement and check for zero operation is | |
4342 | usually quicker than an increment and compare. However, the | |
4343 | process of managing a known value decrement to zero, is higher | |
4344 | than the cost of using an explicit value UINT_MAX into the | |
4345 | future. Which system is used will depend on how complicated the | |
4346 | I/O model is, and how much it is likely to affect the simulator | |
4347 | bandwidth. | |
4348 | ||
4349 | If events need to be scheduled further in the future than | |
4350 | UINT_MAX event ticks, then the I/O model should just provide its | |
4351 | own counter, triggered from the event system. */ | |
4352 | ||
4353 | /* MIPS pipeline ticks. To allow for future support where the | |
4354 | pipeline hit of individual instructions is known, this control | |
4355 | loop manages a "pipeline_count" variable. It is initialised to | |
4356 | 1 (one), and will only be changed by the simulator engine when | |
4357 | executing an instruction. If the engine does not have access to | |
4358 | pipeline cycle count information then all instructions will be | |
4359 | treated as using a single cycle. NOTE: A standard system is not | |
4360 | provided by the default simulator because different MIPS | |
4361 | architectures have different cycle counts for the same | |
4362 | instructions. */ | |
4363 | ||
4364 | #if defined(HASFPU) | |
4365 | /* Set previous flag, depending on current: */ | |
4366 | if (state & simPCOC0) | |
4367 | state |= simPCOC1; | |
4368 | else | |
4369 | state &= ~simPCOC1; | |
4370 | /* and update the current value: */ | |
4371 | if (GETFCC(0)) | |
4372 | state |= simPCOC0; | |
4373 | else | |
4374 | state &= ~simPCOC0; | |
4375 | #endif /* HASFPU */ | |
4376 | ||
4377 | /* NOTE: For multi-context simulation environments the "instruction" | |
4378 | variable should be local to this routine. */ | |
4379 | ||
4380 | /* Shorthand accesses for engine. Note: If we wanted to use global | |
4381 | variables (and a single-threaded simulator engine), then we can | |
4382 | create the actual variables with these names. */ | |
4383 | ||
4384 | if (!(state & simSKIPNEXT)) { | |
4385 | /* Include the simulator engine */ | |
4386 | #include "engine.c" | |
f24b7b69 | 4387 | #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT) |
8bae0a0c JSC |
4388 | #error "Mismatch between run-time simulator code and simulation engine" |
4389 | #endif | |
4390 | ||
4391 | #if defined(WARN_LOHI) | |
4392 | /* Decrement the HI/LO validity ticks */ | |
4393 | if (HIACCESS > 0) | |
4394 | HIACCESS--; | |
4395 | if (LOACCESS > 0) | |
4396 | LOACCESS--; | |
53b9417e DE |
4397 | if (HI1ACCESS > 0) |
4398 | HI1ACCESS--; | |
4399 | if (LO1ACCESS > 0) | |
4400 | LO1ACCESS--; | |
8bae0a0c JSC |
4401 | #endif /* WARN_LOHI */ |
4402 | ||
4403 | #if defined(WARN_ZERO) | |
4404 | /* For certain MIPS architectures, GPR[0] is hardwired to zero. We | |
4405 | should check for it being changed. It is better doing it here, | |
4406 | than within the simulator, since it will help keep the simulator | |
4407 | small. */ | |
4408 | if (ZERO != 0) { | |
53b9417e | 4409 | sim_warning("The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)",pr_addr(ZERO),pr_addr(IPC)); |
8bae0a0c JSC |
4410 | ZERO = 0; /* reset back to zero before next instruction */ |
4411 | } | |
4412 | #endif /* WARN_ZERO */ | |
4413 | } else /* simSKIPNEXT check */ | |
4414 | state &= ~simSKIPNEXT; | |
4415 | ||
4416 | /* If the delay slot was active before the instruction is | |
4417 | executed, then update the PC to its new value: */ | |
4418 | if (dsstate) { | |
4419 | #ifdef DEBUG | |
53b9417e | 4420 | printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
4421 | #endif /* DEBUG */ |
4422 | PC = DSPC; | |
aaff8437 | 4423 | state &= ~(simDELAYSLOT | simJALDELAYSLOT); |
8bae0a0c JSC |
4424 | } |
4425 | ||
4426 | if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */ | |
4427 | /* Deal with pending register updates: */ | |
4428 | #ifdef DEBUG | |
4429 | printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total); | |
4430 | #endif /* DEBUG */ | |
4431 | if (pending_out != pending_in) { | |
4432 | int loop; | |
4433 | int index = pending_out; | |
4434 | int total = pending_total; | |
4435 | if (pending_total == 0) { | |
4436 | fprintf(stderr,"FATAL: Mis-match on pending update pointers\n"); | |
4437 | exit(1); | |
4438 | } | |
4439 | for (loop = 0; (loop < total); loop++) { | |
4440 | #ifdef DEBUG | |
4441 | printf("DBG: BEFORE index = %d, loop = %d\n",index,loop); | |
4442 | #endif /* DEBUG */ | |
4443 | if (pending_slot_reg[index] != (LAST_EMBED_REGNUM + 1)) { | |
4444 | #ifdef DEBUG | |
4445 | printf("pending_slot_count[%d] = %d\n",index,pending_slot_count[index]); | |
4446 | #endif /* DEBUG */ | |
4447 | if (--(pending_slot_count[index]) == 0) { | |
4448 | #ifdef DEBUG | |
4449 | printf("pending_slot_reg[%d] = %d\n",index,pending_slot_reg[index]); | |
53b9417e | 4450 | printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(pending_slot_value[index])); |
8bae0a0c JSC |
4451 | #endif /* DEBUG */ |
4452 | if (pending_slot_reg[index] == COCIDX) { | |
4453 | SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0)); | |
4454 | } else { | |
4455 | registers[pending_slot_reg[index]] = pending_slot_value[index]; | |
4456 | #if defined(HASFPU) | |
4457 | /* The only time we have PENDING updates to FPU | |
4458 | registers, is when performing binary transfers. This | |
4459 | means we should update the register type field. */ | |
4460 | if ((pending_slot_reg[index] >= FGRIDX) && (pending_slot_reg[index] < (FGRIDX + 32))) | |
7e6c297e | 4461 | fpr_state[pending_slot_reg[index] - FGRIDX] = fmt_uninterpreted; |
8bae0a0c JSC |
4462 | #endif /* HASFPU */ |
4463 | } | |
4464 | #ifdef DEBUG | |
53b9417e | 4465 | printf("registers[%d] = 0x%s\n",pending_slot_reg[index],pr_addr(registers[pending_slot_reg[index]])); |
8bae0a0c JSC |
4466 | #endif /* DEBUG */ |
4467 | pending_slot_reg[index] = (LAST_EMBED_REGNUM + 1); | |
4468 | pending_out++; | |
4469 | if (pending_out == PSLOTS) | |
4470 | pending_out = 0; | |
4471 | pending_total--; | |
4472 | } | |
4473 | } | |
4474 | #ifdef DEBUG | |
4475 | printf("DBG: AFTER index = %d, loop = %d\n",index,loop); | |
4476 | #endif /* DEBUG */ | |
4477 | index++; | |
4478 | if (index == PSLOTS) | |
4479 | index = 0; | |
4480 | } | |
4481 | } | |
4482 | #ifdef DEBUG | |
4483 | printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total); | |
4484 | #endif /* DEBUG */ | |
4485 | } | |
4486 | ||
4487 | #if !defined(FASTSIM) | |
4488 | pipeline_ticks += pipeline_count; | |
4489 | #endif /* FASTSIM */ | |
4490 | ||
4491 | if (state & simSTEP) | |
4492 | state |= simSTOP; | |
4493 | } while (!(state & simSTOP)); | |
4494 | ||
4495 | #ifdef DEBUG | |
4496 | if (membank == NULL) { | |
4497 | printf("DBG: simulate() LEAVING with no memory\n"); | |
4498 | exit(1); | |
4499 | } | |
4500 | #endif /* DEBUG */ | |
4501 | ||
4502 | return; | |
4503 | } | |
4504 | ||
53b9417e DE |
4505 | /* This code copied from gdb's utils.c. Would like to share this code, |
4506 | but don't know of a common place where both could get to it. */ | |
4507 | ||
4508 | /* Temporary storage using circular buffer */ | |
4509 | #define NUMCELLS 16 | |
4510 | #define CELLSIZE 32 | |
4511 | static char* | |
4512 | get_cell() | |
4513 | { | |
4514 | static char buf[NUMCELLS][CELLSIZE]; | |
4515 | static int cell=0; | |
4516 | if (++cell>=NUMCELLS) cell=0; | |
4517 | return buf[cell]; | |
4518 | } | |
4519 | ||
4520 | /* Print routines to handle variable size regs, etc */ | |
4521 | ||
4522 | /* Eliminate warning from compiler on 32-bit systems */ | |
4523 | static int thirty_two = 32; | |
4524 | ||
4525 | char* | |
4526 | pr_addr(addr) | |
4527 | SIM_ADDR addr; | |
4528 | { | |
4529 | char *paddr_str=get_cell(); | |
4530 | switch (sizeof(addr)) | |
4531 | { | |
4532 | case 8: | |
4533 | sprintf(paddr_str,"%08x%08x", | |
4534 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); | |
4535 | break; | |
4536 | case 4: | |
4537 | sprintf(paddr_str,"%08x",(unsigned long)addr); | |
4538 | break; | |
4539 | case 2: | |
4540 | sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff)); | |
4541 | break; | |
4542 | default: | |
4543 | sprintf(paddr_str,"%x",addr); | |
4544 | } | |
4545 | return paddr_str; | |
4546 | } | |
4547 | ||
87e43259 AC |
4548 | char* |
4549 | pr_uword64(addr) | |
4550 | uword64 addr; | |
4551 | { | |
4552 | char *paddr_str=get_cell(); | |
4553 | sprintf(paddr_str,"%08x%08x", | |
4554 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); | |
4555 | return paddr_str; | |
4556 | } | |
4557 | ||
4558 | ||
8bae0a0c JSC |
4559 | /*---------------------------------------------------------------------------*/ |
4560 | /*> EOF interp.c <*/ |