projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* monitor.h (MO_PRINT_PROGRAM_OUTPUT): Define.
[deliverable/binutils-gdb.git] / sim / mips / interp.c
CommitLineData
8bae0a0c
JSC		 1/*> interp.c <*/
2/* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 $Revision$
17 $Author$
e3d12c65 18 $Date$
8bae0a0c
JSC		 19
20NOTEs:
21
8bae0a0c
JSC		 22The IDT monitor (found on the VR4300 board), seems to lie about
23register contents. It seems to treat the registers as sign-extended
2432-bit values. This cause *REAL* problems when single-stepping 64-bit
25code on the hardware.
26
27*/
28
e2f8ffb7
AC		 29/* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
8bae0a0c
JSC		 32#if 1 /* 0 to allow user build selection, 1 to force inclusion */
33#define TRACE (1)
8bae0a0c
JSC		 34#endif
35
2e61a3ad
AC		 36#include "bfd.h"
37#include "sim-main.h"
38#include "sim-utils.h"
39#include "sim-options.h"
50a2a691 40#include "sim-assert.h"
2e61a3ad 41
4fa134be
ILT		 42#include "config.h"
43
8bae0a0c
JSC		 44#include <stdio.h>
45#include <stdarg.h>
46#include <ansidecl.h>
8bae0a0c
JSC		 47#include <ctype.h>
48#include <limits.h>
49#include <math.h>
4fa134be
ILT		 50#ifdef HAVE_STDLIB_H
51#include <stdlib.h>
52#endif
53#ifdef HAVE_STRING_H
54#include <string.h>
55#else
56#ifdef HAVE_STRINGS_H
57#include <strings.h>
58#endif
59#endif
8bae0a0c
JSC		 60
61#include "getopt.h"
62#include "libiberty.h"
9d52bcb7 63#include "bfd.h"
8bae0a0c 64#include "callback.h" /* GDB simulator callback interface */
e3d12c65 65#include "remote-sim.h" /* GDB simulator interface */
8bae0a0c 66
f24b7b69
JSC		 67#include "sysdep.h"
68
53b9417e
DE		 69#ifndef PARAMS
70#define PARAMS(x)
71#endif
72
73char* pr_addr PARAMS ((SIM_ADDR addr));
87e43259 74char* pr_uword64 PARAMS ((uword64 addr));
53b9417e 75
f24b7b69 76
8bae0a0c
JSC		 77/* Get the simulator engine description, without including the code: */
78#define SIM_MANIFESTS
284e759d 79#include "oengine.c"
8bae0a0c
JSC		 80#undef SIM_MANIFESTS
81
f7481d45 82
8bae0a0c
JSC		 83/* The following reserved instruction value is used when a simulator
84 trap is required. NOTE: Care must be taken, since this value may be
85 used in later revisions of the MIPS ISA. */
53b9417e
DE		 86#define RSVD_INSTRUCTION (0x00000005)
87#define RSVD_INSTRUCTION_MASK (0xFC00003F)
88
89#define RSVD_INSTRUCTION_ARG_SHIFT 6
90#define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
91
8bae0a0c 92
6eedf3f4
MA		 93/* Bits in the Debug register */
94#define Debug_DBD 0x80000000 /* Debug Branch Delay */
95#define Debug_DM 0x40000000 /* Debug Mode */
96#define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
97
98
99
8bae0a0c 100
8bae0a0c 101
e3d12c65
DE		 102/*---------------------------------------------------------------------------*/
103/*-- GDB simulator interface ------------------------------------------------*/
104/*---------------------------------------------------------------------------*/
105
0c2c5f61 106static void ColdReset PARAMS((SIM_DESC sd));
e3d12c65
DE		 107
108/*---------------------------------------------------------------------------*/
109
8bae0a0c 110
8bae0a0c 111
8bae0a0c 112#define DELAYSLOT() {\
0c2c5f61 113 if (STATE & simDELAYSLOT)\
18c64df6 114 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
0c2c5f61 115 STATE |= simDELAYSLOT;\
8bae0a0c
JSC		 116 }
117
aaff8437
ILT		 118#define JALDELAYSLOT() {\
119 DELAYSLOT ();\
0c2c5f61 120 STATE |= simJALDELAYSLOT;\
aaff8437
ILT		 121 }
122
8bae0a0c 123#define NULLIFY() {\
0c2c5f61
AC		 124 STATE &= ~simDELAYSLOT;\
125 STATE |= simSKIPNEXT;\
8bae0a0c
JSC		 126 }
127
6eedf3f4 128#define CANCELDELAYSLOT() {\
0c2c5f61
AC		 129 DSSTATE = 0;\
130 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
6eedf3f4
MA		 131 }
132
0c2c5f61
AC		 133#define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
134#define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
aaff8437 135
a9f7253f
JSC		 136#define K0BASE (0x80000000)
137#define K0SIZE (0x20000000)
138#define K1BASE (0xA0000000)
139#define K1SIZE (0x20000000)
525d929e
AC		 140#define MONITOR_BASE (0xBFC00000)
141#define MONITOR_SIZE (1 << 11)
142#define MEM_SIZE (2 << 20)
a9f7253f 143
8bae0a0c 144#if defined(TRACE)
4fa134be 145static char *tracefile = "trace.din"; /* default filename for trace log */
030843d7 146FILE *tracefh = NULL;
18c64df6 147static void open_trace PARAMS((SIM_DESC sd));
8bae0a0c
JSC		 148#endif /* TRACE */
149
22de994d
AC		 150#define OPTION_DINERO_TRACE 200
151#define OPTION_DINERO_FILE 201
152
50a2a691
AC		 153static SIM_RC
154mips_option_handler (sd, opt, arg)
155 SIM_DESC sd;
156 int opt;
157 char *arg;
2e61a3ad 158{
50a2a691
AC		 159 switch (opt)
160 {
22de994d 161 case OPTION_DINERO_TRACE: /* ??? */
50a2a691
AC		 162#if defined(TRACE)
163 /* Eventually the simTRACE flag could be treated as a toggle, to
164 allow external control of the program points being traced
165 (i.e. only from main onwards, excluding the run-time setup,
166 etc.). */
167 if (arg == NULL)
0c2c5f61 168 STATE |= simTRACE;
50a2a691 169 else if (strcmp (arg, "yes") == 0)
0c2c5f61 170 STATE |= simTRACE;
50a2a691 171 else if (strcmp (arg, "no") == 0)
0c2c5f61 172 STATE &= ~simTRACE;
22de994d
AC		 173 else if (strcmp (arg, "on") == 0)
174 STATE |= simTRACE;
175 else if (strcmp (arg, "off") == 0)
176 STATE &= ~simTRACE;
50a2a691
AC		 177 else
178 {
22de994d 179 fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg);
50a2a691
AC		 180 return SIM_RC_FAIL;
181 }
182 return SIM_RC_OK;
183#else /* !TRACE */
184 fprintf(stderr,"\
22de994d 185Simulator constructed without dinero tracing support (for performance).\n\
50a2a691
AC		 186Re-compile simulator with \"-DTRACE\" to enable this option.\n");
187 return SIM_RC_FAIL;
188#endif /* !TRACE */
189
22de994d 190 case OPTION_DINERO_FILE:
50a2a691
AC		 191#if defined(TRACE)
192 if (optarg != NULL) {
193 char *tmp;
194 tmp = (char *)malloc(strlen(optarg) + 1);
195 if (tmp == NULL)
196 {
18c64df6 197 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
50a2a691
AC		 198 return SIM_RC_FAIL;
199 }
200 else {
201 strcpy(tmp,optarg);
202 tracefile = tmp;
18c64df6 203 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
50a2a691
AC		 204 }
205 }
206#endif /* TRACE */
207 return SIM_RC_OK;
208
50a2a691
AC		 209 }
210
211 return SIM_RC_OK;
2e61a3ad 212}
50a2a691
AC		 213
214static const OPTION mips_options[] =
2e61a3ad 215{
22de994d
AC		 216 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
217 '\0', "on|off", "Enable dinero tracing",
50a2a691 218 mips_option_handler },
22de994d
AC		 219 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
220 '\0', "FILE", "Write dinero trace to FILE",
50a2a691 221 mips_option_handler },
50a2a691
AC		 222 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
223};
224
225
56e7c849
AC		 226int interrupt_pending;
227
50a2a691
AC		 228static void
229interrupt_event (SIM_DESC sd, void *data)
2e61a3ad 230{
56e7c849
AC		 231 if (SR & status_IE)
232 {
233 interrupt_pending = 0;
18c64df6 234 SignalExceptionInterrupt ();
56e7c849
AC		 235 }
236 else if (!interrupt_pending)
237 sim_events_schedule (sd, 1, interrupt_event, data);
2e61a3ad 238}
f7481d45 239
f7481d45 240
50a2a691 241
8bae0a0c
JSC		 242/*---------------------------------------------------------------------------*/
243/*-- GDB simulator interface ------------------------------------------------*/
244/*---------------------------------------------------------------------------*/
245
53b9417e 246SIM_DESC
247fccde 247sim_open (kind, cb, abfd, argv)
87e43259 248 SIM_OPEN_KIND kind;
50a2a691 249 host_callback *cb;
247fccde 250 struct _bfd *abfd;
53b9417e 251 char **argv;
8bae0a0c 252{
18c64df6 253 SIM_DESC sd = sim_state_alloc (kind, cb);
0c2c5f61 254 sim_cpu *cpu = STATE_CPU (sd, 0);
2e61a3ad 255
525d929e
AC		 256 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
257
50a2a691
AC		 258 /* FIXME: watchpoints code shouldn't need this */
259 STATE_WATCHPOINTS (sd)->pc = &(PC);
260 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
261 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
262
0c2c5f61 263 STATE = 0;
50a2a691 264
2e61a3ad
AC		 265 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
266 return 0;
50a2a691 267 sim_add_option_table (sd, mips_options);
2e61a3ad 268
63be8feb
AC		 269 /* Allocate core managed memory */
270
271 /* the monitor */
272 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
273 /* For compatibility with the old code - under this (at level one)
274 are the kernel spaces K0 & K1. Both of these map to a single
275 smaller sub region */
276 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
277 K1BASE, K0SIZE,
278 MEM_SIZE, /* actual size */
279 K0BASE);
280
2e61a3ad
AC		 281 /* getopt will print the error message so we just have to exit if this fails.
282 FIXME: Hmmm... in the case of gdb we need getopt to call
283 print_filtered. */
284 if (sim_parse_args (sd, argv) != SIM_RC_OK)
285 {
286 /* Uninstall the modules to avoid memory leaks,
287 file descriptor leaks, etc. */
288 sim_module_uninstall (sd);
289 return 0;
290 }
2e61a3ad 291
fafce69a
AC		 292 /* check for/establish the a reference program image */
293 if (sim_analyze_program (sd,
294 (STATE_PROG_ARGV (sd) != NULL
295 ? *STATE_PROG_ARGV (sd)
296 : NULL),
297 abfd) != SIM_RC_OK)
298 {
299 sim_module_uninstall (sd);
300 return 0;
301 }
302
247fccde
AC		 303 /* Configure/verify the target byte order and other runtime
304 configuration options */
fafce69a 305 if (sim_config (sd) != SIM_RC_OK)
247fccde
AC		 306 {
307 sim_module_uninstall (sd);
308 return 0;
309 }
310
2e61a3ad
AC		 311 if (sim_post_argv_init (sd) != SIM_RC_OK)
312 {
313 /* Uninstall the modules to avoid memory leaks,
314 file descriptor leaks, etc. */
315 sim_module_uninstall (sd);
316 return 0;
317 }
318
50a2a691
AC		 319 /* verify assumptions the simulator made about the host type system.
320 This macro does not return if there is a problem */
7ce8b917
AC		 321 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
322 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
8bae0a0c 323
8bae0a0c
JSC		 324#if defined(HASFPU)
325 /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
326 and DOUBLE binary formats. This is a bit nasty, requiring that we
327 trust the explicit manifests held in the source: */
50a2a691
AC		 328 /* TODO: We need to cope with the simulated target and the host not
329 having the same endianness. This will require the high and low
330 words of a (double) to be swapped when converting between the
331 host and the simulated target. */
8bae0a0c 332 {
50a2a691
AC		 333 union {
334 unsigned int i[2];
335 double d;
336 float f[2];
337 } s;
338
339 s.d = (double)523.2939453125;
340
341 if ((s.i[0] == 0 && (s.f[1] != (float)4.01102924346923828125
342 || s.i[1] != 0x40805A5A))
343 || (s.i[1] == 0 && (s.f[0] != (float)4.01102924346923828125
344 || s.i[0] != 0x40805A5A)))
345 {
346 fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
347 return 0;
348 }
8bae0a0c
JSC		 349 }
350#endif /* HASFPU */
351
352 /* This is NASTY, in that we are assuming the size of specific
353 registers: */
354 {
355 int rn;
356 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) {
357 if (rn < 32)
0c2c5f61 358 cpu->register_widths[rn] = GPRLEN;
8bae0a0c 359 else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32)))
0c2c5f61 360 cpu->register_widths[rn] = GPRLEN;
8bae0a0c 361 else if ((rn >= 33) && (rn <= 37))
0c2c5f61 362 cpu->register_widths[rn] = GPRLEN;
8bae0a0c 363 else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89)))
0c2c5f61 364 cpu->register_widths[rn] = 32;
8bae0a0c 365 else
0c2c5f61 366 cpu->register_widths[rn] = 0;
8bae0a0c 367 }
18c64df6
AC		 368 /* start-sanitize-r5900 */
369
370 /* set the 5900 "upper" registers to 64 bits */
371 for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
0c2c5f61 372 cpu->register_widths[rn] = 64;
18c64df6 373 /* end-sanitize-r5900 */
8bae0a0c
JSC		 374 }
375
8bae0a0c 376#if defined(TRACE)
0c2c5f61 377 if (STATE & simTRACE)
18c64df6 378 open_trace(sd);
8bae0a0c
JSC		 379#endif /* TRACE */
380
fafce69a
AC		 381 /* Write the monitor trap address handlers into the monitor (eeprom)
382 address space. This can only be done once the target endianness
383 has been determined. */
384 {
385 unsigned loop;
386 /* Entry into the IDT monitor is via fixed address vectors, and
387 not using machine instructions. To avoid clashing with use of
388 the MIPS TRAP system, we place our own (simulator specific)
389 "undefined" instructions into the relevant vector slots. */
525d929e
AC		 390 for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
391 {
392 address_word vaddr = (MONITOR_BASE + loop);
393 unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
394 H2T (insn);
395 sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
396 }
fafce69a
AC		 397 /* The PMON monitor uses the same address space, but rather than
398 branching into it the address of a routine is loaded. We can
399 cheat for the moment, and direct the PMON routine to IDT style
400 instructions within the monitor space. This relies on the IDT
401 monitor not using the locations from 0xBFC00500 onwards as its
402 entry points.*/
403 for (loop = 0; (loop < 24); loop++)
404 {
525d929e
AC		 405 address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
406 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
fafce69a
AC		 407 switch (loop)
408 {
409 case 0: /* read */
410 value = 7;
411 break;
fafce69a
AC		 412 case 1: /* write */
413 value = 8;
414 break;
fafce69a
AC		 415 case 2: /* open */
416 value = 6;
417 break;
fafce69a
AC		 418 case 3: /* close */
419 value = 10;
420 break;
fafce69a
AC		 421 case 5: /* printf */
422 value = ((0x500 - 16) / 8); /* not an IDT reason code */
423 break;
fafce69a
AC		 424 case 8: /* cliexit */
425 value = 17;
426 break;
fafce69a
AC		 427 case 11: /* flush_cache */
428 value = 28;
429 break;
430 }
525d929e
AC		 431 /* FIXME - should monitor_base be SIM_ADDR?? */
432 value = ((unsigned int)MONITOR_BASE + (value * 8));
433 H2T (value);
434 sim_write (sd, vaddr, (char *)&value, sizeof (value));
fafce69a
AC		 435
436 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
437 vaddr -= 0x300;
525d929e 438 sim_write (sd, vaddr, (char *)&value, sizeof (value));
fafce69a
AC		 439 }
440 }
441
2e61a3ad 442 return sd;
8bae0a0c
JSC		 443}
444
6429b296
JW		 445#if defined(TRACE)
446static void
18c64df6
AC		 447open_trace(sd)
448 SIM_DESC sd;
6429b296
JW		 449{
450 tracefh = fopen(tracefile,"wb+");
451 if (tracefh == NULL)
452 {
18c64df6 453 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
6429b296
JW		 454 tracefh = stderr;
455 }
456}
457#endif /* TRACE */
458
8bae0a0c 459void
53b9417e
DE		 460sim_close (sd, quitting)
461 SIM_DESC sd;
8bae0a0c
JSC		 462 int quitting;
463{
464#ifdef DEBUG
465 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
466#endif
467
8bae0a0c
JSC		 468 /* "quitting" is non-zero if we cannot hang on errors */
469
470 /* Ensure that any resources allocated through the callback
471 mechanism are released: */
18c64df6 472 sim_io_shutdown (sd);
8bae0a0c 473
8bae0a0c 474#if defined(TRACE)
e3d12c65 475 if (tracefh != NULL && tracefh != stderr)
8bae0a0c 476 fclose(tracefh);
e3d12c65 477 tracefh = NULL;
0c2c5f61 478 STATE &= ~simTRACE;
8bae0a0c
JSC		 479#endif /* TRACE */
480
8bae0a0c
JSC		 481 return;
482}
483
8bae0a0c
JSC		 484
485int
53b9417e
DE		 486sim_write (sd,addr,buffer,size)
487 SIM_DESC sd;
8bae0a0c
JSC		 488 SIM_ADDR addr;
489 unsigned char *buffer;
490 int size;
491{
525d929e 492 int index;
8bae0a0c
JSC		 493
494 /* Return the number of bytes written, or zero if error. */
495#ifdef DEBUG
18c64df6 496 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
8bae0a0c
JSC		 497#endif
498
525d929e
AC		 499 /* We use raw read and write routines, since we do not want to count
500 the GDB memory accesses in our statistics gathering. */
501
502 for (index = 0; index < size; index++)
503 {
504 address_word vaddr = (address_word)addr + index;
505 address_word paddr;
506 int cca;
7ce8b917 507 if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
525d929e 508 break;
63be8feb
AC		 509 if (sim_core_write_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1)
510 break;
8bae0a0c 511 }
8bae0a0c 512
525d929e 513 return(index);
8bae0a0c
JSC		 514}
515
516int
53b9417e
DE		 517sim_read (sd,addr,buffer,size)
518 SIM_DESC sd;
8bae0a0c
JSC		 519 SIM_ADDR addr;
520 unsigned char *buffer;
521 int size;
522{
523 int index;
524
525 /* Return the number of bytes read, or zero if error. */
526#ifdef DEBUG
18c64df6 527 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
8bae0a0c
JSC		 528#endif /* DEBUG */
529
525d929e
AC		 530 for (index = 0; (index < size); index++)
531 {
532 address_word vaddr = (address_word)addr + index;
533 address_word paddr;
525d929e 534 int cca;
7ce8b917 535 if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
525d929e 536 break;
63be8feb
AC		 537 if (sim_core_read_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1)
538 break;
525d929e 539 }
8bae0a0c
JSC		 540
541 return(index);
542}
543
544void
53b9417e
DE		 545sim_store_register (sd,rn,memory)
546 SIM_DESC sd;
8bae0a0c
JSC		 547 int rn;
548 unsigned char *memory;
549{
0c2c5f61 550 sim_cpu *cpu = STATE_CPU (sd, 0);
50a2a691
AC		 551 /* NOTE: gdb (the client) stores registers in target byte order
552 while the simulator uses host byte order */
8bae0a0c 553#ifdef DEBUG
18c64df6 554 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
8bae0a0c
JSC		 555#endif /* DEBUG */
556
557 /* Unfortunately this suffers from the same problem as the register
558 numbering one. We need to know what the width of each logical
559 register number is for the architecture being simulated. */
50a2a691 560
0c2c5f61 561 if (cpu->register_widths[rn] == 0)
18c64df6
AC		 562 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
563 /* start-sanitize-r5900 */
564 else if (rn == REGISTER_SA)
565 SA = T2H_8(*(uword64*)memory);
566 else if (rn > LAST_EMBED_REGNUM)
0c2c5f61 567 cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(uword64*)memory);
18c64df6 568 /* end-sanitize-r5900 */
0c2c5f61
AC		 569 else if (cpu->register_widths[rn] == 32)
570 cpu->registers[rn] = T2H_4 (*(unsigned int*)memory);
50a2a691 571 else
0c2c5f61 572 cpu->registers[rn] = T2H_8 (*(uword64*)memory);
8bae0a0c
JSC		 573
574 return;
575}
576
577void
53b9417e
DE		 578sim_fetch_register (sd,rn,memory)
579 SIM_DESC sd;
8bae0a0c
JSC		 580 int rn;
581 unsigned char *memory;
582{
0c2c5f61 583 sim_cpu *cpu = STATE_CPU (sd, 0);
50a2a691
AC		 584 /* NOTE: gdb (the client) stores registers in target byte order
585 while the simulator uses host byte order */
8bae0a0c 586#ifdef DEBUG
18c64df6 587 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
8bae0a0c
JSC		 588#endif /* DEBUG */
589
0c2c5f61 590 if (cpu->register_widths[rn] == 0)
18c64df6
AC		 591 sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn);
592 /* start-sanitize-r5900 */
593 else if (rn == REGISTER_SA)
594 *((uword64 *)memory) = H2T_8(SA);
595 else if (rn > LAST_EMBED_REGNUM)
0c2c5f61 596 *((uword64 *)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]);
18c64df6 597 /* end-sanitize-r5900 */
0c2c5f61
AC		 598 else if (cpu->register_widths[rn] == 32)
599 *((unsigned int *)memory) = H2T_4 ((unsigned int)(cpu->registers[rn] & 0xFFFFFFFF));
18c64df6 600 else /* 64bit register */
0c2c5f61 601 *((uword64 *)memory) = H2T_8 (cpu->registers[rn]);
50a2a691 602
8bae0a0c
JSC		 603 return;
604}
50a2a691 605
8bae0a0c
JSC		 606
607void
53b9417e
DE		 608sim_info (sd,verbose)
609 SIM_DESC sd;
8bae0a0c
JSC		 610 int verbose;
611{
612 /* Accessed from the GDB "info files" command: */
56e7c849
AC		 613 if (STATE_VERBOSE_P (sd) || verbose)
614 {
615
616 sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n",
617 (PROCESSOR_64BIT ? 64 : 32),
618 (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little"));
619
8bae0a0c 620#if !defined(FASTSIM)
56e7c849
AC		 621 /* It would be a useful feature, if when performing multi-cycle
622 simulations (rather than single-stepping) we keep the start and
623 end times of the execution, so that we can give a performance
624 figure for the simulator. */
8bae0a0c 625#endif /* !FASTSIM */
56e7c849
AC		 626 sim_io_printf (sd, "Number of execution cycles = %ld\n",
627 (long) sim_events_time (sd));
628
629 /* print information pertaining to MIPS ISA and architecture being simulated */
630 /* things that may be interesting */
631 /* instructions executed - if available */
632 /* cycles executed - if available */
633 /* pipeline stalls - if available */
634 /* virtual time taken */
635 /* profiling size */
636 /* profiling frequency */
637 /* profile minpc */
638 /* profile maxpc */
639 }
aa324b9b 640 profile_print (sd, STATE_VERBOSE_P (sd), NULL, NULL);
8bae0a0c
JSC		 641}
642
8bae0a0c 643
9d52bcb7 644SIM_RC
fafce69a 645sim_create_inferior (sd, abfd, argv,env)
53b9417e 646 SIM_DESC sd;
fafce69a 647 struct _bfd *abfd;
8bae0a0c
JSC		 648 char **argv;
649 char **env;
650{
50a2a691 651
8bae0a0c 652#ifdef DEBUG
9d52bcb7
DE		 653 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
654 pr_addr(PC));
8bae0a0c
JSC		 655#endif /* DEBUG */
656
0c2c5f61 657 ColdReset(sd);
50a2a691 658
fafce69a 659 if (abfd != NULL)
dad6f1f3
AC		 660 /* override PC value set by ColdReset () */
661 PC = (unsigned64) bfd_get_start_address (abfd);
2e61a3ad 662
f24b7b69 663#if 0 /* def DEBUG */
dad6f1f3 664 if (argv || env)
8bae0a0c 665 {
dad6f1f3
AC		 666 /* We should really place the argv slot values into the argument
667 registers, and onto the stack as required. However, this
668 assumes that we have a stack defined, which is not
669 necessarily true at the moment. */
670 char **cptr;
671 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
672 for (cptr = argv; (cptr && *cptr); cptr++)
673 printf("DBG: arg \"%s\"\n",*cptr);
8bae0a0c
JSC		 674 }
675#endif /* DEBUG */
8bae0a0c 676
9d52bcb7 677 return SIM_RC_OK;
8bae0a0c
JSC		 678}
679
8bae0a0c 680void
53b9417e
DE		 681sim_do_command (sd,cmd)
682 SIM_DESC sd;
8bae0a0c
JSC		 683 char *cmd;
684{
63be8feb
AC		 685 if (sim_args_command (sd, cmd) != SIM_RC_OK)
686 sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
687 cmd);
8bae0a0c
JSC		 688}
689
8bae0a0c
JSC		 690/*---------------------------------------------------------------------------*/
691/*-- Private simulator support interface ------------------------------------*/
692/*---------------------------------------------------------------------------*/
693
525d929e
AC		 694/* Read a null terminated string from memory, return in a buffer */
695static char *
696fetch_str (sd, addr)
697 SIM_DESC sd;
698 address_word addr;
699{
700 char *buf;
701 int nr = 0;
702 char null;
703 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
704 nr++;
705 buf = NZALLOC (char, nr + 1);
706 sim_read (sd, addr, buf, nr);
707 return buf;
708}
709
a9f7253f 710/* Simple monitor interface (currently setup for the IDT and PMON monitors) */
8bae0a0c 711static void
95469ceb 712sim_monitor(sd,cia,reason)
18c64df6 713 SIM_DESC sd;
95469ceb 714 address_word cia;
8bae0a0c
JSC		 715 unsigned int reason;
716{
53b9417e
DE		 717#ifdef DEBUG
718 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
719#endif /* DEBUG */
720
8bae0a0c
JSC		 721 /* The IDT monitor actually allows two instructions per vector
722 slot. However, the simulator currently causes a trap on each
723 individual instruction. We cheat, and lose the bottom bit. */
724 reason >>= 1;
725
726 /* The following callback functions are available, however the
727 monitor we are simulating does not make use of them: get_errno,
728 isatty, lseek, rename, system, time and unlink */
525d929e
AC		 729 switch (reason)
730 {
731
8bae0a0c
JSC		 732 case 6: /* int open(char *path,int flags) */
733 {
525d929e
AC		 734 char *path = fetch_str (sd, A0);
735 V0 = sim_io_open (sd, path, (int)A1);
736 zfree (path);
737 break;
8bae0a0c 738 }
8bae0a0c
JSC		 739
740 case 7: /* int read(int file,char *ptr,int len) */
741 {
525d929e
AC		 742 int fd = A0;
743 int nr = A2;
744 char *buf = zalloc (nr);
745 V0 = sim_io_read (sd, fd, buf, nr);
746 sim_write (sd, A1, buf, nr);
747 zfree (buf);
8bae0a0c
JSC		 748 }
749 break;
750
751 case 8: /* int write(int file,char *ptr,int len) */
752 {
525d929e
AC		 753 int fd = A0;
754 int nr = A2;
755 char *buf = zalloc (nr);
756 sim_read (sd, A1, buf, nr);
757 V0 = sim_io_write (sd, fd, buf, nr);
758 zfree (buf);
759 break;
8bae0a0c 760 }
8bae0a0c
JSC		 761
762 case 10: /* int close(int file) */
525d929e
AC		 763 {
764 V0 = sim_io_close (sd, (int)A0);
765 break;
766 }
8bae0a0c
JSC		 767
768 case 11: /* char inbyte(void) */
769 {
770 char tmp;
525d929e
AC		 771 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
772 {
773 sim_io_error(sd,"Invalid return from character read");
774 V0 = (ut_reg)-1;
775 }
8bae0a0c 776 else
525d929e
AC		 777 V0 = (ut_reg)tmp;
778 break;
8bae0a0c 779 }
8bae0a0c
JSC		 780
781 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
782 {
783 char tmp = (char)(A0 & 0xFF);
525d929e
AC		 784 sim_io_write_stdout (sd, &tmp, sizeof(char));
785 break;
8bae0a0c 786 }
8bae0a0c
JSC		 787
788 case 17: /* void _exit() */
525d929e
AC		 789 {
790 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
791 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, sim_exited,
792 (unsigned int)(A0 & 0xFFFFFFFF));
793 break;
794 }
8bae0a0c 795
280f90e1
AMT		 796 case 28 : /* PMON flush_cache */
797 break;
798
8bae0a0c
JSC		 799 case 55: /* void get_mem_info(unsigned int *ptr) */
800 /* in: A0 = pointer to three word memory location */
801 /* out: [A0 + 0] = size */
802 /* [A0 + 4] = instruction cache size */
803 /* [A0 + 8] = data cache size */
804 {
525d929e
AC		 805 address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
806 H2T (value);
807 sim_write (sd, A0, (char *)&value, sizeof (value));
030843d7 808 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
525d929e 809 break;
8bae0a0c 810 }
525d929e 811
a9f7253f
JSC		 812 case 158 : /* PMON printf */
813 /* in: A0 = pointer to format string */
814 /* A1 = optional argument 1 */
815 /* A2 = optional argument 2 */
816 /* A3 = optional argument 3 */
817 /* out: void */
f24b7b69 818 /* The following is based on the PMON printf source */
a9f7253f 819 {
525d929e
AC		 820 address_word s = A0;
821 char c;
822 signed_word *ap = &A1; /* 1st argument */
f24b7b69
JSC		 823 /* This isn't the quickest way, since we call the host print
824 routine for every character almost. But it does avoid
825 having to allocate and manage a temporary string buffer. */
525d929e
AC		 826 /* TODO: Include check that we only use three arguments (A1,
827 A2 and A3) */
828 while (sim_read (sd, s++, &c, 1) && c != '\0')
829 {
830 if (c == '%')
831 {
832 char tmp[40];
833 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
834 int width = 0, trunc = 0, haddot = 0, longlong = 0;
835 while (sim_read (sd, s++, &c, 1) && c != '\0')
836 {
837 if (strchr ("dobxXulscefg%", s))
838 break;
839 else if (c == '-')
840 fmt = FMT_LJUST;
841 else if (c == '0')
842 fmt = FMT_RJUST0;
843 else if (c == '~')
844 fmt = FMT_CENTER;
845 else if (c == '*')
846 {
847 if (haddot)
848 trunc = (int)*ap++;
849 else
850 width = (int)*ap++;
851 }
852 else if (c >= '1' && c <= '9')
853 {
854 address_word t = s;
855 unsigned int n;
856 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
857 tmp[s - t] = c;
858 tmp[s - t] = '\0';
859 n = (unsigned int)strtol(tmp,NULL,10);
860 if (haddot)
861 trunc = n;
862 else
863 width = n;
864 s--;
865 }
866 else if (c == '.')
867 haddot = 1;
868 }
869 switch (c)
870 {
871 case '%':
872 sim_io_printf (sd, "%%");
873 break;
874 case 's':
875 if ((int)*ap != 0)
876 {
877 address_word p = *ap++;
878 char ch;
879 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
880 sim_io_printf(sd, "%c", ch);
881 }
882 else
883 sim_io_printf(sd,"(null)");
884 break;
885 case 'c':
886 sim_io_printf (sd, "%c", (int)*ap++);
887 break;
888 default:
889 if (c == 'l')
890 {
891 sim_read (sd, s++, &c, 1);
892 if (c == 'l')
893 {
894 longlong = 1;
895 sim_read (sd, s++, &c, 1);
896 }
897 }
898 if (strchr ("dobxXu", c))
899 {
900 word64 lv = (word64) *ap++;
901 if (c == 'b')
902 sim_io_printf(sd,"<binary not supported>");
903 else
904 {
905 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
906 if (longlong)
907 sim_io_printf(sd, tmp, lv);
908 else
909 sim_io_printf(sd, tmp, (int)lv);
910 }
911 }
912 else if (strchr ("eEfgG", c))
913 {
914 double dbl = *(double*)(ap++);
915 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
916 sim_io_printf (sd, tmp, dbl);
917 trunc = 0;
918 }
919 }
920 }
921 else
922 sim_io_printf(sd, "%c", c);
923 }
924 break;
a9f7253f 925 }
a9f7253f 926
8bae0a0c 927 default:
525d929e 928 sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
95469ceb 929 reason, pr_addr(cia));
8bae0a0c
JSC		 930 break;
931 }
932 return;
933}
934
7e6c297e
ILT		 935/* Store a word into memory. */
936
937static void
7ce8b917 938store_word (sd, cia, vaddr, val)
18c64df6 939 SIM_DESC sd;
7ce8b917 940 address_word cia;
7e6c297e
ILT		 941 uword64 vaddr;
942 t_reg val;
943{
dad6f1f3 944 address_word paddr;
7e6c297e
ILT		 945 int uncached;
946
947 if ((vaddr & 3) != 0)
18c64df6 948 SignalExceptionAddressStore ();
7e6c297e
ILT		 949 else
950 {
951 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
952 isTARGET, isREAL))
953 {
954 const uword64 mask = 7;
955 uword64 memval;
956 unsigned int byte;
957
958 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
959 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
960 memval = ((uword64) val) << (8 * byte);
53b9417e 961 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
7e6c297e
ILT		 962 isREAL);
963 }
964 }
965}
966
967/* Load a word from memory. */
968
969static t_reg
7ce8b917 970load_word (sd, cia, vaddr)
18c64df6 971 SIM_DESC sd;
7ce8b917 972 address_word cia;
7e6c297e
ILT		 973 uword64 vaddr;
974{
975 if ((vaddr & 3) != 0)
18c64df6 976 SignalExceptionAddressLoad ();
7e6c297e
ILT		 977 else
978 {
dad6f1f3 979 address_word paddr;
7e6c297e
ILT		 980 int uncached;
981
982 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
983 isTARGET, isREAL))
984 {
985 const uword64 mask = 0x7;
986 const unsigned int reverse = ReverseEndian ? 1 : 0;
987 const unsigned int bigend = BigEndianCPU ? 1 : 0;
988 uword64 memval;
989 unsigned int byte;
990
991 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
53b9417e 992 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
7e6c297e
ILT		 993 isDATA, isREAL);
994 byte = (vaddr & mask) ^ (bigend << 2);
995 return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
996 }
997 }
998
999 return 0;
1000}
1001
1002/* Simulate the mips16 entry and exit pseudo-instructions. These
1003 would normally be handled by the reserved instruction exception
1004 code, but for ease of simulation we just handle them directly. */
1005
1006static void
0c2c5f61
AC		 1007mips16_entry (sd,insn)
1008 SIM_DESC sd;
7e6c297e
ILT		 1009 unsigned int insn;
1010{
1011 int aregs, sregs, rreg;
1012
53b9417e
DE		 1013#ifdef DEBUG
1014 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1015#endif /* DEBUG */
1016
7e6c297e
ILT		 1017 aregs = (insn & 0x700) >> 8;
1018 sregs = (insn & 0x0c0) >> 6;
1019 rreg = (insn & 0x020) >> 5;
1020
da0bce9c
ILT		 1021 /* This should be checked by the caller. */
1022 if (sregs == 3)
7e6c297e
ILT		 1023 abort ();
1024
da0bce9c 1025 if (aregs < 5)
7e6c297e
ILT		 1026 {
1027 int i;
1028 t_reg tsp;
1029
1030 /* This is the entry pseudo-instruction. */
1031
1032 for (i = 0; i < aregs; i++)
0c2c5f61 1033 store_word ((uword64) (SP + 4 * i), GPR[i + 4]);
7e6c297e
ILT		 1034
1035 tsp = SP;
1036 SP -= 32;
1037
1038 if (rreg)
1039 {
1040 tsp -= 4;
1041 store_word ((uword64) tsp, RA);
1042 }
1043
1044 for (i = 0; i < sregs; i++)
1045 {
1046 tsp -= 4;
0c2c5f61 1047 store_word ((uword64) tsp, GPR[16 + i]);
7e6c297e
ILT		 1048 }
1049 }
1050 else
1051 {
1052 int i;
1053 t_reg tsp;
1054
1055 /* This is the exit pseudo-instruction. */
1056
1057 tsp = SP + 32;
1058
1059 if (rreg)
1060 {
1061 tsp -= 4;
1062 RA = load_word ((uword64) tsp);
1063 }
1064
1065 for (i = 0; i < sregs; i++)
1066 {
1067 tsp -= 4;
0c2c5f61 1068 GPR[i + 16] = load_word ((uword64) tsp);
7e6c297e
ILT		 1069 }
1070
1071 SP += 32;
1072
9cb8397f 1073#if defined(HASFPU)
da0bce9c
ILT		 1074 if (aregs == 5)
1075 {
1076 FGR[0] = WORD64LO (GPR[4]);
0c2c5f61 1077 FPR_STATE[0] = fmt_uninterpreted;
da0bce9c
ILT		 1078 }
1079 else if (aregs == 6)
1080 {
1081 FGR[0] = WORD64LO (GPR[5]);
1082 FGR[1] = WORD64LO (GPR[4]);
0c2c5f61
AC		 1083 FPR_STATE[0] = fmt_uninterpreted;
1084 FPR_STATE[1] = fmt_uninterpreted;
da0bce9c 1085 }
9cb8397f 1086#endif /* defined(HASFPU) */
da0bce9c 1087
7e6c297e
ILT		 1088 PC = RA;
1089 }
1090}
1091
8bae0a0c
JSC		 1092/*-- trace support ----------------------------------------------------------*/
1093
1094/* The TRACE support is provided (if required) in the memory accessing
1095 routines. Since we are also providing the architecture specific
1096 features, the architecture simulation code can also deal with
1097 notifying the TRACE world of cache flushes, etc. Similarly we do
1098 not need to provide profiling support in the simulator engine,
1099 since we can sample in the instruction fetch control loop. By
1100 defining the TRACE manifest, we add tracing as a run-time
1101 option. */
1102
1103#if defined(TRACE)
1104/* Tracing by default produces "din" format (as required by
1105 dineroIII). Each line of such a trace file *MUST* have a din label
1106 and address field. The rest of the line is ignored, so comments can
1107 be included if desired. The first field is the label which must be
1108 one of the following values:
1109
1110 0 read data
1111 1 write data
1112 2 instruction fetch
1113 3 escape record (treated as unknown access type)
1114 4 escape record (causes cache flush)
1115
1116 The address field is a 32bit (lower-case) hexadecimal address
1117 value. The address should *NOT* be preceded by "0x".
1118
1119 The size of the memory transfer is not important when dealing with
1120 cache lines (as long as no more than a cache line can be
1121 transferred in a single operation :-), however more information
1122 could be given following the dineroIII requirement to allow more
1123 complete memory and cache simulators to provide better
1124 results. i.e. the University of Pisa has a cache simulator that can
1125 also take bus size and speed as (variable) inputs to calculate
1126 complete system performance (a much more useful ability when trying
1127 to construct an end product, rather than a processor). They
1128 currently have an ARM version of their tool called ChARM. */
1129
e3d12c65 1130
030843d7
AC		 1131void
1132dotrace (SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...)
8bae0a0c 1133{
0c2c5f61 1134 if (STATE & simTRACE) {
8bae0a0c 1135 va_list ap;
53b9417e 1136 fprintf(tracefh,"%d %s ; width %d ; ",
6429b296 1137 type,
53b9417e
DE		 1138 pr_addr(address),
1139 width);
8bae0a0c 1140 va_start(ap,comment);
6429b296 1141 vfprintf(tracefh,comment,ap);
8bae0a0c
JSC		 1142 va_end(ap);
1143 fprintf(tracefh,"\n");
1144 }
1145 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1146 we may be generating 64bit ones, we should put the hi-32bits of the
1147 address into the comment field. */
1148
1149 /* TODO: Provide a buffer for the trace lines. We can then avoid
1150 performing writes until the buffer is filled, or the file is
1151 being closed. */
1152
1153 /* NOTE: We could consider adding a comment field to the "din" file
1154 produced using type 3 markers (unknown access). This would then
1155 allow information about the program that the "din" is for, and
1156 the MIPs world that was being simulated, to be placed into the
1157 trace file. */
1158
1159 return;
1160}
1161#endif /* TRACE */
1162
1163/*---------------------------------------------------------------------------*/
1164/*-- simulator engine -------------------------------------------------------*/
1165/*---------------------------------------------------------------------------*/
1166
1167static void
dad6f1f3 1168ColdReset (sd)
0c2c5f61 1169 SIM_DESC sd;
8bae0a0c
JSC		 1170{
1171 /* RESET: Fixed PC address: */
dad6f1f3 1172 PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
8bae0a0c
JSC		 1173 /* The reset vector address is in the unmapped, uncached memory space. */
1174
1175 SR &= ~(status_SR | status_TS | status_RP);
1176 SR |= (status_ERL | status_BEV);
8bae0a0c 1177
dad6f1f3
AC		 1178 /* Cheat and allow access to the complete register set immediately */
1179 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1180 && WITH_TARGET_WORD_BITSIZE == 64)
1181 SR |= status_FR; /* 64bit registers */
8bae0a0c
JSC		 1182
1183 /* Ensure that any instructions with pending register updates are
1184 cleared: */
1185 {
1186 int loop;
1187 for (loop = 0; (loop < PSLOTS); loop++)
0c2c5f61
AC		 1188 PENDING_SLOT_REG[loop] = (LAST_EMBED_REGNUM + 1);
1189 PENDING_IN = PENDING_OUT = PENDING_TOTAL = 0;
8bae0a0c
JSC		 1190 }
1191
8bae0a0c 1192 /* Initialise the FPU registers to the unknown state */
dad6f1f3
AC		 1193 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1194 {
1195 int rn;
1196 for (rn = 0; (rn < 32); rn++)
1197 FPR_STATE[rn] = fmt_uninterpreted;
1198 }
8bae0a0c
JSC		 1199
1200 return;
1201}
1202
dad6f1f3
AC		 1203/* Description from page A-22 of the "MIPS IV Instruction Set" manual
1204 (revision 3.1) */
8bae0a0c
JSC		 1205/* Translate a virtual address to a physical address and cache
1206 coherence algorithm describing the mechanism used to resolve the
1207 memory reference. Given the virtual address vAddr, and whether the
1208 reference is to Instructions ot Data (IorD), find the corresponding
1209 physical address (pAddr) and the cache coherence algorithm (CCA)
1210 used to resolve the reference. If the virtual address is in one of
1211 the unmapped address spaces the physical address and the CCA are
1212 determined directly by the virtual address. If the virtual address
1213 is in one of the mapped address spaces then the TLB is used to
1214 determine the physical address and access type; if the required
1215 translation is not present in the TLB or the desired access is not
1216 permitted the function fails and an exception is taken.
1217
dad6f1f3
AC		 1218 NOTE: Normally (RAW == 0), when address translation fails, this
1219 function raises an exception and does not return. */
8bae0a0c 1220
18c64df6 1221int
7ce8b917 1222address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw)
18c64df6 1223 SIM_DESC sd;
7ce8b917 1224 address_word cia;
dad6f1f3 1225 address_word vAddr;
8bae0a0c
JSC		 1226 int IorD;
1227 int LorS;
dad6f1f3 1228 address_word *pAddr;
8bae0a0c 1229 int *CCA;
8bae0a0c
JSC		 1230 int raw;
1231{
1232 int res = -1; /* TRUE : Assume good return */
1233
1234#ifdef DEBUG
18c64df6 1235 sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
8bae0a0c
JSC		 1236#endif
1237
1238 /* Check that the address is valid for this memory model */
1239
1240 /* For a simple (flat) memory model, we simply pass virtual
1241 addressess through (mostly) unchanged. */
1242 vAddr &= 0xFFFFFFFF;
a9f7253f 1243
8bae0a0c
JSC		 1244 *pAddr = vAddr; /* default for isTARGET */
1245 *CCA = Uncached; /* not used for isHOST */
1246
8bae0a0c
JSC		 1247 return(res);
1248}
1249
63be8feb
AC		 1250/* Description from page A-23 of the "MIPS IV Instruction Set" manual
1251 (revision 3.1) */
8bae0a0c
JSC		 1252/* Prefetch data from memory. Prefetch is an advisory instruction for
1253 which an implementation specific action is taken. The action taken
1254 may increase performance, but must not change the meaning of the
1255 program, or alter architecturally-visible state. */
50a2a691 1256
ea985d24 1257void
7ce8b917 1258prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint)
ea985d24 1259 SIM_DESC sd;
7ce8b917 1260 address_word cia;
8bae0a0c 1261 int CCA;
dad6f1f3
AC		 1262 address_word pAddr;
1263 address_word vAddr;
8bae0a0c
JSC		 1264 int DATA;
1265 int hint;
1266{
1267#ifdef DEBUG
18c64df6 1268 sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
8bae0a0c
JSC		 1269#endif /* DEBUG */
1270
1271 /* For our simple memory model we do nothing */
1272 return;
1273}
1274
63be8feb
AC		 1275/* Description from page A-22 of the "MIPS IV Instruction Set" manual
1276 (revision 3.1) */
8bae0a0c
JSC		 1277/* Load a value from memory. Use the cache and main memory as
1278 specified in the Cache Coherence Algorithm (CCA) and the sort of
1279 access (IorD) to find the contents of AccessLength memory bytes
1280 starting at physical location pAddr. The data is returned in the
1281 fixed width naturally-aligned memory element (MemElem). The
1282 low-order two (or three) bits of the address and the AccessLength
1283 indicate which of the bytes within MemElem needs to be given to the
1284 processor. If the memory access type of the reference is uncached
1285 then only the referenced bytes are read from memory and valid
1286 within the memory element. If the access type is cached, and the
1287 data is not present in cache, an implementation specific size and
1288 alignment block of memory is read and loaded into the cache to
1289 satisfy a load reference. At a minimum, the block is the entire
1290 memory element. */
18c64df6 1291void
7ce8b917 1292load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
18c64df6 1293 SIM_DESC sd;
7ce8b917 1294 address_word cia;
53b9417e
DE		 1295 uword64* memvalp;
1296 uword64* memval1p;
8bae0a0c
JSC		 1297 int CCA;
1298 int AccessLength;
dad6f1f3
AC		 1299 address_word pAddr;
1300 address_word vAddr;
8bae0a0c 1301 int IorD;
8bae0a0c 1302{
50a2a691
AC		 1303 uword64 value = 0;
1304 uword64 value1 = 0;
8bae0a0c
JSC		 1305
1306#ifdef DEBUG
63be8feb 1307 sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
8bae0a0c
JSC		 1308#endif /* DEBUG */
1309
1310#if defined(WARN_MEM)
1311 if (CCA != uncached)
63be8feb 1312 sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
8bae0a0c
JSC		 1313#endif /* WARN_MEM */
1314
8bae0a0c
JSC		 1315 /* If instruction fetch then we need to check that the two lo-order
1316 bits are zero, otherwise raise a InstructionFetch exception: */
6429b296
JW		 1317 if ((IorD == isINSTRUCTION)
1318 && ((pAddr & 0x3) != 0)
1319 && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
63be8feb
AC		 1320 SignalExceptionInstructionFetch ();
1321
1322 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1323 {
1324 /* In reality this should be a Bus Error */
1325 sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1326 AccessLength,
1327 (LOADDRMASK + 1) << 2,
1328 pr_addr (pAddr));
1329 }
8bae0a0c 1330
8bae0a0c 1331#if defined(TRACE)
63be8feb 1332 dotrace(sd,tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
8bae0a0c 1333#endif /* TRACE */
63be8feb
AC		 1334
1335 /* Read the specified number of bytes from memory. Adjust for
1336 host/target byte ordering/ Align the least significant byte
1337 read. */
8bae0a0c 1338
63be8feb
AC		 1339 switch (AccessLength)
1340 {
1341 case AccessLength_QUADWORD :
1342 {
1343 unsigned_16 val = sim_core_read_aligned_16 (STATE_CPU (sd, 0), NULL_CIA,
1344 sim_core_read_map, pAddr);
1345 value1 = VH8_16 (val);
1346 value = VL8_16 (val);
1347 break;
8bae0a0c 1348 }
63be8feb
AC		 1349 case AccessLength_DOUBLEWORD :
1350 value = sim_core_read_aligned_8 (STATE_CPU (sd, 0), NULL_CIA,
1351 sim_core_read_map, pAddr);
1352 break;
1353 case AccessLength_SEPTIBYTE :
1354 value = sim_core_read_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA,
1355 sim_core_read_map, pAddr);
1356 case AccessLength_SEXTIBYTE :
1357 value = sim_core_read_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA,
1358 sim_core_read_map, pAddr);
1359 case AccessLength_QUINTIBYTE :
1360 value = sim_core_read_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA,
1361 sim_core_read_map, pAddr);
1362 case AccessLength_WORD :
1363 value = sim_core_read_aligned_4 (STATE_CPU (sd, 0), NULL_CIA,
1364 sim_core_read_map, pAddr);
1365 break;
1366 case AccessLength_TRIPLEBYTE :
1367 value = sim_core_read_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA,
1368 sim_core_read_map, pAddr);
1369 case AccessLength_HALFWORD :
1370 value = sim_core_read_aligned_2 (STATE_CPU (sd, 0), NULL_CIA,
1371 sim_core_read_map, pAddr);
1372 break;
1373 case AccessLength_BYTE :
1374 value = sim_core_read_aligned_1 (STATE_CPU (sd, 0), NULL_CIA,
1375 sim_core_read_map, pAddr);
1376 break;
1377 default:
1378 abort ();
1379 }
1380
8bae0a0c 1381#ifdef DEBUG
63be8feb
AC		 1382 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1383 (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
8bae0a0c 1384#endif /* DEBUG */
63be8feb
AC		 1385
1386 /* See also store_memory. */
1387 if (AccessLength <= AccessLength_DOUBLEWORD)
1388 {
1389 if (BigEndianMem)
1390 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1391 shifted to the most significant byte position. */
1392 value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1393 else
1394 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1395 is already in the correct postition. */
1396 value <<= ((pAddr & LOADDRMASK) * 8);
1397 }
1398
8bae0a0c 1399#ifdef DEBUG
63be8feb
AC		 1400 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1401 pr_uword64(value1),pr_uword64(value));
e871dd18 1402#endif /* DEBUG */
63be8feb 1403
525d929e
AC		 1404 *memvalp = value;
1405 if (memval1p) *memval1p = value1;
8bae0a0c
JSC		 1406}
1407
53b9417e 1408
50a2a691
AC		 1409/* Description from page A-23 of the "MIPS IV Instruction Set" manual
1410 (revision 3.1) */
8bae0a0c
JSC		 1411/* Store a value to memory. The specified data is stored into the
1412 physical location pAddr using the memory hierarchy (data caches and
1413 main memory) as specified by the Cache Coherence Algorithm
1414 (CCA). The MemElem contains the data for an aligned, fixed-width
1415 memory element (word for 32-bit processors, doubleword for 64-bit
1416 processors), though only the bytes that will actually be stored to
1417 memory need to be valid. The low-order two (or three) bits of pAddr
1418 and the AccessLength field indicates which of the bytes within the
1419 MemElem data should actually be stored; only these bytes in memory
1420 will be changed. */
53b9417e 1421
18c64df6 1422void
7ce8b917 1423store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
18c64df6 1424 SIM_DESC sd;
7ce8b917 1425 address_word cia;
8bae0a0c
JSC		 1426 int CCA;
1427 int AccessLength;
e871dd18 1428 uword64 MemElem;
53b9417e 1429 uword64 MemElem1; /* High order 64 bits */
dad6f1f3
AC		 1430 address_word pAddr;
1431 address_word vAddr;
8bae0a0c
JSC		 1432{
1433#ifdef DEBUG
63be8feb 1434 sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
8bae0a0c 1435#endif /* DEBUG */
63be8feb 1436
8bae0a0c
JSC		 1437#if defined(WARN_MEM)
1438 if (CCA != uncached)
63be8feb 1439 sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
8bae0a0c 1440#endif /* WARN_MEM */
63be8feb
AC		 1441
1442 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1443 sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
1444
8bae0a0c 1445#if defined(TRACE)
63be8feb 1446 dotrace(sd,tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
8bae0a0c 1447#endif /* TRACE */
63be8feb 1448
8bae0a0c 1449#ifdef DEBUG
63be8feb 1450 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
8bae0a0c 1451#endif /* DEBUG */
63be8feb
AC		 1452
1453 /* See also load_memory */
1454 if (AccessLength <= AccessLength_DOUBLEWORD)
1455 {
1456 if (BigEndianMem)
1457 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1458 shifted to the most significant byte position. */
1459 MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1460 else
1461 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1462 is already in the correct postition. */
1463 MemElem >>= ((pAddr & LOADDRMASK) * 8);
1464 }
1465
8bae0a0c 1466#ifdef DEBUG
63be8feb 1467 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
8bae0a0c 1468#endif /* DEBUG */
63be8feb
AC		 1469
1470 switch (AccessLength)
1471 {
1472 case AccessLength_QUADWORD :
1473 {
1474 unsigned_16 val = U16_8 (MemElem1, MemElem);
1475 sim_core_write_aligned_16 (STATE_CPU (sd, 0), NULL_CIA,
1476 sim_core_write_map, pAddr, val);
1477 break;
8bae0a0c 1478 }
63be8feb
AC		 1479 case AccessLength_DOUBLEWORD :
1480 sim_core_write_aligned_8 (STATE_CPU (sd, 0), NULL_CIA,
1481 sim_core_write_map, pAddr, MemElem);
1482 break;
1483 case AccessLength_SEPTIBYTE :
1484 sim_core_write_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA,
1485 sim_core_write_map, pAddr, MemElem);
1486 break;
1487 case AccessLength_SEXTIBYTE :
1488 sim_core_write_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA,
1489 sim_core_write_map, pAddr, MemElem);
1490 break;
1491 case AccessLength_QUINTIBYTE :
1492 sim_core_write_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA,
1493 sim_core_write_map, pAddr, MemElem);
1494 break;
1495 case AccessLength_WORD :
1496 sim_core_write_aligned_4 (STATE_CPU (sd, 0), NULL_CIA,
1497 sim_core_write_map, pAddr, MemElem);
1498 break;
1499 case AccessLength_TRIPLEBYTE :
1500 sim_core_write_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA,
1501 sim_core_write_map, pAddr, MemElem);
1502 break;
1503 case AccessLength_HALFWORD :
1504 sim_core_write_aligned_2 (STATE_CPU (sd, 0), NULL_CIA,
1505 sim_core_write_map, pAddr, MemElem);
1506 break;
1507 case AccessLength_BYTE :
1508 sim_core_write_aligned_1 (STATE_CPU (sd, 0), NULL_CIA,
1509 sim_core_write_map, pAddr, MemElem);
1510 break;
1511 default:
1512 abort ();
1513 }
1514
8bae0a0c
JSC		 1515 return;
1516}
1517
53b9417e 1518
dad6f1f3 1519unsigned32
7ce8b917
AC		 1520ifetch32 (SIM_DESC sd,
1521 address_word cia,
1522 address_word vaddr)
dad6f1f3
AC		 1523{
1524 /* Copy the action of the LW instruction */
1525 address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
1526 address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
1527 unsigned64 value;
1528 address_word paddr;
1529 unsigned32 instruction;
1530 unsigned byte;
1531 int cca;
1532 AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
1533 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
1534 LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
1535 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
1536 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
1537 return instruction;
1538}
1539
1540
8bae0a0c
JSC		 1541/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1542/* Order loads and stores to synchronise shared memory. Perform the
1543 action necessary to make the effects of groups of synchronizable
1544 loads and stores indicated by stype occur in the same order for all
1545 processors. */
ea985d24 1546void
7ce8b917 1547sync_operation(sd,cia,stype)
ea985d24 1548 SIM_DESC sd;
7ce8b917 1549 address_word cia;
8bae0a0c
JSC		 1550 int stype;
1551{
1552#ifdef DEBUG
18c64df6 1553 sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
8bae0a0c
JSC		 1554#endif /* DEBUG */
1555 return;
1556}
1557
1558/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1559/* Signal an exception condition. This will result in an exception
1560 that aborts the instruction. The instruction operation pseudocode
50a2a691 1561 will never see a return from this function call. */
2e61a3ad 1562
18c64df6 1563void
7ce8b917
AC		 1564signal_exception (SIM_DESC sd,
1565 address_word cia,
1566 int exception,...)
8bae0a0c 1567{
56e7c849 1568 int vector;
6eedf3f4
MA		 1569
1570#ifdef DEBUG
95469ceb 1571 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
6eedf3f4
MA		 1572#endif /* DEBUG */
1573
8bae0a0c
JSC		 1574 /* Ensure that any active atomic read/modify/write operation will fail: */
1575 LLBIT = 0;
1576
1577 switch (exception) {
1578 /* TODO: For testing purposes I have been ignoring TRAPs. In
1579 reality we should either simulate them, or allow the user to
6eedf3f4
MA		 1580 ignore them at run-time.
1581 Same for SYSCALL */
8bae0a0c 1582 case Trap :
95469ceb 1583 sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia));
8bae0a0c
JSC		 1584 break;
1585
6eedf3f4
MA		 1586 case SystemCall :
1587 {
1588 va_list ap;
1589 unsigned int instruction;
1590 unsigned int code;
1591
1592 va_start(ap,exception);
1593 instruction = va_arg(ap,unsigned int);
1594 va_end(ap);
1595
1596 code = (instruction >> 6) & 0xFFFFF;
1597
18c64df6 1598 sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
95469ceb 1599 code, pr_addr(cia));
6eedf3f4
MA		 1600 }
1601 break;
1602
1603 case DebugBreakPoint :
1604 if (! (Debug & Debug_DM))
1605 {
1606 if (INDELAYSLOT())
1607 {
1608 CANCELDELAYSLOT();
1609
1610 Debug |= Debug_DBD; /* signaled from within in delay slot */
95469ceb 1611 DEPC = cia - 4; /* reference the branch instruction */
6eedf3f4
MA		 1612 }
1613 else
1614 {
1615 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
95469ceb 1616 DEPC = cia;
6eedf3f4
MA		 1617 }
1618
1619 Debug |= Debug_DM; /* in debugging mode */
1620 Debug |= Debug_DBp; /* raising a DBp exception */
1621 PC = 0xBFC00200;
1622 sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA);
1623 }
1624 break;
1625
8bae0a0c
JSC		 1626 case ReservedInstruction :
1627 {
1628 va_list ap;
1629 unsigned int instruction;
1630 va_start(ap,exception);
1631 instruction = va_arg(ap,unsigned int);
1632 va_end(ap);
1633 /* Provide simple monitor support using ReservedInstruction
1634 exceptions. The following code simulates the fixed vector
1635 entry points into the IDT monitor by causing a simulator
1636 trap, performing the monitor operation, and returning to
1637 the address held in the $ra register (standard PCS return
1638 address). This means we only need to pre-load the vector
1639 space with suitable instruction values. For systems were
1640 actual trap instructions are used, we would not need to
1641 perform this magic. */
7ce8b917
AC		 1642 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1643 {
95469ceb 1644 sim_monitor(sd, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
7ce8b917
AC		 1645 /* NOTE: This assumes that a branch-and-link style
1646 instruction was used to enter the vector (which is the
1647 case with the current IDT monitor). */
1648 sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, RA);
1649 }
7e6c297e
ILT		 1650 /* Look for the mips16 entry and exit instructions, and
1651 simulate a handler for them. */
95469ceb 1652 else if ((cia & 1) != 0
7e6c297e 1653 && (instruction & 0xf81f) == 0xe809
7ce8b917
AC		 1654 && (instruction & 0x0c0) != 0x0c0)
1655 {
1656 mips16_entry (instruction);
1657 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1658 }
1659 /* else fall through to normal exception processing */
95469ceb 1660 sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia));
8bae0a0c
JSC		 1661 }
1662
05d1322f 1663 case BreakPoint:
e3d12c65 1664#ifdef DEBUG
95469ceb 1665 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
8bae0a0c 1666#endif /* DEBUG */
05d1322f
JL		 1667 /* Keep a copy of the current A0 in-case this is the program exit
1668 breakpoint: */
1669 {
1670 va_list ap;
1671 unsigned int instruction;
1672 va_start(ap,exception);
1673 instruction = va_arg(ap,unsigned int);
1674 va_end(ap);
1675 /* Check for our special terminating BREAK: */
1676 if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
7ce8b917 1677 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia,
05d1322f
JL		 1678 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1679 }
1680 }
0c2c5f61 1681 if (STATE & simDELAYSLOT)
95469ceb 1682 PC = cia - 4; /* reference the branch instruction */
05d1322f 1683 else
95469ceb
AC		 1684 PC = cia;
1685 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia,
232156de 1686 sim_stopped, SIM_SIGTRAP);
05d1322f
JL		 1687
1688 default:
8bae0a0c
JSC		 1689 /* Store exception code into current exception id variable (used
1690 by exit code): */
1691
1692 /* TODO: If not simulating exceptions then stop the simulator
1693 execution. At the moment we always stop the simulation. */
e3d12c65 1694
56e7c849
AC		 1695 /* See figure 5-17 for an outline of the code below */
1696 if (! (SR & status_EXL))
1697 {
1698 CAUSE = (exception << 2);
0c2c5f61 1699 if (STATE & simDELAYSLOT)
56e7c849 1700 {
0c2c5f61 1701 STATE &= ~simDELAYSLOT;
56e7c849 1702 CAUSE |= cause_BD;
95469ceb 1703 EPC = (cia - 4); /* reference the branch instruction */
56e7c849
AC		 1704 }
1705 else
95469ceb 1706 EPC = cia;
56e7c849
AC		 1707 /* FIXME: TLB et.al. */
1708 vector = 0x180;
1709 }
1710 else
1711 {
05d1322f 1712 CAUSE = (exception << 2);
56e7c849
AC		 1713 vector = 0x180;
1714 }
1715 SR |= status_EXL;
e3d12c65
DE		 1716 /* Store exception code into current exception id variable (used
1717 by exit code): */
56e7c849
AC		 1718 if (SR & status_BEV)
1719 PC = (signed)0xBFC00200 + 0x180;
1720 else
1721 PC = (signed)0x80000000 + 0x180;
1722
50a2a691
AC		 1723 switch ((CAUSE >> 2) & 0x1F)
1724 {
1725 case Interrupt:
56e7c849
AC		 1726 /* Interrupts arrive during event processing, no need to
1727 restart */
1728 return;
50a2a691
AC		 1729
1730 case TLBModification:
1731 case TLBLoad:
1732 case TLBStore:
1733 case AddressLoad:
1734 case AddressStore:
1735 case InstructionFetch:
1736 case DataReference:
56e7c849
AC		 1737 /* The following is so that the simulator will continue from the
1738 exception address on breakpoint operations. */
1739 PC = EPC;
50a2a691 1740 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
232156de 1741 sim_stopped, SIM_SIGBUS);
50a2a691
AC		 1742
1743 case ReservedInstruction:
1744 case CoProcessorUnusable:
56e7c849 1745 PC = EPC;
50a2a691 1746 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
232156de 1747 sim_stopped, SIM_SIGILL);
50a2a691
AC		 1748
1749 case IntegerOverflow:
1750 case FPE:
1751 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
232156de 1752 sim_stopped, SIM_SIGFPE);
50a2a691
AC		 1753
1754 case Trap:
1755 case Watch:
1756 case SystemCall:
56e7c849 1757 PC = EPC;
50a2a691 1758 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
232156de 1759 sim_stopped, SIM_SIGTRAP);
50a2a691 1760
05d1322f
JL		 1761 case BreakPoint:
1762 PC = EPC;
1763 sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA,
1764 "FATAL: Should not encounter a breakpoint\n");
1765
50a2a691 1766 default : /* Unknown internal exception */
56e7c849 1767 PC = EPC;
50a2a691 1768 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
232156de 1769 sim_stopped, SIM_SIGABRT);
50a2a691
AC		 1770
1771 }
8bae0a0c
JSC		 1772
1773 case SimulatorFault:
1774 {
1775 va_list ap;
1776 char *msg;
1777 va_start(ap,exception);
1778 msg = va_arg(ap,char *);
50a2a691 1779 va_end(ap);
2e61a3ad
AC		 1780 sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA,
1781 "FATAL: Simulator error \"%s\"\n",msg);
8bae0a0c 1782 }
8bae0a0c
JSC		 1783 }
1784
1785 return;
1786}
1787
1788#if defined(WARN_RESULT)
1789/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1790/* This function indicates that the result of the operation is
1791 undefined. However, this should not affect the instruction
1792 stream. All that is meant to happen is that the destination
1793 register is set to an undefined result. To keep the simulator
1794 simple, we just don't bother updating the destination register, so
1795 the overall result will be undefined. If desired we can stop the
1796 simulator by raising a pseudo-exception. */
95469ceb 1797#define UndefinedResult() undefined_result (sd,cia)
8bae0a0c 1798static void
95469ceb
AC		 1799undefined_result(sd,cia)
1800 SIM_DESC sd;
1801 address_word cia;
8bae0a0c 1802{
95469ceb 1803 sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
8bae0a0c
JSC		 1804#if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1805 state |= simSTOP;
1806#endif
1807 return;
1808}
1809#endif /* WARN_RESULT */
1810
18c64df6 1811void
7ce8b917 1812cache_op(sd,cia,op,pAddr,vAddr,instruction)
18c64df6 1813 SIM_DESC sd;
7ce8b917 1814 address_word cia;
8bae0a0c 1815 int op;
dad6f1f3
AC		 1816 address_word pAddr;
1817 address_word vAddr;
8bae0a0c
JSC		 1818 unsigned int instruction;
1819{
f24b7b69
JSC		 1820#if 1 /* stop warning message being displayed (we should really just remove the code) */
1821 static int icache_warning = 1;
1822 static int dcache_warning = 1;
1823#else
a9f7253f
JSC		 1824 static int icache_warning = 0;
1825 static int dcache_warning = 0;
f24b7b69 1826#endif
a9f7253f 1827
8bae0a0c
JSC		 1828 /* If CP0 is not useable (User or Supervisor mode) and the CP0
1829 enable bit in the Status Register is clear - a coprocessor
1830 unusable exception is taken. */
a9f7253f 1831#if 0
95469ceb 1832 sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia));
a9f7253f 1833#endif
8bae0a0c
JSC		 1834
1835 switch (op & 0x3) {
1836 case 0: /* instruction cache */
1837 switch (op >> 2) {
1838 case 0: /* Index Invalidate */
1839 case 1: /* Index Load Tag */
1840 case 2: /* Index Store Tag */
1841 case 4: /* Hit Invalidate */
1842 case 5: /* Fill */
1843 case 6: /* Hit Writeback */
a9f7253f
JSC		 1844 if (!icache_warning)
1845 {
18c64df6 1846 sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2));
a9f7253f
JSC		 1847 icache_warning = 1;
1848 }
8bae0a0c
JSC		 1849 break;
1850
1851 default:
1852 SignalException(ReservedInstruction,instruction);
1853 break;
1854 }
1855 break;
1856
1857 case 1: /* data cache */
1858 switch (op >> 2) {
1859 case 0: /* Index Writeback Invalidate */
1860 case 1: /* Index Load Tag */
1861 case 2: /* Index Store Tag */
1862 case 3: /* Create Dirty */
1863 case 4: /* Hit Invalidate */
1864 case 5: /* Hit Writeback Invalidate */
1865 case 6: /* Hit Writeback */
a9f7253f
JSC		 1866 if (!dcache_warning)
1867 {
18c64df6 1868 sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2));
a9f7253f
JSC		 1869 dcache_warning = 1;
1870 }
8bae0a0c
JSC		 1871 break;
1872
1873 default:
1874 SignalException(ReservedInstruction,instruction);
1875 break;
1876 }
1877 break;
1878
1879 default: /* unrecognised cache ID */
1880 SignalException(ReservedInstruction,instruction);
1881 break;
1882 }
1883
1884 return;
1885}
1886
1887/*-- FPU support routines ---------------------------------------------------*/
1888
1889#if defined(HASFPU) /* Only needed when building FPU aware simulators */
1890
8bae0a0c
JSC		 1891/* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1892 formats conform to ANSI/IEEE Std 754-1985. */
1893/* SINGLE precision floating:
1894 * seeeeeeeefffffffffffffffffffffff
1895 * s = 1bit = sign
1896 * e = 8bits = exponent
1897 * f = 23bits = fraction
1898 */
1899/* SINGLE precision fixed:
1900 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1901 * s = 1bit = sign
1902 * i = 31bits = integer
1903 */
1904/* DOUBLE precision floating:
1905 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1906 * s = 1bit = sign
1907 * e = 11bits = exponent
1908 * f = 52bits = fraction
1909 */
1910/* DOUBLE precision fixed:
1911 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1912 * s = 1bit = sign
1913 * i = 63bits = integer
1914 */
1915
1916/* Extract sign-bit: */
1917#define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
e871dd18 1918#define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
8bae0a0c
JSC		 1919/* Extract biased exponent: */
1920#define FP_S_be(v) (((v) >> 23) & 0xFF)
1921#define FP_D_be(v) (((v) >> 52) & 0x7FF)
1922/* Extract unbiased Exponent: */
1923#define FP_S_e(v) (FP_S_be(v) - 0x7F)
1924#define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1925/* Extract complete fraction field: */
1926#define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
e871dd18 1927#define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
8bae0a0c
JSC		 1928/* Extract numbered fraction bit: */
1929#define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1930#define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1931
1932/* Explicit QNaN values used when value required: */
1933#define FPQNaN_SINGLE (0x7FBFFFFF)
1934#define FPQNaN_WORD (0x7FFFFFFF)
e871dd18
JSC		 1935#define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1936#define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
8bae0a0c
JSC		 1937
1938/* Explicit Infinity values used when required: */
1939#define FPINF_SINGLE (0x7F800000)
e871dd18 1940#define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
8bae0a0c
JSC		 1941
1942#if 1 /* def DEBUG */
1943#define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1944#define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
1945#endif /* DEBUG */
1946
18c64df6 1947uword64
7ce8b917 1948value_fpr(sd,cia,fpr,fmt)
18c64df6 1949 SIM_DESC sd;
7ce8b917 1950 address_word cia;
18c64df6
AC		 1951 int fpr;
1952 FP_formats fmt;
8bae0a0c 1953{
50a2a691 1954 uword64 value = 0;
8bae0a0c
JSC		 1955 int err = 0;
1956
1957 /* Treat unused register values, as fixed-point 64bit values: */
1958 if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
1959#if 1
1960 /* If request to read data as "uninterpreted", then use the current
1961 encoding: */
0c2c5f61 1962 fmt = FPR_STATE[fpr];
8bae0a0c
JSC		 1963#else
1964 fmt = fmt_long;
1965#endif
1966
1967 /* For values not yet accessed, set to the desired format: */
0c2c5f61
AC		 1968 if (FPR_STATE[fpr] == fmt_uninterpreted) {
1969 FPR_STATE[fpr] = fmt;
8bae0a0c
JSC		 1970#ifdef DEBUG
1971 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
1972#endif /* DEBUG */
1973 }
0c2c5f61 1974 if (fmt != FPR_STATE[fpr]) {
95469ceb 1975 sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia));
0c2c5f61 1976 FPR_STATE[fpr] = fmt_unknown;
8bae0a0c
JSC		 1977 }
1978
0c2c5f61 1979 if (FPR_STATE[fpr] == fmt_unknown) {
8bae0a0c
JSC		 1980 /* Set QNaN value: */
1981 switch (fmt) {
1982 case fmt_single:
1983 value = FPQNaN_SINGLE;
1984 break;
1985
1986 case fmt_double:
1987 value = FPQNaN_DOUBLE;
1988 break;
1989
1990 case fmt_word:
1991 value = FPQNaN_WORD;
1992 break;
1993
1994 case fmt_long:
1995 value = FPQNaN_LONG;
1996 break;
1997
1998 default:
1999 err = -1;
2000 break;
2001 }
2002 } else if (SizeFGR() == 64) {
2003 switch (fmt) {
2004 case fmt_single:
2005 case fmt_word:
2006 value = (FGR[fpr] & 0xFFFFFFFF);
2007 break;
2008
2009 case fmt_uninterpreted:
2010 case fmt_double:
2011 case fmt_long:
2012 value = FGR[fpr];
2013 break;
2014
2015 default :
2016 err = -1;
2017 break;
2018 }
da0bce9c 2019 } else {
8bae0a0c
JSC		 2020 switch (fmt) {
2021 case fmt_single:
2022 case fmt_word:
2023 value = (FGR[fpr] & 0xFFFFFFFF);
2024 break;
2025
2026 case fmt_uninterpreted:
2027 case fmt_double:
2028 case fmt_long:
da0bce9c
ILT		 2029 if ((fpr & 1) == 0) { /* even registers only */
2030 value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
2031 } else {
18c64df6 2032 SignalException(ReservedInstruction,0);
da0bce9c 2033 }
8bae0a0c
JSC		 2034 break;
2035
2036 default :
2037 err = -1;
2038 break;
2039 }
2040 }
2041
2042 if (err)
18c64df6 2043 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
8bae0a0c
JSC		 2044
2045#ifdef DEBUG
95469ceb 2046 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
8bae0a0c
JSC		 2047#endif /* DEBUG */
2048
2049 return(value);
2050}
2051
18c64df6 2052void
7ce8b917 2053store_fpr(sd,cia,fpr,fmt,value)
18c64df6 2054 SIM_DESC sd;
7ce8b917 2055 address_word cia;
8bae0a0c
JSC		 2056 int fpr;
2057 FP_formats fmt;
e871dd18 2058 uword64 value;
8bae0a0c
JSC		 2059{
2060 int err = 0;
2061
2062#ifdef DEBUG
95469ceb 2063 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
8bae0a0c
JSC		 2064#endif /* DEBUG */
2065
2066 if (SizeFGR() == 64) {
2067 switch (fmt) {
a09a30d2
AC		 2068 case fmt_uninterpreted_32:
2069 fmt = fmt_uninterpreted;
8bae0a0c
JSC		 2070 case fmt_single :
2071 case fmt_word :
e871dd18 2072 FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
0c2c5f61 2073 FPR_STATE[fpr] = fmt;
8bae0a0c
JSC		 2074 break;
2075
a09a30d2
AC		 2076 case fmt_uninterpreted_64:
2077 fmt = fmt_uninterpreted;
8bae0a0c
JSC		 2078 case fmt_uninterpreted:
2079 case fmt_double :
2080 case fmt_long :
2081 FGR[fpr] = value;
0c2c5f61 2082 FPR_STATE[fpr] = fmt;
8bae0a0c
JSC		 2083 break;
2084
2085 default :
0c2c5f61 2086 FPR_STATE[fpr] = fmt_unknown;
8bae0a0c
JSC		 2087 err = -1;
2088 break;
2089 }
da0bce9c 2090 } else {
8bae0a0c 2091 switch (fmt) {
a09a30d2
AC		 2092 case fmt_uninterpreted_32:
2093 fmt = fmt_uninterpreted;
8bae0a0c
JSC		 2094 case fmt_single :
2095 case fmt_word :
8bae0a0c 2096 FGR[fpr] = (value & 0xFFFFFFFF);
0c2c5f61 2097 FPR_STATE[fpr] = fmt;
8bae0a0c
JSC		 2098 break;
2099
a09a30d2
AC		 2100 case fmt_uninterpreted_64:
2101 fmt = fmt_uninterpreted;
8bae0a0c
JSC		 2102 case fmt_uninterpreted:
2103 case fmt_double :
2104 case fmt_long :
da0bce9c
ILT		 2105 if ((fpr & 1) == 0) { /* even register number only */
2106 FGR[fpr+1] = (value >> 32);
2107 FGR[fpr] = (value & 0xFFFFFFFF);
0c2c5f61
AC		 2108 FPR_STATE[fpr + 1] = fmt;
2109 FPR_STATE[fpr] = fmt;
da0bce9c 2110 } else {
0c2c5f61
AC		 2111 FPR_STATE[fpr] = fmt_unknown;
2112 FPR_STATE[fpr + 1] = fmt_unknown;
18c64df6 2113 SignalException(ReservedInstruction,0);
da0bce9c 2114 }
8bae0a0c
JSC		 2115 break;
2116
2117 default :
0c2c5f61 2118 FPR_STATE[fpr] = fmt_unknown;
8bae0a0c
JSC		 2119 err = -1;
2120 break;
2121 }
e871dd18
JSC		 2122 }
2123#if defined(WARN_RESULT)
2124 else
2125 UndefinedResult();
2126#endif /* WARN_RESULT */
8bae0a0c
JSC		 2127
2128 if (err)
18c64df6 2129 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
8bae0a0c
JSC		 2130
2131#ifdef DEBUG
53b9417e 2132 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
8bae0a0c
JSC		 2133#endif /* DEBUG */
2134
2135 return;
2136}
2137
18c64df6 2138int
8bae0a0c 2139NaN(op,fmt)
e871dd18 2140 uword64 op;
8bae0a0c
JSC		 2141 FP_formats fmt;
2142{
2143 int boolean = 0;
8bae0a0c
JSC		 2144 switch (fmt) {
2145 case fmt_single:
8bae0a0c 2146 case fmt_word:
76ef4165
FL		 2147 {
2148 sim_fpu wop;
2149 sim_fpu_32to (&wop, op);
2150 boolean = sim_fpu_is_nan (&wop);
2151 break;
2152 }
2153 case fmt_double:
8bae0a0c 2154 case fmt_long:
76ef4165
FL		 2155 {
2156 sim_fpu wop;
2157 sim_fpu_64to (&wop, op);
2158 boolean = sim_fpu_is_nan (&wop);
2159 break;
2160 }
50a2a691
AC		 2161 default:
2162 fprintf (stderr, "Bad switch\n");
2163 abort ();
8bae0a0c
JSC		 2164 }
2165
2166#ifdef DEBUG
53b9417e 2167printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
8bae0a0c
JSC		 2168#endif /* DEBUG */
2169
2170 return(boolean);
2171}
2172
18c64df6 2173int
8bae0a0c 2174Infinity(op,fmt)
e871dd18 2175 uword64 op;
8bae0a0c
JSC		 2176 FP_formats fmt;
2177{
2178 int boolean = 0;
2179
2180#ifdef DEBUG
95469ceb 2181 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
8bae0a0c
JSC		 2182#endif /* DEBUG */
2183
8bae0a0c
JSC		 2184 switch (fmt) {
2185 case fmt_single:
76ef4165
FL		 2186 {
2187 sim_fpu wop;
2188 sim_fpu_32to (&wop, op);
2189 boolean = sim_fpu_is_infinity (&wop);
2190 break;
2191 }
8bae0a0c 2192 case fmt_double:
76ef4165
FL		 2193 {
2194 sim_fpu wop;
2195 sim_fpu_64to (&wop, op);
2196 boolean = sim_fpu_is_infinity (&wop);
2197 break;
2198 }
8bae0a0c
JSC		 2199 default:
2200 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
2201 break;
2202 }
2203
2204#ifdef DEBUG
53b9417e 2205 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
8bae0a0c
JSC		 2206#endif /* DEBUG */
2207
2208 return(boolean);
2209}
2210
18c64df6 2211int
8bae0a0c 2212Less(op1,op2,fmt)
e871dd18
JSC		 2213 uword64 op1;
2214 uword64 op2;
8bae0a0c
JSC		 2215 FP_formats fmt;
2216{
2217 int boolean = 0;
2218
e871dd18
JSC		 2219 /* Argument checking already performed by the FPCOMPARE code */
2220
8bae0a0c 2221#ifdef DEBUG
53b9417e 2222 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2223#endif /* DEBUG */
2224
8bae0a0c
JSC		 2225 /* The format type should already have been checked: */
2226 switch (fmt) {
2227 case fmt_single:
2228 {
76ef4165
FL		 2229 sim_fpu wop1;
2230 sim_fpu wop2;
2231 sim_fpu_32to (&wop1, op1);
2232 sim_fpu_32to (&wop2, op2);
2233 boolean = sim_fpu_is_lt (&wop1, &wop2);
2234 break;
8bae0a0c 2235 }
8bae0a0c 2236 case fmt_double:
76ef4165
FL		 2237 {
2238 sim_fpu wop1;
2239 sim_fpu wop2;
2240 sim_fpu_64to (&wop1, op1);
2241 sim_fpu_64to (&wop2, op2);
2242 boolean = sim_fpu_is_lt (&wop1, &wop2);
2243 break;
2244 }
50a2a691
AC		 2245 default:
2246 fprintf (stderr, "Bad switch\n");
2247 abort ();
8bae0a0c
JSC		 2248 }
2249
2250#ifdef DEBUG
2251 printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2252#endif /* DEBUG */
2253
2254 return(boolean);
2255}
2256
18c64df6 2257int
8bae0a0c 2258Equal(op1,op2,fmt)
e871dd18
JSC		 2259 uword64 op1;
2260 uword64 op2;
8bae0a0c
JSC		 2261 FP_formats fmt;
2262{
2263 int boolean = 0;
2264
e871dd18
JSC		 2265 /* Argument checking already performed by the FPCOMPARE code */
2266
8bae0a0c 2267#ifdef DEBUG
53b9417e 2268 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2269#endif /* DEBUG */
2270
8bae0a0c
JSC		 2271 /* The format type should already have been checked: */
2272 switch (fmt) {
2273 case fmt_single:
76ef4165
FL		 2274 {
2275 sim_fpu wop1;
2276 sim_fpu wop2;
2277 sim_fpu_32to (&wop1, op1);
2278 sim_fpu_32to (&wop2, op2);
2279 boolean = sim_fpu_is_eq (&wop1, &wop2);
2280 break;
2281 }
8bae0a0c 2282 case fmt_double:
76ef4165
FL		 2283 {
2284 sim_fpu wop1;
2285 sim_fpu wop2;
2286 sim_fpu_64to (&wop1, op1);
2287 sim_fpu_64to (&wop2, op2);
2288 boolean = sim_fpu_is_eq (&wop1, &wop2);
2289 break;
2290 }
50a2a691
AC		 2291 default:
2292 fprintf (stderr, "Bad switch\n");
2293 abort ();
8bae0a0c
JSC		 2294 }
2295
2296#ifdef DEBUG
2297 printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2298#endif /* DEBUG */
2299
2300 return(boolean);
2301}
2302
18c64df6 2303uword64
a9f7253f
JSC		 2304AbsoluteValue(op,fmt)
2305 uword64 op;
2306 FP_formats fmt;
2307{
50a2a691 2308 uword64 result = 0;
a9f7253f
JSC		 2309
2310#ifdef DEBUG
53b9417e 2311 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
a9f7253f
JSC		 2312#endif /* DEBUG */
2313
2314 /* The format type should already have been checked: */
2315 switch (fmt) {
2316 case fmt_single:
2317 {
76ef4165
FL		 2318 sim_fpu wop;
2319 unsigned32 ans;
2320 sim_fpu_32to (&wop, op);
2321 sim_fpu_abs (&wop, &wop);
2322 sim_fpu_to32 (&ans, &wop);
2323 result = ans;
2324 break;
a9f7253f 2325 }
a9f7253f
JSC		 2326 case fmt_double:
2327 {
76ef4165
FL		 2328 sim_fpu wop;
2329 unsigned64 ans;
2330 sim_fpu_64to (&wop, op);
2331 sim_fpu_abs (&wop, &wop);
2332 sim_fpu_to64 (&ans, &wop);
2333 result = ans;
2334 break;
a9f7253f 2335 }
50a2a691
AC		 2336 default:
2337 fprintf (stderr, "Bad switch\n");
2338 abort ();
a9f7253f
JSC		 2339 }
2340
2341 return(result);
2342}
2343
18c64df6 2344uword64
8bae0a0c 2345Negate(op,fmt)
e871dd18 2346 uword64 op;
8bae0a0c
JSC		 2347 FP_formats fmt;
2348{
50a2a691 2349 uword64 result = 0;
8bae0a0c
JSC		 2350
2351#ifdef DEBUG
53b9417e 2352 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
8bae0a0c
JSC		 2353#endif /* DEBUG */
2354
2355 /* The format type should already have been checked: */
2356 switch (fmt) {
2357 case fmt_single:
2358 {
76ef4165
FL		 2359 sim_fpu wop;
2360 unsigned32 ans;
2361 sim_fpu_32to (&wop, op);
2362 sim_fpu_neg (&wop, &wop);
2363 sim_fpu_to32 (&ans, &wop);
2364 result = ans;
2365 break;
8bae0a0c 2366 }
8bae0a0c
JSC		 2367 case fmt_double:
2368 {
76ef4165
FL		 2369 sim_fpu wop;
2370 unsigned64 ans;
2371 sim_fpu_64to (&wop, op);
2372 sim_fpu_neg (&wop, &wop);
2373 sim_fpu_to64 (&ans, &wop);
2374 result = ans;
2375 break;
8bae0a0c 2376 }
50a2a691
AC		 2377 default:
2378 fprintf (stderr, "Bad switch\n");
2379 abort ();
8bae0a0c
JSC		 2380 }
2381
2382 return(result);
2383}
2384
18c64df6 2385uword64
8bae0a0c 2386Add(op1,op2,fmt)
e871dd18
JSC		 2387 uword64 op1;
2388 uword64 op2;
8bae0a0c
JSC		 2389 FP_formats fmt;
2390{
50a2a691 2391 uword64 result = 0;
8bae0a0c
JSC		 2392
2393#ifdef DEBUG
53b9417e 2394 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2395#endif /* DEBUG */
2396
e871dd18
JSC		 2397 /* The registers must specify FPRs valid for operands of type
2398 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2399
2400 /* The format type should already have been checked: */
2401 switch (fmt) {
2402 case fmt_single:
2403 {
76ef4165
FL		 2404 sim_fpu wop1;
2405 sim_fpu wop2;
2406 sim_fpu ans;
2407 unsigned32 res;
2408 sim_fpu_32to (&wop1, op1);
2409 sim_fpu_32to (&wop2, op2);
2410 sim_fpu_add (&ans, &wop1, &wop2);
2411 sim_fpu_to32 (&res, &ans);
2412 result = res;
2413 break;
8bae0a0c 2414 }
8bae0a0c
JSC		 2415 case fmt_double:
2416 {
76ef4165
FL		 2417 sim_fpu wop1;
2418 sim_fpu wop2;
2419 sim_fpu ans;
2420 unsigned64 res;
2421 sim_fpu_64to (&wop1, op1);
2422 sim_fpu_64to (&wop2, op2);
2423 sim_fpu_add (&ans, &wop1, &wop2);
2424 sim_fpu_to64 (&res, &ans);
2425 result = res;
2426 break;
8bae0a0c 2427 }
50a2a691
AC		 2428 default:
2429 fprintf (stderr, "Bad switch\n");
2430 abort ();
8bae0a0c
JSC		 2431 }
2432
2433#ifdef DEBUG
53b9417e 2434 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2435#endif /* DEBUG */
2436
2437 return(result);
2438}
2439
18c64df6 2440uword64
8bae0a0c 2441Sub(op1,op2,fmt)
e871dd18
JSC		 2442 uword64 op1;
2443 uword64 op2;
8bae0a0c
JSC		 2444 FP_formats fmt;
2445{
50a2a691 2446 uword64 result = 0;
8bae0a0c
JSC		 2447
2448#ifdef DEBUG
53b9417e 2449 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2450#endif /* DEBUG */
2451
e871dd18
JSC		 2452 /* The registers must specify FPRs valid for operands of type
2453 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2454
2455 /* The format type should already have been checked: */
2456 switch (fmt) {
2457 case fmt_single:
2458 {
76ef4165
FL		 2459 sim_fpu wop1;
2460 sim_fpu wop2;
2461 sim_fpu ans;
2462 unsigned32 res;
2463 sim_fpu_32to (&wop1, op1);
2464 sim_fpu_32to (&wop2, op2);
2465 sim_fpu_sub (&ans, &wop1, &wop2);
2466 sim_fpu_to32 (&res, &ans);
2467 result = res;
8bae0a0c
JSC		 2468 }
2469 break;
2470 case fmt_double:
2471 {
76ef4165
FL		 2472 sim_fpu wop1;
2473 sim_fpu wop2;
2474 sim_fpu ans;
2475 unsigned64 res;
2476 sim_fpu_64to (&wop1, op1);
2477 sim_fpu_64to (&wop2, op2);
2478 sim_fpu_sub (&ans, &wop1, &wop2);
2479 sim_fpu_to64 (&res, &ans);
2480 result = res;
8bae0a0c
JSC		 2481 }
2482 break;
50a2a691
AC		 2483 default:
2484 fprintf (stderr, "Bad switch\n");
2485 abort ();
8bae0a0c
JSC		 2486 }
2487
2488#ifdef DEBUG
53b9417e 2489 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2490#endif /* DEBUG */
2491
2492 return(result);
2493}
2494
18c64df6 2495uword64
8bae0a0c 2496Multiply(op1,op2,fmt)
e871dd18
JSC		 2497 uword64 op1;
2498 uword64 op2;
8bae0a0c
JSC		 2499 FP_formats fmt;
2500{
50a2a691 2501 uword64 result = 0;
8bae0a0c
JSC		 2502
2503#ifdef DEBUG
53b9417e 2504 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2505#endif /* DEBUG */
2506
e871dd18
JSC		 2507 /* The registers must specify FPRs valid for operands of type
2508 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2509
2510 /* The format type should already have been checked: */
2511 switch (fmt) {
2512 case fmt_single:
2513 {
76ef4165
FL		 2514 sim_fpu wop1;
2515 sim_fpu wop2;
2516 sim_fpu ans;
2517 unsigned32 res;
2518 sim_fpu_32to (&wop1, op1);
2519 sim_fpu_32to (&wop2, op2);
2520 sim_fpu_mul (&ans, &wop1, &wop2);
2521 sim_fpu_to32 (&res, &ans);
2522 result = res;
2523 break;
8bae0a0c 2524 }
8bae0a0c
JSC		 2525 case fmt_double:
2526 {
76ef4165
FL		 2527 sim_fpu wop1;
2528 sim_fpu wop2;
2529 sim_fpu ans;
2530 unsigned64 res;
2531 sim_fpu_64to (&wop1, op1);
2532 sim_fpu_64to (&wop2, op2);
2533 sim_fpu_mul (&ans, &wop1, &wop2);
2534 sim_fpu_to64 (&res, &ans);
2535 result = res;
2536 break;
8bae0a0c 2537 }
50a2a691
AC		 2538 default:
2539 fprintf (stderr, "Bad switch\n");
2540 abort ();
8bae0a0c
JSC		 2541 }
2542
2543#ifdef DEBUG
53b9417e 2544 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2545#endif /* DEBUG */
2546
2547 return(result);
2548}
2549
18c64df6 2550uword64
8bae0a0c 2551Divide(op1,op2,fmt)
e871dd18
JSC		 2552 uword64 op1;
2553 uword64 op2;
8bae0a0c
JSC		 2554 FP_formats fmt;
2555{
50a2a691 2556 uword64 result = 0;
8bae0a0c
JSC		 2557
2558#ifdef DEBUG
53b9417e 2559 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
8bae0a0c
JSC		 2560#endif /* DEBUG */
2561
e871dd18
JSC		 2562 /* The registers must specify FPRs valid for operands of type
2563 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2564
2565 /* The format type should already have been checked: */
2566 switch (fmt) {
2567 case fmt_single:
2568 {
76ef4165
FL		 2569 sim_fpu wop1;
2570 sim_fpu wop2;
2571 sim_fpu ans;
2572 unsigned32 res;
2573 sim_fpu_32to (&wop1, op1);
2574 sim_fpu_32to (&wop2, op2);
2575 sim_fpu_div (&ans, &wop1, &wop2);
2576 sim_fpu_to32 (&res, &ans);
2577 result = res;
2578 break;
8bae0a0c 2579 }
8bae0a0c
JSC		 2580 case fmt_double:
2581 {
76ef4165
FL		 2582 sim_fpu wop1;
2583 sim_fpu wop2;
2584 sim_fpu ans;
2585 unsigned64 res;
2586 sim_fpu_64to (&wop1, op1);
2587 sim_fpu_64to (&wop2, op2);
2588 sim_fpu_div (&ans, &wop1, &wop2);
2589 sim_fpu_to64 (&res, &ans);
2590 result = res;
2591 break;
8bae0a0c 2592 }
50a2a691
AC		 2593 default:
2594 fprintf (stderr, "Bad switch\n");
2595 abort ();
8bae0a0c
JSC		 2596 }
2597
2598#ifdef DEBUG
53b9417e 2599 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2600#endif /* DEBUG */
2601
2602 return(result);
2603}
2604
18c64df6 2605uword64 UNUSED
8bae0a0c 2606Recip(op,fmt)
e871dd18 2607 uword64 op;
8bae0a0c
JSC		 2608 FP_formats fmt;
2609{
50a2a691 2610 uword64 result = 0;
8bae0a0c
JSC		 2611
2612#ifdef DEBUG
53b9417e 2613 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
8bae0a0c
JSC		 2614#endif /* DEBUG */
2615
e871dd18
JSC		 2616 /* The registers must specify FPRs valid for operands of type
2617 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2618
2619 /* The format type should already have been checked: */
2620 switch (fmt) {
2621 case fmt_single:
2622 {
76ef4165
FL		 2623 sim_fpu wop;
2624 sim_fpu ans;
2625 unsigned32 res;
2626 sim_fpu_32to (&wop, op);
2627 sim_fpu_inv (&ans, &wop);
2628 sim_fpu_to32 (&res, &ans);
2629 result = res;
2630 break;
8bae0a0c 2631 }
8bae0a0c
JSC		 2632 case fmt_double:
2633 {
76ef4165
FL		 2634 sim_fpu wop;
2635 sim_fpu ans;
2636 unsigned64 res;
2637 sim_fpu_64to (&wop, op);
2638 sim_fpu_inv (&ans, &wop);
2639 sim_fpu_to64 (&res, &ans);
2640 result = res;
2641 break;
8bae0a0c 2642 }
50a2a691
AC		 2643 default:
2644 fprintf (stderr, "Bad switch\n");
2645 abort ();
8bae0a0c
JSC		 2646 }
2647
2648#ifdef DEBUG
53b9417e 2649 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2650#endif /* DEBUG */
2651
2652 return(result);
2653}
2654
18c64df6 2655uword64
8bae0a0c 2656SquareRoot(op,fmt)
e871dd18 2657 uword64 op;
8bae0a0c
JSC		 2658 FP_formats fmt;
2659{
50a2a691 2660 uword64 result = 0;
8bae0a0c
JSC		 2661
2662#ifdef DEBUG
53b9417e 2663 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
8bae0a0c
JSC		 2664#endif /* DEBUG */
2665
e871dd18
JSC		 2666 /* The registers must specify FPRs valid for operands of type
2667 "fmt". If they are not valid, the result is undefined. */
8bae0a0c
JSC		 2668
2669 /* The format type should already have been checked: */
2670 switch (fmt) {
2671 case fmt_single:
2672 {
76ef4165
FL		 2673 sim_fpu wop;
2674 sim_fpu ans;
2675 unsigned32 res;
2676 sim_fpu_32to (&wop, op);
2677 sim_fpu_sqrt (&ans, &wop);
2678 sim_fpu_to32 (&res, &ans);
2679 result = res;
2680 break;
8bae0a0c 2681 }
8bae0a0c
JSC		 2682 case fmt_double:
2683 {
76ef4165
FL		 2684 sim_fpu wop;
2685 sim_fpu ans;
2686 unsigned64 res;
2687 sim_fpu_64to (&wop, op);
2688 sim_fpu_sqrt (&ans, &wop);
2689 sim_fpu_to64 (&res, &ans);
2690 result = res;
2691 break;
8bae0a0c 2692 }
50a2a691
AC		 2693 default:
2694 fprintf (stderr, "Bad switch\n");
2695 abort ();
8bae0a0c
JSC		 2696 }
2697
2698#ifdef DEBUG
53b9417e 2699 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
8bae0a0c
JSC		 2700#endif /* DEBUG */
2701
2702 return(result);
2703}
2704
18c64df6 2705uword64
7ce8b917 2706convert(sd,cia,rm,op,from,to)
18c64df6 2707 SIM_DESC sd;
7ce8b917 2708 address_word cia;
8bae0a0c 2709 int rm;
e871dd18 2710 uword64 op;
8bae0a0c
JSC		 2711 FP_formats from;
2712 FP_formats to;
2713{
76ef4165
FL		 2714 sim_fpu wop;
2715 sim_fpu_round round;
2716 unsigned32 result32;
2717 unsigned64 result64;
8bae0a0c
JSC		 2718
2719#ifdef DEBUG
53b9417e 2720 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
8bae0a0c
JSC		 2721#endif /* DEBUG */
2722
76ef4165 2723 switch (rm)
8bae0a0c 2724 {
76ef4165
FL		 2725 case FP_RM_NEAREST:
2726 /* Round result to nearest representable value. When two
2727 representable values are equally near, round to the value
2728 that has a least significant bit of zero (i.e. is even). */
2729 round = sim_fpu_round_near;
2730 break;
2731 case FP_RM_TOZERO:
2732 /* Round result to the value closest to, and not greater in
2733 magnitude than, the result. */
2734 round = sim_fpu_round_zero;
2735 break;
2736 case FP_RM_TOPINF:
2737 /* Round result to the value closest to, and not less than,
2738 the result. */
2739 round = sim_fpu_round_up;
2740 break;
2741
2742 case FP_RM_TOMINF:
2743 /* Round result to the value closest to, and not greater than,
2744 the result. */
2745 round = sim_fpu_round_down;
2746 break;
2747 default:
2748 round = 0;
2749 fprintf (stderr, "Bad switch\n");
2750 abort ();
8bae0a0c 2751 }
76ef4165
FL		 2752
2753 /* Convert the input to sim_fpu internal format */
2754 switch (from)
8bae0a0c 2755 {
76ef4165
FL		 2756 case fmt_double:
2757 sim_fpu_64to (&wop, op);
2758 break;
2759 case fmt_single:
2760 sim_fpu_32to (&wop, op);
2761 break;
2762 case fmt_word:
2763 sim_fpu_i32to (&wop, op, round);
2764 break;
2765 case fmt_long:
2766 sim_fpu_i64to (&wop, op, round);
2767 break;
2768 default:
2769 fprintf (stderr, "Bad switch\n");
2770 abort ();
8bae0a0c 2771 }
8bae0a0c 2772
76ef4165
FL		 2773 /* Convert sim_fpu format into the output */
2774 /* The value WOP is converted to the destination format, rounding
2775 using mode RM. When the destination is a fixed-point format, then
2776 a source value of Infinity, NaN or one which would round to an
2777 integer outside the fixed point range then an IEEE Invalid
2778 Operation condition is raised. */
2779 switch (to)
2780 {
2781 case fmt_single:
2782 sim_fpu_round_32 (&wop, round, 0);
2783 sim_fpu_to32 (&result32, &wop);
2784 result64 = result32;
2785 break;
2786 case fmt_double:
2787 sim_fpu_round_64 (&wop, round, 0);
2788 sim_fpu_to64 (&result64, &wop);
2789 break;
2790 case fmt_word:
2791 sim_fpu_to32i (&result32, &wop, round);
2792 result64 = result32;
2793 break;
2794 case fmt_long:
2795 sim_fpu_to64i (&result64, &wop, round);
2796 break;
2797 default:
2798 result64 = 0;
2799 fprintf (stderr, "Bad switch\n");
2800 abort ();
8bae0a0c 2801 }
76ef4165 2802
8bae0a0c 2803#ifdef DEBUG
76ef4165 2804 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to));
8bae0a0c
JSC		 2805#endif /* DEBUG */
2806
76ef4165 2807 return(result64);
8bae0a0c
JSC		 2808}
2809#endif /* HASFPU */
2810
76ef4165 2811
8bae0a0c
JSC		 2812/*-- co-processor support routines ------------------------------------------*/
2813
2f2e6c5d 2814static int UNUSED
8bae0a0c
JSC		 2815CoProcPresent(coproc_number)
2816 unsigned int coproc_number;
2817{
2818 /* Return TRUE if simulator provides a model for the given co-processor number */
2819 return(0);
2820}
2821
18c64df6 2822void
7ce8b917 2823cop_lw(sd,cia,coproc_num,coproc_reg,memword)
18c64df6 2824 SIM_DESC sd;
7ce8b917 2825 address_word cia;
8bae0a0c
JSC		 2826 int coproc_num, coproc_reg;
2827 unsigned int memword;
2828{
2829 switch (coproc_num) {
2830#if defined(HASFPU)
2831 case 1:
2832#ifdef DEBUG
53b9417e 2833 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
8bae0a0c 2834#endif
da0bce9c 2835 StoreFPR(coproc_reg,fmt_word,(uword64)memword);
0c2c5f61 2836 FPR_STATE[coproc_reg] = fmt_uninterpreted;
8bae0a0c
JSC		 2837 break;
2838#endif /* HASFPU */
2839
2840 default:
f24b7b69 2841#if 0 /* this should be controlled by a configuration option */
95469ceb 2842 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
f24b7b69 2843#endif
8bae0a0c
JSC		 2844 break;
2845 }
2846
2847 return;
2848}
2849
18c64df6 2850void
7ce8b917 2851cop_ld(sd,cia,coproc_num,coproc_reg,memword)
18c64df6 2852 SIM_DESC sd;
7ce8b917 2853 address_word cia;
8bae0a0c 2854 int coproc_num, coproc_reg;
e871dd18 2855 uword64 memword;
8bae0a0c
JSC		 2856{
2857 switch (coproc_num) {
2858#if defined(HASFPU)
2859 case 1:
2860 StoreFPR(coproc_reg,fmt_uninterpreted,memword);
2861 break;
2862#endif /* HASFPU */
2863
2864 default:
f24b7b69 2865#if 0 /* this message should be controlled by a configuration option */
95469ceb 2866 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
f24b7b69 2867#endif
8bae0a0c
JSC		 2868 break;
2869 }
2870
2871 return;
2872}
2873
18c64df6 2874unsigned int
7ce8b917 2875cop_sw(sd,cia,coproc_num,coproc_reg)
18c64df6 2876 SIM_DESC sd;
7ce8b917 2877 address_word cia;
8bae0a0c
JSC		 2878 int coproc_num, coproc_reg;
2879{
2880 unsigned int value = 0;
da0bce9c 2881
8bae0a0c
JSC		 2882 switch (coproc_num) {
2883#if defined(HASFPU)
2884 case 1:
2885#if 1
9cb8397f
GRK		 2886 {
2887 FP_formats hold;
0c2c5f61
AC		 2888 hold = FPR_STATE[coproc_reg];
2889 FPR_STATE[coproc_reg] = fmt_word;
9cb8397f 2890 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
0c2c5f61 2891 FPR_STATE[coproc_reg] = hold;
9cb8397f 2892 }
8bae0a0c
JSC		 2893#else
2894#if 1
0c2c5f61 2895 value = (unsigned int)ValueFPR(coproc_reg,FPR_STATE[coproc_reg]);
8bae0a0c
JSC		 2896#else
2897#ifdef DEBUG
0c2c5f61 2898 printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE[coproc_reg]));
8bae0a0c
JSC		 2899#endif /* DEBUG */
2900 value = (unsigned int)ValueFPR(coproc_reg,fmt_single);
2901#endif
2902#endif
2903 break;
2904#endif /* HASFPU */
2905
2906 default:
f24b7b69 2907#if 0 /* should be controlled by configuration option */
95469ceb 2908 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
f24b7b69 2909#endif
8bae0a0c
JSC		 2910 break;
2911 }
2912
2913 return(value);
2914}
2915
18c64df6 2916uword64
7ce8b917 2917cop_sd(sd,cia,coproc_num,coproc_reg)
18c64df6 2918 SIM_DESC sd;
7ce8b917 2919 address_word cia;
8bae0a0c
JSC		 2920 int coproc_num, coproc_reg;
2921{
e871dd18 2922 uword64 value = 0;
8bae0a0c
JSC		 2923 switch (coproc_num) {
2924#if defined(HASFPU)
2925 case 1:
2926#if 1
2927 value = ValueFPR(coproc_reg,fmt_uninterpreted);
2928#else
2929#if 1
0c2c5f61 2930 value = ValueFPR(coproc_reg,FPR_STATE[coproc_reg]);
8bae0a0c
JSC		 2931#else
2932#ifdef DEBUG
0c2c5f61 2933 printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE[coproc_reg]));
8bae0a0c
JSC		 2934#endif /* DEBUG */
2935 value = ValueFPR(coproc_reg,fmt_double);
2936#endif
2937#endif
2938 break;
2939#endif /* HASFPU */
2940
2941 default:
f24b7b69 2942#if 0 /* should be controlled by configuration option */
95469ceb 2943 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
f24b7b69 2944#endif
8bae0a0c
JSC		 2945 break;
2946 }
2947
2948 return(value);
2949}
2950
ea985d24 2951void
7ce8b917 2952decode_coproc(sd,cia,instruction)
18c64df6 2953 SIM_DESC sd;
7ce8b917 2954 address_word cia;
8bae0a0c
JSC		 2955 unsigned int instruction;
2956{
2957 int coprocnum = ((instruction >> 26) & 3);
2958
56e7c849
AC		 2959 switch (coprocnum)
2960 {
8bae0a0c
JSC		 2961 case 0: /* standard CPU control and cache registers */
2962 {
8bae0a0c
JSC		 2963 int code = ((instruction >> 21) & 0x1F);
2964 /* R4000 Users Manual (second edition) lists the following CP0
2965 instructions:
56e7c849
AC		 2966 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2967 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2968 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2969 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2970 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2971 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2972 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2973 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2974 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2975 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2976 */
2977 if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
2978 {
2979 int rt = ((instruction >> 16) & 0x1F);
2980 int rd = ((instruction >> 11) & 0x1F);
2981
2982 switch (rd) /* NOTEs: Standard CP0 registers */
2983 {
2984 /* 0 = Index R4000 VR4100 VR4300 */
2985 /* 1 = Random R4000 VR4100 VR4300 */
2986 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2987 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2988 /* 4 = Context R4000 VR4100 VR4300 */
2989 /* 5 = PageMask R4000 VR4100 VR4300 */
2990 /* 6 = Wired R4000 VR4100 VR4300 */
2991 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2992 /* 9 = Count R4000 VR4100 VR4300 */
2993 /* 10 = EntryHi R4000 VR4100 VR4300 */
2994 /* 11 = Compare R4000 VR4100 VR4300 */
2995 /* 12 = SR R4000 VR4100 VR4300 */
2996 case 12:
2997 if (code == 0x00)
2998 GPR[rt] = SR;
2999 else
3000 SR = GPR[rt];
3001 break;
3002 /* 13 = Cause R4000 VR4100 VR4300 */
05d1322f
JL		 3003 case 13:
3004 if (code == 0x00)
3005 GPR[rt] = CAUSE;
3006 else
3007 CAUSE = GPR[rt];
3008 break;
56e7c849
AC		 3009 /* 14 = EPC R4000 VR4100 VR4300 */
3010 /* 15 = PRId R4000 VR4100 VR4300 */
6eedf3f4
MA		 3011#ifdef SUBTARGET_R3900
3012 /* 16 = Debug */
3013 case 16:
3014 if (code == 0x00)
3015 GPR[rt] = Debug;
3016 else
3017 Debug = GPR[rt];
3018 break;
3019#else
56e7c849 3020 /* 16 = Config R4000 VR4100 VR4300 */
a09a30d2
AC		 3021 case 16:
3022 if (code == 0x00)
3023 GPR[rt] = C0_CONFIG;
3024 else
3025 C0_CONFIG = GPR[rt];
3026 break;
6eedf3f4
MA		 3027#endif
3028#ifdef SUBTARGET_R3900
3029 /* 17 = Debug */
3030 case 17:
3031 if (code == 0x00)
3032 GPR[rt] = DEPC;
3033 else
3034 DEPC = GPR[rt];
3035 break;
3036#else
56e7c849 3037 /* 17 = LLAddr R4000 VR4100 VR4300 */
6eedf3f4 3038#endif
56e7c849
AC		 3039 /* 18 = WatchLo R4000 VR4100 VR4300 */
3040 /* 19 = WatchHi R4000 VR4100 VR4300 */
3041 /* 20 = XContext R4000 VR4100 VR4300 */
3042 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3043 /* 27 = CacheErr R4000 VR4100 */
3044 /* 28 = TagLo R4000 VR4100 VR4300 */
3045 /* 29 = TagHi R4000 VR4100 VR4300 */
3046 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3047 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
3048 /* CPR[0,rd] = GPR[rt]; */
3049 default:
3050 if (code == 0x00)
18c64df6 3051 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
56e7c849 3052 else
18c64df6 3053 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
56e7c849
AC		 3054 }
3055 }
3056 else if (code == 0x10 && (instruction & 0x3f) == 0x18)
3057 {
3058 /* ERET */
3059 if (SR & status_ERL)
3060 {
3061 /* Oops, not yet available */
18c64df6 3062 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
56e7c849
AC		 3063 PC = EPC;
3064 SR &= ~status_ERL;
3065 }
3066 else
3067 {
3068 PC = EPC;
3069 SR &= ~status_EXL;
3070 }
3071 }
6eedf3f4
MA		 3072 else if (code == 0x10 && (instruction & 0x3f) == 0x10)
3073 {
3074 /* RFE */
3075 }
3076 else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
3077 {
3078 /* DERET */
3079 Debug &= ~Debug_DM;
3080 DELAYSLOT();
3081 DSPC = DEPC;
3082 }
56e7c849 3083 else
95469ceb 3084 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
e871dd18 3085 /* TODO: When executing an ERET or RFE instruction we should
8bae0a0c
JSC		 3086 clear LLBIT, to ensure that any out-standing atomic
3087 read/modify/write sequence fails. */
3088 }
56e7c849
AC		 3089 break;
3090
8bae0a0c 3091 case 2: /* undefined co-processor */
95469ceb 3092 sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
8bae0a0c 3093 break;
56e7c849 3094
8bae0a0c
JSC		 3095 case 1: /* should not occur (FPU co-processor) */
3096 case 3: /* should not occur (FPU co-processor) */
3097 SignalException(ReservedInstruction,instruction);
3098 break;
56e7c849
AC		 3099 }
3100
8bae0a0c
JSC		 3101 return;
3102}
3103
3104/*-- instruction simulation -------------------------------------------------*/
3105
16bd5d6e
AC		 3106/* When the IGEN simulator is being built, the function below is be
3107 replaced by a generated version. However, WITH_IGEN == 2 indicates
3108 that the fubction below should be compiled but under a different
3109 name (to allow backward compatibility) */
3110
3111#if (WITH_IGEN != 1)
3112#if (WITH_IGEN > 1)
dad6f1f3
AC		 3113void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
3114void
3115old_engine_run (sd, next_cpu_nr, siggnal)
3116#else
2e61a3ad
AC		 3117void
3118sim_engine_run (sd, next_cpu_nr, siggnal)
dad6f1f3 3119#endif
2e61a3ad
AC		 3120 SIM_DESC sd;
3121 int next_cpu_nr; /* ignore */
3122 int siggnal; /* ignore */
8bae0a0c 3123{
50a2a691 3124#if !defined(FASTSIM)
8bae0a0c 3125 unsigned int pipeline_count = 1;
50a2a691 3126#endif
8bae0a0c
JSC		 3127
3128#ifdef DEBUG
50a2a691 3129 if (STATE_MEMORY (sd) == NULL) {
8bae0a0c
JSC		 3130 printf("DBG: simulate() entered with no memory\n");
3131 exit(1);
3132 }
3133#endif /* DEBUG */
3134
3135#if 0 /* Disabled to check that everything works OK */
3136 /* The VR4300 seems to sign-extend the PC on its first
3137 access. However, this may just be because it is currently
3138 configured in 32bit mode. However... */
3139 PC = SIGNEXTEND(PC,32);
3140#endif
3141
3142 /* main controlling loop */
2e61a3ad 3143 while (1) {
7ce8b917
AC		 3144 /* vaddr is slowly being replaced with cia - current instruction
3145 address */
3146 address_word cia = (uword64)PC;
3147 address_word vaddr = cia;
dad6f1f3 3148 address_word paddr;
8bae0a0c 3149 int cca;
53b9417e 3150 unsigned int instruction; /* uword64? what's this used for? FIXME! */
8bae0a0c
JSC		 3151
3152#ifdef DEBUG
3153 {
3154 printf("DBG: state = 0x%08X :",state);
8bae0a0c
JSC		 3155 if (state & simHALTEX) printf(" simHALTEX");
3156 if (state & simHALTIN) printf(" simHALTIN");
53b9417e 3157 printf("\n");
8bae0a0c
JSC		 3158 }
3159#endif /* DEBUG */
3160
0c2c5f61 3161 DSSTATE = (STATE & simDELAYSLOT);
8bae0a0c
JSC		 3162#ifdef DEBUG
3163 if (dsstate)
18c64df6 3164 sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
8bae0a0c
JSC		 3165#endif /* DEBUG */
3166
7ce8b917
AC		 3167 /* Fetch the next instruction from the simulator memory: */
3168 if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
6429b296
JW		 3169 if ((vaddr & 1) == 0) {
3170 /* Copy the action of the LW instruction */
3171 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
3172 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
3173 uword64 value;
3174 unsigned int byte;
3175 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
53b9417e 3176 LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
6429b296
JW		 3177 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
3178 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
3179 } else {
3180 /* Copy the action of the LH instruction */
3181 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
3182 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
3183 uword64 value;
3184 unsigned int byte;
3185 paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
3186 | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
53b9417e 3187 LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
6429b296
JW		 3188 paddr & ~ (uword64) 1,
3189 vaddr, isINSTRUCTION, isREAL);
3190 byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
3191 instruction = ((value >> (8 * byte)) & 0xFFFF);
3192 }
8bae0a0c 3193 } else {
53b9417e 3194 fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
8bae0a0c
JSC		 3195 exit(1);
3196 }
3197
3198#ifdef DEBUG
18c64df6 3199 sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
8bae0a0c
JSC		 3200#endif /* DEBUG */
3201
8bae0a0c
JSC		 3202 /* This is required by exception processing, to ensure that we can
3203 cope with exceptions in the delay slots of branches that may
3204 already have changed the PC. */
6429b296
JW		 3205 if ((vaddr & 1) == 0)
3206 PC += 4; /* increment ready for the next fetch */
3207 else
3208 PC += 2;
8bae0a0c
JSC		 3209 /* NOTE: If we perform a delay slot change to the PC, this
3210 increment is not requuired. However, it would make the
3211 simulator more complicated to try and avoid this small hit. */
3212
3213 /* Currently this code provides a simple model. For more
3214 complicated models we could perform exception status checks at
3215 this point, and set the simSTOP state as required. This could
3216 also include processing any hardware interrupts raised by any
3217 I/O model attached to the simulator context.
3218
3219 Support for "asynchronous" I/O events within the simulated world
3220 could be providing by managing a counter, and calling a I/O
3221 specific handler when a particular threshold is reached. On most
3222 architectures a decrement and check for zero operation is
3223 usually quicker than an increment and compare. However, the
3224 process of managing a known value decrement to zero, is higher
3225 than the cost of using an explicit value UINT_MAX into the
3226 future. Which system is used will depend on how complicated the
3227 I/O model is, and how much it is likely to affect the simulator
3228 bandwidth.
3229
3230 If events need to be scheduled further in the future than
3231 UINT_MAX event ticks, then the I/O model should just provide its
3232 own counter, triggered from the event system. */
3233
3234 /* MIPS pipeline ticks. To allow for future support where the
3235 pipeline hit of individual instructions is known, this control
3236 loop manages a "pipeline_count" variable. It is initialised to
3237 1 (one), and will only be changed by the simulator engine when
3238 executing an instruction. If the engine does not have access to
3239 pipeline cycle count information then all instructions will be
3240 treated as using a single cycle. NOTE: A standard system is not
3241 provided by the default simulator because different MIPS
3242 architectures have different cycle counts for the same
50a2a691
AC		 3243 instructions.
3244
3245 [NOTE: pipeline_count has been replaced the event queue] */
8bae0a0c 3246
a09a30d2
AC		 3247 /* shuffle the floating point status pipeline state */
3248 ENGINE_ISSUE_PREFIX_HOOK();
8bae0a0c
JSC		 3249
3250/* NOTE: For multi-context simulation environments the "instruction"
3251 variable should be local to this routine. */
3252
3253/* Shorthand accesses for engine. Note: If we wanted to use global
3254 variables (and a single-threaded simulator engine), then we can
3255 create the actual variables with these names. */
3256
0c2c5f61 3257 if (!(STATE & simSKIPNEXT)) {
8bae0a0c 3258 /* Include the simulator engine */
284e759d 3259#include "oengine.c"
f24b7b69 3260#if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
8bae0a0c
JSC		 3261#error "Mismatch between run-time simulator code and simulation engine"
3262#endif
18c64df6
AC		 3263#if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3264#error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3265#endif
76ef4165 3266#if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
18c64df6
AC		 3267#error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3268#endif
8bae0a0c
JSC		 3269
3270#if defined(WARN_LOHI)
3271 /* Decrement the HI/LO validity ticks */
3272 if (HIACCESS > 0)
3273 HIACCESS--;
3274 if (LOACCESS > 0)
3275 LOACCESS--;
0425cfb3 3276 /* start-sanitize-r5900 */
53b9417e
DE		 3277 if (HI1ACCESS > 0)
3278 HI1ACCESS--;
3279 if (LO1ACCESS > 0)
3280 LO1ACCESS--;
0425cfb3 3281 /* end-sanitize-r5900 */
8bae0a0c
JSC		 3282#endif /* WARN_LOHI */
3283
8bae0a0c
JSC		 3284 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3285 should check for it being changed. It is better doing it here,
3286 than within the simulator, since it will help keep the simulator
3287 small. */
3288 if (ZERO != 0) {
05d1322f 3289#if defined(WARN_ZERO)
95469ceb 3290 sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
05d1322f 3291#endif /* WARN_ZERO */
8bae0a0c
JSC		 3292 ZERO = 0; /* reset back to zero before next instruction */
3293 }
8bae0a0c 3294 } else /* simSKIPNEXT check */
0c2c5f61 3295 STATE &= ~simSKIPNEXT;
8bae0a0c
JSC		 3296
3297 /* If the delay slot was active before the instruction is
3298 executed, then update the PC to its new value: */
0c2c5f61 3299 if (DSSTATE) {
8bae0a0c 3300#ifdef DEBUG
53b9417e 3301 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
8bae0a0c
JSC		 3302#endif /* DEBUG */
3303 PC = DSPC;
6eedf3f4 3304 CANCELDELAYSLOT();
8bae0a0c
JSC		 3305 }
3306
3307 if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */
3308 /* Deal with pending register updates: */
3309#ifdef DEBUG
3310 printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);
3311#endif /* DEBUG */
0c2c5f61 3312 if (PENDING_OUT != PENDING_IN) {
8bae0a0c 3313 int loop;
0c2c5f61
AC		 3314 int index = PENDING_OUT;
3315 int total = PENDING_TOTAL;
3316 if (PENDING_TOTAL == 0) {
8bae0a0c
JSC		 3317 fprintf(stderr,"FATAL: Mis-match on pending update pointers\n");
3318 exit(1);
3319 }
3320 for (loop = 0; (loop < total); loop++) {
3321#ifdef DEBUG
3322 printf("DBG: BEFORE index = %d, loop = %d\n",index,loop);
3323#endif /* DEBUG */
0c2c5f61 3324 if (PENDING_SLOT_REG[index] != (LAST_EMBED_REGNUM + 1)) {
8bae0a0c 3325#ifdef DEBUG
0c2c5f61 3326 printf("pending_slot_count[%d] = %d\n",index,PENDING_SLOT_COUNT[index]);
8bae0a0c 3327#endif /* DEBUG */
0c2c5f61 3328 if (--(PENDING_SLOT_COUNT[index]) == 0) {
8bae0a0c 3329#ifdef DEBUG
0c2c5f61
AC		 3330 printf("pending_slot_reg[%d] = %d\n",index,PENDING_SLOT_REG[index]);
3331 printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(PENDING_SLOT_VALUE[index]));
8bae0a0c 3332#endif /* DEBUG */
0c2c5f61 3333 if (PENDING_SLOT_REG[index] == COCIDX) {
9cb8397f 3334#if defined(HASFPU)
8bae0a0c 3335 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
9cb8397f
GRK		 3336#else
3337 ;
3338#endif
8bae0a0c 3339 } else {
0c2c5f61 3340 REGISTERS[PENDING_SLOT_REG[index]] = PENDING_SLOT_VALUE[index];
8bae0a0c
JSC		 3341#if defined(HASFPU)
3342 /* The only time we have PENDING updates to FPU
3343 registers, is when performing binary transfers. This
3344 means we should update the register type field. */
0c2c5f61
AC		 3345 if ((PENDING_SLOT_REG[index] >= FGRIDX) && (PENDING_SLOT_REG[index] < (FGRIDX + 32)))
3346 FPR_STATE[PENDING_SLOT_REG[index] - FGRIDX] = fmt_uninterpreted;
8bae0a0c
JSC		 3347#endif /* HASFPU */
3348 }
3349#ifdef DEBUG
0c2c5f61 3350 printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG[index],pr_addr(REGISTERS[PENDING_SLOT_REG[index]]));
8bae0a0c 3351#endif /* DEBUG */
0c2c5f61
AC		 3352 PENDING_SLOT_REG[index] = (LAST_EMBED_REGNUM + 1);
3353 PENDING_OUT++;
3354 if (PENDING_OUT == PSLOTS)
3355 PENDING_OUT = 0;
3356 PENDING_TOTAL--;
8bae0a0c
JSC		 3357 }
3358 }
3359#ifdef DEBUG
3360 printf("DBG: AFTER index = %d, loop = %d\n",index,loop);
3361#endif /* DEBUG */
3362 index++;
3363 if (index == PSLOTS)
3364 index = 0;
3365 }
3366 }
3367#ifdef DEBUG
0c2c5f61 3368 printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);
8bae0a0c
JSC		 3369#endif /* DEBUG */
3370 }
3371
3372#if !defined(FASTSIM)
50a2a691
AC		 3373 if (sim_events_tickn (sd, pipeline_count))
3374 {
3375 /* cpu->cia = cia; */
3376 sim_events_process (sd);
3377 }
3378#else
2e61a3ad
AC		 3379 if (sim_events_tick (sd))
3380 {
3381 /* cpu->cia = cia; */
3382 sim_events_process (sd);
3383 }
50a2a691 3384#endif /* FASTSIM */
8bae0a0c 3385 }
8bae0a0c 3386}
16bd5d6e
AC		 3387#endif
3388
8bae0a0c 3389
53b9417e
DE		 3390/* This code copied from gdb's utils.c. Would like to share this code,
3391 but don't know of a common place where both could get to it. */
3392
3393/* Temporary storage using circular buffer */
3394#define NUMCELLS 16
3395#define CELLSIZE 32
3396static char*
3397get_cell()
3398{
3399 static char buf[NUMCELLS][CELLSIZE];
3400 static int cell=0;
3401 if (++cell>=NUMCELLS) cell=0;
3402 return buf[cell];
3403}
3404
3405/* Print routines to handle variable size regs, etc */
3406
3407/* Eliminate warning from compiler on 32-bit systems */
3408static int thirty_two = 32;
3409
3410char*
3411pr_addr(addr)
3412 SIM_ADDR addr;
3413{
3414 char *paddr_str=get_cell();
3415 switch (sizeof(addr))
3416 {
3417 case 8:
50a2a691 3418 sprintf(paddr_str,"%08lx%08lx",
53b9417e
DE		 3419 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3420 break;
3421 case 4:
50a2a691 3422 sprintf(paddr_str,"%08lx",(unsigned long)addr);
53b9417e
DE		 3423 break;
3424 case 2:
3425 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
3426 break;
3427 default:
3428 sprintf(paddr_str,"%x",addr);
3429 }
3430 return paddr_str;
3431}
3432
87e43259
AC		 3433char*
3434pr_uword64(addr)
3435 uword64 addr;
3436{
3437 char *paddr_str=get_cell();
50a2a691 3438 sprintf(paddr_str,"%08lx%08lx",
87e43259
AC		 3439 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3440 return paddr_str;
3441}
3442
3443
8bae0a0c
JSC		 3444/*---------------------------------------------------------------------------*/
3445/*> EOF interp.c <*/
GDB Binutils - Deliverables
This page took 0.301072 seconds and 4 git commands to generate.