Commit | Line | Data |
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8bae0a0c JSC |
1 | /*> interp.c <*/ |
2 | /* Simulator for the MIPS architecture. | |
3 | ||
4 | This file is part of the MIPS sim | |
5 | ||
6 | THIS SOFTWARE IS NOT COPYRIGHTED | |
7 | ||
8 | Cygnus offers the following for use in the public domain. Cygnus | |
9 | makes no warranty with regard to the software or it's performance | |
10 | and the user accepts the software "AS IS" with all faults. | |
11 | ||
12 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
13 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
14 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
15 | ||
16 | $Revision$ | |
17 | $Author$ | |
e3d12c65 | 18 | $Date$ |
8bae0a0c JSC |
19 | |
20 | NOTEs: | |
21 | ||
8bae0a0c JSC |
22 | The IDT monitor (found on the VR4300 board), seems to lie about |
23 | register contents. It seems to treat the registers as sign-extended | |
24 | 32-bit values. This cause *REAL* problems when single-stepping 64-bit | |
25 | code on the hardware. | |
26 | ||
27 | */ | |
28 | ||
e2f8ffb7 AC |
29 | /* The TRACE manifests enable the provision of extra features. If they |
30 | are not defined then a simpler (quicker) simulator is constructed | |
31 | without the required run-time checks, etc. */ | |
8bae0a0c JSC |
32 | #if 1 /* 0 to allow user build selection, 1 to force inclusion */ |
33 | #define TRACE (1) | |
8bae0a0c JSC |
34 | #endif |
35 | ||
2e61a3ad AC |
36 | #include "bfd.h" |
37 | #include "sim-main.h" | |
38 | #include "sim-utils.h" | |
39 | #include "sim-options.h" | |
50a2a691 | 40 | #include "sim-assert.h" |
2e61a3ad | 41 | |
4fa134be ILT |
42 | #include "config.h" |
43 | ||
8bae0a0c JSC |
44 | #include <stdio.h> |
45 | #include <stdarg.h> | |
46 | #include <ansidecl.h> | |
8bae0a0c JSC |
47 | #include <ctype.h> |
48 | #include <limits.h> | |
49 | #include <math.h> | |
4fa134be ILT |
50 | #ifdef HAVE_STDLIB_H |
51 | #include <stdlib.h> | |
52 | #endif | |
53 | #ifdef HAVE_STRING_H | |
54 | #include <string.h> | |
55 | #else | |
56 | #ifdef HAVE_STRINGS_H | |
57 | #include <strings.h> | |
58 | #endif | |
59 | #endif | |
8bae0a0c JSC |
60 | |
61 | #include "getopt.h" | |
62 | #include "libiberty.h" | |
9d52bcb7 | 63 | #include "bfd.h" |
8bae0a0c | 64 | #include "callback.h" /* GDB simulator callback interface */ |
e3d12c65 | 65 | #include "remote-sim.h" /* GDB simulator interface */ |
8bae0a0c | 66 | |
f24b7b69 JSC |
67 | #include "sysdep.h" |
68 | ||
53b9417e DE |
69 | #ifndef PARAMS |
70 | #define PARAMS(x) | |
71 | #endif | |
72 | ||
73 | char* pr_addr PARAMS ((SIM_ADDR addr)); | |
87e43259 | 74 | char* pr_uword64 PARAMS ((uword64 addr)); |
53b9417e | 75 | |
f24b7b69 | 76 | |
8bae0a0c | 77 | /* Get the simulator engine description, without including the code: */ |
192ae475 AC |
78 | #if (WITH_IGEN) |
79 | #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3) | |
80 | #else | |
8bae0a0c | 81 | #define SIM_MANIFESTS |
284e759d | 82 | #include "oengine.c" |
8bae0a0c | 83 | #undef SIM_MANIFESTS |
192ae475 | 84 | #endif |
8bae0a0c | 85 | |
01737f42 AC |
86 | /* Within interp.c we refer to the sim_state and sim_cpu directly. */ |
87 | #define SD sd | |
88 | #define CPU cpu | |
89 | ||
f7481d45 | 90 | |
8bae0a0c JSC |
91 | /* The following reserved instruction value is used when a simulator |
92 | trap is required. NOTE: Care must be taken, since this value may be | |
93 | used in later revisions of the MIPS ISA. */ | |
53b9417e DE |
94 | #define RSVD_INSTRUCTION (0x00000005) |
95 | #define RSVD_INSTRUCTION_MASK (0xFC00003F) | |
96 | ||
97 | #define RSVD_INSTRUCTION_ARG_SHIFT 6 | |
98 | #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF | |
99 | ||
8bae0a0c | 100 | |
6eedf3f4 MA |
101 | /* Bits in the Debug register */ |
102 | #define Debug_DBD 0x80000000 /* Debug Branch Delay */ | |
103 | #define Debug_DM 0x40000000 /* Debug Mode */ | |
104 | #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */ | |
105 | ||
106 | ||
107 | ||
8bae0a0c | 108 | |
8bae0a0c | 109 | |
e3d12c65 DE |
110 | /*---------------------------------------------------------------------------*/ |
111 | /*-- GDB simulator interface ------------------------------------------------*/ | |
112 | /*---------------------------------------------------------------------------*/ | |
113 | ||
0c2c5f61 | 114 | static void ColdReset PARAMS((SIM_DESC sd)); |
e3d12c65 DE |
115 | |
116 | /*---------------------------------------------------------------------------*/ | |
117 | ||
8bae0a0c | 118 | |
8bae0a0c | 119 | |
8bae0a0c | 120 | #define DELAYSLOT() {\ |
0c2c5f61 | 121 | if (STATE & simDELAYSLOT)\ |
18c64df6 | 122 | sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\ |
0c2c5f61 | 123 | STATE |= simDELAYSLOT;\ |
8bae0a0c JSC |
124 | } |
125 | ||
aaff8437 ILT |
126 | #define JALDELAYSLOT() {\ |
127 | DELAYSLOT ();\ | |
0c2c5f61 | 128 | STATE |= simJALDELAYSLOT;\ |
aaff8437 ILT |
129 | } |
130 | ||
8bae0a0c | 131 | #define NULLIFY() {\ |
0c2c5f61 AC |
132 | STATE &= ~simDELAYSLOT;\ |
133 | STATE |= simSKIPNEXT;\ | |
8bae0a0c JSC |
134 | } |
135 | ||
6eedf3f4 | 136 | #define CANCELDELAYSLOT() {\ |
0c2c5f61 AC |
137 | DSSTATE = 0;\ |
138 | STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\ | |
6eedf3f4 MA |
139 | } |
140 | ||
0c2c5f61 AC |
141 | #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0) |
142 | #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0) | |
aaff8437 | 143 | |
a9f7253f JSC |
144 | #define K0BASE (0x80000000) |
145 | #define K0SIZE (0x20000000) | |
146 | #define K1BASE (0xA0000000) | |
147 | #define K1SIZE (0x20000000) | |
525d929e AC |
148 | #define MONITOR_BASE (0xBFC00000) |
149 | #define MONITOR_SIZE (1 << 11) | |
150 | #define MEM_SIZE (2 << 20) | |
a9f7253f | 151 | |
8bae0a0c | 152 | #if defined(TRACE) |
4fa134be | 153 | static char *tracefile = "trace.din"; /* default filename for trace log */ |
030843d7 | 154 | FILE *tracefh = NULL; |
18c64df6 | 155 | static void open_trace PARAMS((SIM_DESC sd)); |
8bae0a0c JSC |
156 | #endif /* TRACE */ |
157 | ||
22de994d AC |
158 | #define OPTION_DINERO_TRACE 200 |
159 | #define OPTION_DINERO_FILE 201 | |
160 | ||
50a2a691 AC |
161 | static SIM_RC |
162 | mips_option_handler (sd, opt, arg) | |
163 | SIM_DESC sd; | |
164 | int opt; | |
165 | char *arg; | |
2e61a3ad | 166 | { |
01737f42 | 167 | int cpu_nr; |
50a2a691 AC |
168 | switch (opt) |
169 | { | |
22de994d | 170 | case OPTION_DINERO_TRACE: /* ??? */ |
50a2a691 AC |
171 | #if defined(TRACE) |
172 | /* Eventually the simTRACE flag could be treated as a toggle, to | |
173 | allow external control of the program points being traced | |
174 | (i.e. only from main onwards, excluding the run-time setup, | |
175 | etc.). */ | |
01737f42 | 176 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) |
50a2a691 | 177 | { |
01737f42 AC |
178 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); |
179 | if (arg == NULL) | |
180 | STATE |= simTRACE; | |
181 | else if (strcmp (arg, "yes") == 0) | |
182 | STATE |= simTRACE; | |
183 | else if (strcmp (arg, "no") == 0) | |
184 | STATE &= ~simTRACE; | |
185 | else if (strcmp (arg, "on") == 0) | |
186 | STATE |= simTRACE; | |
187 | else if (strcmp (arg, "off") == 0) | |
188 | STATE &= ~simTRACE; | |
189 | else | |
190 | { | |
191 | fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg); | |
192 | return SIM_RC_FAIL; | |
193 | } | |
50a2a691 AC |
194 | } |
195 | return SIM_RC_OK; | |
196 | #else /* !TRACE */ | |
197 | fprintf(stderr,"\ | |
22de994d | 198 | Simulator constructed without dinero tracing support (for performance).\n\ |
50a2a691 AC |
199 | Re-compile simulator with \"-DTRACE\" to enable this option.\n"); |
200 | return SIM_RC_FAIL; | |
201 | #endif /* !TRACE */ | |
202 | ||
22de994d | 203 | case OPTION_DINERO_FILE: |
50a2a691 AC |
204 | #if defined(TRACE) |
205 | if (optarg != NULL) { | |
206 | char *tmp; | |
207 | tmp = (char *)malloc(strlen(optarg) + 1); | |
208 | if (tmp == NULL) | |
209 | { | |
18c64df6 | 210 | sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg); |
50a2a691 AC |
211 | return SIM_RC_FAIL; |
212 | } | |
213 | else { | |
214 | strcpy(tmp,optarg); | |
215 | tracefile = tmp; | |
18c64df6 | 216 | sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile); |
50a2a691 AC |
217 | } |
218 | } | |
219 | #endif /* TRACE */ | |
220 | return SIM_RC_OK; | |
221 | ||
50a2a691 AC |
222 | } |
223 | ||
224 | return SIM_RC_OK; | |
2e61a3ad | 225 | } |
50a2a691 AC |
226 | |
227 | static const OPTION mips_options[] = | |
2e61a3ad | 228 | { |
22de994d AC |
229 | { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE}, |
230 | '\0', "on|off", "Enable dinero tracing", | |
50a2a691 | 231 | mips_option_handler }, |
22de994d AC |
232 | { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE}, |
233 | '\0', "FILE", "Write dinero trace to FILE", | |
50a2a691 | 234 | mips_option_handler }, |
50a2a691 AC |
235 | { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } |
236 | }; | |
237 | ||
238 | ||
56e7c849 AC |
239 | int interrupt_pending; |
240 | ||
50a2a691 AC |
241 | static void |
242 | interrupt_event (SIM_DESC sd, void *data) | |
2e61a3ad | 243 | { |
01737f42 | 244 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
56e7c849 AC |
245 | if (SR & status_IE) |
246 | { | |
247 | interrupt_pending = 0; | |
18c64df6 | 248 | SignalExceptionInterrupt (); |
56e7c849 AC |
249 | } |
250 | else if (!interrupt_pending) | |
251 | sim_events_schedule (sd, 1, interrupt_event, data); | |
2e61a3ad | 252 | } |
f7481d45 | 253 | |
f7481d45 | 254 | |
2c88fae9 IC |
255 | /*---------------------------------------------------------------------------*/ |
256 | /*-- Device registration hook -----------------------------------------------*/ | |
257 | /*---------------------------------------------------------------------------*/ | |
97908603 | 258 | static void device_init(SIM_DESC sd) { |
2c88fae9 IC |
259 | #ifdef DEVICE_INIT |
260 | extern void register_devices(SIM_DESC); | |
261 | register_devices(sd); | |
262 | #endif | |
263 | } | |
50a2a691 | 264 | |
97908603 RU |
265 | /* start-sanitize-sky */ |
266 | static struct { | |
267 | short i[16]; | |
268 | int f[NUM_VU_REGS - 16]; | |
269 | } vu_regs[2]; | |
270 | /* end-sanitize-sky */ | |
271 | ||
8bae0a0c JSC |
272 | /*---------------------------------------------------------------------------*/ |
273 | /*-- GDB simulator interface ------------------------------------------------*/ | |
274 | /*---------------------------------------------------------------------------*/ | |
275 | ||
53b9417e | 276 | SIM_DESC |
247fccde | 277 | sim_open (kind, cb, abfd, argv) |
87e43259 | 278 | SIM_OPEN_KIND kind; |
50a2a691 | 279 | host_callback *cb; |
247fccde | 280 | struct _bfd *abfd; |
53b9417e | 281 | char **argv; |
8bae0a0c | 282 | { |
18c64df6 | 283 | SIM_DESC sd = sim_state_alloc (kind, cb); |
01737f42 | 284 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
2e61a3ad | 285 | |
525d929e AC |
286 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
287 | ||
50a2a691 AC |
288 | /* FIXME: watchpoints code shouldn't need this */ |
289 | STATE_WATCHPOINTS (sd)->pc = &(PC); | |
290 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
291 | STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event; | |
292 | ||
0c2c5f61 | 293 | STATE = 0; |
50a2a691 | 294 | |
2e61a3ad AC |
295 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
296 | return 0; | |
50a2a691 | 297 | sim_add_option_table (sd, mips_options); |
2e61a3ad | 298 | |
63be8feb AC |
299 | /* Allocate core managed memory */ |
300 | ||
301 | /* the monitor */ | |
302 | sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE); | |
303 | /* For compatibility with the old code - under this (at level one) | |
304 | are the kernel spaces K0 & K1. Both of these map to a single | |
305 | smaller sub region */ | |
306 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x", | |
307 | K1BASE, K0SIZE, | |
308 | MEM_SIZE, /* actual size */ | |
309 | K0BASE); | |
310 | ||
2c88fae9 IC |
311 | device_init(sd); |
312 | ||
2e61a3ad AC |
313 | /* getopt will print the error message so we just have to exit if this fails. |
314 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
315 | print_filtered. */ | |
316 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
317 | { | |
318 | /* Uninstall the modules to avoid memory leaks, | |
319 | file descriptor leaks, etc. */ | |
320 | sim_module_uninstall (sd); | |
321 | return 0; | |
322 | } | |
2e61a3ad | 323 | |
fafce69a AC |
324 | /* check for/establish the a reference program image */ |
325 | if (sim_analyze_program (sd, | |
326 | (STATE_PROG_ARGV (sd) != NULL | |
327 | ? *STATE_PROG_ARGV (sd) | |
328 | : NULL), | |
329 | abfd) != SIM_RC_OK) | |
330 | { | |
331 | sim_module_uninstall (sd); | |
332 | return 0; | |
333 | } | |
334 | ||
247fccde AC |
335 | /* Configure/verify the target byte order and other runtime |
336 | configuration options */ | |
fafce69a | 337 | if (sim_config (sd) != SIM_RC_OK) |
247fccde AC |
338 | { |
339 | sim_module_uninstall (sd); | |
340 | return 0; | |
341 | } | |
342 | ||
2e61a3ad AC |
343 | if (sim_post_argv_init (sd) != SIM_RC_OK) |
344 | { | |
345 | /* Uninstall the modules to avoid memory leaks, | |
346 | file descriptor leaks, etc. */ | |
347 | sim_module_uninstall (sd); | |
348 | return 0; | |
349 | } | |
350 | ||
50a2a691 AC |
351 | /* verify assumptions the simulator made about the host type system. |
352 | This macro does not return if there is a problem */ | |
7ce8b917 AC |
353 | SIM_ASSERT (sizeof(int) == (4 * sizeof(char))); |
354 | SIM_ASSERT (sizeof(word64) == (8 * sizeof(char))); | |
8bae0a0c | 355 | |
8bae0a0c JSC |
356 | /* This is NASTY, in that we are assuming the size of specific |
357 | registers: */ | |
358 | { | |
359 | int rn; | |
a97f304b AC |
360 | for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) |
361 | { | |
362 | if (rn < 32) | |
363 | cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; | |
364 | else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR))) | |
365 | cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE; | |
366 | else if ((rn >= 33) && (rn <= 37)) | |
367 | cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; | |
368 | else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89))) | |
369 | cpu->register_widths[rn] = 32; | |
370 | else | |
371 | cpu->register_widths[rn] = 0; | |
372 | } | |
18c64df6 AC |
373 | /* start-sanitize-r5900 */ |
374 | ||
375 | /* set the 5900 "upper" registers to 64 bits */ | |
376 | for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++) | |
0c2c5f61 | 377 | cpu->register_widths[rn] = 64; |
18c64df6 | 378 | /* end-sanitize-r5900 */ |
97908603 RU |
379 | |
380 | /* start-sanitize-sky */ | |
381 | #ifdef TARGET_SKY | |
382 | /* Now the VU registers */ | |
383 | for( rn = 0; rn < 16; rn++ ) { /* first the integer registers */ | |
384 | cpu->register_widths[rn + NUM_R5900_REGS] = 16; | |
385 | cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16; | |
386 | ||
387 | /* Hack for now - to test gdb interface */ | |
388 | vu_regs[0].i[rn] = rn + 0x100; | |
389 | vu_regs[1].i[rn] = rn + 0x200; | |
390 | } | |
391 | ||
392 | for( rn = 16; rn < NUM_VU_REGS; rn++ ) { /* then the FP registers */ | |
393 | float f; | |
394 | ||
395 | cpu->register_widths[rn + NUM_R5900_REGS] = 32; | |
396 | cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32; | |
397 | ||
398 | /* Hack for now - to test gdb interface */ | |
399 | if( rn < 24 ) { | |
400 | f = rn - 16 + 100.0; | |
401 | vu_regs[0].f[rn-16] = *((unsigned *) &f); | |
402 | f = rn - 16 + 200.0; | |
403 | vu_regs[1].f[rn-16] = *((unsigned *) &f); | |
404 | } | |
405 | else { | |
406 | f = (rn - 24)/4 + (rn - 24)%4 + 1000.0; | |
407 | vu_regs[0].f[rn-16] = *((unsigned *) &f); | |
408 | f = (rn - 24)/4 + (rn - 24)%4 + 2000.0; | |
409 | vu_regs[1].f[rn-16] = *((unsigned *) &f); | |
410 | } | |
411 | } | |
412 | #endif | |
413 | /* end-sanitize-sky */ | |
8bae0a0c JSC |
414 | } |
415 | ||
8bae0a0c | 416 | #if defined(TRACE) |
0c2c5f61 | 417 | if (STATE & simTRACE) |
18c64df6 | 418 | open_trace(sd); |
8bae0a0c JSC |
419 | #endif /* TRACE */ |
420 | ||
fafce69a AC |
421 | /* Write the monitor trap address handlers into the monitor (eeprom) |
422 | address space. This can only be done once the target endianness | |
423 | has been determined. */ | |
424 | { | |
425 | unsigned loop; | |
426 | /* Entry into the IDT monitor is via fixed address vectors, and | |
427 | not using machine instructions. To avoid clashing with use of | |
428 | the MIPS TRAP system, we place our own (simulator specific) | |
429 | "undefined" instructions into the relevant vector slots. */ | |
525d929e AC |
430 | for (loop = 0; (loop < MONITOR_SIZE); loop += 4) |
431 | { | |
432 | address_word vaddr = (MONITOR_BASE + loop); | |
433 | unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT)); | |
434 | H2T (insn); | |
435 | sim_write (sd, vaddr, (char *)&insn, sizeof (insn)); | |
436 | } | |
fafce69a AC |
437 | /* The PMON monitor uses the same address space, but rather than |
438 | branching into it the address of a routine is loaded. We can | |
439 | cheat for the moment, and direct the PMON routine to IDT style | |
440 | instructions within the monitor space. This relies on the IDT | |
441 | monitor not using the locations from 0xBFC00500 onwards as its | |
442 | entry points.*/ | |
443 | for (loop = 0; (loop < 24); loop++) | |
444 | { | |
525d929e AC |
445 | address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4)); |
446 | unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */ | |
fafce69a AC |
447 | switch (loop) |
448 | { | |
449 | case 0: /* read */ | |
450 | value = 7; | |
451 | break; | |
fafce69a AC |
452 | case 1: /* write */ |
453 | value = 8; | |
454 | break; | |
fafce69a AC |
455 | case 2: /* open */ |
456 | value = 6; | |
457 | break; | |
fafce69a AC |
458 | case 3: /* close */ |
459 | value = 10; | |
460 | break; | |
fafce69a AC |
461 | case 5: /* printf */ |
462 | value = ((0x500 - 16) / 8); /* not an IDT reason code */ | |
463 | break; | |
fafce69a AC |
464 | case 8: /* cliexit */ |
465 | value = 17; | |
466 | break; | |
fafce69a AC |
467 | case 11: /* flush_cache */ |
468 | value = 28; | |
469 | break; | |
470 | } | |
525d929e AC |
471 | /* FIXME - should monitor_base be SIM_ADDR?? */ |
472 | value = ((unsigned int)MONITOR_BASE + (value * 8)); | |
473 | H2T (value); | |
474 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); | |
fafce69a AC |
475 | |
476 | /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */ | |
477 | vaddr -= 0x300; | |
525d929e | 478 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); |
fafce69a AC |
479 | } |
480 | } | |
481 | ||
2e61a3ad | 482 | return sd; |
8bae0a0c JSC |
483 | } |
484 | ||
6429b296 JW |
485 | #if defined(TRACE) |
486 | static void | |
18c64df6 AC |
487 | open_trace(sd) |
488 | SIM_DESC sd; | |
6429b296 JW |
489 | { |
490 | tracefh = fopen(tracefile,"wb+"); | |
491 | if (tracefh == NULL) | |
492 | { | |
18c64df6 | 493 | sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile); |
6429b296 JW |
494 | tracefh = stderr; |
495 | } | |
496 | } | |
497 | #endif /* TRACE */ | |
498 | ||
8bae0a0c | 499 | void |
53b9417e DE |
500 | sim_close (sd, quitting) |
501 | SIM_DESC sd; | |
8bae0a0c JSC |
502 | int quitting; |
503 | { | |
504 | #ifdef DEBUG | |
505 | printf("DBG: sim_close: entered (quitting = %d)\n",quitting); | |
506 | #endif | |
507 | ||
8bae0a0c JSC |
508 | /* "quitting" is non-zero if we cannot hang on errors */ |
509 | ||
510 | /* Ensure that any resources allocated through the callback | |
511 | mechanism are released: */ | |
18c64df6 | 512 | sim_io_shutdown (sd); |
8bae0a0c | 513 | |
8bae0a0c | 514 | #if defined(TRACE) |
e3d12c65 | 515 | if (tracefh != NULL && tracefh != stderr) |
8bae0a0c | 516 | fclose(tracefh); |
e3d12c65 | 517 | tracefh = NULL; |
8bae0a0c JSC |
518 | #endif /* TRACE */ |
519 | ||
01737f42 AC |
520 | /* FIXME - free SD */ |
521 | ||
8bae0a0c JSC |
522 | return; |
523 | } | |
524 | ||
8bae0a0c JSC |
525 | |
526 | int | |
53b9417e DE |
527 | sim_write (sd,addr,buffer,size) |
528 | SIM_DESC sd; | |
8bae0a0c JSC |
529 | SIM_ADDR addr; |
530 | unsigned char *buffer; | |
531 | int size; | |
532 | { | |
525d929e | 533 | int index; |
01737f42 | 534 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
8bae0a0c JSC |
535 | |
536 | /* Return the number of bytes written, or zero if error. */ | |
537 | #ifdef DEBUG | |
18c64df6 | 538 | sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
539 | #endif |
540 | ||
525d929e AC |
541 | /* We use raw read and write routines, since we do not want to count |
542 | the GDB memory accesses in our statistics gathering. */ | |
543 | ||
544 | for (index = 0; index < size; index++) | |
545 | { | |
546 | address_word vaddr = (address_word)addr + index; | |
547 | address_word paddr; | |
548 | int cca; | |
01737f42 | 549 | if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW)) |
525d929e | 550 | break; |
01737f42 | 551 | if (sim_core_write_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1) |
63be8feb | 552 | break; |
8bae0a0c | 553 | } |
8bae0a0c | 554 | |
525d929e | 555 | return(index); |
8bae0a0c JSC |
556 | } |
557 | ||
558 | int | |
53b9417e DE |
559 | sim_read (sd,addr,buffer,size) |
560 | SIM_DESC sd; | |
8bae0a0c JSC |
561 | SIM_ADDR addr; |
562 | unsigned char *buffer; | |
563 | int size; | |
564 | { | |
565 | int index; | |
01737f42 | 566 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
8bae0a0c JSC |
567 | |
568 | /* Return the number of bytes read, or zero if error. */ | |
569 | #ifdef DEBUG | |
18c64df6 | 570 | sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
571 | #endif /* DEBUG */ |
572 | ||
525d929e AC |
573 | for (index = 0; (index < size); index++) |
574 | { | |
575 | address_word vaddr = (address_word)addr + index; | |
576 | address_word paddr; | |
525d929e | 577 | int cca; |
01737f42 | 578 | if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW)) |
525d929e | 579 | break; |
01737f42 | 580 | if (sim_core_read_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1) |
63be8feb | 581 | break; |
525d929e | 582 | } |
8bae0a0c JSC |
583 | |
584 | return(index); | |
585 | } | |
586 | ||
587 | void | |
53b9417e DE |
588 | sim_store_register (sd,rn,memory) |
589 | SIM_DESC sd; | |
8bae0a0c JSC |
590 | int rn; |
591 | unsigned char *memory; | |
592 | { | |
01737f42 | 593 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
50a2a691 AC |
594 | /* NOTE: gdb (the client) stores registers in target byte order |
595 | while the simulator uses host byte order */ | |
8bae0a0c | 596 | #ifdef DEBUG |
18c64df6 | 597 | sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory))); |
8bae0a0c JSC |
598 | #endif /* DEBUG */ |
599 | ||
600 | /* Unfortunately this suffers from the same problem as the register | |
601 | numbering one. We need to know what the width of each logical | |
602 | register number is for the architecture being simulated. */ | |
50a2a691 | 603 | |
0c2c5f61 | 604 | if (cpu->register_widths[rn] == 0) |
18c64df6 | 605 | sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn); |
97908603 RU |
606 | /* start-sanitize-sky */ |
607 | #ifdef TARGET_SKY | |
608 | else if( rn > NUM_R5900_REGS ) { | |
609 | rn = rn - NUM_R5900_REGS; | |
610 | ||
611 | if( rn < 16 ) | |
612 | vu_regs[0].i[rn] = T2H_2( *(unsigned short *) memory ); | |
613 | else if( rn < NUM_VU_REGS ) | |
614 | vu_regs[0].f[rn - 16] = T2H_4( *(unsigned int *) memory ); | |
615 | else { | |
616 | rn = rn - NUM_VU_REGS; | |
617 | ||
618 | if( rn < 16 ) | |
619 | vu_regs[1].i[rn] = T2H_2( *(unsigned short *) memory ); | |
620 | else if( rn < NUM_VU_REGS ) | |
621 | vu_regs[1].f[rn - 16] = T2H_4( *(unsigned int *) memory ); | |
622 | else | |
623 | sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" ); | |
624 | } | |
625 | } | |
626 | #endif | |
627 | /* end-sanitize-sky */ | |
18c64df6 AC |
628 | /* start-sanitize-r5900 */ |
629 | else if (rn == REGISTER_SA) | |
a97f304b | 630 | SA = T2H_8(*(unsigned64*)memory); |
18c64df6 | 631 | else if (rn > LAST_EMBED_REGNUM) |
a97f304b | 632 | cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(unsigned64*)memory); |
18c64df6 | 633 | /* end-sanitize-r5900 */ |
a97f304b AC |
634 | else if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) |
635 | { | |
636 | if (cpu->register_widths[rn] == 32) | |
637 | cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory); | |
638 | else | |
639 | cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory); | |
640 | } | |
0c2c5f61 | 641 | else if (cpu->register_widths[rn] == 32) |
a97f304b | 642 | cpu->registers[rn] = T2H_4 (*(unsigned32*)memory); |
50a2a691 | 643 | else |
a97f304b | 644 | cpu->registers[rn] = T2H_8 (*(unsigned64*)memory); |
8bae0a0c JSC |
645 | |
646 | return; | |
647 | } | |
648 | ||
649 | void | |
53b9417e DE |
650 | sim_fetch_register (sd,rn,memory) |
651 | SIM_DESC sd; | |
8bae0a0c JSC |
652 | int rn; |
653 | unsigned char *memory; | |
654 | { | |
01737f42 | 655 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
50a2a691 AC |
656 | /* NOTE: gdb (the client) stores registers in target byte order |
657 | while the simulator uses host byte order */ | |
8bae0a0c | 658 | #ifdef DEBUG |
18c64df6 | 659 | sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn])); |
8bae0a0c JSC |
660 | #endif /* DEBUG */ |
661 | ||
0c2c5f61 | 662 | if (cpu->register_widths[rn] == 0) |
18c64df6 | 663 | sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn); |
97908603 RU |
664 | /* start-sanitize-sky */ |
665 | #ifdef TARGET_SKY | |
666 | else if( rn > NUM_R5900_REGS ) { | |
667 | rn = rn - NUM_R5900_REGS; | |
668 | ||
669 | if( rn < 16 ) | |
670 | *((unsigned short *) memory) = H2T_2( vu_regs[0].i[rn] ); | |
671 | else if( rn < NUM_VU_REGS ) | |
672 | *((unsigned int *) memory) = H2T_4( vu_regs[0].f[rn - 16] ); | |
673 | else { | |
674 | rn = rn - NUM_VU_REGS; | |
675 | ||
676 | if( rn < 16 ) | |
677 | (*(unsigned short *) memory) = H2T_2( vu_regs[1].i[rn] ); | |
678 | else if( rn < NUM_VU_REGS ) | |
679 | (*(unsigned int *) memory) = H2T_4( vu_regs[1].f[rn - 16] ); | |
680 | else | |
681 | sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" ); | |
682 | } | |
683 | } | |
684 | #endif | |
685 | /* end-sanitize-sky */ | |
18c64df6 AC |
686 | /* start-sanitize-r5900 */ |
687 | else if (rn == REGISTER_SA) | |
a97f304b | 688 | *((unsigned64*)memory) = H2T_8(SA); |
18c64df6 | 689 | else if (rn > LAST_EMBED_REGNUM) |
a97f304b | 690 | *((unsigned64*)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]); |
18c64df6 | 691 | /* end-sanitize-r5900 */ |
a97f304b AC |
692 | else if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) |
693 | { | |
694 | if (cpu->register_widths[rn] == 32) | |
695 | *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]); | |
696 | else | |
697 | *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]); | |
698 | } | |
0c2c5f61 | 699 | else if (cpu->register_widths[rn] == 32) |
a97f304b | 700 | *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn])); |
18c64df6 | 701 | else /* 64bit register */ |
a97f304b | 702 | *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn])); |
50a2a691 | 703 | |
8bae0a0c JSC |
704 | return; |
705 | } | |
50a2a691 | 706 | |
8bae0a0c JSC |
707 | |
708 | void | |
53b9417e DE |
709 | sim_info (sd,verbose) |
710 | SIM_DESC sd; | |
8bae0a0c JSC |
711 | int verbose; |
712 | { | |
713 | /* Accessed from the GDB "info files" command: */ | |
56e7c849 AC |
714 | if (STATE_VERBOSE_P (sd) || verbose) |
715 | { | |
716 | ||
717 | sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n", | |
192ae475 | 718 | WITH_TARGET_WORD_BITSIZE, |
56e7c849 AC |
719 | (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little")); |
720 | ||
8bae0a0c | 721 | #if !defined(FASTSIM) |
56e7c849 AC |
722 | /* It would be a useful feature, if when performing multi-cycle |
723 | simulations (rather than single-stepping) we keep the start and | |
724 | end times of the execution, so that we can give a performance | |
725 | figure for the simulator. */ | |
8bae0a0c | 726 | #endif /* !FASTSIM */ |
56e7c849 AC |
727 | sim_io_printf (sd, "Number of execution cycles = %ld\n", |
728 | (long) sim_events_time (sd)); | |
729 | ||
730 | /* print information pertaining to MIPS ISA and architecture being simulated */ | |
731 | /* things that may be interesting */ | |
732 | /* instructions executed - if available */ | |
733 | /* cycles executed - if available */ | |
734 | /* pipeline stalls - if available */ | |
735 | /* virtual time taken */ | |
736 | /* profiling size */ | |
737 | /* profiling frequency */ | |
738 | /* profile minpc */ | |
739 | /* profile maxpc */ | |
740 | } | |
aa324b9b | 741 | profile_print (sd, STATE_VERBOSE_P (sd), NULL, NULL); |
8bae0a0c JSC |
742 | } |
743 | ||
8bae0a0c | 744 | |
9d52bcb7 | 745 | SIM_RC |
fafce69a | 746 | sim_create_inferior (sd, abfd, argv,env) |
53b9417e | 747 | SIM_DESC sd; |
fafce69a | 748 | struct _bfd *abfd; |
8bae0a0c JSC |
749 | char **argv; |
750 | char **env; | |
751 | { | |
50a2a691 | 752 | |
8bae0a0c | 753 | #ifdef DEBUG |
9d52bcb7 DE |
754 | printf("DBG: sim_create_inferior entered: start_address = 0x%s\n", |
755 | pr_addr(PC)); | |
8bae0a0c JSC |
756 | #endif /* DEBUG */ |
757 | ||
0c2c5f61 | 758 | ColdReset(sd); |
50a2a691 | 759 | |
fafce69a | 760 | if (abfd != NULL) |
01737f42 AC |
761 | { |
762 | /* override PC value set by ColdReset () */ | |
763 | int cpu_nr; | |
764 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) | |
765 | { | |
766 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); | |
767 | CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd)); | |
768 | } | |
769 | } | |
2e61a3ad | 770 | |
f24b7b69 | 771 | #if 0 /* def DEBUG */ |
dad6f1f3 | 772 | if (argv || env) |
8bae0a0c | 773 | { |
dad6f1f3 AC |
774 | /* We should really place the argv slot values into the argument |
775 | registers, and onto the stack as required. However, this | |
776 | assumes that we have a stack defined, which is not | |
777 | necessarily true at the moment. */ | |
778 | char **cptr; | |
779 | sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n"); | |
780 | for (cptr = argv; (cptr && *cptr); cptr++) | |
781 | printf("DBG: arg \"%s\"\n",*cptr); | |
8bae0a0c JSC |
782 | } |
783 | #endif /* DEBUG */ | |
8bae0a0c | 784 | |
9d52bcb7 | 785 | return SIM_RC_OK; |
8bae0a0c JSC |
786 | } |
787 | ||
8bae0a0c | 788 | void |
53b9417e DE |
789 | sim_do_command (sd,cmd) |
790 | SIM_DESC sd; | |
8bae0a0c JSC |
791 | char *cmd; |
792 | { | |
63be8feb AC |
793 | if (sim_args_command (sd, cmd) != SIM_RC_OK) |
794 | sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n", | |
795 | cmd); | |
8bae0a0c JSC |
796 | } |
797 | ||
8bae0a0c JSC |
798 | /*---------------------------------------------------------------------------*/ |
799 | /*-- Private simulator support interface ------------------------------------*/ | |
800 | /*---------------------------------------------------------------------------*/ | |
801 | ||
525d929e AC |
802 | /* Read a null terminated string from memory, return in a buffer */ |
803 | static char * | |
804 | fetch_str (sd, addr) | |
805 | SIM_DESC sd; | |
806 | address_word addr; | |
807 | { | |
808 | char *buf; | |
809 | int nr = 0; | |
810 | char null; | |
811 | while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0) | |
812 | nr++; | |
813 | buf = NZALLOC (char, nr + 1); | |
814 | sim_read (sd, addr, buf, nr); | |
815 | return buf; | |
816 | } | |
817 | ||
a9f7253f | 818 | /* Simple monitor interface (currently setup for the IDT and PMON monitors) */ |
8bae0a0c | 819 | static void |
01737f42 AC |
820 | sim_monitor (SIM_DESC sd, |
821 | sim_cpu *cpu, | |
822 | address_word cia, | |
823 | unsigned int reason) | |
8bae0a0c | 824 | { |
53b9417e DE |
825 | #ifdef DEBUG |
826 | printf("DBG: sim_monitor: entered (reason = %d)\n",reason); | |
827 | #endif /* DEBUG */ | |
828 | ||
8bae0a0c JSC |
829 | /* The IDT monitor actually allows two instructions per vector |
830 | slot. However, the simulator currently causes a trap on each | |
831 | individual instruction. We cheat, and lose the bottom bit. */ | |
832 | reason >>= 1; | |
833 | ||
834 | /* The following callback functions are available, however the | |
835 | monitor we are simulating does not make use of them: get_errno, | |
836 | isatty, lseek, rename, system, time and unlink */ | |
525d929e AC |
837 | switch (reason) |
838 | { | |
839 | ||
8bae0a0c JSC |
840 | case 6: /* int open(char *path,int flags) */ |
841 | { | |
525d929e AC |
842 | char *path = fetch_str (sd, A0); |
843 | V0 = sim_io_open (sd, path, (int)A1); | |
844 | zfree (path); | |
845 | break; | |
8bae0a0c | 846 | } |
8bae0a0c JSC |
847 | |
848 | case 7: /* int read(int file,char *ptr,int len) */ | |
849 | { | |
525d929e AC |
850 | int fd = A0; |
851 | int nr = A2; | |
852 | char *buf = zalloc (nr); | |
853 | V0 = sim_io_read (sd, fd, buf, nr); | |
854 | sim_write (sd, A1, buf, nr); | |
855 | zfree (buf); | |
8bae0a0c JSC |
856 | } |
857 | break; | |
858 | ||
859 | case 8: /* int write(int file,char *ptr,int len) */ | |
860 | { | |
525d929e AC |
861 | int fd = A0; |
862 | int nr = A2; | |
863 | char *buf = zalloc (nr); | |
864 | sim_read (sd, A1, buf, nr); | |
865 | V0 = sim_io_write (sd, fd, buf, nr); | |
866 | zfree (buf); | |
867 | break; | |
8bae0a0c | 868 | } |
8bae0a0c JSC |
869 | |
870 | case 10: /* int close(int file) */ | |
525d929e AC |
871 | { |
872 | V0 = sim_io_close (sd, (int)A0); | |
873 | break; | |
874 | } | |
8bae0a0c | 875 | |
e0e0fc76 MA |
876 | case 2: /* Densan monitor: char inbyte(int waitflag) */ |
877 | { | |
878 | if (A0 == 0) /* waitflag == NOWAIT */ | |
192ae475 | 879 | V0 = (unsigned_word)-1; |
e0e0fc76 MA |
880 | } |
881 | /* Drop through to case 11 */ | |
882 | ||
8bae0a0c JSC |
883 | case 11: /* char inbyte(void) */ |
884 | { | |
885 | char tmp; | |
525d929e AC |
886 | if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char)) |
887 | { | |
888 | sim_io_error(sd,"Invalid return from character read"); | |
192ae475 | 889 | V0 = (unsigned_word)-1; |
525d929e | 890 | } |
8bae0a0c | 891 | else |
192ae475 | 892 | V0 = (unsigned_word)tmp; |
525d929e | 893 | break; |
8bae0a0c | 894 | } |
8bae0a0c | 895 | |
e0e0fc76 | 896 | case 3: /* Densan monitor: void co(char chr) */ |
8bae0a0c JSC |
897 | case 12: /* void outbyte(char chr) : write a byte to "stdout" */ |
898 | { | |
899 | char tmp = (char)(A0 & 0xFF); | |
525d929e AC |
900 | sim_io_write_stdout (sd, &tmp, sizeof(char)); |
901 | break; | |
8bae0a0c | 902 | } |
8bae0a0c JSC |
903 | |
904 | case 17: /* void _exit() */ | |
525d929e AC |
905 | { |
906 | sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n"); | |
01737f42 | 907 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited, |
525d929e AC |
908 | (unsigned int)(A0 & 0xFFFFFFFF)); |
909 | break; | |
910 | } | |
8bae0a0c | 911 | |
280f90e1 AMT |
912 | case 28 : /* PMON flush_cache */ |
913 | break; | |
914 | ||
8bae0a0c JSC |
915 | case 55: /* void get_mem_info(unsigned int *ptr) */ |
916 | /* in: A0 = pointer to three word memory location */ | |
917 | /* out: [A0 + 0] = size */ | |
918 | /* [A0 + 4] = instruction cache size */ | |
919 | /* [A0 + 8] = data cache size */ | |
920 | { | |
525d929e AC |
921 | address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */; |
922 | H2T (value); | |
923 | sim_write (sd, A0, (char *)&value, sizeof (value)); | |
030843d7 | 924 | /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */ |
525d929e | 925 | break; |
8bae0a0c | 926 | } |
525d929e | 927 | |
a9f7253f JSC |
928 | case 158 : /* PMON printf */ |
929 | /* in: A0 = pointer to format string */ | |
930 | /* A1 = optional argument 1 */ | |
931 | /* A2 = optional argument 2 */ | |
932 | /* A3 = optional argument 3 */ | |
933 | /* out: void */ | |
f24b7b69 | 934 | /* The following is based on the PMON printf source */ |
a9f7253f | 935 | { |
525d929e AC |
936 | address_word s = A0; |
937 | char c; | |
938 | signed_word *ap = &A1; /* 1st argument */ | |
f24b7b69 JSC |
939 | /* This isn't the quickest way, since we call the host print |
940 | routine for every character almost. But it does avoid | |
941 | having to allocate and manage a temporary string buffer. */ | |
525d929e AC |
942 | /* TODO: Include check that we only use three arguments (A1, |
943 | A2 and A3) */ | |
944 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
945 | { | |
946 | if (c == '%') | |
947 | { | |
948 | char tmp[40]; | |
949 | enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST; | |
950 | int width = 0, trunc = 0, haddot = 0, longlong = 0; | |
951 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
952 | { | |
953 | if (strchr ("dobxXulscefg%", s)) | |
954 | break; | |
955 | else if (c == '-') | |
956 | fmt = FMT_LJUST; | |
957 | else if (c == '0') | |
958 | fmt = FMT_RJUST0; | |
959 | else if (c == '~') | |
960 | fmt = FMT_CENTER; | |
961 | else if (c == '*') | |
962 | { | |
963 | if (haddot) | |
964 | trunc = (int)*ap++; | |
965 | else | |
966 | width = (int)*ap++; | |
967 | } | |
968 | else if (c >= '1' && c <= '9') | |
969 | { | |
970 | address_word t = s; | |
971 | unsigned int n; | |
972 | while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c)) | |
973 | tmp[s - t] = c; | |
974 | tmp[s - t] = '\0'; | |
975 | n = (unsigned int)strtol(tmp,NULL,10); | |
976 | if (haddot) | |
977 | trunc = n; | |
978 | else | |
979 | width = n; | |
980 | s--; | |
981 | } | |
982 | else if (c == '.') | |
983 | haddot = 1; | |
984 | } | |
985 | switch (c) | |
986 | { | |
987 | case '%': | |
988 | sim_io_printf (sd, "%%"); | |
989 | break; | |
990 | case 's': | |
991 | if ((int)*ap != 0) | |
992 | { | |
993 | address_word p = *ap++; | |
994 | char ch; | |
995 | while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0') | |
996 | sim_io_printf(sd, "%c", ch); | |
997 | } | |
998 | else | |
999 | sim_io_printf(sd,"(null)"); | |
1000 | break; | |
1001 | case 'c': | |
1002 | sim_io_printf (sd, "%c", (int)*ap++); | |
1003 | break; | |
1004 | default: | |
1005 | if (c == 'l') | |
1006 | { | |
1007 | sim_read (sd, s++, &c, 1); | |
1008 | if (c == 'l') | |
1009 | { | |
1010 | longlong = 1; | |
1011 | sim_read (sd, s++, &c, 1); | |
1012 | } | |
1013 | } | |
1014 | if (strchr ("dobxXu", c)) | |
1015 | { | |
1016 | word64 lv = (word64) *ap++; | |
1017 | if (c == 'b') | |
1018 | sim_io_printf(sd,"<binary not supported>"); | |
1019 | else | |
1020 | { | |
1021 | sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c); | |
1022 | if (longlong) | |
1023 | sim_io_printf(sd, tmp, lv); | |
1024 | else | |
1025 | sim_io_printf(sd, tmp, (int)lv); | |
1026 | } | |
1027 | } | |
1028 | else if (strchr ("eEfgG", c)) | |
1029 | { | |
1030 | double dbl = *(double*)(ap++); | |
1031 | sprintf (tmp, "%%%d.%d%c", width, trunc, c); | |
1032 | sim_io_printf (sd, tmp, dbl); | |
1033 | trunc = 0; | |
1034 | } | |
1035 | } | |
1036 | } | |
1037 | else | |
1038 | sim_io_printf(sd, "%c", c); | |
1039 | } | |
1040 | break; | |
a9f7253f | 1041 | } |
a9f7253f | 1042 | |
8bae0a0c | 1043 | default: |
525d929e | 1044 | sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n", |
95469ceb | 1045 | reason, pr_addr(cia)); |
8bae0a0c JSC |
1046 | break; |
1047 | } | |
1048 | return; | |
1049 | } | |
1050 | ||
7e6c297e ILT |
1051 | /* Store a word into memory. */ |
1052 | ||
1053 | static void | |
01737f42 AC |
1054 | store_word (SIM_DESC sd, |
1055 | sim_cpu *cpu, | |
1056 | address_word cia, | |
1057 | uword64 vaddr, | |
192ae475 | 1058 | signed_word val) |
7e6c297e | 1059 | { |
dad6f1f3 | 1060 | address_word paddr; |
7e6c297e ILT |
1061 | int uncached; |
1062 | ||
1063 | if ((vaddr & 3) != 0) | |
18c64df6 | 1064 | SignalExceptionAddressStore (); |
7e6c297e ILT |
1065 | else |
1066 | { | |
1067 | if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, | |
1068 | isTARGET, isREAL)) | |
1069 | { | |
1070 | const uword64 mask = 7; | |
1071 | uword64 memval; | |
1072 | unsigned int byte; | |
1073 | ||
1074 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)); | |
1075 | byte = (vaddr & mask) ^ (BigEndianCPU << 2); | |
1076 | memval = ((uword64) val) << (8 * byte); | |
53b9417e | 1077 | StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, |
7e6c297e ILT |
1078 | isREAL); |
1079 | } | |
1080 | } | |
1081 | } | |
1082 | ||
1083 | /* Load a word from memory. */ | |
1084 | ||
192ae475 | 1085 | static signed_word |
01737f42 AC |
1086 | load_word (SIM_DESC sd, |
1087 | sim_cpu *cpu, | |
1088 | address_word cia, | |
1089 | uword64 vaddr) | |
7e6c297e ILT |
1090 | { |
1091 | if ((vaddr & 3) != 0) | |
18c64df6 | 1092 | SignalExceptionAddressLoad (); |
7e6c297e ILT |
1093 | else |
1094 | { | |
dad6f1f3 | 1095 | address_word paddr; |
7e6c297e ILT |
1096 | int uncached; |
1097 | ||
1098 | if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, | |
1099 | isTARGET, isREAL)) | |
1100 | { | |
1101 | const uword64 mask = 0x7; | |
1102 | const unsigned int reverse = ReverseEndian ? 1 : 0; | |
1103 | const unsigned int bigend = BigEndianCPU ? 1 : 0; | |
1104 | uword64 memval; | |
1105 | unsigned int byte; | |
1106 | ||
1107 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2)); | |
53b9417e | 1108 | LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr, |
7e6c297e ILT |
1109 | isDATA, isREAL); |
1110 | byte = (vaddr & mask) ^ (bigend << 2); | |
1111 | return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32); | |
1112 | } | |
1113 | } | |
1114 | ||
1115 | return 0; | |
1116 | } | |
1117 | ||
1118 | /* Simulate the mips16 entry and exit pseudo-instructions. These | |
1119 | would normally be handled by the reserved instruction exception | |
1120 | code, but for ease of simulation we just handle them directly. */ | |
1121 | ||
1122 | static void | |
01737f42 AC |
1123 | mips16_entry (SIM_DESC sd, |
1124 | sim_cpu *cpu, | |
1125 | address_word cia, | |
1126 | unsigned int insn) | |
7e6c297e ILT |
1127 | { |
1128 | int aregs, sregs, rreg; | |
1129 | ||
53b9417e DE |
1130 | #ifdef DEBUG |
1131 | printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn); | |
1132 | #endif /* DEBUG */ | |
1133 | ||
7e6c297e ILT |
1134 | aregs = (insn & 0x700) >> 8; |
1135 | sregs = (insn & 0x0c0) >> 6; | |
1136 | rreg = (insn & 0x020) >> 5; | |
1137 | ||
da0bce9c ILT |
1138 | /* This should be checked by the caller. */ |
1139 | if (sregs == 3) | |
7e6c297e ILT |
1140 | abort (); |
1141 | ||
da0bce9c | 1142 | if (aregs < 5) |
7e6c297e ILT |
1143 | { |
1144 | int i; | |
192ae475 | 1145 | signed_word tsp; |
7e6c297e ILT |
1146 | |
1147 | /* This is the entry pseudo-instruction. */ | |
1148 | ||
1149 | for (i = 0; i < aregs; i++) | |
01737f42 | 1150 | store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]); |
7e6c297e ILT |
1151 | |
1152 | tsp = SP; | |
1153 | SP -= 32; | |
1154 | ||
1155 | if (rreg) | |
1156 | { | |
1157 | tsp -= 4; | |
01737f42 | 1158 | store_word (SD, CPU, cia, (uword64) tsp, RA); |
7e6c297e ILT |
1159 | } |
1160 | ||
1161 | for (i = 0; i < sregs; i++) | |
1162 | { | |
1163 | tsp -= 4; | |
01737f42 | 1164 | store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]); |
7e6c297e ILT |
1165 | } |
1166 | } | |
1167 | else | |
1168 | { | |
1169 | int i; | |
192ae475 | 1170 | signed_word tsp; |
7e6c297e ILT |
1171 | |
1172 | /* This is the exit pseudo-instruction. */ | |
1173 | ||
1174 | tsp = SP + 32; | |
1175 | ||
1176 | if (rreg) | |
1177 | { | |
1178 | tsp -= 4; | |
01737f42 | 1179 | RA = load_word (SD, CPU, cia, (uword64) tsp); |
7e6c297e ILT |
1180 | } |
1181 | ||
1182 | for (i = 0; i < sregs; i++) | |
1183 | { | |
1184 | tsp -= 4; | |
01737f42 | 1185 | GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp); |
7e6c297e ILT |
1186 | } |
1187 | ||
1188 | SP += 32; | |
1189 | ||
192ae475 | 1190 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
da0bce9c | 1191 | { |
192ae475 AC |
1192 | if (aregs == 5) |
1193 | { | |
1194 | FGR[0] = WORD64LO (GPR[4]); | |
1195 | FPR_STATE[0] = fmt_uninterpreted; | |
1196 | } | |
1197 | else if (aregs == 6) | |
1198 | { | |
1199 | FGR[0] = WORD64LO (GPR[5]); | |
1200 | FGR[1] = WORD64LO (GPR[4]); | |
1201 | FPR_STATE[0] = fmt_uninterpreted; | |
1202 | FPR_STATE[1] = fmt_uninterpreted; | |
1203 | } | |
1204 | } | |
da0bce9c | 1205 | |
7e6c297e ILT |
1206 | PC = RA; |
1207 | } | |
192ae475 | 1208 | |
7e6c297e ILT |
1209 | } |
1210 | ||
8bae0a0c JSC |
1211 | /*-- trace support ----------------------------------------------------------*/ |
1212 | ||
1213 | /* The TRACE support is provided (if required) in the memory accessing | |
1214 | routines. Since we are also providing the architecture specific | |
1215 | features, the architecture simulation code can also deal with | |
1216 | notifying the TRACE world of cache flushes, etc. Similarly we do | |
1217 | not need to provide profiling support in the simulator engine, | |
1218 | since we can sample in the instruction fetch control loop. By | |
1219 | defining the TRACE manifest, we add tracing as a run-time | |
1220 | option. */ | |
1221 | ||
1222 | #if defined(TRACE) | |
1223 | /* Tracing by default produces "din" format (as required by | |
1224 | dineroIII). Each line of such a trace file *MUST* have a din label | |
1225 | and address field. The rest of the line is ignored, so comments can | |
1226 | be included if desired. The first field is the label which must be | |
1227 | one of the following values: | |
1228 | ||
1229 | 0 read data | |
1230 | 1 write data | |
1231 | 2 instruction fetch | |
1232 | 3 escape record (treated as unknown access type) | |
1233 | 4 escape record (causes cache flush) | |
1234 | ||
1235 | The address field is a 32bit (lower-case) hexadecimal address | |
1236 | value. The address should *NOT* be preceded by "0x". | |
1237 | ||
1238 | The size of the memory transfer is not important when dealing with | |
1239 | cache lines (as long as no more than a cache line can be | |
1240 | transferred in a single operation :-), however more information | |
1241 | could be given following the dineroIII requirement to allow more | |
1242 | complete memory and cache simulators to provide better | |
1243 | results. i.e. the University of Pisa has a cache simulator that can | |
1244 | also take bus size and speed as (variable) inputs to calculate | |
1245 | complete system performance (a much more useful ability when trying | |
1246 | to construct an end product, rather than a processor). They | |
1247 | currently have an ARM version of their tool called ChARM. */ | |
1248 | ||
e3d12c65 | 1249 | |
030843d7 | 1250 | void |
01737f42 AC |
1251 | dotrace (SIM_DESC sd, |
1252 | sim_cpu *cpu, | |
1253 | FILE *tracefh, | |
1254 | int type, | |
1255 | SIM_ADDR address, | |
1256 | int width, | |
1257 | char *comment,...) | |
8bae0a0c | 1258 | { |
0c2c5f61 | 1259 | if (STATE & simTRACE) { |
8bae0a0c | 1260 | va_list ap; |
53b9417e | 1261 | fprintf(tracefh,"%d %s ; width %d ; ", |
6429b296 | 1262 | type, |
53b9417e DE |
1263 | pr_addr(address), |
1264 | width); | |
8bae0a0c | 1265 | va_start(ap,comment); |
6429b296 | 1266 | vfprintf(tracefh,comment,ap); |
8bae0a0c JSC |
1267 | va_end(ap); |
1268 | fprintf(tracefh,"\n"); | |
1269 | } | |
1270 | /* NOTE: Since the "din" format will only accept 32bit addresses, and | |
1271 | we may be generating 64bit ones, we should put the hi-32bits of the | |
1272 | address into the comment field. */ | |
1273 | ||
1274 | /* TODO: Provide a buffer for the trace lines. We can then avoid | |
1275 | performing writes until the buffer is filled, or the file is | |
1276 | being closed. */ | |
1277 | ||
1278 | /* NOTE: We could consider adding a comment field to the "din" file | |
1279 | produced using type 3 markers (unknown access). This would then | |
1280 | allow information about the program that the "din" is for, and | |
1281 | the MIPs world that was being simulated, to be placed into the | |
1282 | trace file. */ | |
1283 | ||
1284 | return; | |
1285 | } | |
1286 | #endif /* TRACE */ | |
1287 | ||
1288 | /*---------------------------------------------------------------------------*/ | |
1289 | /*-- simulator engine -------------------------------------------------------*/ | |
1290 | /*---------------------------------------------------------------------------*/ | |
1291 | ||
1292 | static void | |
01737f42 | 1293 | ColdReset (SIM_DESC sd) |
8bae0a0c | 1294 | { |
01737f42 AC |
1295 | int cpu_nr; |
1296 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) | |
dad6f1f3 | 1297 | { |
01737f42 AC |
1298 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); |
1299 | /* RESET: Fixed PC address: */ | |
1300 | PC = UNSIGNED64 (0xFFFFFFFFBFC00000); | |
1301 | /* The reset vector address is in the unmapped, uncached memory space. */ | |
1302 | ||
1303 | SR &= ~(status_SR | status_TS | status_RP); | |
1304 | SR |= (status_ERL | status_BEV); | |
1305 | ||
1306 | /* Cheat and allow access to the complete register set immediately */ | |
1307 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT | |
1308 | && WITH_TARGET_WORD_BITSIZE == 64) | |
1309 | SR |= status_FR; /* 64bit registers */ | |
1310 | ||
1311 | /* Ensure that any instructions with pending register updates are | |
1312 | cleared: */ | |
2acd126a | 1313 | PENDING_INVALIDATE(); |
01737f42 AC |
1314 | |
1315 | /* Initialise the FPU registers to the unknown state */ | |
1316 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) | |
1317 | { | |
1318 | int rn; | |
1319 | for (rn = 0; (rn < 32); rn++) | |
1320 | FPR_STATE[rn] = fmt_uninterpreted; | |
1321 | } | |
1322 | ||
dad6f1f3 | 1323 | } |
8bae0a0c JSC |
1324 | } |
1325 | ||
dad6f1f3 AC |
1326 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual |
1327 | (revision 3.1) */ | |
8bae0a0c JSC |
1328 | /* Translate a virtual address to a physical address and cache |
1329 | coherence algorithm describing the mechanism used to resolve the | |
1330 | memory reference. Given the virtual address vAddr, and whether the | |
1331 | reference is to Instructions ot Data (IorD), find the corresponding | |
1332 | physical address (pAddr) and the cache coherence algorithm (CCA) | |
1333 | used to resolve the reference. If the virtual address is in one of | |
1334 | the unmapped address spaces the physical address and the CCA are | |
1335 | determined directly by the virtual address. If the virtual address | |
1336 | is in one of the mapped address spaces then the TLB is used to | |
1337 | determine the physical address and access type; if the required | |
1338 | translation is not present in the TLB or the desired access is not | |
1339 | permitted the function fails and an exception is taken. | |
1340 | ||
dad6f1f3 AC |
1341 | NOTE: Normally (RAW == 0), when address translation fails, this |
1342 | function raises an exception and does not return. */ | |
8bae0a0c | 1343 | |
18c64df6 | 1344 | int |
01737f42 AC |
1345 | address_translation (SIM_DESC sd, |
1346 | sim_cpu *cpu, | |
1347 | address_word cia, | |
1348 | address_word vAddr, | |
1349 | int IorD, | |
1350 | int LorS, | |
1351 | address_word *pAddr, | |
1352 | int *CCA, | |
1353 | int raw) | |
8bae0a0c JSC |
1354 | { |
1355 | int res = -1; /* TRUE : Assume good return */ | |
1356 | ||
1357 | #ifdef DEBUG | |
18c64df6 | 1358 | sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD")); |
8bae0a0c JSC |
1359 | #endif |
1360 | ||
1361 | /* Check that the address is valid for this memory model */ | |
1362 | ||
1363 | /* For a simple (flat) memory model, we simply pass virtual | |
1364 | addressess through (mostly) unchanged. */ | |
1365 | vAddr &= 0xFFFFFFFF; | |
a9f7253f | 1366 | |
8bae0a0c JSC |
1367 | *pAddr = vAddr; /* default for isTARGET */ |
1368 | *CCA = Uncached; /* not used for isHOST */ | |
1369 | ||
8bae0a0c JSC |
1370 | return(res); |
1371 | } | |
1372 | ||
63be8feb AC |
1373 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual |
1374 | (revision 3.1) */ | |
8bae0a0c JSC |
1375 | /* Prefetch data from memory. Prefetch is an advisory instruction for |
1376 | which an implementation specific action is taken. The action taken | |
1377 | may increase performance, but must not change the meaning of the | |
1378 | program, or alter architecturally-visible state. */ | |
50a2a691 | 1379 | |
ea985d24 | 1380 | void |
01737f42 AC |
1381 | prefetch (SIM_DESC sd, |
1382 | sim_cpu *cpu, | |
1383 | address_word cia, | |
1384 | int CCA, | |
1385 | address_word pAddr, | |
1386 | address_word vAddr, | |
1387 | int DATA, | |
1388 | int hint) | |
8bae0a0c JSC |
1389 | { |
1390 | #ifdef DEBUG | |
18c64df6 | 1391 | sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint); |
8bae0a0c JSC |
1392 | #endif /* DEBUG */ |
1393 | ||
1394 | /* For our simple memory model we do nothing */ | |
1395 | return; | |
1396 | } | |
1397 | ||
63be8feb AC |
1398 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual |
1399 | (revision 3.1) */ | |
8bae0a0c JSC |
1400 | /* Load a value from memory. Use the cache and main memory as |
1401 | specified in the Cache Coherence Algorithm (CCA) and the sort of | |
1402 | access (IorD) to find the contents of AccessLength memory bytes | |
1403 | starting at physical location pAddr. The data is returned in the | |
1404 | fixed width naturally-aligned memory element (MemElem). The | |
1405 | low-order two (or three) bits of the address and the AccessLength | |
1406 | indicate which of the bytes within MemElem needs to be given to the | |
1407 | processor. If the memory access type of the reference is uncached | |
1408 | then only the referenced bytes are read from memory and valid | |
1409 | within the memory element. If the access type is cached, and the | |
1410 | data is not present in cache, an implementation specific size and | |
1411 | alignment block of memory is read and loaded into the cache to | |
1412 | satisfy a load reference. At a minimum, the block is the entire | |
1413 | memory element. */ | |
18c64df6 | 1414 | void |
01737f42 AC |
1415 | load_memory (SIM_DESC sd, |
1416 | sim_cpu *cpu, | |
1417 | address_word cia, | |
1418 | uword64* memvalp, | |
1419 | uword64* memval1p, | |
1420 | int CCA, | |
1421 | int AccessLength, | |
1422 | address_word pAddr, | |
1423 | address_word vAddr, | |
1424 | int IorD) | |
8bae0a0c | 1425 | { |
50a2a691 AC |
1426 | uword64 value = 0; |
1427 | uword64 value1 = 0; | |
8bae0a0c JSC |
1428 | |
1429 | #ifdef DEBUG | |
63be8feb | 1430 | sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION")); |
8bae0a0c JSC |
1431 | #endif /* DEBUG */ |
1432 | ||
1433 | #if defined(WARN_MEM) | |
1434 | if (CCA != uncached) | |
63be8feb | 1435 | sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); |
8bae0a0c JSC |
1436 | #endif /* WARN_MEM */ |
1437 | ||
8bae0a0c JSC |
1438 | /* If instruction fetch then we need to check that the two lo-order |
1439 | bits are zero, otherwise raise a InstructionFetch exception: */ | |
6429b296 JW |
1440 | if ((IorD == isINSTRUCTION) |
1441 | && ((pAddr & 0x3) != 0) | |
1442 | && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0))) | |
63be8feb AC |
1443 | SignalExceptionInstructionFetch (); |
1444 | ||
1445 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
1446 | { | |
1447 | /* In reality this should be a Bus Error */ | |
1448 | sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n", | |
1449 | AccessLength, | |
1450 | (LOADDRMASK + 1) << 2, | |
1451 | pr_addr (pAddr)); | |
1452 | } | |
8bae0a0c | 1453 | |
8bae0a0c | 1454 | #if defined(TRACE) |
01737f42 | 1455 | dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); |
8bae0a0c | 1456 | #endif /* TRACE */ |
63be8feb AC |
1457 | |
1458 | /* Read the specified number of bytes from memory. Adjust for | |
1459 | host/target byte ordering/ Align the least significant byte | |
1460 | read. */ | |
8bae0a0c | 1461 | |
63be8feb AC |
1462 | switch (AccessLength) |
1463 | { | |
1464 | case AccessLength_QUADWORD : | |
1465 | { | |
01737f42 | 1466 | unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA, |
63be8feb AC |
1467 | sim_core_read_map, pAddr); |
1468 | value1 = VH8_16 (val); | |
1469 | value = VL8_16 (val); | |
1470 | break; | |
8bae0a0c | 1471 | } |
63be8feb | 1472 | case AccessLength_DOUBLEWORD : |
01737f42 | 1473 | value = sim_core_read_aligned_8 (cpu, NULL_CIA, |
63be8feb AC |
1474 | sim_core_read_map, pAddr); |
1475 | break; | |
1476 | case AccessLength_SEPTIBYTE : | |
01737f42 | 1477 | value = sim_core_read_misaligned_7 (cpu, NULL_CIA, |
63be8feb AC |
1478 | sim_core_read_map, pAddr); |
1479 | case AccessLength_SEXTIBYTE : | |
01737f42 | 1480 | value = sim_core_read_misaligned_6 (cpu, NULL_CIA, |
63be8feb AC |
1481 | sim_core_read_map, pAddr); |
1482 | case AccessLength_QUINTIBYTE : | |
01737f42 | 1483 | value = sim_core_read_misaligned_5 (cpu, NULL_CIA, |
63be8feb AC |
1484 | sim_core_read_map, pAddr); |
1485 | case AccessLength_WORD : | |
01737f42 | 1486 | value = sim_core_read_aligned_4 (cpu, NULL_CIA, |
63be8feb AC |
1487 | sim_core_read_map, pAddr); |
1488 | break; | |
1489 | case AccessLength_TRIPLEBYTE : | |
01737f42 | 1490 | value = sim_core_read_misaligned_3 (cpu, NULL_CIA, |
63be8feb AC |
1491 | sim_core_read_map, pAddr); |
1492 | case AccessLength_HALFWORD : | |
01737f42 | 1493 | value = sim_core_read_aligned_2 (cpu, NULL_CIA, |
63be8feb AC |
1494 | sim_core_read_map, pAddr); |
1495 | break; | |
1496 | case AccessLength_BYTE : | |
01737f42 | 1497 | value = sim_core_read_aligned_1 (cpu, NULL_CIA, |
63be8feb AC |
1498 | sim_core_read_map, pAddr); |
1499 | break; | |
1500 | default: | |
1501 | abort (); | |
1502 | } | |
1503 | ||
8bae0a0c | 1504 | #ifdef DEBUG |
63be8feb AC |
1505 | printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n", |
1506 | (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value)); | |
8bae0a0c | 1507 | #endif /* DEBUG */ |
63be8feb AC |
1508 | |
1509 | /* See also store_memory. */ | |
1510 | if (AccessLength <= AccessLength_DOUBLEWORD) | |
1511 | { | |
1512 | if (BigEndianMem) | |
1513 | /* for big endian target, byte (pAddr&LOADDRMASK == 0) is | |
1514 | shifted to the most significant byte position. */ | |
1515 | value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
1516 | else | |
1517 | /* For little endian target, byte (pAddr&LOADDRMASK == 0) | |
1518 | is already in the correct postition. */ | |
1519 | value <<= ((pAddr & LOADDRMASK) * 8); | |
1520 | } | |
1521 | ||
8bae0a0c | 1522 | #ifdef DEBUG |
63be8feb AC |
1523 | printf("DBG: LoadMemory() : shifted value = 0x%s%s\n", |
1524 | pr_uword64(value1),pr_uword64(value)); | |
e871dd18 | 1525 | #endif /* DEBUG */ |
63be8feb | 1526 | |
525d929e AC |
1527 | *memvalp = value; |
1528 | if (memval1p) *memval1p = value1; | |
8bae0a0c JSC |
1529 | } |
1530 | ||
53b9417e | 1531 | |
50a2a691 AC |
1532 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual |
1533 | (revision 3.1) */ | |
8bae0a0c JSC |
1534 | /* Store a value to memory. The specified data is stored into the |
1535 | physical location pAddr using the memory hierarchy (data caches and | |
1536 | main memory) as specified by the Cache Coherence Algorithm | |
1537 | (CCA). The MemElem contains the data for an aligned, fixed-width | |
1538 | memory element (word for 32-bit processors, doubleword for 64-bit | |
1539 | processors), though only the bytes that will actually be stored to | |
1540 | memory need to be valid. The low-order two (or three) bits of pAddr | |
1541 | and the AccessLength field indicates which of the bytes within the | |
1542 | MemElem data should actually be stored; only these bytes in memory | |
1543 | will be changed. */ | |
53b9417e | 1544 | |
18c64df6 | 1545 | void |
01737f42 AC |
1546 | store_memory (SIM_DESC sd, |
1547 | sim_cpu *cpu, | |
1548 | address_word cia, | |
1549 | int CCA, | |
1550 | int AccessLength, | |
1551 | uword64 MemElem, | |
1552 | uword64 MemElem1, /* High order 64 bits */ | |
1553 | address_word pAddr, | |
1554 | address_word vAddr) | |
8bae0a0c JSC |
1555 | { |
1556 | #ifdef DEBUG | |
63be8feb | 1557 | sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr)); |
8bae0a0c | 1558 | #endif /* DEBUG */ |
63be8feb | 1559 | |
8bae0a0c JSC |
1560 | #if defined(WARN_MEM) |
1561 | if (CCA != uncached) | |
63be8feb | 1562 | sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); |
8bae0a0c | 1563 | #endif /* WARN_MEM */ |
63be8feb AC |
1564 | |
1565 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
1566 | sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr)); | |
1567 | ||
8bae0a0c | 1568 | #if defined(TRACE) |
01737f42 | 1569 | dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store"); |
8bae0a0c | 1570 | #endif /* TRACE */ |
63be8feb | 1571 | |
8bae0a0c | 1572 | #ifdef DEBUG |
63be8feb | 1573 | printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c | 1574 | #endif /* DEBUG */ |
63be8feb AC |
1575 | |
1576 | /* See also load_memory */ | |
1577 | if (AccessLength <= AccessLength_DOUBLEWORD) | |
1578 | { | |
1579 | if (BigEndianMem) | |
1580 | /* for big endian target, byte (pAddr&LOADDRMASK == 0) is | |
1581 | shifted to the most significant byte position. */ | |
1582 | MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
1583 | else | |
1584 | /* For little endian target, byte (pAddr&LOADDRMASK == 0) | |
1585 | is already in the correct postition. */ | |
1586 | MemElem >>= ((pAddr & LOADDRMASK) * 8); | |
1587 | } | |
1588 | ||
8bae0a0c | 1589 | #ifdef DEBUG |
63be8feb | 1590 | printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c | 1591 | #endif /* DEBUG */ |
63be8feb AC |
1592 | |
1593 | switch (AccessLength) | |
1594 | { | |
1595 | case AccessLength_QUADWORD : | |
1596 | { | |
1597 | unsigned_16 val = U16_8 (MemElem1, MemElem); | |
01737f42 | 1598 | sim_core_write_aligned_16 (cpu, NULL_CIA, |
63be8feb AC |
1599 | sim_core_write_map, pAddr, val); |
1600 | break; | |
8bae0a0c | 1601 | } |
63be8feb | 1602 | case AccessLength_DOUBLEWORD : |
01737f42 | 1603 | sim_core_write_aligned_8 (cpu, NULL_CIA, |
63be8feb AC |
1604 | sim_core_write_map, pAddr, MemElem); |
1605 | break; | |
1606 | case AccessLength_SEPTIBYTE : | |
01737f42 | 1607 | sim_core_write_misaligned_7 (cpu, NULL_CIA, |
63be8feb AC |
1608 | sim_core_write_map, pAddr, MemElem); |
1609 | break; | |
1610 | case AccessLength_SEXTIBYTE : | |
01737f42 | 1611 | sim_core_write_misaligned_6 (cpu, NULL_CIA, |
63be8feb AC |
1612 | sim_core_write_map, pAddr, MemElem); |
1613 | break; | |
1614 | case AccessLength_QUINTIBYTE : | |
01737f42 | 1615 | sim_core_write_misaligned_5 (cpu, NULL_CIA, |
63be8feb AC |
1616 | sim_core_write_map, pAddr, MemElem); |
1617 | break; | |
1618 | case AccessLength_WORD : | |
01737f42 | 1619 | sim_core_write_aligned_4 (cpu, NULL_CIA, |
63be8feb AC |
1620 | sim_core_write_map, pAddr, MemElem); |
1621 | break; | |
1622 | case AccessLength_TRIPLEBYTE : | |
01737f42 | 1623 | sim_core_write_misaligned_3 (cpu, NULL_CIA, |
63be8feb AC |
1624 | sim_core_write_map, pAddr, MemElem); |
1625 | break; | |
1626 | case AccessLength_HALFWORD : | |
01737f42 | 1627 | sim_core_write_aligned_2 (cpu, NULL_CIA, |
63be8feb AC |
1628 | sim_core_write_map, pAddr, MemElem); |
1629 | break; | |
1630 | case AccessLength_BYTE : | |
01737f42 | 1631 | sim_core_write_aligned_1 (cpu, NULL_CIA, |
63be8feb AC |
1632 | sim_core_write_map, pAddr, MemElem); |
1633 | break; | |
1634 | default: | |
1635 | abort (); | |
1636 | } | |
1637 | ||
8bae0a0c JSC |
1638 | return; |
1639 | } | |
1640 | ||
53b9417e | 1641 | |
dad6f1f3 | 1642 | unsigned32 |
7ce8b917 | 1643 | ifetch32 (SIM_DESC sd, |
01737f42 | 1644 | sim_cpu *cpu, |
7ce8b917 AC |
1645 | address_word cia, |
1646 | address_word vaddr) | |
dad6f1f3 AC |
1647 | { |
1648 | /* Copy the action of the LW instruction */ | |
1649 | address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
1650 | address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
1651 | unsigned64 value; | |
1652 | address_word paddr; | |
1653 | unsigned32 instruction; | |
1654 | unsigned byte; | |
1655 | int cca; | |
1656 | AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL); | |
1657 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
37379a25 AC |
1658 | LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL); |
1659 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); | |
1660 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
1661 | return instruction; | |
1662 | } | |
1663 | ||
1664 | ||
1665 | unsigned16 | |
1666 | ifetch16 (SIM_DESC sd, | |
1667 | sim_cpu *cpu, | |
1668 | address_word cia, | |
1669 | address_word vaddr) | |
1670 | { | |
1671 | /* Copy the action of the LW instruction */ | |
1672 | address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
1673 | address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
1674 | unsigned64 value; | |
1675 | address_word paddr; | |
1676 | unsigned16 instruction; | |
1677 | unsigned byte; | |
1678 | int cca; | |
1679 | AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL); | |
1680 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
dad6f1f3 AC |
1681 | LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL); |
1682 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); | |
1683 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
1684 | return instruction; | |
1685 | } | |
1686 | ||
1687 | ||
8bae0a0c JSC |
1688 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ |
1689 | /* Order loads and stores to synchronise shared memory. Perform the | |
1690 | action necessary to make the effects of groups of synchronizable | |
1691 | loads and stores indicated by stype occur in the same order for all | |
1692 | processors. */ | |
ea985d24 | 1693 | void |
01737f42 AC |
1694 | sync_operation (SIM_DESC sd, |
1695 | sim_cpu *cpu, | |
1696 | address_word cia, | |
1697 | int stype) | |
8bae0a0c JSC |
1698 | { |
1699 | #ifdef DEBUG | |
18c64df6 | 1700 | sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype); |
8bae0a0c JSC |
1701 | #endif /* DEBUG */ |
1702 | return; | |
1703 | } | |
1704 | ||
1705 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1706 | /* Signal an exception condition. This will result in an exception | |
1707 | that aborts the instruction. The instruction operation pseudocode | |
50a2a691 | 1708 | will never see a return from this function call. */ |
2e61a3ad | 1709 | |
18c64df6 | 1710 | void |
7ce8b917 | 1711 | signal_exception (SIM_DESC sd, |
01737f42 | 1712 | sim_cpu *cpu, |
7ce8b917 AC |
1713 | address_word cia, |
1714 | int exception,...) | |
8bae0a0c | 1715 | { |
56e7c849 | 1716 | int vector; |
6eedf3f4 MA |
1717 | |
1718 | #ifdef DEBUG | |
95469ceb | 1719 | sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); |
6eedf3f4 MA |
1720 | #endif /* DEBUG */ |
1721 | ||
8bae0a0c JSC |
1722 | /* Ensure that any active atomic read/modify/write operation will fail: */ |
1723 | LLBIT = 0; | |
1724 | ||
1725 | switch (exception) { | |
1726 | /* TODO: For testing purposes I have been ignoring TRAPs. In | |
1727 | reality we should either simulate them, or allow the user to | |
6eedf3f4 MA |
1728 | ignore them at run-time. |
1729 | Same for SYSCALL */ | |
8bae0a0c | 1730 | case Trap : |
95469ceb | 1731 | sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia)); |
8bae0a0c JSC |
1732 | break; |
1733 | ||
6eedf3f4 MA |
1734 | case SystemCall : |
1735 | { | |
1736 | va_list ap; | |
1737 | unsigned int instruction; | |
1738 | unsigned int code; | |
1739 | ||
1740 | va_start(ap,exception); | |
1741 | instruction = va_arg(ap,unsigned int); | |
1742 | va_end(ap); | |
1743 | ||
1744 | code = (instruction >> 6) & 0xFFFFF; | |
1745 | ||
18c64df6 | 1746 | sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n", |
95469ceb | 1747 | code, pr_addr(cia)); |
6eedf3f4 MA |
1748 | } |
1749 | break; | |
1750 | ||
1751 | case DebugBreakPoint : | |
1752 | if (! (Debug & Debug_DM)) | |
1753 | { | |
1754 | if (INDELAYSLOT()) | |
1755 | { | |
1756 | CANCELDELAYSLOT(); | |
1757 | ||
1758 | Debug |= Debug_DBD; /* signaled from within in delay slot */ | |
95469ceb | 1759 | DEPC = cia - 4; /* reference the branch instruction */ |
6eedf3f4 MA |
1760 | } |
1761 | else | |
1762 | { | |
1763 | Debug &= ~Debug_DBD; /* not signaled from within a delay slot */ | |
95469ceb | 1764 | DEPC = cia; |
6eedf3f4 MA |
1765 | } |
1766 | ||
1767 | Debug |= Debug_DM; /* in debugging mode */ | |
1768 | Debug |= Debug_DBp; /* raising a DBp exception */ | |
1769 | PC = 0xBFC00200; | |
01737f42 | 1770 | sim_engine_restart (SD, CPU, NULL, NULL_CIA); |
6eedf3f4 MA |
1771 | } |
1772 | break; | |
1773 | ||
8bae0a0c JSC |
1774 | case ReservedInstruction : |
1775 | { | |
1776 | va_list ap; | |
1777 | unsigned int instruction; | |
1778 | va_start(ap,exception); | |
1779 | instruction = va_arg(ap,unsigned int); | |
1780 | va_end(ap); | |
1781 | /* Provide simple monitor support using ReservedInstruction | |
1782 | exceptions. The following code simulates the fixed vector | |
1783 | entry points into the IDT monitor by causing a simulator | |
1784 | trap, performing the monitor operation, and returning to | |
1785 | the address held in the $ra register (standard PCS return | |
1786 | address). This means we only need to pre-load the vector | |
1787 | space with suitable instruction values. For systems were | |
1788 | actual trap instructions are used, we would not need to | |
1789 | perform this magic. */ | |
7ce8b917 AC |
1790 | if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION) |
1791 | { | |
01737f42 | 1792 | sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) ); |
7ce8b917 AC |
1793 | /* NOTE: This assumes that a branch-and-link style |
1794 | instruction was used to enter the vector (which is the | |
1795 | case with the current IDT monitor). */ | |
01737f42 | 1796 | sim_engine_restart (SD, CPU, NULL, RA); |
7ce8b917 | 1797 | } |
7e6c297e ILT |
1798 | /* Look for the mips16 entry and exit instructions, and |
1799 | simulate a handler for them. */ | |
95469ceb | 1800 | else if ((cia & 1) != 0 |
7e6c297e | 1801 | && (instruction & 0xf81f) == 0xe809 |
7ce8b917 AC |
1802 | && (instruction & 0x0c0) != 0x0c0) |
1803 | { | |
01737f42 | 1804 | mips16_entry (SD, CPU, cia, instruction); |
7ce8b917 AC |
1805 | sim_engine_restart (sd, NULL, NULL, NULL_CIA); |
1806 | } | |
1807 | /* else fall through to normal exception processing */ | |
95469ceb | 1808 | sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia)); |
8bae0a0c JSC |
1809 | } |
1810 | ||
05d1322f | 1811 | case BreakPoint: |
e3d12c65 | 1812 | #ifdef DEBUG |
95469ceb | 1813 | sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); |
8bae0a0c | 1814 | #endif /* DEBUG */ |
05d1322f JL |
1815 | /* Keep a copy of the current A0 in-case this is the program exit |
1816 | breakpoint: */ | |
1817 | { | |
1818 | va_list ap; | |
1819 | unsigned int instruction; | |
1820 | va_start(ap,exception); | |
1821 | instruction = va_arg(ap,unsigned int); | |
1822 | va_end(ap); | |
1823 | /* Check for our special terminating BREAK: */ | |
1824 | if ((instruction & 0x03FFFFC0) == 0x03ff0000) { | |
01737f42 | 1825 | sim_engine_halt (SD, CPU, NULL, cia, |
05d1322f JL |
1826 | sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); |
1827 | } | |
1828 | } | |
0c2c5f61 | 1829 | if (STATE & simDELAYSLOT) |
95469ceb | 1830 | PC = cia - 4; /* reference the branch instruction */ |
05d1322f | 1831 | else |
95469ceb | 1832 | PC = cia; |
01737f42 | 1833 | sim_engine_halt (SD, CPU, NULL, cia, |
232156de | 1834 | sim_stopped, SIM_SIGTRAP); |
05d1322f JL |
1835 | |
1836 | default: | |
8bae0a0c JSC |
1837 | /* Store exception code into current exception id variable (used |
1838 | by exit code): */ | |
1839 | ||
1840 | /* TODO: If not simulating exceptions then stop the simulator | |
1841 | execution. At the moment we always stop the simulation. */ | |
e3d12c65 | 1842 | |
56e7c849 AC |
1843 | /* See figure 5-17 for an outline of the code below */ |
1844 | if (! (SR & status_EXL)) | |
1845 | { | |
1846 | CAUSE = (exception << 2); | |
0c2c5f61 | 1847 | if (STATE & simDELAYSLOT) |
56e7c849 | 1848 | { |
0c2c5f61 | 1849 | STATE &= ~simDELAYSLOT; |
56e7c849 | 1850 | CAUSE |= cause_BD; |
95469ceb | 1851 | EPC = (cia - 4); /* reference the branch instruction */ |
56e7c849 AC |
1852 | } |
1853 | else | |
95469ceb | 1854 | EPC = cia; |
56e7c849 AC |
1855 | /* FIXME: TLB et.al. */ |
1856 | vector = 0x180; | |
1857 | } | |
1858 | else | |
1859 | { | |
05d1322f | 1860 | CAUSE = (exception << 2); |
56e7c849 AC |
1861 | vector = 0x180; |
1862 | } | |
1863 | SR |= status_EXL; | |
e3d12c65 DE |
1864 | /* Store exception code into current exception id variable (used |
1865 | by exit code): */ | |
56e7c849 AC |
1866 | if (SR & status_BEV) |
1867 | PC = (signed)0xBFC00200 + 0x180; | |
1868 | else | |
1869 | PC = (signed)0x80000000 + 0x180; | |
1870 | ||
50a2a691 AC |
1871 | switch ((CAUSE >> 2) & 0x1F) |
1872 | { | |
1873 | case Interrupt: | |
56e7c849 AC |
1874 | /* Interrupts arrive during event processing, no need to |
1875 | restart */ | |
1876 | return; | |
50a2a691 AC |
1877 | |
1878 | case TLBModification: | |
1879 | case TLBLoad: | |
1880 | case TLBStore: | |
1881 | case AddressLoad: | |
1882 | case AddressStore: | |
1883 | case InstructionFetch: | |
1884 | case DataReference: | |
56e7c849 AC |
1885 | /* The following is so that the simulator will continue from the |
1886 | exception address on breakpoint operations. */ | |
1887 | PC = EPC; | |
01737f42 | 1888 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1889 | sim_stopped, SIM_SIGBUS); |
50a2a691 AC |
1890 | |
1891 | case ReservedInstruction: | |
1892 | case CoProcessorUnusable: | |
56e7c849 | 1893 | PC = EPC; |
01737f42 | 1894 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1895 | sim_stopped, SIM_SIGILL); |
50a2a691 AC |
1896 | |
1897 | case IntegerOverflow: | |
1898 | case FPE: | |
01737f42 | 1899 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1900 | sim_stopped, SIM_SIGFPE); |
50a2a691 AC |
1901 | |
1902 | case Trap: | |
1903 | case Watch: | |
1904 | case SystemCall: | |
56e7c849 | 1905 | PC = EPC; |
01737f42 | 1906 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1907 | sim_stopped, SIM_SIGTRAP); |
50a2a691 | 1908 | |
05d1322f JL |
1909 | case BreakPoint: |
1910 | PC = EPC; | |
01737f42 | 1911 | sim_engine_abort (SD, CPU, NULL_CIA, |
05d1322f JL |
1912 | "FATAL: Should not encounter a breakpoint\n"); |
1913 | ||
50a2a691 | 1914 | default : /* Unknown internal exception */ |
56e7c849 | 1915 | PC = EPC; |
01737f42 | 1916 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1917 | sim_stopped, SIM_SIGABRT); |
50a2a691 AC |
1918 | |
1919 | } | |
8bae0a0c JSC |
1920 | |
1921 | case SimulatorFault: | |
1922 | { | |
1923 | va_list ap; | |
1924 | char *msg; | |
1925 | va_start(ap,exception); | |
1926 | msg = va_arg(ap,char *); | |
50a2a691 | 1927 | va_end(ap); |
01737f42 | 1928 | sim_engine_abort (SD, CPU, NULL_CIA, |
2e61a3ad | 1929 | "FATAL: Simulator error \"%s\"\n",msg); |
8bae0a0c | 1930 | } |
8bae0a0c JSC |
1931 | } |
1932 | ||
1933 | return; | |
1934 | } | |
1935 | ||
1936 | #if defined(WARN_RESULT) | |
1937 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1938 | /* This function indicates that the result of the operation is | |
1939 | undefined. However, this should not affect the instruction | |
1940 | stream. All that is meant to happen is that the destination | |
1941 | register is set to an undefined result. To keep the simulator | |
1942 | simple, we just don't bother updating the destination register, so | |
1943 | the overall result will be undefined. If desired we can stop the | |
1944 | simulator by raising a pseudo-exception. */ | |
95469ceb | 1945 | #define UndefinedResult() undefined_result (sd,cia) |
8bae0a0c | 1946 | static void |
95469ceb AC |
1947 | undefined_result(sd,cia) |
1948 | SIM_DESC sd; | |
1949 | address_word cia; | |
8bae0a0c | 1950 | { |
95469ceb | 1951 | sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia)); |
8bae0a0c JSC |
1952 | #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */ |
1953 | state |= simSTOP; | |
1954 | #endif | |
1955 | return; | |
1956 | } | |
1957 | #endif /* WARN_RESULT */ | |
1958 | ||
18c64df6 | 1959 | void |
01737f42 AC |
1960 | cache_op (SIM_DESC sd, |
1961 | sim_cpu *cpu, | |
1962 | address_word cia, | |
1963 | int op, | |
1964 | address_word pAddr, | |
1965 | address_word vAddr, | |
1966 | unsigned int instruction) | |
8bae0a0c | 1967 | { |
f24b7b69 JSC |
1968 | #if 1 /* stop warning message being displayed (we should really just remove the code) */ |
1969 | static int icache_warning = 1; | |
1970 | static int dcache_warning = 1; | |
1971 | #else | |
a9f7253f JSC |
1972 | static int icache_warning = 0; |
1973 | static int dcache_warning = 0; | |
f24b7b69 | 1974 | #endif |
a9f7253f | 1975 | |
8bae0a0c JSC |
1976 | /* If CP0 is not useable (User or Supervisor mode) and the CP0 |
1977 | enable bit in the Status Register is clear - a coprocessor | |
1978 | unusable exception is taken. */ | |
a9f7253f | 1979 | #if 0 |
95469ceb | 1980 | sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia)); |
a9f7253f | 1981 | #endif |
8bae0a0c JSC |
1982 | |
1983 | switch (op & 0x3) { | |
1984 | case 0: /* instruction cache */ | |
1985 | switch (op >> 2) { | |
1986 | case 0: /* Index Invalidate */ | |
1987 | case 1: /* Index Load Tag */ | |
1988 | case 2: /* Index Store Tag */ | |
1989 | case 4: /* Hit Invalidate */ | |
1990 | case 5: /* Fill */ | |
1991 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
1992 | if (!icache_warning) |
1993 | { | |
18c64df6 | 1994 | sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2)); |
a9f7253f JSC |
1995 | icache_warning = 1; |
1996 | } | |
8bae0a0c JSC |
1997 | break; |
1998 | ||
1999 | default: | |
2000 | SignalException(ReservedInstruction,instruction); | |
2001 | break; | |
2002 | } | |
2003 | break; | |
2004 | ||
2005 | case 1: /* data cache */ | |
2006 | switch (op >> 2) { | |
2007 | case 0: /* Index Writeback Invalidate */ | |
2008 | case 1: /* Index Load Tag */ | |
2009 | case 2: /* Index Store Tag */ | |
2010 | case 3: /* Create Dirty */ | |
2011 | case 4: /* Hit Invalidate */ | |
2012 | case 5: /* Hit Writeback Invalidate */ | |
2013 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
2014 | if (!dcache_warning) |
2015 | { | |
18c64df6 | 2016 | sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2)); |
a9f7253f JSC |
2017 | dcache_warning = 1; |
2018 | } | |
8bae0a0c JSC |
2019 | break; |
2020 | ||
2021 | default: | |
2022 | SignalException(ReservedInstruction,instruction); | |
2023 | break; | |
2024 | } | |
2025 | break; | |
2026 | ||
2027 | default: /* unrecognised cache ID */ | |
2028 | SignalException(ReservedInstruction,instruction); | |
2029 | break; | |
2030 | } | |
2031 | ||
2032 | return; | |
2033 | } | |
2034 | ||
2035 | /*-- FPU support routines ---------------------------------------------------*/ | |
2036 | ||
8bae0a0c JSC |
2037 | /* Numbers are held in normalized form. The SINGLE and DOUBLE binary |
2038 | formats conform to ANSI/IEEE Std 754-1985. */ | |
2039 | /* SINGLE precision floating: | |
2040 | * seeeeeeeefffffffffffffffffffffff | |
2041 | * s = 1bit = sign | |
2042 | * e = 8bits = exponent | |
2043 | * f = 23bits = fraction | |
2044 | */ | |
2045 | /* SINGLE precision fixed: | |
2046 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
2047 | * s = 1bit = sign | |
2048 | * i = 31bits = integer | |
2049 | */ | |
2050 | /* DOUBLE precision floating: | |
2051 | * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff | |
2052 | * s = 1bit = sign | |
2053 | * e = 11bits = exponent | |
2054 | * f = 52bits = fraction | |
2055 | */ | |
2056 | /* DOUBLE precision fixed: | |
2057 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
2058 | * s = 1bit = sign | |
2059 | * i = 63bits = integer | |
2060 | */ | |
2061 | ||
2062 | /* Extract sign-bit: */ | |
2063 | #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0) | |
e871dd18 | 2064 | #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0) |
8bae0a0c JSC |
2065 | /* Extract biased exponent: */ |
2066 | #define FP_S_be(v) (((v) >> 23) & 0xFF) | |
2067 | #define FP_D_be(v) (((v) >> 52) & 0x7FF) | |
2068 | /* Extract unbiased Exponent: */ | |
2069 | #define FP_S_e(v) (FP_S_be(v) - 0x7F) | |
2070 | #define FP_D_e(v) (FP_D_be(v) - 0x3FF) | |
2071 | /* Extract complete fraction field: */ | |
2072 | #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23)) | |
e871dd18 | 2073 | #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52)) |
8bae0a0c JSC |
2074 | /* Extract numbered fraction bit: */ |
2075 | #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0) | |
2076 | #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0) | |
2077 | ||
2078 | /* Explicit QNaN values used when value required: */ | |
2079 | #define FPQNaN_SINGLE (0x7FBFFFFF) | |
2080 | #define FPQNaN_WORD (0x7FFFFFFF) | |
e871dd18 JSC |
2081 | #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF) |
2082 | #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF) | |
8bae0a0c JSC |
2083 | |
2084 | /* Explicit Infinity values used when required: */ | |
2085 | #define FPINF_SINGLE (0x7F800000) | |
e871dd18 | 2086 | #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000) |
8bae0a0c JSC |
2087 | |
2088 | #if 1 /* def DEBUG */ | |
2089 | #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor"))) | |
2090 | #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>")))))) | |
2091 | #endif /* DEBUG */ | |
2092 | ||
18c64df6 | 2093 | uword64 |
01737f42 AC |
2094 | value_fpr (SIM_DESC sd, |
2095 | sim_cpu *cpu, | |
2096 | address_word cia, | |
2097 | int fpr, | |
2098 | FP_formats fmt) | |
8bae0a0c | 2099 | { |
50a2a691 | 2100 | uword64 value = 0; |
8bae0a0c JSC |
2101 | int err = 0; |
2102 | ||
2103 | /* Treat unused register values, as fixed-point 64bit values: */ | |
2104 | if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown)) | |
2105 | #if 1 | |
2106 | /* If request to read data as "uninterpreted", then use the current | |
2107 | encoding: */ | |
0c2c5f61 | 2108 | fmt = FPR_STATE[fpr]; |
8bae0a0c JSC |
2109 | #else |
2110 | fmt = fmt_long; | |
2111 | #endif | |
2112 | ||
2113 | /* For values not yet accessed, set to the desired format: */ | |
0c2c5f61 AC |
2114 | if (FPR_STATE[fpr] == fmt_uninterpreted) { |
2115 | FPR_STATE[fpr] = fmt; | |
8bae0a0c JSC |
2116 | #ifdef DEBUG |
2117 | printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt)); | |
2118 | #endif /* DEBUG */ | |
2119 | } | |
0c2c5f61 | 2120 | if (fmt != FPR_STATE[fpr]) { |
95469ceb | 2121 | sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia)); |
0c2c5f61 | 2122 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2123 | } |
2124 | ||
0c2c5f61 | 2125 | if (FPR_STATE[fpr] == fmt_unknown) { |
8bae0a0c JSC |
2126 | /* Set QNaN value: */ |
2127 | switch (fmt) { | |
2128 | case fmt_single: | |
2129 | value = FPQNaN_SINGLE; | |
2130 | break; | |
2131 | ||
2132 | case fmt_double: | |
2133 | value = FPQNaN_DOUBLE; | |
2134 | break; | |
2135 | ||
2136 | case fmt_word: | |
2137 | value = FPQNaN_WORD; | |
2138 | break; | |
2139 | ||
2140 | case fmt_long: | |
2141 | value = FPQNaN_LONG; | |
2142 | break; | |
2143 | ||
2144 | default: | |
2145 | err = -1; | |
2146 | break; | |
2147 | } | |
2148 | } else if (SizeFGR() == 64) { | |
2149 | switch (fmt) { | |
2150 | case fmt_single: | |
2151 | case fmt_word: | |
2152 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2153 | break; | |
2154 | ||
2155 | case fmt_uninterpreted: | |
2156 | case fmt_double: | |
2157 | case fmt_long: | |
2158 | value = FGR[fpr]; | |
2159 | break; | |
2160 | ||
2161 | default : | |
2162 | err = -1; | |
2163 | break; | |
2164 | } | |
da0bce9c | 2165 | } else { |
8bae0a0c JSC |
2166 | switch (fmt) { |
2167 | case fmt_single: | |
2168 | case fmt_word: | |
2169 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2170 | break; | |
2171 | ||
2172 | case fmt_uninterpreted: | |
2173 | case fmt_double: | |
2174 | case fmt_long: | |
da0bce9c ILT |
2175 | if ((fpr & 1) == 0) { /* even registers only */ |
2176 | value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF)); | |
2177 | } else { | |
18c64df6 | 2178 | SignalException(ReservedInstruction,0); |
da0bce9c | 2179 | } |
8bae0a0c JSC |
2180 | break; |
2181 | ||
2182 | default : | |
2183 | err = -1; | |
2184 | break; | |
2185 | } | |
2186 | } | |
2187 | ||
2188 | if (err) | |
18c64df6 | 2189 | SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()"); |
8bae0a0c JSC |
2190 | |
2191 | #ifdef DEBUG | |
95469ceb | 2192 | printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR()); |
8bae0a0c JSC |
2193 | #endif /* DEBUG */ |
2194 | ||
2195 | return(value); | |
2196 | } | |
2197 | ||
18c64df6 | 2198 | void |
01737f42 AC |
2199 | store_fpr (SIM_DESC sd, |
2200 | sim_cpu *cpu, | |
2201 | address_word cia, | |
2202 | int fpr, | |
2203 | FP_formats fmt, | |
2204 | uword64 value) | |
8bae0a0c JSC |
2205 | { |
2206 | int err = 0; | |
2207 | ||
2208 | #ifdef DEBUG | |
95469ceb | 2209 | printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR()); |
8bae0a0c JSC |
2210 | #endif /* DEBUG */ |
2211 | ||
2212 | if (SizeFGR() == 64) { | |
2213 | switch (fmt) { | |
a09a30d2 AC |
2214 | case fmt_uninterpreted_32: |
2215 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2216 | case fmt_single : |
2217 | case fmt_word : | |
e871dd18 | 2218 | FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF)); |
0c2c5f61 | 2219 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2220 | break; |
2221 | ||
a09a30d2 AC |
2222 | case fmt_uninterpreted_64: |
2223 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2224 | case fmt_uninterpreted: |
2225 | case fmt_double : | |
2226 | case fmt_long : | |
2227 | FGR[fpr] = value; | |
0c2c5f61 | 2228 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2229 | break; |
2230 | ||
2231 | default : | |
0c2c5f61 | 2232 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2233 | err = -1; |
2234 | break; | |
2235 | } | |
da0bce9c | 2236 | } else { |
8bae0a0c | 2237 | switch (fmt) { |
a09a30d2 AC |
2238 | case fmt_uninterpreted_32: |
2239 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2240 | case fmt_single : |
2241 | case fmt_word : | |
8bae0a0c | 2242 | FGR[fpr] = (value & 0xFFFFFFFF); |
0c2c5f61 | 2243 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2244 | break; |
2245 | ||
a09a30d2 AC |
2246 | case fmt_uninterpreted_64: |
2247 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2248 | case fmt_uninterpreted: |
2249 | case fmt_double : | |
2250 | case fmt_long : | |
da0bce9c ILT |
2251 | if ((fpr & 1) == 0) { /* even register number only */ |
2252 | FGR[fpr+1] = (value >> 32); | |
2253 | FGR[fpr] = (value & 0xFFFFFFFF); | |
0c2c5f61 AC |
2254 | FPR_STATE[fpr + 1] = fmt; |
2255 | FPR_STATE[fpr] = fmt; | |
da0bce9c | 2256 | } else { |
0c2c5f61 AC |
2257 | FPR_STATE[fpr] = fmt_unknown; |
2258 | FPR_STATE[fpr + 1] = fmt_unknown; | |
18c64df6 | 2259 | SignalException(ReservedInstruction,0); |
da0bce9c | 2260 | } |
8bae0a0c JSC |
2261 | break; |
2262 | ||
2263 | default : | |
0c2c5f61 | 2264 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2265 | err = -1; |
2266 | break; | |
2267 | } | |
e871dd18 JSC |
2268 | } |
2269 | #if defined(WARN_RESULT) | |
2270 | else | |
2271 | UndefinedResult(); | |
2272 | #endif /* WARN_RESULT */ | |
8bae0a0c JSC |
2273 | |
2274 | if (err) | |
18c64df6 | 2275 | SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()"); |
8bae0a0c JSC |
2276 | |
2277 | #ifdef DEBUG | |
53b9417e | 2278 | printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt)); |
8bae0a0c JSC |
2279 | #endif /* DEBUG */ |
2280 | ||
2281 | return; | |
2282 | } | |
2283 | ||
18c64df6 | 2284 | int |
8bae0a0c | 2285 | NaN(op,fmt) |
e871dd18 | 2286 | uword64 op; |
8bae0a0c JSC |
2287 | FP_formats fmt; |
2288 | { | |
2289 | int boolean = 0; | |
8bae0a0c JSC |
2290 | switch (fmt) { |
2291 | case fmt_single: | |
8bae0a0c | 2292 | case fmt_word: |
76ef4165 FL |
2293 | { |
2294 | sim_fpu wop; | |
2295 | sim_fpu_32to (&wop, op); | |
2296 | boolean = sim_fpu_is_nan (&wop); | |
2297 | break; | |
2298 | } | |
2299 | case fmt_double: | |
8bae0a0c | 2300 | case fmt_long: |
76ef4165 FL |
2301 | { |
2302 | sim_fpu wop; | |
2303 | sim_fpu_64to (&wop, op); | |
2304 | boolean = sim_fpu_is_nan (&wop); | |
2305 | break; | |
2306 | } | |
50a2a691 AC |
2307 | default: |
2308 | fprintf (stderr, "Bad switch\n"); | |
2309 | abort (); | |
8bae0a0c JSC |
2310 | } |
2311 | ||
2312 | #ifdef DEBUG | |
53b9417e | 2313 | printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2314 | #endif /* DEBUG */ |
2315 | ||
2316 | return(boolean); | |
2317 | } | |
2318 | ||
18c64df6 | 2319 | int |
8bae0a0c | 2320 | Infinity(op,fmt) |
e871dd18 | 2321 | uword64 op; |
8bae0a0c JSC |
2322 | FP_formats fmt; |
2323 | { | |
2324 | int boolean = 0; | |
2325 | ||
2326 | #ifdef DEBUG | |
95469ceb | 2327 | printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2328 | #endif /* DEBUG */ |
2329 | ||
8bae0a0c JSC |
2330 | switch (fmt) { |
2331 | case fmt_single: | |
76ef4165 FL |
2332 | { |
2333 | sim_fpu wop; | |
2334 | sim_fpu_32to (&wop, op); | |
2335 | boolean = sim_fpu_is_infinity (&wop); | |
2336 | break; | |
2337 | } | |
8bae0a0c | 2338 | case fmt_double: |
76ef4165 FL |
2339 | { |
2340 | sim_fpu wop; | |
2341 | sim_fpu_64to (&wop, op); | |
2342 | boolean = sim_fpu_is_infinity (&wop); | |
2343 | break; | |
2344 | } | |
8bae0a0c JSC |
2345 | default: |
2346 | printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt)); | |
2347 | break; | |
2348 | } | |
2349 | ||
2350 | #ifdef DEBUG | |
53b9417e | 2351 | printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2352 | #endif /* DEBUG */ |
2353 | ||
2354 | return(boolean); | |
2355 | } | |
2356 | ||
18c64df6 | 2357 | int |
8bae0a0c | 2358 | Less(op1,op2,fmt) |
e871dd18 JSC |
2359 | uword64 op1; |
2360 | uword64 op2; | |
8bae0a0c JSC |
2361 | FP_formats fmt; |
2362 | { | |
2363 | int boolean = 0; | |
2364 | ||
e871dd18 JSC |
2365 | /* Argument checking already performed by the FPCOMPARE code */ |
2366 | ||
8bae0a0c | 2367 | #ifdef DEBUG |
53b9417e | 2368 | printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2369 | #endif /* DEBUG */ |
2370 | ||
8bae0a0c JSC |
2371 | /* The format type should already have been checked: */ |
2372 | switch (fmt) { | |
2373 | case fmt_single: | |
2374 | { | |
76ef4165 FL |
2375 | sim_fpu wop1; |
2376 | sim_fpu wop2; | |
2377 | sim_fpu_32to (&wop1, op1); | |
2378 | sim_fpu_32to (&wop2, op2); | |
2379 | boolean = sim_fpu_is_lt (&wop1, &wop2); | |
2380 | break; | |
8bae0a0c | 2381 | } |
8bae0a0c | 2382 | case fmt_double: |
76ef4165 FL |
2383 | { |
2384 | sim_fpu wop1; | |
2385 | sim_fpu wop2; | |
2386 | sim_fpu_64to (&wop1, op1); | |
2387 | sim_fpu_64to (&wop2, op2); | |
2388 | boolean = sim_fpu_is_lt (&wop1, &wop2); | |
2389 | break; | |
2390 | } | |
50a2a691 AC |
2391 | default: |
2392 | fprintf (stderr, "Bad switch\n"); | |
2393 | abort (); | |
8bae0a0c JSC |
2394 | } |
2395 | ||
2396 | #ifdef DEBUG | |
2397 | printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2398 | #endif /* DEBUG */ | |
2399 | ||
2400 | return(boolean); | |
2401 | } | |
2402 | ||
18c64df6 | 2403 | int |
8bae0a0c | 2404 | Equal(op1,op2,fmt) |
e871dd18 JSC |
2405 | uword64 op1; |
2406 | uword64 op2; | |
8bae0a0c JSC |
2407 | FP_formats fmt; |
2408 | { | |
2409 | int boolean = 0; | |
2410 | ||
e871dd18 JSC |
2411 | /* Argument checking already performed by the FPCOMPARE code */ |
2412 | ||
8bae0a0c | 2413 | #ifdef DEBUG |
53b9417e | 2414 | printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2415 | #endif /* DEBUG */ |
2416 | ||
8bae0a0c JSC |
2417 | /* The format type should already have been checked: */ |
2418 | switch (fmt) { | |
2419 | case fmt_single: | |
76ef4165 FL |
2420 | { |
2421 | sim_fpu wop1; | |
2422 | sim_fpu wop2; | |
2423 | sim_fpu_32to (&wop1, op1); | |
2424 | sim_fpu_32to (&wop2, op2); | |
2425 | boolean = sim_fpu_is_eq (&wop1, &wop2); | |
2426 | break; | |
2427 | } | |
8bae0a0c | 2428 | case fmt_double: |
76ef4165 FL |
2429 | { |
2430 | sim_fpu wop1; | |
2431 | sim_fpu wop2; | |
2432 | sim_fpu_64to (&wop1, op1); | |
2433 | sim_fpu_64to (&wop2, op2); | |
2434 | boolean = sim_fpu_is_eq (&wop1, &wop2); | |
2435 | break; | |
2436 | } | |
50a2a691 AC |
2437 | default: |
2438 | fprintf (stderr, "Bad switch\n"); | |
2439 | abort (); | |
8bae0a0c JSC |
2440 | } |
2441 | ||
2442 | #ifdef DEBUG | |
2443 | printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2444 | #endif /* DEBUG */ | |
2445 | ||
2446 | return(boolean); | |
2447 | } | |
2448 | ||
18c64df6 | 2449 | uword64 |
a9f7253f JSC |
2450 | AbsoluteValue(op,fmt) |
2451 | uword64 op; | |
2452 | FP_formats fmt; | |
2453 | { | |
50a2a691 | 2454 | uword64 result = 0; |
a9f7253f JSC |
2455 | |
2456 | #ifdef DEBUG | |
53b9417e | 2457 | printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
a9f7253f JSC |
2458 | #endif /* DEBUG */ |
2459 | ||
2460 | /* The format type should already have been checked: */ | |
2461 | switch (fmt) { | |
2462 | case fmt_single: | |
2463 | { | |
76ef4165 FL |
2464 | sim_fpu wop; |
2465 | unsigned32 ans; | |
2466 | sim_fpu_32to (&wop, op); | |
2467 | sim_fpu_abs (&wop, &wop); | |
2468 | sim_fpu_to32 (&ans, &wop); | |
2469 | result = ans; | |
2470 | break; | |
a9f7253f | 2471 | } |
a9f7253f JSC |
2472 | case fmt_double: |
2473 | { | |
76ef4165 FL |
2474 | sim_fpu wop; |
2475 | unsigned64 ans; | |
2476 | sim_fpu_64to (&wop, op); | |
2477 | sim_fpu_abs (&wop, &wop); | |
2478 | sim_fpu_to64 (&ans, &wop); | |
2479 | result = ans; | |
2480 | break; | |
a9f7253f | 2481 | } |
50a2a691 AC |
2482 | default: |
2483 | fprintf (stderr, "Bad switch\n"); | |
2484 | abort (); | |
a9f7253f JSC |
2485 | } |
2486 | ||
2487 | return(result); | |
2488 | } | |
2489 | ||
18c64df6 | 2490 | uword64 |
8bae0a0c | 2491 | Negate(op,fmt) |
e871dd18 | 2492 | uword64 op; |
8bae0a0c JSC |
2493 | FP_formats fmt; |
2494 | { | |
50a2a691 | 2495 | uword64 result = 0; |
8bae0a0c JSC |
2496 | |
2497 | #ifdef DEBUG | |
53b9417e | 2498 | printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2499 | #endif /* DEBUG */ |
2500 | ||
2501 | /* The format type should already have been checked: */ | |
2502 | switch (fmt) { | |
2503 | case fmt_single: | |
2504 | { | |
76ef4165 FL |
2505 | sim_fpu wop; |
2506 | unsigned32 ans; | |
2507 | sim_fpu_32to (&wop, op); | |
2508 | sim_fpu_neg (&wop, &wop); | |
2509 | sim_fpu_to32 (&ans, &wop); | |
2510 | result = ans; | |
2511 | break; | |
8bae0a0c | 2512 | } |
8bae0a0c JSC |
2513 | case fmt_double: |
2514 | { | |
76ef4165 FL |
2515 | sim_fpu wop; |
2516 | unsigned64 ans; | |
2517 | sim_fpu_64to (&wop, op); | |
2518 | sim_fpu_neg (&wop, &wop); | |
2519 | sim_fpu_to64 (&ans, &wop); | |
2520 | result = ans; | |
2521 | break; | |
8bae0a0c | 2522 | } |
50a2a691 AC |
2523 | default: |
2524 | fprintf (stderr, "Bad switch\n"); | |
2525 | abort (); | |
8bae0a0c JSC |
2526 | } |
2527 | ||
2528 | return(result); | |
2529 | } | |
2530 | ||
18c64df6 | 2531 | uword64 |
8bae0a0c | 2532 | Add(op1,op2,fmt) |
e871dd18 JSC |
2533 | uword64 op1; |
2534 | uword64 op2; | |
8bae0a0c JSC |
2535 | FP_formats fmt; |
2536 | { | |
50a2a691 | 2537 | uword64 result = 0; |
8bae0a0c JSC |
2538 | |
2539 | #ifdef DEBUG | |
53b9417e | 2540 | printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2541 | #endif /* DEBUG */ |
2542 | ||
e871dd18 JSC |
2543 | /* The registers must specify FPRs valid for operands of type |
2544 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2545 | |
2546 | /* The format type should already have been checked: */ | |
2547 | switch (fmt) { | |
2548 | case fmt_single: | |
2549 | { | |
76ef4165 FL |
2550 | sim_fpu wop1; |
2551 | sim_fpu wop2; | |
2552 | sim_fpu ans; | |
2553 | unsigned32 res; | |
2554 | sim_fpu_32to (&wop1, op1); | |
2555 | sim_fpu_32to (&wop2, op2); | |
2556 | sim_fpu_add (&ans, &wop1, &wop2); | |
2557 | sim_fpu_to32 (&res, &ans); | |
2558 | result = res; | |
2559 | break; | |
8bae0a0c | 2560 | } |
8bae0a0c JSC |
2561 | case fmt_double: |
2562 | { | |
76ef4165 FL |
2563 | sim_fpu wop1; |
2564 | sim_fpu wop2; | |
2565 | sim_fpu ans; | |
2566 | unsigned64 res; | |
2567 | sim_fpu_64to (&wop1, op1); | |
2568 | sim_fpu_64to (&wop2, op2); | |
2569 | sim_fpu_add (&ans, &wop1, &wop2); | |
2570 | sim_fpu_to64 (&res, &ans); | |
2571 | result = res; | |
2572 | break; | |
8bae0a0c | 2573 | } |
50a2a691 AC |
2574 | default: |
2575 | fprintf (stderr, "Bad switch\n"); | |
2576 | abort (); | |
8bae0a0c JSC |
2577 | } |
2578 | ||
2579 | #ifdef DEBUG | |
53b9417e | 2580 | printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2581 | #endif /* DEBUG */ |
2582 | ||
2583 | return(result); | |
2584 | } | |
2585 | ||
18c64df6 | 2586 | uword64 |
8bae0a0c | 2587 | Sub(op1,op2,fmt) |
e871dd18 JSC |
2588 | uword64 op1; |
2589 | uword64 op2; | |
8bae0a0c JSC |
2590 | FP_formats fmt; |
2591 | { | |
50a2a691 | 2592 | uword64 result = 0; |
8bae0a0c JSC |
2593 | |
2594 | #ifdef DEBUG | |
53b9417e | 2595 | printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2596 | #endif /* DEBUG */ |
2597 | ||
e871dd18 JSC |
2598 | /* The registers must specify FPRs valid for operands of type |
2599 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2600 | |
2601 | /* The format type should already have been checked: */ | |
2602 | switch (fmt) { | |
2603 | case fmt_single: | |
2604 | { | |
76ef4165 FL |
2605 | sim_fpu wop1; |
2606 | sim_fpu wop2; | |
2607 | sim_fpu ans; | |
2608 | unsigned32 res; | |
2609 | sim_fpu_32to (&wop1, op1); | |
2610 | sim_fpu_32to (&wop2, op2); | |
2611 | sim_fpu_sub (&ans, &wop1, &wop2); | |
2612 | sim_fpu_to32 (&res, &ans); | |
2613 | result = res; | |
8bae0a0c JSC |
2614 | } |
2615 | break; | |
2616 | case fmt_double: | |
2617 | { | |
76ef4165 FL |
2618 | sim_fpu wop1; |
2619 | sim_fpu wop2; | |
2620 | sim_fpu ans; | |
2621 | unsigned64 res; | |
2622 | sim_fpu_64to (&wop1, op1); | |
2623 | sim_fpu_64to (&wop2, op2); | |
2624 | sim_fpu_sub (&ans, &wop1, &wop2); | |
2625 | sim_fpu_to64 (&res, &ans); | |
2626 | result = res; | |
8bae0a0c JSC |
2627 | } |
2628 | break; | |
50a2a691 AC |
2629 | default: |
2630 | fprintf (stderr, "Bad switch\n"); | |
2631 | abort (); | |
8bae0a0c JSC |
2632 | } |
2633 | ||
2634 | #ifdef DEBUG | |
53b9417e | 2635 | printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2636 | #endif /* DEBUG */ |
2637 | ||
2638 | return(result); | |
2639 | } | |
2640 | ||
18c64df6 | 2641 | uword64 |
8bae0a0c | 2642 | Multiply(op1,op2,fmt) |
e871dd18 JSC |
2643 | uword64 op1; |
2644 | uword64 op2; | |
8bae0a0c JSC |
2645 | FP_formats fmt; |
2646 | { | |
50a2a691 | 2647 | uword64 result = 0; |
8bae0a0c JSC |
2648 | |
2649 | #ifdef DEBUG | |
53b9417e | 2650 | printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2651 | #endif /* DEBUG */ |
2652 | ||
e871dd18 JSC |
2653 | /* The registers must specify FPRs valid for operands of type |
2654 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2655 | |
2656 | /* The format type should already have been checked: */ | |
2657 | switch (fmt) { | |
2658 | case fmt_single: | |
2659 | { | |
76ef4165 FL |
2660 | sim_fpu wop1; |
2661 | sim_fpu wop2; | |
2662 | sim_fpu ans; | |
2663 | unsigned32 res; | |
2664 | sim_fpu_32to (&wop1, op1); | |
2665 | sim_fpu_32to (&wop2, op2); | |
2666 | sim_fpu_mul (&ans, &wop1, &wop2); | |
2667 | sim_fpu_to32 (&res, &ans); | |
2668 | result = res; | |
2669 | break; | |
8bae0a0c | 2670 | } |
8bae0a0c JSC |
2671 | case fmt_double: |
2672 | { | |
76ef4165 FL |
2673 | sim_fpu wop1; |
2674 | sim_fpu wop2; | |
2675 | sim_fpu ans; | |
2676 | unsigned64 res; | |
2677 | sim_fpu_64to (&wop1, op1); | |
2678 | sim_fpu_64to (&wop2, op2); | |
2679 | sim_fpu_mul (&ans, &wop1, &wop2); | |
2680 | sim_fpu_to64 (&res, &ans); | |
2681 | result = res; | |
2682 | break; | |
8bae0a0c | 2683 | } |
50a2a691 AC |
2684 | default: |
2685 | fprintf (stderr, "Bad switch\n"); | |
2686 | abort (); | |
8bae0a0c JSC |
2687 | } |
2688 | ||
2689 | #ifdef DEBUG | |
53b9417e | 2690 | printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2691 | #endif /* DEBUG */ |
2692 | ||
2693 | return(result); | |
2694 | } | |
2695 | ||
18c64df6 | 2696 | uword64 |
8bae0a0c | 2697 | Divide(op1,op2,fmt) |
e871dd18 JSC |
2698 | uword64 op1; |
2699 | uword64 op2; | |
8bae0a0c JSC |
2700 | FP_formats fmt; |
2701 | { | |
50a2a691 | 2702 | uword64 result = 0; |
8bae0a0c JSC |
2703 | |
2704 | #ifdef DEBUG | |
53b9417e | 2705 | printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2706 | #endif /* DEBUG */ |
2707 | ||
e871dd18 JSC |
2708 | /* The registers must specify FPRs valid for operands of type |
2709 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2710 | |
2711 | /* The format type should already have been checked: */ | |
2712 | switch (fmt) { | |
2713 | case fmt_single: | |
2714 | { | |
76ef4165 FL |
2715 | sim_fpu wop1; |
2716 | sim_fpu wop2; | |
2717 | sim_fpu ans; | |
2718 | unsigned32 res; | |
2719 | sim_fpu_32to (&wop1, op1); | |
2720 | sim_fpu_32to (&wop2, op2); | |
2721 | sim_fpu_div (&ans, &wop1, &wop2); | |
2722 | sim_fpu_to32 (&res, &ans); | |
2723 | result = res; | |
2724 | break; | |
8bae0a0c | 2725 | } |
8bae0a0c JSC |
2726 | case fmt_double: |
2727 | { | |
76ef4165 FL |
2728 | sim_fpu wop1; |
2729 | sim_fpu wop2; | |
2730 | sim_fpu ans; | |
2731 | unsigned64 res; | |
2732 | sim_fpu_64to (&wop1, op1); | |
2733 | sim_fpu_64to (&wop2, op2); | |
2734 | sim_fpu_div (&ans, &wop1, &wop2); | |
2735 | sim_fpu_to64 (&res, &ans); | |
2736 | result = res; | |
2737 | break; | |
8bae0a0c | 2738 | } |
50a2a691 AC |
2739 | default: |
2740 | fprintf (stderr, "Bad switch\n"); | |
2741 | abort (); | |
8bae0a0c JSC |
2742 | } |
2743 | ||
2744 | #ifdef DEBUG | |
53b9417e | 2745 | printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2746 | #endif /* DEBUG */ |
2747 | ||
2748 | return(result); | |
2749 | } | |
2750 | ||
18c64df6 | 2751 | uword64 UNUSED |
8bae0a0c | 2752 | Recip(op,fmt) |
e871dd18 | 2753 | uword64 op; |
8bae0a0c JSC |
2754 | FP_formats fmt; |
2755 | { | |
50a2a691 | 2756 | uword64 result = 0; |
8bae0a0c JSC |
2757 | |
2758 | #ifdef DEBUG | |
53b9417e | 2759 | printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2760 | #endif /* DEBUG */ |
2761 | ||
e871dd18 JSC |
2762 | /* The registers must specify FPRs valid for operands of type |
2763 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2764 | |
2765 | /* The format type should already have been checked: */ | |
2766 | switch (fmt) { | |
2767 | case fmt_single: | |
2768 | { | |
76ef4165 FL |
2769 | sim_fpu wop; |
2770 | sim_fpu ans; | |
2771 | unsigned32 res; | |
2772 | sim_fpu_32to (&wop, op); | |
2773 | sim_fpu_inv (&ans, &wop); | |
2774 | sim_fpu_to32 (&res, &ans); | |
2775 | result = res; | |
2776 | break; | |
8bae0a0c | 2777 | } |
8bae0a0c JSC |
2778 | case fmt_double: |
2779 | { | |
76ef4165 FL |
2780 | sim_fpu wop; |
2781 | sim_fpu ans; | |
2782 | unsigned64 res; | |
2783 | sim_fpu_64to (&wop, op); | |
2784 | sim_fpu_inv (&ans, &wop); | |
2785 | sim_fpu_to64 (&res, &ans); | |
2786 | result = res; | |
2787 | break; | |
8bae0a0c | 2788 | } |
50a2a691 AC |
2789 | default: |
2790 | fprintf (stderr, "Bad switch\n"); | |
2791 | abort (); | |
8bae0a0c JSC |
2792 | } |
2793 | ||
2794 | #ifdef DEBUG | |
53b9417e | 2795 | printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2796 | #endif /* DEBUG */ |
2797 | ||
2798 | return(result); | |
2799 | } | |
2800 | ||
18c64df6 | 2801 | uword64 |
8bae0a0c | 2802 | SquareRoot(op,fmt) |
e871dd18 | 2803 | uword64 op; |
8bae0a0c JSC |
2804 | FP_formats fmt; |
2805 | { | |
50a2a691 | 2806 | uword64 result = 0; |
8bae0a0c JSC |
2807 | |
2808 | #ifdef DEBUG | |
53b9417e | 2809 | printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2810 | #endif /* DEBUG */ |
2811 | ||
e871dd18 JSC |
2812 | /* The registers must specify FPRs valid for operands of type |
2813 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2814 | |
2815 | /* The format type should already have been checked: */ | |
2816 | switch (fmt) { | |
2817 | case fmt_single: | |
2818 | { | |
76ef4165 FL |
2819 | sim_fpu wop; |
2820 | sim_fpu ans; | |
2821 | unsigned32 res; | |
2822 | sim_fpu_32to (&wop, op); | |
2823 | sim_fpu_sqrt (&ans, &wop); | |
2824 | sim_fpu_to32 (&res, &ans); | |
2825 | result = res; | |
2826 | break; | |
8bae0a0c | 2827 | } |
8bae0a0c JSC |
2828 | case fmt_double: |
2829 | { | |
76ef4165 FL |
2830 | sim_fpu wop; |
2831 | sim_fpu ans; | |
2832 | unsigned64 res; | |
2833 | sim_fpu_64to (&wop, op); | |
2834 | sim_fpu_sqrt (&ans, &wop); | |
2835 | sim_fpu_to64 (&res, &ans); | |
2836 | result = res; | |
2837 | break; | |
8bae0a0c | 2838 | } |
50a2a691 AC |
2839 | default: |
2840 | fprintf (stderr, "Bad switch\n"); | |
2841 | abort (); | |
8bae0a0c JSC |
2842 | } |
2843 | ||
2844 | #ifdef DEBUG | |
53b9417e | 2845 | printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2846 | #endif /* DEBUG */ |
2847 | ||
2848 | return(result); | |
2849 | } | |
2850 | ||
18c64df6 | 2851 | uword64 |
01737f42 AC |
2852 | convert (SIM_DESC sd, |
2853 | sim_cpu *cpu, | |
2854 | address_word cia, | |
2855 | int rm, | |
2856 | uword64 op, | |
2857 | FP_formats from, | |
2858 | FP_formats to) | |
8bae0a0c | 2859 | { |
76ef4165 FL |
2860 | sim_fpu wop; |
2861 | sim_fpu_round round; | |
2862 | unsigned32 result32; | |
2863 | unsigned64 result64; | |
8bae0a0c JSC |
2864 | |
2865 | #ifdef DEBUG | |
53b9417e | 2866 | printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC)); |
8bae0a0c JSC |
2867 | #endif /* DEBUG */ |
2868 | ||
76ef4165 | 2869 | switch (rm) |
8bae0a0c | 2870 | { |
76ef4165 FL |
2871 | case FP_RM_NEAREST: |
2872 | /* Round result to nearest representable value. When two | |
2873 | representable values are equally near, round to the value | |
2874 | that has a least significant bit of zero (i.e. is even). */ | |
2875 | round = sim_fpu_round_near; | |
2876 | break; | |
2877 | case FP_RM_TOZERO: | |
2878 | /* Round result to the value closest to, and not greater in | |
2879 | magnitude than, the result. */ | |
2880 | round = sim_fpu_round_zero; | |
2881 | break; | |
2882 | case FP_RM_TOPINF: | |
2883 | /* Round result to the value closest to, and not less than, | |
2884 | the result. */ | |
2885 | round = sim_fpu_round_up; | |
2886 | break; | |
2887 | ||
2888 | case FP_RM_TOMINF: | |
2889 | /* Round result to the value closest to, and not greater than, | |
2890 | the result. */ | |
2891 | round = sim_fpu_round_down; | |
2892 | break; | |
2893 | default: | |
2894 | round = 0; | |
2895 | fprintf (stderr, "Bad switch\n"); | |
2896 | abort (); | |
8bae0a0c | 2897 | } |
76ef4165 FL |
2898 | |
2899 | /* Convert the input to sim_fpu internal format */ | |
2900 | switch (from) | |
8bae0a0c | 2901 | { |
76ef4165 FL |
2902 | case fmt_double: |
2903 | sim_fpu_64to (&wop, op); | |
2904 | break; | |
2905 | case fmt_single: | |
2906 | sim_fpu_32to (&wop, op); | |
2907 | break; | |
2908 | case fmt_word: | |
2909 | sim_fpu_i32to (&wop, op, round); | |
2910 | break; | |
2911 | case fmt_long: | |
2912 | sim_fpu_i64to (&wop, op, round); | |
2913 | break; | |
2914 | default: | |
2915 | fprintf (stderr, "Bad switch\n"); | |
2916 | abort (); | |
8bae0a0c | 2917 | } |
8bae0a0c | 2918 | |
76ef4165 FL |
2919 | /* Convert sim_fpu format into the output */ |
2920 | /* The value WOP is converted to the destination format, rounding | |
2921 | using mode RM. When the destination is a fixed-point format, then | |
2922 | a source value of Infinity, NaN or one which would round to an | |
2923 | integer outside the fixed point range then an IEEE Invalid | |
2924 | Operation condition is raised. */ | |
2925 | switch (to) | |
2926 | { | |
2927 | case fmt_single: | |
2928 | sim_fpu_round_32 (&wop, round, 0); | |
2929 | sim_fpu_to32 (&result32, &wop); | |
2930 | result64 = result32; | |
2931 | break; | |
2932 | case fmt_double: | |
2933 | sim_fpu_round_64 (&wop, round, 0); | |
2934 | sim_fpu_to64 (&result64, &wop); | |
2935 | break; | |
2936 | case fmt_word: | |
2937 | sim_fpu_to32i (&result32, &wop, round); | |
2938 | result64 = result32; | |
2939 | break; | |
2940 | case fmt_long: | |
2941 | sim_fpu_to64i (&result64, &wop, round); | |
2942 | break; | |
2943 | default: | |
2944 | result64 = 0; | |
2945 | fprintf (stderr, "Bad switch\n"); | |
2946 | abort (); | |
8bae0a0c | 2947 | } |
76ef4165 | 2948 | |
8bae0a0c | 2949 | #ifdef DEBUG |
76ef4165 | 2950 | printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to)); |
8bae0a0c JSC |
2951 | #endif /* DEBUG */ |
2952 | ||
76ef4165 | 2953 | return(result64); |
8bae0a0c | 2954 | } |
8bae0a0c | 2955 | |
76ef4165 | 2956 | |
8bae0a0c JSC |
2957 | /*-- co-processor support routines ------------------------------------------*/ |
2958 | ||
2f2e6c5d | 2959 | static int UNUSED |
8bae0a0c JSC |
2960 | CoProcPresent(coproc_number) |
2961 | unsigned int coproc_number; | |
2962 | { | |
2963 | /* Return TRUE if simulator provides a model for the given co-processor number */ | |
2964 | return(0); | |
2965 | } | |
2966 | ||
18c64df6 | 2967 | void |
01737f42 AC |
2968 | cop_lw (SIM_DESC sd, |
2969 | sim_cpu *cpu, | |
2970 | address_word cia, | |
2971 | int coproc_num, | |
2972 | int coproc_reg, | |
2973 | unsigned int memword) | |
8bae0a0c | 2974 | { |
192ae475 AC |
2975 | switch (coproc_num) |
2976 | { | |
8bae0a0c | 2977 | case 1: |
192ae475 AC |
2978 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
2979 | { | |
8bae0a0c | 2980 | #ifdef DEBUG |
192ae475 | 2981 | printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword)); |
8bae0a0c | 2982 | #endif |
192ae475 AC |
2983 | StoreFPR(coproc_reg,fmt_word,(uword64)memword); |
2984 | FPR_STATE[coproc_reg] = fmt_uninterpreted; | |
2985 | break; | |
2986 | } | |
8bae0a0c JSC |
2987 | |
2988 | default: | |
f24b7b69 | 2989 | #if 0 /* this should be controlled by a configuration option */ |
192ae475 | 2990 | sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia)); |
f24b7b69 | 2991 | #endif |
192ae475 AC |
2992 | break; |
2993 | } | |
8bae0a0c JSC |
2994 | |
2995 | return; | |
2996 | } | |
2997 | ||
18c64df6 | 2998 | void |
01737f42 AC |
2999 | cop_ld (SIM_DESC sd, |
3000 | sim_cpu *cpu, | |
3001 | address_word cia, | |
3002 | int coproc_num, | |
3003 | int coproc_reg, | |
3004 | uword64 memword) | |
8bae0a0c JSC |
3005 | { |
3006 | switch (coproc_num) { | |
8bae0a0c | 3007 | case 1: |
192ae475 AC |
3008 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3009 | { | |
3010 | StoreFPR(coproc_reg,fmt_uninterpreted,memword); | |
3011 | break; | |
3012 | } | |
8bae0a0c JSC |
3013 | |
3014 | default: | |
f24b7b69 | 3015 | #if 0 /* this message should be controlled by a configuration option */ |
95469ceb | 3016 | sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia)); |
f24b7b69 | 3017 | #endif |
8bae0a0c JSC |
3018 | break; |
3019 | } | |
3020 | ||
3021 | return; | |
3022 | } | |
3023 | ||
18c64df6 | 3024 | unsigned int |
01737f42 AC |
3025 | cop_sw (SIM_DESC sd, |
3026 | sim_cpu *cpu, | |
3027 | address_word cia, | |
3028 | int coproc_num, | |
3029 | int coproc_reg) | |
8bae0a0c JSC |
3030 | { |
3031 | unsigned int value = 0; | |
da0bce9c | 3032 | |
192ae475 AC |
3033 | switch (coproc_num) |
3034 | { | |
8bae0a0c | 3035 | case 1: |
192ae475 AC |
3036 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3037 | { | |
3038 | FP_formats hold; | |
3039 | hold = FPR_STATE[coproc_reg]; | |
3040 | FPR_STATE[coproc_reg] = fmt_word; | |
3041 | value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted); | |
3042 | FPR_STATE[coproc_reg] = hold; | |
3043 | break; | |
3044 | } | |
8bae0a0c JSC |
3045 | |
3046 | default: | |
f24b7b69 | 3047 | #if 0 /* should be controlled by configuration option */ |
192ae475 | 3048 | sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); |
f24b7b69 | 3049 | #endif |
192ae475 AC |
3050 | break; |
3051 | } | |
8bae0a0c JSC |
3052 | |
3053 | return(value); | |
3054 | } | |
3055 | ||
18c64df6 | 3056 | uword64 |
01737f42 AC |
3057 | cop_sd (SIM_DESC sd, |
3058 | sim_cpu *cpu, | |
3059 | address_word cia, | |
3060 | int coproc_num, | |
3061 | int coproc_reg) | |
8bae0a0c | 3062 | { |
e871dd18 | 3063 | uword64 value = 0; |
192ae475 AC |
3064 | switch (coproc_num) |
3065 | { | |
8bae0a0c | 3066 | case 1: |
192ae475 AC |
3067 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3068 | { | |
3069 | value = ValueFPR(coproc_reg,fmt_uninterpreted); | |
3070 | break; | |
3071 | } | |
8bae0a0c JSC |
3072 | |
3073 | default: | |
f24b7b69 | 3074 | #if 0 /* should be controlled by configuration option */ |
192ae475 | 3075 | sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); |
f24b7b69 | 3076 | #endif |
192ae475 AC |
3077 | break; |
3078 | } | |
8bae0a0c JSC |
3079 | |
3080 | return(value); | |
3081 | } | |
3082 | ||
ea985d24 | 3083 | void |
01737f42 AC |
3084 | decode_coproc (SIM_DESC sd, |
3085 | sim_cpu *cpu, | |
3086 | address_word cia, | |
3087 | unsigned int instruction) | |
8bae0a0c JSC |
3088 | { |
3089 | int coprocnum = ((instruction >> 26) & 3); | |
3090 | ||
56e7c849 AC |
3091 | switch (coprocnum) |
3092 | { | |
8bae0a0c JSC |
3093 | case 0: /* standard CPU control and cache registers */ |
3094 | { | |
8bae0a0c JSC |
3095 | int code = ((instruction >> 21) & 0x1F); |
3096 | /* R4000 Users Manual (second edition) lists the following CP0 | |
3097 | instructions: | |
56e7c849 AC |
3098 | DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000) |
3099 | DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000) | |
3100 | MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000) | |
3101 | MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000) | |
3102 | TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001) | |
3103 | TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010) | |
3104 | TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110) | |
3105 | TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000) | |
3106 | CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii) | |
3107 | ERET Exception return (VR4100 = 01000010000000000000000000011000) | |
3108 | */ | |
3109 | if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0)) | |
3110 | { | |
3111 | int rt = ((instruction >> 16) & 0x1F); | |
3112 | int rd = ((instruction >> 11) & 0x1F); | |
3113 | ||
3114 | switch (rd) /* NOTEs: Standard CP0 registers */ | |
3115 | { | |
3116 | /* 0 = Index R4000 VR4100 VR4300 */ | |
3117 | /* 1 = Random R4000 VR4100 VR4300 */ | |
3118 | /* 2 = EntryLo0 R4000 VR4100 VR4300 */ | |
3119 | /* 3 = EntryLo1 R4000 VR4100 VR4300 */ | |
3120 | /* 4 = Context R4000 VR4100 VR4300 */ | |
3121 | /* 5 = PageMask R4000 VR4100 VR4300 */ | |
3122 | /* 6 = Wired R4000 VR4100 VR4300 */ | |
3123 | /* 8 = BadVAddr R4000 VR4100 VR4300 */ | |
3124 | /* 9 = Count R4000 VR4100 VR4300 */ | |
3125 | /* 10 = EntryHi R4000 VR4100 VR4300 */ | |
3126 | /* 11 = Compare R4000 VR4100 VR4300 */ | |
3127 | /* 12 = SR R4000 VR4100 VR4300 */ | |
3128 | case 12: | |
3129 | if (code == 0x00) | |
3130 | GPR[rt] = SR; | |
3131 | else | |
3132 | SR = GPR[rt]; | |
3133 | break; | |
3134 | /* 13 = Cause R4000 VR4100 VR4300 */ | |
05d1322f JL |
3135 | case 13: |
3136 | if (code == 0x00) | |
3137 | GPR[rt] = CAUSE; | |
3138 | else | |
3139 | CAUSE = GPR[rt]; | |
3140 | break; | |
56e7c849 AC |
3141 | /* 14 = EPC R4000 VR4100 VR4300 */ |
3142 | /* 15 = PRId R4000 VR4100 VR4300 */ | |
6eedf3f4 MA |
3143 | #ifdef SUBTARGET_R3900 |
3144 | /* 16 = Debug */ | |
3145 | case 16: | |
3146 | if (code == 0x00) | |
3147 | GPR[rt] = Debug; | |
3148 | else | |
3149 | Debug = GPR[rt]; | |
3150 | break; | |
3151 | #else | |
56e7c849 | 3152 | /* 16 = Config R4000 VR4100 VR4300 */ |
a09a30d2 AC |
3153 | case 16: |
3154 | if (code == 0x00) | |
3155 | GPR[rt] = C0_CONFIG; | |
3156 | else | |
3157 | C0_CONFIG = GPR[rt]; | |
3158 | break; | |
6eedf3f4 MA |
3159 | #endif |
3160 | #ifdef SUBTARGET_R3900 | |
3161 | /* 17 = Debug */ | |
3162 | case 17: | |
3163 | if (code == 0x00) | |
3164 | GPR[rt] = DEPC; | |
3165 | else | |
3166 | DEPC = GPR[rt]; | |
3167 | break; | |
3168 | #else | |
56e7c849 | 3169 | /* 17 = LLAddr R4000 VR4100 VR4300 */ |
6eedf3f4 | 3170 | #endif |
56e7c849 AC |
3171 | /* 18 = WatchLo R4000 VR4100 VR4300 */ |
3172 | /* 19 = WatchHi R4000 VR4100 VR4300 */ | |
3173 | /* 20 = XContext R4000 VR4100 VR4300 */ | |
3174 | /* 26 = PErr or ECC R4000 VR4100 VR4300 */ | |
3175 | /* 27 = CacheErr R4000 VR4100 */ | |
3176 | /* 28 = TagLo R4000 VR4100 VR4300 */ | |
3177 | /* 29 = TagHi R4000 VR4100 VR4300 */ | |
3178 | /* 30 = ErrorEPC R4000 VR4100 VR4300 */ | |
3179 | GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */ | |
3180 | /* CPR[0,rd] = GPR[rt]; */ | |
3181 | default: | |
3182 | if (code == 0x00) | |
18c64df6 | 3183 | sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 | 3184 | else |
18c64df6 | 3185 | sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 AC |
3186 | } |
3187 | } | |
3188 | else if (code == 0x10 && (instruction & 0x3f) == 0x18) | |
3189 | { | |
3190 | /* ERET */ | |
3191 | if (SR & status_ERL) | |
3192 | { | |
3193 | /* Oops, not yet available */ | |
18c64df6 | 3194 | sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet"); |
56e7c849 AC |
3195 | PC = EPC; |
3196 | SR &= ~status_ERL; | |
3197 | } | |
3198 | else | |
3199 | { | |
3200 | PC = EPC; | |
3201 | SR &= ~status_EXL; | |
3202 | } | |
3203 | } | |
6eedf3f4 MA |
3204 | else if (code == 0x10 && (instruction & 0x3f) == 0x10) |
3205 | { | |
3206 | /* RFE */ | |
3207 | } | |
3208 | else if (code == 0x10 && (instruction & 0x3f) == 0x1F) | |
3209 | { | |
3210 | /* DERET */ | |
3211 | Debug &= ~Debug_DM; | |
3212 | DELAYSLOT(); | |
3213 | DSPC = DEPC; | |
3214 | } | |
56e7c849 | 3215 | else |
95469ceb | 3216 | sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia)); |
e871dd18 | 3217 | /* TODO: When executing an ERET or RFE instruction we should |
8bae0a0c JSC |
3218 | clear LLBIT, to ensure that any out-standing atomic |
3219 | read/modify/write sequence fails. */ | |
3220 | } | |
56e7c849 AC |
3221 | break; |
3222 | ||
8bae0a0c | 3223 | case 2: /* undefined co-processor */ |
95469ceb | 3224 | sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia)); |
8bae0a0c | 3225 | break; |
56e7c849 | 3226 | |
8bae0a0c JSC |
3227 | case 1: /* should not occur (FPU co-processor) */ |
3228 | case 3: /* should not occur (FPU co-processor) */ | |
3229 | SignalException(ReservedInstruction,instruction); | |
3230 | break; | |
56e7c849 AC |
3231 | } |
3232 | ||
8bae0a0c JSC |
3233 | return; |
3234 | } | |
3235 | ||
3236 | /*-- instruction simulation -------------------------------------------------*/ | |
3237 | ||
16bd5d6e AC |
3238 | /* When the IGEN simulator is being built, the function below is be |
3239 | replaced by a generated version. However, WITH_IGEN == 2 indicates | |
3240 | that the fubction below should be compiled but under a different | |
3241 | name (to allow backward compatibility) */ | |
3242 | ||
3243 | #if (WITH_IGEN != 1) | |
3244 | #if (WITH_IGEN > 1) | |
dad6f1f3 AC |
3245 | void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal)); |
3246 | void | |
9ec6741b | 3247 | old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal) |
dad6f1f3 | 3248 | #else |
2e61a3ad | 3249 | void |
9ec6741b | 3250 | sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal) |
dad6f1f3 | 3251 | #endif |
2e61a3ad AC |
3252 | SIM_DESC sd; |
3253 | int next_cpu_nr; /* ignore */ | |
9ec6741b | 3254 | int nr_cpus; /* ignore */ |
2e61a3ad | 3255 | int siggnal; /* ignore */ |
8bae0a0c | 3256 | { |
01737f42 | 3257 | sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */ |
50a2a691 | 3258 | #if !defined(FASTSIM) |
8bae0a0c | 3259 | unsigned int pipeline_count = 1; |
50a2a691 | 3260 | #endif |
8bae0a0c JSC |
3261 | |
3262 | #ifdef DEBUG | |
50a2a691 | 3263 | if (STATE_MEMORY (sd) == NULL) { |
8bae0a0c JSC |
3264 | printf("DBG: simulate() entered with no memory\n"); |
3265 | exit(1); | |
3266 | } | |
3267 | #endif /* DEBUG */ | |
3268 | ||
3269 | #if 0 /* Disabled to check that everything works OK */ | |
3270 | /* The VR4300 seems to sign-extend the PC on its first | |
3271 | access. However, this may just be because it is currently | |
3272 | configured in 32bit mode. However... */ | |
3273 | PC = SIGNEXTEND(PC,32); | |
3274 | #endif | |
3275 | ||
3276 | /* main controlling loop */ | |
2e61a3ad | 3277 | while (1) { |
7ce8b917 AC |
3278 | /* vaddr is slowly being replaced with cia - current instruction |
3279 | address */ | |
3280 | address_word cia = (uword64)PC; | |
3281 | address_word vaddr = cia; | |
dad6f1f3 | 3282 | address_word paddr; |
8bae0a0c | 3283 | int cca; |
53b9417e | 3284 | unsigned int instruction; /* uword64? what's this used for? FIXME! */ |
8bae0a0c JSC |
3285 | |
3286 | #ifdef DEBUG | |
3287 | { | |
3288 | printf("DBG: state = 0x%08X :",state); | |
8bae0a0c JSC |
3289 | if (state & simHALTEX) printf(" simHALTEX"); |
3290 | if (state & simHALTIN) printf(" simHALTIN"); | |
53b9417e | 3291 | printf("\n"); |
8bae0a0c JSC |
3292 | } |
3293 | #endif /* DEBUG */ | |
3294 | ||
0c2c5f61 | 3295 | DSSTATE = (STATE & simDELAYSLOT); |
8bae0a0c JSC |
3296 | #ifdef DEBUG |
3297 | if (dsstate) | |
18c64df6 | 3298 | sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3299 | #endif /* DEBUG */ |
3300 | ||
7ce8b917 AC |
3301 | /* Fetch the next instruction from the simulator memory: */ |
3302 | if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { | |
6429b296 JW |
3303 | if ((vaddr & 1) == 0) { |
3304 | /* Copy the action of the LW instruction */ | |
3305 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
3306 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
3307 | uword64 value; | |
3308 | unsigned int byte; | |
3309 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
53b9417e | 3310 | LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL); |
6429b296 JW |
3311 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); |
3312 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
3313 | } else { | |
3314 | /* Copy the action of the LH instruction */ | |
3315 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0); | |
3316 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0); | |
3317 | uword64 value; | |
3318 | unsigned int byte; | |
3319 | paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK) | |
3320 | | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1))); | |
53b9417e | 3321 | LoadMemory(&value,NULL,cca, AccessLength_HALFWORD, |
6429b296 JW |
3322 | paddr & ~ (uword64) 1, |
3323 | vaddr, isINSTRUCTION, isREAL); | |
3324 | byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1)); | |
3325 | instruction = ((value >> (8 * byte)) & 0xFFFF); | |
3326 | } | |
8bae0a0c | 3327 | } else { |
53b9417e | 3328 | fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC)); |
8bae0a0c JSC |
3329 | exit(1); |
3330 | } | |
3331 | ||
3332 | #ifdef DEBUG | |
18c64df6 | 3333 | sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC)); |
8bae0a0c JSC |
3334 | #endif /* DEBUG */ |
3335 | ||
8bae0a0c JSC |
3336 | /* This is required by exception processing, to ensure that we can |
3337 | cope with exceptions in the delay slots of branches that may | |
3338 | already have changed the PC. */ | |
6429b296 JW |
3339 | if ((vaddr & 1) == 0) |
3340 | PC += 4; /* increment ready for the next fetch */ | |
3341 | else | |
3342 | PC += 2; | |
8bae0a0c JSC |
3343 | /* NOTE: If we perform a delay slot change to the PC, this |
3344 | increment is not requuired. However, it would make the | |
3345 | simulator more complicated to try and avoid this small hit. */ | |
3346 | ||
3347 | /* Currently this code provides a simple model. For more | |
3348 | complicated models we could perform exception status checks at | |
3349 | this point, and set the simSTOP state as required. This could | |
3350 | also include processing any hardware interrupts raised by any | |
3351 | I/O model attached to the simulator context. | |
3352 | ||
3353 | Support for "asynchronous" I/O events within the simulated world | |
3354 | could be providing by managing a counter, and calling a I/O | |
3355 | specific handler when a particular threshold is reached. On most | |
3356 | architectures a decrement and check for zero operation is | |
3357 | usually quicker than an increment and compare. However, the | |
3358 | process of managing a known value decrement to zero, is higher | |
3359 | than the cost of using an explicit value UINT_MAX into the | |
3360 | future. Which system is used will depend on how complicated the | |
3361 | I/O model is, and how much it is likely to affect the simulator | |
3362 | bandwidth. | |
3363 | ||
3364 | If events need to be scheduled further in the future than | |
3365 | UINT_MAX event ticks, then the I/O model should just provide its | |
3366 | own counter, triggered from the event system. */ | |
3367 | ||
3368 | /* MIPS pipeline ticks. To allow for future support where the | |
3369 | pipeline hit of individual instructions is known, this control | |
3370 | loop manages a "pipeline_count" variable. It is initialised to | |
3371 | 1 (one), and will only be changed by the simulator engine when | |
3372 | executing an instruction. If the engine does not have access to | |
3373 | pipeline cycle count information then all instructions will be | |
3374 | treated as using a single cycle. NOTE: A standard system is not | |
3375 | provided by the default simulator because different MIPS | |
3376 | architectures have different cycle counts for the same | |
50a2a691 AC |
3377 | instructions. |
3378 | ||
3379 | [NOTE: pipeline_count has been replaced the event queue] */ | |
8bae0a0c | 3380 | |
a09a30d2 AC |
3381 | /* shuffle the floating point status pipeline state */ |
3382 | ENGINE_ISSUE_PREFIX_HOOK(); | |
8bae0a0c JSC |
3383 | |
3384 | /* NOTE: For multi-context simulation environments the "instruction" | |
3385 | variable should be local to this routine. */ | |
3386 | ||
3387 | /* Shorthand accesses for engine. Note: If we wanted to use global | |
3388 | variables (and a single-threaded simulator engine), then we can | |
3389 | create the actual variables with these names. */ | |
3390 | ||
0c2c5f61 | 3391 | if (!(STATE & simSKIPNEXT)) { |
8bae0a0c | 3392 | /* Include the simulator engine */ |
284e759d | 3393 | #include "oengine.c" |
f24b7b69 | 3394 | #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT) |
8bae0a0c JSC |
3395 | #error "Mismatch between run-time simulator code and simulation engine" |
3396 | #endif | |
18c64df6 AC |
3397 | #if (WITH_TARGET_WORD_BITSIZE != GPRLEN) |
3398 | #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN" | |
3399 | #endif | |
76ef4165 | 3400 | #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU)) |
18c64df6 AC |
3401 | #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU" |
3402 | #endif | |
8bae0a0c JSC |
3403 | |
3404 | #if defined(WARN_LOHI) | |
3405 | /* Decrement the HI/LO validity ticks */ | |
3406 | if (HIACCESS > 0) | |
3407 | HIACCESS--; | |
3408 | if (LOACCESS > 0) | |
3409 | LOACCESS--; | |
0425cfb3 | 3410 | /* start-sanitize-r5900 */ |
53b9417e DE |
3411 | if (HI1ACCESS > 0) |
3412 | HI1ACCESS--; | |
3413 | if (LO1ACCESS > 0) | |
3414 | LO1ACCESS--; | |
0425cfb3 | 3415 | /* end-sanitize-r5900 */ |
8bae0a0c JSC |
3416 | #endif /* WARN_LOHI */ |
3417 | ||
8bae0a0c JSC |
3418 | /* For certain MIPS architectures, GPR[0] is hardwired to zero. We |
3419 | should check for it being changed. It is better doing it here, | |
3420 | than within the simulator, since it will help keep the simulator | |
3421 | small. */ | |
3422 | if (ZERO != 0) { | |
05d1322f | 3423 | #if defined(WARN_ZERO) |
95469ceb | 3424 | sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia)); |
05d1322f | 3425 | #endif /* WARN_ZERO */ |
8bae0a0c JSC |
3426 | ZERO = 0; /* reset back to zero before next instruction */ |
3427 | } | |
8bae0a0c | 3428 | } else /* simSKIPNEXT check */ |
0c2c5f61 | 3429 | STATE &= ~simSKIPNEXT; |
8bae0a0c JSC |
3430 | |
3431 | /* If the delay slot was active before the instruction is | |
3432 | executed, then update the PC to its new value: */ | |
0c2c5f61 | 3433 | if (DSSTATE) { |
8bae0a0c | 3434 | #ifdef DEBUG |
53b9417e | 3435 | printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3436 | #endif /* DEBUG */ |
3437 | PC = DSPC; | |
6eedf3f4 | 3438 | CANCELDELAYSLOT(); |
8bae0a0c JSC |
3439 | } |
3440 | ||
2acd126a AC |
3441 | if (MIPSISA < 4) |
3442 | PENDING_TICK(); | |
8bae0a0c JSC |
3443 | |
3444 | #if !defined(FASTSIM) | |
50a2a691 AC |
3445 | if (sim_events_tickn (sd, pipeline_count)) |
3446 | { | |
3447 | /* cpu->cia = cia; */ | |
3448 | sim_events_process (sd); | |
3449 | } | |
3450 | #else | |
2e61a3ad AC |
3451 | if (sim_events_tick (sd)) |
3452 | { | |
3453 | /* cpu->cia = cia; */ | |
3454 | sim_events_process (sd); | |
3455 | } | |
50a2a691 | 3456 | #endif /* FASTSIM */ |
8bae0a0c | 3457 | } |
8bae0a0c | 3458 | } |
16bd5d6e AC |
3459 | #endif |
3460 | ||
8bae0a0c | 3461 | |
53b9417e DE |
3462 | /* This code copied from gdb's utils.c. Would like to share this code, |
3463 | but don't know of a common place where both could get to it. */ | |
3464 | ||
3465 | /* Temporary storage using circular buffer */ | |
3466 | #define NUMCELLS 16 | |
3467 | #define CELLSIZE 32 | |
3468 | static char* | |
3469 | get_cell() | |
3470 | { | |
3471 | static char buf[NUMCELLS][CELLSIZE]; | |
3472 | static int cell=0; | |
3473 | if (++cell>=NUMCELLS) cell=0; | |
3474 | return buf[cell]; | |
3475 | } | |
3476 | ||
3477 | /* Print routines to handle variable size regs, etc */ | |
3478 | ||
3479 | /* Eliminate warning from compiler on 32-bit systems */ | |
3480 | static int thirty_two = 32; | |
3481 | ||
3482 | char* | |
3483 | pr_addr(addr) | |
3484 | SIM_ADDR addr; | |
3485 | { | |
3486 | char *paddr_str=get_cell(); | |
3487 | switch (sizeof(addr)) | |
3488 | { | |
3489 | case 8: | |
50a2a691 | 3490 | sprintf(paddr_str,"%08lx%08lx", |
53b9417e DE |
3491 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3492 | break; | |
3493 | case 4: | |
50a2a691 | 3494 | sprintf(paddr_str,"%08lx",(unsigned long)addr); |
53b9417e DE |
3495 | break; |
3496 | case 2: | |
3497 | sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff)); | |
3498 | break; | |
3499 | default: | |
3500 | sprintf(paddr_str,"%x",addr); | |
3501 | } | |
3502 | return paddr_str; | |
3503 | } | |
3504 | ||
87e43259 AC |
3505 | char* |
3506 | pr_uword64(addr) | |
3507 | uword64 addr; | |
3508 | { | |
3509 | char *paddr_str=get_cell(); | |
50a2a691 | 3510 | sprintf(paddr_str,"%08lx%08lx", |
87e43259 AC |
3511 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3512 | return paddr_str; | |
3513 | } | |
3514 | ||
3515 | ||
2acd126a AC |
3516 | void |
3517 | pending_tick (SIM_DESC sd, | |
3518 | sim_cpu *cpu, | |
3519 | address_word cia) | |
3520 | { | |
3521 | if (PENDING_TRACE) | |
3522 | sim_io_printf (sd, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN, PENDING_OUT, PENDING_TOTAL); | |
3523 | if (PENDING_OUT != PENDING_IN) | |
3524 | { | |
3525 | int loop; | |
3526 | int index = PENDING_OUT; | |
3527 | int total = PENDING_TOTAL; | |
3528 | if (PENDING_TOTAL == 0) | |
3529 | sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n"); | |
3530 | for (loop = 0; (loop < total); loop++) | |
3531 | { | |
3532 | if (PENDING_SLOT_DEST[index] != NULL) | |
3533 | { | |
3534 | PENDING_SLOT_DELAY[index] -= 1; | |
3535 | if (PENDING_SLOT_DELAY[index] == 0) | |
3536 | { | |
3537 | if (PENDING_SLOT_BIT[index] >= 0) | |
3538 | switch (PENDING_SLOT_SIZE[index]) | |
3539 | { | |
3540 | case 32: | |
3541 | if (PENDING_SLOT_VALUE[index]) | |
3542 | *(unsigned32*)PENDING_SLOT_DEST[index] |= | |
3543 | BIT32 (PENDING_SLOT_BIT[index]); | |
3544 | else | |
3545 | *(unsigned32*)PENDING_SLOT_DEST[index] &= | |
3546 | BIT32 (PENDING_SLOT_BIT[index]); | |
3547 | break; | |
3548 | case 64: | |
3549 | if (PENDING_SLOT_VALUE[index]) | |
3550 | *(unsigned64*)PENDING_SLOT_DEST[index] |= | |
3551 | BIT64 (PENDING_SLOT_BIT[index]); | |
3552 | else | |
3553 | *(unsigned64*)PENDING_SLOT_DEST[index] &= | |
3554 | BIT64 (PENDING_SLOT_BIT[index]); | |
3555 | break; | |
3556 | break; | |
3557 | } | |
3558 | else | |
3559 | switch (PENDING_SLOT_SIZE[index]) | |
3560 | { | |
3561 | case 32: | |
3562 | *(unsigned32*)PENDING_SLOT_DEST[index] = | |
3563 | PENDING_SLOT_VALUE[index]; | |
3564 | break; | |
3565 | case 64: | |
3566 | *(unsigned64*)PENDING_SLOT_DEST[index] = | |
3567 | PENDING_SLOT_VALUE[index]; | |
3568 | break; | |
3569 | } | |
3570 | } | |
3571 | if (PENDING_OUT == index) | |
3572 | { | |
3573 | PENDING_SLOT_DEST[index] = NULL; | |
3574 | PENDING_OUT = (PENDING_OUT + 1) % PSLOTS; | |
3575 | PENDING_TOTAL--; | |
3576 | } | |
3577 | } | |
3578 | } | |
3579 | index = (index + 1) % PSLOTS; | |
3580 | } | |
3581 | } | |
3582 | ||
8bae0a0c JSC |
3583 | /*---------------------------------------------------------------------------*/ |
3584 | /*> EOF interp.c <*/ |