Commit | Line | Data |
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8bae0a0c JSC |
1 | /*> interp.c <*/ |
2 | /* Simulator for the MIPS architecture. | |
3 | ||
4 | This file is part of the MIPS sim | |
5 | ||
6 | THIS SOFTWARE IS NOT COPYRIGHTED | |
7 | ||
8 | Cygnus offers the following for use in the public domain. Cygnus | |
9 | makes no warranty with regard to the software or it's performance | |
10 | and the user accepts the software "AS IS" with all faults. | |
11 | ||
12 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
13 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
14 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
15 | ||
16 | $Revision$ | |
17 | $Author$ | |
e3d12c65 | 18 | $Date$ |
8bae0a0c JSC |
19 | |
20 | NOTEs: | |
21 | ||
8bae0a0c JSC |
22 | The IDT monitor (found on the VR4300 board), seems to lie about |
23 | register contents. It seems to treat the registers as sign-extended | |
24 | 32-bit values. This cause *REAL* problems when single-stepping 64-bit | |
25 | code on the hardware. | |
26 | ||
27 | */ | |
28 | ||
e2f8ffb7 AC |
29 | /* The TRACE manifests enable the provision of extra features. If they |
30 | are not defined then a simpler (quicker) simulator is constructed | |
31 | without the required run-time checks, etc. */ | |
8bae0a0c JSC |
32 | #if 1 /* 0 to allow user build selection, 1 to force inclusion */ |
33 | #define TRACE (1) | |
8bae0a0c JSC |
34 | #endif |
35 | ||
2e61a3ad AC |
36 | #include "bfd.h" |
37 | #include "sim-main.h" | |
38 | #include "sim-utils.h" | |
39 | #include "sim-options.h" | |
50a2a691 | 40 | #include "sim-assert.h" |
2e61a3ad | 41 | |
4fa134be ILT |
42 | #include "config.h" |
43 | ||
8bae0a0c JSC |
44 | #include <stdio.h> |
45 | #include <stdarg.h> | |
46 | #include <ansidecl.h> | |
8bae0a0c JSC |
47 | #include <ctype.h> |
48 | #include <limits.h> | |
49 | #include <math.h> | |
4fa134be ILT |
50 | #ifdef HAVE_STDLIB_H |
51 | #include <stdlib.h> | |
52 | #endif | |
53 | #ifdef HAVE_STRING_H | |
54 | #include <string.h> | |
55 | #else | |
56 | #ifdef HAVE_STRINGS_H | |
57 | #include <strings.h> | |
58 | #endif | |
59 | #endif | |
8bae0a0c JSC |
60 | |
61 | #include "getopt.h" | |
62 | #include "libiberty.h" | |
9d52bcb7 | 63 | #include "bfd.h" |
8bae0a0c | 64 | #include "callback.h" /* GDB simulator callback interface */ |
e3d12c65 | 65 | #include "remote-sim.h" /* GDB simulator interface */ |
8bae0a0c | 66 | |
f24b7b69 JSC |
67 | #include "sysdep.h" |
68 | ||
53b9417e DE |
69 | #ifndef PARAMS |
70 | #define PARAMS(x) | |
71 | #endif | |
72 | ||
73 | char* pr_addr PARAMS ((SIM_ADDR addr)); | |
87e43259 | 74 | char* pr_uword64 PARAMS ((uword64 addr)); |
53b9417e | 75 | |
f24b7b69 | 76 | |
8bae0a0c | 77 | /* Get the simulator engine description, without including the code: */ |
192ae475 AC |
78 | #if (WITH_IGEN) |
79 | #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3) | |
80 | #else | |
8bae0a0c | 81 | #define SIM_MANIFESTS |
284e759d | 82 | #include "oengine.c" |
8bae0a0c | 83 | #undef SIM_MANIFESTS |
192ae475 | 84 | #endif |
8bae0a0c | 85 | |
01737f42 AC |
86 | /* Within interp.c we refer to the sim_state and sim_cpu directly. */ |
87 | #define SD sd | |
88 | #define CPU cpu | |
89 | ||
f7481d45 | 90 | |
8bae0a0c JSC |
91 | /* The following reserved instruction value is used when a simulator |
92 | trap is required. NOTE: Care must be taken, since this value may be | |
93 | used in later revisions of the MIPS ISA. */ | |
53b9417e DE |
94 | #define RSVD_INSTRUCTION (0x00000005) |
95 | #define RSVD_INSTRUCTION_MASK (0xFC00003F) | |
96 | ||
97 | #define RSVD_INSTRUCTION_ARG_SHIFT 6 | |
98 | #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF | |
99 | ||
8bae0a0c | 100 | |
6eedf3f4 MA |
101 | /* Bits in the Debug register */ |
102 | #define Debug_DBD 0x80000000 /* Debug Branch Delay */ | |
103 | #define Debug_DM 0x40000000 /* Debug Mode */ | |
104 | #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */ | |
105 | ||
106 | ||
107 | ||
8bae0a0c | 108 | |
8bae0a0c | 109 | |
e3d12c65 DE |
110 | /*---------------------------------------------------------------------------*/ |
111 | /*-- GDB simulator interface ------------------------------------------------*/ | |
112 | /*---------------------------------------------------------------------------*/ | |
113 | ||
0c2c5f61 | 114 | static void ColdReset PARAMS((SIM_DESC sd)); |
e3d12c65 DE |
115 | |
116 | /*---------------------------------------------------------------------------*/ | |
117 | ||
8bae0a0c | 118 | |
8bae0a0c | 119 | |
8bae0a0c | 120 | #define DELAYSLOT() {\ |
0c2c5f61 | 121 | if (STATE & simDELAYSLOT)\ |
18c64df6 | 122 | sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\ |
0c2c5f61 | 123 | STATE |= simDELAYSLOT;\ |
8bae0a0c JSC |
124 | } |
125 | ||
aaff8437 ILT |
126 | #define JALDELAYSLOT() {\ |
127 | DELAYSLOT ();\ | |
0c2c5f61 | 128 | STATE |= simJALDELAYSLOT;\ |
aaff8437 ILT |
129 | } |
130 | ||
8bae0a0c | 131 | #define NULLIFY() {\ |
0c2c5f61 AC |
132 | STATE &= ~simDELAYSLOT;\ |
133 | STATE |= simSKIPNEXT;\ | |
8bae0a0c JSC |
134 | } |
135 | ||
6eedf3f4 | 136 | #define CANCELDELAYSLOT() {\ |
0c2c5f61 AC |
137 | DSSTATE = 0;\ |
138 | STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\ | |
6eedf3f4 MA |
139 | } |
140 | ||
0c2c5f61 AC |
141 | #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0) |
142 | #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0) | |
aaff8437 | 143 | |
a9f7253f JSC |
144 | #define K0BASE (0x80000000) |
145 | #define K0SIZE (0x20000000) | |
146 | #define K1BASE (0xA0000000) | |
147 | #define K1SIZE (0x20000000) | |
525d929e AC |
148 | #define MONITOR_BASE (0xBFC00000) |
149 | #define MONITOR_SIZE (1 << 11) | |
150 | #define MEM_SIZE (2 << 20) | |
a9f7253f | 151 | |
8bae0a0c | 152 | #if defined(TRACE) |
4fa134be | 153 | static char *tracefile = "trace.din"; /* default filename for trace log */ |
030843d7 | 154 | FILE *tracefh = NULL; |
18c64df6 | 155 | static void open_trace PARAMS((SIM_DESC sd)); |
8bae0a0c JSC |
156 | #endif /* TRACE */ |
157 | ||
7c5d88c1 DE |
158 | static DECLARE_OPTION_HANDLER (mips_option_handler); |
159 | ||
22de994d AC |
160 | #define OPTION_DINERO_TRACE 200 |
161 | #define OPTION_DINERO_FILE 201 | |
162 | ||
50a2a691 | 163 | static SIM_RC |
7c5d88c1 | 164 | mips_option_handler (sd, cpu, opt, arg, is_command) |
50a2a691 | 165 | SIM_DESC sd; |
7c5d88c1 | 166 | sim_cpu *cpu; |
50a2a691 AC |
167 | int opt; |
168 | char *arg; | |
7c5d88c1 | 169 | int is_command; |
2e61a3ad | 170 | { |
01737f42 | 171 | int cpu_nr; |
50a2a691 AC |
172 | switch (opt) |
173 | { | |
22de994d | 174 | case OPTION_DINERO_TRACE: /* ??? */ |
50a2a691 AC |
175 | #if defined(TRACE) |
176 | /* Eventually the simTRACE flag could be treated as a toggle, to | |
177 | allow external control of the program points being traced | |
178 | (i.e. only from main onwards, excluding the run-time setup, | |
179 | etc.). */ | |
01737f42 | 180 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) |
50a2a691 | 181 | { |
01737f42 AC |
182 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); |
183 | if (arg == NULL) | |
184 | STATE |= simTRACE; | |
185 | else if (strcmp (arg, "yes") == 0) | |
186 | STATE |= simTRACE; | |
187 | else if (strcmp (arg, "no") == 0) | |
188 | STATE &= ~simTRACE; | |
189 | else if (strcmp (arg, "on") == 0) | |
190 | STATE |= simTRACE; | |
191 | else if (strcmp (arg, "off") == 0) | |
192 | STATE &= ~simTRACE; | |
193 | else | |
194 | { | |
195 | fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg); | |
196 | return SIM_RC_FAIL; | |
197 | } | |
50a2a691 AC |
198 | } |
199 | return SIM_RC_OK; | |
200 | #else /* !TRACE */ | |
201 | fprintf(stderr,"\ | |
22de994d | 202 | Simulator constructed without dinero tracing support (for performance).\n\ |
50a2a691 AC |
203 | Re-compile simulator with \"-DTRACE\" to enable this option.\n"); |
204 | return SIM_RC_FAIL; | |
205 | #endif /* !TRACE */ | |
206 | ||
22de994d | 207 | case OPTION_DINERO_FILE: |
50a2a691 AC |
208 | #if defined(TRACE) |
209 | if (optarg != NULL) { | |
210 | char *tmp; | |
211 | tmp = (char *)malloc(strlen(optarg) + 1); | |
212 | if (tmp == NULL) | |
213 | { | |
18c64df6 | 214 | sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg); |
50a2a691 AC |
215 | return SIM_RC_FAIL; |
216 | } | |
217 | else { | |
218 | strcpy(tmp,optarg); | |
219 | tracefile = tmp; | |
18c64df6 | 220 | sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile); |
50a2a691 AC |
221 | } |
222 | } | |
223 | #endif /* TRACE */ | |
224 | return SIM_RC_OK; | |
225 | ||
50a2a691 AC |
226 | } |
227 | ||
228 | return SIM_RC_OK; | |
2e61a3ad | 229 | } |
50a2a691 AC |
230 | |
231 | static const OPTION mips_options[] = | |
2e61a3ad | 232 | { |
22de994d AC |
233 | { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE}, |
234 | '\0', "on|off", "Enable dinero tracing", | |
50a2a691 | 235 | mips_option_handler }, |
22de994d AC |
236 | { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE}, |
237 | '\0', "FILE", "Write dinero trace to FILE", | |
50a2a691 | 238 | mips_option_handler }, |
50a2a691 AC |
239 | { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } |
240 | }; | |
241 | ||
242 | ||
56e7c849 AC |
243 | int interrupt_pending; |
244 | ||
50a2a691 AC |
245 | static void |
246 | interrupt_event (SIM_DESC sd, void *data) | |
2e61a3ad | 247 | { |
01737f42 | 248 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
56e7c849 AC |
249 | if (SR & status_IE) |
250 | { | |
251 | interrupt_pending = 0; | |
18c64df6 | 252 | SignalExceptionInterrupt (); |
56e7c849 AC |
253 | } |
254 | else if (!interrupt_pending) | |
255 | sim_events_schedule (sd, 1, interrupt_event, data); | |
2e61a3ad | 256 | } |
f7481d45 | 257 | |
f7481d45 | 258 | |
2c88fae9 IC |
259 | /*---------------------------------------------------------------------------*/ |
260 | /*-- Device registration hook -----------------------------------------------*/ | |
261 | /*---------------------------------------------------------------------------*/ | |
97908603 | 262 | static void device_init(SIM_DESC sd) { |
2c88fae9 IC |
263 | #ifdef DEVICE_INIT |
264 | extern void register_devices(SIM_DESC); | |
265 | register_devices(sd); | |
266 | #endif | |
267 | } | |
50a2a691 | 268 | |
97908603 | 269 | /* start-sanitize-sky */ |
7aa6042f | 270 | #ifdef TARGET_SKY |
97908603 | 271 | static struct { |
a859684b RU |
272 | short i[NUM_VU_INTEGER_REGS]; |
273 | int f[NUM_VU_REGS - NUM_VU_INTEGER_REGS]; | |
97908603 | 274 | } vu_regs[2]; |
7aa6042f | 275 | #endif |
97908603 RU |
276 | /* end-sanitize-sky */ |
277 | ||
8bae0a0c JSC |
278 | /*---------------------------------------------------------------------------*/ |
279 | /*-- GDB simulator interface ------------------------------------------------*/ | |
280 | /*---------------------------------------------------------------------------*/ | |
281 | ||
53b9417e | 282 | SIM_DESC |
247fccde | 283 | sim_open (kind, cb, abfd, argv) |
87e43259 | 284 | SIM_OPEN_KIND kind; |
50a2a691 | 285 | host_callback *cb; |
247fccde | 286 | struct _bfd *abfd; |
53b9417e | 287 | char **argv; |
8bae0a0c | 288 | { |
18c64df6 | 289 | SIM_DESC sd = sim_state_alloc (kind, cb); |
01737f42 | 290 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
2e61a3ad | 291 | |
525d929e AC |
292 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
293 | ||
50a2a691 AC |
294 | /* FIXME: watchpoints code shouldn't need this */ |
295 | STATE_WATCHPOINTS (sd)->pc = &(PC); | |
296 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
297 | STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event; | |
298 | ||
0c2c5f61 | 299 | STATE = 0; |
50a2a691 | 300 | |
2e61a3ad AC |
301 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
302 | return 0; | |
7c5d88c1 | 303 | sim_add_option_table (sd, NULL, mips_options); |
2e61a3ad | 304 | |
63be8feb AC |
305 | /* Allocate core managed memory */ |
306 | ||
307 | /* the monitor */ | |
308 | sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE); | |
309 | /* For compatibility with the old code - under this (at level one) | |
310 | are the kernel spaces K0 & K1. Both of these map to a single | |
311 | smaller sub region */ | |
a48e8c8d | 312 | sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */ |
63be8feb AC |
313 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x", |
314 | K1BASE, K0SIZE, | |
315 | MEM_SIZE, /* actual size */ | |
316 | K0BASE); | |
317 | ||
2c88fae9 IC |
318 | device_init(sd); |
319 | ||
2e61a3ad AC |
320 | /* getopt will print the error message so we just have to exit if this fails. |
321 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
322 | print_filtered. */ | |
323 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
324 | { | |
325 | /* Uninstall the modules to avoid memory leaks, | |
326 | file descriptor leaks, etc. */ | |
327 | sim_module_uninstall (sd); | |
328 | return 0; | |
329 | } | |
2e61a3ad | 330 | |
fafce69a AC |
331 | /* check for/establish the a reference program image */ |
332 | if (sim_analyze_program (sd, | |
333 | (STATE_PROG_ARGV (sd) != NULL | |
334 | ? *STATE_PROG_ARGV (sd) | |
335 | : NULL), | |
336 | abfd) != SIM_RC_OK) | |
337 | { | |
338 | sim_module_uninstall (sd); | |
339 | return 0; | |
340 | } | |
341 | ||
247fccde AC |
342 | /* Configure/verify the target byte order and other runtime |
343 | configuration options */ | |
fafce69a | 344 | if (sim_config (sd) != SIM_RC_OK) |
247fccde AC |
345 | { |
346 | sim_module_uninstall (sd); | |
347 | return 0; | |
348 | } | |
349 | ||
2e61a3ad AC |
350 | if (sim_post_argv_init (sd) != SIM_RC_OK) |
351 | { | |
352 | /* Uninstall the modules to avoid memory leaks, | |
353 | file descriptor leaks, etc. */ | |
354 | sim_module_uninstall (sd); | |
355 | return 0; | |
356 | } | |
357 | ||
50a2a691 AC |
358 | /* verify assumptions the simulator made about the host type system. |
359 | This macro does not return if there is a problem */ | |
7ce8b917 AC |
360 | SIM_ASSERT (sizeof(int) == (4 * sizeof(char))); |
361 | SIM_ASSERT (sizeof(word64) == (8 * sizeof(char))); | |
8bae0a0c | 362 | |
8bae0a0c JSC |
363 | /* This is NASTY, in that we are assuming the size of specific |
364 | registers: */ | |
365 | { | |
366 | int rn; | |
a97f304b AC |
367 | for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) |
368 | { | |
369 | if (rn < 32) | |
370 | cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; | |
371 | else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR))) | |
372 | cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE; | |
373 | else if ((rn >= 33) && (rn <= 37)) | |
374 | cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; | |
a48e8c8d AC |
375 | else if ((rn == SRIDX) |
376 | || (rn == FCR0IDX) | |
377 | || (rn == FCR31IDX) | |
378 | || ((rn >= 72) && (rn <= 89))) | |
a97f304b AC |
379 | cpu->register_widths[rn] = 32; |
380 | else | |
381 | cpu->register_widths[rn] = 0; | |
382 | } | |
18c64df6 AC |
383 | /* start-sanitize-r5900 */ |
384 | ||
385 | /* set the 5900 "upper" registers to 64 bits */ | |
386 | for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++) | |
0c2c5f61 | 387 | cpu->register_widths[rn] = 64; |
18c64df6 | 388 | /* end-sanitize-r5900 */ |
97908603 RU |
389 | |
390 | /* start-sanitize-sky */ | |
391 | #ifdef TARGET_SKY | |
392 | /* Now the VU registers */ | |
a859684b | 393 | for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) { |
97908603 RU |
394 | cpu->register_widths[rn + NUM_R5900_REGS] = 16; |
395 | cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16; | |
396 | ||
397 | /* Hack for now - to test gdb interface */ | |
398 | vu_regs[0].i[rn] = rn + 0x100; | |
399 | vu_regs[1].i[rn] = rn + 0x200; | |
400 | } | |
401 | ||
a859684b | 402 | for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) { |
97908603 | 403 | float f; |
a859684b | 404 | int first_vec_reg = NUM_VU_INTEGER_REGS + 8; |
97908603 RU |
405 | |
406 | cpu->register_widths[rn + NUM_R5900_REGS] = 32; | |
407 | cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32; | |
408 | ||
409 | /* Hack for now - to test gdb interface */ | |
a859684b RU |
410 | if( rn < first_vec_reg ) { |
411 | f = rn - NUM_VU_INTEGER_REGS + 100.0; | |
412 | vu_regs[0].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f); | |
413 | f = rn - NUM_VU_INTEGER_REGS + 200.0; | |
414 | vu_regs[1].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f); | |
97908603 RU |
415 | } |
416 | else { | |
a859684b RU |
417 | f = (rn - first_vec_reg)/4 + (rn - first_vec_reg)%4 + 1000.0; |
418 | vu_regs[0].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f); | |
419 | f = (rn - first_vec_reg)/4 + (rn - first_vec_reg)%4 + 2000.0; | |
420 | vu_regs[1].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f); | |
97908603 RU |
421 | } |
422 | } | |
423 | #endif | |
424 | /* end-sanitize-sky */ | |
8bae0a0c JSC |
425 | } |
426 | ||
8bae0a0c | 427 | #if defined(TRACE) |
0c2c5f61 | 428 | if (STATE & simTRACE) |
18c64df6 | 429 | open_trace(sd); |
8bae0a0c JSC |
430 | #endif /* TRACE */ |
431 | ||
fafce69a AC |
432 | /* Write the monitor trap address handlers into the monitor (eeprom) |
433 | address space. This can only be done once the target endianness | |
434 | has been determined. */ | |
435 | { | |
436 | unsigned loop; | |
437 | /* Entry into the IDT monitor is via fixed address vectors, and | |
438 | not using machine instructions. To avoid clashing with use of | |
439 | the MIPS TRAP system, we place our own (simulator specific) | |
440 | "undefined" instructions into the relevant vector slots. */ | |
525d929e AC |
441 | for (loop = 0; (loop < MONITOR_SIZE); loop += 4) |
442 | { | |
443 | address_word vaddr = (MONITOR_BASE + loop); | |
444 | unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT)); | |
445 | H2T (insn); | |
446 | sim_write (sd, vaddr, (char *)&insn, sizeof (insn)); | |
447 | } | |
fafce69a AC |
448 | /* The PMON monitor uses the same address space, but rather than |
449 | branching into it the address of a routine is loaded. We can | |
450 | cheat for the moment, and direct the PMON routine to IDT style | |
451 | instructions within the monitor space. This relies on the IDT | |
452 | monitor not using the locations from 0xBFC00500 onwards as its | |
453 | entry points.*/ | |
454 | for (loop = 0; (loop < 24); loop++) | |
455 | { | |
525d929e AC |
456 | address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4)); |
457 | unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */ | |
fafce69a AC |
458 | switch (loop) |
459 | { | |
460 | case 0: /* read */ | |
461 | value = 7; | |
462 | break; | |
fafce69a AC |
463 | case 1: /* write */ |
464 | value = 8; | |
465 | break; | |
fafce69a AC |
466 | case 2: /* open */ |
467 | value = 6; | |
468 | break; | |
fafce69a AC |
469 | case 3: /* close */ |
470 | value = 10; | |
471 | break; | |
fafce69a AC |
472 | case 5: /* printf */ |
473 | value = ((0x500 - 16) / 8); /* not an IDT reason code */ | |
474 | break; | |
fafce69a AC |
475 | case 8: /* cliexit */ |
476 | value = 17; | |
477 | break; | |
fafce69a AC |
478 | case 11: /* flush_cache */ |
479 | value = 28; | |
480 | break; | |
481 | } | |
525d929e AC |
482 | /* FIXME - should monitor_base be SIM_ADDR?? */ |
483 | value = ((unsigned int)MONITOR_BASE + (value * 8)); | |
484 | H2T (value); | |
485 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); | |
fafce69a AC |
486 | |
487 | /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */ | |
488 | vaddr -= 0x300; | |
525d929e | 489 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); |
fafce69a AC |
490 | } |
491 | } | |
492 | ||
2e61a3ad | 493 | return sd; |
8bae0a0c JSC |
494 | } |
495 | ||
6429b296 JW |
496 | #if defined(TRACE) |
497 | static void | |
18c64df6 AC |
498 | open_trace(sd) |
499 | SIM_DESC sd; | |
6429b296 JW |
500 | { |
501 | tracefh = fopen(tracefile,"wb+"); | |
502 | if (tracefh == NULL) | |
503 | { | |
18c64df6 | 504 | sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile); |
6429b296 JW |
505 | tracefh = stderr; |
506 | } | |
507 | } | |
508 | #endif /* TRACE */ | |
509 | ||
8bae0a0c | 510 | void |
53b9417e DE |
511 | sim_close (sd, quitting) |
512 | SIM_DESC sd; | |
8bae0a0c JSC |
513 | int quitting; |
514 | { | |
515 | #ifdef DEBUG | |
516 | printf("DBG: sim_close: entered (quitting = %d)\n",quitting); | |
517 | #endif | |
518 | ||
8bae0a0c JSC |
519 | /* "quitting" is non-zero if we cannot hang on errors */ |
520 | ||
521 | /* Ensure that any resources allocated through the callback | |
522 | mechanism are released: */ | |
18c64df6 | 523 | sim_io_shutdown (sd); |
8bae0a0c | 524 | |
8bae0a0c | 525 | #if defined(TRACE) |
e3d12c65 | 526 | if (tracefh != NULL && tracefh != stderr) |
8bae0a0c | 527 | fclose(tracefh); |
e3d12c65 | 528 | tracefh = NULL; |
8bae0a0c JSC |
529 | #endif /* TRACE */ |
530 | ||
01737f42 AC |
531 | /* FIXME - free SD */ |
532 | ||
8bae0a0c JSC |
533 | return; |
534 | } | |
535 | ||
8bae0a0c JSC |
536 | |
537 | int | |
53b9417e DE |
538 | sim_write (sd,addr,buffer,size) |
539 | SIM_DESC sd; | |
8bae0a0c JSC |
540 | SIM_ADDR addr; |
541 | unsigned char *buffer; | |
542 | int size; | |
543 | { | |
525d929e | 544 | int index; |
01737f42 | 545 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
8bae0a0c JSC |
546 | |
547 | /* Return the number of bytes written, or zero if error. */ | |
548 | #ifdef DEBUG | |
18c64df6 | 549 | sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
550 | #endif |
551 | ||
525d929e AC |
552 | /* We use raw read and write routines, since we do not want to count |
553 | the GDB memory accesses in our statistics gathering. */ | |
554 | ||
555 | for (index = 0; index < size; index++) | |
556 | { | |
557 | address_word vaddr = (address_word)addr + index; | |
558 | address_word paddr; | |
559 | int cca; | |
01737f42 | 560 | if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW)) |
525d929e | 561 | break; |
01737f42 | 562 | if (sim_core_write_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1) |
63be8feb | 563 | break; |
8bae0a0c | 564 | } |
8bae0a0c | 565 | |
525d929e | 566 | return(index); |
8bae0a0c JSC |
567 | } |
568 | ||
569 | int | |
53b9417e DE |
570 | sim_read (sd,addr,buffer,size) |
571 | SIM_DESC sd; | |
8bae0a0c JSC |
572 | SIM_ADDR addr; |
573 | unsigned char *buffer; | |
574 | int size; | |
575 | { | |
576 | int index; | |
01737f42 | 577 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
8bae0a0c JSC |
578 | |
579 | /* Return the number of bytes read, or zero if error. */ | |
580 | #ifdef DEBUG | |
18c64df6 | 581 | sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
582 | #endif /* DEBUG */ |
583 | ||
525d929e AC |
584 | for (index = 0; (index < size); index++) |
585 | { | |
586 | address_word vaddr = (address_word)addr + index; | |
587 | address_word paddr; | |
525d929e | 588 | int cca; |
01737f42 | 589 | if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW)) |
525d929e | 590 | break; |
01737f42 | 591 | if (sim_core_read_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1) |
63be8feb | 592 | break; |
525d929e | 593 | } |
8bae0a0c JSC |
594 | |
595 | return(index); | |
596 | } | |
597 | ||
f319bab2 GRK |
598 | int |
599 | sim_store_register (sd,rn,memory,length) | |
53b9417e | 600 | SIM_DESC sd; |
8bae0a0c JSC |
601 | int rn; |
602 | unsigned char *memory; | |
f319bab2 | 603 | int length; |
8bae0a0c | 604 | { |
01737f42 | 605 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
50a2a691 AC |
606 | /* NOTE: gdb (the client) stores registers in target byte order |
607 | while the simulator uses host byte order */ | |
8bae0a0c | 608 | #ifdef DEBUG |
18c64df6 | 609 | sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory))); |
8bae0a0c JSC |
610 | #endif /* DEBUG */ |
611 | ||
612 | /* Unfortunately this suffers from the same problem as the register | |
613 | numbering one. We need to know what the width of each logical | |
614 | register number is for the architecture being simulated. */ | |
50a2a691 | 615 | |
0c2c5f61 | 616 | if (cpu->register_widths[rn] == 0) |
a48e8c8d AC |
617 | { |
618 | sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn); | |
619 | return 0; | |
620 | } | |
621 | ||
622 | /* start-sanitize-r5900 */ | |
623 | if (rn >= 90 && rn < 90 + 32) | |
624 | { | |
625 | GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory); | |
626 | return 8; | |
627 | } | |
628 | switch (rn) | |
629 | { | |
630 | case REGISTER_SA: | |
631 | SA = T2H_8(*(unsigned64*)memory); | |
632 | return 8; | |
633 | case 122: /* FIXME */ | |
634 | LO1 = T2H_8(*(unsigned64*)memory); | |
635 | return 8; | |
636 | case 123: /* FIXME */ | |
637 | HI1 = T2H_8(*(unsigned64*)memory); | |
638 | return 8; | |
639 | } | |
a48e8c8d | 640 | /* end-sanitize-r5900 */ |
ce4713dc | 641 | |
97908603 RU |
642 | /* start-sanitize-sky */ |
643 | #ifdef TARGET_SKY | |
a859684b | 644 | if (rn >= NUM_R5900_REGS) |
ce4713dc | 645 | { |
a859684b RU |
646 | int size = 4; /* Default register size */ |
647 | ||
ce4713dc | 648 | rn = rn - NUM_R5900_REGS; |
97908603 | 649 | |
a859684b RU |
650 | if (rn < NUM_VU_INTEGER_REGS) |
651 | { | |
652 | vu_regs[0].i[rn] = T2H_2( *(unsigned short *) memory ); | |
653 | size = 2; | |
654 | } | |
97908603 | 655 | else if( rn < NUM_VU_REGS ) |
a859684b RU |
656 | vu_regs[0].f[rn - NUM_VU_INTEGER_REGS] |
657 | = T2H_4( *(unsigned int *) memory ); | |
ce4713dc RU |
658 | else { |
659 | rn = rn - NUM_VU_REGS; | |
660 | ||
a859684b RU |
661 | if( rn < NUM_VU_INTEGER_REGS ) |
662 | { | |
663 | vu_regs[1].i[rn] = T2H_2( *(unsigned short *) memory ); | |
664 | size = 2; | |
665 | } | |
ce4713dc | 666 | else if( rn < NUM_VU_REGS ) |
a859684b RU |
667 | vu_regs[1].f[rn - NUM_VU_INTEGER_REGS] |
668 | = T2H_4( *(unsigned int *) memory ); | |
ce4713dc RU |
669 | else |
670 | sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" ); | |
671 | } | |
a859684b RU |
672 | |
673 | return size; | |
97908603 | 674 | } |
97908603 RU |
675 | #endif |
676 | /* end-sanitize-sky */ | |
a48e8c8d AC |
677 | |
678 | if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) | |
a97f304b AC |
679 | { |
680 | if (cpu->register_widths[rn] == 32) | |
a48e8c8d AC |
681 | { |
682 | cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory); | |
683 | return 4; | |
684 | } | |
a97f304b | 685 | else |
a48e8c8d AC |
686 | { |
687 | cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory); | |
688 | return 8; | |
689 | } | |
a97f304b | 690 | } |
8bae0a0c | 691 | |
a48e8c8d AC |
692 | if (cpu->register_widths[rn] == 32) |
693 | { | |
694 | cpu->registers[rn] = T2H_4 (*(unsigned32*)memory); | |
695 | return 4; | |
696 | } | |
697 | else | |
698 | { | |
699 | cpu->registers[rn] = T2H_8 (*(unsigned64*)memory); | |
700 | return 8; | |
701 | } | |
8bae0a0c JSC |
702 | } |
703 | ||
f319bab2 GRK |
704 | int |
705 | sim_fetch_register (sd,rn,memory,length) | |
53b9417e | 706 | SIM_DESC sd; |
8bae0a0c JSC |
707 | int rn; |
708 | unsigned char *memory; | |
f319bab2 | 709 | int length; |
8bae0a0c | 710 | { |
01737f42 | 711 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
50a2a691 AC |
712 | /* NOTE: gdb (the client) stores registers in target byte order |
713 | while the simulator uses host byte order */ | |
8bae0a0c | 714 | #ifdef DEBUG |
18c64df6 | 715 | sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn])); |
8bae0a0c JSC |
716 | #endif /* DEBUG */ |
717 | ||
0c2c5f61 | 718 | if (cpu->register_widths[rn] == 0) |
a48e8c8d AC |
719 | { |
720 | sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn); | |
721 | return 0; | |
722 | } | |
723 | ||
724 | /* start-sanitize-r5900 */ | |
725 | if (rn >= 90 && rn < 90 + 32) | |
726 | { | |
727 | *(unsigned64*)memory = GPR1[rn - 90]; | |
728 | return 8; | |
729 | } | |
730 | switch (rn) | |
731 | { | |
732 | case REGISTER_SA: | |
733 | *((unsigned64*)memory) = H2T_8(SA); | |
734 | return 8; | |
735 | case 122: /* FIXME */ | |
736 | *((unsigned64*)memory) = H2T_8(LO1); | |
737 | return 8; | |
738 | case 123: /* FIXME */ | |
739 | *((unsigned64*)memory) = H2T_8(HI1); | |
740 | return 8; | |
741 | } | |
a48e8c8d | 742 | /* end-sanitize-r5900 */ |
ce4713dc | 743 | |
97908603 RU |
744 | /* start-sanitize-sky */ |
745 | #ifdef TARGET_SKY | |
a859684b | 746 | if (rn >= NUM_R5900_REGS) |
ce4713dc | 747 | { |
a859684b RU |
748 | int size = 4; /* default register width */ |
749 | ||
ce4713dc | 750 | rn = rn - NUM_R5900_REGS; |
97908603 | 751 | |
a859684b RU |
752 | if (rn < NUM_VU_INTEGER_REGS) |
753 | { | |
754 | *((unsigned short *) memory) = H2T_2( vu_regs[0].i[rn] ); | |
755 | size = 2; | |
756 | } | |
757 | else if (rn < NUM_VU_REGS) | |
758 | *((unsigned int *) memory) | |
759 | = H2T_4( vu_regs[0].f[rn - NUM_VU_INTEGER_REGS] ); | |
760 | else | |
761 | { | |
762 | rn = rn - NUM_VU_REGS; | |
ce4713dc | 763 | |
a859684b RU |
764 | if (rn < NUM_VU_INTEGER_REGS) |
765 | { | |
766 | (*(unsigned short *) memory) = H2T_2( vu_regs[1].i[rn] ); | |
767 | size = 2; | |
768 | } | |
769 | else if (rn < NUM_VU_REGS) | |
770 | (*(unsigned int *) memory) | |
771 | = H2T_4( vu_regs[1].f[rn - NUM_VU_INTEGER_REGS] ); | |
772 | else | |
773 | sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" ); | |
774 | } | |
775 | ||
776 | return size; | |
97908603 | 777 | } |
97908603 RU |
778 | #endif |
779 | /* end-sanitize-sky */ | |
a48e8c8d AC |
780 | |
781 | /* Any floating point register */ | |
782 | if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) | |
a97f304b AC |
783 | { |
784 | if (cpu->register_widths[rn] == 32) | |
a48e8c8d AC |
785 | { |
786 | *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]); | |
787 | return 4; | |
788 | } | |
a97f304b | 789 | else |
a48e8c8d AC |
790 | { |
791 | *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]); | |
792 | return 8; | |
793 | } | |
a97f304b | 794 | } |
50a2a691 | 795 | |
a48e8c8d AC |
796 | if (cpu->register_widths[rn] == 32) |
797 | { | |
798 | *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn])); | |
799 | return 4; | |
800 | } | |
801 | else | |
802 | { | |
803 | *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn])); | |
804 | return 8; | |
805 | } | |
8bae0a0c | 806 | } |
50a2a691 | 807 | |
8bae0a0c | 808 | |
9d52bcb7 | 809 | SIM_RC |
fafce69a | 810 | sim_create_inferior (sd, abfd, argv,env) |
53b9417e | 811 | SIM_DESC sd; |
fafce69a | 812 | struct _bfd *abfd; |
8bae0a0c JSC |
813 | char **argv; |
814 | char **env; | |
815 | { | |
50a2a691 | 816 | |
8bae0a0c | 817 | #ifdef DEBUG |
9d52bcb7 DE |
818 | printf("DBG: sim_create_inferior entered: start_address = 0x%s\n", |
819 | pr_addr(PC)); | |
8bae0a0c JSC |
820 | #endif /* DEBUG */ |
821 | ||
0c2c5f61 | 822 | ColdReset(sd); |
50a2a691 | 823 | |
fafce69a | 824 | if (abfd != NULL) |
01737f42 AC |
825 | { |
826 | /* override PC value set by ColdReset () */ | |
827 | int cpu_nr; | |
828 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) | |
829 | { | |
830 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); | |
831 | CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd)); | |
832 | } | |
833 | } | |
2e61a3ad | 834 | |
f24b7b69 | 835 | #if 0 /* def DEBUG */ |
dad6f1f3 | 836 | if (argv || env) |
8bae0a0c | 837 | { |
dad6f1f3 AC |
838 | /* We should really place the argv slot values into the argument |
839 | registers, and onto the stack as required. However, this | |
840 | assumes that we have a stack defined, which is not | |
841 | necessarily true at the moment. */ | |
842 | char **cptr; | |
843 | sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n"); | |
844 | for (cptr = argv; (cptr && *cptr); cptr++) | |
845 | printf("DBG: arg \"%s\"\n",*cptr); | |
8bae0a0c JSC |
846 | } |
847 | #endif /* DEBUG */ | |
8bae0a0c | 848 | |
9d52bcb7 | 849 | return SIM_RC_OK; |
8bae0a0c JSC |
850 | } |
851 | ||
8bae0a0c | 852 | void |
53b9417e DE |
853 | sim_do_command (sd,cmd) |
854 | SIM_DESC sd; | |
8bae0a0c JSC |
855 | char *cmd; |
856 | { | |
63be8feb AC |
857 | if (sim_args_command (sd, cmd) != SIM_RC_OK) |
858 | sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n", | |
859 | cmd); | |
8bae0a0c JSC |
860 | } |
861 | ||
8bae0a0c JSC |
862 | /*---------------------------------------------------------------------------*/ |
863 | /*-- Private simulator support interface ------------------------------------*/ | |
864 | /*---------------------------------------------------------------------------*/ | |
865 | ||
525d929e AC |
866 | /* Read a null terminated string from memory, return in a buffer */ |
867 | static char * | |
868 | fetch_str (sd, addr) | |
869 | SIM_DESC sd; | |
870 | address_word addr; | |
871 | { | |
872 | char *buf; | |
873 | int nr = 0; | |
874 | char null; | |
875 | while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0) | |
876 | nr++; | |
877 | buf = NZALLOC (char, nr + 1); | |
878 | sim_read (sd, addr, buf, nr); | |
879 | return buf; | |
880 | } | |
881 | ||
a9f7253f | 882 | /* Simple monitor interface (currently setup for the IDT and PMON monitors) */ |
8bae0a0c | 883 | static void |
01737f42 AC |
884 | sim_monitor (SIM_DESC sd, |
885 | sim_cpu *cpu, | |
886 | address_word cia, | |
887 | unsigned int reason) | |
8bae0a0c | 888 | { |
53b9417e DE |
889 | #ifdef DEBUG |
890 | printf("DBG: sim_monitor: entered (reason = %d)\n",reason); | |
891 | #endif /* DEBUG */ | |
892 | ||
8bae0a0c JSC |
893 | /* The IDT monitor actually allows two instructions per vector |
894 | slot. However, the simulator currently causes a trap on each | |
895 | individual instruction. We cheat, and lose the bottom bit. */ | |
896 | reason >>= 1; | |
897 | ||
898 | /* The following callback functions are available, however the | |
899 | monitor we are simulating does not make use of them: get_errno, | |
900 | isatty, lseek, rename, system, time and unlink */ | |
525d929e AC |
901 | switch (reason) |
902 | { | |
903 | ||
8bae0a0c JSC |
904 | case 6: /* int open(char *path,int flags) */ |
905 | { | |
525d929e AC |
906 | char *path = fetch_str (sd, A0); |
907 | V0 = sim_io_open (sd, path, (int)A1); | |
908 | zfree (path); | |
909 | break; | |
8bae0a0c | 910 | } |
8bae0a0c JSC |
911 | |
912 | case 7: /* int read(int file,char *ptr,int len) */ | |
913 | { | |
525d929e AC |
914 | int fd = A0; |
915 | int nr = A2; | |
916 | char *buf = zalloc (nr); | |
917 | V0 = sim_io_read (sd, fd, buf, nr); | |
918 | sim_write (sd, A1, buf, nr); | |
919 | zfree (buf); | |
8bae0a0c JSC |
920 | } |
921 | break; | |
922 | ||
923 | case 8: /* int write(int file,char *ptr,int len) */ | |
924 | { | |
525d929e AC |
925 | int fd = A0; |
926 | int nr = A2; | |
927 | char *buf = zalloc (nr); | |
928 | sim_read (sd, A1, buf, nr); | |
929 | V0 = sim_io_write (sd, fd, buf, nr); | |
930 | zfree (buf); | |
931 | break; | |
8bae0a0c | 932 | } |
8bae0a0c JSC |
933 | |
934 | case 10: /* int close(int file) */ | |
525d929e AC |
935 | { |
936 | V0 = sim_io_close (sd, (int)A0); | |
937 | break; | |
938 | } | |
8bae0a0c | 939 | |
e0e0fc76 MA |
940 | case 2: /* Densan monitor: char inbyte(int waitflag) */ |
941 | { | |
942 | if (A0 == 0) /* waitflag == NOWAIT */ | |
192ae475 | 943 | V0 = (unsigned_word)-1; |
e0e0fc76 MA |
944 | } |
945 | /* Drop through to case 11 */ | |
946 | ||
8bae0a0c JSC |
947 | case 11: /* char inbyte(void) */ |
948 | { | |
949 | char tmp; | |
525d929e AC |
950 | if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char)) |
951 | { | |
952 | sim_io_error(sd,"Invalid return from character read"); | |
192ae475 | 953 | V0 = (unsigned_word)-1; |
525d929e | 954 | } |
8bae0a0c | 955 | else |
192ae475 | 956 | V0 = (unsigned_word)tmp; |
525d929e | 957 | break; |
8bae0a0c | 958 | } |
8bae0a0c | 959 | |
e0e0fc76 | 960 | case 3: /* Densan monitor: void co(char chr) */ |
8bae0a0c JSC |
961 | case 12: /* void outbyte(char chr) : write a byte to "stdout" */ |
962 | { | |
963 | char tmp = (char)(A0 & 0xFF); | |
525d929e AC |
964 | sim_io_write_stdout (sd, &tmp, sizeof(char)); |
965 | break; | |
8bae0a0c | 966 | } |
8bae0a0c JSC |
967 | |
968 | case 17: /* void _exit() */ | |
525d929e AC |
969 | { |
970 | sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n"); | |
01737f42 | 971 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited, |
525d929e AC |
972 | (unsigned int)(A0 & 0xFFFFFFFF)); |
973 | break; | |
974 | } | |
8bae0a0c | 975 | |
280f90e1 AMT |
976 | case 28 : /* PMON flush_cache */ |
977 | break; | |
978 | ||
8bae0a0c JSC |
979 | case 55: /* void get_mem_info(unsigned int *ptr) */ |
980 | /* in: A0 = pointer to three word memory location */ | |
981 | /* out: [A0 + 0] = size */ | |
982 | /* [A0 + 4] = instruction cache size */ | |
983 | /* [A0 + 8] = data cache size */ | |
984 | { | |
525d929e AC |
985 | address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */; |
986 | H2T (value); | |
987 | sim_write (sd, A0, (char *)&value, sizeof (value)); | |
030843d7 | 988 | /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */ |
525d929e | 989 | break; |
8bae0a0c | 990 | } |
525d929e | 991 | |
a9f7253f JSC |
992 | case 158 : /* PMON printf */ |
993 | /* in: A0 = pointer to format string */ | |
994 | /* A1 = optional argument 1 */ | |
995 | /* A2 = optional argument 2 */ | |
996 | /* A3 = optional argument 3 */ | |
997 | /* out: void */ | |
f24b7b69 | 998 | /* The following is based on the PMON printf source */ |
a9f7253f | 999 | { |
525d929e AC |
1000 | address_word s = A0; |
1001 | char c; | |
1002 | signed_word *ap = &A1; /* 1st argument */ | |
f24b7b69 JSC |
1003 | /* This isn't the quickest way, since we call the host print |
1004 | routine for every character almost. But it does avoid | |
1005 | having to allocate and manage a temporary string buffer. */ | |
525d929e AC |
1006 | /* TODO: Include check that we only use three arguments (A1, |
1007 | A2 and A3) */ | |
1008 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
1009 | { | |
1010 | if (c == '%') | |
1011 | { | |
1012 | char tmp[40]; | |
1013 | enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST; | |
1014 | int width = 0, trunc = 0, haddot = 0, longlong = 0; | |
1015 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
1016 | { | |
1017 | if (strchr ("dobxXulscefg%", s)) | |
1018 | break; | |
1019 | else if (c == '-') | |
1020 | fmt = FMT_LJUST; | |
1021 | else if (c == '0') | |
1022 | fmt = FMT_RJUST0; | |
1023 | else if (c == '~') | |
1024 | fmt = FMT_CENTER; | |
1025 | else if (c == '*') | |
1026 | { | |
1027 | if (haddot) | |
1028 | trunc = (int)*ap++; | |
1029 | else | |
1030 | width = (int)*ap++; | |
1031 | } | |
1032 | else if (c >= '1' && c <= '9') | |
1033 | { | |
1034 | address_word t = s; | |
1035 | unsigned int n; | |
1036 | while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c)) | |
1037 | tmp[s - t] = c; | |
1038 | tmp[s - t] = '\0'; | |
1039 | n = (unsigned int)strtol(tmp,NULL,10); | |
1040 | if (haddot) | |
1041 | trunc = n; | |
1042 | else | |
1043 | width = n; | |
1044 | s--; | |
1045 | } | |
1046 | else if (c == '.') | |
1047 | haddot = 1; | |
1048 | } | |
1049 | switch (c) | |
1050 | { | |
1051 | case '%': | |
1052 | sim_io_printf (sd, "%%"); | |
1053 | break; | |
1054 | case 's': | |
1055 | if ((int)*ap != 0) | |
1056 | { | |
1057 | address_word p = *ap++; | |
1058 | char ch; | |
1059 | while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0') | |
1060 | sim_io_printf(sd, "%c", ch); | |
1061 | } | |
1062 | else | |
1063 | sim_io_printf(sd,"(null)"); | |
1064 | break; | |
1065 | case 'c': | |
1066 | sim_io_printf (sd, "%c", (int)*ap++); | |
1067 | break; | |
1068 | default: | |
1069 | if (c == 'l') | |
1070 | { | |
1071 | sim_read (sd, s++, &c, 1); | |
1072 | if (c == 'l') | |
1073 | { | |
1074 | longlong = 1; | |
1075 | sim_read (sd, s++, &c, 1); | |
1076 | } | |
1077 | } | |
1078 | if (strchr ("dobxXu", c)) | |
1079 | { | |
1080 | word64 lv = (word64) *ap++; | |
1081 | if (c == 'b') | |
1082 | sim_io_printf(sd,"<binary not supported>"); | |
1083 | else | |
1084 | { | |
1085 | sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c); | |
1086 | if (longlong) | |
1087 | sim_io_printf(sd, tmp, lv); | |
1088 | else | |
1089 | sim_io_printf(sd, tmp, (int)lv); | |
1090 | } | |
1091 | } | |
1092 | else if (strchr ("eEfgG", c)) | |
1093 | { | |
1094 | double dbl = *(double*)(ap++); | |
1095 | sprintf (tmp, "%%%d.%d%c", width, trunc, c); | |
1096 | sim_io_printf (sd, tmp, dbl); | |
1097 | trunc = 0; | |
1098 | } | |
1099 | } | |
1100 | } | |
1101 | else | |
1102 | sim_io_printf(sd, "%c", c); | |
1103 | } | |
1104 | break; | |
a9f7253f | 1105 | } |
a9f7253f | 1106 | |
8bae0a0c | 1107 | default: |
525d929e | 1108 | sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n", |
95469ceb | 1109 | reason, pr_addr(cia)); |
8bae0a0c JSC |
1110 | break; |
1111 | } | |
1112 | return; | |
1113 | } | |
1114 | ||
7e6c297e ILT |
1115 | /* Store a word into memory. */ |
1116 | ||
1117 | static void | |
01737f42 AC |
1118 | store_word (SIM_DESC sd, |
1119 | sim_cpu *cpu, | |
1120 | address_word cia, | |
1121 | uword64 vaddr, | |
192ae475 | 1122 | signed_word val) |
7e6c297e | 1123 | { |
dad6f1f3 | 1124 | address_word paddr; |
7e6c297e ILT |
1125 | int uncached; |
1126 | ||
1127 | if ((vaddr & 3) != 0) | |
18c64df6 | 1128 | SignalExceptionAddressStore (); |
7e6c297e ILT |
1129 | else |
1130 | { | |
1131 | if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, | |
1132 | isTARGET, isREAL)) | |
1133 | { | |
1134 | const uword64 mask = 7; | |
1135 | uword64 memval; | |
1136 | unsigned int byte; | |
1137 | ||
1138 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)); | |
1139 | byte = (vaddr & mask) ^ (BigEndianCPU << 2); | |
1140 | memval = ((uword64) val) << (8 * byte); | |
53b9417e | 1141 | StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, |
7e6c297e ILT |
1142 | isREAL); |
1143 | } | |
1144 | } | |
1145 | } | |
1146 | ||
1147 | /* Load a word from memory. */ | |
1148 | ||
192ae475 | 1149 | static signed_word |
01737f42 AC |
1150 | load_word (SIM_DESC sd, |
1151 | sim_cpu *cpu, | |
1152 | address_word cia, | |
1153 | uword64 vaddr) | |
7e6c297e ILT |
1154 | { |
1155 | if ((vaddr & 3) != 0) | |
18c64df6 | 1156 | SignalExceptionAddressLoad (); |
7e6c297e ILT |
1157 | else |
1158 | { | |
dad6f1f3 | 1159 | address_word paddr; |
7e6c297e ILT |
1160 | int uncached; |
1161 | ||
1162 | if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, | |
1163 | isTARGET, isREAL)) | |
1164 | { | |
1165 | const uword64 mask = 0x7; | |
1166 | const unsigned int reverse = ReverseEndian ? 1 : 0; | |
1167 | const unsigned int bigend = BigEndianCPU ? 1 : 0; | |
1168 | uword64 memval; | |
1169 | unsigned int byte; | |
1170 | ||
1171 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2)); | |
53b9417e | 1172 | LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr, |
7e6c297e ILT |
1173 | isDATA, isREAL); |
1174 | byte = (vaddr & mask) ^ (bigend << 2); | |
1175 | return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32); | |
1176 | } | |
1177 | } | |
1178 | ||
1179 | return 0; | |
1180 | } | |
1181 | ||
1182 | /* Simulate the mips16 entry and exit pseudo-instructions. These | |
1183 | would normally be handled by the reserved instruction exception | |
1184 | code, but for ease of simulation we just handle them directly. */ | |
1185 | ||
1186 | static void | |
01737f42 AC |
1187 | mips16_entry (SIM_DESC sd, |
1188 | sim_cpu *cpu, | |
1189 | address_word cia, | |
1190 | unsigned int insn) | |
7e6c297e ILT |
1191 | { |
1192 | int aregs, sregs, rreg; | |
1193 | ||
53b9417e DE |
1194 | #ifdef DEBUG |
1195 | printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn); | |
1196 | #endif /* DEBUG */ | |
1197 | ||
7e6c297e ILT |
1198 | aregs = (insn & 0x700) >> 8; |
1199 | sregs = (insn & 0x0c0) >> 6; | |
1200 | rreg = (insn & 0x020) >> 5; | |
1201 | ||
da0bce9c ILT |
1202 | /* This should be checked by the caller. */ |
1203 | if (sregs == 3) | |
7e6c297e ILT |
1204 | abort (); |
1205 | ||
da0bce9c | 1206 | if (aregs < 5) |
7e6c297e ILT |
1207 | { |
1208 | int i; | |
192ae475 | 1209 | signed_word tsp; |
7e6c297e ILT |
1210 | |
1211 | /* This is the entry pseudo-instruction. */ | |
1212 | ||
1213 | for (i = 0; i < aregs; i++) | |
01737f42 | 1214 | store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]); |
7e6c297e ILT |
1215 | |
1216 | tsp = SP; | |
1217 | SP -= 32; | |
1218 | ||
1219 | if (rreg) | |
1220 | { | |
1221 | tsp -= 4; | |
01737f42 | 1222 | store_word (SD, CPU, cia, (uword64) tsp, RA); |
7e6c297e ILT |
1223 | } |
1224 | ||
1225 | for (i = 0; i < sregs; i++) | |
1226 | { | |
1227 | tsp -= 4; | |
01737f42 | 1228 | store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]); |
7e6c297e ILT |
1229 | } |
1230 | } | |
1231 | else | |
1232 | { | |
1233 | int i; | |
192ae475 | 1234 | signed_word tsp; |
7e6c297e ILT |
1235 | |
1236 | /* This is the exit pseudo-instruction. */ | |
1237 | ||
1238 | tsp = SP + 32; | |
1239 | ||
1240 | if (rreg) | |
1241 | { | |
1242 | tsp -= 4; | |
01737f42 | 1243 | RA = load_word (SD, CPU, cia, (uword64) tsp); |
7e6c297e ILT |
1244 | } |
1245 | ||
1246 | for (i = 0; i < sregs; i++) | |
1247 | { | |
1248 | tsp -= 4; | |
01737f42 | 1249 | GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp); |
7e6c297e ILT |
1250 | } |
1251 | ||
1252 | SP += 32; | |
1253 | ||
192ae475 | 1254 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
da0bce9c | 1255 | { |
192ae475 AC |
1256 | if (aregs == 5) |
1257 | { | |
1258 | FGR[0] = WORD64LO (GPR[4]); | |
1259 | FPR_STATE[0] = fmt_uninterpreted; | |
1260 | } | |
1261 | else if (aregs == 6) | |
1262 | { | |
1263 | FGR[0] = WORD64LO (GPR[5]); | |
1264 | FGR[1] = WORD64LO (GPR[4]); | |
1265 | FPR_STATE[0] = fmt_uninterpreted; | |
1266 | FPR_STATE[1] = fmt_uninterpreted; | |
1267 | } | |
1268 | } | |
da0bce9c | 1269 | |
7e6c297e ILT |
1270 | PC = RA; |
1271 | } | |
192ae475 | 1272 | |
7e6c297e ILT |
1273 | } |
1274 | ||
8bae0a0c JSC |
1275 | /*-- trace support ----------------------------------------------------------*/ |
1276 | ||
1277 | /* The TRACE support is provided (if required) in the memory accessing | |
1278 | routines. Since we are also providing the architecture specific | |
1279 | features, the architecture simulation code can also deal with | |
1280 | notifying the TRACE world of cache flushes, etc. Similarly we do | |
1281 | not need to provide profiling support in the simulator engine, | |
1282 | since we can sample in the instruction fetch control loop. By | |
1283 | defining the TRACE manifest, we add tracing as a run-time | |
1284 | option. */ | |
1285 | ||
1286 | #if defined(TRACE) | |
1287 | /* Tracing by default produces "din" format (as required by | |
1288 | dineroIII). Each line of such a trace file *MUST* have a din label | |
1289 | and address field. The rest of the line is ignored, so comments can | |
1290 | be included if desired. The first field is the label which must be | |
1291 | one of the following values: | |
1292 | ||
1293 | 0 read data | |
1294 | 1 write data | |
1295 | 2 instruction fetch | |
1296 | 3 escape record (treated as unknown access type) | |
1297 | 4 escape record (causes cache flush) | |
1298 | ||
1299 | The address field is a 32bit (lower-case) hexadecimal address | |
1300 | value. The address should *NOT* be preceded by "0x". | |
1301 | ||
1302 | The size of the memory transfer is not important when dealing with | |
1303 | cache lines (as long as no more than a cache line can be | |
1304 | transferred in a single operation :-), however more information | |
1305 | could be given following the dineroIII requirement to allow more | |
1306 | complete memory and cache simulators to provide better | |
1307 | results. i.e. the University of Pisa has a cache simulator that can | |
1308 | also take bus size and speed as (variable) inputs to calculate | |
1309 | complete system performance (a much more useful ability when trying | |
1310 | to construct an end product, rather than a processor). They | |
1311 | currently have an ARM version of their tool called ChARM. */ | |
1312 | ||
e3d12c65 | 1313 | |
030843d7 | 1314 | void |
01737f42 AC |
1315 | dotrace (SIM_DESC sd, |
1316 | sim_cpu *cpu, | |
1317 | FILE *tracefh, | |
1318 | int type, | |
1319 | SIM_ADDR address, | |
1320 | int width, | |
1321 | char *comment,...) | |
8bae0a0c | 1322 | { |
0c2c5f61 | 1323 | if (STATE & simTRACE) { |
8bae0a0c | 1324 | va_list ap; |
53b9417e | 1325 | fprintf(tracefh,"%d %s ; width %d ; ", |
6429b296 | 1326 | type, |
53b9417e DE |
1327 | pr_addr(address), |
1328 | width); | |
8bae0a0c | 1329 | va_start(ap,comment); |
6429b296 | 1330 | vfprintf(tracefh,comment,ap); |
8bae0a0c JSC |
1331 | va_end(ap); |
1332 | fprintf(tracefh,"\n"); | |
1333 | } | |
1334 | /* NOTE: Since the "din" format will only accept 32bit addresses, and | |
1335 | we may be generating 64bit ones, we should put the hi-32bits of the | |
1336 | address into the comment field. */ | |
1337 | ||
1338 | /* TODO: Provide a buffer for the trace lines. We can then avoid | |
1339 | performing writes until the buffer is filled, or the file is | |
1340 | being closed. */ | |
1341 | ||
1342 | /* NOTE: We could consider adding a comment field to the "din" file | |
1343 | produced using type 3 markers (unknown access). This would then | |
1344 | allow information about the program that the "din" is for, and | |
1345 | the MIPs world that was being simulated, to be placed into the | |
1346 | trace file. */ | |
1347 | ||
1348 | return; | |
1349 | } | |
1350 | #endif /* TRACE */ | |
1351 | ||
1352 | /*---------------------------------------------------------------------------*/ | |
1353 | /*-- simulator engine -------------------------------------------------------*/ | |
1354 | /*---------------------------------------------------------------------------*/ | |
1355 | ||
1356 | static void | |
01737f42 | 1357 | ColdReset (SIM_DESC sd) |
8bae0a0c | 1358 | { |
01737f42 AC |
1359 | int cpu_nr; |
1360 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) | |
dad6f1f3 | 1361 | { |
01737f42 AC |
1362 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); |
1363 | /* RESET: Fixed PC address: */ | |
1364 | PC = UNSIGNED64 (0xFFFFFFFFBFC00000); | |
1365 | /* The reset vector address is in the unmapped, uncached memory space. */ | |
1366 | ||
1367 | SR &= ~(status_SR | status_TS | status_RP); | |
1368 | SR |= (status_ERL | status_BEV); | |
1369 | ||
1370 | /* Cheat and allow access to the complete register set immediately */ | |
1371 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT | |
1372 | && WITH_TARGET_WORD_BITSIZE == 64) | |
1373 | SR |= status_FR; /* 64bit registers */ | |
1374 | ||
1375 | /* Ensure that any instructions with pending register updates are | |
1376 | cleared: */ | |
2acd126a | 1377 | PENDING_INVALIDATE(); |
01737f42 AC |
1378 | |
1379 | /* Initialise the FPU registers to the unknown state */ | |
1380 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) | |
1381 | { | |
1382 | int rn; | |
1383 | for (rn = 0; (rn < 32); rn++) | |
1384 | FPR_STATE[rn] = fmt_uninterpreted; | |
1385 | } | |
1386 | ||
dad6f1f3 | 1387 | } |
8bae0a0c JSC |
1388 | } |
1389 | ||
dad6f1f3 AC |
1390 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual |
1391 | (revision 3.1) */ | |
8bae0a0c JSC |
1392 | /* Translate a virtual address to a physical address and cache |
1393 | coherence algorithm describing the mechanism used to resolve the | |
1394 | memory reference. Given the virtual address vAddr, and whether the | |
1395 | reference is to Instructions ot Data (IorD), find the corresponding | |
1396 | physical address (pAddr) and the cache coherence algorithm (CCA) | |
1397 | used to resolve the reference. If the virtual address is in one of | |
1398 | the unmapped address spaces the physical address and the CCA are | |
1399 | determined directly by the virtual address. If the virtual address | |
1400 | is in one of the mapped address spaces then the TLB is used to | |
1401 | determine the physical address and access type; if the required | |
1402 | translation is not present in the TLB or the desired access is not | |
1403 | permitted the function fails and an exception is taken. | |
1404 | ||
dad6f1f3 AC |
1405 | NOTE: Normally (RAW == 0), when address translation fails, this |
1406 | function raises an exception and does not return. */ | |
8bae0a0c | 1407 | |
18c64df6 | 1408 | int |
01737f42 AC |
1409 | address_translation (SIM_DESC sd, |
1410 | sim_cpu *cpu, | |
1411 | address_word cia, | |
1412 | address_word vAddr, | |
1413 | int IorD, | |
1414 | int LorS, | |
1415 | address_word *pAddr, | |
1416 | int *CCA, | |
1417 | int raw) | |
8bae0a0c JSC |
1418 | { |
1419 | int res = -1; /* TRUE : Assume good return */ | |
1420 | ||
1421 | #ifdef DEBUG | |
18c64df6 | 1422 | sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD")); |
8bae0a0c JSC |
1423 | #endif |
1424 | ||
1425 | /* Check that the address is valid for this memory model */ | |
1426 | ||
1427 | /* For a simple (flat) memory model, we simply pass virtual | |
1428 | addressess through (mostly) unchanged. */ | |
1429 | vAddr &= 0xFFFFFFFF; | |
a9f7253f | 1430 | |
8bae0a0c JSC |
1431 | *pAddr = vAddr; /* default for isTARGET */ |
1432 | *CCA = Uncached; /* not used for isHOST */ | |
1433 | ||
8bae0a0c JSC |
1434 | return(res); |
1435 | } | |
1436 | ||
63be8feb AC |
1437 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual |
1438 | (revision 3.1) */ | |
8bae0a0c JSC |
1439 | /* Prefetch data from memory. Prefetch is an advisory instruction for |
1440 | which an implementation specific action is taken. The action taken | |
1441 | may increase performance, but must not change the meaning of the | |
1442 | program, or alter architecturally-visible state. */ | |
50a2a691 | 1443 | |
ea985d24 | 1444 | void |
01737f42 AC |
1445 | prefetch (SIM_DESC sd, |
1446 | sim_cpu *cpu, | |
1447 | address_word cia, | |
1448 | int CCA, | |
1449 | address_word pAddr, | |
1450 | address_word vAddr, | |
1451 | int DATA, | |
1452 | int hint) | |
8bae0a0c JSC |
1453 | { |
1454 | #ifdef DEBUG | |
18c64df6 | 1455 | sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint); |
8bae0a0c JSC |
1456 | #endif /* DEBUG */ |
1457 | ||
1458 | /* For our simple memory model we do nothing */ | |
1459 | return; | |
1460 | } | |
1461 | ||
63be8feb AC |
1462 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual |
1463 | (revision 3.1) */ | |
8bae0a0c JSC |
1464 | /* Load a value from memory. Use the cache and main memory as |
1465 | specified in the Cache Coherence Algorithm (CCA) and the sort of | |
1466 | access (IorD) to find the contents of AccessLength memory bytes | |
1467 | starting at physical location pAddr. The data is returned in the | |
1468 | fixed width naturally-aligned memory element (MemElem). The | |
1469 | low-order two (or three) bits of the address and the AccessLength | |
1470 | indicate which of the bytes within MemElem needs to be given to the | |
1471 | processor. If the memory access type of the reference is uncached | |
1472 | then only the referenced bytes are read from memory and valid | |
1473 | within the memory element. If the access type is cached, and the | |
1474 | data is not present in cache, an implementation specific size and | |
1475 | alignment block of memory is read and loaded into the cache to | |
1476 | satisfy a load reference. At a minimum, the block is the entire | |
1477 | memory element. */ | |
18c64df6 | 1478 | void |
01737f42 AC |
1479 | load_memory (SIM_DESC sd, |
1480 | sim_cpu *cpu, | |
1481 | address_word cia, | |
1482 | uword64* memvalp, | |
1483 | uword64* memval1p, | |
1484 | int CCA, | |
1485 | int AccessLength, | |
1486 | address_word pAddr, | |
1487 | address_word vAddr, | |
1488 | int IorD) | |
8bae0a0c | 1489 | { |
50a2a691 AC |
1490 | uword64 value = 0; |
1491 | uword64 value1 = 0; | |
8bae0a0c JSC |
1492 | |
1493 | #ifdef DEBUG | |
63be8feb | 1494 | sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION")); |
8bae0a0c JSC |
1495 | #endif /* DEBUG */ |
1496 | ||
1497 | #if defined(WARN_MEM) | |
1498 | if (CCA != uncached) | |
63be8feb | 1499 | sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); |
8bae0a0c JSC |
1500 | #endif /* WARN_MEM */ |
1501 | ||
8bae0a0c JSC |
1502 | /* If instruction fetch then we need to check that the two lo-order |
1503 | bits are zero, otherwise raise a InstructionFetch exception: */ | |
6429b296 JW |
1504 | if ((IorD == isINSTRUCTION) |
1505 | && ((pAddr & 0x3) != 0) | |
1506 | && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0))) | |
63be8feb AC |
1507 | SignalExceptionInstructionFetch (); |
1508 | ||
1509 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
1510 | { | |
1511 | /* In reality this should be a Bus Error */ | |
1512 | sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n", | |
1513 | AccessLength, | |
1514 | (LOADDRMASK + 1) << 2, | |
1515 | pr_addr (pAddr)); | |
1516 | } | |
8bae0a0c | 1517 | |
8bae0a0c | 1518 | #if defined(TRACE) |
01737f42 | 1519 | dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); |
8bae0a0c | 1520 | #endif /* TRACE */ |
63be8feb AC |
1521 | |
1522 | /* Read the specified number of bytes from memory. Adjust for | |
1523 | host/target byte ordering/ Align the least significant byte | |
1524 | read. */ | |
8bae0a0c | 1525 | |
63be8feb AC |
1526 | switch (AccessLength) |
1527 | { | |
1528 | case AccessLength_QUADWORD : | |
1529 | { | |
01737f42 | 1530 | unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA, |
63be8feb AC |
1531 | sim_core_read_map, pAddr); |
1532 | value1 = VH8_16 (val); | |
1533 | value = VL8_16 (val); | |
1534 | break; | |
8bae0a0c | 1535 | } |
63be8feb | 1536 | case AccessLength_DOUBLEWORD : |
01737f42 | 1537 | value = sim_core_read_aligned_8 (cpu, NULL_CIA, |
63be8feb AC |
1538 | sim_core_read_map, pAddr); |
1539 | break; | |
1540 | case AccessLength_SEPTIBYTE : | |
01737f42 | 1541 | value = sim_core_read_misaligned_7 (cpu, NULL_CIA, |
63be8feb | 1542 | sim_core_read_map, pAddr); |
f319bab2 | 1543 | break; |
63be8feb | 1544 | case AccessLength_SEXTIBYTE : |
01737f42 | 1545 | value = sim_core_read_misaligned_6 (cpu, NULL_CIA, |
63be8feb | 1546 | sim_core_read_map, pAddr); |
f319bab2 | 1547 | break; |
63be8feb | 1548 | case AccessLength_QUINTIBYTE : |
01737f42 | 1549 | value = sim_core_read_misaligned_5 (cpu, NULL_CIA, |
63be8feb | 1550 | sim_core_read_map, pAddr); |
f319bab2 | 1551 | break; |
63be8feb | 1552 | case AccessLength_WORD : |
01737f42 | 1553 | value = sim_core_read_aligned_4 (cpu, NULL_CIA, |
63be8feb AC |
1554 | sim_core_read_map, pAddr); |
1555 | break; | |
1556 | case AccessLength_TRIPLEBYTE : | |
01737f42 | 1557 | value = sim_core_read_misaligned_3 (cpu, NULL_CIA, |
63be8feb | 1558 | sim_core_read_map, pAddr); |
f319bab2 | 1559 | break; |
63be8feb | 1560 | case AccessLength_HALFWORD : |
01737f42 | 1561 | value = sim_core_read_aligned_2 (cpu, NULL_CIA, |
63be8feb AC |
1562 | sim_core_read_map, pAddr); |
1563 | break; | |
1564 | case AccessLength_BYTE : | |
01737f42 | 1565 | value = sim_core_read_aligned_1 (cpu, NULL_CIA, |
63be8feb AC |
1566 | sim_core_read_map, pAddr); |
1567 | break; | |
1568 | default: | |
1569 | abort (); | |
1570 | } | |
1571 | ||
8bae0a0c | 1572 | #ifdef DEBUG |
63be8feb AC |
1573 | printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n", |
1574 | (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value)); | |
8bae0a0c | 1575 | #endif /* DEBUG */ |
63be8feb AC |
1576 | |
1577 | /* See also store_memory. */ | |
1578 | if (AccessLength <= AccessLength_DOUBLEWORD) | |
1579 | { | |
1580 | if (BigEndianMem) | |
1581 | /* for big endian target, byte (pAddr&LOADDRMASK == 0) is | |
1582 | shifted to the most significant byte position. */ | |
1583 | value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
1584 | else | |
1585 | /* For little endian target, byte (pAddr&LOADDRMASK == 0) | |
1586 | is already in the correct postition. */ | |
1587 | value <<= ((pAddr & LOADDRMASK) * 8); | |
1588 | } | |
1589 | ||
8bae0a0c | 1590 | #ifdef DEBUG |
63be8feb AC |
1591 | printf("DBG: LoadMemory() : shifted value = 0x%s%s\n", |
1592 | pr_uword64(value1),pr_uword64(value)); | |
e871dd18 | 1593 | #endif /* DEBUG */ |
63be8feb | 1594 | |
525d929e AC |
1595 | *memvalp = value; |
1596 | if (memval1p) *memval1p = value1; | |
8bae0a0c JSC |
1597 | } |
1598 | ||
53b9417e | 1599 | |
50a2a691 AC |
1600 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual |
1601 | (revision 3.1) */ | |
8bae0a0c JSC |
1602 | /* Store a value to memory. The specified data is stored into the |
1603 | physical location pAddr using the memory hierarchy (data caches and | |
1604 | main memory) as specified by the Cache Coherence Algorithm | |
1605 | (CCA). The MemElem contains the data for an aligned, fixed-width | |
1606 | memory element (word for 32-bit processors, doubleword for 64-bit | |
1607 | processors), though only the bytes that will actually be stored to | |
1608 | memory need to be valid. The low-order two (or three) bits of pAddr | |
1609 | and the AccessLength field indicates which of the bytes within the | |
1610 | MemElem data should actually be stored; only these bytes in memory | |
1611 | will be changed. */ | |
53b9417e | 1612 | |
18c64df6 | 1613 | void |
01737f42 AC |
1614 | store_memory (SIM_DESC sd, |
1615 | sim_cpu *cpu, | |
1616 | address_word cia, | |
1617 | int CCA, | |
1618 | int AccessLength, | |
1619 | uword64 MemElem, | |
1620 | uword64 MemElem1, /* High order 64 bits */ | |
1621 | address_word pAddr, | |
1622 | address_word vAddr) | |
8bae0a0c JSC |
1623 | { |
1624 | #ifdef DEBUG | |
63be8feb | 1625 | sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr)); |
8bae0a0c | 1626 | #endif /* DEBUG */ |
63be8feb | 1627 | |
8bae0a0c JSC |
1628 | #if defined(WARN_MEM) |
1629 | if (CCA != uncached) | |
63be8feb | 1630 | sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); |
8bae0a0c | 1631 | #endif /* WARN_MEM */ |
63be8feb AC |
1632 | |
1633 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
1634 | sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr)); | |
1635 | ||
8bae0a0c | 1636 | #if defined(TRACE) |
01737f42 | 1637 | dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store"); |
8bae0a0c | 1638 | #endif /* TRACE */ |
63be8feb | 1639 | |
8bae0a0c | 1640 | #ifdef DEBUG |
63be8feb | 1641 | printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c | 1642 | #endif /* DEBUG */ |
63be8feb AC |
1643 | |
1644 | /* See also load_memory */ | |
1645 | if (AccessLength <= AccessLength_DOUBLEWORD) | |
1646 | { | |
1647 | if (BigEndianMem) | |
1648 | /* for big endian target, byte (pAddr&LOADDRMASK == 0) is | |
1649 | shifted to the most significant byte position. */ | |
1650 | MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
1651 | else | |
1652 | /* For little endian target, byte (pAddr&LOADDRMASK == 0) | |
1653 | is already in the correct postition. */ | |
1654 | MemElem >>= ((pAddr & LOADDRMASK) * 8); | |
1655 | } | |
1656 | ||
8bae0a0c | 1657 | #ifdef DEBUG |
63be8feb | 1658 | printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c | 1659 | #endif /* DEBUG */ |
63be8feb AC |
1660 | |
1661 | switch (AccessLength) | |
1662 | { | |
1663 | case AccessLength_QUADWORD : | |
1664 | { | |
1665 | unsigned_16 val = U16_8 (MemElem1, MemElem); | |
01737f42 | 1666 | sim_core_write_aligned_16 (cpu, NULL_CIA, |
63be8feb AC |
1667 | sim_core_write_map, pAddr, val); |
1668 | break; | |
8bae0a0c | 1669 | } |
63be8feb | 1670 | case AccessLength_DOUBLEWORD : |
01737f42 | 1671 | sim_core_write_aligned_8 (cpu, NULL_CIA, |
63be8feb AC |
1672 | sim_core_write_map, pAddr, MemElem); |
1673 | break; | |
1674 | case AccessLength_SEPTIBYTE : | |
01737f42 | 1675 | sim_core_write_misaligned_7 (cpu, NULL_CIA, |
63be8feb AC |
1676 | sim_core_write_map, pAddr, MemElem); |
1677 | break; | |
1678 | case AccessLength_SEXTIBYTE : | |
01737f42 | 1679 | sim_core_write_misaligned_6 (cpu, NULL_CIA, |
63be8feb AC |
1680 | sim_core_write_map, pAddr, MemElem); |
1681 | break; | |
1682 | case AccessLength_QUINTIBYTE : | |
01737f42 | 1683 | sim_core_write_misaligned_5 (cpu, NULL_CIA, |
63be8feb AC |
1684 | sim_core_write_map, pAddr, MemElem); |
1685 | break; | |
1686 | case AccessLength_WORD : | |
01737f42 | 1687 | sim_core_write_aligned_4 (cpu, NULL_CIA, |
63be8feb AC |
1688 | sim_core_write_map, pAddr, MemElem); |
1689 | break; | |
1690 | case AccessLength_TRIPLEBYTE : | |
01737f42 | 1691 | sim_core_write_misaligned_3 (cpu, NULL_CIA, |
63be8feb AC |
1692 | sim_core_write_map, pAddr, MemElem); |
1693 | break; | |
1694 | case AccessLength_HALFWORD : | |
01737f42 | 1695 | sim_core_write_aligned_2 (cpu, NULL_CIA, |
63be8feb AC |
1696 | sim_core_write_map, pAddr, MemElem); |
1697 | break; | |
1698 | case AccessLength_BYTE : | |
01737f42 | 1699 | sim_core_write_aligned_1 (cpu, NULL_CIA, |
63be8feb AC |
1700 | sim_core_write_map, pAddr, MemElem); |
1701 | break; | |
1702 | default: | |
1703 | abort (); | |
1704 | } | |
1705 | ||
8bae0a0c JSC |
1706 | return; |
1707 | } | |
1708 | ||
53b9417e | 1709 | |
dad6f1f3 | 1710 | unsigned32 |
7ce8b917 | 1711 | ifetch32 (SIM_DESC sd, |
01737f42 | 1712 | sim_cpu *cpu, |
7ce8b917 AC |
1713 | address_word cia, |
1714 | address_word vaddr) | |
dad6f1f3 AC |
1715 | { |
1716 | /* Copy the action of the LW instruction */ | |
1717 | address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
1718 | address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
1719 | unsigned64 value; | |
1720 | address_word paddr; | |
1721 | unsigned32 instruction; | |
1722 | unsigned byte; | |
1723 | int cca; | |
1724 | AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL); | |
1725 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
37379a25 AC |
1726 | LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL); |
1727 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); | |
1728 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
1729 | return instruction; | |
1730 | } | |
1731 | ||
1732 | ||
1733 | unsigned16 | |
1734 | ifetch16 (SIM_DESC sd, | |
1735 | sim_cpu *cpu, | |
1736 | address_word cia, | |
1737 | address_word vaddr) | |
1738 | { | |
1739 | /* Copy the action of the LW instruction */ | |
1740 | address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
1741 | address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
1742 | unsigned64 value; | |
1743 | address_word paddr; | |
1744 | unsigned16 instruction; | |
1745 | unsigned byte; | |
1746 | int cca; | |
1747 | AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL); | |
1748 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
dad6f1f3 AC |
1749 | LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL); |
1750 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); | |
1751 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
1752 | return instruction; | |
1753 | } | |
1754 | ||
1755 | ||
8bae0a0c JSC |
1756 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ |
1757 | /* Order loads and stores to synchronise shared memory. Perform the | |
1758 | action necessary to make the effects of groups of synchronizable | |
1759 | loads and stores indicated by stype occur in the same order for all | |
1760 | processors. */ | |
ea985d24 | 1761 | void |
01737f42 AC |
1762 | sync_operation (SIM_DESC sd, |
1763 | sim_cpu *cpu, | |
1764 | address_word cia, | |
1765 | int stype) | |
8bae0a0c JSC |
1766 | { |
1767 | #ifdef DEBUG | |
18c64df6 | 1768 | sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype); |
8bae0a0c JSC |
1769 | #endif /* DEBUG */ |
1770 | return; | |
1771 | } | |
1772 | ||
1773 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1774 | /* Signal an exception condition. This will result in an exception | |
1775 | that aborts the instruction. The instruction operation pseudocode | |
50a2a691 | 1776 | will never see a return from this function call. */ |
2e61a3ad | 1777 | |
18c64df6 | 1778 | void |
7ce8b917 | 1779 | signal_exception (SIM_DESC sd, |
01737f42 | 1780 | sim_cpu *cpu, |
7ce8b917 AC |
1781 | address_word cia, |
1782 | int exception,...) | |
8bae0a0c | 1783 | { |
56e7c849 | 1784 | int vector; |
6eedf3f4 MA |
1785 | |
1786 | #ifdef DEBUG | |
95469ceb | 1787 | sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); |
6eedf3f4 MA |
1788 | #endif /* DEBUG */ |
1789 | ||
8bae0a0c JSC |
1790 | /* Ensure that any active atomic read/modify/write operation will fail: */ |
1791 | LLBIT = 0; | |
1792 | ||
1793 | switch (exception) { | |
1794 | /* TODO: For testing purposes I have been ignoring TRAPs. In | |
1795 | reality we should either simulate them, or allow the user to | |
6eedf3f4 MA |
1796 | ignore them at run-time. |
1797 | Same for SYSCALL */ | |
8bae0a0c | 1798 | case Trap : |
95469ceb | 1799 | sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia)); |
8bae0a0c JSC |
1800 | break; |
1801 | ||
6eedf3f4 MA |
1802 | case SystemCall : |
1803 | { | |
1804 | va_list ap; | |
1805 | unsigned int instruction; | |
1806 | unsigned int code; | |
1807 | ||
1808 | va_start(ap,exception); | |
1809 | instruction = va_arg(ap,unsigned int); | |
1810 | va_end(ap); | |
1811 | ||
1812 | code = (instruction >> 6) & 0xFFFFF; | |
1813 | ||
18c64df6 | 1814 | sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n", |
95469ceb | 1815 | code, pr_addr(cia)); |
6eedf3f4 MA |
1816 | } |
1817 | break; | |
1818 | ||
1819 | case DebugBreakPoint : | |
1820 | if (! (Debug & Debug_DM)) | |
1821 | { | |
1822 | if (INDELAYSLOT()) | |
1823 | { | |
1824 | CANCELDELAYSLOT(); | |
1825 | ||
1826 | Debug |= Debug_DBD; /* signaled from within in delay slot */ | |
95469ceb | 1827 | DEPC = cia - 4; /* reference the branch instruction */ |
6eedf3f4 MA |
1828 | } |
1829 | else | |
1830 | { | |
1831 | Debug &= ~Debug_DBD; /* not signaled from within a delay slot */ | |
95469ceb | 1832 | DEPC = cia; |
6eedf3f4 MA |
1833 | } |
1834 | ||
1835 | Debug |= Debug_DM; /* in debugging mode */ | |
1836 | Debug |= Debug_DBp; /* raising a DBp exception */ | |
1837 | PC = 0xBFC00200; | |
01737f42 | 1838 | sim_engine_restart (SD, CPU, NULL, NULL_CIA); |
6eedf3f4 MA |
1839 | } |
1840 | break; | |
1841 | ||
8bae0a0c JSC |
1842 | case ReservedInstruction : |
1843 | { | |
1844 | va_list ap; | |
1845 | unsigned int instruction; | |
1846 | va_start(ap,exception); | |
1847 | instruction = va_arg(ap,unsigned int); | |
1848 | va_end(ap); | |
1849 | /* Provide simple monitor support using ReservedInstruction | |
1850 | exceptions. The following code simulates the fixed vector | |
1851 | entry points into the IDT monitor by causing a simulator | |
1852 | trap, performing the monitor operation, and returning to | |
1853 | the address held in the $ra register (standard PCS return | |
1854 | address). This means we only need to pre-load the vector | |
1855 | space with suitable instruction values. For systems were | |
1856 | actual trap instructions are used, we would not need to | |
1857 | perform this magic. */ | |
7ce8b917 AC |
1858 | if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION) |
1859 | { | |
01737f42 | 1860 | sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) ); |
7ce8b917 AC |
1861 | /* NOTE: This assumes that a branch-and-link style |
1862 | instruction was used to enter the vector (which is the | |
1863 | case with the current IDT monitor). */ | |
01737f42 | 1864 | sim_engine_restart (SD, CPU, NULL, RA); |
7ce8b917 | 1865 | } |
7e6c297e ILT |
1866 | /* Look for the mips16 entry and exit instructions, and |
1867 | simulate a handler for them. */ | |
95469ceb | 1868 | else if ((cia & 1) != 0 |
7e6c297e | 1869 | && (instruction & 0xf81f) == 0xe809 |
7ce8b917 AC |
1870 | && (instruction & 0x0c0) != 0x0c0) |
1871 | { | |
01737f42 | 1872 | mips16_entry (SD, CPU, cia, instruction); |
7ce8b917 AC |
1873 | sim_engine_restart (sd, NULL, NULL, NULL_CIA); |
1874 | } | |
1875 | /* else fall through to normal exception processing */ | |
95469ceb | 1876 | sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia)); |
8bae0a0c JSC |
1877 | } |
1878 | ||
05d1322f | 1879 | case BreakPoint: |
e3d12c65 | 1880 | #ifdef DEBUG |
95469ceb | 1881 | sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); |
8bae0a0c | 1882 | #endif /* DEBUG */ |
05d1322f JL |
1883 | /* Keep a copy of the current A0 in-case this is the program exit |
1884 | breakpoint: */ | |
1885 | { | |
1886 | va_list ap; | |
1887 | unsigned int instruction; | |
1888 | va_start(ap,exception); | |
1889 | instruction = va_arg(ap,unsigned int); | |
1890 | va_end(ap); | |
1891 | /* Check for our special terminating BREAK: */ | |
1892 | if ((instruction & 0x03FFFFC0) == 0x03ff0000) { | |
01737f42 | 1893 | sim_engine_halt (SD, CPU, NULL, cia, |
05d1322f JL |
1894 | sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); |
1895 | } | |
1896 | } | |
0c2c5f61 | 1897 | if (STATE & simDELAYSLOT) |
95469ceb | 1898 | PC = cia - 4; /* reference the branch instruction */ |
05d1322f | 1899 | else |
95469ceb | 1900 | PC = cia; |
01737f42 | 1901 | sim_engine_halt (SD, CPU, NULL, cia, |
232156de | 1902 | sim_stopped, SIM_SIGTRAP); |
05d1322f JL |
1903 | |
1904 | default: | |
8bae0a0c JSC |
1905 | /* Store exception code into current exception id variable (used |
1906 | by exit code): */ | |
1907 | ||
1908 | /* TODO: If not simulating exceptions then stop the simulator | |
1909 | execution. At the moment we always stop the simulation. */ | |
e3d12c65 | 1910 | |
56e7c849 AC |
1911 | /* See figure 5-17 for an outline of the code below */ |
1912 | if (! (SR & status_EXL)) | |
1913 | { | |
1914 | CAUSE = (exception << 2); | |
0c2c5f61 | 1915 | if (STATE & simDELAYSLOT) |
56e7c849 | 1916 | { |
0c2c5f61 | 1917 | STATE &= ~simDELAYSLOT; |
56e7c849 | 1918 | CAUSE |= cause_BD; |
95469ceb | 1919 | EPC = (cia - 4); /* reference the branch instruction */ |
56e7c849 AC |
1920 | } |
1921 | else | |
95469ceb | 1922 | EPC = cia; |
56e7c849 AC |
1923 | /* FIXME: TLB et.al. */ |
1924 | vector = 0x180; | |
1925 | } | |
1926 | else | |
1927 | { | |
05d1322f | 1928 | CAUSE = (exception << 2); |
56e7c849 AC |
1929 | vector = 0x180; |
1930 | } | |
1931 | SR |= status_EXL; | |
e3d12c65 DE |
1932 | /* Store exception code into current exception id variable (used |
1933 | by exit code): */ | |
56e7c849 AC |
1934 | if (SR & status_BEV) |
1935 | PC = (signed)0xBFC00200 + 0x180; | |
1936 | else | |
1937 | PC = (signed)0x80000000 + 0x180; | |
1938 | ||
50a2a691 AC |
1939 | switch ((CAUSE >> 2) & 0x1F) |
1940 | { | |
1941 | case Interrupt: | |
56e7c849 AC |
1942 | /* Interrupts arrive during event processing, no need to |
1943 | restart */ | |
1944 | return; | |
50a2a691 AC |
1945 | |
1946 | case TLBModification: | |
1947 | case TLBLoad: | |
1948 | case TLBStore: | |
1949 | case AddressLoad: | |
1950 | case AddressStore: | |
1951 | case InstructionFetch: | |
1952 | case DataReference: | |
56e7c849 AC |
1953 | /* The following is so that the simulator will continue from the |
1954 | exception address on breakpoint operations. */ | |
1955 | PC = EPC; | |
01737f42 | 1956 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1957 | sim_stopped, SIM_SIGBUS); |
50a2a691 AC |
1958 | |
1959 | case ReservedInstruction: | |
1960 | case CoProcessorUnusable: | |
56e7c849 | 1961 | PC = EPC; |
01737f42 | 1962 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1963 | sim_stopped, SIM_SIGILL); |
50a2a691 AC |
1964 | |
1965 | case IntegerOverflow: | |
1966 | case FPE: | |
01737f42 | 1967 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1968 | sim_stopped, SIM_SIGFPE); |
50a2a691 AC |
1969 | |
1970 | case Trap: | |
1971 | case Watch: | |
1972 | case SystemCall: | |
56e7c849 | 1973 | PC = EPC; |
01737f42 | 1974 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1975 | sim_stopped, SIM_SIGTRAP); |
50a2a691 | 1976 | |
05d1322f JL |
1977 | case BreakPoint: |
1978 | PC = EPC; | |
01737f42 | 1979 | sim_engine_abort (SD, CPU, NULL_CIA, |
05d1322f JL |
1980 | "FATAL: Should not encounter a breakpoint\n"); |
1981 | ||
50a2a691 | 1982 | default : /* Unknown internal exception */ |
56e7c849 | 1983 | PC = EPC; |
01737f42 | 1984 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1985 | sim_stopped, SIM_SIGABRT); |
50a2a691 AC |
1986 | |
1987 | } | |
8bae0a0c JSC |
1988 | |
1989 | case SimulatorFault: | |
1990 | { | |
1991 | va_list ap; | |
1992 | char *msg; | |
1993 | va_start(ap,exception); | |
1994 | msg = va_arg(ap,char *); | |
50a2a691 | 1995 | va_end(ap); |
01737f42 | 1996 | sim_engine_abort (SD, CPU, NULL_CIA, |
2e61a3ad | 1997 | "FATAL: Simulator error \"%s\"\n",msg); |
8bae0a0c | 1998 | } |
8bae0a0c JSC |
1999 | } |
2000 | ||
2001 | return; | |
2002 | } | |
2003 | ||
2004 | #if defined(WARN_RESULT) | |
2005 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
2006 | /* This function indicates that the result of the operation is | |
2007 | undefined. However, this should not affect the instruction | |
2008 | stream. All that is meant to happen is that the destination | |
2009 | register is set to an undefined result. To keep the simulator | |
2010 | simple, we just don't bother updating the destination register, so | |
2011 | the overall result will be undefined. If desired we can stop the | |
2012 | simulator by raising a pseudo-exception. */ | |
95469ceb | 2013 | #define UndefinedResult() undefined_result (sd,cia) |
8bae0a0c | 2014 | static void |
95469ceb AC |
2015 | undefined_result(sd,cia) |
2016 | SIM_DESC sd; | |
2017 | address_word cia; | |
8bae0a0c | 2018 | { |
95469ceb | 2019 | sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia)); |
8bae0a0c JSC |
2020 | #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */ |
2021 | state |= simSTOP; | |
2022 | #endif | |
2023 | return; | |
2024 | } | |
2025 | #endif /* WARN_RESULT */ | |
2026 | ||
18c64df6 | 2027 | void |
01737f42 AC |
2028 | cache_op (SIM_DESC sd, |
2029 | sim_cpu *cpu, | |
2030 | address_word cia, | |
2031 | int op, | |
2032 | address_word pAddr, | |
2033 | address_word vAddr, | |
2034 | unsigned int instruction) | |
8bae0a0c | 2035 | { |
f24b7b69 JSC |
2036 | #if 1 /* stop warning message being displayed (we should really just remove the code) */ |
2037 | static int icache_warning = 1; | |
2038 | static int dcache_warning = 1; | |
2039 | #else | |
a9f7253f JSC |
2040 | static int icache_warning = 0; |
2041 | static int dcache_warning = 0; | |
f24b7b69 | 2042 | #endif |
a9f7253f | 2043 | |
8bae0a0c JSC |
2044 | /* If CP0 is not useable (User or Supervisor mode) and the CP0 |
2045 | enable bit in the Status Register is clear - a coprocessor | |
2046 | unusable exception is taken. */ | |
a9f7253f | 2047 | #if 0 |
95469ceb | 2048 | sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia)); |
a9f7253f | 2049 | #endif |
8bae0a0c JSC |
2050 | |
2051 | switch (op & 0x3) { | |
2052 | case 0: /* instruction cache */ | |
2053 | switch (op >> 2) { | |
2054 | case 0: /* Index Invalidate */ | |
2055 | case 1: /* Index Load Tag */ | |
2056 | case 2: /* Index Store Tag */ | |
2057 | case 4: /* Hit Invalidate */ | |
2058 | case 5: /* Fill */ | |
2059 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
2060 | if (!icache_warning) |
2061 | { | |
18c64df6 | 2062 | sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2)); |
a9f7253f JSC |
2063 | icache_warning = 1; |
2064 | } | |
8bae0a0c JSC |
2065 | break; |
2066 | ||
2067 | default: | |
2068 | SignalException(ReservedInstruction,instruction); | |
2069 | break; | |
2070 | } | |
2071 | break; | |
2072 | ||
2073 | case 1: /* data cache */ | |
2074 | switch (op >> 2) { | |
2075 | case 0: /* Index Writeback Invalidate */ | |
2076 | case 1: /* Index Load Tag */ | |
2077 | case 2: /* Index Store Tag */ | |
2078 | case 3: /* Create Dirty */ | |
2079 | case 4: /* Hit Invalidate */ | |
2080 | case 5: /* Hit Writeback Invalidate */ | |
2081 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
2082 | if (!dcache_warning) |
2083 | { | |
18c64df6 | 2084 | sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2)); |
a9f7253f JSC |
2085 | dcache_warning = 1; |
2086 | } | |
8bae0a0c JSC |
2087 | break; |
2088 | ||
2089 | default: | |
2090 | SignalException(ReservedInstruction,instruction); | |
2091 | break; | |
2092 | } | |
2093 | break; | |
2094 | ||
2095 | default: /* unrecognised cache ID */ | |
2096 | SignalException(ReservedInstruction,instruction); | |
2097 | break; | |
2098 | } | |
2099 | ||
2100 | return; | |
2101 | } | |
2102 | ||
2103 | /*-- FPU support routines ---------------------------------------------------*/ | |
2104 | ||
8bae0a0c JSC |
2105 | /* Numbers are held in normalized form. The SINGLE and DOUBLE binary |
2106 | formats conform to ANSI/IEEE Std 754-1985. */ | |
2107 | /* SINGLE precision floating: | |
2108 | * seeeeeeeefffffffffffffffffffffff | |
2109 | * s = 1bit = sign | |
2110 | * e = 8bits = exponent | |
2111 | * f = 23bits = fraction | |
2112 | */ | |
2113 | /* SINGLE precision fixed: | |
2114 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
2115 | * s = 1bit = sign | |
2116 | * i = 31bits = integer | |
2117 | */ | |
2118 | /* DOUBLE precision floating: | |
2119 | * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff | |
2120 | * s = 1bit = sign | |
2121 | * e = 11bits = exponent | |
2122 | * f = 52bits = fraction | |
2123 | */ | |
2124 | /* DOUBLE precision fixed: | |
2125 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
2126 | * s = 1bit = sign | |
2127 | * i = 63bits = integer | |
2128 | */ | |
2129 | ||
2130 | /* Extract sign-bit: */ | |
2131 | #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0) | |
e871dd18 | 2132 | #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0) |
8bae0a0c JSC |
2133 | /* Extract biased exponent: */ |
2134 | #define FP_S_be(v) (((v) >> 23) & 0xFF) | |
2135 | #define FP_D_be(v) (((v) >> 52) & 0x7FF) | |
2136 | /* Extract unbiased Exponent: */ | |
2137 | #define FP_S_e(v) (FP_S_be(v) - 0x7F) | |
2138 | #define FP_D_e(v) (FP_D_be(v) - 0x3FF) | |
2139 | /* Extract complete fraction field: */ | |
2140 | #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23)) | |
e871dd18 | 2141 | #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52)) |
8bae0a0c JSC |
2142 | /* Extract numbered fraction bit: */ |
2143 | #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0) | |
2144 | #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0) | |
2145 | ||
2146 | /* Explicit QNaN values used when value required: */ | |
2147 | #define FPQNaN_SINGLE (0x7FBFFFFF) | |
2148 | #define FPQNaN_WORD (0x7FFFFFFF) | |
e871dd18 JSC |
2149 | #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF) |
2150 | #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF) | |
8bae0a0c JSC |
2151 | |
2152 | /* Explicit Infinity values used when required: */ | |
2153 | #define FPINF_SINGLE (0x7F800000) | |
e871dd18 | 2154 | #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000) |
8bae0a0c JSC |
2155 | |
2156 | #if 1 /* def DEBUG */ | |
2157 | #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor"))) | |
2158 | #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>")))))) | |
2159 | #endif /* DEBUG */ | |
2160 | ||
18c64df6 | 2161 | uword64 |
01737f42 AC |
2162 | value_fpr (SIM_DESC sd, |
2163 | sim_cpu *cpu, | |
2164 | address_word cia, | |
2165 | int fpr, | |
2166 | FP_formats fmt) | |
8bae0a0c | 2167 | { |
50a2a691 | 2168 | uword64 value = 0; |
8bae0a0c JSC |
2169 | int err = 0; |
2170 | ||
2171 | /* Treat unused register values, as fixed-point 64bit values: */ | |
2172 | if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown)) | |
2173 | #if 1 | |
2174 | /* If request to read data as "uninterpreted", then use the current | |
2175 | encoding: */ | |
0c2c5f61 | 2176 | fmt = FPR_STATE[fpr]; |
8bae0a0c JSC |
2177 | #else |
2178 | fmt = fmt_long; | |
2179 | #endif | |
2180 | ||
2181 | /* For values not yet accessed, set to the desired format: */ | |
0c2c5f61 AC |
2182 | if (FPR_STATE[fpr] == fmt_uninterpreted) { |
2183 | FPR_STATE[fpr] = fmt; | |
8bae0a0c JSC |
2184 | #ifdef DEBUG |
2185 | printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt)); | |
2186 | #endif /* DEBUG */ | |
2187 | } | |
0c2c5f61 | 2188 | if (fmt != FPR_STATE[fpr]) { |
95469ceb | 2189 | sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia)); |
0c2c5f61 | 2190 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2191 | } |
2192 | ||
0c2c5f61 | 2193 | if (FPR_STATE[fpr] == fmt_unknown) { |
8bae0a0c JSC |
2194 | /* Set QNaN value: */ |
2195 | switch (fmt) { | |
2196 | case fmt_single: | |
2197 | value = FPQNaN_SINGLE; | |
2198 | break; | |
2199 | ||
2200 | case fmt_double: | |
2201 | value = FPQNaN_DOUBLE; | |
2202 | break; | |
2203 | ||
2204 | case fmt_word: | |
2205 | value = FPQNaN_WORD; | |
2206 | break; | |
2207 | ||
2208 | case fmt_long: | |
2209 | value = FPQNaN_LONG; | |
2210 | break; | |
2211 | ||
2212 | default: | |
2213 | err = -1; | |
2214 | break; | |
2215 | } | |
2216 | } else if (SizeFGR() == 64) { | |
2217 | switch (fmt) { | |
2218 | case fmt_single: | |
2219 | case fmt_word: | |
2220 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2221 | break; | |
2222 | ||
2223 | case fmt_uninterpreted: | |
2224 | case fmt_double: | |
2225 | case fmt_long: | |
2226 | value = FGR[fpr]; | |
2227 | break; | |
2228 | ||
2229 | default : | |
2230 | err = -1; | |
2231 | break; | |
2232 | } | |
da0bce9c | 2233 | } else { |
8bae0a0c JSC |
2234 | switch (fmt) { |
2235 | case fmt_single: | |
2236 | case fmt_word: | |
2237 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2238 | break; | |
2239 | ||
2240 | case fmt_uninterpreted: | |
2241 | case fmt_double: | |
2242 | case fmt_long: | |
da0bce9c ILT |
2243 | if ((fpr & 1) == 0) { /* even registers only */ |
2244 | value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF)); | |
2245 | } else { | |
18c64df6 | 2246 | SignalException(ReservedInstruction,0); |
da0bce9c | 2247 | } |
8bae0a0c JSC |
2248 | break; |
2249 | ||
2250 | default : | |
2251 | err = -1; | |
2252 | break; | |
2253 | } | |
2254 | } | |
2255 | ||
2256 | if (err) | |
18c64df6 | 2257 | SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()"); |
8bae0a0c JSC |
2258 | |
2259 | #ifdef DEBUG | |
95469ceb | 2260 | printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR()); |
8bae0a0c JSC |
2261 | #endif /* DEBUG */ |
2262 | ||
2263 | return(value); | |
2264 | } | |
2265 | ||
18c64df6 | 2266 | void |
01737f42 AC |
2267 | store_fpr (SIM_DESC sd, |
2268 | sim_cpu *cpu, | |
2269 | address_word cia, | |
2270 | int fpr, | |
2271 | FP_formats fmt, | |
2272 | uword64 value) | |
8bae0a0c JSC |
2273 | { |
2274 | int err = 0; | |
2275 | ||
2276 | #ifdef DEBUG | |
95469ceb | 2277 | printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR()); |
8bae0a0c JSC |
2278 | #endif /* DEBUG */ |
2279 | ||
2280 | if (SizeFGR() == 64) { | |
2281 | switch (fmt) { | |
a09a30d2 AC |
2282 | case fmt_uninterpreted_32: |
2283 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2284 | case fmt_single : |
2285 | case fmt_word : | |
e871dd18 | 2286 | FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF)); |
0c2c5f61 | 2287 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2288 | break; |
2289 | ||
a09a30d2 AC |
2290 | case fmt_uninterpreted_64: |
2291 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2292 | case fmt_uninterpreted: |
2293 | case fmt_double : | |
2294 | case fmt_long : | |
2295 | FGR[fpr] = value; | |
0c2c5f61 | 2296 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2297 | break; |
2298 | ||
2299 | default : | |
0c2c5f61 | 2300 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2301 | err = -1; |
2302 | break; | |
2303 | } | |
da0bce9c | 2304 | } else { |
8bae0a0c | 2305 | switch (fmt) { |
a09a30d2 AC |
2306 | case fmt_uninterpreted_32: |
2307 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2308 | case fmt_single : |
2309 | case fmt_word : | |
8bae0a0c | 2310 | FGR[fpr] = (value & 0xFFFFFFFF); |
0c2c5f61 | 2311 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2312 | break; |
2313 | ||
a09a30d2 AC |
2314 | case fmt_uninterpreted_64: |
2315 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2316 | case fmt_uninterpreted: |
2317 | case fmt_double : | |
2318 | case fmt_long : | |
da0bce9c ILT |
2319 | if ((fpr & 1) == 0) { /* even register number only */ |
2320 | FGR[fpr+1] = (value >> 32); | |
2321 | FGR[fpr] = (value & 0xFFFFFFFF); | |
0c2c5f61 AC |
2322 | FPR_STATE[fpr + 1] = fmt; |
2323 | FPR_STATE[fpr] = fmt; | |
da0bce9c | 2324 | } else { |
0c2c5f61 AC |
2325 | FPR_STATE[fpr] = fmt_unknown; |
2326 | FPR_STATE[fpr + 1] = fmt_unknown; | |
18c64df6 | 2327 | SignalException(ReservedInstruction,0); |
da0bce9c | 2328 | } |
8bae0a0c JSC |
2329 | break; |
2330 | ||
2331 | default : | |
0c2c5f61 | 2332 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2333 | err = -1; |
2334 | break; | |
2335 | } | |
e871dd18 JSC |
2336 | } |
2337 | #if defined(WARN_RESULT) | |
2338 | else | |
2339 | UndefinedResult(); | |
2340 | #endif /* WARN_RESULT */ | |
8bae0a0c JSC |
2341 | |
2342 | if (err) | |
18c64df6 | 2343 | SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()"); |
8bae0a0c JSC |
2344 | |
2345 | #ifdef DEBUG | |
53b9417e | 2346 | printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt)); |
8bae0a0c JSC |
2347 | #endif /* DEBUG */ |
2348 | ||
2349 | return; | |
2350 | } | |
2351 | ||
18c64df6 | 2352 | int |
8bae0a0c | 2353 | NaN(op,fmt) |
e871dd18 | 2354 | uword64 op; |
8bae0a0c JSC |
2355 | FP_formats fmt; |
2356 | { | |
2357 | int boolean = 0; | |
8bae0a0c JSC |
2358 | switch (fmt) { |
2359 | case fmt_single: | |
8bae0a0c | 2360 | case fmt_word: |
76ef4165 FL |
2361 | { |
2362 | sim_fpu wop; | |
2363 | sim_fpu_32to (&wop, op); | |
2364 | boolean = sim_fpu_is_nan (&wop); | |
2365 | break; | |
2366 | } | |
2367 | case fmt_double: | |
8bae0a0c | 2368 | case fmt_long: |
76ef4165 FL |
2369 | { |
2370 | sim_fpu wop; | |
2371 | sim_fpu_64to (&wop, op); | |
2372 | boolean = sim_fpu_is_nan (&wop); | |
2373 | break; | |
2374 | } | |
50a2a691 AC |
2375 | default: |
2376 | fprintf (stderr, "Bad switch\n"); | |
2377 | abort (); | |
8bae0a0c JSC |
2378 | } |
2379 | ||
2380 | #ifdef DEBUG | |
53b9417e | 2381 | printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2382 | #endif /* DEBUG */ |
2383 | ||
2384 | return(boolean); | |
2385 | } | |
2386 | ||
18c64df6 | 2387 | int |
8bae0a0c | 2388 | Infinity(op,fmt) |
e871dd18 | 2389 | uword64 op; |
8bae0a0c JSC |
2390 | FP_formats fmt; |
2391 | { | |
2392 | int boolean = 0; | |
2393 | ||
2394 | #ifdef DEBUG | |
95469ceb | 2395 | printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2396 | #endif /* DEBUG */ |
2397 | ||
8bae0a0c JSC |
2398 | switch (fmt) { |
2399 | case fmt_single: | |
76ef4165 FL |
2400 | { |
2401 | sim_fpu wop; | |
2402 | sim_fpu_32to (&wop, op); | |
2403 | boolean = sim_fpu_is_infinity (&wop); | |
2404 | break; | |
2405 | } | |
8bae0a0c | 2406 | case fmt_double: |
76ef4165 FL |
2407 | { |
2408 | sim_fpu wop; | |
2409 | sim_fpu_64to (&wop, op); | |
2410 | boolean = sim_fpu_is_infinity (&wop); | |
2411 | break; | |
2412 | } | |
8bae0a0c JSC |
2413 | default: |
2414 | printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt)); | |
2415 | break; | |
2416 | } | |
2417 | ||
2418 | #ifdef DEBUG | |
53b9417e | 2419 | printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2420 | #endif /* DEBUG */ |
2421 | ||
2422 | return(boolean); | |
2423 | } | |
2424 | ||
18c64df6 | 2425 | int |
8bae0a0c | 2426 | Less(op1,op2,fmt) |
e871dd18 JSC |
2427 | uword64 op1; |
2428 | uword64 op2; | |
8bae0a0c JSC |
2429 | FP_formats fmt; |
2430 | { | |
2431 | int boolean = 0; | |
2432 | ||
e871dd18 JSC |
2433 | /* Argument checking already performed by the FPCOMPARE code */ |
2434 | ||
8bae0a0c | 2435 | #ifdef DEBUG |
53b9417e | 2436 | printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2437 | #endif /* DEBUG */ |
2438 | ||
8bae0a0c JSC |
2439 | /* The format type should already have been checked: */ |
2440 | switch (fmt) { | |
2441 | case fmt_single: | |
2442 | { | |
76ef4165 FL |
2443 | sim_fpu wop1; |
2444 | sim_fpu wop2; | |
2445 | sim_fpu_32to (&wop1, op1); | |
2446 | sim_fpu_32to (&wop2, op2); | |
2447 | boolean = sim_fpu_is_lt (&wop1, &wop2); | |
2448 | break; | |
8bae0a0c | 2449 | } |
8bae0a0c | 2450 | case fmt_double: |
76ef4165 FL |
2451 | { |
2452 | sim_fpu wop1; | |
2453 | sim_fpu wop2; | |
2454 | sim_fpu_64to (&wop1, op1); | |
2455 | sim_fpu_64to (&wop2, op2); | |
2456 | boolean = sim_fpu_is_lt (&wop1, &wop2); | |
2457 | break; | |
2458 | } | |
50a2a691 AC |
2459 | default: |
2460 | fprintf (stderr, "Bad switch\n"); | |
2461 | abort (); | |
8bae0a0c JSC |
2462 | } |
2463 | ||
2464 | #ifdef DEBUG | |
2465 | printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2466 | #endif /* DEBUG */ | |
2467 | ||
2468 | return(boolean); | |
2469 | } | |
2470 | ||
18c64df6 | 2471 | int |
8bae0a0c | 2472 | Equal(op1,op2,fmt) |
e871dd18 JSC |
2473 | uword64 op1; |
2474 | uword64 op2; | |
8bae0a0c JSC |
2475 | FP_formats fmt; |
2476 | { | |
2477 | int boolean = 0; | |
2478 | ||
e871dd18 JSC |
2479 | /* Argument checking already performed by the FPCOMPARE code */ |
2480 | ||
8bae0a0c | 2481 | #ifdef DEBUG |
53b9417e | 2482 | printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2483 | #endif /* DEBUG */ |
2484 | ||
8bae0a0c JSC |
2485 | /* The format type should already have been checked: */ |
2486 | switch (fmt) { | |
2487 | case fmt_single: | |
76ef4165 FL |
2488 | { |
2489 | sim_fpu wop1; | |
2490 | sim_fpu wop2; | |
2491 | sim_fpu_32to (&wop1, op1); | |
2492 | sim_fpu_32to (&wop2, op2); | |
2493 | boolean = sim_fpu_is_eq (&wop1, &wop2); | |
2494 | break; | |
2495 | } | |
8bae0a0c | 2496 | case fmt_double: |
76ef4165 FL |
2497 | { |
2498 | sim_fpu wop1; | |
2499 | sim_fpu wop2; | |
2500 | sim_fpu_64to (&wop1, op1); | |
2501 | sim_fpu_64to (&wop2, op2); | |
2502 | boolean = sim_fpu_is_eq (&wop1, &wop2); | |
2503 | break; | |
2504 | } | |
50a2a691 AC |
2505 | default: |
2506 | fprintf (stderr, "Bad switch\n"); | |
2507 | abort (); | |
8bae0a0c JSC |
2508 | } |
2509 | ||
2510 | #ifdef DEBUG | |
2511 | printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2512 | #endif /* DEBUG */ | |
2513 | ||
2514 | return(boolean); | |
2515 | } | |
2516 | ||
18c64df6 | 2517 | uword64 |
a9f7253f JSC |
2518 | AbsoluteValue(op,fmt) |
2519 | uword64 op; | |
2520 | FP_formats fmt; | |
2521 | { | |
50a2a691 | 2522 | uword64 result = 0; |
a9f7253f JSC |
2523 | |
2524 | #ifdef DEBUG | |
53b9417e | 2525 | printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
a9f7253f JSC |
2526 | #endif /* DEBUG */ |
2527 | ||
2528 | /* The format type should already have been checked: */ | |
2529 | switch (fmt) { | |
2530 | case fmt_single: | |
2531 | { | |
76ef4165 FL |
2532 | sim_fpu wop; |
2533 | unsigned32 ans; | |
2534 | sim_fpu_32to (&wop, op); | |
2535 | sim_fpu_abs (&wop, &wop); | |
2536 | sim_fpu_to32 (&ans, &wop); | |
2537 | result = ans; | |
2538 | break; | |
a9f7253f | 2539 | } |
a9f7253f JSC |
2540 | case fmt_double: |
2541 | { | |
76ef4165 FL |
2542 | sim_fpu wop; |
2543 | unsigned64 ans; | |
2544 | sim_fpu_64to (&wop, op); | |
2545 | sim_fpu_abs (&wop, &wop); | |
2546 | sim_fpu_to64 (&ans, &wop); | |
2547 | result = ans; | |
2548 | break; | |
a9f7253f | 2549 | } |
50a2a691 AC |
2550 | default: |
2551 | fprintf (stderr, "Bad switch\n"); | |
2552 | abort (); | |
a9f7253f JSC |
2553 | } |
2554 | ||
2555 | return(result); | |
2556 | } | |
2557 | ||
18c64df6 | 2558 | uword64 |
8bae0a0c | 2559 | Negate(op,fmt) |
e871dd18 | 2560 | uword64 op; |
8bae0a0c JSC |
2561 | FP_formats fmt; |
2562 | { | |
50a2a691 | 2563 | uword64 result = 0; |
8bae0a0c JSC |
2564 | |
2565 | #ifdef DEBUG | |
53b9417e | 2566 | printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2567 | #endif /* DEBUG */ |
2568 | ||
2569 | /* The format type should already have been checked: */ | |
2570 | switch (fmt) { | |
2571 | case fmt_single: | |
2572 | { | |
76ef4165 FL |
2573 | sim_fpu wop; |
2574 | unsigned32 ans; | |
2575 | sim_fpu_32to (&wop, op); | |
2576 | sim_fpu_neg (&wop, &wop); | |
2577 | sim_fpu_to32 (&ans, &wop); | |
2578 | result = ans; | |
2579 | break; | |
8bae0a0c | 2580 | } |
8bae0a0c JSC |
2581 | case fmt_double: |
2582 | { | |
76ef4165 FL |
2583 | sim_fpu wop; |
2584 | unsigned64 ans; | |
2585 | sim_fpu_64to (&wop, op); | |
2586 | sim_fpu_neg (&wop, &wop); | |
2587 | sim_fpu_to64 (&ans, &wop); | |
2588 | result = ans; | |
2589 | break; | |
8bae0a0c | 2590 | } |
50a2a691 AC |
2591 | default: |
2592 | fprintf (stderr, "Bad switch\n"); | |
2593 | abort (); | |
8bae0a0c JSC |
2594 | } |
2595 | ||
2596 | return(result); | |
2597 | } | |
2598 | ||
18c64df6 | 2599 | uword64 |
8bae0a0c | 2600 | Add(op1,op2,fmt) |
e871dd18 JSC |
2601 | uword64 op1; |
2602 | uword64 op2; | |
8bae0a0c JSC |
2603 | FP_formats fmt; |
2604 | { | |
50a2a691 | 2605 | uword64 result = 0; |
8bae0a0c JSC |
2606 | |
2607 | #ifdef DEBUG | |
53b9417e | 2608 | printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2609 | #endif /* DEBUG */ |
2610 | ||
e871dd18 JSC |
2611 | /* The registers must specify FPRs valid for operands of type |
2612 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2613 | |
2614 | /* The format type should already have been checked: */ | |
2615 | switch (fmt) { | |
2616 | case fmt_single: | |
2617 | { | |
76ef4165 FL |
2618 | sim_fpu wop1; |
2619 | sim_fpu wop2; | |
2620 | sim_fpu ans; | |
2621 | unsigned32 res; | |
2622 | sim_fpu_32to (&wop1, op1); | |
2623 | sim_fpu_32to (&wop2, op2); | |
2624 | sim_fpu_add (&ans, &wop1, &wop2); | |
2625 | sim_fpu_to32 (&res, &ans); | |
2626 | result = res; | |
2627 | break; | |
8bae0a0c | 2628 | } |
8bae0a0c JSC |
2629 | case fmt_double: |
2630 | { | |
76ef4165 FL |
2631 | sim_fpu wop1; |
2632 | sim_fpu wop2; | |
2633 | sim_fpu ans; | |
2634 | unsigned64 res; | |
2635 | sim_fpu_64to (&wop1, op1); | |
2636 | sim_fpu_64to (&wop2, op2); | |
2637 | sim_fpu_add (&ans, &wop1, &wop2); | |
2638 | sim_fpu_to64 (&res, &ans); | |
2639 | result = res; | |
2640 | break; | |
8bae0a0c | 2641 | } |
50a2a691 AC |
2642 | default: |
2643 | fprintf (stderr, "Bad switch\n"); | |
2644 | abort (); | |
8bae0a0c JSC |
2645 | } |
2646 | ||
2647 | #ifdef DEBUG | |
53b9417e | 2648 | printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2649 | #endif /* DEBUG */ |
2650 | ||
2651 | return(result); | |
2652 | } | |
2653 | ||
18c64df6 | 2654 | uword64 |
8bae0a0c | 2655 | Sub(op1,op2,fmt) |
e871dd18 JSC |
2656 | uword64 op1; |
2657 | uword64 op2; | |
8bae0a0c JSC |
2658 | FP_formats fmt; |
2659 | { | |
50a2a691 | 2660 | uword64 result = 0; |
8bae0a0c JSC |
2661 | |
2662 | #ifdef DEBUG | |
53b9417e | 2663 | printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2664 | #endif /* DEBUG */ |
2665 | ||
e871dd18 JSC |
2666 | /* The registers must specify FPRs valid for operands of type |
2667 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2668 | |
2669 | /* The format type should already have been checked: */ | |
2670 | switch (fmt) { | |
2671 | case fmt_single: | |
2672 | { | |
76ef4165 FL |
2673 | sim_fpu wop1; |
2674 | sim_fpu wop2; | |
2675 | sim_fpu ans; | |
2676 | unsigned32 res; | |
2677 | sim_fpu_32to (&wop1, op1); | |
2678 | sim_fpu_32to (&wop2, op2); | |
2679 | sim_fpu_sub (&ans, &wop1, &wop2); | |
2680 | sim_fpu_to32 (&res, &ans); | |
2681 | result = res; | |
8bae0a0c JSC |
2682 | } |
2683 | break; | |
2684 | case fmt_double: | |
2685 | { | |
76ef4165 FL |
2686 | sim_fpu wop1; |
2687 | sim_fpu wop2; | |
2688 | sim_fpu ans; | |
2689 | unsigned64 res; | |
2690 | sim_fpu_64to (&wop1, op1); | |
2691 | sim_fpu_64to (&wop2, op2); | |
2692 | sim_fpu_sub (&ans, &wop1, &wop2); | |
2693 | sim_fpu_to64 (&res, &ans); | |
2694 | result = res; | |
8bae0a0c JSC |
2695 | } |
2696 | break; | |
50a2a691 AC |
2697 | default: |
2698 | fprintf (stderr, "Bad switch\n"); | |
2699 | abort (); | |
8bae0a0c JSC |
2700 | } |
2701 | ||
2702 | #ifdef DEBUG | |
53b9417e | 2703 | printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2704 | #endif /* DEBUG */ |
2705 | ||
2706 | return(result); | |
2707 | } | |
2708 | ||
18c64df6 | 2709 | uword64 |
8bae0a0c | 2710 | Multiply(op1,op2,fmt) |
e871dd18 JSC |
2711 | uword64 op1; |
2712 | uword64 op2; | |
8bae0a0c JSC |
2713 | FP_formats fmt; |
2714 | { | |
50a2a691 | 2715 | uword64 result = 0; |
8bae0a0c JSC |
2716 | |
2717 | #ifdef DEBUG | |
53b9417e | 2718 | printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2719 | #endif /* DEBUG */ |
2720 | ||
e871dd18 JSC |
2721 | /* The registers must specify FPRs valid for operands of type |
2722 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2723 | |
2724 | /* The format type should already have been checked: */ | |
2725 | switch (fmt) { | |
2726 | case fmt_single: | |
2727 | { | |
76ef4165 FL |
2728 | sim_fpu wop1; |
2729 | sim_fpu wop2; | |
2730 | sim_fpu ans; | |
2731 | unsigned32 res; | |
2732 | sim_fpu_32to (&wop1, op1); | |
2733 | sim_fpu_32to (&wop2, op2); | |
2734 | sim_fpu_mul (&ans, &wop1, &wop2); | |
2735 | sim_fpu_to32 (&res, &ans); | |
2736 | result = res; | |
2737 | break; | |
8bae0a0c | 2738 | } |
8bae0a0c JSC |
2739 | case fmt_double: |
2740 | { | |
76ef4165 FL |
2741 | sim_fpu wop1; |
2742 | sim_fpu wop2; | |
2743 | sim_fpu ans; | |
2744 | unsigned64 res; | |
2745 | sim_fpu_64to (&wop1, op1); | |
2746 | sim_fpu_64to (&wop2, op2); | |
2747 | sim_fpu_mul (&ans, &wop1, &wop2); | |
2748 | sim_fpu_to64 (&res, &ans); | |
2749 | result = res; | |
2750 | break; | |
8bae0a0c | 2751 | } |
50a2a691 AC |
2752 | default: |
2753 | fprintf (stderr, "Bad switch\n"); | |
2754 | abort (); | |
8bae0a0c JSC |
2755 | } |
2756 | ||
2757 | #ifdef DEBUG | |
53b9417e | 2758 | printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2759 | #endif /* DEBUG */ |
2760 | ||
2761 | return(result); | |
2762 | } | |
2763 | ||
18c64df6 | 2764 | uword64 |
8bae0a0c | 2765 | Divide(op1,op2,fmt) |
e871dd18 JSC |
2766 | uword64 op1; |
2767 | uword64 op2; | |
8bae0a0c JSC |
2768 | FP_formats fmt; |
2769 | { | |
50a2a691 | 2770 | uword64 result = 0; |
8bae0a0c JSC |
2771 | |
2772 | #ifdef DEBUG | |
53b9417e | 2773 | printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2774 | #endif /* DEBUG */ |
2775 | ||
e871dd18 JSC |
2776 | /* The registers must specify FPRs valid for operands of type |
2777 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2778 | |
2779 | /* The format type should already have been checked: */ | |
2780 | switch (fmt) { | |
2781 | case fmt_single: | |
2782 | { | |
76ef4165 FL |
2783 | sim_fpu wop1; |
2784 | sim_fpu wop2; | |
2785 | sim_fpu ans; | |
2786 | unsigned32 res; | |
2787 | sim_fpu_32to (&wop1, op1); | |
2788 | sim_fpu_32to (&wop2, op2); | |
2789 | sim_fpu_div (&ans, &wop1, &wop2); | |
2790 | sim_fpu_to32 (&res, &ans); | |
2791 | result = res; | |
2792 | break; | |
8bae0a0c | 2793 | } |
8bae0a0c JSC |
2794 | case fmt_double: |
2795 | { | |
76ef4165 FL |
2796 | sim_fpu wop1; |
2797 | sim_fpu wop2; | |
2798 | sim_fpu ans; | |
2799 | unsigned64 res; | |
2800 | sim_fpu_64to (&wop1, op1); | |
2801 | sim_fpu_64to (&wop2, op2); | |
2802 | sim_fpu_div (&ans, &wop1, &wop2); | |
2803 | sim_fpu_to64 (&res, &ans); | |
2804 | result = res; | |
2805 | break; | |
8bae0a0c | 2806 | } |
50a2a691 AC |
2807 | default: |
2808 | fprintf (stderr, "Bad switch\n"); | |
2809 | abort (); | |
8bae0a0c JSC |
2810 | } |
2811 | ||
2812 | #ifdef DEBUG | |
53b9417e | 2813 | printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2814 | #endif /* DEBUG */ |
2815 | ||
2816 | return(result); | |
2817 | } | |
2818 | ||
18c64df6 | 2819 | uword64 UNUSED |
8bae0a0c | 2820 | Recip(op,fmt) |
e871dd18 | 2821 | uword64 op; |
8bae0a0c JSC |
2822 | FP_formats fmt; |
2823 | { | |
50a2a691 | 2824 | uword64 result = 0; |
8bae0a0c JSC |
2825 | |
2826 | #ifdef DEBUG | |
53b9417e | 2827 | printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2828 | #endif /* DEBUG */ |
2829 | ||
e871dd18 JSC |
2830 | /* The registers must specify FPRs valid for operands of type |
2831 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2832 | |
2833 | /* The format type should already have been checked: */ | |
2834 | switch (fmt) { | |
2835 | case fmt_single: | |
2836 | { | |
76ef4165 FL |
2837 | sim_fpu wop; |
2838 | sim_fpu ans; | |
2839 | unsigned32 res; | |
2840 | sim_fpu_32to (&wop, op); | |
2841 | sim_fpu_inv (&ans, &wop); | |
2842 | sim_fpu_to32 (&res, &ans); | |
2843 | result = res; | |
2844 | break; | |
8bae0a0c | 2845 | } |
8bae0a0c JSC |
2846 | case fmt_double: |
2847 | { | |
76ef4165 FL |
2848 | sim_fpu wop; |
2849 | sim_fpu ans; | |
2850 | unsigned64 res; | |
2851 | sim_fpu_64to (&wop, op); | |
2852 | sim_fpu_inv (&ans, &wop); | |
2853 | sim_fpu_to64 (&res, &ans); | |
2854 | result = res; | |
2855 | break; | |
8bae0a0c | 2856 | } |
50a2a691 AC |
2857 | default: |
2858 | fprintf (stderr, "Bad switch\n"); | |
2859 | abort (); | |
8bae0a0c JSC |
2860 | } |
2861 | ||
2862 | #ifdef DEBUG | |
53b9417e | 2863 | printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2864 | #endif /* DEBUG */ |
2865 | ||
2866 | return(result); | |
2867 | } | |
2868 | ||
18c64df6 | 2869 | uword64 |
8bae0a0c | 2870 | SquareRoot(op,fmt) |
e871dd18 | 2871 | uword64 op; |
8bae0a0c JSC |
2872 | FP_formats fmt; |
2873 | { | |
50a2a691 | 2874 | uword64 result = 0; |
8bae0a0c JSC |
2875 | |
2876 | #ifdef DEBUG | |
53b9417e | 2877 | printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2878 | #endif /* DEBUG */ |
2879 | ||
e871dd18 JSC |
2880 | /* The registers must specify FPRs valid for operands of type |
2881 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2882 | |
2883 | /* The format type should already have been checked: */ | |
2884 | switch (fmt) { | |
2885 | case fmt_single: | |
2886 | { | |
76ef4165 FL |
2887 | sim_fpu wop; |
2888 | sim_fpu ans; | |
2889 | unsigned32 res; | |
2890 | sim_fpu_32to (&wop, op); | |
2891 | sim_fpu_sqrt (&ans, &wop); | |
2892 | sim_fpu_to32 (&res, &ans); | |
2893 | result = res; | |
2894 | break; | |
8bae0a0c | 2895 | } |
8bae0a0c JSC |
2896 | case fmt_double: |
2897 | { | |
76ef4165 FL |
2898 | sim_fpu wop; |
2899 | sim_fpu ans; | |
2900 | unsigned64 res; | |
2901 | sim_fpu_64to (&wop, op); | |
2902 | sim_fpu_sqrt (&ans, &wop); | |
2903 | sim_fpu_to64 (&res, &ans); | |
2904 | result = res; | |
2905 | break; | |
8bae0a0c | 2906 | } |
50a2a691 AC |
2907 | default: |
2908 | fprintf (stderr, "Bad switch\n"); | |
2909 | abort (); | |
8bae0a0c JSC |
2910 | } |
2911 | ||
2912 | #ifdef DEBUG | |
53b9417e | 2913 | printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2914 | #endif /* DEBUG */ |
2915 | ||
2916 | return(result); | |
2917 | } | |
2918 | ||
a48e8c8d AC |
2919 | uword64 |
2920 | Max (uword64 op1, | |
2921 | uword64 op2, | |
2922 | FP_formats fmt) | |
2923 | { | |
2924 | int cmp; | |
2925 | unsigned64 result; | |
2926 | ||
2927 | #ifdef DEBUG | |
2928 | printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); | |
2929 | #endif /* DEBUG */ | |
2930 | ||
2931 | /* The registers must specify FPRs valid for operands of type | |
2932 | "fmt". If they are not valid, the result is undefined. */ | |
2933 | ||
2934 | /* The format type should already have been checked: */ | |
2935 | switch (fmt) | |
2936 | { | |
2937 | case fmt_single: | |
2938 | { | |
2939 | sim_fpu wop1; | |
2940 | sim_fpu wop2; | |
2941 | sim_fpu_32to (&wop1, op1); | |
2942 | sim_fpu_32to (&wop2, op2); | |
2943 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
2944 | break; | |
2945 | } | |
2946 | case fmt_double: | |
2947 | { | |
2948 | sim_fpu wop1; | |
2949 | sim_fpu wop2; | |
2950 | sim_fpu_64to (&wop1, op1); | |
2951 | sim_fpu_64to (&wop2, op2); | |
2952 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
2953 | break; | |
2954 | } | |
2955 | default: | |
2956 | fprintf (stderr, "Bad switch\n"); | |
2957 | abort (); | |
2958 | } | |
2959 | ||
2960 | switch (cmp) | |
2961 | { | |
2962 | case SIM_FPU_IS_SNAN: | |
2963 | case SIM_FPU_IS_QNAN: | |
2964 | result = op1; | |
2965 | case SIM_FPU_IS_NINF: | |
2966 | case SIM_FPU_IS_NNUMBER: | |
2967 | case SIM_FPU_IS_NDENORM: | |
2968 | case SIM_FPU_IS_NZERO: | |
2969 | result = op2; /* op1 - op2 < 0 */ | |
2970 | case SIM_FPU_IS_PINF: | |
2971 | case SIM_FPU_IS_PNUMBER: | |
2972 | case SIM_FPU_IS_PDENORM: | |
2973 | case SIM_FPU_IS_PZERO: | |
2974 | result = op1; /* op1 - op2 > 0 */ | |
2975 | default: | |
2976 | fprintf (stderr, "Bad switch\n"); | |
2977 | abort (); | |
2978 | } | |
2979 | ||
2980 | #ifdef DEBUG | |
2981 | printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); | |
2982 | #endif /* DEBUG */ | |
2983 | ||
2984 | return(result); | |
2985 | } | |
2986 | ||
2987 | uword64 | |
2988 | Min (uword64 op1, | |
2989 | uword64 op2, | |
2990 | FP_formats fmt) | |
2991 | { | |
2992 | int cmp; | |
2993 | unsigned64 result; | |
2994 | ||
2995 | #ifdef DEBUG | |
2996 | printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); | |
2997 | #endif /* DEBUG */ | |
2998 | ||
2999 | /* The registers must specify FPRs valid for operands of type | |
3000 | "fmt". If they are not valid, the result is undefined. */ | |
3001 | ||
3002 | /* The format type should already have been checked: */ | |
3003 | switch (fmt) | |
3004 | { | |
3005 | case fmt_single: | |
3006 | { | |
3007 | sim_fpu wop1; | |
3008 | sim_fpu wop2; | |
3009 | sim_fpu_32to (&wop1, op1); | |
3010 | sim_fpu_32to (&wop2, op2); | |
3011 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
3012 | break; | |
3013 | } | |
3014 | case fmt_double: | |
3015 | { | |
3016 | sim_fpu wop1; | |
3017 | sim_fpu wop2; | |
3018 | sim_fpu_64to (&wop1, op1); | |
3019 | sim_fpu_64to (&wop2, op2); | |
3020 | cmp = sim_fpu_cmp (&wop1, &wop2); | |
3021 | break; | |
3022 | } | |
3023 | default: | |
3024 | fprintf (stderr, "Bad switch\n"); | |
3025 | abort (); | |
3026 | } | |
3027 | ||
3028 | switch (cmp) | |
3029 | { | |
3030 | case SIM_FPU_IS_SNAN: | |
3031 | case SIM_FPU_IS_QNAN: | |
3032 | result = op1; | |
3033 | case SIM_FPU_IS_NINF: | |
3034 | case SIM_FPU_IS_NNUMBER: | |
3035 | case SIM_FPU_IS_NDENORM: | |
3036 | case SIM_FPU_IS_NZERO: | |
3037 | result = op1; /* op1 - op2 < 0 */ | |
3038 | case SIM_FPU_IS_PINF: | |
3039 | case SIM_FPU_IS_PNUMBER: | |
3040 | case SIM_FPU_IS_PDENORM: | |
3041 | case SIM_FPU_IS_PZERO: | |
3042 | result = op2; /* op1 - op2 > 0 */ | |
3043 | default: | |
3044 | fprintf (stderr, "Bad switch\n"); | |
3045 | abort (); | |
3046 | } | |
3047 | ||
3048 | #ifdef DEBUG | |
3049 | printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); | |
3050 | #endif /* DEBUG */ | |
3051 | ||
3052 | return(result); | |
3053 | } | |
3054 | ||
18c64df6 | 3055 | uword64 |
01737f42 AC |
3056 | convert (SIM_DESC sd, |
3057 | sim_cpu *cpu, | |
3058 | address_word cia, | |
3059 | int rm, | |
3060 | uword64 op, | |
3061 | FP_formats from, | |
3062 | FP_formats to) | |
8bae0a0c | 3063 | { |
76ef4165 FL |
3064 | sim_fpu wop; |
3065 | sim_fpu_round round; | |
3066 | unsigned32 result32; | |
3067 | unsigned64 result64; | |
8bae0a0c JSC |
3068 | |
3069 | #ifdef DEBUG | |
53b9417e | 3070 | printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC)); |
8bae0a0c JSC |
3071 | #endif /* DEBUG */ |
3072 | ||
76ef4165 | 3073 | switch (rm) |
8bae0a0c | 3074 | { |
76ef4165 FL |
3075 | case FP_RM_NEAREST: |
3076 | /* Round result to nearest representable value. When two | |
3077 | representable values are equally near, round to the value | |
3078 | that has a least significant bit of zero (i.e. is even). */ | |
3079 | round = sim_fpu_round_near; | |
3080 | break; | |
3081 | case FP_RM_TOZERO: | |
3082 | /* Round result to the value closest to, and not greater in | |
3083 | magnitude than, the result. */ | |
3084 | round = sim_fpu_round_zero; | |
3085 | break; | |
3086 | case FP_RM_TOPINF: | |
3087 | /* Round result to the value closest to, and not less than, | |
3088 | the result. */ | |
3089 | round = sim_fpu_round_up; | |
3090 | break; | |
3091 | ||
3092 | case FP_RM_TOMINF: | |
3093 | /* Round result to the value closest to, and not greater than, | |
3094 | the result. */ | |
3095 | round = sim_fpu_round_down; | |
3096 | break; | |
3097 | default: | |
3098 | round = 0; | |
3099 | fprintf (stderr, "Bad switch\n"); | |
3100 | abort (); | |
8bae0a0c | 3101 | } |
76ef4165 FL |
3102 | |
3103 | /* Convert the input to sim_fpu internal format */ | |
3104 | switch (from) | |
8bae0a0c | 3105 | { |
76ef4165 FL |
3106 | case fmt_double: |
3107 | sim_fpu_64to (&wop, op); | |
3108 | break; | |
3109 | case fmt_single: | |
3110 | sim_fpu_32to (&wop, op); | |
3111 | break; | |
3112 | case fmt_word: | |
3113 | sim_fpu_i32to (&wop, op, round); | |
3114 | break; | |
3115 | case fmt_long: | |
3116 | sim_fpu_i64to (&wop, op, round); | |
3117 | break; | |
3118 | default: | |
3119 | fprintf (stderr, "Bad switch\n"); | |
3120 | abort (); | |
8bae0a0c | 3121 | } |
8bae0a0c | 3122 | |
76ef4165 FL |
3123 | /* Convert sim_fpu format into the output */ |
3124 | /* The value WOP is converted to the destination format, rounding | |
3125 | using mode RM. When the destination is a fixed-point format, then | |
3126 | a source value of Infinity, NaN or one which would round to an | |
3127 | integer outside the fixed point range then an IEEE Invalid | |
3128 | Operation condition is raised. */ | |
3129 | switch (to) | |
3130 | { | |
3131 | case fmt_single: | |
3132 | sim_fpu_round_32 (&wop, round, 0); | |
3133 | sim_fpu_to32 (&result32, &wop); | |
3134 | result64 = result32; | |
3135 | break; | |
3136 | case fmt_double: | |
3137 | sim_fpu_round_64 (&wop, round, 0); | |
3138 | sim_fpu_to64 (&result64, &wop); | |
3139 | break; | |
3140 | case fmt_word: | |
3141 | sim_fpu_to32i (&result32, &wop, round); | |
3142 | result64 = result32; | |
3143 | break; | |
3144 | case fmt_long: | |
3145 | sim_fpu_to64i (&result64, &wop, round); | |
3146 | break; | |
3147 | default: | |
3148 | result64 = 0; | |
3149 | fprintf (stderr, "Bad switch\n"); | |
3150 | abort (); | |
8bae0a0c | 3151 | } |
76ef4165 | 3152 | |
8bae0a0c | 3153 | #ifdef DEBUG |
76ef4165 | 3154 | printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to)); |
8bae0a0c JSC |
3155 | #endif /* DEBUG */ |
3156 | ||
76ef4165 | 3157 | return(result64); |
8bae0a0c | 3158 | } |
8bae0a0c | 3159 | |
76ef4165 | 3160 | |
8bae0a0c JSC |
3161 | /*-- co-processor support routines ------------------------------------------*/ |
3162 | ||
2f2e6c5d | 3163 | static int UNUSED |
8bae0a0c JSC |
3164 | CoProcPresent(coproc_number) |
3165 | unsigned int coproc_number; | |
3166 | { | |
3167 | /* Return TRUE if simulator provides a model for the given co-processor number */ | |
3168 | return(0); | |
3169 | } | |
3170 | ||
18c64df6 | 3171 | void |
01737f42 AC |
3172 | cop_lw (SIM_DESC sd, |
3173 | sim_cpu *cpu, | |
3174 | address_word cia, | |
3175 | int coproc_num, | |
3176 | int coproc_reg, | |
3177 | unsigned int memword) | |
8bae0a0c | 3178 | { |
192ae475 AC |
3179 | switch (coproc_num) |
3180 | { | |
8bae0a0c | 3181 | case 1: |
192ae475 AC |
3182 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3183 | { | |
8bae0a0c | 3184 | #ifdef DEBUG |
192ae475 | 3185 | printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword)); |
8bae0a0c | 3186 | #endif |
192ae475 AC |
3187 | StoreFPR(coproc_reg,fmt_word,(uword64)memword); |
3188 | FPR_STATE[coproc_reg] = fmt_uninterpreted; | |
3189 | break; | |
3190 | } | |
8bae0a0c JSC |
3191 | |
3192 | default: | |
f24b7b69 | 3193 | #if 0 /* this should be controlled by a configuration option */ |
192ae475 | 3194 | sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia)); |
f24b7b69 | 3195 | #endif |
192ae475 AC |
3196 | break; |
3197 | } | |
8bae0a0c JSC |
3198 | |
3199 | return; | |
3200 | } | |
3201 | ||
18c64df6 | 3202 | void |
01737f42 AC |
3203 | cop_ld (SIM_DESC sd, |
3204 | sim_cpu *cpu, | |
3205 | address_word cia, | |
3206 | int coproc_num, | |
3207 | int coproc_reg, | |
3208 | uword64 memword) | |
8bae0a0c JSC |
3209 | { |
3210 | switch (coproc_num) { | |
8bae0a0c | 3211 | case 1: |
192ae475 AC |
3212 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3213 | { | |
3214 | StoreFPR(coproc_reg,fmt_uninterpreted,memword); | |
3215 | break; | |
3216 | } | |
8bae0a0c JSC |
3217 | |
3218 | default: | |
f24b7b69 | 3219 | #if 0 /* this message should be controlled by a configuration option */ |
95469ceb | 3220 | sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia)); |
f24b7b69 | 3221 | #endif |
8bae0a0c JSC |
3222 | break; |
3223 | } | |
3224 | ||
3225 | return; | |
3226 | } | |
3227 | ||
18c64df6 | 3228 | unsigned int |
01737f42 AC |
3229 | cop_sw (SIM_DESC sd, |
3230 | sim_cpu *cpu, | |
3231 | address_word cia, | |
3232 | int coproc_num, | |
3233 | int coproc_reg) | |
8bae0a0c JSC |
3234 | { |
3235 | unsigned int value = 0; | |
da0bce9c | 3236 | |
192ae475 AC |
3237 | switch (coproc_num) |
3238 | { | |
8bae0a0c | 3239 | case 1: |
192ae475 AC |
3240 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3241 | { | |
3242 | FP_formats hold; | |
3243 | hold = FPR_STATE[coproc_reg]; | |
3244 | FPR_STATE[coproc_reg] = fmt_word; | |
3245 | value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted); | |
3246 | FPR_STATE[coproc_reg] = hold; | |
3247 | break; | |
3248 | } | |
8bae0a0c JSC |
3249 | |
3250 | default: | |
f24b7b69 | 3251 | #if 0 /* should be controlled by configuration option */ |
192ae475 | 3252 | sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); |
f24b7b69 | 3253 | #endif |
192ae475 AC |
3254 | break; |
3255 | } | |
8bae0a0c JSC |
3256 | |
3257 | return(value); | |
3258 | } | |
3259 | ||
18c64df6 | 3260 | uword64 |
01737f42 AC |
3261 | cop_sd (SIM_DESC sd, |
3262 | sim_cpu *cpu, | |
3263 | address_word cia, | |
3264 | int coproc_num, | |
3265 | int coproc_reg) | |
8bae0a0c | 3266 | { |
e871dd18 | 3267 | uword64 value = 0; |
192ae475 AC |
3268 | switch (coproc_num) |
3269 | { | |
8bae0a0c | 3270 | case 1: |
192ae475 AC |
3271 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) |
3272 | { | |
3273 | value = ValueFPR(coproc_reg,fmt_uninterpreted); | |
3274 | break; | |
3275 | } | |
8bae0a0c JSC |
3276 | |
3277 | default: | |
f24b7b69 | 3278 | #if 0 /* should be controlled by configuration option */ |
192ae475 | 3279 | sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); |
f24b7b69 | 3280 | #endif |
192ae475 AC |
3281 | break; |
3282 | } | |
8bae0a0c JSC |
3283 | |
3284 | return(value); | |
3285 | } | |
3286 | ||
ea985d24 | 3287 | void |
01737f42 AC |
3288 | decode_coproc (SIM_DESC sd, |
3289 | sim_cpu *cpu, | |
3290 | address_word cia, | |
3291 | unsigned int instruction) | |
8bae0a0c JSC |
3292 | { |
3293 | int coprocnum = ((instruction >> 26) & 3); | |
3294 | ||
56e7c849 AC |
3295 | switch (coprocnum) |
3296 | { | |
8bae0a0c JSC |
3297 | case 0: /* standard CPU control and cache registers */ |
3298 | { | |
8bae0a0c JSC |
3299 | int code = ((instruction >> 21) & 0x1F); |
3300 | /* R4000 Users Manual (second edition) lists the following CP0 | |
3301 | instructions: | |
56e7c849 AC |
3302 | DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000) |
3303 | DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000) | |
3304 | MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000) | |
3305 | MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000) | |
3306 | TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001) | |
3307 | TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010) | |
3308 | TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110) | |
3309 | TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000) | |
3310 | CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii) | |
3311 | ERET Exception return (VR4100 = 01000010000000000000000000011000) | |
3312 | */ | |
3313 | if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0)) | |
3314 | { | |
3315 | int rt = ((instruction >> 16) & 0x1F); | |
3316 | int rd = ((instruction >> 11) & 0x1F); | |
3317 | ||
3318 | switch (rd) /* NOTEs: Standard CP0 registers */ | |
3319 | { | |
3320 | /* 0 = Index R4000 VR4100 VR4300 */ | |
3321 | /* 1 = Random R4000 VR4100 VR4300 */ | |
3322 | /* 2 = EntryLo0 R4000 VR4100 VR4300 */ | |
3323 | /* 3 = EntryLo1 R4000 VR4100 VR4300 */ | |
3324 | /* 4 = Context R4000 VR4100 VR4300 */ | |
3325 | /* 5 = PageMask R4000 VR4100 VR4300 */ | |
3326 | /* 6 = Wired R4000 VR4100 VR4300 */ | |
3327 | /* 8 = BadVAddr R4000 VR4100 VR4300 */ | |
3328 | /* 9 = Count R4000 VR4100 VR4300 */ | |
3329 | /* 10 = EntryHi R4000 VR4100 VR4300 */ | |
3330 | /* 11 = Compare R4000 VR4100 VR4300 */ | |
3331 | /* 12 = SR R4000 VR4100 VR4300 */ | |
3332 | case 12: | |
3333 | if (code == 0x00) | |
3334 | GPR[rt] = SR; | |
3335 | else | |
3336 | SR = GPR[rt]; | |
3337 | break; | |
3338 | /* 13 = Cause R4000 VR4100 VR4300 */ | |
05d1322f JL |
3339 | case 13: |
3340 | if (code == 0x00) | |
3341 | GPR[rt] = CAUSE; | |
3342 | else | |
3343 | CAUSE = GPR[rt]; | |
3344 | break; | |
56e7c849 AC |
3345 | /* 14 = EPC R4000 VR4100 VR4300 */ |
3346 | /* 15 = PRId R4000 VR4100 VR4300 */ | |
6eedf3f4 MA |
3347 | #ifdef SUBTARGET_R3900 |
3348 | /* 16 = Debug */ | |
3349 | case 16: | |
3350 | if (code == 0x00) | |
3351 | GPR[rt] = Debug; | |
3352 | else | |
3353 | Debug = GPR[rt]; | |
3354 | break; | |
3355 | #else | |
56e7c849 | 3356 | /* 16 = Config R4000 VR4100 VR4300 */ |
a09a30d2 AC |
3357 | case 16: |
3358 | if (code == 0x00) | |
3359 | GPR[rt] = C0_CONFIG; | |
3360 | else | |
3361 | C0_CONFIG = GPR[rt]; | |
3362 | break; | |
6eedf3f4 MA |
3363 | #endif |
3364 | #ifdef SUBTARGET_R3900 | |
3365 | /* 17 = Debug */ | |
3366 | case 17: | |
3367 | if (code == 0x00) | |
3368 | GPR[rt] = DEPC; | |
3369 | else | |
3370 | DEPC = GPR[rt]; | |
3371 | break; | |
3372 | #else | |
56e7c849 | 3373 | /* 17 = LLAddr R4000 VR4100 VR4300 */ |
6eedf3f4 | 3374 | #endif |
56e7c849 AC |
3375 | /* 18 = WatchLo R4000 VR4100 VR4300 */ |
3376 | /* 19 = WatchHi R4000 VR4100 VR4300 */ | |
3377 | /* 20 = XContext R4000 VR4100 VR4300 */ | |
3378 | /* 26 = PErr or ECC R4000 VR4100 VR4300 */ | |
3379 | /* 27 = CacheErr R4000 VR4100 */ | |
3380 | /* 28 = TagLo R4000 VR4100 VR4300 */ | |
3381 | /* 29 = TagHi R4000 VR4100 VR4300 */ | |
3382 | /* 30 = ErrorEPC R4000 VR4100 VR4300 */ | |
3383 | GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */ | |
3384 | /* CPR[0,rd] = GPR[rt]; */ | |
3385 | default: | |
3386 | if (code == 0x00) | |
18c64df6 | 3387 | sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 | 3388 | else |
18c64df6 | 3389 | sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 AC |
3390 | } |
3391 | } | |
3392 | else if (code == 0x10 && (instruction & 0x3f) == 0x18) | |
3393 | { | |
3394 | /* ERET */ | |
3395 | if (SR & status_ERL) | |
3396 | { | |
3397 | /* Oops, not yet available */ | |
18c64df6 | 3398 | sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet"); |
56e7c849 AC |
3399 | PC = EPC; |
3400 | SR &= ~status_ERL; | |
3401 | } | |
3402 | else | |
3403 | { | |
3404 | PC = EPC; | |
3405 | SR &= ~status_EXL; | |
3406 | } | |
3407 | } | |
6eedf3f4 MA |
3408 | else if (code == 0x10 && (instruction & 0x3f) == 0x10) |
3409 | { | |
3410 | /* RFE */ | |
3411 | } | |
3412 | else if (code == 0x10 && (instruction & 0x3f) == 0x1F) | |
3413 | { | |
3414 | /* DERET */ | |
3415 | Debug &= ~Debug_DM; | |
3416 | DELAYSLOT(); | |
3417 | DSPC = DEPC; | |
3418 | } | |
56e7c849 | 3419 | else |
95469ceb | 3420 | sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia)); |
e871dd18 | 3421 | /* TODO: When executing an ERET or RFE instruction we should |
8bae0a0c JSC |
3422 | clear LLBIT, to ensure that any out-standing atomic |
3423 | read/modify/write sequence fails. */ | |
3424 | } | |
56e7c849 AC |
3425 | break; |
3426 | ||
8bae0a0c | 3427 | case 2: /* undefined co-processor */ |
95469ceb | 3428 | sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia)); |
8bae0a0c | 3429 | break; |
56e7c849 | 3430 | |
8bae0a0c JSC |
3431 | case 1: /* should not occur (FPU co-processor) */ |
3432 | case 3: /* should not occur (FPU co-processor) */ | |
3433 | SignalException(ReservedInstruction,instruction); | |
3434 | break; | |
56e7c849 AC |
3435 | } |
3436 | ||
8bae0a0c JSC |
3437 | return; |
3438 | } | |
3439 | ||
3440 | /*-- instruction simulation -------------------------------------------------*/ | |
3441 | ||
16bd5d6e AC |
3442 | /* When the IGEN simulator is being built, the function below is be |
3443 | replaced by a generated version. However, WITH_IGEN == 2 indicates | |
3444 | that the fubction below should be compiled but under a different | |
3445 | name (to allow backward compatibility) */ | |
3446 | ||
3447 | #if (WITH_IGEN != 1) | |
3448 | #if (WITH_IGEN > 1) | |
dad6f1f3 AC |
3449 | void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal)); |
3450 | void | |
9ec6741b | 3451 | old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal) |
dad6f1f3 | 3452 | #else |
2e61a3ad | 3453 | void |
9ec6741b | 3454 | sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal) |
dad6f1f3 | 3455 | #endif |
2e61a3ad AC |
3456 | SIM_DESC sd; |
3457 | int next_cpu_nr; /* ignore */ | |
9ec6741b | 3458 | int nr_cpus; /* ignore */ |
2e61a3ad | 3459 | int siggnal; /* ignore */ |
8bae0a0c | 3460 | { |
01737f42 | 3461 | sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */ |
50a2a691 | 3462 | #if !defined(FASTSIM) |
8bae0a0c | 3463 | unsigned int pipeline_count = 1; |
50a2a691 | 3464 | #endif |
8bae0a0c JSC |
3465 | |
3466 | #ifdef DEBUG | |
50a2a691 | 3467 | if (STATE_MEMORY (sd) == NULL) { |
8bae0a0c JSC |
3468 | printf("DBG: simulate() entered with no memory\n"); |
3469 | exit(1); | |
3470 | } | |
3471 | #endif /* DEBUG */ | |
3472 | ||
3473 | #if 0 /* Disabled to check that everything works OK */ | |
3474 | /* The VR4300 seems to sign-extend the PC on its first | |
3475 | access. However, this may just be because it is currently | |
3476 | configured in 32bit mode. However... */ | |
3477 | PC = SIGNEXTEND(PC,32); | |
3478 | #endif | |
3479 | ||
3480 | /* main controlling loop */ | |
2e61a3ad | 3481 | while (1) { |
7ce8b917 AC |
3482 | /* vaddr is slowly being replaced with cia - current instruction |
3483 | address */ | |
3484 | address_word cia = (uword64)PC; | |
3485 | address_word vaddr = cia; | |
dad6f1f3 | 3486 | address_word paddr; |
8bae0a0c | 3487 | int cca; |
53b9417e | 3488 | unsigned int instruction; /* uword64? what's this used for? FIXME! */ |
8bae0a0c JSC |
3489 | |
3490 | #ifdef DEBUG | |
3491 | { | |
3492 | printf("DBG: state = 0x%08X :",state); | |
8bae0a0c JSC |
3493 | if (state & simHALTEX) printf(" simHALTEX"); |
3494 | if (state & simHALTIN) printf(" simHALTIN"); | |
53b9417e | 3495 | printf("\n"); |
8bae0a0c JSC |
3496 | } |
3497 | #endif /* DEBUG */ | |
3498 | ||
0c2c5f61 | 3499 | DSSTATE = (STATE & simDELAYSLOT); |
8bae0a0c JSC |
3500 | #ifdef DEBUG |
3501 | if (dsstate) | |
18c64df6 | 3502 | sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3503 | #endif /* DEBUG */ |
3504 | ||
7ce8b917 AC |
3505 | /* Fetch the next instruction from the simulator memory: */ |
3506 | if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { | |
6429b296 JW |
3507 | if ((vaddr & 1) == 0) { |
3508 | /* Copy the action of the LW instruction */ | |
3509 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
3510 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
3511 | uword64 value; | |
3512 | unsigned int byte; | |
3513 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
53b9417e | 3514 | LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL); |
6429b296 JW |
3515 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); |
3516 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
3517 | } else { | |
3518 | /* Copy the action of the LH instruction */ | |
3519 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0); | |
3520 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0); | |
3521 | uword64 value; | |
3522 | unsigned int byte; | |
3523 | paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK) | |
3524 | | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1))); | |
53b9417e | 3525 | LoadMemory(&value,NULL,cca, AccessLength_HALFWORD, |
6429b296 JW |
3526 | paddr & ~ (uword64) 1, |
3527 | vaddr, isINSTRUCTION, isREAL); | |
3528 | byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1)); | |
3529 | instruction = ((value >> (8 * byte)) & 0xFFFF); | |
3530 | } | |
8bae0a0c | 3531 | } else { |
53b9417e | 3532 | fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC)); |
8bae0a0c JSC |
3533 | exit(1); |
3534 | } | |
3535 | ||
3536 | #ifdef DEBUG | |
18c64df6 | 3537 | sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC)); |
8bae0a0c JSC |
3538 | #endif /* DEBUG */ |
3539 | ||
8bae0a0c JSC |
3540 | /* This is required by exception processing, to ensure that we can |
3541 | cope with exceptions in the delay slots of branches that may | |
3542 | already have changed the PC. */ | |
6429b296 JW |
3543 | if ((vaddr & 1) == 0) |
3544 | PC += 4; /* increment ready for the next fetch */ | |
3545 | else | |
3546 | PC += 2; | |
8bae0a0c JSC |
3547 | /* NOTE: If we perform a delay slot change to the PC, this |
3548 | increment is not requuired. However, it would make the | |
3549 | simulator more complicated to try and avoid this small hit. */ | |
3550 | ||
3551 | /* Currently this code provides a simple model. For more | |
3552 | complicated models we could perform exception status checks at | |
3553 | this point, and set the simSTOP state as required. This could | |
3554 | also include processing any hardware interrupts raised by any | |
3555 | I/O model attached to the simulator context. | |
3556 | ||
3557 | Support for "asynchronous" I/O events within the simulated world | |
3558 | could be providing by managing a counter, and calling a I/O | |
3559 | specific handler when a particular threshold is reached. On most | |
3560 | architectures a decrement and check for zero operation is | |
3561 | usually quicker than an increment and compare. However, the | |
3562 | process of managing a known value decrement to zero, is higher | |
3563 | than the cost of using an explicit value UINT_MAX into the | |
3564 | future. Which system is used will depend on how complicated the | |
3565 | I/O model is, and how much it is likely to affect the simulator | |
3566 | bandwidth. | |
3567 | ||
3568 | If events need to be scheduled further in the future than | |
3569 | UINT_MAX event ticks, then the I/O model should just provide its | |
3570 | own counter, triggered from the event system. */ | |
3571 | ||
3572 | /* MIPS pipeline ticks. To allow for future support where the | |
3573 | pipeline hit of individual instructions is known, this control | |
3574 | loop manages a "pipeline_count" variable. It is initialised to | |
3575 | 1 (one), and will only be changed by the simulator engine when | |
3576 | executing an instruction. If the engine does not have access to | |
3577 | pipeline cycle count information then all instructions will be | |
3578 | treated as using a single cycle. NOTE: A standard system is not | |
3579 | provided by the default simulator because different MIPS | |
3580 | architectures have different cycle counts for the same | |
50a2a691 AC |
3581 | instructions. |
3582 | ||
3583 | [NOTE: pipeline_count has been replaced the event queue] */ | |
8bae0a0c | 3584 | |
a09a30d2 AC |
3585 | /* shuffle the floating point status pipeline state */ |
3586 | ENGINE_ISSUE_PREFIX_HOOK(); | |
8bae0a0c JSC |
3587 | |
3588 | /* NOTE: For multi-context simulation environments the "instruction" | |
3589 | variable should be local to this routine. */ | |
3590 | ||
3591 | /* Shorthand accesses for engine. Note: If we wanted to use global | |
3592 | variables (and a single-threaded simulator engine), then we can | |
3593 | create the actual variables with these names. */ | |
3594 | ||
0c2c5f61 | 3595 | if (!(STATE & simSKIPNEXT)) { |
8bae0a0c | 3596 | /* Include the simulator engine */ |
284e759d | 3597 | #include "oengine.c" |
f24b7b69 | 3598 | #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT) |
8bae0a0c JSC |
3599 | #error "Mismatch between run-time simulator code and simulation engine" |
3600 | #endif | |
18c64df6 AC |
3601 | #if (WITH_TARGET_WORD_BITSIZE != GPRLEN) |
3602 | #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN" | |
3603 | #endif | |
76ef4165 | 3604 | #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU)) |
18c64df6 AC |
3605 | #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU" |
3606 | #endif | |
8bae0a0c JSC |
3607 | |
3608 | #if defined(WARN_LOHI) | |
3609 | /* Decrement the HI/LO validity ticks */ | |
3610 | if (HIACCESS > 0) | |
3611 | HIACCESS--; | |
3612 | if (LOACCESS > 0) | |
3613 | LOACCESS--; | |
0425cfb3 | 3614 | /* start-sanitize-r5900 */ |
53b9417e DE |
3615 | if (HI1ACCESS > 0) |
3616 | HI1ACCESS--; | |
3617 | if (LO1ACCESS > 0) | |
3618 | LO1ACCESS--; | |
0425cfb3 | 3619 | /* end-sanitize-r5900 */ |
8bae0a0c JSC |
3620 | #endif /* WARN_LOHI */ |
3621 | ||
8bae0a0c JSC |
3622 | /* For certain MIPS architectures, GPR[0] is hardwired to zero. We |
3623 | should check for it being changed. It is better doing it here, | |
3624 | than within the simulator, since it will help keep the simulator | |
3625 | small. */ | |
3626 | if (ZERO != 0) { | |
05d1322f | 3627 | #if defined(WARN_ZERO) |
95469ceb | 3628 | sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia)); |
05d1322f | 3629 | #endif /* WARN_ZERO */ |
8bae0a0c JSC |
3630 | ZERO = 0; /* reset back to zero before next instruction */ |
3631 | } | |
8bae0a0c | 3632 | } else /* simSKIPNEXT check */ |
0c2c5f61 | 3633 | STATE &= ~simSKIPNEXT; |
8bae0a0c JSC |
3634 | |
3635 | /* If the delay slot was active before the instruction is | |
3636 | executed, then update the PC to its new value: */ | |
0c2c5f61 | 3637 | if (DSSTATE) { |
8bae0a0c | 3638 | #ifdef DEBUG |
53b9417e | 3639 | printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3640 | #endif /* DEBUG */ |
3641 | PC = DSPC; | |
6eedf3f4 | 3642 | CANCELDELAYSLOT(); |
8bae0a0c JSC |
3643 | } |
3644 | ||
2acd126a AC |
3645 | if (MIPSISA < 4) |
3646 | PENDING_TICK(); | |
8bae0a0c JSC |
3647 | |
3648 | #if !defined(FASTSIM) | |
50a2a691 AC |
3649 | if (sim_events_tickn (sd, pipeline_count)) |
3650 | { | |
3651 | /* cpu->cia = cia; */ | |
3652 | sim_events_process (sd); | |
3653 | } | |
3654 | #else | |
2e61a3ad AC |
3655 | if (sim_events_tick (sd)) |
3656 | { | |
3657 | /* cpu->cia = cia; */ | |
3658 | sim_events_process (sd); | |
3659 | } | |
50a2a691 | 3660 | #endif /* FASTSIM */ |
8bae0a0c | 3661 | } |
8bae0a0c | 3662 | } |
16bd5d6e AC |
3663 | #endif |
3664 | ||
8bae0a0c | 3665 | |
53b9417e DE |
3666 | /* This code copied from gdb's utils.c. Would like to share this code, |
3667 | but don't know of a common place where both could get to it. */ | |
3668 | ||
3669 | /* Temporary storage using circular buffer */ | |
3670 | #define NUMCELLS 16 | |
3671 | #define CELLSIZE 32 | |
3672 | static char* | |
3673 | get_cell() | |
3674 | { | |
3675 | static char buf[NUMCELLS][CELLSIZE]; | |
3676 | static int cell=0; | |
3677 | if (++cell>=NUMCELLS) cell=0; | |
3678 | return buf[cell]; | |
3679 | } | |
3680 | ||
3681 | /* Print routines to handle variable size regs, etc */ | |
3682 | ||
3683 | /* Eliminate warning from compiler on 32-bit systems */ | |
3684 | static int thirty_two = 32; | |
3685 | ||
3686 | char* | |
3687 | pr_addr(addr) | |
3688 | SIM_ADDR addr; | |
3689 | { | |
3690 | char *paddr_str=get_cell(); | |
3691 | switch (sizeof(addr)) | |
3692 | { | |
3693 | case 8: | |
50a2a691 | 3694 | sprintf(paddr_str,"%08lx%08lx", |
53b9417e DE |
3695 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3696 | break; | |
3697 | case 4: | |
50a2a691 | 3698 | sprintf(paddr_str,"%08lx",(unsigned long)addr); |
53b9417e DE |
3699 | break; |
3700 | case 2: | |
3701 | sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff)); | |
3702 | break; | |
3703 | default: | |
3704 | sprintf(paddr_str,"%x",addr); | |
3705 | } | |
3706 | return paddr_str; | |
3707 | } | |
3708 | ||
87e43259 AC |
3709 | char* |
3710 | pr_uword64(addr) | |
3711 | uword64 addr; | |
3712 | { | |
3713 | char *paddr_str=get_cell(); | |
50a2a691 | 3714 | sprintf(paddr_str,"%08lx%08lx", |
87e43259 AC |
3715 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3716 | return paddr_str; | |
3717 | } | |
3718 | ||
3719 | ||
2acd126a AC |
3720 | void |
3721 | pending_tick (SIM_DESC sd, | |
3722 | sim_cpu *cpu, | |
3723 | address_word cia) | |
3724 | { | |
3725 | if (PENDING_TRACE) | |
3726 | sim_io_printf (sd, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN, PENDING_OUT, PENDING_TOTAL); | |
3727 | if (PENDING_OUT != PENDING_IN) | |
3728 | { | |
3729 | int loop; | |
3730 | int index = PENDING_OUT; | |
3731 | int total = PENDING_TOTAL; | |
3732 | if (PENDING_TOTAL == 0) | |
3733 | sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n"); | |
3734 | for (loop = 0; (loop < total); loop++) | |
3735 | { | |
3736 | if (PENDING_SLOT_DEST[index] != NULL) | |
3737 | { | |
3738 | PENDING_SLOT_DELAY[index] -= 1; | |
3739 | if (PENDING_SLOT_DELAY[index] == 0) | |
3740 | { | |
3741 | if (PENDING_SLOT_BIT[index] >= 0) | |
3742 | switch (PENDING_SLOT_SIZE[index]) | |
3743 | { | |
3744 | case 32: | |
3745 | if (PENDING_SLOT_VALUE[index]) | |
3746 | *(unsigned32*)PENDING_SLOT_DEST[index] |= | |
3747 | BIT32 (PENDING_SLOT_BIT[index]); | |
3748 | else | |
3749 | *(unsigned32*)PENDING_SLOT_DEST[index] &= | |
3750 | BIT32 (PENDING_SLOT_BIT[index]); | |
3751 | break; | |
3752 | case 64: | |
3753 | if (PENDING_SLOT_VALUE[index]) | |
3754 | *(unsigned64*)PENDING_SLOT_DEST[index] |= | |
3755 | BIT64 (PENDING_SLOT_BIT[index]); | |
3756 | else | |
3757 | *(unsigned64*)PENDING_SLOT_DEST[index] &= | |
3758 | BIT64 (PENDING_SLOT_BIT[index]); | |
3759 | break; | |
3760 | break; | |
3761 | } | |
3762 | else | |
3763 | switch (PENDING_SLOT_SIZE[index]) | |
3764 | { | |
3765 | case 32: | |
3766 | *(unsigned32*)PENDING_SLOT_DEST[index] = | |
3767 | PENDING_SLOT_VALUE[index]; | |
3768 | break; | |
3769 | case 64: | |
3770 | *(unsigned64*)PENDING_SLOT_DEST[index] = | |
3771 | PENDING_SLOT_VALUE[index]; | |
3772 | break; | |
3773 | } | |
3774 | } | |
3775 | if (PENDING_OUT == index) | |
3776 | { | |
3777 | PENDING_SLOT_DEST[index] = NULL; | |
3778 | PENDING_OUT = (PENDING_OUT + 1) % PSLOTS; | |
3779 | PENDING_TOTAL--; | |
3780 | } | |
3781 | } | |
3782 | } | |
3783 | index = (index + 1) % PSLOTS; | |
3784 | } | |
3785 | } | |
3786 | ||
8bae0a0c JSC |
3787 | /*---------------------------------------------------------------------------*/ |
3788 | /*> EOF interp.c <*/ |