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c906108c SS |
1 | /*> interp.c <*/ |
2 | /* Simulator for the MIPS architecture. | |
3 | ||
4 | This file is part of the MIPS sim | |
5 | ||
6 | THIS SOFTWARE IS NOT COPYRIGHTED | |
7 | ||
8 | Cygnus offers the following for use in the public domain. Cygnus | |
9 | makes no warranty with regard to the software or it's performance | |
10 | and the user accepts the software "AS IS" with all faults. | |
11 | ||
12 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
13 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
14 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
15 | ||
c906108c SS |
16 | NOTEs: |
17 | ||
18 | The IDT monitor (found on the VR4300 board), seems to lie about | |
19 | register contents. It seems to treat the registers as sign-extended | |
20 | 32-bit values. This cause *REAL* problems when single-stepping 64-bit | |
21 | code on the hardware. | |
22 | ||
23 | */ | |
24 | ||
25 | /* The TRACE manifests enable the provision of extra features. If they | |
26 | are not defined then a simpler (quicker) simulator is constructed | |
27 | without the required run-time checks, etc. */ | |
28 | #if 1 /* 0 to allow user build selection, 1 to force inclusion */ | |
29 | #define TRACE (1) | |
30 | #endif | |
31 | ||
32 | #include "bfd.h" | |
33 | #include "sim-main.h" | |
34 | #include "sim-utils.h" | |
35 | #include "sim-options.h" | |
36 | #include "sim-assert.h" | |
37 | #include "sim-hw.h" | |
38 | ||
39 | #include "itable.h" | |
40 | ||
41 | ||
42 | #include "config.h" | |
43 | ||
44 | #include <stdio.h> | |
45 | #include <stdarg.h> | |
46 | #include <ansidecl.h> | |
47 | #include <ctype.h> | |
48 | #include <limits.h> | |
49 | #include <math.h> | |
50 | #ifdef HAVE_STDLIB_H | |
51 | #include <stdlib.h> | |
52 | #endif | |
53 | #ifdef HAVE_STRING_H | |
54 | #include <string.h> | |
55 | #else | |
56 | #ifdef HAVE_STRINGS_H | |
57 | #include <strings.h> | |
58 | #endif | |
59 | #endif | |
60 | ||
61 | #include "getopt.h" | |
62 | #include "libiberty.h" | |
63 | #include "bfd.h" | |
64 | #include "callback.h" /* GDB simulator callback interface */ | |
65 | #include "remote-sim.h" /* GDB simulator interface */ | |
66 | ||
67 | #include "sysdep.h" | |
68 | ||
69 | #ifndef PARAMS | |
70 | #define PARAMS(x) | |
71 | #endif | |
72 | ||
73 | char* pr_addr PARAMS ((SIM_ADDR addr)); | |
74 | char* pr_uword64 PARAMS ((uword64 addr)); | |
75 | ||
76 | ||
77 | /* Within interp.c we refer to the sim_state and sim_cpu directly. */ | |
78 | #define CPU cpu | |
79 | #define SD sd | |
80 | ||
81 | ||
82 | /* The following reserved instruction value is used when a simulator | |
83 | trap is required. NOTE: Care must be taken, since this value may be | |
84 | used in later revisions of the MIPS ISA. */ | |
85 | ||
86 | #define RSVD_INSTRUCTION (0x00000005) | |
87 | #define RSVD_INSTRUCTION_MASK (0xFC00003F) | |
88 | ||
89 | #define RSVD_INSTRUCTION_ARG_SHIFT 6 | |
90 | #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF | |
91 | ||
92 | ||
93 | /* Bits in the Debug register */ | |
94 | #define Debug_DBD 0x80000000 /* Debug Branch Delay */ | |
95 | #define Debug_DM 0x40000000 /* Debug Mode */ | |
96 | #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */ | |
97 | ||
98 | /*---------------------------------------------------------------------------*/ | |
99 | /*-- GDB simulator interface ------------------------------------------------*/ | |
100 | /*---------------------------------------------------------------------------*/ | |
101 | ||
102 | static void ColdReset PARAMS((SIM_DESC sd)); | |
103 | ||
104 | /*---------------------------------------------------------------------------*/ | |
105 | ||
106 | ||
107 | ||
108 | #define DELAYSLOT() {\ | |
109 | if (STATE & simDELAYSLOT)\ | |
110 | sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\ | |
111 | STATE |= simDELAYSLOT;\ | |
112 | } | |
113 | ||
114 | #define JALDELAYSLOT() {\ | |
115 | DELAYSLOT ();\ | |
116 | STATE |= simJALDELAYSLOT;\ | |
117 | } | |
118 | ||
119 | #define NULLIFY() {\ | |
120 | STATE &= ~simDELAYSLOT;\ | |
121 | STATE |= simSKIPNEXT;\ | |
122 | } | |
123 | ||
124 | #define CANCELDELAYSLOT() {\ | |
125 | DSSTATE = 0;\ | |
126 | STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\ | |
127 | } | |
128 | ||
129 | #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0) | |
130 | #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0) | |
131 | ||
adf40b2e JM |
132 | /* Note that the monitor code essentially assumes this layout of memory. |
133 | If you change these, change the monitor code, too. */ | |
c906108c SS |
134 | #define K0BASE (0x80000000) |
135 | #define K0SIZE (0x20000000) | |
136 | #define K1BASE (0xA0000000) | |
137 | #define K1SIZE (0x20000000) | |
adf40b2e JM |
138 | |
139 | /* Simple run-time monitor support. | |
140 | ||
141 | We emulate the monitor by placing magic reserved instructions at | |
142 | the monitor's entry points; when we hit these instructions, instead | |
143 | of raising an exception (as we would normally), we look at the | |
144 | instruction and perform the appropriate monitory operation. | |
145 | ||
146 | `*_monitor_base' are the physical addresses at which the corresponding | |
147 | monitor vectors are located. `0' means none. By default, | |
148 | install all three. | |
149 | The RSVD_INSTRUCTION... macros specify the magic instructions we | |
150 | use at the monitor entry points. */ | |
151 | static int firmware_option_p = 0; | |
152 | static SIM_ADDR idt_monitor_base = 0xBFC00000; | |
153 | static SIM_ADDR pmon_monitor_base = 0xBFC00500; | |
154 | static SIM_ADDR lsipmon_monitor_base = 0xBFC00200; | |
155 | ||
156 | static SIM_RC sim_firmware_command (SIM_DESC sd, char* arg); | |
157 | ||
158 | ||
c906108c SS |
159 | #define MEM_SIZE (2 << 20) |
160 | ||
161 | ||
162 | #if defined(TRACE) | |
163 | static char *tracefile = "trace.din"; /* default filename for trace log */ | |
164 | FILE *tracefh = NULL; | |
165 | static void open_trace PARAMS((SIM_DESC sd)); | |
166 | #endif /* TRACE */ | |
167 | ||
168 | static const char * get_insn_name (sim_cpu *, int); | |
169 | ||
170 | /* simulation target board. NULL=canonical */ | |
171 | static char* board = NULL; | |
172 | ||
173 | ||
174 | static DECLARE_OPTION_HANDLER (mips_option_handler); | |
175 | ||
176 | enum { | |
177 | OPTION_DINERO_TRACE = OPTION_START, | |
178 | OPTION_DINERO_FILE, | |
adf40b2e | 179 | OPTION_FIRMWARE, |
c906108c SS |
180 | OPTION_BOARD |
181 | }; | |
182 | ||
183 | ||
184 | static SIM_RC | |
185 | mips_option_handler (sd, cpu, opt, arg, is_command) | |
186 | SIM_DESC sd; | |
187 | sim_cpu *cpu; | |
188 | int opt; | |
189 | char *arg; | |
190 | int is_command; | |
191 | { | |
192 | int cpu_nr; | |
193 | switch (opt) | |
194 | { | |
195 | case OPTION_DINERO_TRACE: /* ??? */ | |
196 | #if defined(TRACE) | |
197 | /* Eventually the simTRACE flag could be treated as a toggle, to | |
198 | allow external control of the program points being traced | |
199 | (i.e. only from main onwards, excluding the run-time setup, | |
200 | etc.). */ | |
201 | for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++) | |
202 | { | |
203 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); | |
204 | if (arg == NULL) | |
205 | STATE |= simTRACE; | |
206 | else if (strcmp (arg, "yes") == 0) | |
207 | STATE |= simTRACE; | |
208 | else if (strcmp (arg, "no") == 0) | |
209 | STATE &= ~simTRACE; | |
210 | else if (strcmp (arg, "on") == 0) | |
211 | STATE |= simTRACE; | |
212 | else if (strcmp (arg, "off") == 0) | |
213 | STATE &= ~simTRACE; | |
214 | else | |
215 | { | |
216 | fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg); | |
217 | return SIM_RC_FAIL; | |
218 | } | |
219 | } | |
220 | return SIM_RC_OK; | |
221 | #else /* !TRACE */ | |
222 | fprintf(stderr,"\ | |
223 | Simulator constructed without dinero tracing support (for performance).\n\ | |
224 | Re-compile simulator with \"-DTRACE\" to enable this option.\n"); | |
225 | return SIM_RC_FAIL; | |
226 | #endif /* !TRACE */ | |
227 | ||
228 | case OPTION_DINERO_FILE: | |
229 | #if defined(TRACE) | |
230 | if (optarg != NULL) { | |
231 | char *tmp; | |
232 | tmp = (char *)malloc(strlen(optarg) + 1); | |
233 | if (tmp == NULL) | |
234 | { | |
235 | sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg); | |
236 | return SIM_RC_FAIL; | |
237 | } | |
238 | else { | |
239 | strcpy(tmp,optarg); | |
240 | tracefile = tmp; | |
241 | sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile); | |
242 | } | |
243 | } | |
244 | #endif /* TRACE */ | |
245 | return SIM_RC_OK; | |
246 | ||
adf40b2e JM |
247 | case OPTION_FIRMWARE: |
248 | return sim_firmware_command (sd, arg); | |
249 | ||
c906108c SS |
250 | case OPTION_BOARD: |
251 | { | |
252 | if (arg) | |
253 | { | |
254 | board = zalloc(strlen(arg) + 1); | |
255 | strcpy(board, arg); | |
256 | } | |
257 | return SIM_RC_OK; | |
258 | } | |
259 | } | |
260 | ||
261 | return SIM_RC_OK; | |
262 | } | |
263 | ||
264 | ||
265 | static const OPTION mips_options[] = | |
266 | { | |
267 | { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE}, | |
268 | '\0', "on|off", "Enable dinero tracing", | |
269 | mips_option_handler }, | |
270 | { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE}, | |
271 | '\0', "FILE", "Write dinero trace to FILE", | |
272 | mips_option_handler }, | |
adf40b2e JM |
273 | { {"firmware", required_argument, NULL, OPTION_FIRMWARE}, |
274 | '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor", | |
275 | mips_option_handler }, | |
c906108c SS |
276 | { {"board", required_argument, NULL, OPTION_BOARD}, |
277 | '\0', "none" /* rely on compile-time string concatenation for other options */ | |
278 | ||
279 | #define BOARD_JMR3904 "jmr3904" | |
280 | "|" BOARD_JMR3904 | |
281 | #define BOARD_JMR3904_PAL "jmr3904pal" | |
282 | "|" BOARD_JMR3904_PAL | |
283 | #define BOARD_JMR3904_DEBUG "jmr3904debug" | |
284 | "|" BOARD_JMR3904_DEBUG | |
43e526b9 JM |
285 | #define BOARD_BSP "bsp" |
286 | "|" BOARD_BSP | |
c906108c SS |
287 | |
288 | , "Customize simulation for a particular board.", mips_option_handler }, | |
289 | ||
290 | { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } | |
291 | }; | |
292 | ||
293 | ||
294 | int interrupt_pending; | |
295 | ||
296 | void | |
297 | interrupt_event (SIM_DESC sd, void *data) | |
298 | { | |
299 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ | |
300 | address_word cia = CIA_GET (cpu); | |
301 | if (SR & status_IE) | |
302 | { | |
303 | interrupt_pending = 0; | |
304 | SignalExceptionInterrupt (1); /* interrupt "1" */ | |
305 | } | |
306 | else if (!interrupt_pending) | |
307 | sim_events_schedule (sd, 1, interrupt_event, data); | |
308 | } | |
309 | ||
310 | ||
311 | /*---------------------------------------------------------------------------*/ | |
312 | /*-- Device registration hook -----------------------------------------------*/ | |
313 | /*---------------------------------------------------------------------------*/ | |
314 | static void device_init(SIM_DESC sd) { | |
315 | #ifdef DEVICE_INIT | |
316 | extern void register_devices(SIM_DESC); | |
317 | register_devices(sd); | |
318 | #endif | |
319 | } | |
320 | ||
321 | /*---------------------------------------------------------------------------*/ | |
322 | /*-- GDB simulator interface ------------------------------------------------*/ | |
323 | /*---------------------------------------------------------------------------*/ | |
324 | ||
325 | SIM_DESC | |
326 | sim_open (kind, cb, abfd, argv) | |
327 | SIM_OPEN_KIND kind; | |
328 | host_callback *cb; | |
329 | struct _bfd *abfd; | |
330 | char **argv; | |
331 | { | |
332 | SIM_DESC sd = sim_state_alloc (kind, cb); | |
333 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ | |
334 | ||
335 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
336 | ||
337 | /* FIXME: watchpoints code shouldn't need this */ | |
338 | STATE_WATCHPOINTS (sd)->pc = &(PC); | |
339 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
340 | STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event; | |
341 | ||
342 | /* Initialize the mechanism for doing insn profiling. */ | |
343 | CPU_INSN_NAME (cpu) = get_insn_name; | |
344 | CPU_MAX_INSNS (cpu) = nr_itable_entries; | |
345 | ||
346 | STATE = 0; | |
347 | ||
348 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
349 | return 0; | |
350 | sim_add_option_table (sd, NULL, mips_options); | |
351 | ||
352 | ||
353 | /* getopt will print the error message so we just have to exit if this fails. | |
354 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
355 | print_filtered. */ | |
356 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
357 | { | |
358 | /* Uninstall the modules to avoid memory leaks, | |
359 | file descriptor leaks, etc. */ | |
360 | sim_module_uninstall (sd); | |
361 | return 0; | |
362 | } | |
363 | ||
364 | /* handle board-specific memory maps */ | |
365 | if (board == NULL) | |
366 | { | |
367 | /* Allocate core managed memory */ | |
368 | ||
adf40b2e | 369 | |
c906108c SS |
370 | /* For compatibility with the old code - under this (at level one) |
371 | are the kernel spaces K0 & K1. Both of these map to a single | |
372 | smaller sub region */ | |
373 | sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */ | |
374 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x", | |
375 | K1BASE, K0SIZE, | |
376 | MEM_SIZE, /* actual size */ | |
377 | K0BASE); | |
378 | ||
379 | device_init(sd); | |
380 | } | |
43e526b9 JM |
381 | else if (board != NULL |
382 | && (strcmp(board, BOARD_BSP) == 0)) | |
383 | { | |
384 | int i; | |
385 | ||
386 | STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT; | |
387 | ||
388 | /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */ | |
389 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x", | |
390 | 0x9FC00000, | |
391 | 4 * 1024 * 1024, /* 4 MB */ | |
392 | 0xBFC00000); | |
393 | ||
394 | /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */ | |
395 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x", | |
396 | 0x80000000, | |
397 | 4 * 1024 * 1024, /* 4 MB */ | |
398 | 0xA0000000); | |
399 | ||
400 | /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */ | |
401 | for (i=0; i<8; i++) /* 32 MB total */ | |
402 | { | |
403 | unsigned size = 4 * 1024 * 1024; /* 4 MB */ | |
404 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x", | |
405 | 0x88000000 + (i * size), | |
406 | size, | |
407 | 0xA8000000 + (i * size)); | |
408 | } | |
409 | } | |
c906108c | 410 | #if (WITH_HW) |
43e526b9 JM |
411 | else if (board != NULL |
412 | && (strcmp(board, BOARD_JMR3904) == 0 || | |
413 | strcmp(board, BOARD_JMR3904_PAL) == 0 || | |
414 | strcmp(board, BOARD_JMR3904_DEBUG) == 0)) | |
c906108c SS |
415 | { |
416 | /* match VIRTUAL memory layout of JMR-TX3904 board */ | |
417 | int i; | |
418 | ||
adf40b2e JM |
419 | /* --- disable monitor unless forced on by user --- */ |
420 | ||
421 | if (! firmware_option_p) | |
422 | { | |
423 | idt_monitor_base = 0; | |
424 | pmon_monitor_base = 0; | |
425 | lsipmon_monitor_base = 0; | |
426 | } | |
427 | ||
c906108c SS |
428 | /* --- environment --- */ |
429 | ||
430 | STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT; | |
431 | ||
432 | /* --- memory --- */ | |
433 | ||
434 | /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */ | |
435 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x", | |
436 | 0x9FC00000, | |
437 | 4 * 1024 * 1024, /* 4 MB */ | |
438 | 0xBFC00000); | |
439 | ||
440 | /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */ | |
441 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x", | |
442 | 0x80000000, | |
443 | 4 * 1024 * 1024, /* 4 MB */ | |
444 | 0xA0000000); | |
445 | ||
446 | /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */ | |
447 | for (i=0; i<8; i++) /* 32 MB total */ | |
448 | { | |
449 | unsigned size = 4 * 1024 * 1024; /* 4 MB */ | |
450 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x", | |
451 | 0x88000000 + (i * size), | |
452 | size, | |
453 | 0xA8000000 + (i * size)); | |
454 | } | |
455 | ||
cb7450ea | 456 | /* Dummy memory regions for unsimulated devices - sorted by address */ |
c906108c | 457 | |
d4f3574e | 458 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */ |
c2d11a7d JM |
459 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */ |
460 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */ | |
d4f3574e SS |
461 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */ |
462 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */ | |
cb7450ea FCE |
463 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x900); /* DRAMC */ |
464 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */ | |
465 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */ | |
466 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */ | |
467 | ||
c906108c SS |
468 | |
469 | /* --- simulated devices --- */ | |
470 | sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20"); | |
471 | sim_hw_parse (sd, "/tx3904cpu"); | |
472 | sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100"); | |
473 | sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100"); | |
474 | sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100"); | |
475 | sim_hw_parse (sd, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100"); | |
476 | { | |
477 | /* FIXME: poking at dv-sockser internals, use tcp backend if | |
478 | --sockser_addr option was given.*/ | |
479 | extern char* sockser_addr; | |
480 | if(sockser_addr == NULL) | |
481 | sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend stdio"); | |
482 | else | |
483 | sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend tcp"); | |
484 | } | |
485 | sim_hw_parse (sd, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100"); | |
486 | sim_hw_parse (sd, "/tx3904sio@0xfffff400/backend stdio"); | |
487 | ||
488 | /* -- device connections --- */ | |
489 | sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu"); | |
490 | sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc"); | |
491 | sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc"); | |
492 | sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc"); | |
493 | sim_hw_parse (sd, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc"); | |
494 | sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc"); | |
495 | ||
496 | /* add PAL timer & I/O module */ | |
497 | if(! strcmp(board, BOARD_JMR3904_PAL)) | |
498 | { | |
499 | /* the device */ | |
500 | sim_hw_parse (sd, "/pal@0xffff0000"); | |
501 | sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64"); | |
502 | ||
503 | /* wire up interrupt ports to irc */ | |
504 | sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc"); | |
505 | sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc"); | |
506 | sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc"); | |
507 | } | |
508 | ||
509 | if(! strcmp(board, BOARD_JMR3904_DEBUG)) | |
510 | { | |
511 | /* -- DEBUG: glue interrupt generators --- */ | |
512 | sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50"); | |
513 | sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc"); | |
514 | sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc"); | |
515 | sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc"); | |
516 | sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc"); | |
517 | sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc"); | |
518 | sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc"); | |
519 | sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc"); | |
520 | sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc"); | |
521 | sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc"); | |
522 | sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc"); | |
523 | sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc"); | |
524 | sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc"); | |
525 | sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc"); | |
526 | sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc"); | |
527 | sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc"); | |
528 | sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc"); | |
529 | sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc"); | |
530 | sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu"); | |
531 | } | |
532 | ||
533 | device_init(sd); | |
534 | } | |
535 | #endif | |
536 | ||
537 | ||
538 | /* check for/establish the a reference program image */ | |
539 | if (sim_analyze_program (sd, | |
540 | (STATE_PROG_ARGV (sd) != NULL | |
541 | ? *STATE_PROG_ARGV (sd) | |
542 | : NULL), | |
543 | abfd) != SIM_RC_OK) | |
544 | { | |
545 | sim_module_uninstall (sd); | |
546 | return 0; | |
547 | } | |
548 | ||
549 | /* Configure/verify the target byte order and other runtime | |
550 | configuration options */ | |
551 | if (sim_config (sd) != SIM_RC_OK) | |
552 | { | |
553 | sim_module_uninstall (sd); | |
554 | return 0; | |
555 | } | |
556 | ||
557 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
558 | { | |
559 | /* Uninstall the modules to avoid memory leaks, | |
560 | file descriptor leaks, etc. */ | |
561 | sim_module_uninstall (sd); | |
562 | return 0; | |
563 | } | |
564 | ||
565 | /* verify assumptions the simulator made about the host type system. | |
566 | This macro does not return if there is a problem */ | |
567 | SIM_ASSERT (sizeof(int) == (4 * sizeof(char))); | |
568 | SIM_ASSERT (sizeof(word64) == (8 * sizeof(char))); | |
569 | ||
570 | /* This is NASTY, in that we are assuming the size of specific | |
571 | registers: */ | |
572 | { | |
573 | int rn; | |
574 | for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) | |
575 | { | |
576 | if (rn < 32) | |
577 | cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; | |
578 | else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR))) | |
579 | cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE; | |
580 | else if ((rn >= 33) && (rn <= 37)) | |
581 | cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; | |
582 | else if ((rn == SRIDX) | |
583 | || (rn == FCR0IDX) | |
584 | || (rn == FCR31IDX) | |
585 | || ((rn >= 72) && (rn <= 89))) | |
586 | cpu->register_widths[rn] = 32; | |
587 | else | |
588 | cpu->register_widths[rn] = 0; | |
589 | } | |
590 | ||
591 | ||
592 | } | |
593 | ||
594 | #if defined(TRACE) | |
595 | if (STATE & simTRACE) | |
596 | open_trace(sd); | |
597 | #endif /* TRACE */ | |
598 | ||
adf40b2e JM |
599 | /* |
600 | sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n", | |
601 | idt_monitor_base, | |
602 | pmon_monitor_base, | |
603 | lsipmon_monitor_base); | |
604 | */ | |
c906108c SS |
605 | |
606 | /* Write the monitor trap address handlers into the monitor (eeprom) | |
607 | address space. This can only be done once the target endianness | |
608 | has been determined. */ | |
adf40b2e JM |
609 | if (idt_monitor_base != 0) |
610 | { | |
611 | unsigned loop; | |
612 | unsigned idt_monitor_size = 1 << 11; | |
613 | ||
614 | /* the default monitor region */ | |
615 | sim_do_commandf (sd, "memory region 0x%x,0x%x", | |
616 | idt_monitor_base, idt_monitor_size); | |
617 | ||
618 | /* Entry into the IDT monitor is via fixed address vectors, and | |
619 | not using machine instructions. To avoid clashing with use of | |
620 | the MIPS TRAP system, we place our own (simulator specific) | |
621 | "undefined" instructions into the relevant vector slots. */ | |
622 | for (loop = 0; (loop < idt_monitor_size); loop += 4) | |
623 | { | |
624 | address_word vaddr = (idt_monitor_base + loop); | |
625 | unsigned32 insn = (RSVD_INSTRUCTION | | |
626 | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) | |
627 | << RSVD_INSTRUCTION_ARG_SHIFT)); | |
628 | H2T (insn); | |
629 | sim_write (sd, vaddr, (char *)&insn, sizeof (insn)); | |
630 | } | |
631 | } | |
632 | ||
633 | if ((pmon_monitor_base != 0) || (lsipmon_monitor_base != 0)) | |
634 | { | |
c906108c SS |
635 | /* The PMON monitor uses the same address space, but rather than |
636 | branching into it the address of a routine is loaded. We can | |
637 | cheat for the moment, and direct the PMON routine to IDT style | |
638 | instructions within the monitor space. This relies on the IDT | |
639 | monitor not using the locations from 0xBFC00500 onwards as its | |
640 | entry points.*/ | |
adf40b2e JM |
641 | unsigned loop; |
642 | for (loop = 0; (loop < 24); loop++) | |
643 | { | |
644 | unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */ | |
645 | switch (loop) | |
646 | { | |
c906108c SS |
647 | case 0: /* read */ |
648 | value = 7; | |
649 | break; | |
650 | case 1: /* write */ | |
651 | value = 8; | |
652 | break; | |
653 | case 2: /* open */ | |
654 | value = 6; | |
655 | break; | |
656 | case 3: /* close */ | |
657 | value = 10; | |
658 | break; | |
659 | case 5: /* printf */ | |
660 | value = ((0x500 - 16) / 8); /* not an IDT reason code */ | |
661 | break; | |
662 | case 8: /* cliexit */ | |
663 | value = 17; | |
664 | break; | |
665 | case 11: /* flush_cache */ | |
666 | value = 28; | |
667 | break; | |
668 | } | |
adf40b2e JM |
669 | |
670 | SIM_ASSERT (idt_monitor_base != 0); | |
671 | value = ((unsigned int) idt_monitor_base + (value * 8)); | |
c906108c | 672 | H2T (value); |
c906108c | 673 | |
adf40b2e JM |
674 | if (pmon_monitor_base != 0) |
675 | { | |
676 | address_word vaddr = (pmon_monitor_base + (loop * 4)); | |
677 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); | |
678 | } | |
679 | ||
680 | if (lsipmon_monitor_base != 0) | |
681 | { | |
682 | address_word vaddr = (lsipmon_monitor_base + (loop * 4)); | |
683 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); | |
684 | } | |
c906108c | 685 | } |
adf40b2e JM |
686 | |
687 | /* Write an abort sequence into the TRAP (common) exception vector | |
688 | addresses. This is to catch code executing a TRAP (et.al.) | |
689 | instruction without installing a trap handler. */ | |
690 | if ((idt_monitor_base != 0) || | |
691 | (pmon_monitor_base != 0) || | |
692 | (lsipmon_monitor_base != 0)) | |
693 | { | |
694 | unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */, | |
695 | HALT_INSTRUCTION /* BREAK */ }; | |
696 | H2T (halt[0]); | |
697 | H2T (halt[1]); | |
698 | sim_write (sd, 0x80000000, (char *) halt, sizeof (halt)); | |
699 | sim_write (sd, 0x80000180, (char *) halt, sizeof (halt)); | |
700 | sim_write (sd, 0x80000200, (char *) halt, sizeof (halt)); | |
b882a66b AO |
701 | #if 0 |
702 | /* This is wrong. We're not supposed to write code to the | |
703 | vector tables, but rather pointers to code. */ | |
adf40b2e JM |
704 | /* XXX: Write here unconditionally? */ |
705 | sim_write (sd, 0xBFC00200, (char *) halt, sizeof (halt)); | |
706 | sim_write (sd, 0xBFC00380, (char *) halt, sizeof (halt)); | |
707 | sim_write (sd, 0xBFC00400, (char *) halt, sizeof (halt)); | |
b882a66b | 708 | #endif |
adf40b2e | 709 | } |
c906108c SS |
710 | } |
711 | ||
712 | ||
713 | ||
714 | return sd; | |
715 | } | |
716 | ||
717 | #if defined(TRACE) | |
718 | static void | |
719 | open_trace(sd) | |
720 | SIM_DESC sd; | |
721 | { | |
722 | tracefh = fopen(tracefile,"wb+"); | |
723 | if (tracefh == NULL) | |
724 | { | |
725 | sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile); | |
726 | tracefh = stderr; | |
727 | } | |
728 | } | |
729 | #endif /* TRACE */ | |
730 | ||
731 | /* Return name of an insn, used by insn profiling. */ | |
732 | static const char * | |
733 | get_insn_name (sim_cpu *cpu, int i) | |
734 | { | |
735 | return itable[i].name; | |
736 | } | |
737 | ||
738 | void | |
739 | sim_close (sd, quitting) | |
740 | SIM_DESC sd; | |
741 | int quitting; | |
742 | { | |
743 | #ifdef DEBUG | |
744 | printf("DBG: sim_close: entered (quitting = %d)\n",quitting); | |
745 | #endif | |
746 | ||
747 | ||
748 | /* "quitting" is non-zero if we cannot hang on errors */ | |
749 | ||
750 | /* shut down modules */ | |
751 | sim_module_uninstall (sd); | |
752 | ||
753 | /* Ensure that any resources allocated through the callback | |
754 | mechanism are released: */ | |
755 | sim_io_shutdown (sd); | |
756 | ||
757 | #if defined(TRACE) | |
758 | if (tracefh != NULL && tracefh != stderr) | |
759 | fclose(tracefh); | |
760 | tracefh = NULL; | |
761 | #endif /* TRACE */ | |
762 | ||
763 | /* FIXME - free SD */ | |
764 | ||
765 | return; | |
766 | } | |
767 | ||
768 | ||
769 | int | |
770 | sim_write (sd,addr,buffer,size) | |
771 | SIM_DESC sd; | |
772 | SIM_ADDR addr; | |
773 | unsigned char *buffer; | |
774 | int size; | |
775 | { | |
776 | int index; | |
777 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ | |
778 | ||
779 | /* Return the number of bytes written, or zero if error. */ | |
780 | #ifdef DEBUG | |
781 | sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size); | |
782 | #endif | |
783 | ||
784 | /* We use raw read and write routines, since we do not want to count | |
785 | the GDB memory accesses in our statistics gathering. */ | |
786 | ||
787 | for (index = 0; index < size; index++) | |
788 | { | |
789 | address_word vaddr = (address_word)addr + index; | |
790 | address_word paddr; | |
791 | int cca; | |
792 | if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW)) | |
793 | break; | |
794 | if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1) | |
795 | break; | |
796 | } | |
797 | ||
798 | return(index); | |
799 | } | |
800 | ||
801 | int | |
802 | sim_read (sd,addr,buffer,size) | |
803 | SIM_DESC sd; | |
804 | SIM_ADDR addr; | |
805 | unsigned char *buffer; | |
806 | int size; | |
807 | { | |
808 | int index; | |
809 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ | |
810 | ||
811 | /* Return the number of bytes read, or zero if error. */ | |
812 | #ifdef DEBUG | |
813 | sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size); | |
814 | #endif /* DEBUG */ | |
815 | ||
816 | for (index = 0; (index < size); index++) | |
817 | { | |
818 | address_word vaddr = (address_word)addr + index; | |
819 | address_word paddr; | |
820 | int cca; | |
821 | if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW)) | |
822 | break; | |
823 | if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1) | |
824 | break; | |
825 | } | |
826 | ||
827 | return(index); | |
828 | } | |
829 | ||
830 | int | |
831 | sim_store_register (sd,rn,memory,length) | |
832 | SIM_DESC sd; | |
833 | int rn; | |
834 | unsigned char *memory; | |
835 | int length; | |
836 | { | |
837 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ | |
838 | /* NOTE: gdb (the client) stores registers in target byte order | |
839 | while the simulator uses host byte order */ | |
840 | #ifdef DEBUG | |
841 | sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory))); | |
842 | #endif /* DEBUG */ | |
843 | ||
844 | /* Unfortunately this suffers from the same problem as the register | |
845 | numbering one. We need to know what the width of each logical | |
846 | register number is for the architecture being simulated. */ | |
847 | ||
848 | if (cpu->register_widths[rn] == 0) | |
849 | { | |
850 | sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn); | |
851 | return 0; | |
852 | } | |
853 | ||
854 | ||
855 | ||
856 | if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) | |
857 | { | |
7a292a7a | 858 | cpu->fpr_state[rn - FGRIDX] = fmt_uninterpreted; |
c906108c SS |
859 | if (cpu->register_widths[rn] == 32) |
860 | { | |
a0b3c4fd JM |
861 | if (length == 8) |
862 | { | |
863 | cpu->fgr[rn - FGRIDX] = | |
864 | (unsigned32) T2H_8 (*(unsigned64*)memory); | |
865 | return 8; | |
866 | } | |
867 | else | |
868 | { | |
869 | cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory); | |
870 | return 4; | |
871 | } | |
c906108c SS |
872 | } |
873 | else | |
874 | { | |
875 | cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory); | |
876 | return 8; | |
877 | } | |
878 | } | |
879 | ||
880 | if (cpu->register_widths[rn] == 32) | |
881 | { | |
a0b3c4fd JM |
882 | if (length == 8) |
883 | { | |
884 | cpu->registers[rn] = | |
885 | (unsigned32) T2H_8 (*(unsigned64*)memory); | |
886 | return 8; | |
887 | } | |
888 | else | |
889 | { | |
890 | cpu->registers[rn] = T2H_4 (*(unsigned32*)memory); | |
891 | return 4; | |
892 | } | |
c906108c SS |
893 | } |
894 | else | |
895 | { | |
896 | cpu->registers[rn] = T2H_8 (*(unsigned64*)memory); | |
897 | return 8; | |
898 | } | |
899 | ||
900 | return 0; | |
901 | } | |
902 | ||
903 | int | |
904 | sim_fetch_register (sd,rn,memory,length) | |
905 | SIM_DESC sd; | |
906 | int rn; | |
907 | unsigned char *memory; | |
908 | int length; | |
909 | { | |
910 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ | |
911 | /* NOTE: gdb (the client) stores registers in target byte order | |
912 | while the simulator uses host byte order */ | |
913 | #ifdef DEBUG | |
914 | #if 0 /* FIXME: doesn't compile */ | |
915 | sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn])); | |
916 | #endif | |
917 | #endif /* DEBUG */ | |
918 | ||
919 | if (cpu->register_widths[rn] == 0) | |
920 | { | |
921 | sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn); | |
922 | return 0; | |
923 | } | |
924 | ||
925 | ||
926 | ||
927 | /* Any floating point register */ | |
928 | if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) | |
929 | { | |
930 | if (cpu->register_widths[rn] == 32) | |
931 | { | |
a0b3c4fd JM |
932 | if (length == 8) |
933 | { | |
934 | *(unsigned64*)memory = | |
935 | H2T_8 ((unsigned32) (cpu->fgr[rn - FGRIDX])); | |
936 | return 8; | |
937 | } | |
938 | else | |
939 | { | |
940 | *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]); | |
941 | return 4; | |
942 | } | |
c906108c SS |
943 | } |
944 | else | |
945 | { | |
946 | *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]); | |
947 | return 8; | |
948 | } | |
949 | } | |
950 | ||
951 | if (cpu->register_widths[rn] == 32) | |
952 | { | |
a0b3c4fd JM |
953 | if (length == 8) |
954 | { | |
955 | *(unsigned64*)memory = | |
956 | H2T_8 ((unsigned32) (cpu->registers[rn])); | |
957 | return 8; | |
958 | } | |
959 | else | |
960 | { | |
961 | *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn])); | |
962 | return 4; | |
963 | } | |
c906108c SS |
964 | } |
965 | else | |
966 | { | |
967 | *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn])); | |
968 | return 8; | |
969 | } | |
970 | ||
971 | return 0; | |
972 | } | |
973 | ||
974 | ||
975 | SIM_RC | |
976 | sim_create_inferior (sd, abfd, argv,env) | |
977 | SIM_DESC sd; | |
978 | struct _bfd *abfd; | |
979 | char **argv; | |
980 | char **env; | |
981 | { | |
982 | ||
983 | #ifdef DEBUG | |
984 | #if 0 /* FIXME: doesn't compile */ | |
985 | printf("DBG: sim_create_inferior entered: start_address = 0x%s\n", | |
986 | pr_addr(PC)); | |
987 | #endif | |
988 | #endif /* DEBUG */ | |
989 | ||
990 | ColdReset(sd); | |
991 | ||
992 | if (abfd != NULL) | |
993 | { | |
994 | /* override PC value set by ColdReset () */ | |
995 | int cpu_nr; | |
996 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) | |
997 | { | |
998 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); | |
999 | CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd)); | |
1000 | } | |
1001 | } | |
1002 | ||
1003 | #if 0 /* def DEBUG */ | |
1004 | if (argv || env) | |
1005 | { | |
1006 | /* We should really place the argv slot values into the argument | |
1007 | registers, and onto the stack as required. However, this | |
1008 | assumes that we have a stack defined, which is not | |
1009 | necessarily true at the moment. */ | |
1010 | char **cptr; | |
1011 | sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n"); | |
1012 | for (cptr = argv; (cptr && *cptr); cptr++) | |
1013 | printf("DBG: arg \"%s\"\n",*cptr); | |
1014 | } | |
1015 | #endif /* DEBUG */ | |
1016 | ||
1017 | return SIM_RC_OK; | |
1018 | } | |
1019 | ||
1020 | void | |
1021 | sim_do_command (sd,cmd) | |
1022 | SIM_DESC sd; | |
1023 | char *cmd; | |
1024 | { | |
1025 | if (sim_args_command (sd, cmd) != SIM_RC_OK) | |
1026 | sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n", | |
1027 | cmd); | |
1028 | } | |
1029 | ||
1030 | /*---------------------------------------------------------------------------*/ | |
1031 | /*-- Private simulator support interface ------------------------------------*/ | |
1032 | /*---------------------------------------------------------------------------*/ | |
1033 | ||
1034 | /* Read a null terminated string from memory, return in a buffer */ | |
1035 | static char * | |
1036 | fetch_str (SIM_DESC sd, | |
1037 | address_word addr) | |
1038 | { | |
1039 | char *buf; | |
1040 | int nr = 0; | |
1041 | char null; | |
1042 | while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0) | |
1043 | nr++; | |
1044 | buf = NZALLOC (char, nr + 1); | |
1045 | sim_read (sd, addr, buf, nr); | |
1046 | return buf; | |
1047 | } | |
1048 | ||
adf40b2e JM |
1049 | |
1050 | /* Implements the "sim firmware" command: | |
1051 | sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME. | |
1052 | NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS | |
1053 | defaults to the normal address for that monitor. | |
1054 | sim firmware none --- don't emulate any ROM monitor. Useful | |
1055 | if you need a clean address space. */ | |
1056 | static SIM_RC | |
1057 | sim_firmware_command (SIM_DESC sd, char *arg) | |
1058 | { | |
1059 | int address_present = 0; | |
1060 | SIM_ADDR address; | |
1061 | ||
1062 | /* Signal occurrence of this option. */ | |
1063 | firmware_option_p = 1; | |
1064 | ||
1065 | /* Parse out the address, if present. */ | |
1066 | { | |
1067 | char *p = strchr (arg, '@'); | |
1068 | if (p) | |
1069 | { | |
1070 | char *q; | |
1071 | address_present = 1; | |
1072 | p ++; /* skip over @ */ | |
1073 | ||
1074 | address = strtoul (p, &q, 0); | |
1075 | if (*q != '\0') | |
1076 | { | |
1077 | sim_io_printf (sd, "Invalid address given to the" | |
1078 | "`sim firmware NAME@ADDRESS' command: %s\n", | |
1079 | p); | |
1080 | return SIM_RC_FAIL; | |
1081 | } | |
1082 | } | |
1083 | else | |
1084 | address_present = 0; | |
1085 | } | |
1086 | ||
1087 | if (! strncmp (arg, "idt", 3)) | |
1088 | { | |
1089 | idt_monitor_base = address_present ? address : 0xBFC00000; | |
1090 | pmon_monitor_base = 0; | |
1091 | lsipmon_monitor_base = 0; | |
1092 | } | |
1093 | else if (! strncmp (arg, "pmon", 4)) | |
1094 | { | |
1095 | /* pmon uses indirect calls. Hook into implied idt. */ | |
1096 | pmon_monitor_base = address_present ? address : 0xBFC00500; | |
1097 | idt_monitor_base = pmon_monitor_base - 0x500; | |
1098 | lsipmon_monitor_base = 0; | |
1099 | } | |
1100 | else if (! strncmp (arg, "lsipmon", 7)) | |
1101 | { | |
1102 | /* lsipmon uses indirect calls. Hook into implied idt. */ | |
1103 | pmon_monitor_base = 0; | |
1104 | lsipmon_monitor_base = address_present ? address : 0xBFC00200; | |
1105 | idt_monitor_base = lsipmon_monitor_base - 0x200; | |
1106 | } | |
1107 | else if (! strncmp (arg, "none", 4)) | |
1108 | { | |
1109 | if (address_present) | |
1110 | { | |
1111 | sim_io_printf (sd, | |
1112 | "The `sim firmware none' command does " | |
1113 | "not take an `ADDRESS' argument.\n"); | |
1114 | return SIM_RC_FAIL; | |
1115 | } | |
1116 | idt_monitor_base = 0; | |
1117 | pmon_monitor_base = 0; | |
1118 | lsipmon_monitor_base = 0; | |
1119 | } | |
1120 | else | |
1121 | { | |
1122 | sim_io_printf (sd, "\ | |
1123 | Unrecognized name given to the `sim firmware NAME' command: %s\n\ | |
1124 | Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n", | |
1125 | arg); | |
1126 | return SIM_RC_FAIL; | |
1127 | } | |
1128 | ||
1129 | return SIM_RC_OK; | |
1130 | } | |
1131 | ||
1132 | ||
1133 | ||
c906108c | 1134 | /* Simple monitor interface (currently setup for the IDT and PMON monitors) */ |
8030f857 | 1135 | int |
c906108c SS |
1136 | sim_monitor (SIM_DESC sd, |
1137 | sim_cpu *cpu, | |
1138 | address_word cia, | |
1139 | unsigned int reason) | |
1140 | { | |
1141 | #ifdef DEBUG | |
1142 | printf("DBG: sim_monitor: entered (reason = %d)\n",reason); | |
1143 | #endif /* DEBUG */ | |
1144 | ||
1145 | /* The IDT monitor actually allows two instructions per vector | |
1146 | slot. However, the simulator currently causes a trap on each | |
1147 | individual instruction. We cheat, and lose the bottom bit. */ | |
1148 | reason >>= 1; | |
1149 | ||
1150 | /* The following callback functions are available, however the | |
1151 | monitor we are simulating does not make use of them: get_errno, | |
1152 | isatty, lseek, rename, system, time and unlink */ | |
1153 | switch (reason) | |
1154 | { | |
1155 | ||
1156 | case 6: /* int open(char *path,int flags) */ | |
1157 | { | |
1158 | char *path = fetch_str (sd, A0); | |
1159 | V0 = sim_io_open (sd, path, (int)A1); | |
1160 | zfree (path); | |
1161 | break; | |
1162 | } | |
1163 | ||
1164 | case 7: /* int read(int file,char *ptr,int len) */ | |
1165 | { | |
1166 | int fd = A0; | |
1167 | int nr = A2; | |
1168 | char *buf = zalloc (nr); | |
1169 | V0 = sim_io_read (sd, fd, buf, nr); | |
1170 | sim_write (sd, A1, buf, nr); | |
1171 | zfree (buf); | |
1172 | } | |
1173 | break; | |
1174 | ||
1175 | case 8: /* int write(int file,char *ptr,int len) */ | |
1176 | { | |
1177 | int fd = A0; | |
1178 | int nr = A2; | |
1179 | char *buf = zalloc (nr); | |
1180 | sim_read (sd, A1, buf, nr); | |
1181 | V0 = sim_io_write (sd, fd, buf, nr); | |
1182 | zfree (buf); | |
1183 | break; | |
1184 | } | |
1185 | ||
1186 | case 10: /* int close(int file) */ | |
1187 | { | |
1188 | V0 = sim_io_close (sd, (int)A0); | |
1189 | break; | |
1190 | } | |
1191 | ||
1192 | case 2: /* Densan monitor: char inbyte(int waitflag) */ | |
1193 | { | |
1194 | if (A0 == 0) /* waitflag == NOWAIT */ | |
1195 | V0 = (unsigned_word)-1; | |
1196 | } | |
1197 | /* Drop through to case 11 */ | |
1198 | ||
1199 | case 11: /* char inbyte(void) */ | |
1200 | { | |
1201 | char tmp; | |
43e526b9 JM |
1202 | /* ensure that all output has gone... */ |
1203 | sim_io_flush_stdout (sd); | |
c906108c SS |
1204 | if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char)) |
1205 | { | |
1206 | sim_io_error(sd,"Invalid return from character read"); | |
1207 | V0 = (unsigned_word)-1; | |
1208 | } | |
1209 | else | |
1210 | V0 = (unsigned_word)tmp; | |
1211 | break; | |
1212 | } | |
1213 | ||
1214 | case 3: /* Densan monitor: void co(char chr) */ | |
1215 | case 12: /* void outbyte(char chr) : write a byte to "stdout" */ | |
1216 | { | |
1217 | char tmp = (char)(A0 & 0xFF); | |
1218 | sim_io_write_stdout (sd, &tmp, sizeof(char)); | |
1219 | break; | |
1220 | } | |
1221 | ||
1222 | case 17: /* void _exit() */ | |
1223 | { | |
1224 | sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n"); | |
1225 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited, | |
1226 | (unsigned int)(A0 & 0xFFFFFFFF)); | |
1227 | break; | |
1228 | } | |
1229 | ||
1230 | case 28 : /* PMON flush_cache */ | |
1231 | break; | |
1232 | ||
1233 | case 55: /* void get_mem_info(unsigned int *ptr) */ | |
1234 | /* in: A0 = pointer to three word memory location */ | |
1235 | /* out: [A0 + 0] = size */ | |
1236 | /* [A0 + 4] = instruction cache size */ | |
1237 | /* [A0 + 8] = data cache size */ | |
1238 | { | |
1239 | unsigned_4 value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */; | |
1240 | unsigned_4 zero = 0; | |
1241 | H2T (value); | |
1242 | sim_write (sd, A0 + 0, (char *)&value, 4); | |
1243 | sim_write (sd, A0 + 4, (char *)&zero, 4); | |
1244 | sim_write (sd, A0 + 8, (char *)&zero, 4); | |
1245 | /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */ | |
1246 | break; | |
1247 | } | |
1248 | ||
1249 | case 158 : /* PMON printf */ | |
1250 | /* in: A0 = pointer to format string */ | |
1251 | /* A1 = optional argument 1 */ | |
1252 | /* A2 = optional argument 2 */ | |
1253 | /* A3 = optional argument 3 */ | |
1254 | /* out: void */ | |
1255 | /* The following is based on the PMON printf source */ | |
1256 | { | |
1257 | address_word s = A0; | |
1258 | char c; | |
1259 | signed_word *ap = &A1; /* 1st argument */ | |
1260 | /* This isn't the quickest way, since we call the host print | |
1261 | routine for every character almost. But it does avoid | |
1262 | having to allocate and manage a temporary string buffer. */ | |
1263 | /* TODO: Include check that we only use three arguments (A1, | |
1264 | A2 and A3) */ | |
1265 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
1266 | { | |
1267 | if (c == '%') | |
1268 | { | |
1269 | char tmp[40]; | |
1270 | enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST; | |
1271 | int width = 0, trunc = 0, haddot = 0, longlong = 0; | |
1272 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
1273 | { | |
1274 | if (strchr ("dobxXulscefg%", c)) | |
1275 | break; | |
1276 | else if (c == '-') | |
1277 | fmt = FMT_LJUST; | |
1278 | else if (c == '0') | |
1279 | fmt = FMT_RJUST0; | |
1280 | else if (c == '~') | |
1281 | fmt = FMT_CENTER; | |
1282 | else if (c == '*') | |
1283 | { | |
1284 | if (haddot) | |
1285 | trunc = (int)*ap++; | |
1286 | else | |
1287 | width = (int)*ap++; | |
1288 | } | |
1289 | else if (c >= '1' && c <= '9') | |
1290 | { | |
1291 | address_word t = s; | |
1292 | unsigned int n; | |
1293 | while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c)) | |
1294 | tmp[s - t] = c; | |
1295 | tmp[s - t] = '\0'; | |
1296 | n = (unsigned int)strtol(tmp,NULL,10); | |
1297 | if (haddot) | |
1298 | trunc = n; | |
1299 | else | |
1300 | width = n; | |
1301 | s--; | |
1302 | } | |
1303 | else if (c == '.') | |
1304 | haddot = 1; | |
1305 | } | |
1306 | switch (c) | |
1307 | { | |
1308 | case '%': | |
1309 | sim_io_printf (sd, "%%"); | |
1310 | break; | |
1311 | case 's': | |
1312 | if ((int)*ap != 0) | |
1313 | { | |
1314 | address_word p = *ap++; | |
1315 | char ch; | |
1316 | while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0') | |
1317 | sim_io_printf(sd, "%c", ch); | |
1318 | } | |
1319 | else | |
1320 | sim_io_printf(sd,"(null)"); | |
1321 | break; | |
1322 | case 'c': | |
1323 | sim_io_printf (sd, "%c", (int)*ap++); | |
1324 | break; | |
1325 | default: | |
1326 | if (c == 'l') | |
1327 | { | |
1328 | sim_read (sd, s++, &c, 1); | |
1329 | if (c == 'l') | |
1330 | { | |
1331 | longlong = 1; | |
1332 | sim_read (sd, s++, &c, 1); | |
1333 | } | |
1334 | } | |
1335 | if (strchr ("dobxXu", c)) | |
1336 | { | |
1337 | word64 lv = (word64) *ap++; | |
1338 | if (c == 'b') | |
1339 | sim_io_printf(sd,"<binary not supported>"); | |
1340 | else | |
1341 | { | |
1342 | sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c); | |
1343 | if (longlong) | |
1344 | sim_io_printf(sd, tmp, lv); | |
1345 | else | |
1346 | sim_io_printf(sd, tmp, (int)lv); | |
1347 | } | |
1348 | } | |
1349 | else if (strchr ("eEfgG", c)) | |
1350 | { | |
1351 | double dbl = *(double*)(ap++); | |
1352 | sprintf (tmp, "%%%d.%d%c", width, trunc, c); | |
1353 | sim_io_printf (sd, tmp, dbl); | |
1354 | trunc = 0; | |
1355 | } | |
1356 | } | |
1357 | } | |
1358 | else | |
1359 | sim_io_printf(sd, "%c", c); | |
1360 | } | |
1361 | break; | |
1362 | } | |
1363 | ||
1364 | default: | |
8030f857 BE |
1365 | /* Unknown reason. */ |
1366 | return 0; | |
c906108c | 1367 | } |
8030f857 | 1368 | return 1; |
c906108c SS |
1369 | } |
1370 | ||
1371 | /* Store a word into memory. */ | |
1372 | ||
1373 | static void | |
1374 | store_word (SIM_DESC sd, | |
1375 | sim_cpu *cpu, | |
1376 | address_word cia, | |
1377 | uword64 vaddr, | |
1378 | signed_word val) | |
1379 | { | |
1380 | address_word paddr; | |
1381 | int uncached; | |
1382 | ||
1383 | if ((vaddr & 3) != 0) | |
1384 | SignalExceptionAddressStore (); | |
1385 | else | |
1386 | { | |
1387 | if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, | |
1388 | isTARGET, isREAL)) | |
1389 | { | |
1390 | const uword64 mask = 7; | |
1391 | uword64 memval; | |
1392 | unsigned int byte; | |
1393 | ||
1394 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)); | |
1395 | byte = (vaddr & mask) ^ (BigEndianCPU << 2); | |
1396 | memval = ((uword64) val) << (8 * byte); | |
1397 | StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, | |
1398 | isREAL); | |
1399 | } | |
1400 | } | |
1401 | } | |
1402 | ||
1403 | /* Load a word from memory. */ | |
1404 | ||
1405 | static signed_word | |
1406 | load_word (SIM_DESC sd, | |
1407 | sim_cpu *cpu, | |
1408 | address_word cia, | |
1409 | uword64 vaddr) | |
1410 | { | |
1411 | if ((vaddr & 3) != 0) | |
1412 | { | |
1413 | SIM_CORE_SIGNAL (SD, cpu, cia, read_map, AccessLength_WORD+1, vaddr, read_transfer, sim_core_unaligned_signal); | |
1414 | } | |
1415 | else | |
1416 | { | |
1417 | address_word paddr; | |
1418 | int uncached; | |
1419 | ||
1420 | if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, | |
1421 | isTARGET, isREAL)) | |
1422 | { | |
1423 | const uword64 mask = 0x7; | |
1424 | const unsigned int reverse = ReverseEndian ? 1 : 0; | |
1425 | const unsigned int bigend = BigEndianCPU ? 1 : 0; | |
1426 | uword64 memval; | |
1427 | unsigned int byte; | |
1428 | ||
1429 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2)); | |
1430 | LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr, | |
1431 | isDATA, isREAL); | |
1432 | byte = (vaddr & mask) ^ (bigend << 2); | |
043b7057 | 1433 | return EXTEND32 (memval >> (8 * byte)); |
c906108c SS |
1434 | } |
1435 | } | |
1436 | ||
1437 | return 0; | |
1438 | } | |
1439 | ||
1440 | /* Simulate the mips16 entry and exit pseudo-instructions. These | |
1441 | would normally be handled by the reserved instruction exception | |
1442 | code, but for ease of simulation we just handle them directly. */ | |
1443 | ||
1444 | static void | |
1445 | mips16_entry (SIM_DESC sd, | |
1446 | sim_cpu *cpu, | |
1447 | address_word cia, | |
1448 | unsigned int insn) | |
1449 | { | |
1450 | int aregs, sregs, rreg; | |
1451 | ||
1452 | #ifdef DEBUG | |
1453 | printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn); | |
1454 | #endif /* DEBUG */ | |
1455 | ||
1456 | aregs = (insn & 0x700) >> 8; | |
1457 | sregs = (insn & 0x0c0) >> 6; | |
1458 | rreg = (insn & 0x020) >> 5; | |
1459 | ||
1460 | /* This should be checked by the caller. */ | |
1461 | if (sregs == 3) | |
1462 | abort (); | |
1463 | ||
1464 | if (aregs < 5) | |
1465 | { | |
1466 | int i; | |
1467 | signed_word tsp; | |
1468 | ||
1469 | /* This is the entry pseudo-instruction. */ | |
1470 | ||
1471 | for (i = 0; i < aregs; i++) | |
1472 | store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]); | |
1473 | ||
1474 | tsp = SP; | |
1475 | SP -= 32; | |
1476 | ||
1477 | if (rreg) | |
1478 | { | |
1479 | tsp -= 4; | |
1480 | store_word (SD, CPU, cia, (uword64) tsp, RA); | |
1481 | } | |
1482 | ||
1483 | for (i = 0; i < sregs; i++) | |
1484 | { | |
1485 | tsp -= 4; | |
1486 | store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]); | |
1487 | } | |
1488 | } | |
1489 | else | |
1490 | { | |
1491 | int i; | |
1492 | signed_word tsp; | |
1493 | ||
1494 | /* This is the exit pseudo-instruction. */ | |
1495 | ||
1496 | tsp = SP + 32; | |
1497 | ||
1498 | if (rreg) | |
1499 | { | |
1500 | tsp -= 4; | |
1501 | RA = load_word (SD, CPU, cia, (uword64) tsp); | |
1502 | } | |
1503 | ||
1504 | for (i = 0; i < sregs; i++) | |
1505 | { | |
1506 | tsp -= 4; | |
1507 | GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp); | |
1508 | } | |
1509 | ||
1510 | SP += 32; | |
1511 | ||
1512 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) | |
1513 | { | |
1514 | if (aregs == 5) | |
1515 | { | |
1516 | FGR[0] = WORD64LO (GPR[4]); | |
1517 | FPR_STATE[0] = fmt_uninterpreted; | |
1518 | } | |
1519 | else if (aregs == 6) | |
1520 | { | |
1521 | FGR[0] = WORD64LO (GPR[5]); | |
1522 | FGR[1] = WORD64LO (GPR[4]); | |
1523 | FPR_STATE[0] = fmt_uninterpreted; | |
1524 | FPR_STATE[1] = fmt_uninterpreted; | |
1525 | } | |
1526 | } | |
1527 | ||
1528 | PC = RA; | |
1529 | } | |
1530 | ||
1531 | } | |
1532 | ||
1533 | /*-- trace support ----------------------------------------------------------*/ | |
1534 | ||
1535 | /* The TRACE support is provided (if required) in the memory accessing | |
1536 | routines. Since we are also providing the architecture specific | |
1537 | features, the architecture simulation code can also deal with | |
1538 | notifying the TRACE world of cache flushes, etc. Similarly we do | |
1539 | not need to provide profiling support in the simulator engine, | |
1540 | since we can sample in the instruction fetch control loop. By | |
1541 | defining the TRACE manifest, we add tracing as a run-time | |
1542 | option. */ | |
1543 | ||
1544 | #if defined(TRACE) | |
1545 | /* Tracing by default produces "din" format (as required by | |
1546 | dineroIII). Each line of such a trace file *MUST* have a din label | |
1547 | and address field. The rest of the line is ignored, so comments can | |
1548 | be included if desired. The first field is the label which must be | |
1549 | one of the following values: | |
1550 | ||
1551 | 0 read data | |
1552 | 1 write data | |
1553 | 2 instruction fetch | |
1554 | 3 escape record (treated as unknown access type) | |
1555 | 4 escape record (causes cache flush) | |
1556 | ||
1557 | The address field is a 32bit (lower-case) hexadecimal address | |
1558 | value. The address should *NOT* be preceded by "0x". | |
1559 | ||
1560 | The size of the memory transfer is not important when dealing with | |
1561 | cache lines (as long as no more than a cache line can be | |
1562 | transferred in a single operation :-), however more information | |
1563 | could be given following the dineroIII requirement to allow more | |
1564 | complete memory and cache simulators to provide better | |
1565 | results. i.e. the University of Pisa has a cache simulator that can | |
1566 | also take bus size and speed as (variable) inputs to calculate | |
1567 | complete system performance (a much more useful ability when trying | |
1568 | to construct an end product, rather than a processor). They | |
1569 | currently have an ARM version of their tool called ChARM. */ | |
1570 | ||
1571 | ||
1572 | void | |
1573 | dotrace (SIM_DESC sd, | |
1574 | sim_cpu *cpu, | |
1575 | FILE *tracefh, | |
1576 | int type, | |
1577 | SIM_ADDR address, | |
1578 | int width, | |
1579 | char *comment,...) | |
1580 | { | |
1581 | if (STATE & simTRACE) { | |
1582 | va_list ap; | |
1583 | fprintf(tracefh,"%d %s ; width %d ; ", | |
1584 | type, | |
1585 | pr_addr(address), | |
1586 | width); | |
1587 | va_start(ap,comment); | |
1588 | vfprintf(tracefh,comment,ap); | |
1589 | va_end(ap); | |
1590 | fprintf(tracefh,"\n"); | |
1591 | } | |
1592 | /* NOTE: Since the "din" format will only accept 32bit addresses, and | |
1593 | we may be generating 64bit ones, we should put the hi-32bits of the | |
1594 | address into the comment field. */ | |
1595 | ||
1596 | /* TODO: Provide a buffer for the trace lines. We can then avoid | |
1597 | performing writes until the buffer is filled, or the file is | |
1598 | being closed. */ | |
1599 | ||
1600 | /* NOTE: We could consider adding a comment field to the "din" file | |
1601 | produced using type 3 markers (unknown access). This would then | |
1602 | allow information about the program that the "din" is for, and | |
1603 | the MIPs world that was being simulated, to be placed into the | |
1604 | trace file. */ | |
1605 | ||
1606 | return; | |
1607 | } | |
1608 | #endif /* TRACE */ | |
1609 | ||
1610 | /*---------------------------------------------------------------------------*/ | |
1611 | /*-- simulator engine -------------------------------------------------------*/ | |
1612 | /*---------------------------------------------------------------------------*/ | |
1613 | ||
1614 | static void | |
1615 | ColdReset (SIM_DESC sd) | |
1616 | { | |
1617 | int cpu_nr; | |
1618 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) | |
1619 | { | |
1620 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); | |
1621 | /* RESET: Fixed PC address: */ | |
1622 | PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000); | |
1623 | /* The reset vector address is in the unmapped, uncached memory space. */ | |
1624 | ||
1625 | SR &= ~(status_SR | status_TS | status_RP); | |
1626 | SR |= (status_ERL | status_BEV); | |
1627 | ||
1628 | /* Cheat and allow access to the complete register set immediately */ | |
1629 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT | |
1630 | && WITH_TARGET_WORD_BITSIZE == 64) | |
1631 | SR |= status_FR; /* 64bit registers */ | |
1632 | ||
1633 | /* Ensure that any instructions with pending register updates are | |
1634 | cleared: */ | |
1635 | PENDING_INVALIDATE(); | |
1636 | ||
1637 | /* Initialise the FPU registers to the unknown state */ | |
1638 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) | |
1639 | { | |
1640 | int rn; | |
1641 | for (rn = 0; (rn < 32); rn++) | |
1642 | FPR_STATE[rn] = fmt_uninterpreted; | |
1643 | } | |
1644 | ||
1645 | } | |
1646 | } | |
1647 | ||
1648 | ||
1649 | ||
1650 | ||
1651 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1652 | /* Signal an exception condition. This will result in an exception | |
1653 | that aborts the instruction. The instruction operation pseudocode | |
1654 | will never see a return from this function call. */ | |
1655 | ||
1656 | void | |
1657 | signal_exception (SIM_DESC sd, | |
1658 | sim_cpu *cpu, | |
1659 | address_word cia, | |
1660 | int exception,...) | |
1661 | { | |
1662 | /* int vector; */ | |
1663 | ||
1664 | #ifdef DEBUG | |
1665 | sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); | |
1666 | #endif /* DEBUG */ | |
1667 | ||
1668 | /* Ensure that any active atomic read/modify/write operation will fail: */ | |
1669 | LLBIT = 0; | |
1670 | ||
1671 | /* Save registers before interrupt dispatching */ | |
1672 | #ifdef SIM_CPU_EXCEPTION_TRIGGER | |
1673 | SIM_CPU_EXCEPTION_TRIGGER(sd, cpu, cia); | |
1674 | #endif | |
1675 | ||
1676 | switch (exception) { | |
1677 | ||
1678 | case DebugBreakPoint : | |
1679 | if (! (Debug & Debug_DM)) | |
1680 | { | |
1681 | if (INDELAYSLOT()) | |
1682 | { | |
1683 | CANCELDELAYSLOT(); | |
1684 | ||
1685 | Debug |= Debug_DBD; /* signaled from within in delay slot */ | |
1686 | DEPC = cia - 4; /* reference the branch instruction */ | |
1687 | } | |
1688 | else | |
1689 | { | |
1690 | Debug &= ~Debug_DBD; /* not signaled from within a delay slot */ | |
1691 | DEPC = cia; | |
1692 | } | |
1693 | ||
1694 | Debug |= Debug_DM; /* in debugging mode */ | |
1695 | Debug |= Debug_DBp; /* raising a DBp exception */ | |
1696 | PC = 0xBFC00200; | |
1697 | sim_engine_restart (SD, CPU, NULL, NULL_CIA); | |
1698 | } | |
1699 | break; | |
1700 | ||
1701 | case ReservedInstruction : | |
1702 | { | |
1703 | va_list ap; | |
1704 | unsigned int instruction; | |
1705 | va_start(ap,exception); | |
1706 | instruction = va_arg(ap,unsigned int); | |
1707 | va_end(ap); | |
1708 | /* Provide simple monitor support using ReservedInstruction | |
1709 | exceptions. The following code simulates the fixed vector | |
1710 | entry points into the IDT monitor by causing a simulator | |
1711 | trap, performing the monitor operation, and returning to | |
1712 | the address held in the $ra register (standard PCS return | |
1713 | address). This means we only need to pre-load the vector | |
1714 | space with suitable instruction values. For systems were | |
1715 | actual trap instructions are used, we would not need to | |
1716 | perform this magic. */ | |
1717 | if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION) | |
1718 | { | |
8030f857 BE |
1719 | int reason = (instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK; |
1720 | if (!sim_monitor (SD, CPU, cia, reason)) | |
1721 | sim_io_error (sd, "sim_monitor: unhandled reason = %d, pc = 0x%s\n", reason, pr_addr (cia)); | |
1722 | ||
c906108c SS |
1723 | /* NOTE: This assumes that a branch-and-link style |
1724 | instruction was used to enter the vector (which is the | |
1725 | case with the current IDT monitor). */ | |
1726 | sim_engine_restart (SD, CPU, NULL, RA); | |
1727 | } | |
1728 | /* Look for the mips16 entry and exit instructions, and | |
1729 | simulate a handler for them. */ | |
1730 | else if ((cia & 1) != 0 | |
1731 | && (instruction & 0xf81f) == 0xe809 | |
1732 | && (instruction & 0x0c0) != 0x0c0) | |
1733 | { | |
1734 | mips16_entry (SD, CPU, cia, instruction); | |
1735 | sim_engine_restart (sd, NULL, NULL, NULL_CIA); | |
1736 | } | |
1737 | /* else fall through to normal exception processing */ | |
1738 | sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia)); | |
1739 | } | |
1740 | ||
1741 | default: | |
1742 | /* Store exception code into current exception id variable (used | |
1743 | by exit code): */ | |
1744 | ||
1745 | /* TODO: If not simulating exceptions then stop the simulator | |
1746 | execution. At the moment we always stop the simulation. */ | |
1747 | ||
1748 | #ifdef SUBTARGET_R3900 | |
1749 | /* update interrupt-related registers */ | |
1750 | ||
1751 | /* insert exception code in bits 6:2 */ | |
1752 | CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2); | |
1753 | /* shift IE/KU history bits left */ | |
1754 | SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2); | |
1755 | ||
1756 | if (STATE & simDELAYSLOT) | |
1757 | { | |
1758 | STATE &= ~simDELAYSLOT; | |
1759 | CAUSE |= cause_BD; | |
1760 | EPC = (cia - 4); /* reference the branch instruction */ | |
1761 | } | |
1762 | else | |
1763 | EPC = cia; | |
1764 | ||
1765 | if (SR & status_BEV) | |
1766 | PC = (signed)0xBFC00000 + 0x180; | |
1767 | else | |
1768 | PC = (signed)0x80000000 + 0x080; | |
1769 | #else | |
1770 | /* See figure 5-17 for an outline of the code below */ | |
1771 | if (! (SR & status_EXL)) | |
1772 | { | |
1773 | CAUSE = (exception << 2); | |
1774 | if (STATE & simDELAYSLOT) | |
1775 | { | |
1776 | STATE &= ~simDELAYSLOT; | |
1777 | CAUSE |= cause_BD; | |
1778 | EPC = (cia - 4); /* reference the branch instruction */ | |
1779 | } | |
1780 | else | |
1781 | EPC = cia; | |
1782 | /* FIXME: TLB et.al. */ | |
1783 | /* vector = 0x180; */ | |
1784 | } | |
1785 | else | |
1786 | { | |
1787 | CAUSE = (exception << 2); | |
1788 | /* vector = 0x180; */ | |
1789 | } | |
1790 | SR |= status_EXL; | |
1791 | /* Store exception code into current exception id variable (used | |
1792 | by exit code): */ | |
1793 | ||
1794 | if (SR & status_BEV) | |
1795 | PC = (signed)0xBFC00200 + 0x180; | |
1796 | else | |
1797 | PC = (signed)0x80000000 + 0x180; | |
1798 | #endif | |
1799 | ||
1800 | switch ((CAUSE >> 2) & 0x1F) | |
1801 | { | |
1802 | case Interrupt: | |
1803 | /* Interrupts arrive during event processing, no need to | |
1804 | restart */ | |
1805 | return; | |
1806 | ||
1807 | case NMIReset: | |
1808 | /* Ditto */ | |
1809 | #ifdef SUBTARGET_3900 | |
1810 | /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */ | |
1811 | PC = (signed)0xBFC00000; | |
0d3e762b | 1812 | #endif /* SUBTARGET_3900 */ |
c906108c SS |
1813 | return; |
1814 | ||
1815 | case TLBModification: | |
1816 | case TLBLoad: | |
1817 | case TLBStore: | |
1818 | case AddressLoad: | |
1819 | case AddressStore: | |
1820 | case InstructionFetch: | |
1821 | case DataReference: | |
1822 | /* The following is so that the simulator will continue from the | |
1823 | exception handler address. */ | |
1824 | sim_engine_halt (SD, CPU, NULL, PC, | |
1825 | sim_stopped, SIM_SIGBUS); | |
1826 | ||
1827 | case ReservedInstruction: | |
1828 | case CoProcessorUnusable: | |
1829 | PC = EPC; | |
1830 | sim_engine_halt (SD, CPU, NULL, PC, | |
1831 | sim_stopped, SIM_SIGILL); | |
1832 | ||
1833 | case IntegerOverflow: | |
1834 | case FPE: | |
1835 | sim_engine_halt (SD, CPU, NULL, PC, | |
1836 | sim_stopped, SIM_SIGFPE); | |
1837 | ||
1838 | case BreakPoint: | |
1839 | sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP); | |
1840 | break; | |
1841 | ||
1842 | case SystemCall: | |
1843 | case Trap: | |
1844 | sim_engine_restart (SD, CPU, NULL, PC); | |
1845 | break; | |
1846 | ||
1847 | case Watch: | |
1848 | PC = EPC; | |
1849 | sim_engine_halt (SD, CPU, NULL, PC, | |
1850 | sim_stopped, SIM_SIGTRAP); | |
1851 | ||
1852 | default : /* Unknown internal exception */ | |
1853 | PC = EPC; | |
1854 | sim_engine_halt (SD, CPU, NULL, PC, | |
1855 | sim_stopped, SIM_SIGABRT); | |
1856 | ||
1857 | } | |
1858 | ||
1859 | case SimulatorFault: | |
1860 | { | |
1861 | va_list ap; | |
1862 | char *msg; | |
1863 | va_start(ap,exception); | |
1864 | msg = va_arg(ap,char *); | |
1865 | va_end(ap); | |
1866 | sim_engine_abort (SD, CPU, NULL_CIA, | |
1867 | "FATAL: Simulator error \"%s\"\n",msg); | |
1868 | } | |
1869 | } | |
1870 | ||
1871 | return; | |
1872 | } | |
1873 | ||
1874 | ||
1875 | ||
1876 | #if defined(WARN_RESULT) | |
1877 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1878 | /* This function indicates that the result of the operation is | |
1879 | undefined. However, this should not affect the instruction | |
1880 | stream. All that is meant to happen is that the destination | |
1881 | register is set to an undefined result. To keep the simulator | |
1882 | simple, we just don't bother updating the destination register, so | |
1883 | the overall result will be undefined. If desired we can stop the | |
1884 | simulator by raising a pseudo-exception. */ | |
1885 | #define UndefinedResult() undefined_result (sd,cia) | |
1886 | static void | |
1887 | undefined_result(sd,cia) | |
1888 | SIM_DESC sd; | |
1889 | address_word cia; | |
1890 | { | |
1891 | sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia)); | |
1892 | #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */ | |
1893 | state |= simSTOP; | |
1894 | #endif | |
1895 | return; | |
1896 | } | |
1897 | #endif /* WARN_RESULT */ | |
1898 | ||
c906108c SS |
1899 | |
1900 | /*-- co-processor support routines ------------------------------------------*/ | |
1901 | ||
1902 | static int UNUSED | |
1903 | CoProcPresent(unsigned int coproc_number) | |
1904 | { | |
1905 | /* Return TRUE if simulator provides a model for the given co-processor number */ | |
1906 | return(0); | |
1907 | } | |
1908 | ||
1909 | void | |
1910 | cop_lw (SIM_DESC sd, | |
1911 | sim_cpu *cpu, | |
1912 | address_word cia, | |
1913 | int coproc_num, | |
1914 | int coproc_reg, | |
1915 | unsigned int memword) | |
1916 | { | |
1917 | switch (coproc_num) | |
1918 | { | |
1919 | case 1: | |
1920 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) | |
1921 | { | |
1922 | #ifdef DEBUG | |
1923 | printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword)); | |
1924 | #endif | |
1925 | StoreFPR(coproc_reg,fmt_word,(uword64)memword); | |
1926 | FPR_STATE[coproc_reg] = fmt_uninterpreted; | |
1927 | break; | |
1928 | } | |
1929 | ||
1930 | default: | |
1931 | #if 0 /* this should be controlled by a configuration option */ | |
1932 | sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia)); | |
1933 | #endif | |
1934 | break; | |
1935 | } | |
1936 | ||
1937 | return; | |
1938 | } | |
1939 | ||
1940 | void | |
1941 | cop_ld (SIM_DESC sd, | |
1942 | sim_cpu *cpu, | |
1943 | address_word cia, | |
1944 | int coproc_num, | |
1945 | int coproc_reg, | |
1946 | uword64 memword) | |
1947 | { | |
1948 | ||
1949 | #ifdef DEBUG | |
1950 | printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia) ); | |
1951 | #endif | |
1952 | ||
1953 | switch (coproc_num) { | |
1954 | case 1: | |
1955 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) | |
1956 | { | |
1957 | StoreFPR(coproc_reg,fmt_uninterpreted,memword); | |
1958 | break; | |
1959 | } | |
1960 | ||
1961 | default: | |
1962 | #if 0 /* this message should be controlled by a configuration option */ | |
1963 | sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia)); | |
1964 | #endif | |
1965 | break; | |
1966 | } | |
1967 | ||
1968 | return; | |
1969 | } | |
1970 | ||
1971 | ||
1972 | ||
1973 | ||
1974 | unsigned int | |
1975 | cop_sw (SIM_DESC sd, | |
1976 | sim_cpu *cpu, | |
1977 | address_word cia, | |
1978 | int coproc_num, | |
1979 | int coproc_reg) | |
1980 | { | |
1981 | unsigned int value = 0; | |
1982 | ||
1983 | switch (coproc_num) | |
1984 | { | |
1985 | case 1: | |
1986 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) | |
1987 | { | |
1988 | FP_formats hold; | |
1989 | hold = FPR_STATE[coproc_reg]; | |
1990 | FPR_STATE[coproc_reg] = fmt_word; | |
1991 | value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted); | |
1992 | FPR_STATE[coproc_reg] = hold; | |
1993 | break; | |
1994 | } | |
1995 | ||
1996 | default: | |
1997 | #if 0 /* should be controlled by configuration option */ | |
1998 | sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); | |
1999 | #endif | |
2000 | break; | |
2001 | } | |
2002 | ||
2003 | return(value); | |
2004 | } | |
2005 | ||
2006 | uword64 | |
2007 | cop_sd (SIM_DESC sd, | |
2008 | sim_cpu *cpu, | |
2009 | address_word cia, | |
2010 | int coproc_num, | |
2011 | int coproc_reg) | |
2012 | { | |
2013 | uword64 value = 0; | |
2014 | switch (coproc_num) | |
2015 | { | |
2016 | case 1: | |
2017 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) | |
2018 | { | |
2019 | value = ValueFPR(coproc_reg,fmt_uninterpreted); | |
2020 | break; | |
2021 | } | |
2022 | ||
2023 | default: | |
2024 | #if 0 /* should be controlled by configuration option */ | |
2025 | sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); | |
2026 | #endif | |
2027 | break; | |
2028 | } | |
2029 | ||
2030 | return(value); | |
2031 | } | |
2032 | ||
2033 | ||
2034 | ||
2035 | ||
2036 | void | |
2037 | decode_coproc (SIM_DESC sd, | |
2038 | sim_cpu *cpu, | |
2039 | address_word cia, | |
2040 | unsigned int instruction) | |
2041 | { | |
2042 | int coprocnum = ((instruction >> 26) & 3); | |
2043 | ||
2044 | switch (coprocnum) | |
2045 | { | |
2046 | case 0: /* standard CPU control and cache registers */ | |
2047 | { | |
2048 | int code = ((instruction >> 21) & 0x1F); | |
2049 | int rt = ((instruction >> 16) & 0x1F); | |
2050 | int rd = ((instruction >> 11) & 0x1F); | |
2051 | int tail = instruction & 0x3ff; | |
2052 | /* R4000 Users Manual (second edition) lists the following CP0 | |
2053 | instructions: | |
2054 | CODE><-RT><RD-><--TAIL---> | |
2055 | DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000) | |
2056 | DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000) | |
2057 | MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000) | |
2058 | MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000) | |
2059 | TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001) | |
2060 | TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010) | |
2061 | TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110) | |
2062 | TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000) | |
2063 | CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii) | |
2064 | ERET Exception return (VR4100 = 01000010000000000000000000011000) | |
2065 | */ | |
4ce44c66 JM |
2066 | if (((code == 0x00) || (code == 0x04) /* MFC0 / MTC0 */ |
2067 | || (code == 0x01) || (code == 0x05)) /* DMFC0 / DMTC0 */ | |
2068 | && tail == 0) | |
c906108c | 2069 | { |
4ce44c66 JM |
2070 | /* Clear double/single coprocessor move bit. */ |
2071 | code &= ~1; | |
2072 | ||
2073 | /* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */ | |
c906108c SS |
2074 | |
2075 | switch (rd) /* NOTEs: Standard CP0 registers */ | |
2076 | { | |
2077 | /* 0 = Index R4000 VR4100 VR4300 */ | |
2078 | /* 1 = Random R4000 VR4100 VR4300 */ | |
2079 | /* 2 = EntryLo0 R4000 VR4100 VR4300 */ | |
2080 | /* 3 = EntryLo1 R4000 VR4100 VR4300 */ | |
2081 | /* 4 = Context R4000 VR4100 VR4300 */ | |
2082 | /* 5 = PageMask R4000 VR4100 VR4300 */ | |
2083 | /* 6 = Wired R4000 VR4100 VR4300 */ | |
2084 | /* 8 = BadVAddr R4000 VR4100 VR4300 */ | |
2085 | /* 9 = Count R4000 VR4100 VR4300 */ | |
2086 | /* 10 = EntryHi R4000 VR4100 VR4300 */ | |
2087 | /* 11 = Compare R4000 VR4100 VR4300 */ | |
2088 | /* 12 = SR R4000 VR4100 VR4300 */ | |
2089 | #ifdef SUBTARGET_R3900 | |
2090 | case 3: | |
2091 | /* 3 = Config R3900 */ | |
2092 | case 7: | |
2093 | /* 7 = Cache R3900 */ | |
2094 | case 15: | |
2095 | /* 15 = PRID R3900 */ | |
2096 | ||
2097 | /* ignore */ | |
2098 | break; | |
2099 | ||
2100 | case 8: | |
2101 | /* 8 = BadVAddr R4000 VR4100 VR4300 */ | |
2102 | if (code == 0x00) | |
2103 | GPR[rt] = COP0_BADVADDR; | |
2104 | else | |
2105 | COP0_BADVADDR = GPR[rt]; | |
2106 | break; | |
2107 | ||
2108 | #endif /* SUBTARGET_R3900 */ | |
2109 | case 12: | |
2110 | if (code == 0x00) | |
2111 | GPR[rt] = SR; | |
2112 | else | |
2113 | SR = GPR[rt]; | |
2114 | break; | |
2115 | /* 13 = Cause R4000 VR4100 VR4300 */ | |
2116 | case 13: | |
2117 | if (code == 0x00) | |
2118 | GPR[rt] = CAUSE; | |
2119 | else | |
2120 | CAUSE = GPR[rt]; | |
2121 | break; | |
2122 | /* 14 = EPC R4000 VR4100 VR4300 */ | |
2123 | case 14: | |
2124 | if (code == 0x00) | |
2125 | GPR[rt] = (signed_word) (signed_address) EPC; | |
2126 | else | |
2127 | EPC = GPR[rt]; | |
2128 | break; | |
2129 | /* 15 = PRId R4000 VR4100 VR4300 */ | |
2130 | #ifdef SUBTARGET_R3900 | |
2131 | /* 16 = Debug */ | |
2132 | case 16: | |
2133 | if (code == 0x00) | |
2134 | GPR[rt] = Debug; | |
2135 | else | |
2136 | Debug = GPR[rt]; | |
2137 | break; | |
2138 | #else | |
2139 | /* 16 = Config R4000 VR4100 VR4300 */ | |
2140 | case 16: | |
2141 | if (code == 0x00) | |
2142 | GPR[rt] = C0_CONFIG; | |
2143 | else | |
2144 | C0_CONFIG = GPR[rt]; | |
2145 | break; | |
2146 | #endif | |
2147 | #ifdef SUBTARGET_R3900 | |
2148 | /* 17 = Debug */ | |
2149 | case 17: | |
2150 | if (code == 0x00) | |
2151 | GPR[rt] = DEPC; | |
2152 | else | |
2153 | DEPC = GPR[rt]; | |
2154 | break; | |
2155 | #else | |
2156 | /* 17 = LLAddr R4000 VR4100 VR4300 */ | |
2157 | #endif | |
2158 | /* 18 = WatchLo R4000 VR4100 VR4300 */ | |
2159 | /* 19 = WatchHi R4000 VR4100 VR4300 */ | |
2160 | /* 20 = XContext R4000 VR4100 VR4300 */ | |
2161 | /* 26 = PErr or ECC R4000 VR4100 VR4300 */ | |
2162 | /* 27 = CacheErr R4000 VR4100 */ | |
2163 | /* 28 = TagLo R4000 VR4100 VR4300 */ | |
2164 | /* 29 = TagHi R4000 VR4100 VR4300 */ | |
2165 | /* 30 = ErrorEPC R4000 VR4100 VR4300 */ | |
a3027dd7 FCE |
2166 | if (STATE_VERBOSE_P(SD)) |
2167 | sim_io_eprintf (SD, | |
e30db738 AC |
2168 | "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n", |
2169 | (unsigned long)cia); | |
c906108c SS |
2170 | GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */ |
2171 | /* CPR[0,rd] = GPR[rt]; */ | |
2172 | default: | |
2173 | if (code == 0x00) | |
2174 | GPR[rt] = (signed_word) (signed32) COP0_GPR[rd]; | |
2175 | else | |
2176 | COP0_GPR[rd] = GPR[rt]; | |
2177 | #if 0 | |
2178 | if (code == 0x00) | |
2179 | sim_io_printf(sd,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia); | |
2180 | else | |
2181 | sim_io_printf(sd,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia); | |
2182 | #endif | |
2183 | } | |
2184 | } | |
2185 | else if (code == 0x10 && (tail & 0x3f) == 0x18) | |
2186 | { | |
2187 | /* ERET */ | |
2188 | if (SR & status_ERL) | |
2189 | { | |
2190 | /* Oops, not yet available */ | |
2191 | sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet"); | |
2192 | PC = EPC; | |
2193 | SR &= ~status_ERL; | |
2194 | } | |
2195 | else | |
2196 | { | |
2197 | PC = EPC; | |
2198 | SR &= ~status_EXL; | |
2199 | } | |
2200 | } | |
2201 | else if (code == 0x10 && (tail & 0x3f) == 0x10) | |
2202 | { | |
2203 | /* RFE */ | |
2204 | #ifdef SUBTARGET_R3900 | |
2205 | /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */ | |
2206 | ||
2207 | /* shift IE/KU history bits right */ | |
2208 | SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0); | |
2209 | ||
2210 | /* TODO: CACHE register */ | |
2211 | #endif /* SUBTARGET_R3900 */ | |
2212 | } | |
2213 | else if (code == 0x10 && (tail & 0x3f) == 0x1F) | |
2214 | { | |
2215 | /* DERET */ | |
2216 | Debug &= ~Debug_DM; | |
2217 | DELAYSLOT(); | |
2218 | DSPC = DEPC; | |
2219 | } | |
2220 | else | |
2221 | sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia)); | |
2222 | /* TODO: When executing an ERET or RFE instruction we should | |
2223 | clear LLBIT, to ensure that any out-standing atomic | |
2224 | read/modify/write sequence fails. */ | |
2225 | } | |
2226 | break; | |
2227 | ||
2228 | case 2: /* co-processor 2 */ | |
2229 | { | |
2230 | int handle = 0; | |
2231 | ||
2232 | ||
2233 | if(! handle) | |
2234 | { | |
2235 | sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n", | |
2236 | instruction,pr_addr(cia)); | |
2237 | } | |
2238 | } | |
2239 | break; | |
2240 | ||
2241 | case 1: /* should not occur (FPU co-processor) */ | |
2242 | case 3: /* should not occur (FPU co-processor) */ | |
2243 | SignalException(ReservedInstruction,instruction); | |
2244 | break; | |
2245 | } | |
2246 | ||
2247 | return; | |
2248 | } | |
2249 | ||
2250 | ||
2251 | /* This code copied from gdb's utils.c. Would like to share this code, | |
2252 | but don't know of a common place where both could get to it. */ | |
2253 | ||
2254 | /* Temporary storage using circular buffer */ | |
2255 | #define NUMCELLS 16 | |
2256 | #define CELLSIZE 32 | |
2257 | static char* | |
2258 | get_cell (void) | |
2259 | { | |
2260 | static char buf[NUMCELLS][CELLSIZE]; | |
2261 | static int cell=0; | |
2262 | if (++cell>=NUMCELLS) cell=0; | |
2263 | return buf[cell]; | |
2264 | } | |
2265 | ||
2266 | /* Print routines to handle variable size regs, etc */ | |
2267 | ||
2268 | /* Eliminate warning from compiler on 32-bit systems */ | |
2269 | static int thirty_two = 32; | |
2270 | ||
2271 | char* | |
2272 | pr_addr(addr) | |
2273 | SIM_ADDR addr; | |
2274 | { | |
2275 | char *paddr_str=get_cell(); | |
2276 | switch (sizeof(addr)) | |
2277 | { | |
2278 | case 8: | |
2279 | sprintf(paddr_str,"%08lx%08lx", | |
2280 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); | |
2281 | break; | |
2282 | case 4: | |
2283 | sprintf(paddr_str,"%08lx",(unsigned long)addr); | |
2284 | break; | |
2285 | case 2: | |
2286 | sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff)); | |
2287 | break; | |
2288 | default: | |
2289 | sprintf(paddr_str,"%x",addr); | |
2290 | } | |
2291 | return paddr_str; | |
2292 | } | |
2293 | ||
2294 | char* | |
2295 | pr_uword64(addr) | |
2296 | uword64 addr; | |
2297 | { | |
2298 | char *paddr_str=get_cell(); | |
2299 | sprintf(paddr_str,"%08lx%08lx", | |
2300 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); | |
2301 | return paddr_str; | |
2302 | } | |
2303 | ||
2304 | ||
2305 | void | |
2306 | mips_core_signal (SIM_DESC sd, | |
2307 | sim_cpu *cpu, | |
2308 | sim_cia cia, | |
2309 | unsigned map, | |
2310 | int nr_bytes, | |
2311 | address_word addr, | |
2312 | transfer_type transfer, | |
2313 | sim_core_signals sig) | |
2314 | { | |
2315 | const char *copy = (transfer == read_transfer ? "read" : "write"); | |
2316 | address_word ip = CIA_ADDR (cia); | |
2317 | ||
2318 | switch (sig) | |
2319 | { | |
2320 | case sim_core_unmapped_signal: | |
2321 | sim_io_eprintf (sd, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n", | |
2322 | nr_bytes, copy, | |
2323 | (unsigned long) addr, (unsigned long) ip); | |
2324 | COP0_BADVADDR = addr; | |
2325 | SignalExceptionDataReference(); | |
2326 | break; | |
2327 | ||
2328 | case sim_core_unaligned_signal: | |
2329 | sim_io_eprintf (sd, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n", | |
2330 | nr_bytes, copy, | |
2331 | (unsigned long) addr, (unsigned long) ip); | |
2332 | COP0_BADVADDR = addr; | |
2333 | if(transfer == read_transfer) | |
2334 | SignalExceptionAddressLoad(); | |
2335 | else | |
2336 | SignalExceptionAddressStore(); | |
2337 | break; | |
2338 | ||
2339 | default: | |
2340 | sim_engine_abort (sd, cpu, cia, | |
2341 | "mips_core_signal - internal error - bad switch"); | |
2342 | } | |
2343 | } | |
2344 | ||
2345 | ||
2346 | void | |
2347 | mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia) | |
2348 | { | |
2349 | ASSERT(cpu != NULL); | |
2350 | ||
2351 | if(cpu->exc_suspended > 0) | |
2352 | sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended); | |
2353 | ||
2354 | PC = cia; | |
2355 | memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers)); | |
2356 | cpu->exc_suspended = 0; | |
2357 | } | |
2358 | ||
2359 | void | |
2360 | mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception) | |
2361 | { | |
2362 | ASSERT(cpu != NULL); | |
2363 | ||
2364 | if(cpu->exc_suspended > 0) | |
2365 | sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n", | |
2366 | cpu->exc_suspended, exception); | |
2367 | ||
2368 | memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers)); | |
2369 | memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers)); | |
2370 | cpu->exc_suspended = exception; | |
2371 | } | |
2372 | ||
2373 | void | |
2374 | mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception) | |
2375 | { | |
2376 | ASSERT(cpu != NULL); | |
2377 | ||
2378 | if(exception == 0 && cpu->exc_suspended > 0) | |
2379 | { | |
2380 | /* warn not for breakpoints */ | |
2381 | if(cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP)) | |
2382 | sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n", | |
2383 | cpu->exc_suspended); | |
2384 | } | |
2385 | else if(exception != 0 && cpu->exc_suspended > 0) | |
2386 | { | |
2387 | if(exception != cpu->exc_suspended) | |
2388 | sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n", | |
2389 | cpu->exc_suspended, exception); | |
2390 | ||
2391 | memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers)); | |
2392 | } | |
2393 | else if(exception != 0 && cpu->exc_suspended == 0) | |
2394 | { | |
2395 | sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception); | |
2396 | } | |
2397 | cpu->exc_suspended = 0; | |
2398 | } | |
2399 | ||
2400 | ||
2401 | /*---------------------------------------------------------------------------*/ | |
2402 | /*> EOF interp.c <*/ |