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8bae0a0c JSC |
1 | /*> interp.c <*/ |
2 | /* Simulator for the MIPS architecture. | |
3 | ||
4 | This file is part of the MIPS sim | |
5 | ||
6 | THIS SOFTWARE IS NOT COPYRIGHTED | |
7 | ||
8 | Cygnus offers the following for use in the public domain. Cygnus | |
9 | makes no warranty with regard to the software or it's performance | |
10 | and the user accepts the software "AS IS" with all faults. | |
11 | ||
12 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
13 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
14 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
15 | ||
16 | $Revision$ | |
17 | $Author$ | |
18 | $Date$ | |
19 | ||
20 | NOTEs: | |
21 | ||
22 | We only need to take account of the target endianness when moving data | |
23 | between the simulator and the host. We do not need to worry about the | |
24 | endianness of the host, since this sim code and GDB are executing in | |
25 | the same process. | |
26 | ||
27 | The IDT monitor (found on the VR4300 board), seems to lie about | |
28 | register contents. It seems to treat the registers as sign-extended | |
29 | 32-bit values. This cause *REAL* problems when single-stepping 64-bit | |
30 | code on the hardware. | |
31 | ||
32 | */ | |
33 | ||
34 | /* The TRACE and PROFILE manifests enable the provision of extra | |
35 | features. If they are not defined then a simpler (quicker) | |
36 | simulator is constructed without the required run-time checks, | |
37 | etc. */ | |
38 | #if 1 /* 0 to allow user build selection, 1 to force inclusion */ | |
39 | #define TRACE (1) | |
40 | #define PROFILE (1) | |
41 | #endif | |
42 | ||
43 | #include <stdio.h> | |
44 | #include <stdarg.h> | |
45 | #include <ansidecl.h> | |
46 | #include <signal.h> | |
47 | #include <ctype.h> | |
48 | #include <limits.h> | |
49 | #include <math.h> | |
50 | ||
51 | #include "getopt.h" | |
52 | #include "libiberty.h" | |
53 | ||
54 | #include "remote-sim.h" /* GDB simulator interface */ | |
55 | #include "callback.h" /* GDB simulator callback interface */ | |
56 | ||
57 | #include "support.h" /* internal support manifests */ | |
58 | ||
59 | /* Get the simulator engine description, without including the code: */ | |
60 | #define SIM_MANIFESTS | |
61 | #include "engine.c" | |
62 | #undef SIM_MANIFESTS | |
63 | ||
64 | /* The following reserved instruction value is used when a simulator | |
65 | trap is required. NOTE: Care must be taken, since this value may be | |
66 | used in later revisions of the MIPS ISA. */ | |
67 | #define RSVD_INSTRUCTION (0x7C000000) | |
68 | #define RSVD_INSTRUCTION_AMASK (0x03FFFFFF) | |
69 | ||
70 | /* NOTE: These numbers depend on the processor architecture being | |
71 | simulated: */ | |
72 | #define Interrupt (0) | |
73 | #define TLBModification (1) | |
74 | #define TLBLoad (2) | |
75 | #define TLBStore (3) | |
76 | #define AddressLoad (4) | |
77 | #define AddressStore (5) | |
78 | #define InstructionFetch (6) | |
79 | #define DataReference (7) | |
80 | #define SystemCall (8) | |
81 | #define BreakPoint (9) | |
82 | #define ReservedInstruction (10) | |
83 | #define CoProcessorUnusable (11) | |
84 | #define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */ | |
85 | #define Trap (13) | |
86 | #define FPE (15) | |
87 | #define Watch (23) | |
88 | ||
89 | /* The following exception code is actually private to the simulator | |
90 | world. It is *NOT* a processor feature, and is used to signal | |
91 | run-time errors in the simulator. */ | |
92 | #define SimulatorFault (0xFFFFFFFF) | |
93 | ||
94 | /* The following are generic to all versions of the MIPS architecture | |
95 | to date: */ | |
96 | /* Memory Access Types (for CCA): */ | |
97 | #define Uncached (0) | |
98 | #define CachedNoncoherent (1) | |
99 | #define CachedCoherent (2) | |
100 | #define Cached (3) | |
101 | ||
102 | #define isINSTRUCTION (1 == 0) /* FALSE */ | |
103 | #define isDATA (1 == 1) /* TRUE */ | |
104 | ||
105 | #define isLOAD (1 == 0) /* FALSE */ | |
106 | #define isSTORE (1 == 1) /* TRUE */ | |
107 | ||
108 | #define isREAL (1 == 0) /* FALSE */ | |
109 | #define isRAW (1 == 1) /* TRUE */ | |
110 | ||
111 | #define isTARGET (1 == 0) /* FALSE */ | |
112 | #define isHOST (1 == 1) /* TRUE */ | |
113 | ||
114 | /* The "AccessLength" specifications for Loads and Stores. NOTE: This | |
115 | is the number of bytes minus 1. */ | |
116 | #define AccessLength_BYTE (0) | |
117 | #define AccessLength_HALFWORD (1) | |
118 | #define AccessLength_TRIPLEBYTE (2) | |
119 | #define AccessLength_WORD (3) | |
120 | #define AccessLength_QUINTIBYTE (4) | |
121 | #define AccessLength_SEXTIBYTE (5) | |
122 | #define AccessLength_SEPTIBYTE (6) | |
123 | #define AccessLength_DOUBLEWORD (7) | |
124 | ||
125 | #if defined(HASFPU) | |
126 | /* FPU registers must be one of the following types. All other values | |
127 | are reserved (and undefined). */ | |
128 | typedef enum { | |
129 | fmt_single = 0, | |
130 | fmt_double = 1, | |
131 | fmt_word = 4, | |
132 | fmt_long = 5, | |
133 | /* The following are well outside the normal acceptable format | |
134 | range, and are used in the register status vector. */ | |
135 | fmt_unknown = 0x10000000, | |
136 | fmt_uninterpreted = 0x20000000, | |
137 | } FP_formats; | |
138 | #endif /* HASFPU */ | |
139 | ||
140 | /* NOTE: We cannot avoid globals, since the GDB "sim_" interface does | |
141 | not allow a private variable to be passed around. This means that | |
142 | simulators under GDB can only be single-threaded. However, it would | |
143 | be possible for the simulators to be multi-threaded if GDB allowed | |
144 | for a private pointer to be maintained. i.e. a general "void **ptr" | |
145 | variable that GDB passed around in the argument list to all of | |
146 | sim_xxx() routines. It could be initialised to NULL by GDB, and | |
147 | then updated by sim_open() and used by the other sim_xxx() support | |
148 | functions. This would allow new features in the simulator world, | |
149 | like storing a context - continuing execution to gather a result, | |
150 | and then going back to the point where the context was saved and | |
151 | changing some state before continuing. i.e. the ability to perform | |
152 | UNDOs on simulations. It would also allow the simulation of | |
153 | shared-memory multi-processor systems. */ | |
154 | ||
155 | static host_callback *callback = NULL; /* handle onto the current callback structure */ | |
156 | ||
157 | /* The warning system should be improved, to allow more information to | |
158 | be passed about the cause: */ | |
159 | #define WARNING(m) { callback->printf_filtered(callback,"SIM Warning: %s\n",(m)); } | |
160 | ||
161 | /* This is nasty, since we have to rely on matching the register | |
162 | numbers used by GDB. Unfortunately, depending on the MIPS target | |
163 | GDB uses different register numbers. We cannot just include the | |
164 | relevant "gdb/tm.h" link, since GDB may not be configured before | |
165 | the sim world, and also the GDB header file requires too much other | |
166 | state. */ | |
167 | /* TODO: Sort out a scheme for *KNOWING* the mapping between real | |
168 | registers, and the numbers that GDB uses. At the moment due to the | |
169 | order that the tools are built, we cannot rely on a configured GDB | |
170 | world whilst constructing the simulator. This means we have to | |
171 | assume the GDB register number mapping. */ | |
172 | #define LAST_EMBED_REGNUM (89) | |
173 | ||
174 | /* To keep this default simulator simple, and fast, we use a direct | |
175 | vector of registers. The internal simulator engine then uses | |
176 | manifests to access the correct slot. */ | |
177 | ut_reg registers[LAST_EMBED_REGNUM + 1]; | |
178 | int register_widths[LAST_EMBED_REGNUM + 1]; | |
179 | ||
180 | #define GPR (®isters[0]) | |
181 | #if defined(HASFPU) | |
182 | #define FGRIDX (38) | |
183 | #define FGR (®isters[FGRIDX]) | |
184 | #endif /* HASFPU */ | |
185 | #define LO (registers[33]) | |
186 | #define HI (registers[34]) | |
187 | #define PC (registers[37]) | |
188 | #define CAUSE (registers[36]) | |
189 | #define SRIDX (32) | |
190 | #define SR (registers[SRIDX]) /* CPU status register */ | |
191 | #define FCR0IDX (71) | |
192 | #define FCR0 (registers[FCR0IDX]) /* really a 32bit register */ | |
193 | #define FCR31IDX (70) | |
194 | #define FCR31 (registers[FCR31IDX]) /* really a 32bit register */ | |
195 | #define FCSR (FCR31) | |
196 | #define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */ | |
197 | ||
198 | /* The following are pseudonyms for standard registers */ | |
199 | #define ZERO (registers[0]) | |
200 | #define V0 (registers[2]) | |
201 | #define A0 (registers[4]) | |
202 | #define A1 (registers[5]) | |
203 | #define A2 (registers[6]) | |
204 | #define A3 (registers[7]) | |
205 | #define SP (registers[29]) | |
206 | #define RA (registers[31]) | |
207 | ||
208 | ut_reg EPC = 0; /* Exception PC */ | |
209 | ||
210 | #if defined(HASFPU) | |
211 | /* Keep the current format state for each register: */ | |
212 | FP_formats fpr_state[32]; | |
213 | #endif /* HASFPU */ | |
214 | ||
215 | /* VR4300 CP0 configuration register: */ | |
216 | unsigned int CONFIG = 0; | |
217 | ||
218 | /* The following are internal simulator state variables: */ | |
219 | ut_reg IPC = 0; /* internal Instruction PC */ | |
220 | ut_reg DSPC = 0; /* delay-slot PC */ | |
221 | ||
222 | ||
223 | /* TODO : these should be the bitmasks for these bits within the | |
224 | status register. At the moment the following are VR4300 | |
225 | bit-positions: */ | |
226 | #define status_KSU_mask (0x3) /* mask for KSU bits */ | |
227 | #define status_KSU_shift (3) /* shift for field */ | |
228 | #define ksu_kernel (0x0) | |
229 | #define ksu_supervisor (0x1) | |
230 | #define ksu_user (0x2) | |
231 | #define ksu_unknown (0x3) | |
232 | ||
233 | #define status_RE (1 << 25) /* Reverse Endian in user mode */ | |
234 | #define status_FR (1 << 26) /* enables MIPS III additional FP registers */ | |
235 | #define status_SR (1 << 20) /* soft reset or NMI */ | |
236 | #define status_BEV (1 << 22) /* Location of general exception vectors */ | |
237 | #define status_TS (1 << 21) /* TLB shutdown has occurred */ | |
238 | #define status_ERL (1 << 2) /* Error level */ | |
239 | #define status_RP (1 << 27) /* Reduced Power mode */ | |
240 | ||
241 | #define config_EP_mask (0xF) | |
242 | #define config_EP_shift (27) | |
243 | #define config_EP_D (0x0) | |
244 | #define config_EP_DxxDxx (0x6) | |
245 | ||
246 | #define config_BE (1 << 15) | |
247 | ||
248 | #define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */ | |
249 | ||
250 | #if defined(HASFPU) | |
251 | /* Macro to update FPSR condition-code field. This is complicated by | |
252 | the fact that there is a hole in the index range of the bits within | |
253 | the FCSR register. Also, the number of bits visible depends on the | |
254 | MIPS ISA version being supported. */ | |
255 | #define SETFCC(cc,v) {\ | |
256 | int bit = ((cc == 0) ? 23 : (24 + (cc)));\ | |
257 | FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\ | |
258 | } | |
259 | #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0) | |
260 | ||
261 | /* This should be the COC1 value at the start of the preceding | |
262 | instruction: */ | |
263 | #define PREVCOC1() ((state & simPCOC1) ? 1 : 0) | |
264 | #endif /* HASFPU */ | |
265 | ||
266 | /* Standard FCRS bits: */ | |
267 | #define IR (0) /* Inexact Result */ | |
268 | #define UF (1) /* UnderFlow */ | |
269 | #define OF (2) /* OverFlow */ | |
270 | #define DZ (3) /* Division by Zero */ | |
271 | #define IO (4) /* Invalid Operation */ | |
272 | #define UO (5) /* Unimplemented Operation */ | |
273 | ||
274 | /* Get masks for individual flags: */ | |
275 | #if 1 /* SAFE version */ | |
276 | #define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0) | |
277 | #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0) | |
278 | #define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0) | |
279 | #else | |
280 | #define FP_FLAGS(b) (1 << ((b) + 2)) | |
281 | #define FP_ENABLE(b) (1 << ((b) + 7)) | |
282 | #define FP_CAUSE(b) (1 << ((b) + 12)) | |
283 | #endif | |
284 | ||
285 | #define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */ | |
286 | ||
287 | #define FP_MASK_RM (0x3) | |
288 | #define FP_SH_RM (0) | |
289 | #define FP_RM_NEAREST (0) /* Round to nearest (Round) */ | |
290 | #define FP_RM_TOZERO (1) /* Round to zero (Trunc) */ | |
291 | #define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */ | |
292 | #define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */ | |
293 | #define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM) | |
294 | ||
295 | /* Slots for delayed register updates. For the moment we just have a | |
296 | fixed number of slots (rather than a more generic, dynamic | |
297 | system). This keeps the simulator fast. However, we only allow for | |
298 | the register update to be delayed for a single instruction | |
299 | cycle. */ | |
300 | #define PSLOTS (5) /* Maximum number of instruction cycles */ | |
301 | int pending_in; | |
302 | int pending_out; | |
303 | int pending_total; | |
304 | int pending_slot_count[PSLOTS]; | |
305 | int pending_slot_reg[PSLOTS]; | |
306 | ut_reg pending_slot_value[PSLOTS]; | |
307 | ||
308 | /* The following are not used for MIPS IV onwards: */ | |
309 | #define PENDING_FILL(r,v) {\ | |
310 | printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);\ | |
311 | if (pending_slot_reg[pending_in] != (LAST_EMBED_REGNUM + 1))\ | |
312 | callback->printf_filtered(callback,"SIM Warning: Attempt to over-write pending value\n");\ | |
313 | pending_slot_count[pending_in] = 2;\ | |
314 | pending_slot_reg[pending_in] = (r);\ | |
e871dd18 JSC |
315 | pending_slot_value[pending_in] = (uword64)(v);\ |
316 | printf("DBG: FILL reg %d value = 0x%08X%08X\n",(r),WORD64HI(v),WORD64LO(v));\ | |
8bae0a0c JSC |
317 | pending_total++;\ |
318 | pending_in++;\ | |
319 | if (pending_in == PSLOTS)\ | |
320 | pending_in = 0;\ | |
321 | printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);\ | |
322 | } | |
323 | ||
324 | int LLBIT = 0; | |
325 | /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic | |
326 | read-write instructions. It is set when a linked load occurs. It is | |
327 | tested and cleared by the conditional store. It is cleared (during | |
328 | other CPU operations) when a store to the location would no longer | |
329 | be atomic. In particular, it is cleared by exception return | |
330 | instructions. */ | |
331 | ||
332 | int HIACCESS = 0; | |
333 | int LOACCESS = 0; | |
334 | /* The HIACCESS and LOACCESS counts are used to ensure that | |
335 | corruptions caused by using the HI or LO register to close to a | |
336 | following operation are spotted. */ | |
337 | ||
338 | /* If either of the preceding two instructions have accessed the HI or | |
339 | LO registers, then the values they see should be | |
340 | undefined. However, to keep the simulator world simple, we just let | |
341 | them use the value read and raise a warning to notify the user: */ | |
342 | #define CHECKHILO(s) {\ | |
343 | if ((HIACCESS != 0) || (LOACCESS != 0))\ | |
344 | callback->printf_filtered(callback,"SIM Warning: %s over-writing HI and LO registers values\n",(s));\ | |
345 | /* Set the access counts, since we are about\ | |
346 | to update the HI and LO registers: */\ | |
347 | HIACCESS = LOACCESS = 3; /* 3rd instruction will be safe */\ | |
348 | } | |
349 | ||
350 | /* NOTE: We keep the following status flags as bit values (1 for true, | |
351 | 0 for false). This allows them to be used in binary boolean | |
352 | operations without worrying about what exactly the non-zero true | |
353 | value is. */ | |
354 | ||
355 | /* UserMode */ | |
356 | #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0) | |
357 | ||
358 | /* BigEndianMem */ | |
359 | /* Hardware configuration. Affects endianness of LoadMemory and | |
360 | StoreMemory and the endianness of Kernel and Supervisor mode | |
361 | execution. The value is 0 for little-endian; 1 for big-endian. */ | |
362 | #define BigEndianMem ((CONFIG & config_BE) ? 1 : 0) | |
363 | /* NOTE: Problems will occur if the simulator memory model does not | |
364 | match the host program expectation. i.e. if the host is writing | |
365 | big-endian values to a little-endian memory model. */ | |
366 | ||
367 | /* ReverseEndian */ | |
368 | /* This mode is selected if in User mode with the RE bit being set in | |
369 | SR (Status Register). It reverses the endianness of load and store | |
370 | instructions. */ | |
371 | #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0) | |
372 | ||
373 | /* BigEndianCPU */ | |
374 | /* The endianness for load and store instructions (0=little;1=big). In | |
375 | User mode this endianness may be switched by setting the state_RE | |
376 | bit in the SR register. Thus, BigEndianCPU may be computed as | |
377 | (BigEndienMem EOR ReverseEndian). */ | |
378 | #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */ | |
379 | ||
380 | #if !defined(FASTSIM) || defined(PROFILE) | |
381 | /* At the moment these values will be the same, since we do not have | |
382 | access to the pipeline cycle count information from the simulator | |
383 | engine. */ | |
384 | unsigned int instruction_fetches = 0; | |
385 | unsigned int pipeline_ticks = 0; | |
386 | #endif | |
387 | ||
388 | /* Flags in the "state" variable: */ | |
389 | #define simSTOP (1 << 0) /* 0 = execute; 1 = stop simulation */ | |
390 | #define simSTEP (1 << 1) /* 0 = run; 1 = single-step */ | |
391 | #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */ | |
392 | #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */ | |
393 | #define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */ | |
394 | #define simPROFILE (1 << 9) /* 0 = do nothing; 1 = gather profiling samples */ | |
395 | #define simHOSTBE (1 << 10) /* 0 = little-endian; 1 = big-endian (host endianness) */ | |
396 | /* Whilst simSTOP is not set, the simulator control loop should just | |
397 | keep simulating instructions. The simSTEP flag is used to force | |
398 | single-step execution. */ | |
399 | #define simBE (1 << 16) /* 0 = little-endian; 1 = big-endian (target endianness) */ | |
400 | #define simPCOC0 (1 << 17) /* COC[1] from current */ | |
401 | #define simPCOC1 (1 << 18) /* COC[1] from previous */ | |
402 | #define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */ | |
403 | #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */ | |
404 | #define simEXCEPTION (1 << 26) /* 0 = no exception; 1 = exception has occurred */ | |
405 | #define simEXIT (1 << 27) /* 0 = do nothing; 1 = run-time exit() processing */ | |
406 | ||
407 | unsigned int state = (0 | simBE); /* big-endian simulator by default */ | |
408 | unsigned int rcexit = 0; /* _exit() reason code holder */ | |
409 | ||
410 | #define DELAYSLOT() {\ | |
411 | if (state & simDELAYSLOT) callback->printf_filtered(callback,"SIM Warning: Delay slot already activated (branch in delay slot?)\n");\ | |
412 | state |= simDELAYSLOT;\ | |
413 | } | |
414 | ||
415 | #define NULLIFY() {\ | |
416 | state &= ~simDELAYSLOT;\ | |
417 | state |= simSKIPNEXT;\ | |
418 | } | |
419 | ||
420 | /* Very simple memory model to start with: */ | |
421 | unsigned char *membank = NULL; | |
422 | ut_reg membank_base = 0xA0000000; | |
423 | unsigned membank_size = (1 << 20); /* (16 << 20); */ /* power-of-2 */ | |
424 | ||
425 | /* Simple run-time monitor support */ | |
426 | unsigned char *monitor = NULL; | |
427 | ut_reg monitor_base = 0xBFC00000; | |
e871dd18 | 428 | unsigned monitor_size = (1 << 11); /* power-of-2 */ |
8bae0a0c JSC |
429 | |
430 | #if defined(TRACE) | |
431 | char *tracefile = "trace.din"; /* default filename for trace log */ | |
432 | FILE *tracefh = NULL; | |
433 | #endif /* TRACE */ | |
434 | ||
435 | #if defined(PROFILE) | |
436 | unsigned profile_frequency = 256; | |
437 | unsigned profile_nsamples = (128 << 10); | |
438 | unsigned short *profile_hist = NULL; | |
439 | ut_reg profile_minpc; | |
440 | ut_reg profile_maxpc; | |
441 | int profile_shift = 0; /* address shift amount */ | |
442 | #endif /* PROFILE */ | |
443 | ||
444 | /*---------------------------------------------------------------------------*/ | |
445 | /*-- GDB simulator interface ------------------------------------------------*/ | |
446 | /*---------------------------------------------------------------------------*/ | |
447 | ||
448 | static void dotrace PARAMS((FILE *tracefh,int type,unsigned int address,int width,char *comment,...)); | |
449 | extern void sim_error PARAMS((char *fmt,...)); | |
450 | static void ColdReset PARAMS((void)); | |
e871dd18 JSC |
451 | static int AddressTranslation PARAMS((uword64 vAddr,int IorD,int LorS,uword64 *pAddr,int *CCA,int host,int raw)); |
452 | static void StoreMemory PARAMS((int CCA,int AccessLength,uword64 MemElem,uword64 pAddr,uword64 vAddr,int raw)); | |
453 | static uword64 LoadMemory PARAMS((int CCA,int AccessLength,uword64 pAddr,uword64 vAddr,int IorD,int raw)); | |
8bae0a0c JSC |
454 | static void SignalException PARAMS((int exception,...)); |
455 | static void simulate PARAMS((void)); | |
456 | static long getnum(char *value); | |
457 | extern void sim_size(unsigned int newsize); | |
458 | extern void sim_set_profile(int frequency); | |
459 | static unsigned int power2(unsigned int value); | |
460 | ||
461 | void | |
462 | sim_open (args) | |
463 | char *args; | |
464 | { | |
465 | if (callback == NULL) { | |
466 | fprintf(stderr,"SIM Error: sim_open() called without callbacks attached\n"); | |
467 | return; | |
468 | } | |
469 | ||
470 | /* The following ensures that the standard file handles for stdin, | |
471 | stdout and stderr are initialised: */ | |
472 | callback->init(callback); | |
473 | ||
474 | state = 0; | |
475 | CHECKSIM(); | |
476 | if (state & simEXCEPTION) { | |
477 | fprintf(stderr,"This simulator is not suitable for this host configuration\n"); | |
478 | exit(1); | |
479 | } | |
480 | ||
481 | { | |
482 | int data = 0x12; | |
483 | if (*((char *)&data) != 0x12) | |
484 | state |= simHOSTBE; /* big-endian host */ | |
485 | } | |
486 | ||
487 | #if defined(HASFPU) | |
488 | /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE | |
489 | and DOUBLE binary formats. This is a bit nasty, requiring that we | |
490 | trust the explicit manifests held in the source: */ | |
491 | { | |
492 | unsigned int s[2]; | |
493 | s[0] = 0x40805A5A; | |
494 | s[1] = 0x00000000; | |
495 | if (((float)4.01102924346923828125 != *(float *)s) || ((double)523.2939453125 != *(double *)s)) { | |
496 | fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n"); | |
d0757082 JSC |
497 | fprintf(stderr,"*(float *)s = %f (4.01102924346923828125)\n",*(float *)s); |
498 | fprintf(stderr,"*(double *)s = %f (523.2939453125)\n",*(double *)s); | |
8bae0a0c JSC |
499 | exit(1); |
500 | } | |
501 | } | |
502 | #endif /* HASFPU */ | |
503 | ||
504 | /* This is NASTY, in that we are assuming the size of specific | |
505 | registers: */ | |
506 | { | |
507 | int rn; | |
508 | for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) { | |
509 | if (rn < 32) | |
510 | register_widths[rn] = GPRLEN; | |
511 | else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32))) | |
512 | register_widths[rn] = GPRLEN; | |
513 | else if ((rn >= 33) && (rn <= 37)) | |
514 | register_widths[rn] = GPRLEN; | |
515 | else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89))) | |
516 | register_widths[rn] = 32; | |
517 | else | |
518 | register_widths[rn] = 0; | |
519 | } | |
520 | } | |
521 | ||
522 | /* It would be good if we could select particular named MIPS | |
523 | architecture simulators. However, having a pre-built, fixed | |
524 | engine would mean including multiple engines. If the simulator is | |
525 | changed to a run-time conditional version, then the ability to | |
526 | select a particular architecture would be straightforward. */ | |
527 | if (args != NULL) { | |
528 | int c; | |
529 | char *cline; | |
530 | char **argv; | |
531 | int argc; | |
532 | static struct option cmdline[] = { | |
533 | {"help", 0,0,'h'}, | |
534 | {"name", 1,0,'n'}, | |
535 | {"profile", 0,0,'p'}, | |
536 | {"size", 1,0,'s'}, | |
537 | {"trace", 0,0,'t'}, | |
538 | {"tracefile",1,0,'z'}, | |
539 | {"frequency",1,0,'y'}, | |
540 | {"samples", 1,0,'x'}, | |
541 | {0, 0,0,0} | |
542 | }; | |
543 | ||
544 | /* Unfortunately, getopt_long() is designed to be used with | |
545 | vectors, where the first option is normally program name (and | |
546 | ignored). We cheat by creating a dummy first argument, so that | |
547 | we can use the standard argument processing. */ | |
548 | #define DUMMYARG "simulator " | |
549 | cline = (char *)malloc(strlen(args) + strlen(DUMMYARG) + 1); | |
550 | if (cline == NULL) { | |
551 | fprintf(stderr,"Failed to allocate memory for command line buffer\n"); | |
552 | exit(1); | |
553 | } | |
554 | sprintf(cline,"%s%s",DUMMYARG,args); | |
555 | argv = buildargv(cline); | |
556 | for (argc = 0; argv[argc]; argc++); | |
557 | ||
558 | /* Unfortunately, getopt_long() assumes that it is ignoring the | |
559 | first argument (normally the program name). This means it | |
560 | ignores the first option on our "args" line. */ | |
561 | optind = 0; /* Force reset of argument processing */ | |
562 | while (1) { | |
563 | int option_index = 0; | |
564 | ||
565 | c = getopt_long(argc,argv,"hn:s:tp",cmdline,&option_index); | |
566 | if (c == -1) | |
567 | break; | |
568 | ||
569 | switch (c) { | |
570 | case 'h': | |
571 | callback->printf_filtered(callback,"Usage:\n\t\ | |
572 | target sim [-h] [--name=<model>] [--size=<amount>]"); | |
573 | #if defined(TRACE) | |
574 | callback->printf_filtered(callback," [-t [--tracefile=<name>]]"); | |
575 | #endif /* TRACE */ | |
576 | #if defined(PROFILE) | |
577 | callback->printf_filtered(callback," [-p [--frequency=<count>] [--samples=<count>]]"); | |
578 | #endif /* PROFILE */ | |
579 | callback->printf_filtered(callback,"\n"); | |
580 | break; | |
581 | ||
582 | case 'n': | |
583 | callback->printf_filtered(callback,"Explicit model selection not yet available (Ignoring \"%s\")\n",optarg); | |
584 | break; | |
585 | ||
586 | case 's': | |
587 | membank_size = (unsigned)getnum(optarg); | |
588 | break; | |
589 | ||
590 | case 't': | |
591 | #if defined(TRACE) | |
592 | /* Eventually the simTRACE flag could be treated as a toggle, to | |
593 | allow external control of the program points being traced | |
594 | (i.e. only from main onwards, excluding the run-time setup, | |
595 | etc.). */ | |
596 | state |= simTRACE; | |
597 | #else /* !TRACE */ | |
598 | fprintf(stderr,"\ | |
599 | Simulator constructed without tracing support (for performance).\n\ | |
600 | Re-compile simulator with \"-DTRACE\" to enable this option.\n"); | |
601 | #endif /* !TRACE */ | |
602 | break; | |
603 | ||
604 | case 'z': | |
605 | #if defined(TRACE) | |
606 | if (optarg != NULL) { | |
607 | char *tmp; | |
608 | tmp = (char *)malloc(strlen(optarg) + 1); | |
609 | if (tmp == NULL) | |
610 | callback->printf_filtered(callback,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg); | |
611 | else { | |
612 | strcpy(tmp,optarg); | |
613 | tracefile = tmp; | |
614 | callback->printf_filtered(callback,"Placing trace information into file \"%s\"\n",tracefile); | |
615 | } | |
616 | } | |
617 | #endif /* TRACE */ | |
618 | break; | |
619 | ||
620 | case 'p': | |
621 | #if defined(PROFILE) | |
622 | state |= simPROFILE; | |
623 | #else /* !PROFILE */ | |
624 | fprintf(stderr,"\ | |
625 | Simulator constructed without profiling support (for performance).\n\ | |
626 | Re-compile simulator with \"-DPROFILE\" to enable this option.\n"); | |
627 | #endif /* !PROFILE */ | |
628 | break; | |
629 | ||
630 | case 'x': | |
631 | #if defined(PROFILE) | |
632 | profile_nsamples = (unsigned)getnum(optarg); | |
633 | #endif /* PROFILE */ | |
634 | break; | |
635 | ||
636 | case 'y': | |
637 | #if defined(PROFILE) | |
638 | sim_set_profile((int)getnum(optarg)); | |
639 | #endif /* PROFILE */ | |
640 | break; | |
641 | ||
642 | default: | |
643 | callback->printf_filtered(callback,"Warning: Simulator getopt returned unrecognised code 0x%08X\n",c); | |
644 | case '?': | |
645 | break; | |
646 | } | |
647 | } | |
648 | ||
649 | if (optind < argc) { | |
650 | callback->printf_filtered(callback,"Warning: Ignoring spurious non-option arguments "); | |
651 | while (optind < argc) | |
652 | callback->printf_filtered(callback,"\"%s\" ",argv[optind++]); | |
653 | callback->printf_filtered(callback,"\n"); | |
654 | } | |
655 | ||
656 | freeargv(argv); | |
657 | } | |
658 | ||
659 | /* If the host has "mmap" available we could use it to provide a | |
660 | very large virtual address space for the simulator, since memory | |
661 | would only be allocated within the "mmap" space as it is | |
662 | accessed. This can also be linked to the architecture specific | |
663 | support, required to simulate the MMU. */ | |
664 | sim_size(membank_size); | |
665 | /* NOTE: The above will also have enabled any profiling state */ | |
666 | ||
667 | ColdReset(); | |
668 | /* If we were providing a more complete I/O, co-processor or memory | |
669 | simulation, we should perform any "device" initialisation at this | |
670 | point. This can include pre-loading memory areas with particular | |
671 | patterns (e.g. simulating ROM monitors). */ | |
672 | ||
673 | /* We can start writing to the memory, now that the processor has | |
674 | been reset: */ | |
675 | monitor = (unsigned char *)calloc(1,monitor_size); | |
676 | if (!monitor) { | |
677 | fprintf(stderr,"Not enough VM for monitor simulation (%d bytes)\n",monitor_size); | |
678 | } else { | |
679 | int loop; | |
e871dd18 | 680 | /* TODO: Provide support for PMON monitor */ |
8bae0a0c JSC |
681 | /* Entry into the IDT monitor is via fixed address vectors, and |
682 | not using machine instructions. To avoid clashing with use of | |
683 | the MIPS TRAP system, we place our own (simulator specific) | |
684 | "undefined" instructions into the relevant vector slots. */ | |
685 | for (loop = 0; (loop < monitor_size); loop += 4) { | |
e871dd18 JSC |
686 | uword64 vaddr = (monitor_base + loop); |
687 | uword64 paddr; | |
8bae0a0c JSC |
688 | int cca; |
689 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) | |
e871dd18 | 690 | StoreMemory(cca,AccessLength_WORD,(RSVD_INSTRUCTION | ((loop >> 2) & RSVD_INSTRUCTION_AMASK)),paddr,vaddr,isRAW); |
8bae0a0c JSC |
691 | } |
692 | } | |
693 | ||
694 | #if defined(TRACE) | |
695 | if (state & simTRACE) { | |
696 | tracefh = fopen(tracefile,"wb+"); | |
697 | if (tracefh == NULL) { | |
698 | callback->printf_filtered(callback,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile); | |
699 | tracefh = stderr; | |
700 | } | |
701 | } | |
702 | #endif /* TRACE */ | |
703 | ||
704 | return; | |
705 | } | |
706 | ||
707 | /* For the profile writing, we write the data in the host | |
708 | endianness. This unfortunately means we are assuming that the | |
709 | profile file we create is processed on the same host executing the | |
710 | simulator. The gmon.out file format should either have an explicit | |
711 | endianness, or a method of encoding the endianness in the file | |
712 | header. */ | |
713 | static int | |
714 | writeout32(fh,val) | |
715 | FILE *fh; | |
716 | unsigned int val; | |
717 | { | |
718 | char buff[4]; | |
719 | int res = 1; | |
720 | ||
721 | if (state & simHOSTBE) { | |
722 | buff[3] = ((val >> 0) & 0xFF); | |
723 | buff[2] = ((val >> 8) & 0xFF); | |
724 | buff[1] = ((val >> 16) & 0xFF); | |
725 | buff[0] = ((val >> 24) & 0xFF); | |
726 | } else { | |
727 | buff[0] = ((val >> 0) & 0xFF); | |
728 | buff[1] = ((val >> 8) & 0xFF); | |
729 | buff[2] = ((val >> 16) & 0xFF); | |
730 | buff[3] = ((val >> 24) & 0xFF); | |
731 | } | |
732 | if (fwrite(buff,4,1,fh) != 1) { | |
733 | callback->printf_filtered(callback,"Failed to write 4bytes to the profile file\n"); | |
734 | res = 0; | |
735 | } | |
736 | return(res); | |
737 | } | |
738 | ||
739 | static int | |
740 | writeout16(fh,val) | |
741 | FILE *fh; | |
742 | unsigned short val; | |
743 | { | |
744 | char buff[2]; | |
745 | int res = 1; | |
746 | if (state & simHOSTBE) { | |
747 | buff[1] = ((val >> 0) & 0xFF); | |
748 | buff[0] = ((val >> 8) & 0xFF); | |
749 | } else { | |
750 | buff[0] = ((val >> 0) & 0xFF); | |
751 | buff[1] = ((val >> 8) & 0xFF); | |
752 | } | |
753 | if (fwrite(buff,2,1,fh) != 1) { | |
754 | callback->printf_filtered(callback,"Failed to write 2bytes to the profile file\n"); | |
755 | res = 0; | |
756 | } | |
757 | return(res); | |
758 | } | |
759 | ||
760 | void | |
761 | sim_close (quitting) | |
762 | int quitting; | |
763 | { | |
764 | #ifdef DEBUG | |
765 | printf("DBG: sim_close: entered (quitting = %d)\n",quitting); | |
766 | #endif | |
767 | ||
768 | /* Cannot assume sim_kill() has been called */ | |
769 | /* "quitting" is non-zero if we cannot hang on errors */ | |
770 | ||
771 | /* Ensure that any resources allocated through the callback | |
772 | mechanism are released: */ | |
773 | callback->shutdown(callback); | |
774 | ||
775 | #if defined(PROFILE) | |
776 | if ((state & simPROFILE) && (profile_hist != NULL)) { | |
777 | unsigned short *p = profile_hist; | |
778 | FILE *pf = fopen("gmon.out","wb"); | |
779 | int loop; | |
780 | ||
781 | if (pf == NULL) | |
782 | callback->printf_filtered(callback,"Failed to open \"gmon.out\" profile file\n"); | |
783 | else { | |
784 | int ok; | |
785 | #ifdef DEBUG | |
786 | printf("DBG: minpc = 0x%08X\n",(unsigned int)profile_minpc); | |
787 | printf("DBG: maxpc = 0x%08X\n",(unsigned int)profile_maxpc); | |
788 | #endif /* DEBUG */ | |
789 | ok = writeout32(pf,(unsigned int)profile_minpc); | |
790 | if (ok) | |
791 | ok = writeout32(pf,(unsigned int)profile_maxpc); | |
792 | if (ok) | |
793 | ok = writeout32(pf,(profile_nsamples * 2) + 12); /* size of sample buffer (+ header) */ | |
794 | #ifdef DEBUG | |
795 | printf("DBG: nsamples = %d (size = 0x%08X)\n",profile_nsamples,((profile_nsamples * 2) + 12)); | |
796 | #endif /* DEBUG */ | |
797 | for (loop = 0; (ok && (loop < profile_nsamples)); loop++) { | |
798 | ok = writeout16(pf,profile_hist[loop]); | |
799 | if (!ok) | |
800 | break; | |
801 | } | |
802 | ||
803 | fclose(pf); | |
804 | } | |
805 | ||
806 | free(profile_hist); | |
807 | profile_hist = NULL; | |
808 | state &= ~simPROFILE; | |
809 | } | |
810 | #endif /* PROFILE */ | |
811 | ||
812 | #if defined(TRACE) | |
813 | if (tracefh != stderr) | |
814 | fclose(tracefh); | |
815 | state &= ~simTRACE; | |
816 | #endif /* TRACE */ | |
817 | ||
818 | if (membank) | |
d0757082 | 819 | free(membank); /* cfree not available on all hosts */ |
8bae0a0c JSC |
820 | membank = NULL; |
821 | ||
822 | return; | |
823 | } | |
824 | ||
825 | void | |
826 | sim_resume (step,signal) | |
827 | int step, signal; | |
828 | { | |
829 | #ifdef DEBUG | |
830 | printf("DBG: sim_resume entered: step = %d, signal = %d (membank = 0x%08X)\n",step,signal,membank); | |
831 | #endif /* DEBUG */ | |
832 | ||
833 | if (step) | |
834 | state |= simSTEP; /* execute only a single instruction */ | |
835 | else | |
836 | state &= ~(simSTOP | simSTEP); /* execute until event */ | |
837 | ||
838 | state |= (simHALTEX | simHALTIN); /* treat interrupt event as exception */ | |
839 | ||
840 | /* Start executing instructions from the current state (set | |
841 | explicitly by register updates, or by sim_create_inferior): */ | |
842 | ||
843 | simulate(); | |
844 | return; | |
845 | } | |
846 | ||
847 | int | |
848 | sim_write (addr,buffer,size) | |
849 | SIM_ADDR addr; | |
850 | unsigned char *buffer; | |
851 | int size; | |
852 | { | |
853 | int index = size; | |
e871dd18 | 854 | uword64 vaddr = (uword64)addr; |
8bae0a0c JSC |
855 | |
856 | /* Return the number of bytes written, or zero if error. */ | |
857 | #ifdef DEBUG | |
e871dd18 | 858 | callback->printf_filtered(callback,"sim_write(0x%08X%08X,buffer,%d);\n",WORD64HI(addr),WORD64LO(addr),size); |
8bae0a0c JSC |
859 | #endif |
860 | ||
861 | /* We provide raw read and write routines, since we do not want to | |
862 | count the GDB memory accesses in our statistics gathering. */ | |
863 | ||
864 | /* There is a lot of code duplication in the individual blocks | |
865 | below, but the variables are declared locally to a block to give | |
866 | the optimiser the best chance of improving the code. We have to | |
867 | perform slow byte reads from the host memory, to ensure that we | |
868 | get the data into the correct endianness for the (simulated) | |
869 | target memory world. */ | |
870 | ||
871 | /* Mask count to get odd byte, odd halfword, and odd word out of the | |
872 | way. We can then perform doubleword transfers to and from the | |
873 | simulator memory for optimum performance. */ | |
874 | if (index && (index & 1)) { | |
e871dd18 | 875 | uword64 paddr; |
8bae0a0c JSC |
876 | int cca; |
877 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) { | |
e871dd18 | 878 | uword64 value = ((uword64)(*buffer++)); |
8bae0a0c JSC |
879 | StoreMemory(cca,AccessLength_BYTE,value,paddr,vaddr,isRAW); |
880 | } | |
881 | vaddr++; | |
882 | index &= ~1; /* logical operations usually quicker than arithmetic on RISC systems */ | |
883 | } | |
884 | if (index && (index & 2)) { | |
e871dd18 | 885 | uword64 paddr; |
8bae0a0c JSC |
886 | int cca; |
887 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) { | |
e871dd18 | 888 | uword64 value; |
8bae0a0c JSC |
889 | /* We need to perform the following magic to ensure that that |
890 | bytes are written into same byte positions in the target memory | |
891 | world, regardless of the endianness of the host. */ | |
892 | if (BigEndianMem) { | |
e871dd18 JSC |
893 | value = ((uword64)(*buffer++) << 8); |
894 | value |= ((uword64)(*buffer++) << 0); | |
8bae0a0c | 895 | } else { |
e871dd18 JSC |
896 | value = ((uword64)(*buffer++) << 0); |
897 | value |= ((uword64)(*buffer++) << 8); | |
8bae0a0c JSC |
898 | } |
899 | StoreMemory(cca,AccessLength_HALFWORD,value,paddr,vaddr,isRAW); | |
900 | } | |
901 | vaddr += 2; | |
902 | index &= ~2; | |
903 | } | |
904 | if (index && (index & 4)) { | |
e871dd18 | 905 | uword64 paddr; |
8bae0a0c JSC |
906 | int cca; |
907 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) { | |
e871dd18 | 908 | uword64 value; |
8bae0a0c | 909 | if (BigEndianMem) { |
e871dd18 JSC |
910 | value = ((uword64)(*buffer++) << 24); |
911 | value |= ((uword64)(*buffer++) << 16); | |
912 | value |= ((uword64)(*buffer++) << 8); | |
913 | value |= ((uword64)(*buffer++) << 0); | |
8bae0a0c | 914 | } else { |
e871dd18 JSC |
915 | value = ((uword64)(*buffer++) << 0); |
916 | value |= ((uword64)(*buffer++) << 8); | |
917 | value |= ((uword64)(*buffer++) << 16); | |
918 | value |= ((uword64)(*buffer++) << 24); | |
8bae0a0c JSC |
919 | } |
920 | StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW); | |
921 | } | |
922 | vaddr += 4; | |
923 | index &= ~4; | |
924 | } | |
925 | for (;index; index -= 8) { | |
e871dd18 | 926 | uword64 paddr; |
8bae0a0c JSC |
927 | int cca; |
928 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) { | |
e871dd18 | 929 | uword64 value; |
8bae0a0c | 930 | if (BigEndianMem) { |
e871dd18 JSC |
931 | value = ((uword64)(*buffer++) << 56); |
932 | value |= ((uword64)(*buffer++) << 48); | |
933 | value |= ((uword64)(*buffer++) << 40); | |
934 | value |= ((uword64)(*buffer++) << 32); | |
935 | value |= ((uword64)(*buffer++) << 24); | |
936 | value |= ((uword64)(*buffer++) << 16); | |
937 | value |= ((uword64)(*buffer++) << 8); | |
938 | value |= ((uword64)(*buffer++) << 0); | |
8bae0a0c | 939 | } else { |
e871dd18 JSC |
940 | value = ((uword64)(*buffer++) << 0); |
941 | value |= ((uword64)(*buffer++) << 8); | |
942 | value |= ((uword64)(*buffer++) << 16); | |
943 | value |= ((uword64)(*buffer++) << 24); | |
944 | value |= ((uword64)(*buffer++) << 32); | |
945 | value |= ((uword64)(*buffer++) << 40); | |
946 | value |= ((uword64)(*buffer++) << 48); | |
947 | value |= ((uword64)(*buffer++) << 56); | |
8bae0a0c JSC |
948 | } |
949 | StoreMemory(cca,AccessLength_DOUBLEWORD,value,paddr,vaddr,isRAW); | |
950 | } | |
951 | vaddr += 8; | |
952 | } | |
953 | ||
954 | return(size); | |
955 | } | |
956 | ||
957 | int | |
958 | sim_read (addr,buffer,size) | |
959 | SIM_ADDR addr; | |
960 | unsigned char *buffer; | |
961 | int size; | |
962 | { | |
963 | int index; | |
964 | ||
965 | /* Return the number of bytes read, or zero if error. */ | |
966 | #ifdef DEBUG | |
e871dd18 | 967 | callback->printf_filtered(callback,"sim_read(0x%08X%08X,buffer,%d);\n",WORD64HI(addr),WORD64LO(addr),size); |
8bae0a0c JSC |
968 | #endif /* DEBUG */ |
969 | ||
970 | /* TODO: Perform same optimisation as the sim_write() code | |
971 | above. NOTE: This will require a bit more work since we will need | |
972 | to ensure that the source physical address is doubleword aligned | |
973 | before, and then deal with trailing bytes. */ | |
974 | for (index = 0; (index < size); index++) { | |
e871dd18 | 975 | uword64 vaddr,paddr,value; |
8bae0a0c | 976 | int cca; |
e871dd18 | 977 | vaddr = (uword64)addr + index; |
8bae0a0c JSC |
978 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&cca,isTARGET,isRAW)) { |
979 | value = LoadMemory(cca,AccessLength_BYTE,paddr,vaddr,isDATA,isRAW); | |
980 | buffer[index] = (unsigned char)(value&0xFF); | |
981 | } else | |
982 | break; | |
983 | } | |
984 | ||
985 | return(index); | |
986 | } | |
987 | ||
988 | void | |
989 | sim_store_register (rn,memory) | |
990 | int rn; | |
991 | unsigned char *memory; | |
992 | { | |
993 | #ifdef DEBUG | |
994 | callback->printf_filtered(callback,"sim_store_register(%d,*memory=0x%08X%08X);\n",rn,*((unsigned int *)memory),*((unsigned int *)(memory + 4))); | |
995 | #endif /* DEBUG */ | |
996 | ||
997 | /* Unfortunately this suffers from the same problem as the register | |
998 | numbering one. We need to know what the width of each logical | |
999 | register number is for the architecture being simulated. */ | |
1000 | if (register_widths[rn] == 0) | |
1001 | callback->printf_filtered(callback,"Warning: Invalid register width for %d (register store ignored)\n",rn); | |
1002 | else { | |
1003 | if (register_widths[rn] == 32) | |
1004 | registers[rn] = *((unsigned int *)memory); | |
1005 | else | |
e871dd18 | 1006 | registers[rn] = *((uword64 *)memory); |
8bae0a0c JSC |
1007 | } |
1008 | ||
1009 | return; | |
1010 | } | |
1011 | ||
1012 | void | |
1013 | sim_fetch_register (rn,memory) | |
1014 | int rn; | |
1015 | unsigned char *memory; | |
1016 | { | |
1017 | #ifdef DEBUG | |
e871dd18 | 1018 | callback->printf_filtered(callback,"sim_fetch_register(%d=0x%08X%08X,mem) : place simulator registers into memory\n",rn,WORD64HI(registers[rn]),WORD64LO(registers[rn])); |
8bae0a0c JSC |
1019 | #endif /* DEBUG */ |
1020 | ||
1021 | if (register_widths[rn] == 0) | |
1022 | callback->printf_filtered(callback,"Warning: Invalid register width for %d (register fetch ignored)\n",rn); | |
1023 | else { | |
1024 | if (register_widths[rn] == 32) | |
1025 | *((unsigned int *)memory) = (registers[rn] & 0xFFFFFFFF); | |
1026 | else /* 64bit register */ | |
e871dd18 | 1027 | *((uword64 *)memory) = registers[rn]; |
8bae0a0c JSC |
1028 | } |
1029 | return; | |
1030 | } | |
1031 | ||
1032 | void | |
1033 | sim_stop_reason (reason,sigrc) | |
1034 | enum sim_stop *reason; | |
1035 | int *sigrc; | |
1036 | { | |
1037 | /* We can have "*reason = {sim_exited, sim_stopped, sim_signalled}", so | |
1038 | sim_exited *sigrc = argument to exit() | |
1039 | sim_stopped *sigrc = exception number | |
1040 | sim_signalled *sigrc = signal number | |
1041 | */ | |
1042 | if (state & simEXCEPTION) { | |
1043 | /* If "sim_signalled" is used, GDB expects normal SIGNAL numbers, | |
1044 | and not the MIPS specific exception codes. */ | |
1045 | #if 1 | |
1046 | /* For some reason, sending GDB a sim_signalled reason cause it to | |
1047 | terminate out. */ | |
1048 | *reason = sim_stopped; | |
1049 | #else | |
1050 | *reason = sim_signalled; | |
1051 | #endif | |
1052 | switch ((CAUSE >> 2) & 0x1F) { | |
1053 | case Interrupt: | |
1054 | *sigrc = SIGINT; /* wrong type of interrupt, but it will do for the moment */ | |
1055 | break; | |
1056 | ||
1057 | case TLBModification: | |
1058 | case TLBLoad: | |
1059 | case TLBStore: | |
1060 | case AddressLoad: | |
1061 | case AddressStore: | |
1062 | case InstructionFetch: | |
1063 | case DataReference: | |
1064 | *sigrc = SIGBUS; | |
1065 | break; | |
1066 | ||
1067 | case ReservedInstruction: | |
1068 | case CoProcessorUnusable: | |
1069 | *sigrc = SIGILL; | |
1070 | break; | |
1071 | ||
1072 | case IntegerOverflow: | |
1073 | case FPE: | |
1074 | *sigrc = SIGFPE; | |
1075 | break; | |
1076 | ||
1077 | case Trap: | |
1078 | case Watch: | |
1079 | case SystemCall: | |
1080 | case BreakPoint: | |
1081 | *sigrc = SIGTRAP; | |
1082 | break; | |
1083 | ||
1084 | default : /* Unknown internal exception */ | |
1085 | *sigrc = SIGQUIT; | |
1086 | break; | |
1087 | } | |
1088 | } else if (state & simEXIT) { | |
1089 | printf("DBG: simEXIT (%d)\n",rcexit); | |
1090 | *reason = sim_exited; | |
1091 | *sigrc = rcexit; | |
1092 | } else { /* assume single-stepping */ | |
1093 | *reason = sim_stopped; | |
1094 | *sigrc = SIGTRAP; | |
1095 | } | |
1096 | state &= ~(simEXCEPTION | simEXIT); | |
1097 | return; | |
1098 | } | |
1099 | ||
1100 | void | |
1101 | sim_info (verbose) | |
1102 | int verbose; | |
1103 | { | |
1104 | /* Accessed from the GDB "info files" command: */ | |
1105 | ||
1106 | callback->printf_filtered(callback,"MIPS %d-bit simulator\n",(PROCESSOR_64BIT ? 64 : 32)); | |
1107 | ||
1108 | callback->printf_filtered(callback,"%s endian memory model\n",(BigEndianMem ? "Big" : "Little")); | |
1109 | ||
e871dd18 | 1110 | callback->printf_filtered(callback,"0x%08X bytes of memory at 0x%08X%08X\n",(unsigned int)membank_size,WORD64HI(membank_base),WORD64LO(membank_base)); |
8bae0a0c JSC |
1111 | |
1112 | #if !defined(FASTSIM) | |
1113 | callback->printf_filtered(callback,"Instruction fetches = %d\n",instruction_fetches); | |
1114 | callback->printf_filtered(callback,"Pipeline ticks = %d\n",pipeline_ticks); | |
1115 | /* It would be a useful feature, if when performing multi-cycle | |
1116 | simulations (rather than single-stepping) we keep the start and | |
1117 | end times of the execution, so that we can give a performance | |
1118 | figure for the simulator. */ | |
1119 | #endif /* !FASTSIM */ | |
1120 | ||
1121 | /* print information pertaining to MIPS ISA and architecture being simulated */ | |
1122 | /* things that may be interesting */ | |
1123 | /* instructions executed - if available */ | |
1124 | /* cycles executed - if available */ | |
1125 | /* pipeline stalls - if available */ | |
1126 | /* virtual time taken */ | |
1127 | /* profiling size */ | |
1128 | /* profiling frequency */ | |
1129 | /* profile minpc */ | |
1130 | /* profile maxpc */ | |
1131 | ||
1132 | return; | |
1133 | } | |
1134 | ||
1135 | int | |
1136 | sim_load (prog,from_tty) | |
1137 | char *prog; | |
1138 | int from_tty; | |
1139 | { | |
1140 | /* Return non-zero if the caller should handle the load. Zero if | |
1141 | we have loaded the image. */ | |
1142 | return(-1); | |
1143 | } | |
1144 | ||
1145 | void | |
1146 | sim_create_inferior (start_address,argv,env) | |
1147 | SIM_ADDR start_address; | |
1148 | char **argv; | |
1149 | char **env; | |
1150 | { | |
1151 | #ifdef DEBUG | |
1152 | printf("DBG: sim_create_inferior entered: start_address = 0x%08X\n",start_address); | |
1153 | #endif /* DEBUG */ | |
1154 | ||
1155 | /* Prepare to execute the program to be simulated */ | |
1156 | /* argv and env are NULL terminated lists of pointers */ | |
1157 | ||
1158 | #if 1 | |
e871dd18 | 1159 | PC = (uword64)start_address; |
8bae0a0c JSC |
1160 | #else |
1161 | /* TODO: Sort this properly. SIM_ADDR may already be a 64bit value: */ | |
1162 | PC = SIGNEXTEND(start_address,32); | |
1163 | #endif | |
1164 | /* NOTE: GDB normally sets the PC explicitly. However, this call is | |
1165 | used by other clients of the simulator. */ | |
1166 | ||
1167 | if (argv || env) { | |
1168 | callback->printf_filtered(callback,"sim_create_inferior() : passed arguments ignored\n"); | |
1169 | #if 1 /* def DEBUG */ | |
1170 | { | |
1171 | char **cptr; | |
1172 | for (cptr = argv; (cptr && *cptr); cptr++) | |
1173 | printf("DBG: arg \"%s\"\n",*cptr); | |
1174 | } | |
1175 | #endif /* DEBUG */ | |
1176 | /* We should really place the argv slot values into the argument | |
1177 | registers, and onto the stack as required. However, this | |
1178 | assumes that we have a stack defined, which is not necessarily | |
1179 | true at the moment. */ | |
1180 | } | |
1181 | ||
1182 | return; | |
1183 | } | |
1184 | ||
1185 | void | |
1186 | sim_kill () | |
1187 | { | |
1188 | #if 1 | |
1189 | /* This routine should be for terminating any existing simulation | |
1190 | thread. Since we are single-threaded only at the moment, this is | |
1191 | not an issue. It should *NOT* be used to terminate the | |
1192 | simulator. */ | |
1193 | #else /* do *NOT* call sim_close */ | |
1194 | sim_close(1); /* Do not hang on errors */ | |
1195 | /* This would also be the point where any memory mapped areas used | |
1196 | by the simulator should be released. */ | |
1197 | #endif | |
1198 | return; | |
1199 | } | |
1200 | ||
1201 | int | |
1202 | sim_get_quit_code () | |
1203 | { | |
1204 | /* The standard MIPS PCS (Procedure Calling Standard) uses V0(r2) as | |
1205 | the function return value. However, it may be more correct for | |
1206 | this to return the argument to the exit() function (if | |
1207 | called). */ | |
1208 | return(V0); | |
1209 | } | |
1210 | ||
1211 | void | |
1212 | sim_set_callbacks (p) | |
1213 | host_callback *p; | |
1214 | { | |
1215 | callback = p; | |
1216 | return; | |
1217 | } | |
1218 | ||
1219 | typedef enum {e_terminate,e_help,e_setmemsize,e_reset} e_cmds; | |
1220 | ||
1221 | static struct t_sim_command { | |
1222 | e_cmds id; | |
1223 | const char *name; | |
1224 | const char *help; | |
1225 | } sim_commands[] = { | |
1226 | {e_help, "help", ": Show MIPS simulator private commands"}, | |
1227 | {e_setmemsize,"set-memory-size","<n> : Specify amount of memory simulated"}, | |
1228 | {e_reset, "reset-system", ": Reset the simulated processor"}, | |
1229 | {e_terminate, NULL} | |
1230 | }; | |
1231 | ||
1232 | void | |
1233 | sim_do_command (cmd) | |
1234 | char *cmd; | |
1235 | { | |
1236 | struct t_sim_command *cptr; | |
1237 | ||
1238 | if (!(cmd && *cmd != '\0')) | |
1239 | cmd = "help"; | |
1240 | ||
1241 | /* NOTE: Accessed from the GDB "sim" commmand: */ | |
1242 | for (cptr = sim_commands; cptr && cptr->name; cptr++) | |
1243 | if (strncmp(cmd,cptr->name,strlen(cptr->name)) == 0) { | |
1244 | cmd += strlen(cptr->name); | |
1245 | switch (cptr->id) { | |
1246 | case e_help: /* no arguments */ | |
1247 | { /* no arguments */ | |
1248 | struct t_sim_command *lptr; | |
1249 | callback->printf_filtered(callback,"List of MIPS simulator commands:\n"); | |
1250 | for (lptr = sim_commands; lptr->name; lptr++) | |
1251 | callback->printf_filtered(callback,"%s %s\n",lptr->name,lptr->help); | |
1252 | } | |
1253 | break; | |
1254 | ||
1255 | case e_setmemsize: /* memory size argument */ | |
1256 | { | |
1257 | unsigned int newsize = (unsigned int)getnum(cmd); | |
1258 | sim_size(newsize); | |
1259 | } | |
1260 | break; | |
1261 | ||
1262 | case e_reset: /* no arguments */ | |
1263 | ColdReset(); | |
1264 | /* NOTE: See the comments in sim_open() relating to device | |
1265 | initialisation. */ | |
1266 | break; | |
1267 | ||
1268 | default: | |
1269 | callback->printf_filtered(callback,"FATAL: Matched \"%s\", but failed to match command id %d.\n",cmd,cptr->id); | |
1270 | break; | |
1271 | } | |
1272 | break; | |
1273 | } | |
1274 | ||
1275 | if (!(cptr->name)) | |
1276 | callback->printf_filtered(callback,"Error: \"%s\" is not a valid MIPS simulator command.\n",cmd); | |
1277 | ||
1278 | return; | |
1279 | } | |
1280 | ||
1281 | /*---------------------------------------------------------------------------*/ | |
1282 | /* NOTE: The following routines do not seem to be used by GDB at the | |
1283 | moment. However, they may be useful to the standalone simulator | |
1284 | world. */ | |
1285 | ||
1286 | ||
1287 | /* The profiling format is described in the "gmon_out.h" header file */ | |
1288 | void | |
1289 | sim_set_profile (n) | |
1290 | int n; | |
1291 | { | |
1292 | #if defined(PROFILE) | |
1293 | profile_frequency = n; | |
1294 | state |= simPROFILE; | |
1295 | #endif /* PROFILE */ | |
1296 | return; | |
1297 | } | |
1298 | ||
1299 | void | |
1300 | sim_set_profile_size (n) | |
1301 | int n; | |
1302 | { | |
1303 | #if defined(PROFILE) | |
1304 | if (state & simPROFILE) { | |
1305 | int bsize; | |
1306 | ||
1307 | /* Since we KNOW that the memory banks are a power-of-2 in size: */ | |
1308 | profile_nsamples = power2(n); | |
1309 | profile_minpc = membank_base; | |
1310 | profile_maxpc = (membank_base + membank_size); | |
1311 | ||
1312 | /* Just in-case we are sampling every address: NOTE: The shift | |
1313 | right of 2 is because we only have word-aligned PC addresses. */ | |
1314 | if (profile_nsamples > (membank_size >> 2)) | |
1315 | profile_nsamples = (membank_size >> 2); | |
1316 | ||
1317 | /* Since we are dealing with power-of-2 values: */ | |
1318 | profile_shift = (((membank_size >> 2) / profile_nsamples) - 1); | |
1319 | ||
1320 | bsize = (profile_nsamples * sizeof(unsigned short)); | |
1321 | if (profile_hist == NULL) | |
1322 | profile_hist = (unsigned short *)calloc(64,(bsize / 64)); | |
1323 | else | |
1324 | profile_hist = (unsigned short *)realloc(profile_hist,bsize); | |
1325 | if (profile_hist == NULL) { | |
1326 | callback->printf_filtered(callback,"Failed to allocate VM for profiling buffer (0x%08X bytes)\n",bsize); | |
1327 | state &= ~simPROFILE; | |
1328 | } | |
1329 | } | |
1330 | #endif /* PROFILE */ | |
1331 | ||
1332 | return; | |
1333 | } | |
1334 | ||
1335 | void | |
1336 | sim_size(newsize) | |
1337 | unsigned int newsize; | |
1338 | { | |
1339 | char *new; | |
1340 | /* Used by "run", and internally, to set the simulated memory size */ | |
1341 | newsize = power2(newsize); | |
1342 | if (membank == NULL) | |
1343 | new = (char *)calloc(64,(membank_size / 64)); | |
1344 | else | |
1345 | new = (char *)realloc(membank,newsize); | |
1346 | if (new == NULL) { | |
1347 | if (membank == NULL) | |
1348 | callback->printf_filtered(callback,"Not enough VM for simulation memory of 0x%08X bytes\n",membank_size); | |
1349 | else | |
1350 | callback->printf_filtered(callback,"Failed to resize memory (still 0x%08X bytes)\n",membank_size); | |
1351 | } else { | |
1352 | membank_size = (unsigned)newsize; | |
1353 | membank = new; | |
1354 | callback->printf_filtered(callback,"Memory size now 0x%08X bytes\n",membank_size); | |
1355 | #if defined(PROFILE) | |
1356 | /* Ensure that we sample across the new memory range */ | |
1357 | sim_set_profile_size(profile_nsamples); | |
1358 | #endif /* PROFILE */ | |
1359 | } | |
1360 | ||
1361 | return; | |
1362 | } | |
1363 | ||
1364 | int | |
1365 | sim_trace() | |
1366 | { | |
1367 | /* This routine is called by the "run" program, when detailed | |
1368 | execution information is required. Rather than executing a single | |
1369 | instruction, and looping around externally... we just start | |
1370 | simulating, returning TRUE when the simulator stops (for whatever | |
1371 | reason). */ | |
1372 | ||
1373 | #if defined(TRACE) | |
1374 | /* Ensure tracing is enabled, if available */ | |
1375 | if (tracefh != NULL) | |
1376 | state |= simTRACE; | |
1377 | #endif /* TRACE */ | |
1378 | ||
1379 | state &= ~(simSTOP | simSTEP); /* execute until event */ | |
1380 | state |= (simHALTEX | simHALTIN); /* treat interrupt event as exception */ | |
1381 | /* Start executing instructions from the current state (set | |
1382 | explicitly by register updates, or by sim_create_inferior): */ | |
1383 | simulate(); | |
1384 | ||
1385 | return(1); | |
1386 | } | |
1387 | ||
1388 | /*---------------------------------------------------------------------------*/ | |
1389 | /*-- Private simulator support interface ------------------------------------*/ | |
1390 | /*---------------------------------------------------------------------------*/ | |
1391 | ||
e871dd18 | 1392 | /* Simple monitor interface (currently setup for the IDT monitor) */ |
8bae0a0c JSC |
1393 | static void |
1394 | sim_monitor(reason) | |
1395 | unsigned int reason; | |
1396 | { | |
1397 | /* The IDT monitor actually allows two instructions per vector | |
1398 | slot. However, the simulator currently causes a trap on each | |
1399 | individual instruction. We cheat, and lose the bottom bit. */ | |
1400 | reason >>= 1; | |
1401 | ||
1402 | /* The following callback functions are available, however the | |
1403 | monitor we are simulating does not make use of them: get_errno, | |
1404 | isatty, lseek, rename, system, time and unlink */ | |
1405 | switch (reason) { | |
1406 | case 6: /* int open(char *path,int flags) */ | |
1407 | { | |
1408 | const char *ptr; | |
e871dd18 | 1409 | uword64 paddr; |
8bae0a0c JSC |
1410 | int cca; |
1411 | if (AddressTranslation(A0,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) | |
1412 | V0 = callback->open(callback,(char *)((int)paddr),(int)A1); | |
1413 | else | |
1414 | callback->printf_filtered(callback,"WARNING: Attempt to pass pointer that does not reference simulated memory\n"); | |
1415 | } | |
1416 | break; | |
1417 | ||
1418 | case 7: /* int read(int file,char *ptr,int len) */ | |
1419 | { | |
1420 | const char *ptr; | |
e871dd18 | 1421 | uword64 paddr; |
8bae0a0c JSC |
1422 | int cca; |
1423 | if (AddressTranslation(A1,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) | |
1424 | V0 = callback->read(callback,(int)A0,(char *)((int)paddr),(int)A2); | |
1425 | else | |
1426 | callback->printf_filtered(callback,"WARNING: Attempt to pass pointer that does not reference simulated memory\n"); | |
1427 | } | |
1428 | break; | |
1429 | ||
1430 | case 8: /* int write(int file,char *ptr,int len) */ | |
1431 | { | |
1432 | const char *ptr; | |
e871dd18 | 1433 | uword64 paddr; |
8bae0a0c JSC |
1434 | int cca; |
1435 | if (AddressTranslation(A1,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) | |
1436 | V0 = callback->write(callback,(int)A0,(const char *)((int)paddr),(int)A2); | |
1437 | else | |
1438 | callback->printf_filtered(callback,"WARNING: Attempt to pass pointer that does not reference simulated memory\n"); | |
1439 | } | |
1440 | break; | |
1441 | ||
1442 | case 10: /* int close(int file) */ | |
1443 | V0 = callback->close(callback,(int)A0); | |
1444 | break; | |
1445 | ||
1446 | case 11: /* char inbyte(void) */ | |
1447 | { | |
1448 | char tmp; | |
1449 | if (callback->read_stdin(callback,&tmp,sizeof(char)) != sizeof(char)) { | |
1450 | callback->printf_filtered(callback,"WARNING: Invalid return from character read\n"); | |
1451 | V0 = -1; | |
1452 | } | |
1453 | else | |
1454 | V0 = tmp; | |
1455 | } | |
1456 | break; | |
1457 | ||
1458 | case 12: /* void outbyte(char chr) : write a byte to "stdout" */ | |
1459 | { | |
1460 | char tmp = (char)(A0 & 0xFF); | |
1461 | callback->write_stdout(callback,&tmp,sizeof(char)); | |
1462 | } | |
1463 | break; | |
1464 | ||
1465 | case 17: /* void _exit() */ | |
1466 | callback->printf_filtered(callback,"sim_monitor(17): _exit(int reason) to be coded\n"); | |
1467 | state |= (simSTOP | simEXIT); /* stop executing code */ | |
1468 | rcexit = (unsigned int)(A0 & 0xFFFFFFFF); | |
1469 | break; | |
1470 | ||
1471 | case 55: /* void get_mem_info(unsigned int *ptr) */ | |
1472 | /* in: A0 = pointer to three word memory location */ | |
1473 | /* out: [A0 + 0] = size */ | |
1474 | /* [A0 + 4] = instruction cache size */ | |
1475 | /* [A0 + 8] = data cache size */ | |
1476 | { | |
e871dd18 JSC |
1477 | uword64 vaddr = A0; |
1478 | uword64 paddr, value; | |
8bae0a0c JSC |
1479 | int cca; |
1480 | int failed = 0; | |
1481 | ||
1482 | /* NOTE: We use RAW memory writes here, but since we are not | |
1483 | gathering statistics for the monitor calls we are simulating, | |
1484 | it is not an issue. */ | |
1485 | ||
1486 | /* Memory size */ | |
1487 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL)) { | |
e871dd18 | 1488 | value = (uword64)membank_size; |
8bae0a0c JSC |
1489 | StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW); |
1490 | /* We re-do the address translations, in-case the block | |
1491 | overlaps a memory boundary: */ | |
1492 | value = 0; | |
1493 | vaddr += (AccessLength_WORD + 1); | |
1494 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL)) { | |
1495 | StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW); | |
1496 | vaddr += (AccessLength_WORD + 1); | |
1497 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL)) | |
1498 | StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW); | |
1499 | else | |
1500 | failed = -1; | |
1501 | } else | |
1502 | failed = -1; | |
1503 | } else | |
1504 | failed = -1; | |
1505 | ||
1506 | if (failed) | |
1507 | callback->printf_filtered(callback,"WARNING: Invalid pointer passed into monitor call\n"); | |
1508 | } | |
1509 | break; | |
1510 | ||
1511 | default: | |
e871dd18 JSC |
1512 | callback->printf_filtered(callback,"TODO: sim_monitor(%d) : PC = 0x%08X%08X\n",reason,WORD64HI(IPC),WORD64LO(IPC)); |
1513 | callback->printf_filtered(callback,"(Arguments : A0 = 0x%08X%08X : A1 = 0x%08X%08X : A2 = 0x%08X%08X : A3 = 0x%08X%08X)\n",WORD64HI(A0),WORD64LO(A0),WORD64HI(A1),WORD64LO(A1),WORD64HI(A2),WORD64LO(A2),WORD64HI(A3),WORD64LO(A3)); | |
8bae0a0c JSC |
1514 | break; |
1515 | } | |
1516 | return; | |
1517 | } | |
1518 | ||
1519 | void | |
1520 | sim_error(fmt) | |
1521 | char *fmt; | |
1522 | { | |
1523 | va_list ap; | |
1524 | va_start(ap,fmt); | |
1525 | callback->printf_filtered(callback,"SIM Error: "); | |
1526 | callback->printf_filtered(callback,fmt,ap); | |
1527 | va_end(ap); | |
1528 | SignalException(SimulatorFault,""); | |
1529 | return; | |
1530 | } | |
1531 | ||
1532 | static unsigned int | |
1533 | power2(value) | |
1534 | unsigned int value; | |
1535 | { | |
1536 | int loop,tmp; | |
1537 | ||
1538 | /* Round *UP* to the nearest power-of-2 if not already one */ | |
1539 | if (value != (value & ~(value - 1))) { | |
1540 | for (tmp = value, loop = 0; (tmp != 0); loop++) | |
1541 | tmp >>= 1; | |
1542 | value = (1 << loop); | |
1543 | } | |
1544 | ||
1545 | return(value); | |
1546 | } | |
1547 | ||
1548 | static long | |
1549 | getnum(value) | |
1550 | char *value; | |
1551 | { | |
1552 | long num; | |
1553 | char *end; | |
1554 | ||
1555 | num = strtol(value,&end,10); | |
1556 | if (end == value) | |
1557 | callback->printf_filtered(callback,"Warning: Invalid number \"%s\" ignored, using zero\n",value); | |
1558 | else { | |
1559 | if (*end && ((tolower(*end) == 'k') || (tolower(*end) == 'm'))) { | |
1560 | if (tolower(*end) == 'k') | |
1561 | num *= (1 << 10); | |
1562 | else | |
1563 | num *= (1 << 20); | |
1564 | end++; | |
1565 | } | |
1566 | if (*end) | |
1567 | callback->printf_filtered(callback,"Warning: Spurious characters \"%s\" at end of number ignored\n",end); | |
1568 | } | |
1569 | ||
1570 | return(num); | |
1571 | } | |
1572 | ||
1573 | /*-- trace support ----------------------------------------------------------*/ | |
1574 | ||
1575 | /* The TRACE support is provided (if required) in the memory accessing | |
1576 | routines. Since we are also providing the architecture specific | |
1577 | features, the architecture simulation code can also deal with | |
1578 | notifying the TRACE world of cache flushes, etc. Similarly we do | |
1579 | not need to provide profiling support in the simulator engine, | |
1580 | since we can sample in the instruction fetch control loop. By | |
1581 | defining the TRACE manifest, we add tracing as a run-time | |
1582 | option. */ | |
1583 | ||
1584 | #if defined(TRACE) | |
1585 | /* Tracing by default produces "din" format (as required by | |
1586 | dineroIII). Each line of such a trace file *MUST* have a din label | |
1587 | and address field. The rest of the line is ignored, so comments can | |
1588 | be included if desired. The first field is the label which must be | |
1589 | one of the following values: | |
1590 | ||
1591 | 0 read data | |
1592 | 1 write data | |
1593 | 2 instruction fetch | |
1594 | 3 escape record (treated as unknown access type) | |
1595 | 4 escape record (causes cache flush) | |
1596 | ||
1597 | The address field is a 32bit (lower-case) hexadecimal address | |
1598 | value. The address should *NOT* be preceded by "0x". | |
1599 | ||
1600 | The size of the memory transfer is not important when dealing with | |
1601 | cache lines (as long as no more than a cache line can be | |
1602 | transferred in a single operation :-), however more information | |
1603 | could be given following the dineroIII requirement to allow more | |
1604 | complete memory and cache simulators to provide better | |
1605 | results. i.e. the University of Pisa has a cache simulator that can | |
1606 | also take bus size and speed as (variable) inputs to calculate | |
1607 | complete system performance (a much more useful ability when trying | |
1608 | to construct an end product, rather than a processor). They | |
1609 | currently have an ARM version of their tool called ChARM. */ | |
1610 | ||
1611 | static | |
1612 | void dotrace(tracefh,type,address,width,comment) | |
1613 | FILE *tracefh; | |
1614 | int type; | |
1615 | unsigned int address; | |
1616 | int width; | |
1617 | char *comment; | |
1618 | { | |
1619 | if (state & simTRACE) { | |
1620 | va_list ap; | |
1621 | fprintf(tracefh,"%d %08x ; width %d ; ",type,address,width); | |
1622 | va_start(ap,comment); | |
1623 | fprintf(tracefh,comment,ap); | |
1624 | va_end(ap); | |
1625 | fprintf(tracefh,"\n"); | |
1626 | } | |
1627 | /* NOTE: Since the "din" format will only accept 32bit addresses, and | |
1628 | we may be generating 64bit ones, we should put the hi-32bits of the | |
1629 | address into the comment field. */ | |
1630 | ||
1631 | /* TODO: Provide a buffer for the trace lines. We can then avoid | |
1632 | performing writes until the buffer is filled, or the file is | |
1633 | being closed. */ | |
1634 | ||
1635 | /* NOTE: We could consider adding a comment field to the "din" file | |
1636 | produced using type 3 markers (unknown access). This would then | |
1637 | allow information about the program that the "din" is for, and | |
1638 | the MIPs world that was being simulated, to be placed into the | |
1639 | trace file. */ | |
1640 | ||
1641 | return; | |
1642 | } | |
1643 | #endif /* TRACE */ | |
1644 | ||
1645 | /*---------------------------------------------------------------------------*/ | |
1646 | /*-- simulator engine -------------------------------------------------------*/ | |
1647 | /*---------------------------------------------------------------------------*/ | |
1648 | ||
1649 | static void | |
1650 | ColdReset() | |
1651 | { | |
1652 | /* RESET: Fixed PC address: */ | |
e871dd18 | 1653 | PC = (((uword64)0xFFFFFFFF<<32) | 0xBFC00000); |
8bae0a0c JSC |
1654 | /* The reset vector address is in the unmapped, uncached memory space. */ |
1655 | ||
1656 | SR &= ~(status_SR | status_TS | status_RP); | |
1657 | SR |= (status_ERL | status_BEV); | |
1658 | /* VR4300 starts in Big-Endian mode */ | |
1659 | CONFIG &= ~(config_EP_mask << config_EP_shift); | |
1660 | CONFIG |= ((config_EP_D << config_EP_shift) | config_BE); | |
1661 | /* TODO: The VR4300 CONFIG register is not modelled fully at the moment */ | |
1662 | ||
1663 | #if defined(HASFPU) && (GPRLEN == (64)) | |
1664 | /* Cheat and allow access to the complete register set immediately: */ | |
1665 | SR |= status_FR; /* 64bit registers */ | |
1666 | #endif /* HASFPU and 64bit FP registers */ | |
1667 | ||
1668 | /* Ensure that any instructions with pending register updates are | |
1669 | cleared: */ | |
1670 | { | |
1671 | int loop; | |
1672 | for (loop = 0; (loop < PSLOTS); loop++) | |
1673 | pending_slot_reg[loop] = (LAST_EMBED_REGNUM + 1); | |
1674 | pending_in = pending_out = pending_total = 0; | |
1675 | } | |
1676 | ||
1677 | #if defined(HASFPU) | |
1678 | /* Initialise the FPU registers to the unknown state */ | |
1679 | { | |
1680 | int rn; | |
1681 | for (rn = 0; (rn < 32); rn++) | |
1682 | fpr_state[rn] = fmt_uninterpreted; | |
1683 | } | |
1684 | #endif /* HASFPU */ | |
1685 | ||
1686 | return; | |
1687 | } | |
1688 | ||
1689 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1690 | /* Translate a virtual address to a physical address and cache | |
1691 | coherence algorithm describing the mechanism used to resolve the | |
1692 | memory reference. Given the virtual address vAddr, and whether the | |
1693 | reference is to Instructions ot Data (IorD), find the corresponding | |
1694 | physical address (pAddr) and the cache coherence algorithm (CCA) | |
1695 | used to resolve the reference. If the virtual address is in one of | |
1696 | the unmapped address spaces the physical address and the CCA are | |
1697 | determined directly by the virtual address. If the virtual address | |
1698 | is in one of the mapped address spaces then the TLB is used to | |
1699 | determine the physical address and access type; if the required | |
1700 | translation is not present in the TLB or the desired access is not | |
1701 | permitted the function fails and an exception is taken. | |
1702 | ||
1703 | NOTE: This function is extended to return an exception state. This, | |
1704 | along with the exception generation is used to notify whether a | |
1705 | valid address translation occured */ | |
1706 | ||
1707 | static int | |
1708 | AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) | |
e871dd18 | 1709 | uword64 vAddr; |
8bae0a0c JSC |
1710 | int IorD; |
1711 | int LorS; | |
e871dd18 | 1712 | uword64 *pAddr; |
8bae0a0c JSC |
1713 | int *CCA; |
1714 | int host; | |
1715 | int raw; | |
1716 | { | |
1717 | int res = -1; /* TRUE : Assume good return */ | |
1718 | ||
1719 | #ifdef DEBUG | |
e871dd18 | 1720 | callback->printf_filtered(callback,"AddressTranslation(0x%08X%08X,%s,%s,...);\n",WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD")); |
8bae0a0c JSC |
1721 | #endif |
1722 | ||
1723 | /* Check that the address is valid for this memory model */ | |
1724 | ||
1725 | /* For a simple (flat) memory model, we simply pass virtual | |
1726 | addressess through (mostly) unchanged. */ | |
1727 | vAddr &= 0xFFFFFFFF; | |
1728 | *pAddr = vAddr; /* default for isTARGET */ | |
1729 | *CCA = Uncached; /* not used for isHOST */ | |
1730 | ||
1731 | /* NOTE: This is a duplicate of the code that appears in the | |
1732 | LoadMemory and StoreMemory functions. They should be merged into | |
1733 | a single function (that can be in-lined if required). */ | |
1734 | if ((vAddr >= membank_base) && (vAddr < (membank_base + membank_size))) { | |
1735 | if (host) | |
1736 | *pAddr = (int)&membank[((unsigned int)(vAddr - membank_base) & (membank_size - 1))]; | |
1737 | } else if ((vAddr >= monitor_base) && (vAddr < (monitor_base + monitor_size))) { | |
1738 | if (host) | |
1739 | *pAddr = (int)&monitor[((unsigned int)(vAddr - monitor_base) & (monitor_size - 1))]; | |
1740 | } else { | |
1741 | #if 1 /* def DEBUG */ | |
e871dd18 | 1742 | callback->printf_filtered(callback,"Failed: AddressTranslation(0x%08X%08X,%s,%s,...);\n",WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "isSTORE" : "isLOAD")); |
8bae0a0c JSC |
1743 | #endif /* DEBUG */ |
1744 | res = 0; /* AddressTranslation has failed */ | |
1745 | *pAddr = -1; | |
1746 | if (!raw) /* only generate exceptions on real memory transfers */ | |
1747 | SignalException((LorS == isSTORE) ? AddressStore : AddressLoad); | |
1748 | else | |
e871dd18 | 1749 | callback->printf_filtered(callback,"AddressTranslation for %s %s from 0x%08X%08X failed\n",(IorD ? "data" : "instruction"),(LorS ? "store" : "load"),WORD64HI(vAddr),WORD64LO(vAddr)); |
8bae0a0c JSC |
1750 | } |
1751 | ||
1752 | return(res); | |
1753 | } | |
1754 | ||
1755 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1756 | /* Prefetch data from memory. Prefetch is an advisory instruction for | |
1757 | which an implementation specific action is taken. The action taken | |
1758 | may increase performance, but must not change the meaning of the | |
1759 | program, or alter architecturally-visible state. */ | |
1760 | static void | |
1761 | Prefetch(CCA,pAddr,vAddr,DATA,hint) | |
1762 | int CCA; | |
e871dd18 JSC |
1763 | uword64 pAddr; |
1764 | uword64 vAddr; | |
8bae0a0c JSC |
1765 | int DATA; |
1766 | int hint; | |
1767 | { | |
1768 | #ifdef DEBUG | |
e871dd18 | 1769 | callback->printf_filtered(callback,"Prefetch(%d,0x%08X%08X,0x%08X%08X,%d,%d);\n",CCA,WORD64HI(pAddr),WORD64LO(pAddr),WORD64HI(vAddr),WORD64LO(vAddr),DATA,hint); |
8bae0a0c JSC |
1770 | #endif /* DEBUG */ |
1771 | ||
1772 | /* For our simple memory model we do nothing */ | |
1773 | return; | |
1774 | } | |
1775 | ||
1776 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1777 | /* Load a value from memory. Use the cache and main memory as | |
1778 | specified in the Cache Coherence Algorithm (CCA) and the sort of | |
1779 | access (IorD) to find the contents of AccessLength memory bytes | |
1780 | starting at physical location pAddr. The data is returned in the | |
1781 | fixed width naturally-aligned memory element (MemElem). The | |
1782 | low-order two (or three) bits of the address and the AccessLength | |
1783 | indicate which of the bytes within MemElem needs to be given to the | |
1784 | processor. If the memory access type of the reference is uncached | |
1785 | then only the referenced bytes are read from memory and valid | |
1786 | within the memory element. If the access type is cached, and the | |
1787 | data is not present in cache, an implementation specific size and | |
1788 | alignment block of memory is read and loaded into the cache to | |
1789 | satisfy a load reference. At a minimum, the block is the entire | |
1790 | memory element. */ | |
e871dd18 | 1791 | static uword64 |
8bae0a0c JSC |
1792 | LoadMemory(CCA,AccessLength,pAddr,vAddr,IorD,raw) |
1793 | int CCA; | |
1794 | int AccessLength; | |
e871dd18 JSC |
1795 | uword64 pAddr; |
1796 | uword64 vAddr; | |
8bae0a0c JSC |
1797 | int IorD; |
1798 | int raw; | |
1799 | { | |
e871dd18 | 1800 | uword64 value; |
8bae0a0c JSC |
1801 | |
1802 | #ifdef DEBUG | |
1803 | if (membank == NULL) | |
e871dd18 | 1804 | callback->printf_filtered(callback,"DBG: LoadMemory(%d,%d,0x%08X%08X,0x%08X%08X,%s,%s)\n",CCA,AccessLength,WORD64HI(pAddr),WORD64LO(pAddr),WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(raw ? "isRAW" : "isREAL")); |
8bae0a0c JSC |
1805 | #endif /* DEBUG */ |
1806 | ||
1807 | #if defined(WARN_MEM) | |
1808 | if (CCA != uncached) | |
1809 | callback->printf_filtered(callback,"SIM Warning: LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); | |
1810 | ||
1811 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) { | |
1812 | /* In reality this should be a Bus Error */ | |
e871dd18 | 1813 | sim_error("AccessLength of %d would extend over 64bit aligned boundary for physical address 0x%08X%08X\n",AccessLength,WORD64HI(pAddr),WORD64LO(pAddr)); |
8bae0a0c JSC |
1814 | } |
1815 | #endif /* WARN_MEM */ | |
1816 | ||
1817 | /* Decide which physical memory locations are being dealt with. At | |
1818 | this point we should be able to split the pAddr bits into the | |
1819 | relevant address map being simulated. If the "raw" variable is | |
1820 | set, the memory read being performed should *NOT* update any I/O | |
1821 | state or affect the CPU state. This also includes avoiding | |
1822 | affecting statistics gathering. */ | |
1823 | ||
1824 | /* If instruction fetch then we need to check that the two lo-order | |
1825 | bits are zero, otherwise raise a InstructionFetch exception: */ | |
1826 | if ((IorD == isINSTRUCTION) && ((pAddr & 0x3) != 0)) | |
1827 | SignalException(InstructionFetch); | |
1828 | else { | |
1829 | unsigned int index; | |
1830 | unsigned char *mem = NULL; | |
1831 | ||
8bae0a0c JSC |
1832 | #if defined(TRACE) |
1833 | if (!raw) | |
1834 | dotrace(tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); | |
1835 | #endif /* TRACE */ | |
1836 | ||
1837 | /* NOTE: Quicker methods of decoding the address space can be used | |
1838 | when a real memory map is being simulated (i.e. using hi-order | |
1839 | address bits to select device). */ | |
1840 | if ((pAddr >= membank_base) && (pAddr < (membank_base + membank_size))) { | |
1841 | index = ((unsigned int)(pAddr - membank_base) & (membank_size - 1)); | |
1842 | mem = membank; | |
1843 | } else if ((pAddr >= monitor_base) && (pAddr < (monitor_base + monitor_size))) { | |
1844 | index = ((unsigned int)(pAddr - monitor_base) & (monitor_size - 1)); | |
1845 | mem = monitor; | |
1846 | } | |
1847 | if (mem == NULL) | |
e871dd18 | 1848 | sim_error("Simulator memory not found for physical address 0x%08X%08X\n",WORD64HI(pAddr),WORD64LO(pAddr)); |
8bae0a0c JSC |
1849 | else { |
1850 | /* If we obtained the endianness of the host, and it is the same | |
1851 | as the target memory system we can optimise the memory | |
1852 | accesses. However, without that information we must perform | |
1853 | slow transfer, and hope that the compiler optimisation will | |
1854 | merge successive loads. */ | |
1855 | value = 0; /* no data loaded yet */ | |
1856 | ||
1857 | /* In reality we should always be loading a doubleword value (or | |
1858 | word value in 32bit memory worlds). The external code then | |
1859 | extracts the required bytes. However, to keep performance | |
1860 | high we only load the required bytes into the relevant | |
1861 | slots. */ | |
1862 | if (BigEndianMem) | |
1863 | switch (AccessLength) { /* big-endian memory */ | |
1864 | case AccessLength_DOUBLEWORD : | |
e871dd18 | 1865 | value |= ((uword64)mem[index++] << 56); |
8bae0a0c | 1866 | case AccessLength_SEPTIBYTE : |
e871dd18 | 1867 | value |= ((uword64)mem[index++] << 48); |
8bae0a0c | 1868 | case AccessLength_SEXTIBYTE : |
e871dd18 | 1869 | value |= ((uword64)mem[index++] << 40); |
8bae0a0c | 1870 | case AccessLength_QUINTIBYTE : |
e871dd18 | 1871 | value |= ((uword64)mem[index++] << 32); |
8bae0a0c JSC |
1872 | case AccessLength_WORD : |
1873 | value |= ((unsigned int)mem[index++] << 24); | |
1874 | case AccessLength_TRIPLEBYTE : | |
1875 | value |= ((unsigned int)mem[index++] << 16); | |
1876 | case AccessLength_HALFWORD : | |
1877 | value |= ((unsigned int)mem[index++] << 8); | |
1878 | case AccessLength_BYTE : | |
1879 | value |= mem[index]; | |
1880 | break; | |
1881 | } | |
1882 | else { | |
1883 | index += (AccessLength + 1); | |
1884 | switch (AccessLength) { /* little-endian memory */ | |
1885 | case AccessLength_DOUBLEWORD : | |
e871dd18 | 1886 | value |= ((uword64)mem[--index] << 56); |
8bae0a0c | 1887 | case AccessLength_SEPTIBYTE : |
e871dd18 | 1888 | value |= ((uword64)mem[--index] << 48); |
8bae0a0c | 1889 | case AccessLength_SEXTIBYTE : |
e871dd18 | 1890 | value |= ((uword64)mem[--index] << 40); |
8bae0a0c | 1891 | case AccessLength_QUINTIBYTE : |
e871dd18 | 1892 | value |= ((uword64)mem[--index] << 32); |
8bae0a0c | 1893 | case AccessLength_WORD : |
e871dd18 | 1894 | value |= ((uword64)mem[--index] << 24); |
8bae0a0c | 1895 | case AccessLength_TRIPLEBYTE : |
e871dd18 | 1896 | value |= ((uword64)mem[--index] << 16); |
8bae0a0c | 1897 | case AccessLength_HALFWORD : |
e871dd18 | 1898 | value |= ((uword64)mem[--index] << 8); |
8bae0a0c | 1899 | case AccessLength_BYTE : |
e871dd18 | 1900 | value |= ((uword64)mem[--index] << 0); |
8bae0a0c JSC |
1901 | break; |
1902 | } | |
1903 | } | |
1904 | ||
1905 | #ifdef DEBUG | |
e871dd18 | 1906 | printf("DBG: LoadMemory() : (offset %d) : value = 0x%08X%08X\n",(int)(pAddr & LOADDRMASK),WORD64HI(value),WORD64LO(value)); |
8bae0a0c JSC |
1907 | #endif /* DEBUG */ |
1908 | ||
1909 | /* TODO: We could try and avoid the shifts when dealing with raw | |
1910 | memory accesses. This would mean updating the LoadMemory and | |
1911 | StoreMemory routines to avoid shifting the data before | |
1912 | returning or using it. */ | |
1913 | if (!raw) { /* do nothing for raw accessess */ | |
1914 | if (BigEndianMem) | |
1915 | value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
1916 | else /* little-endian only needs to be shifted up to the correct byte offset */ | |
1917 | value <<= ((pAddr & LOADDRMASK) * 8); | |
1918 | } | |
1919 | ||
1920 | #ifdef DEBUG | |
e871dd18 JSC |
1921 | printf("DBG: LoadMemory() : shifted value = 0x%08X%08X\n",WORD64HI(value),WORD64LO(value)); |
1922 | #endif /* DEBUG */ | |
8bae0a0c JSC |
1923 | } |
1924 | } | |
1925 | ||
1926 | return(value); | |
1927 | } | |
1928 | ||
1929 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1930 | /* Store a value to memory. The specified data is stored into the | |
1931 | physical location pAddr using the memory hierarchy (data caches and | |
1932 | main memory) as specified by the Cache Coherence Algorithm | |
1933 | (CCA). The MemElem contains the data for an aligned, fixed-width | |
1934 | memory element (word for 32-bit processors, doubleword for 64-bit | |
1935 | processors), though only the bytes that will actually be stored to | |
1936 | memory need to be valid. The low-order two (or three) bits of pAddr | |
1937 | and the AccessLength field indicates which of the bytes within the | |
1938 | MemElem data should actually be stored; only these bytes in memory | |
1939 | will be changed. */ | |
1940 | static void | |
1941 | StoreMemory(CCA,AccessLength,MemElem,pAddr,vAddr,raw) | |
1942 | int CCA; | |
1943 | int AccessLength; | |
e871dd18 JSC |
1944 | uword64 MemElem; |
1945 | uword64 pAddr; | |
1946 | uword64 vAddr; | |
8bae0a0c JSC |
1947 | int raw; |
1948 | { | |
1949 | #ifdef DEBUG | |
e871dd18 | 1950 | callback->printf_filtered(callback,"DBG: StoreMemory(%d,%d,0x%08X%08X,0x%08X%08X,0x%08X%08X,%s)\n",CCA,AccessLength,WORD64HI(MemElem),WORD64LO(MemElem),WORD64HI(pAddr),WORD64LO(pAddr),WORD64HI(vAddr),WORD64LO(vAddr),(raw ? "isRAW" : "isREAL")); |
8bae0a0c JSC |
1951 | #endif /* DEBUG */ |
1952 | ||
1953 | #if defined(WARN_MEM) | |
1954 | if (CCA != uncached) | |
1955 | callback->printf_filtered(callback,"SIM Warning: StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); | |
1956 | ||
1957 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
e871dd18 | 1958 | sim_error("AccessLength of %d would extend over 64bit aligned boundary for physical address 0x%08X%08X\n",AccessLength,WORD64HI(pAddr),WORD64LO(pAddr)); |
8bae0a0c JSC |
1959 | #endif /* WARN_MEM */ |
1960 | ||
1961 | #if defined(TRACE) | |
1962 | if (!raw) | |
1963 | dotrace(tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store"); | |
1964 | #endif /* TRACE */ | |
1965 | ||
1966 | /* See the comments in the LoadMemory routine about optimising | |
1967 | memory accesses. Also if we wanted to make the simulator smaller, | |
1968 | we could merge a lot of this code with the LoadMemory | |
1969 | routine. However, this would slow the simulator down with | |
1970 | run-time conditionals. */ | |
1971 | { | |
1972 | unsigned int index; | |
1973 | unsigned char *mem = NULL; | |
1974 | ||
1975 | if ((pAddr >= membank_base) && (pAddr < (membank_base + membank_size))) { | |
1976 | index = ((unsigned int)(pAddr - membank_base) & (membank_size - 1)); | |
1977 | mem = membank; | |
1978 | } else if ((pAddr >= monitor_base) && (pAddr < (monitor_base + monitor_size))) { | |
1979 | index = ((unsigned int)(pAddr - monitor_base) & (monitor_size - 1)); | |
1980 | mem = monitor; | |
1981 | } | |
1982 | ||
1983 | if (mem == NULL) | |
e871dd18 | 1984 | sim_error("Simulator memory not found for physical address 0x%08X%08X\n",WORD64HI(pAddr),WORD64LO(pAddr)); |
8bae0a0c JSC |
1985 | else { |
1986 | int shift = 0; | |
1987 | ||
1988 | #ifdef DEBUG | |
e871dd18 | 1989 | printf("DBG: StoreMemory: offset = %d MemElem = 0x%08X%08X\n",(unsigned int)(pAddr & LOADDRMASK),WORD64HI(MemElem),WORD64LO(MemElem)); |
8bae0a0c JSC |
1990 | #endif /* DEBUG */ |
1991 | ||
1992 | if (BigEndianMem) { | |
1993 | if (raw) | |
1994 | shift = ((7 - AccessLength) * 8); | |
1995 | else /* real memory access */ | |
1996 | shift = ((pAddr & LOADDRMASK) * 8); | |
1997 | MemElem <<= shift; | |
1998 | } else { | |
1999 | /* no need to shift raw little-endian data */ | |
2000 | if (!raw) | |
2001 | MemElem >>= ((pAddr & LOADDRMASK) * 8); | |
2002 | } | |
2003 | ||
2004 | #ifdef DEBUG | |
e871dd18 | 2005 | printf("DBG: StoreMemory: shift = %d MemElem = 0x%08X%08X\n",shift,WORD64HI(MemElem),WORD64LO(MemElem)); |
8bae0a0c JSC |
2006 | #endif /* DEBUG */ |
2007 | ||
2008 | if (BigEndianMem) { | |
2009 | switch (AccessLength) { /* big-endian memory */ | |
2010 | case AccessLength_DOUBLEWORD : | |
2011 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2012 | MemElem <<= 8; | |
2013 | case AccessLength_SEPTIBYTE : | |
2014 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2015 | MemElem <<= 8; | |
2016 | case AccessLength_SEXTIBYTE : | |
2017 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2018 | MemElem <<= 8; | |
2019 | case AccessLength_QUINTIBYTE : | |
2020 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2021 | MemElem <<= 8; | |
2022 | case AccessLength_WORD : | |
2023 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2024 | MemElem <<= 8; | |
2025 | case AccessLength_TRIPLEBYTE : | |
2026 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2027 | MemElem <<= 8; | |
2028 | case AccessLength_HALFWORD : | |
2029 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2030 | MemElem <<= 8; | |
2031 | case AccessLength_BYTE : | |
2032 | mem[index++] = (unsigned char)(MemElem >> 56); | |
2033 | break; | |
2034 | } | |
2035 | } else { | |
2036 | index += (AccessLength + 1); | |
2037 | switch (AccessLength) { /* little-endian memory */ | |
2038 | case AccessLength_DOUBLEWORD : | |
2039 | mem[--index] = (unsigned char)(MemElem >> 56); | |
2040 | case AccessLength_SEPTIBYTE : | |
2041 | mem[--index] = (unsigned char)(MemElem >> 48); | |
2042 | case AccessLength_SEXTIBYTE : | |
2043 | mem[--index] = (unsigned char)(MemElem >> 40); | |
2044 | case AccessLength_QUINTIBYTE : | |
2045 | mem[--index] = (unsigned char)(MemElem >> 32); | |
2046 | case AccessLength_WORD : | |
2047 | mem[--index] = (unsigned char)(MemElem >> 24); | |
2048 | case AccessLength_TRIPLEBYTE : | |
2049 | mem[--index] = (unsigned char)(MemElem >> 16); | |
2050 | case AccessLength_HALFWORD : | |
2051 | mem[--index] = (unsigned char)(MemElem >> 8); | |
2052 | case AccessLength_BYTE : | |
2053 | mem[--index] = (unsigned char)(MemElem >> 0); | |
2054 | break; | |
2055 | } | |
2056 | } | |
2057 | } | |
2058 | } | |
2059 | ||
2060 | return; | |
2061 | } | |
2062 | ||
2063 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
2064 | /* Order loads and stores to synchronise shared memory. Perform the | |
2065 | action necessary to make the effects of groups of synchronizable | |
2066 | loads and stores indicated by stype occur in the same order for all | |
2067 | processors. */ | |
2068 | static void | |
2069 | SyncOperation(stype) | |
2070 | int stype; | |
2071 | { | |
2072 | #ifdef DEBUG | |
2073 | callback->printf_filtered(callback,"SyncOperation(%d) : TODO\n",stype); | |
2074 | #endif /* DEBUG */ | |
2075 | return; | |
2076 | } | |
2077 | ||
2078 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
2079 | /* Signal an exception condition. This will result in an exception | |
2080 | that aborts the instruction. The instruction operation pseudocode | |
2081 | will never see a return from this function call. */ | |
2082 | static void | |
2083 | SignalException(exception) | |
2084 | int exception; | |
2085 | { | |
2086 | /* Ensure that any active atomic read/modify/write operation will fail: */ | |
2087 | LLBIT = 0; | |
2088 | ||
2089 | switch (exception) { | |
2090 | /* TODO: For testing purposes I have been ignoring TRAPs. In | |
2091 | reality we should either simulate them, or allow the user to | |
2092 | ignore them at run-time. */ | |
2093 | case Trap : | |
e871dd18 | 2094 | callback->printf_filtered(callback,"Ignoring instruction TRAP (PC 0x%08X%08X)\n",WORD64HI(IPC),WORD64LO(IPC)); |
8bae0a0c JSC |
2095 | break; |
2096 | ||
2097 | case ReservedInstruction : | |
2098 | { | |
2099 | va_list ap; | |
2100 | unsigned int instruction; | |
2101 | va_start(ap,exception); | |
2102 | instruction = va_arg(ap,unsigned int); | |
2103 | va_end(ap); | |
2104 | /* Provide simple monitor support using ReservedInstruction | |
2105 | exceptions. The following code simulates the fixed vector | |
2106 | entry points into the IDT monitor by causing a simulator | |
2107 | trap, performing the monitor operation, and returning to | |
2108 | the address held in the $ra register (standard PCS return | |
2109 | address). This means we only need to pre-load the vector | |
2110 | space with suitable instruction values. For systems were | |
2111 | actual trap instructions are used, we would not need to | |
2112 | perform this magic. */ | |
2113 | if ((instruction & ~RSVD_INSTRUCTION_AMASK) == RSVD_INSTRUCTION) { | |
2114 | sim_monitor(instruction & RSVD_INSTRUCTION_AMASK); | |
2115 | PC = RA; /* simulate the return from the vector entry */ | |
2116 | /* NOTE: This assumes that a branch-and-link style | |
2117 | instruction was used to enter the vector (which is the | |
2118 | case with the current IDT monitor). */ | |
2119 | break; /* out of the switch statement */ | |
2120 | } /* else fall through to normal exception processing */ | |
e871dd18 | 2121 | callback->printf_filtered(callback,"DBG: ReservedInstruction 0x%08X at IPC = 0x%08X%08X\n",instruction,WORD64HI(IPC),WORD64LO(IPC)); |
8bae0a0c JSC |
2122 | } |
2123 | ||
2124 | default: | |
2125 | #if 1 /* def DEBUG */ | |
e871dd18 | 2126 | callback->printf_filtered(callback,"DBG: SignalException(%d) IPC = 0x%08X%08X\n",exception,WORD64HI(IPC),WORD64LO(IPC)); |
8bae0a0c JSC |
2127 | #endif /* DEBUG */ |
2128 | /* Store exception code into current exception id variable (used | |
2129 | by exit code): */ | |
2130 | ||
2131 | /* TODO: If not simulating exceptions then stop the simulator | |
2132 | execution. At the moment we always stop the simulation. */ | |
2133 | state |= (simSTOP | simEXCEPTION); | |
2134 | CAUSE = (exception << 2); | |
2135 | if (state & simDELAYSLOT) { | |
2136 | CAUSE |= cause_BD; | |
2137 | EPC = (IPC - 4); /* reference the branch instruction */ | |
2138 | } else | |
2139 | EPC = IPC; | |
2140 | /* The following is so that the simulator will continue from the | |
2141 | exception address on breakpoint operations. */ | |
2142 | PC = EPC; | |
2143 | break; | |
2144 | ||
2145 | case SimulatorFault: | |
2146 | { | |
2147 | va_list ap; | |
2148 | char *msg; | |
2149 | va_start(ap,exception); | |
2150 | msg = va_arg(ap,char *); | |
2151 | fprintf(stderr,"FATAL: Simulator error \"%s\"\n",msg); | |
2152 | va_end(ap); | |
2153 | } | |
2154 | exit(1); | |
2155 | } | |
2156 | ||
2157 | return; | |
2158 | } | |
2159 | ||
2160 | #if defined(WARN_RESULT) | |
2161 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
2162 | /* This function indicates that the result of the operation is | |
2163 | undefined. However, this should not affect the instruction | |
2164 | stream. All that is meant to happen is that the destination | |
2165 | register is set to an undefined result. To keep the simulator | |
2166 | simple, we just don't bother updating the destination register, so | |
2167 | the overall result will be undefined. If desired we can stop the | |
2168 | simulator by raising a pseudo-exception. */ | |
2169 | static void | |
2170 | UndefinedResult() | |
2171 | { | |
e871dd18 | 2172 | callback->printf_filtered(callback,"UndefinedResult: IPC = 0x%08X%08X\n",WORD64HI(IPC),WORD64LO(IPC)); |
8bae0a0c JSC |
2173 | #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */ |
2174 | state |= simSTOP; | |
2175 | #endif | |
2176 | return; | |
2177 | } | |
2178 | #endif /* WARN_RESULT */ | |
2179 | ||
2180 | static void | |
2181 | CacheOp(op,pAddr,vAddr,instruction) | |
2182 | int op; | |
e871dd18 JSC |
2183 | uword64 pAddr; |
2184 | uword64 vAddr; | |
8bae0a0c JSC |
2185 | unsigned int instruction; |
2186 | { | |
2187 | /* If CP0 is not useable (User or Supervisor mode) and the CP0 | |
2188 | enable bit in the Status Register is clear - a coprocessor | |
2189 | unusable exception is taken. */ | |
e871dd18 | 2190 | callback->printf_filtered(callback,"TODO: Cache availability checking (PC = 0x%08X%08X)\n",WORD64HI(IPC),WORD64LO(IPC)); |
8bae0a0c JSC |
2191 | |
2192 | switch (op & 0x3) { | |
2193 | case 0: /* instruction cache */ | |
2194 | switch (op >> 2) { | |
2195 | case 0: /* Index Invalidate */ | |
2196 | case 1: /* Index Load Tag */ | |
2197 | case 2: /* Index Store Tag */ | |
2198 | case 4: /* Hit Invalidate */ | |
2199 | case 5: /* Fill */ | |
2200 | case 6: /* Hit Writeback */ | |
2201 | callback->printf_filtered(callback,"SIM Warning: Instruction CACHE operation %d to be coded\n",(op >> 2)); | |
2202 | break; | |
2203 | ||
2204 | default: | |
2205 | SignalException(ReservedInstruction,instruction); | |
2206 | break; | |
2207 | } | |
2208 | break; | |
2209 | ||
2210 | case 1: /* data cache */ | |
2211 | switch (op >> 2) { | |
2212 | case 0: /* Index Writeback Invalidate */ | |
2213 | case 1: /* Index Load Tag */ | |
2214 | case 2: /* Index Store Tag */ | |
2215 | case 3: /* Create Dirty */ | |
2216 | case 4: /* Hit Invalidate */ | |
2217 | case 5: /* Hit Writeback Invalidate */ | |
2218 | case 6: /* Hit Writeback */ | |
2219 | callback->printf_filtered(callback,"SIM Warning: Data CACHE operation %d to be coded\n",(op >> 2)); | |
2220 | break; | |
2221 | ||
2222 | default: | |
2223 | SignalException(ReservedInstruction,instruction); | |
2224 | break; | |
2225 | } | |
2226 | break; | |
2227 | ||
2228 | default: /* unrecognised cache ID */ | |
2229 | SignalException(ReservedInstruction,instruction); | |
2230 | break; | |
2231 | } | |
2232 | ||
2233 | return; | |
2234 | } | |
2235 | ||
2236 | /*-- FPU support routines ---------------------------------------------------*/ | |
2237 | ||
2238 | #if defined(HASFPU) /* Only needed when building FPU aware simulators */ | |
2239 | ||
2240 | #if 1 | |
2241 | #define SizeFGR() (GPRLEN) | |
2242 | #else | |
2243 | /* They depend on the CPU being simulated */ | |
2244 | #define SizeFGR() ((PROCESSOR_64BIT && ((SR & status_FR) == 1)) ? 64 : 32) | |
2245 | #endif | |
2246 | ||
2247 | /* Numbers are held in normalized form. The SINGLE and DOUBLE binary | |
2248 | formats conform to ANSI/IEEE Std 754-1985. */ | |
2249 | /* SINGLE precision floating: | |
2250 | * seeeeeeeefffffffffffffffffffffff | |
2251 | * s = 1bit = sign | |
2252 | * e = 8bits = exponent | |
2253 | * f = 23bits = fraction | |
2254 | */ | |
2255 | /* SINGLE precision fixed: | |
2256 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
2257 | * s = 1bit = sign | |
2258 | * i = 31bits = integer | |
2259 | */ | |
2260 | /* DOUBLE precision floating: | |
2261 | * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff | |
2262 | * s = 1bit = sign | |
2263 | * e = 11bits = exponent | |
2264 | * f = 52bits = fraction | |
2265 | */ | |
2266 | /* DOUBLE precision fixed: | |
2267 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
2268 | * s = 1bit = sign | |
2269 | * i = 63bits = integer | |
2270 | */ | |
2271 | ||
2272 | /* Extract sign-bit: */ | |
2273 | #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0) | |
e871dd18 | 2274 | #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0) |
8bae0a0c JSC |
2275 | /* Extract biased exponent: */ |
2276 | #define FP_S_be(v) (((v) >> 23) & 0xFF) | |
2277 | #define FP_D_be(v) (((v) >> 52) & 0x7FF) | |
2278 | /* Extract unbiased Exponent: */ | |
2279 | #define FP_S_e(v) (FP_S_be(v) - 0x7F) | |
2280 | #define FP_D_e(v) (FP_D_be(v) - 0x3FF) | |
2281 | /* Extract complete fraction field: */ | |
2282 | #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23)) | |
e871dd18 | 2283 | #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52)) |
8bae0a0c JSC |
2284 | /* Extract numbered fraction bit: */ |
2285 | #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0) | |
2286 | #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0) | |
2287 | ||
2288 | /* Explicit QNaN values used when value required: */ | |
2289 | #define FPQNaN_SINGLE (0x7FBFFFFF) | |
2290 | #define FPQNaN_WORD (0x7FFFFFFF) | |
e871dd18 JSC |
2291 | #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF) |
2292 | #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF) | |
8bae0a0c JSC |
2293 | |
2294 | /* Explicit Infinity values used when required: */ | |
2295 | #define FPINF_SINGLE (0x7F800000) | |
e871dd18 | 2296 | #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000) |
8bae0a0c JSC |
2297 | |
2298 | #if 1 /* def DEBUG */ | |
2299 | #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor"))) | |
2300 | #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>")))))) | |
2301 | #endif /* DEBUG */ | |
2302 | ||
e871dd18 | 2303 | static uword64 |
8bae0a0c JSC |
2304 | ValueFPR(fpr,fmt) |
2305 | int fpr; | |
2306 | FP_formats fmt; | |
2307 | { | |
e871dd18 | 2308 | uword64 value; |
8bae0a0c JSC |
2309 | int err = 0; |
2310 | ||
2311 | /* Treat unused register values, as fixed-point 64bit values: */ | |
2312 | if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown)) | |
2313 | #if 1 | |
2314 | /* If request to read data as "uninterpreted", then use the current | |
2315 | encoding: */ | |
2316 | fmt = fpr_state[fpr]; | |
2317 | #else | |
2318 | fmt = fmt_long; | |
2319 | #endif | |
2320 | ||
2321 | /* For values not yet accessed, set to the desired format: */ | |
2322 | if (fpr_state[fpr] == fmt_uninterpreted) { | |
2323 | fpr_state[fpr] = fmt; | |
2324 | #ifdef DEBUG | |
2325 | printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt)); | |
2326 | #endif /* DEBUG */ | |
2327 | } | |
2328 | if (fmt != fpr_state[fpr]) { | |
e871dd18 | 2329 | callback->printf_filtered(callback,"Warning: FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%08X%08X)\n",fpr,DOFMT(fpr_state[fpr]),DOFMT(fmt),WORD64HI(IPC),WORD64LO(IPC)); |
8bae0a0c JSC |
2330 | fpr_state[fpr] = fmt_unknown; |
2331 | } | |
2332 | ||
2333 | if (fpr_state[fpr] == fmt_unknown) { | |
2334 | /* Set QNaN value: */ | |
2335 | switch (fmt) { | |
2336 | case fmt_single: | |
2337 | value = FPQNaN_SINGLE; | |
2338 | break; | |
2339 | ||
2340 | case fmt_double: | |
2341 | value = FPQNaN_DOUBLE; | |
2342 | break; | |
2343 | ||
2344 | case fmt_word: | |
2345 | value = FPQNaN_WORD; | |
2346 | break; | |
2347 | ||
2348 | case fmt_long: | |
2349 | value = FPQNaN_LONG; | |
2350 | break; | |
2351 | ||
2352 | default: | |
2353 | err = -1; | |
2354 | break; | |
2355 | } | |
2356 | } else if (SizeFGR() == 64) { | |
2357 | switch (fmt) { | |
2358 | case fmt_single: | |
2359 | case fmt_word: | |
2360 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2361 | break; | |
2362 | ||
2363 | case fmt_uninterpreted: | |
2364 | case fmt_double: | |
2365 | case fmt_long: | |
2366 | value = FGR[fpr]; | |
2367 | break; | |
2368 | ||
2369 | default : | |
2370 | err = -1; | |
2371 | break; | |
2372 | } | |
2373 | } else if ((fpr & 1) == 0) { /* even registers only */ | |
2374 | switch (fmt) { | |
2375 | case fmt_single: | |
2376 | case fmt_word: | |
2377 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2378 | break; | |
2379 | ||
2380 | case fmt_uninterpreted: | |
2381 | case fmt_double: | |
2382 | case fmt_long: | |
2383 | value = ((FGR[fpr+1] << 32) | (FGR[fpr] & 0xFFFFFFFF)); | |
2384 | break; | |
2385 | ||
2386 | default : | |
2387 | err = -1; | |
2388 | break; | |
2389 | } | |
2390 | } | |
2391 | ||
2392 | if (err) | |
2393 | SignalException(SimulatorFault,"Unrecognised FP format in ValueFPR()"); | |
2394 | ||
2395 | #ifdef DEBUG | |
e871dd18 | 2396 | printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%08X%08X : PC = 0x%08X%08X : SizeFGR() = %d\n",fpr,DOFMT(fmt),WORD64HI(value),WORD64LO(value),WORD64HI(IPC),WORD64LO(IPC),SizeFGR()); |
8bae0a0c JSC |
2397 | #endif /* DEBUG */ |
2398 | ||
2399 | return(value); | |
2400 | } | |
2401 | ||
2402 | static void | |
2403 | StoreFPR(fpr,fmt,value) | |
2404 | int fpr; | |
2405 | FP_formats fmt; | |
e871dd18 | 2406 | uword64 value; |
8bae0a0c JSC |
2407 | { |
2408 | int err = 0; | |
2409 | ||
2410 | #ifdef DEBUG | |
e871dd18 | 2411 | printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%08X%08X : PC = 0x%08X%08X : SizeFGR() = %d\n",fpr,DOFMT(fmt),WORD64HI(value),WORD64LO(value),WORD64HI(IPC),WORD64LO(IPC),SizeFGR()); |
8bae0a0c JSC |
2412 | #endif /* DEBUG */ |
2413 | ||
2414 | if (SizeFGR() == 64) { | |
2415 | switch (fmt) { | |
2416 | case fmt_single : | |
2417 | case fmt_word : | |
e871dd18 | 2418 | FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF)); |
8bae0a0c JSC |
2419 | fpr_state[fpr] = fmt; |
2420 | break; | |
2421 | ||
2422 | case fmt_uninterpreted: | |
2423 | case fmt_double : | |
2424 | case fmt_long : | |
2425 | FGR[fpr] = value; | |
2426 | fpr_state[fpr] = fmt; | |
2427 | break; | |
2428 | ||
2429 | default : | |
2430 | fpr_state[fpr] = fmt_unknown; | |
2431 | err = -1; | |
2432 | break; | |
2433 | } | |
2434 | } else if ((fpr & 1) == 0) { /* even register number only */ | |
2435 | switch (fmt) { | |
2436 | case fmt_single : | |
2437 | case fmt_word : | |
2438 | FGR[fpr+1] = 0xDEADC0DE; | |
2439 | FGR[fpr] = (value & 0xFFFFFFFF); | |
2440 | fpr_state[fpr + 1] = fmt; | |
2441 | fpr_state[fpr] = fmt; | |
2442 | break; | |
2443 | ||
2444 | case fmt_uninterpreted: | |
2445 | case fmt_double : | |
2446 | case fmt_long : | |
2447 | FGR[fpr+1] = (value >> 32); | |
2448 | FGR[fpr] = (value & 0xFFFFFFFF); | |
2449 | fpr_state[fpr + 1] = fmt; | |
2450 | fpr_state[fpr] = fmt; | |
2451 | break; | |
2452 | ||
2453 | default : | |
2454 | fpr_state[fpr] = fmt_unknown; | |
2455 | err = -1; | |
2456 | break; | |
2457 | } | |
e871dd18 JSC |
2458 | } |
2459 | #if defined(WARN_RESULT) | |
2460 | else | |
2461 | UndefinedResult(); | |
2462 | #endif /* WARN_RESULT */ | |
8bae0a0c JSC |
2463 | |
2464 | if (err) | |
2465 | SignalException(SimulatorFault,"Unrecognised FP format in StoreFPR()"); | |
2466 | ||
2467 | #ifdef DEBUG | |
e871dd18 | 2468 | printf("DBG: StoreFPR: fpr[%d] = 0x%08X%08X (format %s)\n",fpr,WORD64HI(FGR[fpr]),WORD64LO(FGR[fpr]),DOFMT(fmt)); |
8bae0a0c JSC |
2469 | #endif /* DEBUG */ |
2470 | ||
2471 | return; | |
2472 | } | |
2473 | ||
2474 | static int | |
2475 | NaN(op,fmt) | |
e871dd18 | 2476 | uword64 op; |
8bae0a0c JSC |
2477 | FP_formats fmt; |
2478 | { | |
2479 | int boolean = 0; | |
2480 | ||
2481 | /* Check if (((E - bias) == (E_max + 1)) && (fraction != 0)). We | |
2482 | know that the exponent field is biased... we we cheat and avoid | |
2483 | removing the bias value. */ | |
2484 | switch (fmt) { | |
2485 | case fmt_single: | |
2486 | boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) != 0)); | |
2487 | /* We could use "FP_S_fb(1,op)" to ascertain whether we are | |
2488 | dealing with a SNaN or QNaN */ | |
2489 | break; | |
2490 | case fmt_double: | |
2491 | boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) != 0)); | |
2492 | /* We could use "FP_S_fb(1,op)" to ascertain whether we are | |
2493 | dealing with a SNaN or QNaN */ | |
2494 | break; | |
2495 | case fmt_word: | |
2496 | boolean = (op == FPQNaN_WORD); | |
2497 | break; | |
2498 | case fmt_long: | |
2499 | boolean = (op == FPQNaN_LONG); | |
2500 | break; | |
2501 | } | |
2502 | ||
2503 | #ifdef DEBUG | |
e871dd18 | 2504 | printf("DBG: NaN: returning %d for 0x%08X%08X (format = %s)\n",boolean,WORD64HI(op),WORD64LO(op),DOFMT(fmt)); |
8bae0a0c JSC |
2505 | #endif /* DEBUG */ |
2506 | ||
2507 | return(boolean); | |
2508 | } | |
2509 | ||
2510 | static int | |
2511 | Infinity(op,fmt) | |
e871dd18 | 2512 | uword64 op; |
8bae0a0c JSC |
2513 | FP_formats fmt; |
2514 | { | |
2515 | int boolean = 0; | |
2516 | ||
2517 | #ifdef DEBUG | |
e871dd18 | 2518 | printf("DBG: Infinity: format %s 0x%08X%08X (PC = 0x%08X%08X)\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op),WORD64HI(IPC),WORD64LO(IPC)); |
8bae0a0c JSC |
2519 | #endif /* DEBUG */ |
2520 | ||
2521 | /* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We | |
2522 | know that the exponent field is biased... we we cheat and avoid | |
2523 | removing the bias value. */ | |
2524 | switch (fmt) { | |
2525 | case fmt_single: | |
2526 | boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) == 0)); | |
2527 | break; | |
2528 | case fmt_double: | |
2529 | boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) == 0)); | |
2530 | break; | |
2531 | default: | |
2532 | printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt)); | |
2533 | break; | |
2534 | } | |
2535 | ||
2536 | #ifdef DEBUG | |
e871dd18 | 2537 | printf("DBG: Infinity: returning %d for 0x%08X%08X (format = %s)\n",boolean,WORD64HI(op),WORD64LO(op),DOFMT(fmt)); |
8bae0a0c JSC |
2538 | #endif /* DEBUG */ |
2539 | ||
2540 | return(boolean); | |
2541 | } | |
2542 | ||
2543 | static int | |
2544 | Less(op1,op2,fmt) | |
e871dd18 JSC |
2545 | uword64 op1; |
2546 | uword64 op2; | |
8bae0a0c JSC |
2547 | FP_formats fmt; |
2548 | { | |
2549 | int boolean = 0; | |
2550 | ||
e871dd18 JSC |
2551 | /* Argument checking already performed by the FPCOMPARE code */ |
2552 | ||
8bae0a0c | 2553 | #ifdef DEBUG |
e871dd18 | 2554 | printf("DBG: Less: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2)); |
8bae0a0c JSC |
2555 | #endif /* DEBUG */ |
2556 | ||
8bae0a0c JSC |
2557 | /* The format type should already have been checked: */ |
2558 | switch (fmt) { | |
2559 | case fmt_single: | |
2560 | { | |
2561 | unsigned int wop1 = (unsigned int)op1; | |
2562 | unsigned int wop2 = (unsigned int)op2; | |
2563 | boolean = (*(float *)&wop1 < *(float *)&wop2); | |
2564 | } | |
2565 | break; | |
2566 | case fmt_double: | |
2567 | boolean = (*(double *)&op1 < *(double *)&op2); | |
2568 | break; | |
2569 | } | |
2570 | ||
2571 | #ifdef DEBUG | |
2572 | printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2573 | #endif /* DEBUG */ | |
2574 | ||
2575 | return(boolean); | |
2576 | } | |
2577 | ||
2578 | static int | |
2579 | Equal(op1,op2,fmt) | |
e871dd18 JSC |
2580 | uword64 op1; |
2581 | uword64 op2; | |
8bae0a0c JSC |
2582 | FP_formats fmt; |
2583 | { | |
2584 | int boolean = 0; | |
2585 | ||
e871dd18 JSC |
2586 | /* Argument checking already performed by the FPCOMPARE code */ |
2587 | ||
8bae0a0c | 2588 | #ifdef DEBUG |
e871dd18 | 2589 | printf("DBG: Equal: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2)); |
8bae0a0c JSC |
2590 | #endif /* DEBUG */ |
2591 | ||
8bae0a0c JSC |
2592 | /* The format type should already have been checked: */ |
2593 | switch (fmt) { | |
2594 | case fmt_single: | |
2595 | boolean = ((op1 & 0xFFFFFFFF) == (op2 & 0xFFFFFFFF)); | |
2596 | break; | |
2597 | case fmt_double: | |
2598 | boolean = (op1 == op2); | |
2599 | break; | |
2600 | } | |
2601 | ||
2602 | #ifdef DEBUG | |
2603 | printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2604 | #endif /* DEBUG */ | |
2605 | ||
2606 | return(boolean); | |
2607 | } | |
2608 | ||
e871dd18 | 2609 | static uword64 |
8bae0a0c | 2610 | Negate(op,fmt) |
e871dd18 | 2611 | uword64 op; |
8bae0a0c JSC |
2612 | FP_formats fmt; |
2613 | { | |
e871dd18 | 2614 | uword64 result; |
8bae0a0c JSC |
2615 | |
2616 | #ifdef DEBUG | |
e871dd18 | 2617 | printf("DBG: Negate: %s: op = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op)); |
8bae0a0c JSC |
2618 | #endif /* DEBUG */ |
2619 | ||
2620 | /* The format type should already have been checked: */ | |
2621 | switch (fmt) { | |
2622 | case fmt_single: | |
2623 | { | |
2624 | unsigned int wop = (unsigned int)op; | |
2625 | float tmp = ((float)0.0 - *(float *)&wop); | |
e871dd18 | 2626 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2627 | } |
2628 | break; | |
2629 | case fmt_double: | |
2630 | { | |
2631 | double tmp = ((double)0.0 - *(double *)&op); | |
e871dd18 | 2632 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2633 | } |
2634 | break; | |
2635 | } | |
2636 | ||
2637 | return(result); | |
2638 | } | |
2639 | ||
e871dd18 | 2640 | static uword64 |
8bae0a0c | 2641 | Add(op1,op2,fmt) |
e871dd18 JSC |
2642 | uword64 op1; |
2643 | uword64 op2; | |
8bae0a0c JSC |
2644 | FP_formats fmt; |
2645 | { | |
e871dd18 | 2646 | uword64 result; |
8bae0a0c JSC |
2647 | |
2648 | #ifdef DEBUG | |
e871dd18 | 2649 | printf("DBG: Add: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2)); |
8bae0a0c JSC |
2650 | #endif /* DEBUG */ |
2651 | ||
e871dd18 JSC |
2652 | /* The registers must specify FPRs valid for operands of type |
2653 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2654 | |
2655 | /* The format type should already have been checked: */ | |
2656 | switch (fmt) { | |
2657 | case fmt_single: | |
2658 | { | |
2659 | unsigned int wop1 = (unsigned int)op1; | |
2660 | unsigned int wop2 = (unsigned int)op2; | |
2661 | float tmp = (*(float *)&wop1 + *(float *)&wop2); | |
e871dd18 | 2662 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2663 | } |
2664 | break; | |
2665 | case fmt_double: | |
2666 | { | |
2667 | double tmp = (*(double *)&op1 + *(double *)&op2); | |
e871dd18 | 2668 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2669 | } |
2670 | break; | |
2671 | } | |
2672 | ||
2673 | #ifdef DEBUG | |
e871dd18 | 2674 | printf("DBG: Add: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt)); |
8bae0a0c JSC |
2675 | #endif /* DEBUG */ |
2676 | ||
2677 | return(result); | |
2678 | } | |
2679 | ||
e871dd18 | 2680 | static uword64 |
8bae0a0c | 2681 | Sub(op1,op2,fmt) |
e871dd18 JSC |
2682 | uword64 op1; |
2683 | uword64 op2; | |
8bae0a0c JSC |
2684 | FP_formats fmt; |
2685 | { | |
e871dd18 | 2686 | uword64 result; |
8bae0a0c JSC |
2687 | |
2688 | #ifdef DEBUG | |
e871dd18 | 2689 | printf("DBG: Sub: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64H(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2)); |
8bae0a0c JSC |
2690 | #endif /* DEBUG */ |
2691 | ||
e871dd18 JSC |
2692 | /* The registers must specify FPRs valid for operands of type |
2693 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2694 | |
2695 | /* The format type should already have been checked: */ | |
2696 | switch (fmt) { | |
2697 | case fmt_single: | |
2698 | { | |
2699 | unsigned int wop1 = (unsigned int)op1; | |
2700 | unsigned int wop2 = (unsigned int)op2; | |
2701 | float tmp = (*(float *)&wop1 - *(float *)&wop2); | |
e871dd18 | 2702 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2703 | } |
2704 | break; | |
2705 | case fmt_double: | |
2706 | { | |
2707 | double tmp = (*(double *)&op1 - *(double *)&op2); | |
e871dd18 | 2708 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2709 | } |
2710 | break; | |
2711 | } | |
2712 | ||
2713 | #ifdef DEBUG | |
e871dd18 | 2714 | printf("DBG: Sub: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt)); |
8bae0a0c JSC |
2715 | #endif /* DEBUG */ |
2716 | ||
2717 | return(result); | |
2718 | } | |
2719 | ||
e871dd18 | 2720 | static uword64 |
8bae0a0c | 2721 | Multiply(op1,op2,fmt) |
e871dd18 JSC |
2722 | uword64 op1; |
2723 | uword64 op2; | |
8bae0a0c JSC |
2724 | FP_formats fmt; |
2725 | { | |
e871dd18 | 2726 | uword64 result; |
8bae0a0c JSC |
2727 | |
2728 | #ifdef DEBUG | |
e871dd18 | 2729 | printf("DBG: Multiply: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2)); |
8bae0a0c JSC |
2730 | #endif /* DEBUG */ |
2731 | ||
e871dd18 JSC |
2732 | /* The registers must specify FPRs valid for operands of type |
2733 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2734 | |
2735 | /* The format type should already have been checked: */ | |
2736 | switch (fmt) { | |
2737 | case fmt_single: | |
2738 | { | |
2739 | unsigned int wop1 = (unsigned int)op1; | |
2740 | unsigned int wop2 = (unsigned int)op2; | |
2741 | float tmp = (*(float *)&wop1 * *(float *)&wop2); | |
e871dd18 | 2742 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2743 | } |
2744 | break; | |
2745 | case fmt_double: | |
2746 | { | |
2747 | double tmp = (*(double *)&op1 * *(double *)&op2); | |
e871dd18 | 2748 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2749 | } |
2750 | break; | |
2751 | } | |
2752 | ||
2753 | #ifdef DEBUG | |
e871dd18 | 2754 | printf("DBG: Multiply: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt)); |
8bae0a0c JSC |
2755 | #endif /* DEBUG */ |
2756 | ||
2757 | return(result); | |
2758 | } | |
2759 | ||
e871dd18 | 2760 | static uword64 |
8bae0a0c | 2761 | Divide(op1,op2,fmt) |
e871dd18 JSC |
2762 | uword64 op1; |
2763 | uword64 op2; | |
8bae0a0c JSC |
2764 | FP_formats fmt; |
2765 | { | |
e871dd18 | 2766 | uword64 result; |
8bae0a0c JSC |
2767 | |
2768 | #ifdef DEBUG | |
e871dd18 | 2769 | printf("DBG: Divide: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2)); |
8bae0a0c JSC |
2770 | #endif /* DEBUG */ |
2771 | ||
e871dd18 JSC |
2772 | /* The registers must specify FPRs valid for operands of type |
2773 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2774 | |
2775 | /* The format type should already have been checked: */ | |
2776 | switch (fmt) { | |
2777 | case fmt_single: | |
2778 | { | |
2779 | unsigned int wop1 = (unsigned int)op1; | |
2780 | unsigned int wop2 = (unsigned int)op2; | |
2781 | float tmp = (*(float *)&wop1 / *(float *)&wop2); | |
e871dd18 | 2782 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2783 | } |
2784 | break; | |
2785 | case fmt_double: | |
2786 | { | |
2787 | double tmp = (*(double *)&op1 / *(double *)&op2); | |
e871dd18 | 2788 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2789 | } |
2790 | break; | |
2791 | } | |
2792 | ||
2793 | #ifdef DEBUG | |
e871dd18 | 2794 | printf("DBG: Divide: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt)); |
8bae0a0c JSC |
2795 | #endif /* DEBUG */ |
2796 | ||
2797 | return(result); | |
2798 | } | |
2799 | ||
e871dd18 | 2800 | static uword64 |
8bae0a0c | 2801 | Recip(op,fmt) |
e871dd18 | 2802 | uword64 op; |
8bae0a0c JSC |
2803 | FP_formats fmt; |
2804 | { | |
e871dd18 | 2805 | uword64 result; |
8bae0a0c JSC |
2806 | |
2807 | #ifdef DEBUG | |
e871dd18 | 2808 | printf("DBG: Recip: %s: op = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op)); |
8bae0a0c JSC |
2809 | #endif /* DEBUG */ |
2810 | ||
e871dd18 JSC |
2811 | /* The registers must specify FPRs valid for operands of type |
2812 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2813 | |
2814 | /* The format type should already have been checked: */ | |
2815 | switch (fmt) { | |
2816 | case fmt_single: | |
2817 | { | |
2818 | unsigned int wop = (unsigned int)op; | |
2819 | float tmp = ((float)1.0 / *(float *)&wop); | |
e871dd18 | 2820 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2821 | } |
2822 | break; | |
2823 | case fmt_double: | |
2824 | { | |
2825 | double tmp = ((double)1.0 / *(double *)&op); | |
e871dd18 | 2826 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2827 | } |
2828 | break; | |
2829 | } | |
2830 | ||
2831 | #ifdef DEBUG | |
e871dd18 | 2832 | printf("DBG: Recip: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt)); |
8bae0a0c JSC |
2833 | #endif /* DEBUG */ |
2834 | ||
2835 | return(result); | |
2836 | } | |
2837 | ||
e871dd18 | 2838 | static uword64 |
8bae0a0c | 2839 | SquareRoot(op,fmt) |
e871dd18 | 2840 | uword64 op; |
8bae0a0c JSC |
2841 | FP_formats fmt; |
2842 | { | |
e871dd18 | 2843 | uword64 result; |
8bae0a0c JSC |
2844 | |
2845 | #ifdef DEBUG | |
e871dd18 | 2846 | printf("DBG: SquareRoot: %s: op = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op)); |
8bae0a0c JSC |
2847 | #endif /* DEBUG */ |
2848 | ||
e871dd18 JSC |
2849 | /* The registers must specify FPRs valid for operands of type |
2850 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2851 | |
2852 | /* The format type should already have been checked: */ | |
2853 | switch (fmt) { | |
2854 | case fmt_single: | |
2855 | { | |
2856 | unsigned int wop = (unsigned int)op; | |
2857 | float tmp = ((float)sqrt((double)*(float *)&wop)); | |
e871dd18 | 2858 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2859 | } |
2860 | break; | |
2861 | case fmt_double: | |
2862 | { | |
2863 | double tmp = (sqrt(*(double *)&op)); | |
e871dd18 | 2864 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2865 | } |
2866 | break; | |
2867 | } | |
2868 | ||
2869 | #ifdef DEBUG | |
e871dd18 | 2870 | printf("DBG: SquareRoot: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt)); |
8bae0a0c JSC |
2871 | #endif /* DEBUG */ |
2872 | ||
2873 | return(result); | |
2874 | } | |
2875 | ||
e871dd18 | 2876 | static uword64 |
8bae0a0c JSC |
2877 | Convert(rm,op,from,to) |
2878 | int rm; | |
e871dd18 | 2879 | uword64 op; |
8bae0a0c JSC |
2880 | FP_formats from; |
2881 | FP_formats to; | |
2882 | { | |
e871dd18 | 2883 | uword64 result; |
8bae0a0c JSC |
2884 | |
2885 | #ifdef DEBUG | |
e871dd18 | 2886 | printf("DBG: Convert: mode %s : op 0x%08X%08X : from %s : to %s : (PC = 0x%08X%08X)\n",RMMODE(rm),WORD64HI(op),WORD64LO(op),DOFMT(from),DOFMT(to),WORD64HI(IPC),WORD64LO(IPC)); |
8bae0a0c JSC |
2887 | #endif /* DEBUG */ |
2888 | ||
2889 | /* The value "op" is converted to the destination format, rounding | |
2890 | using mode "rm". When the destination is a fixed-point format, | |
2891 | then a source value of Infinity, NaN or one which would round to | |
2892 | an integer outside the fixed point range then an IEEE Invalid | |
2893 | Operation condition is raised. */ | |
2894 | switch (to) { | |
2895 | case fmt_single: | |
2896 | { | |
2897 | float tmp; | |
2898 | switch (from) { | |
2899 | case fmt_double: | |
2900 | tmp = (float)(*(double *)&op); | |
2901 | break; | |
2902 | ||
2903 | case fmt_word: | |
2904 | tmp = (float)((int)(op & 0xFFFFFFFF)); | |
2905 | break; | |
2906 | ||
2907 | case fmt_long: | |
2908 | tmp = (float)((int)op); | |
2909 | break; | |
2910 | } | |
2911 | ||
2912 | switch (rm) { | |
2913 | case FP_RM_NEAREST: | |
e871dd18 JSC |
2914 | /* Round result to nearest representable value. When two |
2915 | representable values are equally near, round to the value | |
2916 | that has a least significant bit of zero (i.e. is even). */ | |
d0757082 | 2917 | #if defined(sun) |
e871dd18 | 2918 | tmp = (float)anint((double)tmp); |
d0757082 JSC |
2919 | #else |
2920 | /* TODO: Provide round-to-nearest */ | |
2921 | #endif | |
8bae0a0c JSC |
2922 | break; |
2923 | ||
2924 | case FP_RM_TOZERO: | |
e871dd18 JSC |
2925 | /* Round result to the value closest to, and not greater in |
2926 | magnitude than, the result. */ | |
d0757082 | 2927 | #if defined(sun) |
e871dd18 | 2928 | tmp = (float)aint((double)tmp); |
d0757082 JSC |
2929 | #else |
2930 | /* TODO: Provide round-to-zero */ | |
2931 | #endif | |
8bae0a0c JSC |
2932 | break; |
2933 | ||
2934 | case FP_RM_TOPINF: | |
e871dd18 JSC |
2935 | /* Round result to the value closest to, and not less than, |
2936 | the result. */ | |
2937 | tmp = (float)ceil((double)tmp); | |
8bae0a0c JSC |
2938 | break; |
2939 | ||
2940 | case FP_RM_TOMINF: | |
e871dd18 JSC |
2941 | /* Round result to the value closest to, and not greater than, |
2942 | the result. */ | |
2943 | tmp = (float)floor((double)tmp); | |
8bae0a0c JSC |
2944 | break; |
2945 | } | |
e871dd18 | 2946 | result = (uword64)*(unsigned int *)&tmp; |
8bae0a0c JSC |
2947 | } |
2948 | break; | |
2949 | ||
2950 | case fmt_double: | |
2951 | { | |
2952 | double tmp; | |
2953 | ||
2954 | switch (from) { | |
2955 | case fmt_single: | |
2956 | { | |
2957 | unsigned int wop = (unsigned int)op; | |
2958 | tmp = (double)(*(float *)&wop); | |
2959 | } | |
2960 | break; | |
2961 | ||
2962 | case fmt_word: | |
e871dd18 | 2963 | tmp = (double)((word64)SIGNEXTEND((op & 0xFFFFFFFF),32)); |
8bae0a0c JSC |
2964 | break; |
2965 | ||
2966 | case fmt_long: | |
e871dd18 | 2967 | tmp = (double)((word64)op); |
8bae0a0c JSC |
2968 | break; |
2969 | } | |
e871dd18 | 2970 | |
8bae0a0c JSC |
2971 | switch (rm) { |
2972 | case FP_RM_NEAREST: | |
d0757082 | 2973 | #if defined(sun) |
e871dd18 | 2974 | tmp = anint(*(double *)&tmp); |
d0757082 JSC |
2975 | #else |
2976 | /* TODO: Provide round-to-nearest */ | |
2977 | #endif | |
8bae0a0c JSC |
2978 | break; |
2979 | ||
2980 | case FP_RM_TOZERO: | |
d0757082 | 2981 | #if defined(sun) |
e871dd18 | 2982 | tmp = aint(*(double *)&tmp); |
d0757082 JSC |
2983 | #else |
2984 | /* TODO: Provide round-to-zero */ | |
2985 | #endif | |
8bae0a0c JSC |
2986 | break; |
2987 | ||
2988 | case FP_RM_TOPINF: | |
2989 | tmp = ceil(*(double *)&tmp); | |
2990 | break; | |
2991 | ||
2992 | case FP_RM_TOMINF: | |
2993 | tmp = floor(*(double *)&tmp); | |
2994 | break; | |
2995 | } | |
e871dd18 | 2996 | result = *(uword64 *)&tmp; |
8bae0a0c JSC |
2997 | } |
2998 | break; | |
2999 | ||
3000 | case fmt_word: | |
3001 | case fmt_long: | |
3002 | if (Infinity(op,from) || NaN(op,from) || (1 == 0/*TODO: check range */)) { | |
3003 | printf("DBG: TODO: update FCSR\n"); | |
3004 | SignalException(FPE); | |
3005 | } else { | |
3006 | if (to == fmt_word) { | |
3007 | unsigned int tmp; | |
3008 | switch (from) { | |
3009 | case fmt_single: | |
3010 | { | |
3011 | unsigned int wop = (unsigned int)op; | |
3012 | tmp = (unsigned int)*((float *)&wop); | |
3013 | } | |
3014 | break; | |
3015 | case fmt_double: | |
3016 | tmp = (unsigned int)*((double *)&op); | |
3017 | #ifdef DEBUG | |
e871dd18 | 3018 | printf("DBG: from double %.30f (0x%08X%08X) to word: 0x%08X\n",*((double *)&op),WORD64HI(op),WORD64LO(op),tmp); |
8bae0a0c JSC |
3019 | #endif /* DEBUG */ |
3020 | break; | |
3021 | } | |
e871dd18 | 3022 | result = (uword64)tmp; |
8bae0a0c JSC |
3023 | } else { /* fmt_long */ |
3024 | switch (from) { | |
3025 | case fmt_single: | |
3026 | { | |
3027 | unsigned int wop = (unsigned int)op; | |
e871dd18 | 3028 | result = (uword64)*((float *)&wop); |
8bae0a0c JSC |
3029 | } |
3030 | break; | |
3031 | case fmt_double: | |
e871dd18 | 3032 | result = (uword64)*((double *)&op); |
8bae0a0c JSC |
3033 | break; |
3034 | } | |
3035 | } | |
3036 | } | |
3037 | break; | |
3038 | } | |
3039 | ||
3040 | #ifdef DEBUG | |
e871dd18 | 3041 | printf("DBG: Convert: returning 0x%08X%08X (to format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(to)); |
8bae0a0c JSC |
3042 | #endif /* DEBUG */ |
3043 | ||
3044 | return(result); | |
3045 | } | |
3046 | #endif /* HASFPU */ | |
3047 | ||
3048 | /*-- co-processor support routines ------------------------------------------*/ | |
3049 | ||
3050 | static int | |
3051 | CoProcPresent(coproc_number) | |
3052 | unsigned int coproc_number; | |
3053 | { | |
3054 | /* Return TRUE if simulator provides a model for the given co-processor number */ | |
3055 | return(0); | |
3056 | } | |
3057 | ||
3058 | static void | |
3059 | COP_LW(coproc_num,coproc_reg,memword) | |
3060 | int coproc_num, coproc_reg; | |
3061 | unsigned int memword; | |
3062 | { | |
3063 | switch (coproc_num) { | |
3064 | #if defined(HASFPU) | |
3065 | case 1: | |
3066 | #ifdef DEBUG | |
e871dd18 | 3067 | printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%08X%08X\n",memword,WORD64HI(memword),WORD64LO(memword)); |
8bae0a0c | 3068 | #endif |
e871dd18 | 3069 | StoreFPR(coproc_reg,fmt_uninterpreted,(uword64)memword); |
8bae0a0c JSC |
3070 | break; |
3071 | #endif /* HASFPU */ | |
3072 | ||
3073 | default: | |
e871dd18 | 3074 | callback->printf_filtered(callback,"COP_LW(%d,%d,0x%08X) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,WORD64HI(IPC),WORD64LO(IPC)); |
8bae0a0c JSC |
3075 | break; |
3076 | } | |
3077 | ||
3078 | return; | |
3079 | } | |
3080 | ||
3081 | static void | |
3082 | COP_LD(coproc_num,coproc_reg,memword) | |
3083 | int coproc_num, coproc_reg; | |
e871dd18 | 3084 | uword64 memword; |
8bae0a0c JSC |
3085 | { |
3086 | switch (coproc_num) { | |
3087 | #if defined(HASFPU) | |
3088 | case 1: | |
3089 | StoreFPR(coproc_reg,fmt_uninterpreted,memword); | |
3090 | break; | |
3091 | #endif /* HASFPU */ | |
3092 | ||
3093 | default: | |
e871dd18 | 3094 | callback->printf_filtered(callback,"COP_LD(%d,%d,0x%08X%08X) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,WORD64HI(memword),WORD64LO(memword),WORD64HI(IPC),WORD64LO(IPC)); |
8bae0a0c JSC |
3095 | break; |
3096 | } | |
3097 | ||
3098 | return; | |
3099 | } | |
3100 | ||
3101 | static unsigned int | |
3102 | COP_SW(coproc_num,coproc_reg) | |
3103 | int coproc_num, coproc_reg; | |
3104 | { | |
3105 | unsigned int value = 0; | |
3106 | switch (coproc_num) { | |
3107 | #if defined(HASFPU) | |
3108 | case 1: | |
3109 | #if 1 | |
3110 | value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted); | |
3111 | #else | |
3112 | #if 1 | |
3113 | value = (unsigned int)ValueFPR(coproc_reg,fpr_state[coproc_reg]); | |
3114 | #else | |
3115 | #ifdef DEBUG | |
3116 | printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(fpr_state[coproc_reg])); | |
3117 | #endif /* DEBUG */ | |
3118 | value = (unsigned int)ValueFPR(coproc_reg,fmt_single); | |
3119 | #endif | |
3120 | #endif | |
3121 | break; | |
3122 | #endif /* HASFPU */ | |
3123 | ||
3124 | default: | |
e871dd18 | 3125 | callback->printf_filtered(callback,"COP_SW(%d,%d) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,WORD64HI(IPC),WORD64LO(IPC)); |
8bae0a0c JSC |
3126 | break; |
3127 | } | |
3128 | ||
3129 | return(value); | |
3130 | } | |
3131 | ||
e871dd18 | 3132 | static uword64 |
8bae0a0c JSC |
3133 | COP_SD(coproc_num,coproc_reg) |
3134 | int coproc_num, coproc_reg; | |
3135 | { | |
e871dd18 | 3136 | uword64 value = 0; |
8bae0a0c JSC |
3137 | switch (coproc_num) { |
3138 | #if defined(HASFPU) | |
3139 | case 1: | |
3140 | #if 1 | |
3141 | value = ValueFPR(coproc_reg,fmt_uninterpreted); | |
3142 | #else | |
3143 | #if 1 | |
3144 | value = ValueFPR(coproc_reg,fpr_state[coproc_reg]); | |
3145 | #else | |
3146 | #ifdef DEBUG | |
3147 | printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(fpr_state[coproc_reg])); | |
3148 | #endif /* DEBUG */ | |
3149 | value = ValueFPR(coproc_reg,fmt_double); | |
3150 | #endif | |
3151 | #endif | |
3152 | break; | |
3153 | #endif /* HASFPU */ | |
3154 | ||
3155 | default: | |
e871dd18 | 3156 | callback->printf_filtered(callback,"COP_SD(%d,%d) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,WORD64HI(IPC),WORD64LO(IPC)); |
8bae0a0c JSC |
3157 | break; |
3158 | } | |
3159 | ||
3160 | return(value); | |
3161 | } | |
3162 | ||
3163 | static void | |
3164 | decode_coproc(instruction) | |
3165 | unsigned int instruction; | |
3166 | { | |
3167 | int coprocnum = ((instruction >> 26) & 3); | |
3168 | ||
3169 | switch (coprocnum) { | |
3170 | case 0: /* standard CPU control and cache registers */ | |
3171 | { | |
3172 | /* NOTEs: | |
3173 | Standard CP0 registers | |
3174 | 0 = Index R4000 VR4100 VR4300 | |
3175 | 1 = Random R4000 VR4100 VR4300 | |
3176 | 2 = EntryLo0 R4000 VR4100 VR4300 | |
3177 | 3 = EntryLo1 R4000 VR4100 VR4300 | |
3178 | 4 = Context R4000 VR4100 VR4300 | |
3179 | 5 = PageMask R4000 VR4100 VR4300 | |
3180 | 6 = Wired R4000 VR4100 VR4300 | |
3181 | 8 = BadVAddr R4000 VR4100 VR4300 | |
3182 | 9 = Count R4000 VR4100 VR4300 | |
3183 | 10 = EntryHi R4000 VR4100 VR4300 | |
3184 | 11 = Compare R4000 VR4100 VR4300 | |
3185 | 12 = SR R4000 VR4100 VR4300 | |
3186 | 13 = Cause R4000 VR4100 VR4300 | |
3187 | 14 = EPC R4000 VR4100 VR4300 | |
3188 | 15 = PRId R4000 VR4100 VR4300 | |
3189 | 16 = Config R4000 VR4100 VR4300 | |
3190 | 17 = LLAddr R4000 VR4100 VR4300 | |
3191 | 18 = WatchLo R4000 VR4100 VR4300 | |
3192 | 19 = WatchHi R4000 VR4100 VR4300 | |
3193 | 20 = XContext R4000 VR4100 VR4300 | |
3194 | 26 = PErr or ECC R4000 VR4100 VR4300 | |
3195 | 27 = CacheErr R4000 VR4100 | |
3196 | 28 = TagLo R4000 VR4100 VR4300 | |
3197 | 29 = TagHi R4000 VR4100 VR4300 | |
3198 | 30 = ErrorEPC R4000 VR4100 VR4300 | |
3199 | */ | |
3200 | int code = ((instruction >> 21) & 0x1F); | |
3201 | /* R4000 Users Manual (second edition) lists the following CP0 | |
3202 | instructions: | |
3203 | DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000) | |
3204 | DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000) | |
3205 | MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000) | |
3206 | MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000) | |
3207 | TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001) | |
3208 | TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010) | |
3209 | TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110) | |
3210 | TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000) | |
3211 | CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii) | |
3212 | ERET Exception return (VR4100 = 01000010000000000000000000011000) | |
3213 | */ | |
3214 | if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0)) { | |
3215 | int rt = ((instruction >> 16) & 0x1F); | |
3216 | int rd = ((instruction >> 11) & 0x1F); | |
3217 | if (code == 0x00) { /* MF : move from */ | |
3218 | callback->printf_filtered(callback,"Warning: MFC0 %d,%d not handled yet (architecture specific)\n",rt,rd); | |
3219 | GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */ | |
3220 | } else { /* MT : move to */ | |
3221 | /* CPR[0,rd] = GPR[rt]; */ | |
3222 | callback->printf_filtered(callback,"Warning: MTC0 %d,%d not handled yet (architecture specific)\n",rt,rd); | |
3223 | } | |
3224 | } else | |
e871dd18 JSC |
3225 | callback->printf_filtered(callback,"Warning: Unrecognised COP0 instruction 0x%08X at IPC = 0x%08X%08X : No handler present\n",instruction,WORD64HI(IPC),WORD64LO(IPC)); |
3226 | /* TODO: When executing an ERET or RFE instruction we should | |
8bae0a0c JSC |
3227 | clear LLBIT, to ensure that any out-standing atomic |
3228 | read/modify/write sequence fails. */ | |
3229 | } | |
3230 | break; | |
3231 | ||
3232 | case 2: /* undefined co-processor */ | |
e871dd18 | 3233 | callback->printf_filtered(callback,"Warning: COP2 instruction 0x%08X at IPC = 0x%08X%08X : No handler present\n",instruction,WORD64HI(IPC),WORD64LO(IPC)); |
8bae0a0c JSC |
3234 | break; |
3235 | ||
3236 | case 1: /* should not occur (FPU co-processor) */ | |
3237 | case 3: /* should not occur (FPU co-processor) */ | |
3238 | SignalException(ReservedInstruction,instruction); | |
3239 | break; | |
3240 | } | |
3241 | ||
3242 | return; | |
3243 | } | |
3244 | ||
3245 | /*-- instruction simulation -------------------------------------------------*/ | |
3246 | ||
3247 | static void | |
3248 | simulate () | |
3249 | { | |
3250 | unsigned int pipeline_count = 1; | |
3251 | ||
3252 | #ifdef DEBUG | |
3253 | if (membank == NULL) { | |
3254 | printf("DBG: simulate() entered with no memory\n"); | |
3255 | exit(1); | |
3256 | } | |
3257 | #endif /* DEBUG */ | |
3258 | ||
3259 | #if 0 /* Disabled to check that everything works OK */ | |
3260 | /* The VR4300 seems to sign-extend the PC on its first | |
3261 | access. However, this may just be because it is currently | |
3262 | configured in 32bit mode. However... */ | |
3263 | PC = SIGNEXTEND(PC,32); | |
3264 | #endif | |
3265 | ||
3266 | /* main controlling loop */ | |
3267 | do { | |
3268 | /* Fetch the next instruction from the simulator memory: */ | |
e871dd18 JSC |
3269 | uword64 vaddr = (uword64)PC; |
3270 | uword64 paddr; | |
8bae0a0c JSC |
3271 | int cca; |
3272 | unsigned int instruction; | |
3273 | int dsstate = (state & simDELAYSLOT); | |
3274 | ||
3275 | #ifdef DEBUG | |
3276 | { | |
3277 | printf("DBG: state = 0x%08X :",state); | |
3278 | if (state & simSTOP) printf(" simSTOP"); | |
3279 | if (state & simSTEP) printf(" simSTEP"); | |
3280 | if (state & simHALTEX) printf(" simHALTEX"); | |
3281 | if (state & simHALTIN) printf(" simHALTIN"); | |
3282 | if (state & simBE) printf(" simBE"); | |
3283 | } | |
3284 | #endif /* DEBUG */ | |
3285 | ||
3286 | #ifdef DEBUG | |
3287 | if (dsstate) | |
e871dd18 | 3288 | callback->printf_filtered(callback,"DBG: DSPC = 0x%08X%08X\n",WORD64HI(DSPC),WORD64LO(DSPC)); |
8bae0a0c JSC |
3289 | #endif /* DEBUG */ |
3290 | ||
3291 | if (AddressTranslation(PC,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { /* Copy the action of the LW instruction */ | |
3292 | unsigned int reverse = (ReverseEndian ? 1 : 0); | |
3293 | unsigned int bigend = (BigEndianCPU ? 1 : 0); | |
e871dd18 | 3294 | uword64 value; |
8bae0a0c JSC |
3295 | unsigned int byte; |
3296 | paddr = ((paddr & ~0x7) | ((paddr & 0x7) ^ (reverse << 2))); | |
3297 | value = LoadMemory(cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL); | |
3298 | byte = ((vaddr & 0x7) ^ (bigend << 2)); | |
3299 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
3300 | } else { | |
e871dd18 | 3301 | fprintf(stderr,"Cannot translate address for PC = 0x%08X%08X failed\n",WORD64HI(PC),WORD64LO(PC)); |
8bae0a0c JSC |
3302 | exit(1); |
3303 | } | |
3304 | ||
3305 | #ifdef DEBUG | |
e871dd18 | 3306 | callback->printf_filtered(callback,"DBG: fetched 0x%08X from PC = 0x%08X%08X\n",instruction,WORD64HI(PC),WORD64LO(PC)); |
8bae0a0c JSC |
3307 | #endif /* DEBUG */ |
3308 | ||
3309 | #if !defined(FASTSIM) || defined(PROFILE) | |
3310 | instruction_fetches++; | |
3311 | #if defined(PROFILE) | |
3312 | if ((state & simPROFILE) && ((instruction_fetches % profile_frequency) == 0) && profile_hist) { | |
3313 | int n = ((unsigned int)(PC - profile_minpc) >> (profile_shift + 2)); | |
3314 | if (n < profile_nsamples) { | |
3315 | /* NOTE: The counts for the profiling bins are only 16bits wide */ | |
3316 | if (profile_hist[n] != USHRT_MAX) | |
3317 | (profile_hist[n])++; | |
3318 | } | |
3319 | } | |
3320 | #endif /* PROFILE */ | |
3321 | #endif /* !FASTSIM && PROFILE */ | |
3322 | ||
3323 | IPC = PC; /* copy PC for this instruction */ | |
3324 | /* This is required by exception processing, to ensure that we can | |
3325 | cope with exceptions in the delay slots of branches that may | |
3326 | already have changed the PC. */ | |
3327 | PC += 4; /* increment ready for the next fetch */ | |
3328 | /* NOTE: If we perform a delay slot change to the PC, this | |
3329 | increment is not requuired. However, it would make the | |
3330 | simulator more complicated to try and avoid this small hit. */ | |
3331 | ||
3332 | /* Currently this code provides a simple model. For more | |
3333 | complicated models we could perform exception status checks at | |
3334 | this point, and set the simSTOP state as required. This could | |
3335 | also include processing any hardware interrupts raised by any | |
3336 | I/O model attached to the simulator context. | |
3337 | ||
3338 | Support for "asynchronous" I/O events within the simulated world | |
3339 | could be providing by managing a counter, and calling a I/O | |
3340 | specific handler when a particular threshold is reached. On most | |
3341 | architectures a decrement and check for zero operation is | |
3342 | usually quicker than an increment and compare. However, the | |
3343 | process of managing a known value decrement to zero, is higher | |
3344 | than the cost of using an explicit value UINT_MAX into the | |
3345 | future. Which system is used will depend on how complicated the | |
3346 | I/O model is, and how much it is likely to affect the simulator | |
3347 | bandwidth. | |
3348 | ||
3349 | If events need to be scheduled further in the future than | |
3350 | UINT_MAX event ticks, then the I/O model should just provide its | |
3351 | own counter, triggered from the event system. */ | |
3352 | ||
3353 | /* MIPS pipeline ticks. To allow for future support where the | |
3354 | pipeline hit of individual instructions is known, this control | |
3355 | loop manages a "pipeline_count" variable. It is initialised to | |
3356 | 1 (one), and will only be changed by the simulator engine when | |
3357 | executing an instruction. If the engine does not have access to | |
3358 | pipeline cycle count information then all instructions will be | |
3359 | treated as using a single cycle. NOTE: A standard system is not | |
3360 | provided by the default simulator because different MIPS | |
3361 | architectures have different cycle counts for the same | |
3362 | instructions. */ | |
3363 | ||
3364 | #if defined(HASFPU) | |
3365 | /* Set previous flag, depending on current: */ | |
3366 | if (state & simPCOC0) | |
3367 | state |= simPCOC1; | |
3368 | else | |
3369 | state &= ~simPCOC1; | |
3370 | /* and update the current value: */ | |
3371 | if (GETFCC(0)) | |
3372 | state |= simPCOC0; | |
3373 | else | |
3374 | state &= ~simPCOC0; | |
3375 | #endif /* HASFPU */ | |
3376 | ||
3377 | /* NOTE: For multi-context simulation environments the "instruction" | |
3378 | variable should be local to this routine. */ | |
3379 | ||
3380 | /* Shorthand accesses for engine. Note: If we wanted to use global | |
3381 | variables (and a single-threaded simulator engine), then we can | |
3382 | create the actual variables with these names. */ | |
3383 | ||
3384 | if (!(state & simSKIPNEXT)) { | |
3385 | /* Include the simulator engine */ | |
3386 | #include "engine.c" | |
3387 | #if ((GPRLEN == 64) && !defined(PROCESSOR_64BIT)) || ((GPRLEN == 32) && defined(PROCESSOR_64BIT)) | |
3388 | #error "Mismatch between run-time simulator code and simulation engine" | |
3389 | #endif | |
3390 | ||
3391 | #if defined(WARN_LOHI) | |
3392 | /* Decrement the HI/LO validity ticks */ | |
3393 | if (HIACCESS > 0) | |
3394 | HIACCESS--; | |
3395 | if (LOACCESS > 0) | |
3396 | LOACCESS--; | |
3397 | #endif /* WARN_LOHI */ | |
3398 | ||
3399 | #if defined(WARN_ZERO) | |
3400 | /* For certain MIPS architectures, GPR[0] is hardwired to zero. We | |
3401 | should check for it being changed. It is better doing it here, | |
3402 | than within the simulator, since it will help keep the simulator | |
3403 | small. */ | |
3404 | if (ZERO != 0) { | |
e871dd18 | 3405 | callback->printf_filtered(callback,"SIM Warning: The ZERO register has been updated with 0x%08X%08X (PC = 0x%08X%08X)\nSIM Warning: Resetting back to zero\n",WORD64HI(ZERO),WORD64LO(ZERO),WORD64HI(IPC),WORD64LO(IPC)); |
8bae0a0c JSC |
3406 | ZERO = 0; /* reset back to zero before next instruction */ |
3407 | } | |
3408 | #endif /* WARN_ZERO */ | |
3409 | } else /* simSKIPNEXT check */ | |
3410 | state &= ~simSKIPNEXT; | |
3411 | ||
3412 | /* If the delay slot was active before the instruction is | |
3413 | executed, then update the PC to its new value: */ | |
3414 | if (dsstate) { | |
3415 | #ifdef DEBUG | |
e871dd18 | 3416 | printf("DBG: dsstate set before instruction execution - updating PC to 0x%08X%08X\n",WORD64HI(DSPC),WORD64LO(DSPC)); |
8bae0a0c JSC |
3417 | #endif /* DEBUG */ |
3418 | PC = DSPC; | |
3419 | state &= ~simDELAYSLOT; | |
3420 | } | |
3421 | ||
3422 | if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */ | |
3423 | /* Deal with pending register updates: */ | |
3424 | #ifdef DEBUG | |
3425 | printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total); | |
3426 | #endif /* DEBUG */ | |
3427 | if (pending_out != pending_in) { | |
3428 | int loop; | |
3429 | int index = pending_out; | |
3430 | int total = pending_total; | |
3431 | if (pending_total == 0) { | |
3432 | fprintf(stderr,"FATAL: Mis-match on pending update pointers\n"); | |
3433 | exit(1); | |
3434 | } | |
3435 | for (loop = 0; (loop < total); loop++) { | |
3436 | #ifdef DEBUG | |
3437 | printf("DBG: BEFORE index = %d, loop = %d\n",index,loop); | |
3438 | #endif /* DEBUG */ | |
3439 | if (pending_slot_reg[index] != (LAST_EMBED_REGNUM + 1)) { | |
3440 | #ifdef DEBUG | |
3441 | printf("pending_slot_count[%d] = %d\n",index,pending_slot_count[index]); | |
3442 | #endif /* DEBUG */ | |
3443 | if (--(pending_slot_count[index]) == 0) { | |
3444 | #ifdef DEBUG | |
3445 | printf("pending_slot_reg[%d] = %d\n",index,pending_slot_reg[index]); | |
e871dd18 | 3446 | printf("pending_slot_value[%d] = 0x%08X%08X\n",index,WORD64HI(pending_slot_value[index]),WORD64LO(pending_slot_value[index])); |
8bae0a0c JSC |
3447 | #endif /* DEBUG */ |
3448 | if (pending_slot_reg[index] == COCIDX) { | |
3449 | SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0)); | |
3450 | } else { | |
3451 | registers[pending_slot_reg[index]] = pending_slot_value[index]; | |
3452 | #if defined(HASFPU) | |
3453 | /* The only time we have PENDING updates to FPU | |
3454 | registers, is when performing binary transfers. This | |
3455 | means we should update the register type field. */ | |
3456 | if ((pending_slot_reg[index] >= FGRIDX) && (pending_slot_reg[index] < (FGRIDX + 32))) | |
3457 | fpr_state[pending_slot_reg[index]] = fmt_uninterpreted; | |
3458 | #endif /* HASFPU */ | |
3459 | } | |
3460 | #ifdef DEBUG | |
e871dd18 | 3461 | printf("registers[%d] = 0x%08X%08X\n",pending_slot_reg[index],WORD64HI(registers[pending_slot_reg[index]]),WORD64LO(registers[pending_slot_reg[index]])); |
8bae0a0c JSC |
3462 | #endif /* DEBUG */ |
3463 | pending_slot_reg[index] = (LAST_EMBED_REGNUM + 1); | |
3464 | pending_out++; | |
3465 | if (pending_out == PSLOTS) | |
3466 | pending_out = 0; | |
3467 | pending_total--; | |
3468 | } | |
3469 | } | |
3470 | #ifdef DEBUG | |
3471 | printf("DBG: AFTER index = %d, loop = %d\n",index,loop); | |
3472 | #endif /* DEBUG */ | |
3473 | index++; | |
3474 | if (index == PSLOTS) | |
3475 | index = 0; | |
3476 | } | |
3477 | } | |
3478 | #ifdef DEBUG | |
3479 | printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total); | |
3480 | #endif /* DEBUG */ | |
3481 | } | |
3482 | ||
3483 | #if !defined(FASTSIM) | |
3484 | pipeline_ticks += pipeline_count; | |
3485 | #endif /* FASTSIM */ | |
3486 | ||
3487 | if (state & simSTEP) | |
3488 | state |= simSTOP; | |
3489 | } while (!(state & simSTOP)); | |
3490 | ||
3491 | #ifdef DEBUG | |
3492 | if (membank == NULL) { | |
3493 | printf("DBG: simulate() LEAVING with no memory\n"); | |
3494 | exit(1); | |
3495 | } | |
3496 | #endif /* DEBUG */ | |
3497 | ||
3498 | return; | |
3499 | } | |
3500 | ||
3501 | /*---------------------------------------------------------------------------*/ | |
3502 | /*> EOF interp.c <*/ |