Commit | Line | Data |
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8bae0a0c JSC |
1 | /*> interp.c <*/ |
2 | /* Simulator for the MIPS architecture. | |
3 | ||
4 | This file is part of the MIPS sim | |
5 | ||
6 | THIS SOFTWARE IS NOT COPYRIGHTED | |
7 | ||
8 | Cygnus offers the following for use in the public domain. Cygnus | |
9 | makes no warranty with regard to the software or it's performance | |
10 | and the user accepts the software "AS IS" with all faults. | |
11 | ||
12 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
13 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
14 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
15 | ||
16 | $Revision$ | |
17 | $Author$ | |
e3d12c65 | 18 | $Date$ |
8bae0a0c JSC |
19 | |
20 | NOTEs: | |
21 | ||
8bae0a0c JSC |
22 | The IDT monitor (found on the VR4300 board), seems to lie about |
23 | register contents. It seems to treat the registers as sign-extended | |
24 | 32-bit values. This cause *REAL* problems when single-stepping 64-bit | |
25 | code on the hardware. | |
26 | ||
27 | */ | |
28 | ||
e2f8ffb7 AC |
29 | /* The TRACE manifests enable the provision of extra features. If they |
30 | are not defined then a simpler (quicker) simulator is constructed | |
31 | without the required run-time checks, etc. */ | |
8bae0a0c JSC |
32 | #if 1 /* 0 to allow user build selection, 1 to force inclusion */ |
33 | #define TRACE (1) | |
8bae0a0c JSC |
34 | #endif |
35 | ||
2e61a3ad AC |
36 | #include "bfd.h" |
37 | #include "sim-main.h" | |
38 | #include "sim-utils.h" | |
39 | #include "sim-options.h" | |
50a2a691 | 40 | #include "sim-assert.h" |
2e61a3ad | 41 | |
4fa134be ILT |
42 | #include "config.h" |
43 | ||
8bae0a0c JSC |
44 | #include <stdio.h> |
45 | #include <stdarg.h> | |
46 | #include <ansidecl.h> | |
8bae0a0c JSC |
47 | #include <ctype.h> |
48 | #include <limits.h> | |
49 | #include <math.h> | |
4fa134be ILT |
50 | #ifdef HAVE_STDLIB_H |
51 | #include <stdlib.h> | |
52 | #endif | |
53 | #ifdef HAVE_STRING_H | |
54 | #include <string.h> | |
55 | #else | |
56 | #ifdef HAVE_STRINGS_H | |
57 | #include <strings.h> | |
58 | #endif | |
59 | #endif | |
8bae0a0c JSC |
60 | |
61 | #include "getopt.h" | |
62 | #include "libiberty.h" | |
9d52bcb7 | 63 | #include "bfd.h" |
8bae0a0c | 64 | #include "callback.h" /* GDB simulator callback interface */ |
e3d12c65 | 65 | #include "remote-sim.h" /* GDB simulator interface */ |
8bae0a0c | 66 | |
f24b7b69 JSC |
67 | #include "sysdep.h" |
68 | ||
53b9417e DE |
69 | #ifndef PARAMS |
70 | #define PARAMS(x) | |
71 | #endif | |
72 | ||
73 | char* pr_addr PARAMS ((SIM_ADDR addr)); | |
87e43259 | 74 | char* pr_uword64 PARAMS ((uword64 addr)); |
53b9417e | 75 | |
f24b7b69 | 76 | |
8bae0a0c JSC |
77 | /* Get the simulator engine description, without including the code: */ |
78 | #define SIM_MANIFESTS | |
284e759d | 79 | #include "oengine.c" |
8bae0a0c JSC |
80 | #undef SIM_MANIFESTS |
81 | ||
01737f42 AC |
82 | /* Within interp.c we refer to the sim_state and sim_cpu directly. */ |
83 | #define SD sd | |
84 | #define CPU cpu | |
85 | ||
f7481d45 | 86 | |
8bae0a0c JSC |
87 | /* The following reserved instruction value is used when a simulator |
88 | trap is required. NOTE: Care must be taken, since this value may be | |
89 | used in later revisions of the MIPS ISA. */ | |
53b9417e DE |
90 | #define RSVD_INSTRUCTION (0x00000005) |
91 | #define RSVD_INSTRUCTION_MASK (0xFC00003F) | |
92 | ||
93 | #define RSVD_INSTRUCTION_ARG_SHIFT 6 | |
94 | #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF | |
95 | ||
8bae0a0c | 96 | |
6eedf3f4 MA |
97 | /* Bits in the Debug register */ |
98 | #define Debug_DBD 0x80000000 /* Debug Branch Delay */ | |
99 | #define Debug_DM 0x40000000 /* Debug Mode */ | |
100 | #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */ | |
101 | ||
102 | ||
103 | ||
8bae0a0c | 104 | |
8bae0a0c | 105 | |
e3d12c65 DE |
106 | /*---------------------------------------------------------------------------*/ |
107 | /*-- GDB simulator interface ------------------------------------------------*/ | |
108 | /*---------------------------------------------------------------------------*/ | |
109 | ||
0c2c5f61 | 110 | static void ColdReset PARAMS((SIM_DESC sd)); |
e3d12c65 DE |
111 | |
112 | /*---------------------------------------------------------------------------*/ | |
113 | ||
8bae0a0c | 114 | |
8bae0a0c | 115 | |
8bae0a0c | 116 | #define DELAYSLOT() {\ |
0c2c5f61 | 117 | if (STATE & simDELAYSLOT)\ |
18c64df6 | 118 | sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\ |
0c2c5f61 | 119 | STATE |= simDELAYSLOT;\ |
8bae0a0c JSC |
120 | } |
121 | ||
aaff8437 ILT |
122 | #define JALDELAYSLOT() {\ |
123 | DELAYSLOT ();\ | |
0c2c5f61 | 124 | STATE |= simJALDELAYSLOT;\ |
aaff8437 ILT |
125 | } |
126 | ||
8bae0a0c | 127 | #define NULLIFY() {\ |
0c2c5f61 AC |
128 | STATE &= ~simDELAYSLOT;\ |
129 | STATE |= simSKIPNEXT;\ | |
8bae0a0c JSC |
130 | } |
131 | ||
6eedf3f4 | 132 | #define CANCELDELAYSLOT() {\ |
0c2c5f61 AC |
133 | DSSTATE = 0;\ |
134 | STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\ | |
6eedf3f4 MA |
135 | } |
136 | ||
0c2c5f61 AC |
137 | #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0) |
138 | #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0) | |
aaff8437 | 139 | |
a9f7253f JSC |
140 | #define K0BASE (0x80000000) |
141 | #define K0SIZE (0x20000000) | |
142 | #define K1BASE (0xA0000000) | |
143 | #define K1SIZE (0x20000000) | |
525d929e AC |
144 | #define MONITOR_BASE (0xBFC00000) |
145 | #define MONITOR_SIZE (1 << 11) | |
146 | #define MEM_SIZE (2 << 20) | |
a9f7253f | 147 | |
8bae0a0c | 148 | #if defined(TRACE) |
4fa134be | 149 | static char *tracefile = "trace.din"; /* default filename for trace log */ |
030843d7 | 150 | FILE *tracefh = NULL; |
18c64df6 | 151 | static void open_trace PARAMS((SIM_DESC sd)); |
8bae0a0c JSC |
152 | #endif /* TRACE */ |
153 | ||
22de994d AC |
154 | #define OPTION_DINERO_TRACE 200 |
155 | #define OPTION_DINERO_FILE 201 | |
156 | ||
50a2a691 AC |
157 | static SIM_RC |
158 | mips_option_handler (sd, opt, arg) | |
159 | SIM_DESC sd; | |
160 | int opt; | |
161 | char *arg; | |
2e61a3ad | 162 | { |
01737f42 | 163 | int cpu_nr; |
50a2a691 AC |
164 | switch (opt) |
165 | { | |
22de994d | 166 | case OPTION_DINERO_TRACE: /* ??? */ |
50a2a691 AC |
167 | #if defined(TRACE) |
168 | /* Eventually the simTRACE flag could be treated as a toggle, to | |
169 | allow external control of the program points being traced | |
170 | (i.e. only from main onwards, excluding the run-time setup, | |
171 | etc.). */ | |
01737f42 | 172 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) |
50a2a691 | 173 | { |
01737f42 AC |
174 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); |
175 | if (arg == NULL) | |
176 | STATE |= simTRACE; | |
177 | else if (strcmp (arg, "yes") == 0) | |
178 | STATE |= simTRACE; | |
179 | else if (strcmp (arg, "no") == 0) | |
180 | STATE &= ~simTRACE; | |
181 | else if (strcmp (arg, "on") == 0) | |
182 | STATE |= simTRACE; | |
183 | else if (strcmp (arg, "off") == 0) | |
184 | STATE &= ~simTRACE; | |
185 | else | |
186 | { | |
187 | fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg); | |
188 | return SIM_RC_FAIL; | |
189 | } | |
50a2a691 AC |
190 | } |
191 | return SIM_RC_OK; | |
192 | #else /* !TRACE */ | |
193 | fprintf(stderr,"\ | |
22de994d | 194 | Simulator constructed without dinero tracing support (for performance).\n\ |
50a2a691 AC |
195 | Re-compile simulator with \"-DTRACE\" to enable this option.\n"); |
196 | return SIM_RC_FAIL; | |
197 | #endif /* !TRACE */ | |
198 | ||
22de994d | 199 | case OPTION_DINERO_FILE: |
50a2a691 AC |
200 | #if defined(TRACE) |
201 | if (optarg != NULL) { | |
202 | char *tmp; | |
203 | tmp = (char *)malloc(strlen(optarg) + 1); | |
204 | if (tmp == NULL) | |
205 | { | |
18c64df6 | 206 | sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg); |
50a2a691 AC |
207 | return SIM_RC_FAIL; |
208 | } | |
209 | else { | |
210 | strcpy(tmp,optarg); | |
211 | tracefile = tmp; | |
18c64df6 | 212 | sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile); |
50a2a691 AC |
213 | } |
214 | } | |
215 | #endif /* TRACE */ | |
216 | return SIM_RC_OK; | |
217 | ||
50a2a691 AC |
218 | } |
219 | ||
220 | return SIM_RC_OK; | |
2e61a3ad | 221 | } |
50a2a691 AC |
222 | |
223 | static const OPTION mips_options[] = | |
2e61a3ad | 224 | { |
22de994d AC |
225 | { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE}, |
226 | '\0', "on|off", "Enable dinero tracing", | |
50a2a691 | 227 | mips_option_handler }, |
22de994d AC |
228 | { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE}, |
229 | '\0', "FILE", "Write dinero trace to FILE", | |
50a2a691 | 230 | mips_option_handler }, |
50a2a691 AC |
231 | { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } |
232 | }; | |
233 | ||
234 | ||
56e7c849 AC |
235 | int interrupt_pending; |
236 | ||
50a2a691 AC |
237 | static void |
238 | interrupt_event (SIM_DESC sd, void *data) | |
2e61a3ad | 239 | { |
01737f42 | 240 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
56e7c849 AC |
241 | if (SR & status_IE) |
242 | { | |
243 | interrupt_pending = 0; | |
18c64df6 | 244 | SignalExceptionInterrupt (); |
56e7c849 AC |
245 | } |
246 | else if (!interrupt_pending) | |
247 | sim_events_schedule (sd, 1, interrupt_event, data); | |
2e61a3ad | 248 | } |
f7481d45 | 249 | |
f7481d45 | 250 | |
50a2a691 | 251 | |
8bae0a0c JSC |
252 | /*---------------------------------------------------------------------------*/ |
253 | /*-- GDB simulator interface ------------------------------------------------*/ | |
254 | /*---------------------------------------------------------------------------*/ | |
255 | ||
53b9417e | 256 | SIM_DESC |
247fccde | 257 | sim_open (kind, cb, abfd, argv) |
87e43259 | 258 | SIM_OPEN_KIND kind; |
50a2a691 | 259 | host_callback *cb; |
247fccde | 260 | struct _bfd *abfd; |
53b9417e | 261 | char **argv; |
8bae0a0c | 262 | { |
18c64df6 | 263 | SIM_DESC sd = sim_state_alloc (kind, cb); |
01737f42 | 264 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
2e61a3ad | 265 | |
525d929e AC |
266 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
267 | ||
50a2a691 AC |
268 | /* FIXME: watchpoints code shouldn't need this */ |
269 | STATE_WATCHPOINTS (sd)->pc = &(PC); | |
270 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
271 | STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event; | |
272 | ||
0c2c5f61 | 273 | STATE = 0; |
50a2a691 | 274 | |
2e61a3ad AC |
275 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
276 | return 0; | |
50a2a691 | 277 | sim_add_option_table (sd, mips_options); |
2e61a3ad | 278 | |
63be8feb AC |
279 | /* Allocate core managed memory */ |
280 | ||
281 | /* the monitor */ | |
282 | sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE); | |
283 | /* For compatibility with the old code - under this (at level one) | |
284 | are the kernel spaces K0 & K1. Both of these map to a single | |
285 | smaller sub region */ | |
286 | sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x", | |
287 | K1BASE, K0SIZE, | |
288 | MEM_SIZE, /* actual size */ | |
289 | K0BASE); | |
290 | ||
2e61a3ad AC |
291 | /* getopt will print the error message so we just have to exit if this fails. |
292 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
293 | print_filtered. */ | |
294 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
295 | { | |
296 | /* Uninstall the modules to avoid memory leaks, | |
297 | file descriptor leaks, etc. */ | |
298 | sim_module_uninstall (sd); | |
299 | return 0; | |
300 | } | |
2e61a3ad | 301 | |
fafce69a AC |
302 | /* check for/establish the a reference program image */ |
303 | if (sim_analyze_program (sd, | |
304 | (STATE_PROG_ARGV (sd) != NULL | |
305 | ? *STATE_PROG_ARGV (sd) | |
306 | : NULL), | |
307 | abfd) != SIM_RC_OK) | |
308 | { | |
309 | sim_module_uninstall (sd); | |
310 | return 0; | |
311 | } | |
312 | ||
247fccde AC |
313 | /* Configure/verify the target byte order and other runtime |
314 | configuration options */ | |
fafce69a | 315 | if (sim_config (sd) != SIM_RC_OK) |
247fccde AC |
316 | { |
317 | sim_module_uninstall (sd); | |
318 | return 0; | |
319 | } | |
320 | ||
2e61a3ad AC |
321 | if (sim_post_argv_init (sd) != SIM_RC_OK) |
322 | { | |
323 | /* Uninstall the modules to avoid memory leaks, | |
324 | file descriptor leaks, etc. */ | |
325 | sim_module_uninstall (sd); | |
326 | return 0; | |
327 | } | |
328 | ||
50a2a691 AC |
329 | /* verify assumptions the simulator made about the host type system. |
330 | This macro does not return if there is a problem */ | |
7ce8b917 AC |
331 | SIM_ASSERT (sizeof(int) == (4 * sizeof(char))); |
332 | SIM_ASSERT (sizeof(word64) == (8 * sizeof(char))); | |
8bae0a0c | 333 | |
8bae0a0c JSC |
334 | #if defined(HASFPU) |
335 | /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE | |
336 | and DOUBLE binary formats. This is a bit nasty, requiring that we | |
337 | trust the explicit manifests held in the source: */ | |
50a2a691 AC |
338 | /* TODO: We need to cope with the simulated target and the host not |
339 | having the same endianness. This will require the high and low | |
340 | words of a (double) to be swapped when converting between the | |
341 | host and the simulated target. */ | |
8bae0a0c | 342 | { |
50a2a691 AC |
343 | union { |
344 | unsigned int i[2]; | |
345 | double d; | |
346 | float f[2]; | |
347 | } s; | |
348 | ||
349 | s.d = (double)523.2939453125; | |
350 | ||
351 | if ((s.i[0] == 0 && (s.f[1] != (float)4.01102924346923828125 | |
352 | || s.i[1] != 0x40805A5A)) | |
353 | || (s.i[1] == 0 && (s.f[0] != (float)4.01102924346923828125 | |
354 | || s.i[0] != 0x40805A5A))) | |
355 | { | |
356 | fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n"); | |
357 | return 0; | |
358 | } | |
8bae0a0c JSC |
359 | } |
360 | #endif /* HASFPU */ | |
361 | ||
362 | /* This is NASTY, in that we are assuming the size of specific | |
363 | registers: */ | |
364 | { | |
365 | int rn; | |
366 | for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) { | |
367 | if (rn < 32) | |
0c2c5f61 | 368 | cpu->register_widths[rn] = GPRLEN; |
8bae0a0c | 369 | else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32))) |
0c2c5f61 | 370 | cpu->register_widths[rn] = GPRLEN; |
8bae0a0c | 371 | else if ((rn >= 33) && (rn <= 37)) |
0c2c5f61 | 372 | cpu->register_widths[rn] = GPRLEN; |
8bae0a0c | 373 | else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89))) |
0c2c5f61 | 374 | cpu->register_widths[rn] = 32; |
8bae0a0c | 375 | else |
0c2c5f61 | 376 | cpu->register_widths[rn] = 0; |
8bae0a0c | 377 | } |
18c64df6 AC |
378 | /* start-sanitize-r5900 */ |
379 | ||
380 | /* set the 5900 "upper" registers to 64 bits */ | |
381 | for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++) | |
0c2c5f61 | 382 | cpu->register_widths[rn] = 64; |
18c64df6 | 383 | /* end-sanitize-r5900 */ |
8bae0a0c JSC |
384 | } |
385 | ||
8bae0a0c | 386 | #if defined(TRACE) |
0c2c5f61 | 387 | if (STATE & simTRACE) |
18c64df6 | 388 | open_trace(sd); |
8bae0a0c JSC |
389 | #endif /* TRACE */ |
390 | ||
fafce69a AC |
391 | /* Write the monitor trap address handlers into the monitor (eeprom) |
392 | address space. This can only be done once the target endianness | |
393 | has been determined. */ | |
394 | { | |
395 | unsigned loop; | |
396 | /* Entry into the IDT monitor is via fixed address vectors, and | |
397 | not using machine instructions. To avoid clashing with use of | |
398 | the MIPS TRAP system, we place our own (simulator specific) | |
399 | "undefined" instructions into the relevant vector slots. */ | |
525d929e AC |
400 | for (loop = 0; (loop < MONITOR_SIZE); loop += 4) |
401 | { | |
402 | address_word vaddr = (MONITOR_BASE + loop); | |
403 | unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT)); | |
404 | H2T (insn); | |
405 | sim_write (sd, vaddr, (char *)&insn, sizeof (insn)); | |
406 | } | |
fafce69a AC |
407 | /* The PMON monitor uses the same address space, but rather than |
408 | branching into it the address of a routine is loaded. We can | |
409 | cheat for the moment, and direct the PMON routine to IDT style | |
410 | instructions within the monitor space. This relies on the IDT | |
411 | monitor not using the locations from 0xBFC00500 onwards as its | |
412 | entry points.*/ | |
413 | for (loop = 0; (loop < 24); loop++) | |
414 | { | |
525d929e AC |
415 | address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4)); |
416 | unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */ | |
fafce69a AC |
417 | switch (loop) |
418 | { | |
419 | case 0: /* read */ | |
420 | value = 7; | |
421 | break; | |
fafce69a AC |
422 | case 1: /* write */ |
423 | value = 8; | |
424 | break; | |
fafce69a AC |
425 | case 2: /* open */ |
426 | value = 6; | |
427 | break; | |
fafce69a AC |
428 | case 3: /* close */ |
429 | value = 10; | |
430 | break; | |
fafce69a AC |
431 | case 5: /* printf */ |
432 | value = ((0x500 - 16) / 8); /* not an IDT reason code */ | |
433 | break; | |
fafce69a AC |
434 | case 8: /* cliexit */ |
435 | value = 17; | |
436 | break; | |
fafce69a AC |
437 | case 11: /* flush_cache */ |
438 | value = 28; | |
439 | break; | |
440 | } | |
525d929e AC |
441 | /* FIXME - should monitor_base be SIM_ADDR?? */ |
442 | value = ((unsigned int)MONITOR_BASE + (value * 8)); | |
443 | H2T (value); | |
444 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); | |
fafce69a AC |
445 | |
446 | /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */ | |
447 | vaddr -= 0x300; | |
525d929e | 448 | sim_write (sd, vaddr, (char *)&value, sizeof (value)); |
fafce69a AC |
449 | } |
450 | } | |
451 | ||
2e61a3ad | 452 | return sd; |
8bae0a0c JSC |
453 | } |
454 | ||
6429b296 JW |
455 | #if defined(TRACE) |
456 | static void | |
18c64df6 AC |
457 | open_trace(sd) |
458 | SIM_DESC sd; | |
6429b296 JW |
459 | { |
460 | tracefh = fopen(tracefile,"wb+"); | |
461 | if (tracefh == NULL) | |
462 | { | |
18c64df6 | 463 | sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile); |
6429b296 JW |
464 | tracefh = stderr; |
465 | } | |
466 | } | |
467 | #endif /* TRACE */ | |
468 | ||
8bae0a0c | 469 | void |
53b9417e DE |
470 | sim_close (sd, quitting) |
471 | SIM_DESC sd; | |
8bae0a0c JSC |
472 | int quitting; |
473 | { | |
474 | #ifdef DEBUG | |
475 | printf("DBG: sim_close: entered (quitting = %d)\n",quitting); | |
476 | #endif | |
477 | ||
8bae0a0c JSC |
478 | /* "quitting" is non-zero if we cannot hang on errors */ |
479 | ||
480 | /* Ensure that any resources allocated through the callback | |
481 | mechanism are released: */ | |
18c64df6 | 482 | sim_io_shutdown (sd); |
8bae0a0c | 483 | |
8bae0a0c | 484 | #if defined(TRACE) |
e3d12c65 | 485 | if (tracefh != NULL && tracefh != stderr) |
8bae0a0c | 486 | fclose(tracefh); |
e3d12c65 | 487 | tracefh = NULL; |
8bae0a0c JSC |
488 | #endif /* TRACE */ |
489 | ||
01737f42 AC |
490 | /* FIXME - free SD */ |
491 | ||
8bae0a0c JSC |
492 | return; |
493 | } | |
494 | ||
8bae0a0c JSC |
495 | |
496 | int | |
53b9417e DE |
497 | sim_write (sd,addr,buffer,size) |
498 | SIM_DESC sd; | |
8bae0a0c JSC |
499 | SIM_ADDR addr; |
500 | unsigned char *buffer; | |
501 | int size; | |
502 | { | |
525d929e | 503 | int index; |
01737f42 | 504 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
8bae0a0c JSC |
505 | |
506 | /* Return the number of bytes written, or zero if error. */ | |
507 | #ifdef DEBUG | |
18c64df6 | 508 | sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
509 | #endif |
510 | ||
525d929e AC |
511 | /* We use raw read and write routines, since we do not want to count |
512 | the GDB memory accesses in our statistics gathering. */ | |
513 | ||
514 | for (index = 0; index < size; index++) | |
515 | { | |
516 | address_word vaddr = (address_word)addr + index; | |
517 | address_word paddr; | |
518 | int cca; | |
01737f42 | 519 | if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW)) |
525d929e | 520 | break; |
01737f42 | 521 | if (sim_core_write_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1) |
63be8feb | 522 | break; |
8bae0a0c | 523 | } |
8bae0a0c | 524 | |
525d929e | 525 | return(index); |
8bae0a0c JSC |
526 | } |
527 | ||
528 | int | |
53b9417e DE |
529 | sim_read (sd,addr,buffer,size) |
530 | SIM_DESC sd; | |
8bae0a0c JSC |
531 | SIM_ADDR addr; |
532 | unsigned char *buffer; | |
533 | int size; | |
534 | { | |
535 | int index; | |
01737f42 | 536 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
8bae0a0c JSC |
537 | |
538 | /* Return the number of bytes read, or zero if error. */ | |
539 | #ifdef DEBUG | |
18c64df6 | 540 | sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size); |
8bae0a0c JSC |
541 | #endif /* DEBUG */ |
542 | ||
525d929e AC |
543 | for (index = 0; (index < size); index++) |
544 | { | |
545 | address_word vaddr = (address_word)addr + index; | |
546 | address_word paddr; | |
525d929e | 547 | int cca; |
01737f42 | 548 | if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW)) |
525d929e | 549 | break; |
01737f42 | 550 | if (sim_core_read_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1) |
63be8feb | 551 | break; |
525d929e | 552 | } |
8bae0a0c JSC |
553 | |
554 | return(index); | |
555 | } | |
556 | ||
557 | void | |
53b9417e DE |
558 | sim_store_register (sd,rn,memory) |
559 | SIM_DESC sd; | |
8bae0a0c JSC |
560 | int rn; |
561 | unsigned char *memory; | |
562 | { | |
01737f42 | 563 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
50a2a691 AC |
564 | /* NOTE: gdb (the client) stores registers in target byte order |
565 | while the simulator uses host byte order */ | |
8bae0a0c | 566 | #ifdef DEBUG |
18c64df6 | 567 | sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory))); |
8bae0a0c JSC |
568 | #endif /* DEBUG */ |
569 | ||
570 | /* Unfortunately this suffers from the same problem as the register | |
571 | numbering one. We need to know what the width of each logical | |
572 | register number is for the architecture being simulated. */ | |
50a2a691 | 573 | |
0c2c5f61 | 574 | if (cpu->register_widths[rn] == 0) |
18c64df6 AC |
575 | sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn); |
576 | /* start-sanitize-r5900 */ | |
577 | else if (rn == REGISTER_SA) | |
578 | SA = T2H_8(*(uword64*)memory); | |
579 | else if (rn > LAST_EMBED_REGNUM) | |
0c2c5f61 | 580 | cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(uword64*)memory); |
18c64df6 | 581 | /* end-sanitize-r5900 */ |
0c2c5f61 AC |
582 | else if (cpu->register_widths[rn] == 32) |
583 | cpu->registers[rn] = T2H_4 (*(unsigned int*)memory); | |
50a2a691 | 584 | else |
0c2c5f61 | 585 | cpu->registers[rn] = T2H_8 (*(uword64*)memory); |
8bae0a0c JSC |
586 | |
587 | return; | |
588 | } | |
589 | ||
590 | void | |
53b9417e DE |
591 | sim_fetch_register (sd,rn,memory) |
592 | SIM_DESC sd; | |
8bae0a0c JSC |
593 | int rn; |
594 | unsigned char *memory; | |
595 | { | |
01737f42 | 596 | sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ |
50a2a691 AC |
597 | /* NOTE: gdb (the client) stores registers in target byte order |
598 | while the simulator uses host byte order */ | |
8bae0a0c | 599 | #ifdef DEBUG |
18c64df6 | 600 | sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn])); |
8bae0a0c JSC |
601 | #endif /* DEBUG */ |
602 | ||
0c2c5f61 | 603 | if (cpu->register_widths[rn] == 0) |
18c64df6 AC |
604 | sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn); |
605 | /* start-sanitize-r5900 */ | |
606 | else if (rn == REGISTER_SA) | |
607 | *((uword64 *)memory) = H2T_8(SA); | |
608 | else if (rn > LAST_EMBED_REGNUM) | |
0c2c5f61 | 609 | *((uword64 *)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]); |
18c64df6 | 610 | /* end-sanitize-r5900 */ |
0c2c5f61 AC |
611 | else if (cpu->register_widths[rn] == 32) |
612 | *((unsigned int *)memory) = H2T_4 ((unsigned int)(cpu->registers[rn] & 0xFFFFFFFF)); | |
18c64df6 | 613 | else /* 64bit register */ |
0c2c5f61 | 614 | *((uword64 *)memory) = H2T_8 (cpu->registers[rn]); |
50a2a691 | 615 | |
8bae0a0c JSC |
616 | return; |
617 | } | |
50a2a691 | 618 | |
8bae0a0c JSC |
619 | |
620 | void | |
53b9417e DE |
621 | sim_info (sd,verbose) |
622 | SIM_DESC sd; | |
8bae0a0c JSC |
623 | int verbose; |
624 | { | |
625 | /* Accessed from the GDB "info files" command: */ | |
56e7c849 AC |
626 | if (STATE_VERBOSE_P (sd) || verbose) |
627 | { | |
628 | ||
629 | sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n", | |
630 | (PROCESSOR_64BIT ? 64 : 32), | |
631 | (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little")); | |
632 | ||
8bae0a0c | 633 | #if !defined(FASTSIM) |
56e7c849 AC |
634 | /* It would be a useful feature, if when performing multi-cycle |
635 | simulations (rather than single-stepping) we keep the start and | |
636 | end times of the execution, so that we can give a performance | |
637 | figure for the simulator. */ | |
8bae0a0c | 638 | #endif /* !FASTSIM */ |
56e7c849 AC |
639 | sim_io_printf (sd, "Number of execution cycles = %ld\n", |
640 | (long) sim_events_time (sd)); | |
641 | ||
642 | /* print information pertaining to MIPS ISA and architecture being simulated */ | |
643 | /* things that may be interesting */ | |
644 | /* instructions executed - if available */ | |
645 | /* cycles executed - if available */ | |
646 | /* pipeline stalls - if available */ | |
647 | /* virtual time taken */ | |
648 | /* profiling size */ | |
649 | /* profiling frequency */ | |
650 | /* profile minpc */ | |
651 | /* profile maxpc */ | |
652 | } | |
aa324b9b | 653 | profile_print (sd, STATE_VERBOSE_P (sd), NULL, NULL); |
8bae0a0c JSC |
654 | } |
655 | ||
8bae0a0c | 656 | |
9d52bcb7 | 657 | SIM_RC |
fafce69a | 658 | sim_create_inferior (sd, abfd, argv,env) |
53b9417e | 659 | SIM_DESC sd; |
fafce69a | 660 | struct _bfd *abfd; |
8bae0a0c JSC |
661 | char **argv; |
662 | char **env; | |
663 | { | |
50a2a691 | 664 | |
8bae0a0c | 665 | #ifdef DEBUG |
9d52bcb7 DE |
666 | printf("DBG: sim_create_inferior entered: start_address = 0x%s\n", |
667 | pr_addr(PC)); | |
8bae0a0c JSC |
668 | #endif /* DEBUG */ |
669 | ||
0c2c5f61 | 670 | ColdReset(sd); |
50a2a691 | 671 | |
fafce69a | 672 | if (abfd != NULL) |
01737f42 AC |
673 | { |
674 | /* override PC value set by ColdReset () */ | |
675 | int cpu_nr; | |
676 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) | |
677 | { | |
678 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); | |
679 | CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd)); | |
680 | } | |
681 | } | |
2e61a3ad | 682 | |
f24b7b69 | 683 | #if 0 /* def DEBUG */ |
dad6f1f3 | 684 | if (argv || env) |
8bae0a0c | 685 | { |
dad6f1f3 AC |
686 | /* We should really place the argv slot values into the argument |
687 | registers, and onto the stack as required. However, this | |
688 | assumes that we have a stack defined, which is not | |
689 | necessarily true at the moment. */ | |
690 | char **cptr; | |
691 | sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n"); | |
692 | for (cptr = argv; (cptr && *cptr); cptr++) | |
693 | printf("DBG: arg \"%s\"\n",*cptr); | |
8bae0a0c JSC |
694 | } |
695 | #endif /* DEBUG */ | |
8bae0a0c | 696 | |
9d52bcb7 | 697 | return SIM_RC_OK; |
8bae0a0c JSC |
698 | } |
699 | ||
8bae0a0c | 700 | void |
53b9417e DE |
701 | sim_do_command (sd,cmd) |
702 | SIM_DESC sd; | |
8bae0a0c JSC |
703 | char *cmd; |
704 | { | |
63be8feb AC |
705 | if (sim_args_command (sd, cmd) != SIM_RC_OK) |
706 | sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n", | |
707 | cmd); | |
8bae0a0c JSC |
708 | } |
709 | ||
8bae0a0c JSC |
710 | /*---------------------------------------------------------------------------*/ |
711 | /*-- Private simulator support interface ------------------------------------*/ | |
712 | /*---------------------------------------------------------------------------*/ | |
713 | ||
525d929e AC |
714 | /* Read a null terminated string from memory, return in a buffer */ |
715 | static char * | |
716 | fetch_str (sd, addr) | |
717 | SIM_DESC sd; | |
718 | address_word addr; | |
719 | { | |
720 | char *buf; | |
721 | int nr = 0; | |
722 | char null; | |
723 | while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0) | |
724 | nr++; | |
725 | buf = NZALLOC (char, nr + 1); | |
726 | sim_read (sd, addr, buf, nr); | |
727 | return buf; | |
728 | } | |
729 | ||
a9f7253f | 730 | /* Simple monitor interface (currently setup for the IDT and PMON monitors) */ |
8bae0a0c | 731 | static void |
01737f42 AC |
732 | sim_monitor (SIM_DESC sd, |
733 | sim_cpu *cpu, | |
734 | address_word cia, | |
735 | unsigned int reason) | |
8bae0a0c | 736 | { |
53b9417e DE |
737 | #ifdef DEBUG |
738 | printf("DBG: sim_monitor: entered (reason = %d)\n",reason); | |
739 | #endif /* DEBUG */ | |
740 | ||
8bae0a0c JSC |
741 | /* The IDT monitor actually allows two instructions per vector |
742 | slot. However, the simulator currently causes a trap on each | |
743 | individual instruction. We cheat, and lose the bottom bit. */ | |
744 | reason >>= 1; | |
745 | ||
746 | /* The following callback functions are available, however the | |
747 | monitor we are simulating does not make use of them: get_errno, | |
748 | isatty, lseek, rename, system, time and unlink */ | |
525d929e AC |
749 | switch (reason) |
750 | { | |
751 | ||
8bae0a0c JSC |
752 | case 6: /* int open(char *path,int flags) */ |
753 | { | |
525d929e AC |
754 | char *path = fetch_str (sd, A0); |
755 | V0 = sim_io_open (sd, path, (int)A1); | |
756 | zfree (path); | |
757 | break; | |
8bae0a0c | 758 | } |
8bae0a0c JSC |
759 | |
760 | case 7: /* int read(int file,char *ptr,int len) */ | |
761 | { | |
525d929e AC |
762 | int fd = A0; |
763 | int nr = A2; | |
764 | char *buf = zalloc (nr); | |
765 | V0 = sim_io_read (sd, fd, buf, nr); | |
766 | sim_write (sd, A1, buf, nr); | |
767 | zfree (buf); | |
8bae0a0c JSC |
768 | } |
769 | break; | |
770 | ||
771 | case 8: /* int write(int file,char *ptr,int len) */ | |
772 | { | |
525d929e AC |
773 | int fd = A0; |
774 | int nr = A2; | |
775 | char *buf = zalloc (nr); | |
776 | sim_read (sd, A1, buf, nr); | |
777 | V0 = sim_io_write (sd, fd, buf, nr); | |
778 | zfree (buf); | |
779 | break; | |
8bae0a0c | 780 | } |
8bae0a0c JSC |
781 | |
782 | case 10: /* int close(int file) */ | |
525d929e AC |
783 | { |
784 | V0 = sim_io_close (sd, (int)A0); | |
785 | break; | |
786 | } | |
8bae0a0c | 787 | |
e0e0fc76 MA |
788 | case 2: /* Densan monitor: char inbyte(int waitflag) */ |
789 | { | |
790 | if (A0 == 0) /* waitflag == NOWAIT */ | |
791 | V0 = (ut_reg)-1; | |
792 | } | |
793 | /* Drop through to case 11 */ | |
794 | ||
8bae0a0c JSC |
795 | case 11: /* char inbyte(void) */ |
796 | { | |
797 | char tmp; | |
525d929e AC |
798 | if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char)) |
799 | { | |
800 | sim_io_error(sd,"Invalid return from character read"); | |
801 | V0 = (ut_reg)-1; | |
802 | } | |
8bae0a0c | 803 | else |
525d929e AC |
804 | V0 = (ut_reg)tmp; |
805 | break; | |
8bae0a0c | 806 | } |
8bae0a0c | 807 | |
e0e0fc76 | 808 | case 3: /* Densan monitor: void co(char chr) */ |
8bae0a0c JSC |
809 | case 12: /* void outbyte(char chr) : write a byte to "stdout" */ |
810 | { | |
811 | char tmp = (char)(A0 & 0xFF); | |
525d929e AC |
812 | sim_io_write_stdout (sd, &tmp, sizeof(char)); |
813 | break; | |
8bae0a0c | 814 | } |
8bae0a0c JSC |
815 | |
816 | case 17: /* void _exit() */ | |
525d929e AC |
817 | { |
818 | sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n"); | |
01737f42 | 819 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited, |
525d929e AC |
820 | (unsigned int)(A0 & 0xFFFFFFFF)); |
821 | break; | |
822 | } | |
8bae0a0c | 823 | |
280f90e1 AMT |
824 | case 28 : /* PMON flush_cache */ |
825 | break; | |
826 | ||
8bae0a0c JSC |
827 | case 55: /* void get_mem_info(unsigned int *ptr) */ |
828 | /* in: A0 = pointer to three word memory location */ | |
829 | /* out: [A0 + 0] = size */ | |
830 | /* [A0 + 4] = instruction cache size */ | |
831 | /* [A0 + 8] = data cache size */ | |
832 | { | |
525d929e AC |
833 | address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */; |
834 | H2T (value); | |
835 | sim_write (sd, A0, (char *)&value, sizeof (value)); | |
030843d7 | 836 | /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */ |
525d929e | 837 | break; |
8bae0a0c | 838 | } |
525d929e | 839 | |
a9f7253f JSC |
840 | case 158 : /* PMON printf */ |
841 | /* in: A0 = pointer to format string */ | |
842 | /* A1 = optional argument 1 */ | |
843 | /* A2 = optional argument 2 */ | |
844 | /* A3 = optional argument 3 */ | |
845 | /* out: void */ | |
f24b7b69 | 846 | /* The following is based on the PMON printf source */ |
a9f7253f | 847 | { |
525d929e AC |
848 | address_word s = A0; |
849 | char c; | |
850 | signed_word *ap = &A1; /* 1st argument */ | |
f24b7b69 JSC |
851 | /* This isn't the quickest way, since we call the host print |
852 | routine for every character almost. But it does avoid | |
853 | having to allocate and manage a temporary string buffer. */ | |
525d929e AC |
854 | /* TODO: Include check that we only use three arguments (A1, |
855 | A2 and A3) */ | |
856 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
857 | { | |
858 | if (c == '%') | |
859 | { | |
860 | char tmp[40]; | |
861 | enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST; | |
862 | int width = 0, trunc = 0, haddot = 0, longlong = 0; | |
863 | while (sim_read (sd, s++, &c, 1) && c != '\0') | |
864 | { | |
865 | if (strchr ("dobxXulscefg%", s)) | |
866 | break; | |
867 | else if (c == '-') | |
868 | fmt = FMT_LJUST; | |
869 | else if (c == '0') | |
870 | fmt = FMT_RJUST0; | |
871 | else if (c == '~') | |
872 | fmt = FMT_CENTER; | |
873 | else if (c == '*') | |
874 | { | |
875 | if (haddot) | |
876 | trunc = (int)*ap++; | |
877 | else | |
878 | width = (int)*ap++; | |
879 | } | |
880 | else if (c >= '1' && c <= '9') | |
881 | { | |
882 | address_word t = s; | |
883 | unsigned int n; | |
884 | while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c)) | |
885 | tmp[s - t] = c; | |
886 | tmp[s - t] = '\0'; | |
887 | n = (unsigned int)strtol(tmp,NULL,10); | |
888 | if (haddot) | |
889 | trunc = n; | |
890 | else | |
891 | width = n; | |
892 | s--; | |
893 | } | |
894 | else if (c == '.') | |
895 | haddot = 1; | |
896 | } | |
897 | switch (c) | |
898 | { | |
899 | case '%': | |
900 | sim_io_printf (sd, "%%"); | |
901 | break; | |
902 | case 's': | |
903 | if ((int)*ap != 0) | |
904 | { | |
905 | address_word p = *ap++; | |
906 | char ch; | |
907 | while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0') | |
908 | sim_io_printf(sd, "%c", ch); | |
909 | } | |
910 | else | |
911 | sim_io_printf(sd,"(null)"); | |
912 | break; | |
913 | case 'c': | |
914 | sim_io_printf (sd, "%c", (int)*ap++); | |
915 | break; | |
916 | default: | |
917 | if (c == 'l') | |
918 | { | |
919 | sim_read (sd, s++, &c, 1); | |
920 | if (c == 'l') | |
921 | { | |
922 | longlong = 1; | |
923 | sim_read (sd, s++, &c, 1); | |
924 | } | |
925 | } | |
926 | if (strchr ("dobxXu", c)) | |
927 | { | |
928 | word64 lv = (word64) *ap++; | |
929 | if (c == 'b') | |
930 | sim_io_printf(sd,"<binary not supported>"); | |
931 | else | |
932 | { | |
933 | sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c); | |
934 | if (longlong) | |
935 | sim_io_printf(sd, tmp, lv); | |
936 | else | |
937 | sim_io_printf(sd, tmp, (int)lv); | |
938 | } | |
939 | } | |
940 | else if (strchr ("eEfgG", c)) | |
941 | { | |
942 | double dbl = *(double*)(ap++); | |
943 | sprintf (tmp, "%%%d.%d%c", width, trunc, c); | |
944 | sim_io_printf (sd, tmp, dbl); | |
945 | trunc = 0; | |
946 | } | |
947 | } | |
948 | } | |
949 | else | |
950 | sim_io_printf(sd, "%c", c); | |
951 | } | |
952 | break; | |
a9f7253f | 953 | } |
a9f7253f | 954 | |
8bae0a0c | 955 | default: |
525d929e | 956 | sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n", |
95469ceb | 957 | reason, pr_addr(cia)); |
8bae0a0c JSC |
958 | break; |
959 | } | |
960 | return; | |
961 | } | |
962 | ||
7e6c297e ILT |
963 | /* Store a word into memory. */ |
964 | ||
965 | static void | |
01737f42 AC |
966 | store_word (SIM_DESC sd, |
967 | sim_cpu *cpu, | |
968 | address_word cia, | |
969 | uword64 vaddr, | |
970 | t_reg val) | |
7e6c297e | 971 | { |
dad6f1f3 | 972 | address_word paddr; |
7e6c297e ILT |
973 | int uncached; |
974 | ||
975 | if ((vaddr & 3) != 0) | |
18c64df6 | 976 | SignalExceptionAddressStore (); |
7e6c297e ILT |
977 | else |
978 | { | |
979 | if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, | |
980 | isTARGET, isREAL)) | |
981 | { | |
982 | const uword64 mask = 7; | |
983 | uword64 memval; | |
984 | unsigned int byte; | |
985 | ||
986 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)); | |
987 | byte = (vaddr & mask) ^ (BigEndianCPU << 2); | |
988 | memval = ((uword64) val) << (8 * byte); | |
53b9417e | 989 | StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, |
7e6c297e ILT |
990 | isREAL); |
991 | } | |
992 | } | |
993 | } | |
994 | ||
995 | /* Load a word from memory. */ | |
996 | ||
997 | static t_reg | |
01737f42 AC |
998 | load_word (SIM_DESC sd, |
999 | sim_cpu *cpu, | |
1000 | address_word cia, | |
1001 | uword64 vaddr) | |
7e6c297e ILT |
1002 | { |
1003 | if ((vaddr & 3) != 0) | |
18c64df6 | 1004 | SignalExceptionAddressLoad (); |
7e6c297e ILT |
1005 | else |
1006 | { | |
dad6f1f3 | 1007 | address_word paddr; |
7e6c297e ILT |
1008 | int uncached; |
1009 | ||
1010 | if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, | |
1011 | isTARGET, isREAL)) | |
1012 | { | |
1013 | const uword64 mask = 0x7; | |
1014 | const unsigned int reverse = ReverseEndian ? 1 : 0; | |
1015 | const unsigned int bigend = BigEndianCPU ? 1 : 0; | |
1016 | uword64 memval; | |
1017 | unsigned int byte; | |
1018 | ||
1019 | paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2)); | |
53b9417e | 1020 | LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr, |
7e6c297e ILT |
1021 | isDATA, isREAL); |
1022 | byte = (vaddr & mask) ^ (bigend << 2); | |
1023 | return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32); | |
1024 | } | |
1025 | } | |
1026 | ||
1027 | return 0; | |
1028 | } | |
1029 | ||
1030 | /* Simulate the mips16 entry and exit pseudo-instructions. These | |
1031 | would normally be handled by the reserved instruction exception | |
1032 | code, but for ease of simulation we just handle them directly. */ | |
1033 | ||
1034 | static void | |
01737f42 AC |
1035 | mips16_entry (SIM_DESC sd, |
1036 | sim_cpu *cpu, | |
1037 | address_word cia, | |
1038 | unsigned int insn) | |
7e6c297e ILT |
1039 | { |
1040 | int aregs, sregs, rreg; | |
1041 | ||
53b9417e DE |
1042 | #ifdef DEBUG |
1043 | printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn); | |
1044 | #endif /* DEBUG */ | |
1045 | ||
7e6c297e ILT |
1046 | aregs = (insn & 0x700) >> 8; |
1047 | sregs = (insn & 0x0c0) >> 6; | |
1048 | rreg = (insn & 0x020) >> 5; | |
1049 | ||
da0bce9c ILT |
1050 | /* This should be checked by the caller. */ |
1051 | if (sregs == 3) | |
7e6c297e ILT |
1052 | abort (); |
1053 | ||
da0bce9c | 1054 | if (aregs < 5) |
7e6c297e ILT |
1055 | { |
1056 | int i; | |
1057 | t_reg tsp; | |
1058 | ||
1059 | /* This is the entry pseudo-instruction. */ | |
1060 | ||
1061 | for (i = 0; i < aregs; i++) | |
01737f42 | 1062 | store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]); |
7e6c297e ILT |
1063 | |
1064 | tsp = SP; | |
1065 | SP -= 32; | |
1066 | ||
1067 | if (rreg) | |
1068 | { | |
1069 | tsp -= 4; | |
01737f42 | 1070 | store_word (SD, CPU, cia, (uword64) tsp, RA); |
7e6c297e ILT |
1071 | } |
1072 | ||
1073 | for (i = 0; i < sregs; i++) | |
1074 | { | |
1075 | tsp -= 4; | |
01737f42 | 1076 | store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]); |
7e6c297e ILT |
1077 | } |
1078 | } | |
1079 | else | |
1080 | { | |
1081 | int i; | |
1082 | t_reg tsp; | |
1083 | ||
1084 | /* This is the exit pseudo-instruction. */ | |
1085 | ||
1086 | tsp = SP + 32; | |
1087 | ||
1088 | if (rreg) | |
1089 | { | |
1090 | tsp -= 4; | |
01737f42 | 1091 | RA = load_word (SD, CPU, cia, (uword64) tsp); |
7e6c297e ILT |
1092 | } |
1093 | ||
1094 | for (i = 0; i < sregs; i++) | |
1095 | { | |
1096 | tsp -= 4; | |
01737f42 | 1097 | GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp); |
7e6c297e ILT |
1098 | } |
1099 | ||
1100 | SP += 32; | |
1101 | ||
9cb8397f | 1102 | #if defined(HASFPU) |
da0bce9c ILT |
1103 | if (aregs == 5) |
1104 | { | |
1105 | FGR[0] = WORD64LO (GPR[4]); | |
0c2c5f61 | 1106 | FPR_STATE[0] = fmt_uninterpreted; |
da0bce9c ILT |
1107 | } |
1108 | else if (aregs == 6) | |
1109 | { | |
1110 | FGR[0] = WORD64LO (GPR[5]); | |
1111 | FGR[1] = WORD64LO (GPR[4]); | |
0c2c5f61 AC |
1112 | FPR_STATE[0] = fmt_uninterpreted; |
1113 | FPR_STATE[1] = fmt_uninterpreted; | |
da0bce9c | 1114 | } |
9cb8397f | 1115 | #endif /* defined(HASFPU) */ |
da0bce9c | 1116 | |
7e6c297e ILT |
1117 | PC = RA; |
1118 | } | |
1119 | } | |
1120 | ||
8bae0a0c JSC |
1121 | /*-- trace support ----------------------------------------------------------*/ |
1122 | ||
1123 | /* The TRACE support is provided (if required) in the memory accessing | |
1124 | routines. Since we are also providing the architecture specific | |
1125 | features, the architecture simulation code can also deal with | |
1126 | notifying the TRACE world of cache flushes, etc. Similarly we do | |
1127 | not need to provide profiling support in the simulator engine, | |
1128 | since we can sample in the instruction fetch control loop. By | |
1129 | defining the TRACE manifest, we add tracing as a run-time | |
1130 | option. */ | |
1131 | ||
1132 | #if defined(TRACE) | |
1133 | /* Tracing by default produces "din" format (as required by | |
1134 | dineroIII). Each line of such a trace file *MUST* have a din label | |
1135 | and address field. The rest of the line is ignored, so comments can | |
1136 | be included if desired. The first field is the label which must be | |
1137 | one of the following values: | |
1138 | ||
1139 | 0 read data | |
1140 | 1 write data | |
1141 | 2 instruction fetch | |
1142 | 3 escape record (treated as unknown access type) | |
1143 | 4 escape record (causes cache flush) | |
1144 | ||
1145 | The address field is a 32bit (lower-case) hexadecimal address | |
1146 | value. The address should *NOT* be preceded by "0x". | |
1147 | ||
1148 | The size of the memory transfer is not important when dealing with | |
1149 | cache lines (as long as no more than a cache line can be | |
1150 | transferred in a single operation :-), however more information | |
1151 | could be given following the dineroIII requirement to allow more | |
1152 | complete memory and cache simulators to provide better | |
1153 | results. i.e. the University of Pisa has a cache simulator that can | |
1154 | also take bus size and speed as (variable) inputs to calculate | |
1155 | complete system performance (a much more useful ability when trying | |
1156 | to construct an end product, rather than a processor). They | |
1157 | currently have an ARM version of their tool called ChARM. */ | |
1158 | ||
e3d12c65 | 1159 | |
030843d7 | 1160 | void |
01737f42 AC |
1161 | dotrace (SIM_DESC sd, |
1162 | sim_cpu *cpu, | |
1163 | FILE *tracefh, | |
1164 | int type, | |
1165 | SIM_ADDR address, | |
1166 | int width, | |
1167 | char *comment,...) | |
8bae0a0c | 1168 | { |
0c2c5f61 | 1169 | if (STATE & simTRACE) { |
8bae0a0c | 1170 | va_list ap; |
53b9417e | 1171 | fprintf(tracefh,"%d %s ; width %d ; ", |
6429b296 | 1172 | type, |
53b9417e DE |
1173 | pr_addr(address), |
1174 | width); | |
8bae0a0c | 1175 | va_start(ap,comment); |
6429b296 | 1176 | vfprintf(tracefh,comment,ap); |
8bae0a0c JSC |
1177 | va_end(ap); |
1178 | fprintf(tracefh,"\n"); | |
1179 | } | |
1180 | /* NOTE: Since the "din" format will only accept 32bit addresses, and | |
1181 | we may be generating 64bit ones, we should put the hi-32bits of the | |
1182 | address into the comment field. */ | |
1183 | ||
1184 | /* TODO: Provide a buffer for the trace lines. We can then avoid | |
1185 | performing writes until the buffer is filled, or the file is | |
1186 | being closed. */ | |
1187 | ||
1188 | /* NOTE: We could consider adding a comment field to the "din" file | |
1189 | produced using type 3 markers (unknown access). This would then | |
1190 | allow information about the program that the "din" is for, and | |
1191 | the MIPs world that was being simulated, to be placed into the | |
1192 | trace file. */ | |
1193 | ||
1194 | return; | |
1195 | } | |
1196 | #endif /* TRACE */ | |
1197 | ||
1198 | /*---------------------------------------------------------------------------*/ | |
1199 | /*-- simulator engine -------------------------------------------------------*/ | |
1200 | /*---------------------------------------------------------------------------*/ | |
1201 | ||
1202 | static void | |
01737f42 | 1203 | ColdReset (SIM_DESC sd) |
8bae0a0c | 1204 | { |
01737f42 AC |
1205 | int cpu_nr; |
1206 | for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) | |
dad6f1f3 | 1207 | { |
01737f42 AC |
1208 | sim_cpu *cpu = STATE_CPU (sd, cpu_nr); |
1209 | /* RESET: Fixed PC address: */ | |
1210 | PC = UNSIGNED64 (0xFFFFFFFFBFC00000); | |
1211 | /* The reset vector address is in the unmapped, uncached memory space. */ | |
1212 | ||
1213 | SR &= ~(status_SR | status_TS | status_RP); | |
1214 | SR |= (status_ERL | status_BEV); | |
1215 | ||
1216 | /* Cheat and allow access to the complete register set immediately */ | |
1217 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT | |
1218 | && WITH_TARGET_WORD_BITSIZE == 64) | |
1219 | SR |= status_FR; /* 64bit registers */ | |
1220 | ||
1221 | /* Ensure that any instructions with pending register updates are | |
1222 | cleared: */ | |
1223 | { | |
1224 | int loop; | |
1225 | for (loop = 0; (loop < PSLOTS); loop++) | |
1226 | PENDING_SLOT_REG[loop] = (LAST_EMBED_REGNUM + 1); | |
1227 | PENDING_IN = PENDING_OUT = PENDING_TOTAL = 0; | |
1228 | } | |
1229 | ||
1230 | /* Initialise the FPU registers to the unknown state */ | |
1231 | if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) | |
1232 | { | |
1233 | int rn; | |
1234 | for (rn = 0; (rn < 32); rn++) | |
1235 | FPR_STATE[rn] = fmt_uninterpreted; | |
1236 | } | |
1237 | ||
dad6f1f3 | 1238 | } |
8bae0a0c JSC |
1239 | } |
1240 | ||
dad6f1f3 AC |
1241 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual |
1242 | (revision 3.1) */ | |
8bae0a0c JSC |
1243 | /* Translate a virtual address to a physical address and cache |
1244 | coherence algorithm describing the mechanism used to resolve the | |
1245 | memory reference. Given the virtual address vAddr, and whether the | |
1246 | reference is to Instructions ot Data (IorD), find the corresponding | |
1247 | physical address (pAddr) and the cache coherence algorithm (CCA) | |
1248 | used to resolve the reference. If the virtual address is in one of | |
1249 | the unmapped address spaces the physical address and the CCA are | |
1250 | determined directly by the virtual address. If the virtual address | |
1251 | is in one of the mapped address spaces then the TLB is used to | |
1252 | determine the physical address and access type; if the required | |
1253 | translation is not present in the TLB or the desired access is not | |
1254 | permitted the function fails and an exception is taken. | |
1255 | ||
dad6f1f3 AC |
1256 | NOTE: Normally (RAW == 0), when address translation fails, this |
1257 | function raises an exception and does not return. */ | |
8bae0a0c | 1258 | |
18c64df6 | 1259 | int |
01737f42 AC |
1260 | address_translation (SIM_DESC sd, |
1261 | sim_cpu *cpu, | |
1262 | address_word cia, | |
1263 | address_word vAddr, | |
1264 | int IorD, | |
1265 | int LorS, | |
1266 | address_word *pAddr, | |
1267 | int *CCA, | |
1268 | int raw) | |
8bae0a0c JSC |
1269 | { |
1270 | int res = -1; /* TRUE : Assume good return */ | |
1271 | ||
1272 | #ifdef DEBUG | |
18c64df6 | 1273 | sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD")); |
8bae0a0c JSC |
1274 | #endif |
1275 | ||
1276 | /* Check that the address is valid for this memory model */ | |
1277 | ||
1278 | /* For a simple (flat) memory model, we simply pass virtual | |
1279 | addressess through (mostly) unchanged. */ | |
1280 | vAddr &= 0xFFFFFFFF; | |
a9f7253f | 1281 | |
8bae0a0c JSC |
1282 | *pAddr = vAddr; /* default for isTARGET */ |
1283 | *CCA = Uncached; /* not used for isHOST */ | |
1284 | ||
8bae0a0c JSC |
1285 | return(res); |
1286 | } | |
1287 | ||
63be8feb AC |
1288 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual |
1289 | (revision 3.1) */ | |
8bae0a0c JSC |
1290 | /* Prefetch data from memory. Prefetch is an advisory instruction for |
1291 | which an implementation specific action is taken. The action taken | |
1292 | may increase performance, but must not change the meaning of the | |
1293 | program, or alter architecturally-visible state. */ | |
50a2a691 | 1294 | |
ea985d24 | 1295 | void |
01737f42 AC |
1296 | prefetch (SIM_DESC sd, |
1297 | sim_cpu *cpu, | |
1298 | address_word cia, | |
1299 | int CCA, | |
1300 | address_word pAddr, | |
1301 | address_word vAddr, | |
1302 | int DATA, | |
1303 | int hint) | |
8bae0a0c JSC |
1304 | { |
1305 | #ifdef DEBUG | |
18c64df6 | 1306 | sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint); |
8bae0a0c JSC |
1307 | #endif /* DEBUG */ |
1308 | ||
1309 | /* For our simple memory model we do nothing */ | |
1310 | return; | |
1311 | } | |
1312 | ||
63be8feb AC |
1313 | /* Description from page A-22 of the "MIPS IV Instruction Set" manual |
1314 | (revision 3.1) */ | |
8bae0a0c JSC |
1315 | /* Load a value from memory. Use the cache and main memory as |
1316 | specified in the Cache Coherence Algorithm (CCA) and the sort of | |
1317 | access (IorD) to find the contents of AccessLength memory bytes | |
1318 | starting at physical location pAddr. The data is returned in the | |
1319 | fixed width naturally-aligned memory element (MemElem). The | |
1320 | low-order two (or three) bits of the address and the AccessLength | |
1321 | indicate which of the bytes within MemElem needs to be given to the | |
1322 | processor. If the memory access type of the reference is uncached | |
1323 | then only the referenced bytes are read from memory and valid | |
1324 | within the memory element. If the access type is cached, and the | |
1325 | data is not present in cache, an implementation specific size and | |
1326 | alignment block of memory is read and loaded into the cache to | |
1327 | satisfy a load reference. At a minimum, the block is the entire | |
1328 | memory element. */ | |
18c64df6 | 1329 | void |
01737f42 AC |
1330 | load_memory (SIM_DESC sd, |
1331 | sim_cpu *cpu, | |
1332 | address_word cia, | |
1333 | uword64* memvalp, | |
1334 | uword64* memval1p, | |
1335 | int CCA, | |
1336 | int AccessLength, | |
1337 | address_word pAddr, | |
1338 | address_word vAddr, | |
1339 | int IorD) | |
8bae0a0c | 1340 | { |
50a2a691 AC |
1341 | uword64 value = 0; |
1342 | uword64 value1 = 0; | |
8bae0a0c JSC |
1343 | |
1344 | #ifdef DEBUG | |
63be8feb | 1345 | sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION")); |
8bae0a0c JSC |
1346 | #endif /* DEBUG */ |
1347 | ||
1348 | #if defined(WARN_MEM) | |
1349 | if (CCA != uncached) | |
63be8feb | 1350 | sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); |
8bae0a0c JSC |
1351 | #endif /* WARN_MEM */ |
1352 | ||
8bae0a0c JSC |
1353 | /* If instruction fetch then we need to check that the two lo-order |
1354 | bits are zero, otherwise raise a InstructionFetch exception: */ | |
6429b296 JW |
1355 | if ((IorD == isINSTRUCTION) |
1356 | && ((pAddr & 0x3) != 0) | |
1357 | && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0))) | |
63be8feb AC |
1358 | SignalExceptionInstructionFetch (); |
1359 | ||
1360 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
1361 | { | |
1362 | /* In reality this should be a Bus Error */ | |
1363 | sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n", | |
1364 | AccessLength, | |
1365 | (LOADDRMASK + 1) << 2, | |
1366 | pr_addr (pAddr)); | |
1367 | } | |
8bae0a0c | 1368 | |
8bae0a0c | 1369 | #if defined(TRACE) |
01737f42 | 1370 | dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); |
8bae0a0c | 1371 | #endif /* TRACE */ |
63be8feb AC |
1372 | |
1373 | /* Read the specified number of bytes from memory. Adjust for | |
1374 | host/target byte ordering/ Align the least significant byte | |
1375 | read. */ | |
8bae0a0c | 1376 | |
63be8feb AC |
1377 | switch (AccessLength) |
1378 | { | |
1379 | case AccessLength_QUADWORD : | |
1380 | { | |
01737f42 | 1381 | unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA, |
63be8feb AC |
1382 | sim_core_read_map, pAddr); |
1383 | value1 = VH8_16 (val); | |
1384 | value = VL8_16 (val); | |
1385 | break; | |
8bae0a0c | 1386 | } |
63be8feb | 1387 | case AccessLength_DOUBLEWORD : |
01737f42 | 1388 | value = sim_core_read_aligned_8 (cpu, NULL_CIA, |
63be8feb AC |
1389 | sim_core_read_map, pAddr); |
1390 | break; | |
1391 | case AccessLength_SEPTIBYTE : | |
01737f42 | 1392 | value = sim_core_read_misaligned_7 (cpu, NULL_CIA, |
63be8feb AC |
1393 | sim_core_read_map, pAddr); |
1394 | case AccessLength_SEXTIBYTE : | |
01737f42 | 1395 | value = sim_core_read_misaligned_6 (cpu, NULL_CIA, |
63be8feb AC |
1396 | sim_core_read_map, pAddr); |
1397 | case AccessLength_QUINTIBYTE : | |
01737f42 | 1398 | value = sim_core_read_misaligned_5 (cpu, NULL_CIA, |
63be8feb AC |
1399 | sim_core_read_map, pAddr); |
1400 | case AccessLength_WORD : | |
01737f42 | 1401 | value = sim_core_read_aligned_4 (cpu, NULL_CIA, |
63be8feb AC |
1402 | sim_core_read_map, pAddr); |
1403 | break; | |
1404 | case AccessLength_TRIPLEBYTE : | |
01737f42 | 1405 | value = sim_core_read_misaligned_3 (cpu, NULL_CIA, |
63be8feb AC |
1406 | sim_core_read_map, pAddr); |
1407 | case AccessLength_HALFWORD : | |
01737f42 | 1408 | value = sim_core_read_aligned_2 (cpu, NULL_CIA, |
63be8feb AC |
1409 | sim_core_read_map, pAddr); |
1410 | break; | |
1411 | case AccessLength_BYTE : | |
01737f42 | 1412 | value = sim_core_read_aligned_1 (cpu, NULL_CIA, |
63be8feb AC |
1413 | sim_core_read_map, pAddr); |
1414 | break; | |
1415 | default: | |
1416 | abort (); | |
1417 | } | |
1418 | ||
8bae0a0c | 1419 | #ifdef DEBUG |
63be8feb AC |
1420 | printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n", |
1421 | (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value)); | |
8bae0a0c | 1422 | #endif /* DEBUG */ |
63be8feb AC |
1423 | |
1424 | /* See also store_memory. */ | |
1425 | if (AccessLength <= AccessLength_DOUBLEWORD) | |
1426 | { | |
1427 | if (BigEndianMem) | |
1428 | /* for big endian target, byte (pAddr&LOADDRMASK == 0) is | |
1429 | shifted to the most significant byte position. */ | |
1430 | value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
1431 | else | |
1432 | /* For little endian target, byte (pAddr&LOADDRMASK == 0) | |
1433 | is already in the correct postition. */ | |
1434 | value <<= ((pAddr & LOADDRMASK) * 8); | |
1435 | } | |
1436 | ||
8bae0a0c | 1437 | #ifdef DEBUG |
63be8feb AC |
1438 | printf("DBG: LoadMemory() : shifted value = 0x%s%s\n", |
1439 | pr_uword64(value1),pr_uword64(value)); | |
e871dd18 | 1440 | #endif /* DEBUG */ |
63be8feb | 1441 | |
525d929e AC |
1442 | *memvalp = value; |
1443 | if (memval1p) *memval1p = value1; | |
8bae0a0c JSC |
1444 | } |
1445 | ||
53b9417e | 1446 | |
50a2a691 AC |
1447 | /* Description from page A-23 of the "MIPS IV Instruction Set" manual |
1448 | (revision 3.1) */ | |
8bae0a0c JSC |
1449 | /* Store a value to memory. The specified data is stored into the |
1450 | physical location pAddr using the memory hierarchy (data caches and | |
1451 | main memory) as specified by the Cache Coherence Algorithm | |
1452 | (CCA). The MemElem contains the data for an aligned, fixed-width | |
1453 | memory element (word for 32-bit processors, doubleword for 64-bit | |
1454 | processors), though only the bytes that will actually be stored to | |
1455 | memory need to be valid. The low-order two (or three) bits of pAddr | |
1456 | and the AccessLength field indicates which of the bytes within the | |
1457 | MemElem data should actually be stored; only these bytes in memory | |
1458 | will be changed. */ | |
53b9417e | 1459 | |
18c64df6 | 1460 | void |
01737f42 AC |
1461 | store_memory (SIM_DESC sd, |
1462 | sim_cpu *cpu, | |
1463 | address_word cia, | |
1464 | int CCA, | |
1465 | int AccessLength, | |
1466 | uword64 MemElem, | |
1467 | uword64 MemElem1, /* High order 64 bits */ | |
1468 | address_word pAddr, | |
1469 | address_word vAddr) | |
8bae0a0c JSC |
1470 | { |
1471 | #ifdef DEBUG | |
63be8feb | 1472 | sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr)); |
8bae0a0c | 1473 | #endif /* DEBUG */ |
63be8feb | 1474 | |
8bae0a0c JSC |
1475 | #if defined(WARN_MEM) |
1476 | if (CCA != uncached) | |
63be8feb | 1477 | sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); |
8bae0a0c | 1478 | #endif /* WARN_MEM */ |
63be8feb AC |
1479 | |
1480 | if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) | |
1481 | sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr)); | |
1482 | ||
8bae0a0c | 1483 | #if defined(TRACE) |
01737f42 | 1484 | dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store"); |
8bae0a0c | 1485 | #endif /* TRACE */ |
63be8feb | 1486 | |
8bae0a0c | 1487 | #ifdef DEBUG |
63be8feb | 1488 | printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c | 1489 | #endif /* DEBUG */ |
63be8feb AC |
1490 | |
1491 | /* See also load_memory */ | |
1492 | if (AccessLength <= AccessLength_DOUBLEWORD) | |
1493 | { | |
1494 | if (BigEndianMem) | |
1495 | /* for big endian target, byte (pAddr&LOADDRMASK == 0) is | |
1496 | shifted to the most significant byte position. */ | |
1497 | MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8); | |
1498 | else | |
1499 | /* For little endian target, byte (pAddr&LOADDRMASK == 0) | |
1500 | is already in the correct postition. */ | |
1501 | MemElem >>= ((pAddr & LOADDRMASK) * 8); | |
1502 | } | |
1503 | ||
8bae0a0c | 1504 | #ifdef DEBUG |
63be8feb | 1505 | printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem)); |
8bae0a0c | 1506 | #endif /* DEBUG */ |
63be8feb AC |
1507 | |
1508 | switch (AccessLength) | |
1509 | { | |
1510 | case AccessLength_QUADWORD : | |
1511 | { | |
1512 | unsigned_16 val = U16_8 (MemElem1, MemElem); | |
01737f42 | 1513 | sim_core_write_aligned_16 (cpu, NULL_CIA, |
63be8feb AC |
1514 | sim_core_write_map, pAddr, val); |
1515 | break; | |
8bae0a0c | 1516 | } |
63be8feb | 1517 | case AccessLength_DOUBLEWORD : |
01737f42 | 1518 | sim_core_write_aligned_8 (cpu, NULL_CIA, |
63be8feb AC |
1519 | sim_core_write_map, pAddr, MemElem); |
1520 | break; | |
1521 | case AccessLength_SEPTIBYTE : | |
01737f42 | 1522 | sim_core_write_misaligned_7 (cpu, NULL_CIA, |
63be8feb AC |
1523 | sim_core_write_map, pAddr, MemElem); |
1524 | break; | |
1525 | case AccessLength_SEXTIBYTE : | |
01737f42 | 1526 | sim_core_write_misaligned_6 (cpu, NULL_CIA, |
63be8feb AC |
1527 | sim_core_write_map, pAddr, MemElem); |
1528 | break; | |
1529 | case AccessLength_QUINTIBYTE : | |
01737f42 | 1530 | sim_core_write_misaligned_5 (cpu, NULL_CIA, |
63be8feb AC |
1531 | sim_core_write_map, pAddr, MemElem); |
1532 | break; | |
1533 | case AccessLength_WORD : | |
01737f42 | 1534 | sim_core_write_aligned_4 (cpu, NULL_CIA, |
63be8feb AC |
1535 | sim_core_write_map, pAddr, MemElem); |
1536 | break; | |
1537 | case AccessLength_TRIPLEBYTE : | |
01737f42 | 1538 | sim_core_write_misaligned_3 (cpu, NULL_CIA, |
63be8feb AC |
1539 | sim_core_write_map, pAddr, MemElem); |
1540 | break; | |
1541 | case AccessLength_HALFWORD : | |
01737f42 | 1542 | sim_core_write_aligned_2 (cpu, NULL_CIA, |
63be8feb AC |
1543 | sim_core_write_map, pAddr, MemElem); |
1544 | break; | |
1545 | case AccessLength_BYTE : | |
01737f42 | 1546 | sim_core_write_aligned_1 (cpu, NULL_CIA, |
63be8feb AC |
1547 | sim_core_write_map, pAddr, MemElem); |
1548 | break; | |
1549 | default: | |
1550 | abort (); | |
1551 | } | |
1552 | ||
8bae0a0c JSC |
1553 | return; |
1554 | } | |
1555 | ||
53b9417e | 1556 | |
dad6f1f3 | 1557 | unsigned32 |
7ce8b917 | 1558 | ifetch32 (SIM_DESC sd, |
01737f42 | 1559 | sim_cpu *cpu, |
7ce8b917 AC |
1560 | address_word cia, |
1561 | address_word vaddr) | |
dad6f1f3 AC |
1562 | { |
1563 | /* Copy the action of the LW instruction */ | |
1564 | address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
1565 | address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
1566 | unsigned64 value; | |
1567 | address_word paddr; | |
1568 | unsigned32 instruction; | |
1569 | unsigned byte; | |
1570 | int cca; | |
1571 | AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL); | |
1572 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
1573 | LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL); | |
1574 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); | |
1575 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
1576 | return instruction; | |
1577 | } | |
1578 | ||
1579 | ||
8bae0a0c JSC |
1580 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ |
1581 | /* Order loads and stores to synchronise shared memory. Perform the | |
1582 | action necessary to make the effects of groups of synchronizable | |
1583 | loads and stores indicated by stype occur in the same order for all | |
1584 | processors. */ | |
ea985d24 | 1585 | void |
01737f42 AC |
1586 | sync_operation (SIM_DESC sd, |
1587 | sim_cpu *cpu, | |
1588 | address_word cia, | |
1589 | int stype) | |
8bae0a0c JSC |
1590 | { |
1591 | #ifdef DEBUG | |
18c64df6 | 1592 | sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype); |
8bae0a0c JSC |
1593 | #endif /* DEBUG */ |
1594 | return; | |
1595 | } | |
1596 | ||
1597 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1598 | /* Signal an exception condition. This will result in an exception | |
1599 | that aborts the instruction. The instruction operation pseudocode | |
50a2a691 | 1600 | will never see a return from this function call. */ |
2e61a3ad | 1601 | |
18c64df6 | 1602 | void |
7ce8b917 | 1603 | signal_exception (SIM_DESC sd, |
01737f42 | 1604 | sim_cpu *cpu, |
7ce8b917 AC |
1605 | address_word cia, |
1606 | int exception,...) | |
8bae0a0c | 1607 | { |
56e7c849 | 1608 | int vector; |
6eedf3f4 MA |
1609 | |
1610 | #ifdef DEBUG | |
95469ceb | 1611 | sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); |
6eedf3f4 MA |
1612 | #endif /* DEBUG */ |
1613 | ||
8bae0a0c JSC |
1614 | /* Ensure that any active atomic read/modify/write operation will fail: */ |
1615 | LLBIT = 0; | |
1616 | ||
1617 | switch (exception) { | |
1618 | /* TODO: For testing purposes I have been ignoring TRAPs. In | |
1619 | reality we should either simulate them, or allow the user to | |
6eedf3f4 MA |
1620 | ignore them at run-time. |
1621 | Same for SYSCALL */ | |
8bae0a0c | 1622 | case Trap : |
95469ceb | 1623 | sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia)); |
8bae0a0c JSC |
1624 | break; |
1625 | ||
6eedf3f4 MA |
1626 | case SystemCall : |
1627 | { | |
1628 | va_list ap; | |
1629 | unsigned int instruction; | |
1630 | unsigned int code; | |
1631 | ||
1632 | va_start(ap,exception); | |
1633 | instruction = va_arg(ap,unsigned int); | |
1634 | va_end(ap); | |
1635 | ||
1636 | code = (instruction >> 6) & 0xFFFFF; | |
1637 | ||
18c64df6 | 1638 | sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n", |
95469ceb | 1639 | code, pr_addr(cia)); |
6eedf3f4 MA |
1640 | } |
1641 | break; | |
1642 | ||
1643 | case DebugBreakPoint : | |
1644 | if (! (Debug & Debug_DM)) | |
1645 | { | |
1646 | if (INDELAYSLOT()) | |
1647 | { | |
1648 | CANCELDELAYSLOT(); | |
1649 | ||
1650 | Debug |= Debug_DBD; /* signaled from within in delay slot */ | |
95469ceb | 1651 | DEPC = cia - 4; /* reference the branch instruction */ |
6eedf3f4 MA |
1652 | } |
1653 | else | |
1654 | { | |
1655 | Debug &= ~Debug_DBD; /* not signaled from within a delay slot */ | |
95469ceb | 1656 | DEPC = cia; |
6eedf3f4 MA |
1657 | } |
1658 | ||
1659 | Debug |= Debug_DM; /* in debugging mode */ | |
1660 | Debug |= Debug_DBp; /* raising a DBp exception */ | |
1661 | PC = 0xBFC00200; | |
01737f42 | 1662 | sim_engine_restart (SD, CPU, NULL, NULL_CIA); |
6eedf3f4 MA |
1663 | } |
1664 | break; | |
1665 | ||
8bae0a0c JSC |
1666 | case ReservedInstruction : |
1667 | { | |
1668 | va_list ap; | |
1669 | unsigned int instruction; | |
1670 | va_start(ap,exception); | |
1671 | instruction = va_arg(ap,unsigned int); | |
1672 | va_end(ap); | |
1673 | /* Provide simple monitor support using ReservedInstruction | |
1674 | exceptions. The following code simulates the fixed vector | |
1675 | entry points into the IDT monitor by causing a simulator | |
1676 | trap, performing the monitor operation, and returning to | |
1677 | the address held in the $ra register (standard PCS return | |
1678 | address). This means we only need to pre-load the vector | |
1679 | space with suitable instruction values. For systems were | |
1680 | actual trap instructions are used, we would not need to | |
1681 | perform this magic. */ | |
7ce8b917 AC |
1682 | if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION) |
1683 | { | |
01737f42 | 1684 | sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) ); |
7ce8b917 AC |
1685 | /* NOTE: This assumes that a branch-and-link style |
1686 | instruction was used to enter the vector (which is the | |
1687 | case with the current IDT monitor). */ | |
01737f42 | 1688 | sim_engine_restart (SD, CPU, NULL, RA); |
7ce8b917 | 1689 | } |
7e6c297e ILT |
1690 | /* Look for the mips16 entry and exit instructions, and |
1691 | simulate a handler for them. */ | |
95469ceb | 1692 | else if ((cia & 1) != 0 |
7e6c297e | 1693 | && (instruction & 0xf81f) == 0xe809 |
7ce8b917 AC |
1694 | && (instruction & 0x0c0) != 0x0c0) |
1695 | { | |
01737f42 | 1696 | mips16_entry (SD, CPU, cia, instruction); |
7ce8b917 AC |
1697 | sim_engine_restart (sd, NULL, NULL, NULL_CIA); |
1698 | } | |
1699 | /* else fall through to normal exception processing */ | |
95469ceb | 1700 | sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia)); |
8bae0a0c JSC |
1701 | } |
1702 | ||
05d1322f | 1703 | case BreakPoint: |
e3d12c65 | 1704 | #ifdef DEBUG |
95469ceb | 1705 | sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); |
8bae0a0c | 1706 | #endif /* DEBUG */ |
05d1322f JL |
1707 | /* Keep a copy of the current A0 in-case this is the program exit |
1708 | breakpoint: */ | |
1709 | { | |
1710 | va_list ap; | |
1711 | unsigned int instruction; | |
1712 | va_start(ap,exception); | |
1713 | instruction = va_arg(ap,unsigned int); | |
1714 | va_end(ap); | |
1715 | /* Check for our special terminating BREAK: */ | |
1716 | if ((instruction & 0x03FFFFC0) == 0x03ff0000) { | |
01737f42 | 1717 | sim_engine_halt (SD, CPU, NULL, cia, |
05d1322f JL |
1718 | sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); |
1719 | } | |
1720 | } | |
0c2c5f61 | 1721 | if (STATE & simDELAYSLOT) |
95469ceb | 1722 | PC = cia - 4; /* reference the branch instruction */ |
05d1322f | 1723 | else |
95469ceb | 1724 | PC = cia; |
01737f42 | 1725 | sim_engine_halt (SD, CPU, NULL, cia, |
232156de | 1726 | sim_stopped, SIM_SIGTRAP); |
05d1322f JL |
1727 | |
1728 | default: | |
8bae0a0c JSC |
1729 | /* Store exception code into current exception id variable (used |
1730 | by exit code): */ | |
1731 | ||
1732 | /* TODO: If not simulating exceptions then stop the simulator | |
1733 | execution. At the moment we always stop the simulation. */ | |
e3d12c65 | 1734 | |
56e7c849 AC |
1735 | /* See figure 5-17 for an outline of the code below */ |
1736 | if (! (SR & status_EXL)) | |
1737 | { | |
1738 | CAUSE = (exception << 2); | |
0c2c5f61 | 1739 | if (STATE & simDELAYSLOT) |
56e7c849 | 1740 | { |
0c2c5f61 | 1741 | STATE &= ~simDELAYSLOT; |
56e7c849 | 1742 | CAUSE |= cause_BD; |
95469ceb | 1743 | EPC = (cia - 4); /* reference the branch instruction */ |
56e7c849 AC |
1744 | } |
1745 | else | |
95469ceb | 1746 | EPC = cia; |
56e7c849 AC |
1747 | /* FIXME: TLB et.al. */ |
1748 | vector = 0x180; | |
1749 | } | |
1750 | else | |
1751 | { | |
05d1322f | 1752 | CAUSE = (exception << 2); |
56e7c849 AC |
1753 | vector = 0x180; |
1754 | } | |
1755 | SR |= status_EXL; | |
e3d12c65 DE |
1756 | /* Store exception code into current exception id variable (used |
1757 | by exit code): */ | |
56e7c849 AC |
1758 | if (SR & status_BEV) |
1759 | PC = (signed)0xBFC00200 + 0x180; | |
1760 | else | |
1761 | PC = (signed)0x80000000 + 0x180; | |
1762 | ||
50a2a691 AC |
1763 | switch ((CAUSE >> 2) & 0x1F) |
1764 | { | |
1765 | case Interrupt: | |
56e7c849 AC |
1766 | /* Interrupts arrive during event processing, no need to |
1767 | restart */ | |
1768 | return; | |
50a2a691 AC |
1769 | |
1770 | case TLBModification: | |
1771 | case TLBLoad: | |
1772 | case TLBStore: | |
1773 | case AddressLoad: | |
1774 | case AddressStore: | |
1775 | case InstructionFetch: | |
1776 | case DataReference: | |
56e7c849 AC |
1777 | /* The following is so that the simulator will continue from the |
1778 | exception address on breakpoint operations. */ | |
1779 | PC = EPC; | |
01737f42 | 1780 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1781 | sim_stopped, SIM_SIGBUS); |
50a2a691 AC |
1782 | |
1783 | case ReservedInstruction: | |
1784 | case CoProcessorUnusable: | |
56e7c849 | 1785 | PC = EPC; |
01737f42 | 1786 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1787 | sim_stopped, SIM_SIGILL); |
50a2a691 AC |
1788 | |
1789 | case IntegerOverflow: | |
1790 | case FPE: | |
01737f42 | 1791 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1792 | sim_stopped, SIM_SIGFPE); |
50a2a691 AC |
1793 | |
1794 | case Trap: | |
1795 | case Watch: | |
1796 | case SystemCall: | |
56e7c849 | 1797 | PC = EPC; |
01737f42 | 1798 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1799 | sim_stopped, SIM_SIGTRAP); |
50a2a691 | 1800 | |
05d1322f JL |
1801 | case BreakPoint: |
1802 | PC = EPC; | |
01737f42 | 1803 | sim_engine_abort (SD, CPU, NULL_CIA, |
05d1322f JL |
1804 | "FATAL: Should not encounter a breakpoint\n"); |
1805 | ||
50a2a691 | 1806 | default : /* Unknown internal exception */ |
56e7c849 | 1807 | PC = EPC; |
01737f42 | 1808 | sim_engine_halt (SD, CPU, NULL, NULL_CIA, |
232156de | 1809 | sim_stopped, SIM_SIGABRT); |
50a2a691 AC |
1810 | |
1811 | } | |
8bae0a0c JSC |
1812 | |
1813 | case SimulatorFault: | |
1814 | { | |
1815 | va_list ap; | |
1816 | char *msg; | |
1817 | va_start(ap,exception); | |
1818 | msg = va_arg(ap,char *); | |
50a2a691 | 1819 | va_end(ap); |
01737f42 | 1820 | sim_engine_abort (SD, CPU, NULL_CIA, |
2e61a3ad | 1821 | "FATAL: Simulator error \"%s\"\n",msg); |
8bae0a0c | 1822 | } |
8bae0a0c JSC |
1823 | } |
1824 | ||
1825 | return; | |
1826 | } | |
1827 | ||
1828 | #if defined(WARN_RESULT) | |
1829 | /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ | |
1830 | /* This function indicates that the result of the operation is | |
1831 | undefined. However, this should not affect the instruction | |
1832 | stream. All that is meant to happen is that the destination | |
1833 | register is set to an undefined result. To keep the simulator | |
1834 | simple, we just don't bother updating the destination register, so | |
1835 | the overall result will be undefined. If desired we can stop the | |
1836 | simulator by raising a pseudo-exception. */ | |
95469ceb | 1837 | #define UndefinedResult() undefined_result (sd,cia) |
8bae0a0c | 1838 | static void |
95469ceb AC |
1839 | undefined_result(sd,cia) |
1840 | SIM_DESC sd; | |
1841 | address_word cia; | |
8bae0a0c | 1842 | { |
95469ceb | 1843 | sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia)); |
8bae0a0c JSC |
1844 | #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */ |
1845 | state |= simSTOP; | |
1846 | #endif | |
1847 | return; | |
1848 | } | |
1849 | #endif /* WARN_RESULT */ | |
1850 | ||
18c64df6 | 1851 | void |
01737f42 AC |
1852 | cache_op (SIM_DESC sd, |
1853 | sim_cpu *cpu, | |
1854 | address_word cia, | |
1855 | int op, | |
1856 | address_word pAddr, | |
1857 | address_word vAddr, | |
1858 | unsigned int instruction) | |
8bae0a0c | 1859 | { |
f24b7b69 JSC |
1860 | #if 1 /* stop warning message being displayed (we should really just remove the code) */ |
1861 | static int icache_warning = 1; | |
1862 | static int dcache_warning = 1; | |
1863 | #else | |
a9f7253f JSC |
1864 | static int icache_warning = 0; |
1865 | static int dcache_warning = 0; | |
f24b7b69 | 1866 | #endif |
a9f7253f | 1867 | |
8bae0a0c JSC |
1868 | /* If CP0 is not useable (User or Supervisor mode) and the CP0 |
1869 | enable bit in the Status Register is clear - a coprocessor | |
1870 | unusable exception is taken. */ | |
a9f7253f | 1871 | #if 0 |
95469ceb | 1872 | sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia)); |
a9f7253f | 1873 | #endif |
8bae0a0c JSC |
1874 | |
1875 | switch (op & 0x3) { | |
1876 | case 0: /* instruction cache */ | |
1877 | switch (op >> 2) { | |
1878 | case 0: /* Index Invalidate */ | |
1879 | case 1: /* Index Load Tag */ | |
1880 | case 2: /* Index Store Tag */ | |
1881 | case 4: /* Hit Invalidate */ | |
1882 | case 5: /* Fill */ | |
1883 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
1884 | if (!icache_warning) |
1885 | { | |
18c64df6 | 1886 | sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2)); |
a9f7253f JSC |
1887 | icache_warning = 1; |
1888 | } | |
8bae0a0c JSC |
1889 | break; |
1890 | ||
1891 | default: | |
1892 | SignalException(ReservedInstruction,instruction); | |
1893 | break; | |
1894 | } | |
1895 | break; | |
1896 | ||
1897 | case 1: /* data cache */ | |
1898 | switch (op >> 2) { | |
1899 | case 0: /* Index Writeback Invalidate */ | |
1900 | case 1: /* Index Load Tag */ | |
1901 | case 2: /* Index Store Tag */ | |
1902 | case 3: /* Create Dirty */ | |
1903 | case 4: /* Hit Invalidate */ | |
1904 | case 5: /* Hit Writeback Invalidate */ | |
1905 | case 6: /* Hit Writeback */ | |
a9f7253f JSC |
1906 | if (!dcache_warning) |
1907 | { | |
18c64df6 | 1908 | sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2)); |
a9f7253f JSC |
1909 | dcache_warning = 1; |
1910 | } | |
8bae0a0c JSC |
1911 | break; |
1912 | ||
1913 | default: | |
1914 | SignalException(ReservedInstruction,instruction); | |
1915 | break; | |
1916 | } | |
1917 | break; | |
1918 | ||
1919 | default: /* unrecognised cache ID */ | |
1920 | SignalException(ReservedInstruction,instruction); | |
1921 | break; | |
1922 | } | |
1923 | ||
1924 | return; | |
1925 | } | |
1926 | ||
1927 | /*-- FPU support routines ---------------------------------------------------*/ | |
1928 | ||
1929 | #if defined(HASFPU) /* Only needed when building FPU aware simulators */ | |
1930 | ||
8bae0a0c JSC |
1931 | /* Numbers are held in normalized form. The SINGLE and DOUBLE binary |
1932 | formats conform to ANSI/IEEE Std 754-1985. */ | |
1933 | /* SINGLE precision floating: | |
1934 | * seeeeeeeefffffffffffffffffffffff | |
1935 | * s = 1bit = sign | |
1936 | * e = 8bits = exponent | |
1937 | * f = 23bits = fraction | |
1938 | */ | |
1939 | /* SINGLE precision fixed: | |
1940 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
1941 | * s = 1bit = sign | |
1942 | * i = 31bits = integer | |
1943 | */ | |
1944 | /* DOUBLE precision floating: | |
1945 | * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff | |
1946 | * s = 1bit = sign | |
1947 | * e = 11bits = exponent | |
1948 | * f = 52bits = fraction | |
1949 | */ | |
1950 | /* DOUBLE precision fixed: | |
1951 | * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii | |
1952 | * s = 1bit = sign | |
1953 | * i = 63bits = integer | |
1954 | */ | |
1955 | ||
1956 | /* Extract sign-bit: */ | |
1957 | #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0) | |
e871dd18 | 1958 | #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0) |
8bae0a0c JSC |
1959 | /* Extract biased exponent: */ |
1960 | #define FP_S_be(v) (((v) >> 23) & 0xFF) | |
1961 | #define FP_D_be(v) (((v) >> 52) & 0x7FF) | |
1962 | /* Extract unbiased Exponent: */ | |
1963 | #define FP_S_e(v) (FP_S_be(v) - 0x7F) | |
1964 | #define FP_D_e(v) (FP_D_be(v) - 0x3FF) | |
1965 | /* Extract complete fraction field: */ | |
1966 | #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23)) | |
e871dd18 | 1967 | #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52)) |
8bae0a0c JSC |
1968 | /* Extract numbered fraction bit: */ |
1969 | #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0) | |
1970 | #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0) | |
1971 | ||
1972 | /* Explicit QNaN values used when value required: */ | |
1973 | #define FPQNaN_SINGLE (0x7FBFFFFF) | |
1974 | #define FPQNaN_WORD (0x7FFFFFFF) | |
e871dd18 JSC |
1975 | #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF) |
1976 | #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF) | |
8bae0a0c JSC |
1977 | |
1978 | /* Explicit Infinity values used when required: */ | |
1979 | #define FPINF_SINGLE (0x7F800000) | |
e871dd18 | 1980 | #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000) |
8bae0a0c JSC |
1981 | |
1982 | #if 1 /* def DEBUG */ | |
1983 | #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor"))) | |
1984 | #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>")))))) | |
1985 | #endif /* DEBUG */ | |
1986 | ||
18c64df6 | 1987 | uword64 |
01737f42 AC |
1988 | value_fpr (SIM_DESC sd, |
1989 | sim_cpu *cpu, | |
1990 | address_word cia, | |
1991 | int fpr, | |
1992 | FP_formats fmt) | |
8bae0a0c | 1993 | { |
50a2a691 | 1994 | uword64 value = 0; |
8bae0a0c JSC |
1995 | int err = 0; |
1996 | ||
1997 | /* Treat unused register values, as fixed-point 64bit values: */ | |
1998 | if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown)) | |
1999 | #if 1 | |
2000 | /* If request to read data as "uninterpreted", then use the current | |
2001 | encoding: */ | |
0c2c5f61 | 2002 | fmt = FPR_STATE[fpr]; |
8bae0a0c JSC |
2003 | #else |
2004 | fmt = fmt_long; | |
2005 | #endif | |
2006 | ||
2007 | /* For values not yet accessed, set to the desired format: */ | |
0c2c5f61 AC |
2008 | if (FPR_STATE[fpr] == fmt_uninterpreted) { |
2009 | FPR_STATE[fpr] = fmt; | |
8bae0a0c JSC |
2010 | #ifdef DEBUG |
2011 | printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt)); | |
2012 | #endif /* DEBUG */ | |
2013 | } | |
0c2c5f61 | 2014 | if (fmt != FPR_STATE[fpr]) { |
95469ceb | 2015 | sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia)); |
0c2c5f61 | 2016 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2017 | } |
2018 | ||
0c2c5f61 | 2019 | if (FPR_STATE[fpr] == fmt_unknown) { |
8bae0a0c JSC |
2020 | /* Set QNaN value: */ |
2021 | switch (fmt) { | |
2022 | case fmt_single: | |
2023 | value = FPQNaN_SINGLE; | |
2024 | break; | |
2025 | ||
2026 | case fmt_double: | |
2027 | value = FPQNaN_DOUBLE; | |
2028 | break; | |
2029 | ||
2030 | case fmt_word: | |
2031 | value = FPQNaN_WORD; | |
2032 | break; | |
2033 | ||
2034 | case fmt_long: | |
2035 | value = FPQNaN_LONG; | |
2036 | break; | |
2037 | ||
2038 | default: | |
2039 | err = -1; | |
2040 | break; | |
2041 | } | |
2042 | } else if (SizeFGR() == 64) { | |
2043 | switch (fmt) { | |
2044 | case fmt_single: | |
2045 | case fmt_word: | |
2046 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2047 | break; | |
2048 | ||
2049 | case fmt_uninterpreted: | |
2050 | case fmt_double: | |
2051 | case fmt_long: | |
2052 | value = FGR[fpr]; | |
2053 | break; | |
2054 | ||
2055 | default : | |
2056 | err = -1; | |
2057 | break; | |
2058 | } | |
da0bce9c | 2059 | } else { |
8bae0a0c JSC |
2060 | switch (fmt) { |
2061 | case fmt_single: | |
2062 | case fmt_word: | |
2063 | value = (FGR[fpr] & 0xFFFFFFFF); | |
2064 | break; | |
2065 | ||
2066 | case fmt_uninterpreted: | |
2067 | case fmt_double: | |
2068 | case fmt_long: | |
da0bce9c ILT |
2069 | if ((fpr & 1) == 0) { /* even registers only */ |
2070 | value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF)); | |
2071 | } else { | |
18c64df6 | 2072 | SignalException(ReservedInstruction,0); |
da0bce9c | 2073 | } |
8bae0a0c JSC |
2074 | break; |
2075 | ||
2076 | default : | |
2077 | err = -1; | |
2078 | break; | |
2079 | } | |
2080 | } | |
2081 | ||
2082 | if (err) | |
18c64df6 | 2083 | SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()"); |
8bae0a0c JSC |
2084 | |
2085 | #ifdef DEBUG | |
95469ceb | 2086 | printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR()); |
8bae0a0c JSC |
2087 | #endif /* DEBUG */ |
2088 | ||
2089 | return(value); | |
2090 | } | |
2091 | ||
18c64df6 | 2092 | void |
01737f42 AC |
2093 | store_fpr (SIM_DESC sd, |
2094 | sim_cpu *cpu, | |
2095 | address_word cia, | |
2096 | int fpr, | |
2097 | FP_formats fmt, | |
2098 | uword64 value) | |
8bae0a0c JSC |
2099 | { |
2100 | int err = 0; | |
2101 | ||
2102 | #ifdef DEBUG | |
95469ceb | 2103 | printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR()); |
8bae0a0c JSC |
2104 | #endif /* DEBUG */ |
2105 | ||
2106 | if (SizeFGR() == 64) { | |
2107 | switch (fmt) { | |
a09a30d2 AC |
2108 | case fmt_uninterpreted_32: |
2109 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2110 | case fmt_single : |
2111 | case fmt_word : | |
e871dd18 | 2112 | FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF)); |
0c2c5f61 | 2113 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2114 | break; |
2115 | ||
a09a30d2 AC |
2116 | case fmt_uninterpreted_64: |
2117 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2118 | case fmt_uninterpreted: |
2119 | case fmt_double : | |
2120 | case fmt_long : | |
2121 | FGR[fpr] = value; | |
0c2c5f61 | 2122 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2123 | break; |
2124 | ||
2125 | default : | |
0c2c5f61 | 2126 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2127 | err = -1; |
2128 | break; | |
2129 | } | |
da0bce9c | 2130 | } else { |
8bae0a0c | 2131 | switch (fmt) { |
a09a30d2 AC |
2132 | case fmt_uninterpreted_32: |
2133 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2134 | case fmt_single : |
2135 | case fmt_word : | |
8bae0a0c | 2136 | FGR[fpr] = (value & 0xFFFFFFFF); |
0c2c5f61 | 2137 | FPR_STATE[fpr] = fmt; |
8bae0a0c JSC |
2138 | break; |
2139 | ||
a09a30d2 AC |
2140 | case fmt_uninterpreted_64: |
2141 | fmt = fmt_uninterpreted; | |
8bae0a0c JSC |
2142 | case fmt_uninterpreted: |
2143 | case fmt_double : | |
2144 | case fmt_long : | |
da0bce9c ILT |
2145 | if ((fpr & 1) == 0) { /* even register number only */ |
2146 | FGR[fpr+1] = (value >> 32); | |
2147 | FGR[fpr] = (value & 0xFFFFFFFF); | |
0c2c5f61 AC |
2148 | FPR_STATE[fpr + 1] = fmt; |
2149 | FPR_STATE[fpr] = fmt; | |
da0bce9c | 2150 | } else { |
0c2c5f61 AC |
2151 | FPR_STATE[fpr] = fmt_unknown; |
2152 | FPR_STATE[fpr + 1] = fmt_unknown; | |
18c64df6 | 2153 | SignalException(ReservedInstruction,0); |
da0bce9c | 2154 | } |
8bae0a0c JSC |
2155 | break; |
2156 | ||
2157 | default : | |
0c2c5f61 | 2158 | FPR_STATE[fpr] = fmt_unknown; |
8bae0a0c JSC |
2159 | err = -1; |
2160 | break; | |
2161 | } | |
e871dd18 JSC |
2162 | } |
2163 | #if defined(WARN_RESULT) | |
2164 | else | |
2165 | UndefinedResult(); | |
2166 | #endif /* WARN_RESULT */ | |
8bae0a0c JSC |
2167 | |
2168 | if (err) | |
18c64df6 | 2169 | SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()"); |
8bae0a0c JSC |
2170 | |
2171 | #ifdef DEBUG | |
53b9417e | 2172 | printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt)); |
8bae0a0c JSC |
2173 | #endif /* DEBUG */ |
2174 | ||
2175 | return; | |
2176 | } | |
2177 | ||
18c64df6 | 2178 | int |
8bae0a0c | 2179 | NaN(op,fmt) |
e871dd18 | 2180 | uword64 op; |
8bae0a0c JSC |
2181 | FP_formats fmt; |
2182 | { | |
2183 | int boolean = 0; | |
8bae0a0c JSC |
2184 | switch (fmt) { |
2185 | case fmt_single: | |
8bae0a0c | 2186 | case fmt_word: |
76ef4165 FL |
2187 | { |
2188 | sim_fpu wop; | |
2189 | sim_fpu_32to (&wop, op); | |
2190 | boolean = sim_fpu_is_nan (&wop); | |
2191 | break; | |
2192 | } | |
2193 | case fmt_double: | |
8bae0a0c | 2194 | case fmt_long: |
76ef4165 FL |
2195 | { |
2196 | sim_fpu wop; | |
2197 | sim_fpu_64to (&wop, op); | |
2198 | boolean = sim_fpu_is_nan (&wop); | |
2199 | break; | |
2200 | } | |
50a2a691 AC |
2201 | default: |
2202 | fprintf (stderr, "Bad switch\n"); | |
2203 | abort (); | |
8bae0a0c JSC |
2204 | } |
2205 | ||
2206 | #ifdef DEBUG | |
53b9417e | 2207 | printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2208 | #endif /* DEBUG */ |
2209 | ||
2210 | return(boolean); | |
2211 | } | |
2212 | ||
18c64df6 | 2213 | int |
8bae0a0c | 2214 | Infinity(op,fmt) |
e871dd18 | 2215 | uword64 op; |
8bae0a0c JSC |
2216 | FP_formats fmt; |
2217 | { | |
2218 | int boolean = 0; | |
2219 | ||
2220 | #ifdef DEBUG | |
95469ceb | 2221 | printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2222 | #endif /* DEBUG */ |
2223 | ||
8bae0a0c JSC |
2224 | switch (fmt) { |
2225 | case fmt_single: | |
76ef4165 FL |
2226 | { |
2227 | sim_fpu wop; | |
2228 | sim_fpu_32to (&wop, op); | |
2229 | boolean = sim_fpu_is_infinity (&wop); | |
2230 | break; | |
2231 | } | |
8bae0a0c | 2232 | case fmt_double: |
76ef4165 FL |
2233 | { |
2234 | sim_fpu wop; | |
2235 | sim_fpu_64to (&wop, op); | |
2236 | boolean = sim_fpu_is_infinity (&wop); | |
2237 | break; | |
2238 | } | |
8bae0a0c JSC |
2239 | default: |
2240 | printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt)); | |
2241 | break; | |
2242 | } | |
2243 | ||
2244 | #ifdef DEBUG | |
53b9417e | 2245 | printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt)); |
8bae0a0c JSC |
2246 | #endif /* DEBUG */ |
2247 | ||
2248 | return(boolean); | |
2249 | } | |
2250 | ||
18c64df6 | 2251 | int |
8bae0a0c | 2252 | Less(op1,op2,fmt) |
e871dd18 JSC |
2253 | uword64 op1; |
2254 | uword64 op2; | |
8bae0a0c JSC |
2255 | FP_formats fmt; |
2256 | { | |
2257 | int boolean = 0; | |
2258 | ||
e871dd18 JSC |
2259 | /* Argument checking already performed by the FPCOMPARE code */ |
2260 | ||
8bae0a0c | 2261 | #ifdef DEBUG |
53b9417e | 2262 | printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2263 | #endif /* DEBUG */ |
2264 | ||
8bae0a0c JSC |
2265 | /* The format type should already have been checked: */ |
2266 | switch (fmt) { | |
2267 | case fmt_single: | |
2268 | { | |
76ef4165 FL |
2269 | sim_fpu wop1; |
2270 | sim_fpu wop2; | |
2271 | sim_fpu_32to (&wop1, op1); | |
2272 | sim_fpu_32to (&wop2, op2); | |
2273 | boolean = sim_fpu_is_lt (&wop1, &wop2); | |
2274 | break; | |
8bae0a0c | 2275 | } |
8bae0a0c | 2276 | case fmt_double: |
76ef4165 FL |
2277 | { |
2278 | sim_fpu wop1; | |
2279 | sim_fpu wop2; | |
2280 | sim_fpu_64to (&wop1, op1); | |
2281 | sim_fpu_64to (&wop2, op2); | |
2282 | boolean = sim_fpu_is_lt (&wop1, &wop2); | |
2283 | break; | |
2284 | } | |
50a2a691 AC |
2285 | default: |
2286 | fprintf (stderr, "Bad switch\n"); | |
2287 | abort (); | |
8bae0a0c JSC |
2288 | } |
2289 | ||
2290 | #ifdef DEBUG | |
2291 | printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2292 | #endif /* DEBUG */ | |
2293 | ||
2294 | return(boolean); | |
2295 | } | |
2296 | ||
18c64df6 | 2297 | int |
8bae0a0c | 2298 | Equal(op1,op2,fmt) |
e871dd18 JSC |
2299 | uword64 op1; |
2300 | uword64 op2; | |
8bae0a0c JSC |
2301 | FP_formats fmt; |
2302 | { | |
2303 | int boolean = 0; | |
2304 | ||
e871dd18 JSC |
2305 | /* Argument checking already performed by the FPCOMPARE code */ |
2306 | ||
8bae0a0c | 2307 | #ifdef DEBUG |
53b9417e | 2308 | printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2309 | #endif /* DEBUG */ |
2310 | ||
8bae0a0c JSC |
2311 | /* The format type should already have been checked: */ |
2312 | switch (fmt) { | |
2313 | case fmt_single: | |
76ef4165 FL |
2314 | { |
2315 | sim_fpu wop1; | |
2316 | sim_fpu wop2; | |
2317 | sim_fpu_32to (&wop1, op1); | |
2318 | sim_fpu_32to (&wop2, op2); | |
2319 | boolean = sim_fpu_is_eq (&wop1, &wop2); | |
2320 | break; | |
2321 | } | |
8bae0a0c | 2322 | case fmt_double: |
76ef4165 FL |
2323 | { |
2324 | sim_fpu wop1; | |
2325 | sim_fpu wop2; | |
2326 | sim_fpu_64to (&wop1, op1); | |
2327 | sim_fpu_64to (&wop2, op2); | |
2328 | boolean = sim_fpu_is_eq (&wop1, &wop2); | |
2329 | break; | |
2330 | } | |
50a2a691 AC |
2331 | default: |
2332 | fprintf (stderr, "Bad switch\n"); | |
2333 | abort (); | |
8bae0a0c JSC |
2334 | } |
2335 | ||
2336 | #ifdef DEBUG | |
2337 | printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt)); | |
2338 | #endif /* DEBUG */ | |
2339 | ||
2340 | return(boolean); | |
2341 | } | |
2342 | ||
18c64df6 | 2343 | uword64 |
a9f7253f JSC |
2344 | AbsoluteValue(op,fmt) |
2345 | uword64 op; | |
2346 | FP_formats fmt; | |
2347 | { | |
50a2a691 | 2348 | uword64 result = 0; |
a9f7253f JSC |
2349 | |
2350 | #ifdef DEBUG | |
53b9417e | 2351 | printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
a9f7253f JSC |
2352 | #endif /* DEBUG */ |
2353 | ||
2354 | /* The format type should already have been checked: */ | |
2355 | switch (fmt) { | |
2356 | case fmt_single: | |
2357 | { | |
76ef4165 FL |
2358 | sim_fpu wop; |
2359 | unsigned32 ans; | |
2360 | sim_fpu_32to (&wop, op); | |
2361 | sim_fpu_abs (&wop, &wop); | |
2362 | sim_fpu_to32 (&ans, &wop); | |
2363 | result = ans; | |
2364 | break; | |
a9f7253f | 2365 | } |
a9f7253f JSC |
2366 | case fmt_double: |
2367 | { | |
76ef4165 FL |
2368 | sim_fpu wop; |
2369 | unsigned64 ans; | |
2370 | sim_fpu_64to (&wop, op); | |
2371 | sim_fpu_abs (&wop, &wop); | |
2372 | sim_fpu_to64 (&ans, &wop); | |
2373 | result = ans; | |
2374 | break; | |
a9f7253f | 2375 | } |
50a2a691 AC |
2376 | default: |
2377 | fprintf (stderr, "Bad switch\n"); | |
2378 | abort (); | |
a9f7253f JSC |
2379 | } |
2380 | ||
2381 | return(result); | |
2382 | } | |
2383 | ||
18c64df6 | 2384 | uword64 |
8bae0a0c | 2385 | Negate(op,fmt) |
e871dd18 | 2386 | uword64 op; |
8bae0a0c JSC |
2387 | FP_formats fmt; |
2388 | { | |
50a2a691 | 2389 | uword64 result = 0; |
8bae0a0c JSC |
2390 | |
2391 | #ifdef DEBUG | |
53b9417e | 2392 | printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2393 | #endif /* DEBUG */ |
2394 | ||
2395 | /* The format type should already have been checked: */ | |
2396 | switch (fmt) { | |
2397 | case fmt_single: | |
2398 | { | |
76ef4165 FL |
2399 | sim_fpu wop; |
2400 | unsigned32 ans; | |
2401 | sim_fpu_32to (&wop, op); | |
2402 | sim_fpu_neg (&wop, &wop); | |
2403 | sim_fpu_to32 (&ans, &wop); | |
2404 | result = ans; | |
2405 | break; | |
8bae0a0c | 2406 | } |
8bae0a0c JSC |
2407 | case fmt_double: |
2408 | { | |
76ef4165 FL |
2409 | sim_fpu wop; |
2410 | unsigned64 ans; | |
2411 | sim_fpu_64to (&wop, op); | |
2412 | sim_fpu_neg (&wop, &wop); | |
2413 | sim_fpu_to64 (&ans, &wop); | |
2414 | result = ans; | |
2415 | break; | |
8bae0a0c | 2416 | } |
50a2a691 AC |
2417 | default: |
2418 | fprintf (stderr, "Bad switch\n"); | |
2419 | abort (); | |
8bae0a0c JSC |
2420 | } |
2421 | ||
2422 | return(result); | |
2423 | } | |
2424 | ||
18c64df6 | 2425 | uword64 |
8bae0a0c | 2426 | Add(op1,op2,fmt) |
e871dd18 JSC |
2427 | uword64 op1; |
2428 | uword64 op2; | |
8bae0a0c JSC |
2429 | FP_formats fmt; |
2430 | { | |
50a2a691 | 2431 | uword64 result = 0; |
8bae0a0c JSC |
2432 | |
2433 | #ifdef DEBUG | |
53b9417e | 2434 | printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2435 | #endif /* DEBUG */ |
2436 | ||
e871dd18 JSC |
2437 | /* The registers must specify FPRs valid for operands of type |
2438 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2439 | |
2440 | /* The format type should already have been checked: */ | |
2441 | switch (fmt) { | |
2442 | case fmt_single: | |
2443 | { | |
76ef4165 FL |
2444 | sim_fpu wop1; |
2445 | sim_fpu wop2; | |
2446 | sim_fpu ans; | |
2447 | unsigned32 res; | |
2448 | sim_fpu_32to (&wop1, op1); | |
2449 | sim_fpu_32to (&wop2, op2); | |
2450 | sim_fpu_add (&ans, &wop1, &wop2); | |
2451 | sim_fpu_to32 (&res, &ans); | |
2452 | result = res; | |
2453 | break; | |
8bae0a0c | 2454 | } |
8bae0a0c JSC |
2455 | case fmt_double: |
2456 | { | |
76ef4165 FL |
2457 | sim_fpu wop1; |
2458 | sim_fpu wop2; | |
2459 | sim_fpu ans; | |
2460 | unsigned64 res; | |
2461 | sim_fpu_64to (&wop1, op1); | |
2462 | sim_fpu_64to (&wop2, op2); | |
2463 | sim_fpu_add (&ans, &wop1, &wop2); | |
2464 | sim_fpu_to64 (&res, &ans); | |
2465 | result = res; | |
2466 | break; | |
8bae0a0c | 2467 | } |
50a2a691 AC |
2468 | default: |
2469 | fprintf (stderr, "Bad switch\n"); | |
2470 | abort (); | |
8bae0a0c JSC |
2471 | } |
2472 | ||
2473 | #ifdef DEBUG | |
53b9417e | 2474 | printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2475 | #endif /* DEBUG */ |
2476 | ||
2477 | return(result); | |
2478 | } | |
2479 | ||
18c64df6 | 2480 | uword64 |
8bae0a0c | 2481 | Sub(op1,op2,fmt) |
e871dd18 JSC |
2482 | uword64 op1; |
2483 | uword64 op2; | |
8bae0a0c JSC |
2484 | FP_formats fmt; |
2485 | { | |
50a2a691 | 2486 | uword64 result = 0; |
8bae0a0c JSC |
2487 | |
2488 | #ifdef DEBUG | |
53b9417e | 2489 | printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2490 | #endif /* DEBUG */ |
2491 | ||
e871dd18 JSC |
2492 | /* The registers must specify FPRs valid for operands of type |
2493 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2494 | |
2495 | /* The format type should already have been checked: */ | |
2496 | switch (fmt) { | |
2497 | case fmt_single: | |
2498 | { | |
76ef4165 FL |
2499 | sim_fpu wop1; |
2500 | sim_fpu wop2; | |
2501 | sim_fpu ans; | |
2502 | unsigned32 res; | |
2503 | sim_fpu_32to (&wop1, op1); | |
2504 | sim_fpu_32to (&wop2, op2); | |
2505 | sim_fpu_sub (&ans, &wop1, &wop2); | |
2506 | sim_fpu_to32 (&res, &ans); | |
2507 | result = res; | |
8bae0a0c JSC |
2508 | } |
2509 | break; | |
2510 | case fmt_double: | |
2511 | { | |
76ef4165 FL |
2512 | sim_fpu wop1; |
2513 | sim_fpu wop2; | |
2514 | sim_fpu ans; | |
2515 | unsigned64 res; | |
2516 | sim_fpu_64to (&wop1, op1); | |
2517 | sim_fpu_64to (&wop2, op2); | |
2518 | sim_fpu_sub (&ans, &wop1, &wop2); | |
2519 | sim_fpu_to64 (&res, &ans); | |
2520 | result = res; | |
8bae0a0c JSC |
2521 | } |
2522 | break; | |
50a2a691 AC |
2523 | default: |
2524 | fprintf (stderr, "Bad switch\n"); | |
2525 | abort (); | |
8bae0a0c JSC |
2526 | } |
2527 | ||
2528 | #ifdef DEBUG | |
53b9417e | 2529 | printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2530 | #endif /* DEBUG */ |
2531 | ||
2532 | return(result); | |
2533 | } | |
2534 | ||
18c64df6 | 2535 | uword64 |
8bae0a0c | 2536 | Multiply(op1,op2,fmt) |
e871dd18 JSC |
2537 | uword64 op1; |
2538 | uword64 op2; | |
8bae0a0c JSC |
2539 | FP_formats fmt; |
2540 | { | |
50a2a691 | 2541 | uword64 result = 0; |
8bae0a0c JSC |
2542 | |
2543 | #ifdef DEBUG | |
53b9417e | 2544 | printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2545 | #endif /* DEBUG */ |
2546 | ||
e871dd18 JSC |
2547 | /* The registers must specify FPRs valid for operands of type |
2548 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2549 | |
2550 | /* The format type should already have been checked: */ | |
2551 | switch (fmt) { | |
2552 | case fmt_single: | |
2553 | { | |
76ef4165 FL |
2554 | sim_fpu wop1; |
2555 | sim_fpu wop2; | |
2556 | sim_fpu ans; | |
2557 | unsigned32 res; | |
2558 | sim_fpu_32to (&wop1, op1); | |
2559 | sim_fpu_32to (&wop2, op2); | |
2560 | sim_fpu_mul (&ans, &wop1, &wop2); | |
2561 | sim_fpu_to32 (&res, &ans); | |
2562 | result = res; | |
2563 | break; | |
8bae0a0c | 2564 | } |
8bae0a0c JSC |
2565 | case fmt_double: |
2566 | { | |
76ef4165 FL |
2567 | sim_fpu wop1; |
2568 | sim_fpu wop2; | |
2569 | sim_fpu ans; | |
2570 | unsigned64 res; | |
2571 | sim_fpu_64to (&wop1, op1); | |
2572 | sim_fpu_64to (&wop2, op2); | |
2573 | sim_fpu_mul (&ans, &wop1, &wop2); | |
2574 | sim_fpu_to64 (&res, &ans); | |
2575 | result = res; | |
2576 | break; | |
8bae0a0c | 2577 | } |
50a2a691 AC |
2578 | default: |
2579 | fprintf (stderr, "Bad switch\n"); | |
2580 | abort (); | |
8bae0a0c JSC |
2581 | } |
2582 | ||
2583 | #ifdef DEBUG | |
53b9417e | 2584 | printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2585 | #endif /* DEBUG */ |
2586 | ||
2587 | return(result); | |
2588 | } | |
2589 | ||
18c64df6 | 2590 | uword64 |
8bae0a0c | 2591 | Divide(op1,op2,fmt) |
e871dd18 JSC |
2592 | uword64 op1; |
2593 | uword64 op2; | |
8bae0a0c JSC |
2594 | FP_formats fmt; |
2595 | { | |
50a2a691 | 2596 | uword64 result = 0; |
8bae0a0c JSC |
2597 | |
2598 | #ifdef DEBUG | |
53b9417e | 2599 | printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2)); |
8bae0a0c JSC |
2600 | #endif /* DEBUG */ |
2601 | ||
e871dd18 JSC |
2602 | /* The registers must specify FPRs valid for operands of type |
2603 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2604 | |
2605 | /* The format type should already have been checked: */ | |
2606 | switch (fmt) { | |
2607 | case fmt_single: | |
2608 | { | |
76ef4165 FL |
2609 | sim_fpu wop1; |
2610 | sim_fpu wop2; | |
2611 | sim_fpu ans; | |
2612 | unsigned32 res; | |
2613 | sim_fpu_32to (&wop1, op1); | |
2614 | sim_fpu_32to (&wop2, op2); | |
2615 | sim_fpu_div (&ans, &wop1, &wop2); | |
2616 | sim_fpu_to32 (&res, &ans); | |
2617 | result = res; | |
2618 | break; | |
8bae0a0c | 2619 | } |
8bae0a0c JSC |
2620 | case fmt_double: |
2621 | { | |
76ef4165 FL |
2622 | sim_fpu wop1; |
2623 | sim_fpu wop2; | |
2624 | sim_fpu ans; | |
2625 | unsigned64 res; | |
2626 | sim_fpu_64to (&wop1, op1); | |
2627 | sim_fpu_64to (&wop2, op2); | |
2628 | sim_fpu_div (&ans, &wop1, &wop2); | |
2629 | sim_fpu_to64 (&res, &ans); | |
2630 | result = res; | |
2631 | break; | |
8bae0a0c | 2632 | } |
50a2a691 AC |
2633 | default: |
2634 | fprintf (stderr, "Bad switch\n"); | |
2635 | abort (); | |
8bae0a0c JSC |
2636 | } |
2637 | ||
2638 | #ifdef DEBUG | |
53b9417e | 2639 | printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2640 | #endif /* DEBUG */ |
2641 | ||
2642 | return(result); | |
2643 | } | |
2644 | ||
18c64df6 | 2645 | uword64 UNUSED |
8bae0a0c | 2646 | Recip(op,fmt) |
e871dd18 | 2647 | uword64 op; |
8bae0a0c JSC |
2648 | FP_formats fmt; |
2649 | { | |
50a2a691 | 2650 | uword64 result = 0; |
8bae0a0c JSC |
2651 | |
2652 | #ifdef DEBUG | |
53b9417e | 2653 | printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2654 | #endif /* DEBUG */ |
2655 | ||
e871dd18 JSC |
2656 | /* The registers must specify FPRs valid for operands of type |
2657 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2658 | |
2659 | /* The format type should already have been checked: */ | |
2660 | switch (fmt) { | |
2661 | case fmt_single: | |
2662 | { | |
76ef4165 FL |
2663 | sim_fpu wop; |
2664 | sim_fpu ans; | |
2665 | unsigned32 res; | |
2666 | sim_fpu_32to (&wop, op); | |
2667 | sim_fpu_inv (&ans, &wop); | |
2668 | sim_fpu_to32 (&res, &ans); | |
2669 | result = res; | |
2670 | break; | |
8bae0a0c | 2671 | } |
8bae0a0c JSC |
2672 | case fmt_double: |
2673 | { | |
76ef4165 FL |
2674 | sim_fpu wop; |
2675 | sim_fpu ans; | |
2676 | unsigned64 res; | |
2677 | sim_fpu_64to (&wop, op); | |
2678 | sim_fpu_inv (&ans, &wop); | |
2679 | sim_fpu_to64 (&res, &ans); | |
2680 | result = res; | |
2681 | break; | |
8bae0a0c | 2682 | } |
50a2a691 AC |
2683 | default: |
2684 | fprintf (stderr, "Bad switch\n"); | |
2685 | abort (); | |
8bae0a0c JSC |
2686 | } |
2687 | ||
2688 | #ifdef DEBUG | |
53b9417e | 2689 | printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2690 | #endif /* DEBUG */ |
2691 | ||
2692 | return(result); | |
2693 | } | |
2694 | ||
18c64df6 | 2695 | uword64 |
8bae0a0c | 2696 | SquareRoot(op,fmt) |
e871dd18 | 2697 | uword64 op; |
8bae0a0c JSC |
2698 | FP_formats fmt; |
2699 | { | |
50a2a691 | 2700 | uword64 result = 0; |
8bae0a0c JSC |
2701 | |
2702 | #ifdef DEBUG | |
53b9417e | 2703 | printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op)); |
8bae0a0c JSC |
2704 | #endif /* DEBUG */ |
2705 | ||
e871dd18 JSC |
2706 | /* The registers must specify FPRs valid for operands of type |
2707 | "fmt". If they are not valid, the result is undefined. */ | |
8bae0a0c JSC |
2708 | |
2709 | /* The format type should already have been checked: */ | |
2710 | switch (fmt) { | |
2711 | case fmt_single: | |
2712 | { | |
76ef4165 FL |
2713 | sim_fpu wop; |
2714 | sim_fpu ans; | |
2715 | unsigned32 res; | |
2716 | sim_fpu_32to (&wop, op); | |
2717 | sim_fpu_sqrt (&ans, &wop); | |
2718 | sim_fpu_to32 (&res, &ans); | |
2719 | result = res; | |
2720 | break; | |
8bae0a0c | 2721 | } |
8bae0a0c JSC |
2722 | case fmt_double: |
2723 | { | |
76ef4165 FL |
2724 | sim_fpu wop; |
2725 | sim_fpu ans; | |
2726 | unsigned64 res; | |
2727 | sim_fpu_64to (&wop, op); | |
2728 | sim_fpu_sqrt (&ans, &wop); | |
2729 | sim_fpu_to64 (&res, &ans); | |
2730 | result = res; | |
2731 | break; | |
8bae0a0c | 2732 | } |
50a2a691 AC |
2733 | default: |
2734 | fprintf (stderr, "Bad switch\n"); | |
2735 | abort (); | |
8bae0a0c JSC |
2736 | } |
2737 | ||
2738 | #ifdef DEBUG | |
53b9417e | 2739 | printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt)); |
8bae0a0c JSC |
2740 | #endif /* DEBUG */ |
2741 | ||
2742 | return(result); | |
2743 | } | |
2744 | ||
18c64df6 | 2745 | uword64 |
01737f42 AC |
2746 | convert (SIM_DESC sd, |
2747 | sim_cpu *cpu, | |
2748 | address_word cia, | |
2749 | int rm, | |
2750 | uword64 op, | |
2751 | FP_formats from, | |
2752 | FP_formats to) | |
8bae0a0c | 2753 | { |
76ef4165 FL |
2754 | sim_fpu wop; |
2755 | sim_fpu_round round; | |
2756 | unsigned32 result32; | |
2757 | unsigned64 result64; | |
8bae0a0c JSC |
2758 | |
2759 | #ifdef DEBUG | |
53b9417e | 2760 | printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC)); |
8bae0a0c JSC |
2761 | #endif /* DEBUG */ |
2762 | ||
76ef4165 | 2763 | switch (rm) |
8bae0a0c | 2764 | { |
76ef4165 FL |
2765 | case FP_RM_NEAREST: |
2766 | /* Round result to nearest representable value. When two | |
2767 | representable values are equally near, round to the value | |
2768 | that has a least significant bit of zero (i.e. is even). */ | |
2769 | round = sim_fpu_round_near; | |
2770 | break; | |
2771 | case FP_RM_TOZERO: | |
2772 | /* Round result to the value closest to, and not greater in | |
2773 | magnitude than, the result. */ | |
2774 | round = sim_fpu_round_zero; | |
2775 | break; | |
2776 | case FP_RM_TOPINF: | |
2777 | /* Round result to the value closest to, and not less than, | |
2778 | the result. */ | |
2779 | round = sim_fpu_round_up; | |
2780 | break; | |
2781 | ||
2782 | case FP_RM_TOMINF: | |
2783 | /* Round result to the value closest to, and not greater than, | |
2784 | the result. */ | |
2785 | round = sim_fpu_round_down; | |
2786 | break; | |
2787 | default: | |
2788 | round = 0; | |
2789 | fprintf (stderr, "Bad switch\n"); | |
2790 | abort (); | |
8bae0a0c | 2791 | } |
76ef4165 FL |
2792 | |
2793 | /* Convert the input to sim_fpu internal format */ | |
2794 | switch (from) | |
8bae0a0c | 2795 | { |
76ef4165 FL |
2796 | case fmt_double: |
2797 | sim_fpu_64to (&wop, op); | |
2798 | break; | |
2799 | case fmt_single: | |
2800 | sim_fpu_32to (&wop, op); | |
2801 | break; | |
2802 | case fmt_word: | |
2803 | sim_fpu_i32to (&wop, op, round); | |
2804 | break; | |
2805 | case fmt_long: | |
2806 | sim_fpu_i64to (&wop, op, round); | |
2807 | break; | |
2808 | default: | |
2809 | fprintf (stderr, "Bad switch\n"); | |
2810 | abort (); | |
8bae0a0c | 2811 | } |
8bae0a0c | 2812 | |
76ef4165 FL |
2813 | /* Convert sim_fpu format into the output */ |
2814 | /* The value WOP is converted to the destination format, rounding | |
2815 | using mode RM. When the destination is a fixed-point format, then | |
2816 | a source value of Infinity, NaN or one which would round to an | |
2817 | integer outside the fixed point range then an IEEE Invalid | |
2818 | Operation condition is raised. */ | |
2819 | switch (to) | |
2820 | { | |
2821 | case fmt_single: | |
2822 | sim_fpu_round_32 (&wop, round, 0); | |
2823 | sim_fpu_to32 (&result32, &wop); | |
2824 | result64 = result32; | |
2825 | break; | |
2826 | case fmt_double: | |
2827 | sim_fpu_round_64 (&wop, round, 0); | |
2828 | sim_fpu_to64 (&result64, &wop); | |
2829 | break; | |
2830 | case fmt_word: | |
2831 | sim_fpu_to32i (&result32, &wop, round); | |
2832 | result64 = result32; | |
2833 | break; | |
2834 | case fmt_long: | |
2835 | sim_fpu_to64i (&result64, &wop, round); | |
2836 | break; | |
2837 | default: | |
2838 | result64 = 0; | |
2839 | fprintf (stderr, "Bad switch\n"); | |
2840 | abort (); | |
8bae0a0c | 2841 | } |
76ef4165 | 2842 | |
8bae0a0c | 2843 | #ifdef DEBUG |
76ef4165 | 2844 | printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to)); |
8bae0a0c JSC |
2845 | #endif /* DEBUG */ |
2846 | ||
76ef4165 | 2847 | return(result64); |
8bae0a0c JSC |
2848 | } |
2849 | #endif /* HASFPU */ | |
2850 | ||
76ef4165 | 2851 | |
8bae0a0c JSC |
2852 | /*-- co-processor support routines ------------------------------------------*/ |
2853 | ||
2f2e6c5d | 2854 | static int UNUSED |
8bae0a0c JSC |
2855 | CoProcPresent(coproc_number) |
2856 | unsigned int coproc_number; | |
2857 | { | |
2858 | /* Return TRUE if simulator provides a model for the given co-processor number */ | |
2859 | return(0); | |
2860 | } | |
2861 | ||
18c64df6 | 2862 | void |
01737f42 AC |
2863 | cop_lw (SIM_DESC sd, |
2864 | sim_cpu *cpu, | |
2865 | address_word cia, | |
2866 | int coproc_num, | |
2867 | int coproc_reg, | |
2868 | unsigned int memword) | |
8bae0a0c JSC |
2869 | { |
2870 | switch (coproc_num) { | |
2871 | #if defined(HASFPU) | |
2872 | case 1: | |
2873 | #ifdef DEBUG | |
53b9417e | 2874 | printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword)); |
8bae0a0c | 2875 | #endif |
da0bce9c | 2876 | StoreFPR(coproc_reg,fmt_word,(uword64)memword); |
0c2c5f61 | 2877 | FPR_STATE[coproc_reg] = fmt_uninterpreted; |
8bae0a0c JSC |
2878 | break; |
2879 | #endif /* HASFPU */ | |
2880 | ||
2881 | default: | |
f24b7b69 | 2882 | #if 0 /* this should be controlled by a configuration option */ |
95469ceb | 2883 | sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia)); |
f24b7b69 | 2884 | #endif |
8bae0a0c JSC |
2885 | break; |
2886 | } | |
2887 | ||
2888 | return; | |
2889 | } | |
2890 | ||
18c64df6 | 2891 | void |
01737f42 AC |
2892 | cop_ld (SIM_DESC sd, |
2893 | sim_cpu *cpu, | |
2894 | address_word cia, | |
2895 | int coproc_num, | |
2896 | int coproc_reg, | |
2897 | uword64 memword) | |
8bae0a0c JSC |
2898 | { |
2899 | switch (coproc_num) { | |
2900 | #if defined(HASFPU) | |
2901 | case 1: | |
2902 | StoreFPR(coproc_reg,fmt_uninterpreted,memword); | |
2903 | break; | |
2904 | #endif /* HASFPU */ | |
2905 | ||
2906 | default: | |
f24b7b69 | 2907 | #if 0 /* this message should be controlled by a configuration option */ |
95469ceb | 2908 | sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia)); |
f24b7b69 | 2909 | #endif |
8bae0a0c JSC |
2910 | break; |
2911 | } | |
2912 | ||
2913 | return; | |
2914 | } | |
2915 | ||
18c64df6 | 2916 | unsigned int |
01737f42 AC |
2917 | cop_sw (SIM_DESC sd, |
2918 | sim_cpu *cpu, | |
2919 | address_word cia, | |
2920 | int coproc_num, | |
2921 | int coproc_reg) | |
8bae0a0c JSC |
2922 | { |
2923 | unsigned int value = 0; | |
da0bce9c | 2924 | |
8bae0a0c JSC |
2925 | switch (coproc_num) { |
2926 | #if defined(HASFPU) | |
2927 | case 1: | |
2928 | #if 1 | |
9cb8397f GRK |
2929 | { |
2930 | FP_formats hold; | |
0c2c5f61 AC |
2931 | hold = FPR_STATE[coproc_reg]; |
2932 | FPR_STATE[coproc_reg] = fmt_word; | |
9cb8397f | 2933 | value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted); |
0c2c5f61 | 2934 | FPR_STATE[coproc_reg] = hold; |
9cb8397f | 2935 | } |
8bae0a0c JSC |
2936 | #else |
2937 | #if 1 | |
0c2c5f61 | 2938 | value = (unsigned int)ValueFPR(coproc_reg,FPR_STATE[coproc_reg]); |
8bae0a0c JSC |
2939 | #else |
2940 | #ifdef DEBUG | |
0c2c5f61 | 2941 | printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE[coproc_reg])); |
8bae0a0c JSC |
2942 | #endif /* DEBUG */ |
2943 | value = (unsigned int)ValueFPR(coproc_reg,fmt_single); | |
2944 | #endif | |
2945 | #endif | |
2946 | break; | |
2947 | #endif /* HASFPU */ | |
2948 | ||
2949 | default: | |
f24b7b69 | 2950 | #if 0 /* should be controlled by configuration option */ |
95469ceb | 2951 | sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); |
f24b7b69 | 2952 | #endif |
8bae0a0c JSC |
2953 | break; |
2954 | } | |
2955 | ||
2956 | return(value); | |
2957 | } | |
2958 | ||
18c64df6 | 2959 | uword64 |
01737f42 AC |
2960 | cop_sd (SIM_DESC sd, |
2961 | sim_cpu *cpu, | |
2962 | address_word cia, | |
2963 | int coproc_num, | |
2964 | int coproc_reg) | |
8bae0a0c | 2965 | { |
e871dd18 | 2966 | uword64 value = 0; |
8bae0a0c JSC |
2967 | switch (coproc_num) { |
2968 | #if defined(HASFPU) | |
2969 | case 1: | |
2970 | #if 1 | |
2971 | value = ValueFPR(coproc_reg,fmt_uninterpreted); | |
2972 | #else | |
2973 | #if 1 | |
0c2c5f61 | 2974 | value = ValueFPR(coproc_reg,FPR_STATE[coproc_reg]); |
8bae0a0c JSC |
2975 | #else |
2976 | #ifdef DEBUG | |
0c2c5f61 | 2977 | printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE[coproc_reg])); |
8bae0a0c JSC |
2978 | #endif /* DEBUG */ |
2979 | value = ValueFPR(coproc_reg,fmt_double); | |
2980 | #endif | |
2981 | #endif | |
2982 | break; | |
2983 | #endif /* HASFPU */ | |
2984 | ||
2985 | default: | |
f24b7b69 | 2986 | #if 0 /* should be controlled by configuration option */ |
95469ceb | 2987 | sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia)); |
f24b7b69 | 2988 | #endif |
8bae0a0c JSC |
2989 | break; |
2990 | } | |
2991 | ||
2992 | return(value); | |
2993 | } | |
2994 | ||
ea985d24 | 2995 | void |
01737f42 AC |
2996 | decode_coproc (SIM_DESC sd, |
2997 | sim_cpu *cpu, | |
2998 | address_word cia, | |
2999 | unsigned int instruction) | |
8bae0a0c JSC |
3000 | { |
3001 | int coprocnum = ((instruction >> 26) & 3); | |
3002 | ||
56e7c849 AC |
3003 | switch (coprocnum) |
3004 | { | |
8bae0a0c JSC |
3005 | case 0: /* standard CPU control and cache registers */ |
3006 | { | |
8bae0a0c JSC |
3007 | int code = ((instruction >> 21) & 0x1F); |
3008 | /* R4000 Users Manual (second edition) lists the following CP0 | |
3009 | instructions: | |
56e7c849 AC |
3010 | DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000) |
3011 | DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000) | |
3012 | MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000) | |
3013 | MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000) | |
3014 | TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001) | |
3015 | TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010) | |
3016 | TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110) | |
3017 | TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000) | |
3018 | CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii) | |
3019 | ERET Exception return (VR4100 = 01000010000000000000000000011000) | |
3020 | */ | |
3021 | if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0)) | |
3022 | { | |
3023 | int rt = ((instruction >> 16) & 0x1F); | |
3024 | int rd = ((instruction >> 11) & 0x1F); | |
3025 | ||
3026 | switch (rd) /* NOTEs: Standard CP0 registers */ | |
3027 | { | |
3028 | /* 0 = Index R4000 VR4100 VR4300 */ | |
3029 | /* 1 = Random R4000 VR4100 VR4300 */ | |
3030 | /* 2 = EntryLo0 R4000 VR4100 VR4300 */ | |
3031 | /* 3 = EntryLo1 R4000 VR4100 VR4300 */ | |
3032 | /* 4 = Context R4000 VR4100 VR4300 */ | |
3033 | /* 5 = PageMask R4000 VR4100 VR4300 */ | |
3034 | /* 6 = Wired R4000 VR4100 VR4300 */ | |
3035 | /* 8 = BadVAddr R4000 VR4100 VR4300 */ | |
3036 | /* 9 = Count R4000 VR4100 VR4300 */ | |
3037 | /* 10 = EntryHi R4000 VR4100 VR4300 */ | |
3038 | /* 11 = Compare R4000 VR4100 VR4300 */ | |
3039 | /* 12 = SR R4000 VR4100 VR4300 */ | |
3040 | case 12: | |
3041 | if (code == 0x00) | |
3042 | GPR[rt] = SR; | |
3043 | else | |
3044 | SR = GPR[rt]; | |
3045 | break; | |
3046 | /* 13 = Cause R4000 VR4100 VR4300 */ | |
05d1322f JL |
3047 | case 13: |
3048 | if (code == 0x00) | |
3049 | GPR[rt] = CAUSE; | |
3050 | else | |
3051 | CAUSE = GPR[rt]; | |
3052 | break; | |
56e7c849 AC |
3053 | /* 14 = EPC R4000 VR4100 VR4300 */ |
3054 | /* 15 = PRId R4000 VR4100 VR4300 */ | |
6eedf3f4 MA |
3055 | #ifdef SUBTARGET_R3900 |
3056 | /* 16 = Debug */ | |
3057 | case 16: | |
3058 | if (code == 0x00) | |
3059 | GPR[rt] = Debug; | |
3060 | else | |
3061 | Debug = GPR[rt]; | |
3062 | break; | |
3063 | #else | |
56e7c849 | 3064 | /* 16 = Config R4000 VR4100 VR4300 */ |
a09a30d2 AC |
3065 | case 16: |
3066 | if (code == 0x00) | |
3067 | GPR[rt] = C0_CONFIG; | |
3068 | else | |
3069 | C0_CONFIG = GPR[rt]; | |
3070 | break; | |
6eedf3f4 MA |
3071 | #endif |
3072 | #ifdef SUBTARGET_R3900 | |
3073 | /* 17 = Debug */ | |
3074 | case 17: | |
3075 | if (code == 0x00) | |
3076 | GPR[rt] = DEPC; | |
3077 | else | |
3078 | DEPC = GPR[rt]; | |
3079 | break; | |
3080 | #else | |
56e7c849 | 3081 | /* 17 = LLAddr R4000 VR4100 VR4300 */ |
6eedf3f4 | 3082 | #endif |
56e7c849 AC |
3083 | /* 18 = WatchLo R4000 VR4100 VR4300 */ |
3084 | /* 19 = WatchHi R4000 VR4100 VR4300 */ | |
3085 | /* 20 = XContext R4000 VR4100 VR4300 */ | |
3086 | /* 26 = PErr or ECC R4000 VR4100 VR4300 */ | |
3087 | /* 27 = CacheErr R4000 VR4100 */ | |
3088 | /* 28 = TagLo R4000 VR4100 VR4300 */ | |
3089 | /* 29 = TagHi R4000 VR4100 VR4300 */ | |
3090 | /* 30 = ErrorEPC R4000 VR4100 VR4300 */ | |
3091 | GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */ | |
3092 | /* CPR[0,rd] = GPR[rt]; */ | |
3093 | default: | |
3094 | if (code == 0x00) | |
18c64df6 | 3095 | sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 | 3096 | else |
18c64df6 | 3097 | sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd); |
56e7c849 AC |
3098 | } |
3099 | } | |
3100 | else if (code == 0x10 && (instruction & 0x3f) == 0x18) | |
3101 | { | |
3102 | /* ERET */ | |
3103 | if (SR & status_ERL) | |
3104 | { | |
3105 | /* Oops, not yet available */ | |
18c64df6 | 3106 | sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet"); |
56e7c849 AC |
3107 | PC = EPC; |
3108 | SR &= ~status_ERL; | |
3109 | } | |
3110 | else | |
3111 | { | |
3112 | PC = EPC; | |
3113 | SR &= ~status_EXL; | |
3114 | } | |
3115 | } | |
6eedf3f4 MA |
3116 | else if (code == 0x10 && (instruction & 0x3f) == 0x10) |
3117 | { | |
3118 | /* RFE */ | |
3119 | } | |
3120 | else if (code == 0x10 && (instruction & 0x3f) == 0x1F) | |
3121 | { | |
3122 | /* DERET */ | |
3123 | Debug &= ~Debug_DM; | |
3124 | DELAYSLOT(); | |
3125 | DSPC = DEPC; | |
3126 | } | |
56e7c849 | 3127 | else |
95469ceb | 3128 | sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia)); |
e871dd18 | 3129 | /* TODO: When executing an ERET or RFE instruction we should |
8bae0a0c JSC |
3130 | clear LLBIT, to ensure that any out-standing atomic |
3131 | read/modify/write sequence fails. */ | |
3132 | } | |
56e7c849 AC |
3133 | break; |
3134 | ||
8bae0a0c | 3135 | case 2: /* undefined co-processor */ |
95469ceb | 3136 | sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia)); |
8bae0a0c | 3137 | break; |
56e7c849 | 3138 | |
8bae0a0c JSC |
3139 | case 1: /* should not occur (FPU co-processor) */ |
3140 | case 3: /* should not occur (FPU co-processor) */ | |
3141 | SignalException(ReservedInstruction,instruction); | |
3142 | break; | |
56e7c849 AC |
3143 | } |
3144 | ||
8bae0a0c JSC |
3145 | return; |
3146 | } | |
3147 | ||
3148 | /*-- instruction simulation -------------------------------------------------*/ | |
3149 | ||
16bd5d6e AC |
3150 | /* When the IGEN simulator is being built, the function below is be |
3151 | replaced by a generated version. However, WITH_IGEN == 2 indicates | |
3152 | that the fubction below should be compiled but under a different | |
3153 | name (to allow backward compatibility) */ | |
3154 | ||
3155 | #if (WITH_IGEN != 1) | |
3156 | #if (WITH_IGEN > 1) | |
dad6f1f3 AC |
3157 | void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal)); |
3158 | void | |
9ec6741b | 3159 | old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal) |
dad6f1f3 | 3160 | #else |
2e61a3ad | 3161 | void |
9ec6741b | 3162 | sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal) |
dad6f1f3 | 3163 | #endif |
2e61a3ad AC |
3164 | SIM_DESC sd; |
3165 | int next_cpu_nr; /* ignore */ | |
9ec6741b | 3166 | int nr_cpus; /* ignore */ |
2e61a3ad | 3167 | int siggnal; /* ignore */ |
8bae0a0c | 3168 | { |
01737f42 | 3169 | sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */ |
50a2a691 | 3170 | #if !defined(FASTSIM) |
8bae0a0c | 3171 | unsigned int pipeline_count = 1; |
50a2a691 | 3172 | #endif |
8bae0a0c JSC |
3173 | |
3174 | #ifdef DEBUG | |
50a2a691 | 3175 | if (STATE_MEMORY (sd) == NULL) { |
8bae0a0c JSC |
3176 | printf("DBG: simulate() entered with no memory\n"); |
3177 | exit(1); | |
3178 | } | |
3179 | #endif /* DEBUG */ | |
3180 | ||
3181 | #if 0 /* Disabled to check that everything works OK */ | |
3182 | /* The VR4300 seems to sign-extend the PC on its first | |
3183 | access. However, this may just be because it is currently | |
3184 | configured in 32bit mode. However... */ | |
3185 | PC = SIGNEXTEND(PC,32); | |
3186 | #endif | |
3187 | ||
3188 | /* main controlling loop */ | |
2e61a3ad | 3189 | while (1) { |
7ce8b917 AC |
3190 | /* vaddr is slowly being replaced with cia - current instruction |
3191 | address */ | |
3192 | address_word cia = (uword64)PC; | |
3193 | address_word vaddr = cia; | |
dad6f1f3 | 3194 | address_word paddr; |
8bae0a0c | 3195 | int cca; |
53b9417e | 3196 | unsigned int instruction; /* uword64? what's this used for? FIXME! */ |
8bae0a0c JSC |
3197 | |
3198 | #ifdef DEBUG | |
3199 | { | |
3200 | printf("DBG: state = 0x%08X :",state); | |
8bae0a0c JSC |
3201 | if (state & simHALTEX) printf(" simHALTEX"); |
3202 | if (state & simHALTIN) printf(" simHALTIN"); | |
53b9417e | 3203 | printf("\n"); |
8bae0a0c JSC |
3204 | } |
3205 | #endif /* DEBUG */ | |
3206 | ||
0c2c5f61 | 3207 | DSSTATE = (STATE & simDELAYSLOT); |
8bae0a0c JSC |
3208 | #ifdef DEBUG |
3209 | if (dsstate) | |
18c64df6 | 3210 | sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3211 | #endif /* DEBUG */ |
3212 | ||
7ce8b917 AC |
3213 | /* Fetch the next instruction from the simulator memory: */ |
3214 | if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { | |
6429b296 JW |
3215 | if ((vaddr & 1) == 0) { |
3216 | /* Copy the action of the LW instruction */ | |
3217 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0); | |
3218 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0); | |
3219 | uword64 value; | |
3220 | unsigned int byte; | |
3221 | paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2))); | |
53b9417e | 3222 | LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL); |
6429b296 JW |
3223 | byte = ((vaddr & LOADDRMASK) ^ (bigend << 2)); |
3224 | instruction = ((value >> (8 * byte)) & 0xFFFFFFFF); | |
3225 | } else { | |
3226 | /* Copy the action of the LH instruction */ | |
3227 | unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0); | |
3228 | unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0); | |
3229 | uword64 value; | |
3230 | unsigned int byte; | |
3231 | paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK) | |
3232 | | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1))); | |
53b9417e | 3233 | LoadMemory(&value,NULL,cca, AccessLength_HALFWORD, |
6429b296 JW |
3234 | paddr & ~ (uword64) 1, |
3235 | vaddr, isINSTRUCTION, isREAL); | |
3236 | byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1)); | |
3237 | instruction = ((value >> (8 * byte)) & 0xFFFF); | |
3238 | } | |
8bae0a0c | 3239 | } else { |
53b9417e | 3240 | fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC)); |
8bae0a0c JSC |
3241 | exit(1); |
3242 | } | |
3243 | ||
3244 | #ifdef DEBUG | |
18c64df6 | 3245 | sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC)); |
8bae0a0c JSC |
3246 | #endif /* DEBUG */ |
3247 | ||
8bae0a0c JSC |
3248 | /* This is required by exception processing, to ensure that we can |
3249 | cope with exceptions in the delay slots of branches that may | |
3250 | already have changed the PC. */ | |
6429b296 JW |
3251 | if ((vaddr & 1) == 0) |
3252 | PC += 4; /* increment ready for the next fetch */ | |
3253 | else | |
3254 | PC += 2; | |
8bae0a0c JSC |
3255 | /* NOTE: If we perform a delay slot change to the PC, this |
3256 | increment is not requuired. However, it would make the | |
3257 | simulator more complicated to try and avoid this small hit. */ | |
3258 | ||
3259 | /* Currently this code provides a simple model. For more | |
3260 | complicated models we could perform exception status checks at | |
3261 | this point, and set the simSTOP state as required. This could | |
3262 | also include processing any hardware interrupts raised by any | |
3263 | I/O model attached to the simulator context. | |
3264 | ||
3265 | Support for "asynchronous" I/O events within the simulated world | |
3266 | could be providing by managing a counter, and calling a I/O | |
3267 | specific handler when a particular threshold is reached. On most | |
3268 | architectures a decrement and check for zero operation is | |
3269 | usually quicker than an increment and compare. However, the | |
3270 | process of managing a known value decrement to zero, is higher | |
3271 | than the cost of using an explicit value UINT_MAX into the | |
3272 | future. Which system is used will depend on how complicated the | |
3273 | I/O model is, and how much it is likely to affect the simulator | |
3274 | bandwidth. | |
3275 | ||
3276 | If events need to be scheduled further in the future than | |
3277 | UINT_MAX event ticks, then the I/O model should just provide its | |
3278 | own counter, triggered from the event system. */ | |
3279 | ||
3280 | /* MIPS pipeline ticks. To allow for future support where the | |
3281 | pipeline hit of individual instructions is known, this control | |
3282 | loop manages a "pipeline_count" variable. It is initialised to | |
3283 | 1 (one), and will only be changed by the simulator engine when | |
3284 | executing an instruction. If the engine does not have access to | |
3285 | pipeline cycle count information then all instructions will be | |
3286 | treated as using a single cycle. NOTE: A standard system is not | |
3287 | provided by the default simulator because different MIPS | |
3288 | architectures have different cycle counts for the same | |
50a2a691 AC |
3289 | instructions. |
3290 | ||
3291 | [NOTE: pipeline_count has been replaced the event queue] */ | |
8bae0a0c | 3292 | |
a09a30d2 AC |
3293 | /* shuffle the floating point status pipeline state */ |
3294 | ENGINE_ISSUE_PREFIX_HOOK(); | |
8bae0a0c JSC |
3295 | |
3296 | /* NOTE: For multi-context simulation environments the "instruction" | |
3297 | variable should be local to this routine. */ | |
3298 | ||
3299 | /* Shorthand accesses for engine. Note: If we wanted to use global | |
3300 | variables (and a single-threaded simulator engine), then we can | |
3301 | create the actual variables with these names. */ | |
3302 | ||
0c2c5f61 | 3303 | if (!(STATE & simSKIPNEXT)) { |
8bae0a0c | 3304 | /* Include the simulator engine */ |
284e759d | 3305 | #include "oengine.c" |
f24b7b69 | 3306 | #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT) |
8bae0a0c JSC |
3307 | #error "Mismatch between run-time simulator code and simulation engine" |
3308 | #endif | |
18c64df6 AC |
3309 | #if (WITH_TARGET_WORD_BITSIZE != GPRLEN) |
3310 | #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN" | |
3311 | #endif | |
76ef4165 | 3312 | #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU)) |
18c64df6 AC |
3313 | #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU" |
3314 | #endif | |
8bae0a0c JSC |
3315 | |
3316 | #if defined(WARN_LOHI) | |
3317 | /* Decrement the HI/LO validity ticks */ | |
3318 | if (HIACCESS > 0) | |
3319 | HIACCESS--; | |
3320 | if (LOACCESS > 0) | |
3321 | LOACCESS--; | |
0425cfb3 | 3322 | /* start-sanitize-r5900 */ |
53b9417e DE |
3323 | if (HI1ACCESS > 0) |
3324 | HI1ACCESS--; | |
3325 | if (LO1ACCESS > 0) | |
3326 | LO1ACCESS--; | |
0425cfb3 | 3327 | /* end-sanitize-r5900 */ |
8bae0a0c JSC |
3328 | #endif /* WARN_LOHI */ |
3329 | ||
8bae0a0c JSC |
3330 | /* For certain MIPS architectures, GPR[0] is hardwired to zero. We |
3331 | should check for it being changed. It is better doing it here, | |
3332 | than within the simulator, since it will help keep the simulator | |
3333 | small. */ | |
3334 | if (ZERO != 0) { | |
05d1322f | 3335 | #if defined(WARN_ZERO) |
95469ceb | 3336 | sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia)); |
05d1322f | 3337 | #endif /* WARN_ZERO */ |
8bae0a0c JSC |
3338 | ZERO = 0; /* reset back to zero before next instruction */ |
3339 | } | |
8bae0a0c | 3340 | } else /* simSKIPNEXT check */ |
0c2c5f61 | 3341 | STATE &= ~simSKIPNEXT; |
8bae0a0c JSC |
3342 | |
3343 | /* If the delay slot was active before the instruction is | |
3344 | executed, then update the PC to its new value: */ | |
0c2c5f61 | 3345 | if (DSSTATE) { |
8bae0a0c | 3346 | #ifdef DEBUG |
53b9417e | 3347 | printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC)); |
8bae0a0c JSC |
3348 | #endif /* DEBUG */ |
3349 | PC = DSPC; | |
6eedf3f4 | 3350 | CANCELDELAYSLOT(); |
8bae0a0c JSC |
3351 | } |
3352 | ||
3353 | if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */ | |
3354 | /* Deal with pending register updates: */ | |
3355 | #ifdef DEBUG | |
3356 | printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total); | |
3357 | #endif /* DEBUG */ | |
0c2c5f61 | 3358 | if (PENDING_OUT != PENDING_IN) { |
8bae0a0c | 3359 | int loop; |
0c2c5f61 AC |
3360 | int index = PENDING_OUT; |
3361 | int total = PENDING_TOTAL; | |
3362 | if (PENDING_TOTAL == 0) { | |
8bae0a0c JSC |
3363 | fprintf(stderr,"FATAL: Mis-match on pending update pointers\n"); |
3364 | exit(1); | |
3365 | } | |
3366 | for (loop = 0; (loop < total); loop++) { | |
3367 | #ifdef DEBUG | |
3368 | printf("DBG: BEFORE index = %d, loop = %d\n",index,loop); | |
3369 | #endif /* DEBUG */ | |
0c2c5f61 | 3370 | if (PENDING_SLOT_REG[index] != (LAST_EMBED_REGNUM + 1)) { |
8bae0a0c | 3371 | #ifdef DEBUG |
0c2c5f61 | 3372 | printf("pending_slot_count[%d] = %d\n",index,PENDING_SLOT_COUNT[index]); |
8bae0a0c | 3373 | #endif /* DEBUG */ |
0c2c5f61 | 3374 | if (--(PENDING_SLOT_COUNT[index]) == 0) { |
8bae0a0c | 3375 | #ifdef DEBUG |
0c2c5f61 AC |
3376 | printf("pending_slot_reg[%d] = %d\n",index,PENDING_SLOT_REG[index]); |
3377 | printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(PENDING_SLOT_VALUE[index])); | |
8bae0a0c | 3378 | #endif /* DEBUG */ |
0c2c5f61 | 3379 | if (PENDING_SLOT_REG[index] == COCIDX) { |
9cb8397f | 3380 | #if defined(HASFPU) |
8bae0a0c | 3381 | SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0)); |
9cb8397f GRK |
3382 | #else |
3383 | ; | |
3384 | #endif | |
8bae0a0c | 3385 | } else { |
0c2c5f61 | 3386 | REGISTERS[PENDING_SLOT_REG[index]] = PENDING_SLOT_VALUE[index]; |
8bae0a0c JSC |
3387 | #if defined(HASFPU) |
3388 | /* The only time we have PENDING updates to FPU | |
3389 | registers, is when performing binary transfers. This | |
3390 | means we should update the register type field. */ | |
0c2c5f61 AC |
3391 | if ((PENDING_SLOT_REG[index] >= FGRIDX) && (PENDING_SLOT_REG[index] < (FGRIDX + 32))) |
3392 | FPR_STATE[PENDING_SLOT_REG[index] - FGRIDX] = fmt_uninterpreted; | |
8bae0a0c JSC |
3393 | #endif /* HASFPU */ |
3394 | } | |
3395 | #ifdef DEBUG | |
0c2c5f61 | 3396 | printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG[index],pr_addr(REGISTERS[PENDING_SLOT_REG[index]])); |
8bae0a0c | 3397 | #endif /* DEBUG */ |
0c2c5f61 AC |
3398 | PENDING_SLOT_REG[index] = (LAST_EMBED_REGNUM + 1); |
3399 | PENDING_OUT++; | |
3400 | if (PENDING_OUT == PSLOTS) | |
3401 | PENDING_OUT = 0; | |
3402 | PENDING_TOTAL--; | |
8bae0a0c JSC |
3403 | } |
3404 | } | |
3405 | #ifdef DEBUG | |
3406 | printf("DBG: AFTER index = %d, loop = %d\n",index,loop); | |
3407 | #endif /* DEBUG */ | |
3408 | index++; | |
3409 | if (index == PSLOTS) | |
3410 | index = 0; | |
3411 | } | |
3412 | } | |
3413 | #ifdef DEBUG | |
0c2c5f61 | 3414 | printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); |
8bae0a0c JSC |
3415 | #endif /* DEBUG */ |
3416 | } | |
3417 | ||
3418 | #if !defined(FASTSIM) | |
50a2a691 AC |
3419 | if (sim_events_tickn (sd, pipeline_count)) |
3420 | { | |
3421 | /* cpu->cia = cia; */ | |
3422 | sim_events_process (sd); | |
3423 | } | |
3424 | #else | |
2e61a3ad AC |
3425 | if (sim_events_tick (sd)) |
3426 | { | |
3427 | /* cpu->cia = cia; */ | |
3428 | sim_events_process (sd); | |
3429 | } | |
50a2a691 | 3430 | #endif /* FASTSIM */ |
8bae0a0c | 3431 | } |
8bae0a0c | 3432 | } |
16bd5d6e AC |
3433 | #endif |
3434 | ||
8bae0a0c | 3435 | |
53b9417e DE |
3436 | /* This code copied from gdb's utils.c. Would like to share this code, |
3437 | but don't know of a common place where both could get to it. */ | |
3438 | ||
3439 | /* Temporary storage using circular buffer */ | |
3440 | #define NUMCELLS 16 | |
3441 | #define CELLSIZE 32 | |
3442 | static char* | |
3443 | get_cell() | |
3444 | { | |
3445 | static char buf[NUMCELLS][CELLSIZE]; | |
3446 | static int cell=0; | |
3447 | if (++cell>=NUMCELLS) cell=0; | |
3448 | return buf[cell]; | |
3449 | } | |
3450 | ||
3451 | /* Print routines to handle variable size regs, etc */ | |
3452 | ||
3453 | /* Eliminate warning from compiler on 32-bit systems */ | |
3454 | static int thirty_two = 32; | |
3455 | ||
3456 | char* | |
3457 | pr_addr(addr) | |
3458 | SIM_ADDR addr; | |
3459 | { | |
3460 | char *paddr_str=get_cell(); | |
3461 | switch (sizeof(addr)) | |
3462 | { | |
3463 | case 8: | |
50a2a691 | 3464 | sprintf(paddr_str,"%08lx%08lx", |
53b9417e DE |
3465 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3466 | break; | |
3467 | case 4: | |
50a2a691 | 3468 | sprintf(paddr_str,"%08lx",(unsigned long)addr); |
53b9417e DE |
3469 | break; |
3470 | case 2: | |
3471 | sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff)); | |
3472 | break; | |
3473 | default: | |
3474 | sprintf(paddr_str,"%x",addr); | |
3475 | } | |
3476 | return paddr_str; | |
3477 | } | |
3478 | ||
87e43259 AC |
3479 | char* |
3480 | pr_uword64(addr) | |
3481 | uword64 addr; | |
3482 | { | |
3483 | char *paddr_str=get_cell(); | |
50a2a691 | 3484 | sprintf(paddr_str,"%08lx%08lx", |
87e43259 AC |
3485 | (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff)); |
3486 | return paddr_str; | |
3487 | } | |
3488 | ||
3489 | ||
8bae0a0c JSC |
3490 | /*---------------------------------------------------------------------------*/ |
3491 | /*> EOF interp.c <*/ |