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16bd5d6e AC |
1 | // |
2 | // MIPS Architecture: | |
3 | // | |
4 | // CPU Instruction Set (mips16) | |
5 | // | |
6 | ||
7 | // The instructions in this section are ordered according | |
8 | // to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf. | |
9 | ||
10 | ||
11 | // FIXME: Instead of having the code for mips16 instructions here. | |
12 | // these instructions should instead call the corresponding 32bit | |
13 | // instruction (or a function implementing that instructions code). | |
14 | ||
15 | ||
16 | // Load and Store Instructions | |
17 | ||
18 | ||
19 | 10000,xxx,ddd,55555:RRI:16::LB | |
20 | *mips16: | |
21 | { | |
22 | unsigned32 instruction = instruction_0; | |
23 | signed_word op1 = (instruction >> 8) & 0x7; | |
24 | int destreg = (instruction >> 5) & 0x7; | |
25 | int offset = (instruction >> 0) & 0x1f; | |
26 | if (op1 < 2) | |
27 | op1 += 16; | |
28 | op1 = GPR[op1]; | |
29 | if (destreg < 2) | |
30 | destreg += 16; | |
31 | if (have_extendval) | |
32 | { | |
33 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
34 | if (offset >= 0x8000) | |
35 | offset -= 0x10000; | |
36 | have_extendval = 0; | |
37 | } | |
38 | else | |
39 | { | |
40 | } | |
41 | if (have_extendval) | |
42 | SignalException (ReservedInstruction, instruction); | |
43 | { | |
44 | address_word vaddr = ((unsigned64)op1 + offset); | |
45 | address_word paddr; | |
46 | int uncached; | |
47 | { | |
48 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
49 | { | |
50 | unsigned64 memval = 0; | |
51 | unsigned64 memval1 = 0; | |
52 | unsigned64 mask = 0x7; | |
53 | unsigned int shift = 0; | |
54 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
55 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
56 | unsigned int byte; | |
57 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
58 | LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); | |
59 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
60 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8)); | |
61 | } | |
62 | } | |
63 | } | |
64 | } | |
65 | ||
66 | ||
67 | 10100,xxx,ddd,55555:RRI:16::LBU | |
68 | *mips16: | |
69 | { | |
70 | unsigned32 instruction = instruction_0; | |
71 | signed_word op1 = (instruction >> 8) & 0x7; | |
72 | int destreg = (instruction >> 5) & 0x7; | |
73 | int offset = (instruction >> 0) & 0x1f; | |
74 | if (op1 < 2) | |
75 | op1 += 16; | |
76 | op1 = GPR[op1]; | |
77 | if (destreg < 2) | |
78 | destreg += 16; | |
79 | if (have_extendval) | |
80 | { | |
81 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
82 | if (offset >= 0x8000) | |
83 | offset -= 0x10000; | |
84 | have_extendval = 0; | |
85 | } | |
86 | else | |
87 | { | |
88 | } | |
89 | if (have_extendval) | |
90 | SignalException (ReservedInstruction, instruction); | |
91 | { | |
92 | address_word vaddr = ((unsigned64)op1 + offset); | |
93 | address_word paddr; | |
94 | int uncached; | |
95 | { | |
96 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
97 | { | |
98 | unsigned64 memval = 0; | |
99 | unsigned64 memval1 = 0; | |
100 | unsigned64 mask = 0x7; | |
101 | unsigned int shift = 0; | |
102 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
103 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
104 | unsigned int byte; | |
105 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
106 | LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); | |
107 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
108 | GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF)); | |
109 | } | |
110 | } | |
111 | } | |
112 | } | |
113 | ||
114 | ||
115 | 10001,xxx,ddd,HHHHH:RRI:16::LH | |
116 | *mips16: | |
117 | { | |
118 | unsigned32 instruction = instruction_0; | |
119 | signed_word op1 = (instruction >> 8) & 0x7; | |
120 | int destreg = (instruction >> 5) & 0x7; | |
121 | int offset = (instruction >> 0) & 0x1f; | |
122 | if (op1 < 2) | |
123 | op1 += 16; | |
124 | op1 = GPR[op1]; | |
125 | if (destreg < 2) | |
126 | destreg += 16; | |
127 | if (have_extendval) | |
128 | { | |
129 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
130 | if (offset >= 0x8000) | |
131 | offset -= 0x10000; | |
132 | have_extendval = 0; | |
133 | } | |
134 | else | |
135 | { | |
136 | offset <<= 1; | |
137 | } | |
138 | if (have_extendval) | |
139 | SignalException (ReservedInstruction, instruction); | |
140 | { | |
141 | address_word vaddr = ((unsigned64)op1 + offset); | |
142 | address_word paddr; | |
143 | int uncached; | |
144 | if ((vaddr & 1) != 0) | |
145 | SignalExceptionAddressLoad(); | |
146 | else | |
147 | { | |
148 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
149 | { | |
150 | unsigned64 memval = 0; | |
151 | unsigned64 memval1 = 0; | |
152 | unsigned64 mask = 0x7; | |
153 | unsigned int shift = 1; | |
154 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
155 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
156 | unsigned int byte; | |
157 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
158 | LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); | |
159 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
160 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16)); | |
161 | } | |
162 | } | |
163 | } | |
164 | } | |
165 | ||
166 | ||
167 | 10101,xxx,ddd,HHHHH:RRI:16::LHU | |
168 | *mips16: | |
169 | { | |
170 | unsigned32 instruction = instruction_0; | |
171 | signed_word op1 = (instruction >> 8) & 0x7; | |
172 | int destreg = (instruction >> 5) & 0x7; | |
173 | int offset = (instruction >> 0) & 0x1f; | |
174 | if (op1 < 2) | |
175 | op1 += 16; | |
176 | op1 = GPR[op1]; | |
177 | if (destreg < 2) | |
178 | destreg += 16; | |
179 | if (have_extendval) | |
180 | { | |
181 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
182 | if (offset >= 0x8000) | |
183 | offset -= 0x10000; | |
184 | have_extendval = 0; | |
185 | } | |
186 | else | |
187 | { | |
188 | offset <<= 1; | |
189 | } | |
190 | if (have_extendval) | |
191 | SignalException (ReservedInstruction, instruction); | |
192 | { | |
193 | address_word vaddr = ((unsigned64)op1 + offset); | |
194 | address_word paddr; | |
195 | int uncached; | |
196 | if ((vaddr & 1) != 0) | |
197 | SignalExceptionAddressLoad(); | |
198 | else | |
199 | { | |
200 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
201 | { | |
202 | unsigned64 memval = 0; | |
203 | unsigned64 memval1 = 0; | |
204 | unsigned64 mask = 0x7; | |
205 | unsigned int shift = 1; | |
206 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
207 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
208 | unsigned int byte; | |
209 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
210 | LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); | |
211 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
212 | GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF)); | |
213 | } | |
214 | } | |
215 | } | |
216 | } | |
217 | ||
218 | ||
219 | 10011,xxx,ddd,WWWWW:RRI:16::LW | |
220 | *mips16: | |
221 | { | |
222 | unsigned32 instruction = instruction_0; | |
223 | signed_word op1 = (instruction >> 8) & 0x7; | |
224 | int destreg = (instruction >> 5) & 0x7; | |
225 | int offset = (instruction >> 0) & 0x1f; | |
226 | if (op1 < 2) | |
227 | op1 += 16; | |
228 | op1 = GPR[op1]; | |
229 | if (destreg < 2) | |
230 | destreg += 16; | |
231 | if (have_extendval) | |
232 | { | |
233 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
234 | if (offset >= 0x8000) | |
235 | offset -= 0x10000; | |
236 | have_extendval = 0; | |
237 | } | |
238 | else | |
239 | { | |
240 | offset <<= 2; | |
241 | } | |
242 | if (have_extendval) | |
243 | SignalException (ReservedInstruction, instruction); | |
244 | { | |
245 | address_word vaddr = ((unsigned64)op1 + offset); | |
246 | address_word paddr; | |
247 | int uncached; | |
248 | if ((vaddr & 3) != 0) | |
249 | SignalExceptionAddressLoad(); | |
250 | else | |
251 | { | |
252 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
253 | { | |
254 | unsigned64 memval = 0; | |
255 | unsigned64 memval1 = 0; | |
256 | unsigned64 mask = 0x7; | |
257 | unsigned int shift = 2; | |
258 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
259 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
260 | unsigned int byte; | |
261 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
262 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
263 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
264 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); | |
265 | } | |
266 | } | |
267 | } | |
268 | } | |
269 | ||
270 | ||
271 | 10110,ddd,VVVVVVVV,P:RI:16::LWPC | |
272 | *mips16: | |
273 | { | |
274 | unsigned32 instruction = instruction_0; | |
275 | int destreg = (instruction >> 8) & 0x7; | |
276 | int offset = (instruction >> 0) & 0xff; | |
277 | signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3; | |
278 | if (destreg < 2) | |
279 | destreg += 16; | |
280 | if (have_extendval) | |
281 | { | |
282 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
283 | if (offset >= 0x8000) | |
284 | offset -= 0x10000; | |
285 | have_extendval = 0; | |
286 | } | |
287 | else | |
288 | { | |
289 | offset <<= 2; | |
290 | } | |
291 | if (have_extendval) | |
292 | SignalException (ReservedInstruction, instruction); | |
293 | { | |
294 | address_word vaddr = ((unsigned64)op1 + offset); | |
295 | address_word paddr; | |
296 | int uncached; | |
297 | if ((vaddr & 3) != 0) | |
298 | SignalExceptionAddressLoad(); | |
299 | else | |
300 | { | |
301 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
302 | { | |
303 | unsigned64 memval = 0; | |
304 | unsigned64 memval1 = 0; | |
305 | unsigned64 mask = 0x7; | |
306 | unsigned int shift = 2; | |
307 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
308 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
309 | unsigned int byte; | |
310 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
311 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
312 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
313 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); | |
314 | } | |
315 | } | |
316 | } | |
317 | } | |
318 | ||
319 | ||
320 | 10010,ddd,VVVVVVVV,s:RI:16::LWSP | |
321 | *mips16: | |
322 | { | |
323 | unsigned32 instruction = instruction_0; | |
324 | int destreg = (instruction >> 8) & 0x7; | |
325 | int offset = (instruction >> 0) & 0xff; | |
326 | signed_word op1 = 29; | |
327 | if (destreg < 2) | |
328 | destreg += 16; | |
329 | if (have_extendval) | |
330 | { | |
331 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
332 | if (offset >= 0x8000) | |
333 | offset -= 0x10000; | |
334 | have_extendval = 0; | |
335 | } | |
336 | else | |
337 | { | |
338 | offset <<= 2; | |
339 | } | |
340 | op1 = GPR[op1]; | |
341 | if (have_extendval) | |
342 | SignalException (ReservedInstruction, instruction); | |
343 | { | |
344 | address_word vaddr = ((unsigned64)op1 + offset); | |
345 | address_word paddr; | |
346 | int uncached; | |
347 | if ((vaddr & 3) != 0) | |
348 | SignalExceptionAddressLoad(); | |
349 | else | |
350 | { | |
351 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
352 | { | |
353 | unsigned64 memval = 0; | |
354 | unsigned64 memval1 = 0; | |
355 | unsigned64 mask = 0x7; | |
356 | unsigned int shift = 2; | |
357 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
358 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
359 | unsigned int byte; | |
360 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
361 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
362 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
363 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); | |
364 | } | |
365 | } | |
366 | } | |
367 | } | |
368 | ||
369 | ||
370 | 10111,xxx,ddd,WWWWW:RRI:16::LWU | |
371 | *mips16: | |
372 | { | |
373 | unsigned32 instruction = instruction_0; | |
374 | signed_word op1 = (instruction >> 8) & 0x7; | |
375 | int destreg = (instruction >> 5) & 0x7; | |
376 | int offset = (instruction >> 0) & 0x1f; | |
377 | if (op1 < 2) | |
378 | op1 += 16; | |
379 | op1 = GPR[op1]; | |
380 | if (destreg < 2) | |
381 | destreg += 16; | |
382 | if (have_extendval) | |
383 | { | |
384 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
385 | if (offset >= 0x8000) | |
386 | offset -= 0x10000; | |
387 | have_extendval = 0; | |
388 | } | |
389 | else | |
390 | { | |
391 | offset <<= 2; | |
392 | } | |
393 | if (have_extendval) | |
394 | SignalException (ReservedInstruction, instruction); | |
395 | { | |
396 | address_word vaddr = ((unsigned64)op1 + offset); | |
397 | address_word paddr; | |
398 | int uncached; | |
399 | if ((vaddr & 3) != 0) | |
400 | SignalExceptionAddressLoad(); | |
401 | else | |
402 | { | |
403 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
404 | { | |
405 | unsigned64 memval = 0; | |
406 | unsigned64 memval1 = 0; | |
407 | unsigned64 mask = 0x7; | |
408 | unsigned int shift = 2; | |
409 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
410 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
411 | unsigned int byte; | |
412 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
413 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
414 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
415 | GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF)); | |
416 | } | |
417 | } | |
418 | } | |
419 | } | |
420 | ||
421 | ||
422 | 00111,xxx,ddd,DDDDD:RRI:16::LD | |
423 | *mips16: | |
424 | { | |
425 | unsigned32 instruction = instruction_0; | |
426 | signed_word op1 = (instruction >> 8) & 0x7; | |
427 | int destreg = (instruction >> 5) & 0x7; | |
428 | int offset = (instruction >> 0) & 0x1f; | |
429 | if (op1 < 2) | |
430 | op1 += 16; | |
431 | op1 = GPR[op1]; | |
432 | if (destreg < 2) | |
433 | destreg += 16; | |
434 | if (have_extendval) | |
435 | { | |
436 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
437 | if (offset >= 0x8000) | |
438 | offset -= 0x10000; | |
439 | have_extendval = 0; | |
440 | } | |
441 | else | |
442 | { | |
443 | offset <<= 3; | |
444 | } | |
445 | if (have_extendval) | |
446 | SignalException (ReservedInstruction, instruction); | |
447 | { | |
448 | address_word vaddr = ((unsigned64)op1 + offset); | |
449 | address_word paddr; | |
450 | int uncached; | |
451 | if ((vaddr & 7) != 0) | |
452 | SignalExceptionAddressLoad(); | |
453 | else | |
454 | { | |
455 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
456 | { | |
457 | unsigned64 memval = 0; | |
458 | unsigned64 memval1 = 0; | |
459 | unsigned64 mask = 0x7; | |
460 | unsigned int shift = 4; | |
461 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
462 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
463 | unsigned int byte; | |
464 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); | |
465 | GPR[destreg] = memval; | |
466 | } | |
467 | } | |
468 | } | |
469 | } | |
470 | ||
471 | ||
472 | 11111100,ddd,5.RD,P:RI64:16::LDPC | |
473 | *mips16: | |
474 | { | |
475 | unsigned32 instruction = instruction_0; | |
476 | int destreg = (instruction >> 5) & 0x7; | |
477 | int offset = (instruction >> 0) & 0x1f; | |
478 | signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x7; | |
479 | if (destreg < 2) | |
480 | destreg += 16; | |
481 | if (have_extendval) | |
482 | { | |
483 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
484 | if (offset >= 0x8000) | |
485 | offset -= 0x10000; | |
486 | have_extendval = 0; | |
487 | } | |
488 | else | |
489 | { | |
490 | offset <<= 3; | |
491 | } | |
492 | if (have_extendval) | |
493 | SignalException (ReservedInstruction, instruction); | |
494 | { | |
495 | address_word vaddr = ((unsigned64)op1 + offset); | |
496 | address_word paddr; | |
497 | int uncached; | |
498 | if ((vaddr & 7) != 0) | |
499 | SignalExceptionAddressLoad(); | |
500 | else | |
501 | { | |
502 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
503 | { | |
504 | unsigned64 memval = 0; | |
505 | unsigned64 memval1 = 0; | |
506 | unsigned64 mask = 0x7; | |
507 | unsigned int shift = 4; | |
508 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
509 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
510 | unsigned int byte; | |
511 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); | |
512 | GPR[destreg] = memval; | |
513 | } | |
514 | } | |
515 | } | |
516 | } | |
517 | ||
518 | ||
519 | 11111000,ddd,5.RD,s:RI64:16::LDSP | |
520 | *mips16: | |
521 | { | |
522 | unsigned32 instruction = instruction_0; | |
523 | int destreg = (instruction >> 5) & 0x7; | |
524 | int offset = (instruction >> 0) & 0x1f; | |
525 | signed_word op1 = 29; | |
526 | if (destreg < 2) | |
527 | destreg += 16; | |
528 | if (have_extendval) | |
529 | { | |
530 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
531 | if (offset >= 0x8000) | |
532 | offset -= 0x10000; | |
533 | have_extendval = 0; | |
534 | } | |
535 | else | |
536 | { | |
537 | offset <<= 3; | |
538 | } | |
539 | op1 = GPR[op1]; | |
540 | if (have_extendval) | |
541 | SignalException (ReservedInstruction, instruction); | |
542 | { | |
543 | address_word vaddr = ((unsigned64)op1 + offset); | |
544 | address_word paddr; | |
545 | int uncached; | |
546 | if ((vaddr & 7) != 0) | |
547 | SignalExceptionAddressLoad(); | |
548 | else | |
549 | { | |
550 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
551 | { | |
552 | unsigned64 memval = 0; | |
553 | unsigned64 memval1 = 0; | |
554 | unsigned64 mask = 0x7; | |
555 | unsigned int shift = 4; | |
556 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
557 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
558 | unsigned int byte; | |
559 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); | |
560 | GPR[destreg] = memval; | |
561 | } | |
562 | } | |
563 | } | |
564 | } | |
565 | ||
566 | ||
567 | 11000,xxx,yyy,55555:RRI:16::SB | |
568 | *mips16: | |
569 | { | |
570 | unsigned32 instruction = instruction_0; | |
571 | signed_word op1 = (instruction >> 8) & 0x7; | |
572 | signed_word op2 = (instruction >> 5) & 0x7; | |
573 | int offset = (instruction >> 0) & 0x1f; | |
574 | if (op1 < 2) | |
575 | op1 += 16; | |
576 | op1 = GPR[op1]; | |
577 | if (op2 < 2) | |
578 | op2 += 16; | |
579 | op2 = GPR[op2]; | |
580 | if (have_extendval) | |
581 | { | |
582 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
583 | if (offset >= 0x8000) | |
584 | offset -= 0x10000; | |
585 | have_extendval = 0; | |
586 | } | |
587 | else | |
588 | { | |
589 | } | |
590 | if (have_extendval) | |
591 | SignalException (ReservedInstruction, instruction); | |
592 | { | |
593 | address_word vaddr = ((unsigned64)op1 + offset); | |
594 | address_word paddr; | |
595 | int uncached; | |
596 | { | |
597 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
598 | { | |
599 | unsigned64 memval = 0; | |
600 | unsigned64 memval1 = 0; | |
601 | unsigned64 mask = 0x7; | |
602 | unsigned int shift = 0; | |
603 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
604 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
605 | unsigned int byte; | |
606 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
607 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
608 | memval = ((unsigned64) op2 << (8 * byte)); | |
609 | { | |
610 | StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL); | |
611 | } | |
612 | } | |
613 | } | |
614 | } | |
615 | } | |
616 | ||
617 | ||
618 | 11001,xxx,yyy,HHHHH:RRI:16::SH | |
619 | *mips16: | |
620 | { | |
621 | unsigned32 instruction = instruction_0; | |
622 | signed_word op1 = (instruction >> 8) & 0x7; | |
623 | signed_word op2 = (instruction >> 5) & 0x7; | |
624 | int offset = (instruction >> 0) & 0x1f; | |
625 | if (op1 < 2) | |
626 | op1 += 16; | |
627 | op1 = GPR[op1]; | |
628 | if (op2 < 2) | |
629 | op2 += 16; | |
630 | op2 = GPR[op2]; | |
631 | if (have_extendval) | |
632 | { | |
633 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
634 | if (offset >= 0x8000) | |
635 | offset -= 0x10000; | |
636 | have_extendval = 0; | |
637 | } | |
638 | else | |
639 | { | |
640 | offset <<= 1; | |
641 | } | |
642 | if (have_extendval) | |
643 | SignalException (ReservedInstruction, instruction); | |
644 | { | |
645 | address_word vaddr = ((unsigned64)op1 + offset); | |
646 | address_word paddr; | |
647 | int uncached; | |
648 | if ((vaddr & 1) != 0) | |
649 | SignalExceptionAddressStore(); | |
650 | else | |
651 | { | |
652 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
653 | { | |
654 | unsigned64 memval = 0; | |
655 | unsigned64 memval1 = 0; | |
656 | unsigned64 mask = 0x7; | |
657 | unsigned int shift = 1; | |
658 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
659 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
660 | unsigned int byte; | |
661 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
662 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
663 | memval = ((unsigned64) op2 << (8 * byte)); | |
664 | { | |
665 | StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL); | |
666 | } | |
667 | } | |
668 | } | |
669 | } | |
670 | } | |
671 | ||
672 | ||
673 | 11011,xxx,yyy,WWWWW:RRI:16::SW | |
674 | *mips16: | |
675 | { | |
676 | unsigned32 instruction = instruction_0; | |
677 | signed_word op1 = (instruction >> 8) & 0x7; | |
678 | signed_word op2 = (instruction >> 5) & 0x7; | |
679 | int offset = (instruction >> 0) & 0x1f; | |
680 | if (op1 < 2) | |
681 | op1 += 16; | |
682 | op1 = GPR[op1]; | |
683 | if (op2 < 2) | |
684 | op2 += 16; | |
685 | op2 = GPR[op2]; | |
686 | if (have_extendval) | |
687 | { | |
688 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
689 | if (offset >= 0x8000) | |
690 | offset -= 0x10000; | |
691 | have_extendval = 0; | |
692 | } | |
693 | else | |
694 | { | |
695 | offset <<= 2; | |
696 | } | |
697 | if (have_extendval) | |
698 | SignalException (ReservedInstruction, instruction); | |
699 | { | |
700 | address_word vaddr = ((unsigned64)op1 + offset); | |
701 | address_word paddr; | |
702 | int uncached; | |
703 | if ((vaddr & 3) != 0) | |
704 | SignalExceptionAddressStore(); | |
705 | else | |
706 | { | |
707 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
708 | { | |
709 | unsigned64 memval = 0; | |
710 | unsigned64 memval1 = 0; | |
711 | unsigned64 mask = 0x7; | |
712 | unsigned int byte; | |
713 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
714 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
715 | memval = ((unsigned64) op2 << (8 * byte)); | |
716 | { | |
717 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
718 | } | |
719 | } | |
720 | } | |
721 | } | |
722 | } | |
723 | ||
724 | ||
725 | 11010,yyy,VVVVVVVV,s:RI:16::SWSP | |
726 | *mips16: | |
727 | { | |
728 | unsigned32 instruction = instruction_0; | |
729 | signed_word op2 = (instruction >> 8) & 0x7; | |
730 | int offset = (instruction >> 0) & 0xff; | |
731 | signed_word op1 = 29; | |
732 | if (op2 < 2) | |
733 | op2 += 16; | |
734 | op2 = GPR[op2]; | |
735 | if (have_extendval) | |
736 | { | |
737 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
738 | if (offset >= 0x8000) | |
739 | offset -= 0x10000; | |
740 | have_extendval = 0; | |
741 | } | |
742 | else | |
743 | { | |
744 | offset <<= 2; | |
745 | } | |
746 | op1 = GPR[op1]; | |
747 | if (have_extendval) | |
748 | SignalException (ReservedInstruction, instruction); | |
749 | { | |
750 | address_word vaddr = ((unsigned64)op1 + offset); | |
751 | address_word paddr; | |
752 | int uncached; | |
753 | if ((vaddr & 3) != 0) | |
754 | SignalExceptionAddressStore(); | |
755 | else | |
756 | { | |
757 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
758 | { | |
759 | unsigned64 memval = 0; | |
760 | unsigned64 memval1 = 0; | |
761 | unsigned64 mask = 0x7; | |
762 | unsigned int byte; | |
763 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
764 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
765 | memval = ((unsigned64) op2 << (8 * byte)); | |
766 | { | |
767 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
768 | } | |
769 | } | |
770 | } | |
771 | } | |
772 | } | |
773 | ||
774 | ||
775 | 01100010,VVVVVVVV,Q,s:I8:16::SWRASP | |
776 | *mips16: | |
777 | { | |
778 | unsigned32 instruction = instruction_0; | |
779 | int offset = (instruction >> 0) & 0xff; | |
780 | signed_word op2 = 31; | |
781 | signed_word op1 = 29; | |
782 | if (have_extendval) | |
783 | { | |
784 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
785 | if (offset >= 0x8000) | |
786 | offset -= 0x10000; | |
787 | have_extendval = 0; | |
788 | } | |
789 | else | |
790 | { | |
791 | offset <<= 2; | |
792 | } | |
793 | op2 = GPR[op2]; | |
794 | op1 = GPR[op1]; | |
795 | if (have_extendval) | |
796 | SignalException (ReservedInstruction, instruction); | |
797 | { | |
798 | address_word vaddr = ((unsigned64)op1 + offset); | |
799 | address_word paddr; | |
800 | int uncached; | |
801 | if ((vaddr & 3) != 0) | |
802 | SignalExceptionAddressStore(); | |
803 | else | |
804 | { | |
805 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
806 | { | |
807 | unsigned64 memval = 0; | |
808 | unsigned64 memval1 = 0; | |
809 | unsigned64 mask = 0x7; | |
810 | unsigned int byte; | |
811 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
812 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
813 | memval = ((unsigned64) op2 << (8 * byte)); | |
814 | { | |
815 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
816 | } | |
817 | } | |
818 | } | |
819 | } | |
820 | } | |
821 | ||
822 | ||
823 | 01111,xxx,yyy,DDDDD:RRI:16::SD | |
824 | *mips16: | |
825 | { | |
826 | unsigned32 instruction = instruction_0; | |
827 | signed_word op1 = (instruction >> 8) & 0x7; | |
828 | signed_word op2 = (instruction >> 5) & 0x7; | |
829 | int offset = (instruction >> 0) & 0x1f; | |
830 | if (op1 < 2) | |
831 | op1 += 16; | |
832 | op1 = GPR[op1]; | |
833 | if (op2 < 2) | |
834 | op2 += 16; | |
835 | op2 = GPR[op2]; | |
836 | if (have_extendval) | |
837 | { | |
838 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
839 | if (offset >= 0x8000) | |
840 | offset -= 0x10000; | |
841 | have_extendval = 0; | |
842 | } | |
843 | else | |
844 | { | |
845 | offset <<= 3; | |
846 | } | |
847 | if (have_extendval) | |
848 | SignalException (ReservedInstruction, instruction); | |
849 | { | |
850 | address_word vaddr = ((unsigned64)op1 + offset); | |
851 | address_word paddr; | |
852 | int uncached; | |
853 | if ((vaddr & 7) != 0) | |
854 | SignalExceptionAddressStore(); | |
855 | else | |
856 | { | |
857 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
858 | { | |
859 | unsigned64 memval = 0; | |
860 | unsigned64 memval1 = 0; | |
861 | memval = op2; | |
862 | { | |
863 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
864 | } | |
865 | } | |
866 | } | |
867 | } | |
868 | } | |
869 | ||
870 | ||
871 | 11111001,yyy,5.RD,s:RI64:16::SDSP | |
872 | *mips16: | |
873 | { | |
874 | unsigned32 instruction = instruction_0; | |
875 | signed_word op2 = (instruction >> 5) & 0x7; | |
876 | int offset = (instruction >> 0) & 0x1f; | |
877 | signed_word op1 = 29; | |
878 | if (op2 < 2) | |
879 | op2 += 16; | |
880 | op2 = GPR[op2]; | |
881 | if (have_extendval) | |
882 | { | |
883 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
884 | if (offset >= 0x8000) | |
885 | offset -= 0x10000; | |
886 | have_extendval = 0; | |
887 | } | |
888 | else | |
889 | { | |
890 | offset <<= 3; | |
891 | } | |
892 | op1 = GPR[op1]; | |
893 | if (have_extendval) | |
894 | SignalException (ReservedInstruction, instruction); | |
895 | { | |
896 | address_word vaddr = ((unsigned64)op1 + offset); | |
897 | address_word paddr; | |
898 | int uncached; | |
899 | if ((vaddr & 7) != 0) | |
900 | SignalExceptionAddressStore(); | |
901 | else | |
902 | { | |
903 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
904 | { | |
905 | unsigned64 memval = 0; | |
906 | unsigned64 memval1 = 0; | |
907 | memval = op2; | |
908 | { | |
909 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
910 | } | |
911 | } | |
912 | } | |
913 | } | |
914 | } | |
915 | ||
916 | ||
917 | 11111010,CCCCCCCC,s,Q:I64:16::SDRASP | |
918 | *mips16: | |
919 | { | |
920 | unsigned32 instruction = instruction_0; | |
921 | int offset = (instruction >> 0) & 0xff; | |
922 | signed_word op1 = 29; | |
923 | signed_word op2 = 31; | |
924 | if (have_extendval) | |
925 | { | |
926 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
927 | if (offset >= 0x8000) | |
928 | offset -= 0x10000; | |
929 | have_extendval = 0; | |
930 | } | |
931 | else | |
932 | { | |
933 | offset <<= 3; | |
934 | } | |
935 | op1 = GPR[op1]; | |
936 | op2 = GPR[op2]; | |
937 | if (have_extendval) | |
938 | SignalException (ReservedInstruction, instruction); | |
939 | { | |
940 | address_word vaddr = ((unsigned64)op1 + offset); | |
941 | address_word paddr; | |
942 | int uncached; | |
943 | if ((vaddr & 7) != 0) | |
944 | SignalExceptionAddressStore(); | |
945 | else | |
946 | { | |
947 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
948 | { | |
949 | unsigned64 memval = 0; | |
950 | unsigned64 memval1 = 0; | |
951 | memval = op2; | |
952 | { | |
953 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
954 | } | |
955 | } | |
956 | } | |
957 | } | |
958 | } | |
959 | ||
960 | ||
961 | // ALU Immediate Instructions | |
962 | ||
963 | ||
964 | 01101,ddd,UUUUUUUU,Z:RI:16::LI | |
965 | *mips16: | |
966 | { | |
967 | unsigned32 instruction = instruction_0; | |
968 | int destreg = (instruction >> 8) & 0x7; | |
969 | int op2 = (instruction >> 0) & 0xff; | |
970 | signed_word op1 = 0; | |
971 | if (destreg < 2) | |
972 | destreg += 16; | |
973 | if (have_extendval) | |
974 | { | |
975 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
976 | have_extendval = 0; | |
977 | } | |
978 | else | |
979 | { | |
980 | } | |
981 | if (have_extendval) | |
982 | SignalException (ReservedInstruction, instruction); | |
983 | { | |
984 | if (destreg != 0) | |
985 | GPR[destreg] = (op1 | op2); | |
986 | } | |
987 | } | |
988 | ||
989 | ||
990 | 01000,xxx,ddd,04444:RRI_A:16::ADDIU | |
991 | *mips16: | |
992 | { | |
993 | unsigned32 instruction = instruction_0; | |
994 | signed_word op1 = (instruction >> 8) & 0x7; | |
995 | int destreg = (instruction >> 5) & 0x7; | |
996 | int op2 = (instruction >> 0) & 0xf; | |
997 | if (op1 < 2) | |
998 | op1 += 16; | |
999 | op1 = GPR[op1]; | |
1000 | if (destreg < 2) | |
1001 | destreg += 16; | |
1002 | if (have_extendval) | |
1003 | { | |
1004 | op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0); | |
1005 | if (op2 >= 0x4000) | |
1006 | op2 -= 0x8000; | |
1007 | have_extendval = 0; | |
1008 | } | |
1009 | else | |
1010 | { | |
1011 | if (op2 >= 0x8) | |
1012 | op2 -= 0x10; | |
1013 | } | |
1014 | if (have_extendval) | |
1015 | SignalException (ReservedInstruction, instruction); | |
1016 | { | |
1017 | unsigned int temp = (unsigned int)(op1 + op2); | |
1018 | signed int tempS = (signed int)temp; | |
1019 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
1020 | } | |
1021 | } | |
1022 | ||
1023 | ||
1024 | 01001,www,kkkkkkkk:RI:16::ADDIU8 | |
1025 | *mips16: | |
1026 | { | |
1027 | unsigned32 instruction = instruction_0; | |
1028 | signed_word op1 = (instruction >> 8) & 0x7; | |
1029 | int destreg; | |
1030 | int op2 = (instruction >> 0) & 0xff; | |
1031 | if (op1 < 2) | |
1032 | op1 += 16; | |
1033 | destreg = op1; | |
1034 | op1 = GPR[op1]; | |
1035 | if (have_extendval) | |
1036 | { | |
1037 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
1038 | if (op2 >= 0x8000) | |
1039 | op2 -= 0x10000; | |
1040 | have_extendval = 0; | |
1041 | } | |
1042 | else | |
1043 | { | |
1044 | if (op2 >= 0x80) | |
1045 | op2 -= 0x100; | |
1046 | } | |
1047 | if (have_extendval) | |
1048 | SignalException (ReservedInstruction, instruction); | |
1049 | { | |
1050 | unsigned int temp = (unsigned int)(op1 + op2); | |
1051 | signed int tempS = (signed int)temp; | |
1052 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
1053 | } | |
1054 | } | |
1055 | ||
1056 | ||
1057 | 01100011,KKKKKKKK,S:I8:16::ADJSP | |
1058 | *mips16: | |
1059 | { | |
1060 | unsigned32 instruction = instruction_0; | |
1061 | int op2 = (instruction >> 0) & 0xff; | |
1062 | signed_word op1 = 29; | |
1063 | int destreg; | |
1064 | if (have_extendval) | |
1065 | { | |
1066 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
1067 | if (op2 >= 0x8000) | |
1068 | op2 -= 0x10000; | |
1069 | have_extendval = 0; | |
1070 | } | |
1071 | else | |
1072 | { | |
1073 | if (op2 >= 0x80) | |
1074 | op2 -= 0x100; | |
1075 | op2 <<= 3; | |
1076 | } | |
1077 | destreg = op1; | |
1078 | op1 = GPR[op1]; | |
1079 | if (have_extendval) | |
1080 | SignalException (ReservedInstruction, instruction); | |
1081 | { | |
1082 | unsigned int temp = (unsigned int)(op1 + op2); | |
1083 | signed int tempS = (signed int)temp; | |
1084 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
1085 | } | |
1086 | } | |
1087 | ||
1088 | ||
1089 | 00001,ddd,AAAAAAAA,P:RI:16::ADDIUPC | |
1090 | *mips16: | |
1091 | { | |
1092 | unsigned32 instruction = instruction_0; | |
1093 | int destreg = (instruction >> 8) & 0x7; | |
1094 | int op2 = (instruction >> 0) & 0xff; | |
1095 | signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3; | |
1096 | if (destreg < 2) | |
1097 | destreg += 16; | |
1098 | if (have_extendval) | |
1099 | { | |
1100 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
1101 | if (op2 >= 0x8000) | |
1102 | op2 -= 0x10000; | |
1103 | have_extendval = 0; | |
1104 | } | |
1105 | else | |
1106 | { | |
1107 | op2 <<= 2; | |
1108 | } | |
1109 | if (have_extendval) | |
1110 | SignalException (ReservedInstruction, instruction); | |
1111 | { | |
1112 | unsigned int temp = (unsigned int)(op1 + op2); | |
1113 | signed int tempS = (signed int)temp; | |
1114 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
1115 | } | |
1116 | } | |
1117 | ||
1118 | ||
1119 | 00000,ddd,AAAAAAAA,s:RI:16::ADDIUSP | |
1120 | *mips16: | |
1121 | { | |
1122 | unsigned32 instruction = instruction_0; | |
1123 | int destreg = (instruction >> 8) & 0x7; | |
1124 | int op2 = (instruction >> 0) & 0xff; | |
1125 | signed_word op1 = 29; | |
1126 | if (destreg < 2) | |
1127 | destreg += 16; | |
1128 | if (have_extendval) | |
1129 | { | |
1130 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
1131 | if (op2 >= 0x8000) | |
1132 | op2 -= 0x10000; | |
1133 | have_extendval = 0; | |
1134 | } | |
1135 | else | |
1136 | { | |
1137 | op2 <<= 2; | |
1138 | } | |
1139 | op1 = GPR[op1]; | |
1140 | if (have_extendval) | |
1141 | SignalException (ReservedInstruction, instruction); | |
1142 | { | |
1143 | unsigned int temp = (unsigned int)(op1 + op2); | |
1144 | signed int tempS = (signed int)temp; | |
1145 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
1146 | } | |
1147 | } | |
1148 | ||
1149 | ||
1150 | 01000,xxx,ddd,14444:RRI_A:16::DADDIU | |
1151 | *mips16: | |
1152 | { | |
1153 | unsigned32 instruction = instruction_0; | |
1154 | signed_word op1 = (instruction >> 8) & 0x7; | |
1155 | int destreg = (instruction >> 5) & 0x7; | |
1156 | int op2 = (instruction >> 0) & 0xf; | |
1157 | if (op1 < 2) | |
1158 | op1 += 16; | |
1159 | op1 = GPR[op1]; | |
1160 | if (destreg < 2) | |
1161 | destreg += 16; | |
1162 | if (have_extendval) | |
1163 | { | |
1164 | op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0); | |
1165 | if (op2 >= 0x4000) | |
1166 | op2 -= 0x8000; | |
1167 | have_extendval = 0; | |
1168 | } | |
1169 | else | |
1170 | { | |
1171 | if (op2 >= 0x8) | |
1172 | op2 -= 0x10; | |
1173 | } | |
1174 | if (have_extendval) | |
1175 | SignalException (ReservedInstruction, instruction); | |
1176 | { | |
1177 | unsigned64 temp = (unsigned64)(op1 + op2); | |
1178 | word64 tempS = (word64)temp; | |
1179 | GPR[destreg] = (unsigned64)temp; | |
1180 | } | |
1181 | } | |
1182 | ||
1183 | ||
1184 | 11111101,www,jjjjj:RI64:16::DADDIU5 | |
1185 | *mips16: | |
1186 | { | |
1187 | unsigned32 instruction = instruction_0; | |
1188 | signed_word op1 = (instruction >> 5) & 0x7; | |
1189 | int destreg; | |
1190 | int op2 = (instruction >> 0) & 0x1f; | |
1191 | if (op1 < 2) | |
1192 | op1 += 16; | |
1193 | destreg = op1; | |
1194 | op1 = GPR[op1]; | |
1195 | if (have_extendval) | |
1196 | { | |
1197 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
1198 | if (op2 >= 0x8000) | |
1199 | op2 -= 0x10000; | |
1200 | have_extendval = 0; | |
1201 | } | |
1202 | else | |
1203 | { | |
1204 | if (op2 >= 0x10) | |
1205 | op2 -= 0x20; | |
1206 | } | |
1207 | if (have_extendval) | |
1208 | SignalException (ReservedInstruction, instruction); | |
1209 | { | |
1210 | unsigned64 temp = (unsigned64)(op1 + op2); | |
1211 | word64 tempS = (word64)temp; | |
1212 | GPR[destreg] = (unsigned64)temp; | |
1213 | } | |
1214 | } | |
1215 | ||
1216 | ||
1217 | 11111011,KKKKKKKK,S:I64:16::DADJSP | |
1218 | *mips16: | |
1219 | { | |
1220 | unsigned32 instruction = instruction_0; | |
1221 | int op2 = (instruction >> 0) & 0xff; | |
1222 | signed_word op1 = 29; | |
1223 | int destreg; | |
1224 | if (have_extendval) | |
1225 | { | |
1226 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
1227 | if (op2 >= 0x8000) | |
1228 | op2 -= 0x10000; | |
1229 | have_extendval = 0; | |
1230 | } | |
1231 | else | |
1232 | { | |
1233 | if (op2 >= 0x80) | |
1234 | op2 -= 0x100; | |
1235 | op2 <<= 3; | |
1236 | } | |
1237 | destreg = op1; | |
1238 | op1 = GPR[op1]; | |
1239 | if (have_extendval) | |
1240 | SignalException (ReservedInstruction, instruction); | |
1241 | { | |
1242 | unsigned64 temp = (unsigned64)(op1 + op2); | |
1243 | word64 tempS = (word64)temp; | |
1244 | GPR[destreg] = (unsigned64)temp; | |
1245 | } | |
1246 | } | |
1247 | ||
1248 | ||
1249 | 11111110,ddd,EEEEE,P:RI64:16::DADDIUPC | |
1250 | *mips16: | |
1251 | { | |
1252 | unsigned32 instruction = instruction_0; | |
1253 | int destreg = (instruction >> 5) & 0x7; | |
1254 | int op2 = (instruction >> 0) & 0x1f; | |
1255 | signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3; | |
1256 | if (destreg < 2) | |
1257 | destreg += 16; | |
1258 | if (have_extendval) | |
1259 | { | |
1260 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
1261 | if (op2 >= 0x8000) | |
1262 | op2 -= 0x10000; | |
1263 | have_extendval = 0; | |
1264 | } | |
1265 | else | |
1266 | { | |
1267 | op2 <<= 2; | |
1268 | } | |
1269 | if (have_extendval) | |
1270 | SignalException (ReservedInstruction, instruction); | |
1271 | { | |
1272 | unsigned64 temp = (unsigned64)(op1 + op2); | |
1273 | word64 tempS = (word64)temp; | |
1274 | GPR[destreg] = (unsigned64)temp; | |
1275 | } | |
1276 | } | |
1277 | ||
1278 | ||
1279 | 11111111,ddd,EEEEE,s:RI64:16::DADDIUSP | |
1280 | *mips16: | |
1281 | { | |
1282 | unsigned32 instruction = instruction_0; | |
1283 | int destreg = (instruction >> 5) & 0x7; | |
1284 | int op2 = (instruction >> 0) & 0x1f; | |
1285 | signed_word op1 = 29; | |
1286 | if (destreg < 2) | |
1287 | destreg += 16; | |
1288 | if (have_extendval) | |
1289 | { | |
1290 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
1291 | if (op2 >= 0x8000) | |
1292 | op2 -= 0x10000; | |
1293 | have_extendval = 0; | |
1294 | } | |
1295 | else | |
1296 | { | |
1297 | op2 <<= 2; | |
1298 | } | |
1299 | op1 = GPR[op1]; | |
1300 | if (have_extendval) | |
1301 | SignalException (ReservedInstruction, instruction); | |
1302 | { | |
1303 | unsigned64 temp = (unsigned64)(op1 + op2); | |
1304 | word64 tempS = (word64)temp; | |
1305 | GPR[destreg] = (unsigned64)temp; | |
1306 | } | |
1307 | } | |
1308 | ||
1309 | ||
1310 | 01010,xxx,88888888,T:RI:16::SLTI | |
1311 | *mips16: | |
1312 | { | |
1313 | unsigned32 instruction = instruction_0; | |
1314 | signed_word op1 = (instruction >> 8) & 0x7; | |
1315 | int op2 = (instruction >> 0) & 0xff; | |
1316 | int destreg = 24; | |
1317 | if (op1 < 2) | |
1318 | op1 += 16; | |
1319 | op1 = GPR[op1]; | |
1320 | if (have_extendval) | |
1321 | { | |
1322 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
1323 | if (op2 >= 0x8000) | |
1324 | op2 -= 0x10000; | |
1325 | have_extendval = 0; | |
1326 | } | |
1327 | else | |
1328 | { | |
1329 | } | |
1330 | if (have_extendval) | |
1331 | SignalException (ReservedInstruction, instruction); | |
1332 | { | |
1333 | if ((word64)op1 < (word64)op2) | |
1334 | GPR[destreg] = 1; | |
1335 | else | |
1336 | GPR[destreg] = 0; | |
1337 | } | |
1338 | } | |
1339 | ||
1340 | ||
1341 | 01011,xxx,88888888,T:RI:16::SLTIU | |
1342 | *mips16: | |
1343 | { | |
1344 | unsigned32 instruction = instruction_0; | |
1345 | signed_word op1 = (instruction >> 8) & 0x7; | |
1346 | int op2 = (instruction >> 0) & 0xff; | |
1347 | int destreg = 24; | |
1348 | if (op1 < 2) | |
1349 | op1 += 16; | |
1350 | op1 = GPR[op1]; | |
1351 | if (have_extendval) | |
1352 | { | |
1353 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
1354 | if (op2 >= 0x8000) | |
1355 | op2 -= 0x10000; | |
1356 | have_extendval = 0; | |
1357 | } | |
1358 | else | |
1359 | { | |
1360 | } | |
1361 | if (have_extendval) | |
1362 | SignalException (ReservedInstruction, instruction); | |
1363 | { | |
1364 | if ((unsigned64)op1 < (unsigned64)op2) | |
1365 | GPR[destreg] = 1; | |
1366 | else | |
1367 | GPR[destreg] = 0; | |
1368 | } | |
1369 | } | |
1370 | ||
1371 | ||
1372 | 11101,xxx,yyy,01010,T:RR:16::CMP | |
1373 | *mips16: | |
1374 | { | |
1375 | unsigned32 instruction = instruction_0; | |
1376 | signed_word op1 = (instruction >> 8) & 0x7; | |
1377 | signed_word op2 = (instruction >> 5) & 0x7; | |
1378 | int destreg = 24; | |
1379 | if (op1 < 2) | |
1380 | op1 += 16; | |
1381 | op1 = GPR[op1]; | |
1382 | if (op2 < 2) | |
1383 | op2 += 16; | |
1384 | op2 = GPR[op2]; | |
1385 | if (have_extendval) | |
1386 | SignalException (ReservedInstruction, instruction); | |
1387 | { | |
1388 | GPR[destreg] = (op1 ^ op2); | |
1389 | } | |
1390 | } | |
1391 | ||
1392 | ||
1393 | 01110,xxx,UUUUUUUU,T:RI:16::CMPI | |
1394 | *mips16: | |
1395 | { | |
1396 | unsigned32 instruction = instruction_0; | |
1397 | signed_word op1 = (instruction >> 8) & 0x7; | |
1398 | int op2 = (instruction >> 0) & 0xff; | |
1399 | int destreg = 24; | |
1400 | if (op1 < 2) | |
1401 | op1 += 16; | |
1402 | op1 = GPR[op1]; | |
1403 | if (have_extendval) | |
1404 | { | |
1405 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
1406 | have_extendval = 0; | |
1407 | } | |
1408 | else | |
1409 | { | |
1410 | } | |
1411 | if (have_extendval) | |
1412 | SignalException (ReservedInstruction, instruction); | |
1413 | { | |
1414 | GPR[destreg] = (op1 ^ op2); | |
1415 | } | |
1416 | } | |
1417 | ||
1418 | ||
1419 | // Two/Three Operand, Register-Type | |
1420 | ||
1421 | ||
1422 | 11100,xxx,yyy,ddd,01:RRR:16::ADDU | |
1423 | *mips16: | |
1424 | { | |
1425 | unsigned32 instruction = instruction_0; | |
1426 | signed_word op1 = (instruction >> 8) & 0x7; | |
1427 | signed_word op2 = (instruction >> 5) & 0x7; | |
1428 | int destreg = (instruction >> 2) & 0x7; | |
1429 | if (op1 < 2) | |
1430 | op1 += 16; | |
1431 | op1 = GPR[op1]; | |
1432 | if (op2 < 2) | |
1433 | op2 += 16; | |
1434 | op2 = GPR[op2]; | |
1435 | if (destreg < 2) | |
1436 | destreg += 16; | |
1437 | if (have_extendval) | |
1438 | SignalException (ReservedInstruction, instruction); | |
1439 | { | |
1440 | unsigned int temp = (unsigned int)(op1 + op2); | |
1441 | signed int tempS = (signed int)temp; | |
1442 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
1443 | } | |
1444 | } | |
1445 | ||
1446 | ||
1447 | 11100,xxx,yyy,ddd,11:RRR:16::SUBU | |
1448 | *mips16: | |
1449 | { | |
1450 | unsigned32 instruction = instruction_0; | |
1451 | signed_word op1 = (instruction >> 8) & 0x7; | |
1452 | signed_word op2 = (instruction >> 5) & 0x7; | |
1453 | int destreg = (instruction >> 2) & 0x7; | |
1454 | if (op1 < 2) | |
1455 | op1 += 16; | |
1456 | op1 = GPR[op1]; | |
1457 | if (op2 < 2) | |
1458 | op2 += 16; | |
1459 | op2 = GPR[op2]; | |
1460 | if (destreg < 2) | |
1461 | destreg += 16; | |
1462 | if (have_extendval) | |
1463 | SignalException (ReservedInstruction, instruction); | |
1464 | { | |
1465 | unsigned int temp = (unsigned int)(op1 - op2); | |
1466 | signed int tempS = (signed int)temp; | |
1467 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
1468 | } | |
1469 | } | |
1470 | ||
1471 | ||
1472 | 11100,xxx,yyy,ddd,00:RRR:16::DADDU | |
1473 | *mips16: | |
1474 | { | |
1475 | unsigned32 instruction = instruction_0; | |
1476 | signed_word op1 = (instruction >> 8) & 0x7; | |
1477 | signed_word op2 = (instruction >> 5) & 0x7; | |
1478 | int destreg = (instruction >> 2) & 0x7; | |
1479 | if (op1 < 2) | |
1480 | op1 += 16; | |
1481 | op1 = GPR[op1]; | |
1482 | if (op2 < 2) | |
1483 | op2 += 16; | |
1484 | op2 = GPR[op2]; | |
1485 | if (destreg < 2) | |
1486 | destreg += 16; | |
1487 | if (have_extendval) | |
1488 | SignalException (ReservedInstruction, instruction); | |
1489 | { | |
1490 | unsigned64 temp = (unsigned64)(op1 + op2); | |
1491 | word64 tempS = (word64)temp; | |
1492 | GPR[destreg] = (unsigned64)temp; | |
1493 | } | |
1494 | } | |
1495 | ||
1496 | ||
1497 | 11100,xxx,yyy,ddd,10:RRR:16::DSUBU | |
1498 | *mips16: | |
1499 | { | |
1500 | unsigned32 instruction = instruction_0; | |
1501 | signed_word op1 = (instruction >> 8) & 0x7; | |
1502 | signed_word op2 = (instruction >> 5) & 0x7; | |
1503 | int destreg = (instruction >> 2) & 0x7; | |
1504 | if (op1 < 2) | |
1505 | op1 += 16; | |
1506 | op1 = GPR[op1]; | |
1507 | if (op2 < 2) | |
1508 | op2 += 16; | |
1509 | op2 = GPR[op2]; | |
1510 | if (destreg < 2) | |
1511 | destreg += 16; | |
1512 | if (have_extendval) | |
1513 | SignalException (ReservedInstruction, instruction); | |
1514 | { | |
1515 | unsigned64 temp = (unsigned64)(op1 - op2); | |
1516 | word64 tempS = (word64)temp; | |
1517 | GPR[destreg] = (unsigned64)temp; | |
1518 | } | |
1519 | } | |
1520 | ||
1521 | ||
1522 | 11101,xxx,yyy,00010,T:RR:16::SLT | |
1523 | *mips16: | |
1524 | { | |
1525 | unsigned32 instruction = instruction_0; | |
1526 | signed_word op1 = (instruction >> 8) & 0x7; | |
1527 | signed_word op2 = (instruction >> 5) & 0x7; | |
1528 | int destreg = 24; | |
1529 | if (op1 < 2) | |
1530 | op1 += 16; | |
1531 | op1 = GPR[op1]; | |
1532 | if (op2 < 2) | |
1533 | op2 += 16; | |
1534 | op2 = GPR[op2]; | |
1535 | if (have_extendval) | |
1536 | SignalException (ReservedInstruction, instruction); | |
1537 | { | |
1538 | if ((word64)op1 < (word64)op2) | |
1539 | GPR[destreg] = 1; | |
1540 | else | |
1541 | GPR[destreg] = 0; | |
1542 | } | |
1543 | } | |
1544 | ||
1545 | ||
1546 | 11101,xxx,yyy,00011,T:RR:16::SLTU | |
1547 | *mips16: | |
1548 | { | |
1549 | unsigned32 instruction = instruction_0; | |
1550 | signed_word op1 = (instruction >> 8) & 0x7; | |
1551 | signed_word op2 = (instruction >> 5) & 0x7; | |
1552 | int destreg = 24; | |
1553 | if (op1 < 2) | |
1554 | op1 += 16; | |
1555 | op1 = GPR[op1]; | |
1556 | if (op2 < 2) | |
1557 | op2 += 16; | |
1558 | op2 = GPR[op2]; | |
1559 | if (have_extendval) | |
1560 | SignalException (ReservedInstruction, instruction); | |
1561 | { | |
1562 | if ((unsigned64)op1 < (unsigned64)op2) | |
1563 | GPR[destreg] = 1; | |
1564 | else | |
1565 | GPR[destreg] = 0; | |
1566 | } | |
1567 | } | |
1568 | ||
1569 | ||
1570 | 11101,ddd,yyy,01011,Z:RR:16::NEG | |
1571 | *mips16: | |
1572 | { | |
1573 | unsigned32 instruction = instruction_0; | |
1574 | int destreg = (instruction >> 8) & 0x7; | |
1575 | signed_word op2 = (instruction >> 5) & 0x7; | |
1576 | signed_word op1 = 0; | |
1577 | if (destreg < 2) | |
1578 | destreg += 16; | |
1579 | if (op2 < 2) | |
1580 | op2 += 16; | |
1581 | op2 = GPR[op2]; | |
1582 | if (have_extendval) | |
1583 | SignalException (ReservedInstruction, instruction); | |
1584 | { | |
1585 | unsigned int temp = (unsigned int)(op1 - op2); | |
1586 | signed int tempS = (signed int)temp; | |
1587 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
1588 | } | |
1589 | } | |
1590 | ||
1591 | ||
1592 | 11101,www,yyy,01100:RR:16::AND | |
1593 | *mips16: | |
1594 | { | |
1595 | unsigned32 instruction = instruction_0; | |
1596 | signed_word op1 = (instruction >> 8) & 0x7; | |
1597 | int destreg; | |
1598 | signed_word op2 = (instruction >> 5) & 0x7; | |
1599 | if (op1 < 2) | |
1600 | op1 += 16; | |
1601 | destreg = op1; | |
1602 | op1 = GPR[op1]; | |
1603 | if (op2 < 2) | |
1604 | op2 += 16; | |
1605 | op2 = GPR[op2]; | |
1606 | if (have_extendval) | |
1607 | SignalException (ReservedInstruction, instruction); | |
1608 | { | |
1609 | GPR[destreg] = (op1 & op2); | |
1610 | } | |
1611 | } | |
1612 | ||
1613 | ||
1614 | 11101,www,yyy,01101:RR:16::OR | |
1615 | *mips16: | |
1616 | { | |
1617 | unsigned32 instruction = instruction_0; | |
1618 | signed_word op1 = (instruction >> 8) & 0x7; | |
1619 | int destreg; | |
1620 | signed_word op2 = (instruction >> 5) & 0x7; | |
1621 | if (op1 < 2) | |
1622 | op1 += 16; | |
1623 | destreg = op1; | |
1624 | op1 = GPR[op1]; | |
1625 | if (op2 < 2) | |
1626 | op2 += 16; | |
1627 | op2 = GPR[op2]; | |
1628 | if (have_extendval) | |
1629 | SignalException (ReservedInstruction, instruction); | |
1630 | { | |
1631 | if (destreg != 0) | |
1632 | GPR[destreg] = (op1 | op2); | |
1633 | } | |
1634 | } | |
1635 | ||
1636 | ||
1637 | 11101,www,yyy,01110:RR:16::XOR | |
1638 | *mips16: | |
1639 | { | |
1640 | unsigned32 instruction = instruction_0; | |
1641 | signed_word op1 = (instruction >> 8) & 0x7; | |
1642 | int destreg; | |
1643 | signed_word op2 = (instruction >> 5) & 0x7; | |
1644 | if (op1 < 2) | |
1645 | op1 += 16; | |
1646 | destreg = op1; | |
1647 | op1 = GPR[op1]; | |
1648 | if (op2 < 2) | |
1649 | op2 += 16; | |
1650 | op2 = GPR[op2]; | |
1651 | if (have_extendval) | |
1652 | SignalException (ReservedInstruction, instruction); | |
1653 | { | |
1654 | GPR[destreg] = (op1 ^ op2); | |
1655 | } | |
1656 | } | |
1657 | ||
1658 | ||
1659 | 11101,ddd,yyy,01111,Z:RR:16::NOT | |
1660 | *mips16: | |
1661 | { | |
1662 | unsigned32 instruction = instruction_0; | |
1663 | int destreg = (instruction >> 8) & 0x7; | |
1664 | signed_word op2 = (instruction >> 5) & 0x7; | |
1665 | signed_word op1 = 0; | |
1666 | if (destreg < 2) | |
1667 | destreg += 16; | |
1668 | if (op2 < 2) | |
1669 | op2 += 16; | |
1670 | op2 = GPR[op2]; | |
1671 | if (have_extendval) | |
1672 | SignalException (ReservedInstruction, instruction); | |
1673 | { | |
1674 | if (destreg != 0) | |
1675 | GPR[destreg] = ~(op1 | op2); | |
1676 | } | |
1677 | } | |
1678 | ||
1679 | ||
1680 | 01100111,ddd,XXXXX,z:I8_MOVR32:16::MOVR32 | |
1681 | *mips16: | |
1682 | { | |
1683 | unsigned32 instruction = instruction_0; | |
1684 | int destreg = (instruction >> 5) & 0x7; | |
1685 | signed_word op1 = (instruction >> 0) & 0x1f; | |
1686 | signed_word op2 = 0; | |
1687 | if (destreg < 2) | |
1688 | destreg += 16; | |
1689 | op1 = GPR[op1]; | |
1690 | if (have_extendval) | |
1691 | SignalException (ReservedInstruction, instruction); | |
1692 | { | |
1693 | if (destreg != 0) | |
1694 | GPR[destreg] = (op1 | op2); | |
1695 | } | |
1696 | } | |
1697 | ||
1698 | ||
1699 | 01100101,YYYYY,xxx,z:I8_MOV32R:16::MOV32R | |
1700 | *mips16: | |
1701 | { | |
1702 | unsigned32 instruction = instruction_0; | |
1703 | int destreg = (instruction >> 3) & 0x1f; | |
1704 | signed_word op1 = (instruction >> 0) & 0x7; | |
1705 | signed_word op2 = 0; | |
1706 | destreg = (destreg >> 2) | ((destreg & 3) << 3); | |
1707 | if (op1 < 2) | |
1708 | op1 += 16; | |
1709 | op1 = GPR[op1]; | |
1710 | if (have_extendval) | |
1711 | SignalException (ReservedInstruction, instruction); | |
1712 | { | |
1713 | if (destreg != 0) | |
1714 | GPR[destreg] = (op1 | op2); | |
1715 | } | |
1716 | } | |
1717 | ||
1718 | ||
1719 | 00110,ddd,yyy,sss,00:ISHIFT:16::SLL | |
1720 | *mips16: | |
1721 | { | |
1722 | unsigned32 instruction = instruction_0; | |
1723 | int destreg = (instruction >> 8) & 0x7; | |
1724 | signed_word op2 = (instruction >> 5) & 0x7; | |
1725 | int op1 = (instruction >> 2) & 0x7; | |
1726 | if (destreg < 2) | |
1727 | destreg += 16; | |
1728 | if (op2 < 2) | |
1729 | op2 += 16; | |
1730 | op2 = GPR[op2]; | |
1731 | if (have_extendval) | |
1732 | { | |
1733 | op1 = (extendval >> 6) & 0x1f; | |
1734 | have_extendval = 0; | |
1735 | } | |
1736 | else | |
1737 | { | |
1738 | if (op1 == 0) | |
1739 | op1 = 8; | |
1740 | } | |
1741 | if (have_extendval) | |
1742 | SignalException (ReservedInstruction, instruction); | |
1743 | { | |
1744 | GPR[destreg] = ((unsigned64)op2 << op1); | |
1745 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
1746 | } | |
1747 | } | |
1748 | ||
1749 | ||
1750 | 00110,ddd,yyy,sss,10:ISHIFT:16::SRL | |
1751 | *mips16: | |
1752 | { | |
1753 | unsigned32 instruction = instruction_0; | |
1754 | int destreg = (instruction >> 8) & 0x7; | |
1755 | signed_word op2 = (instruction >> 5) & 0x7; | |
1756 | int op1 = (instruction >> 2) & 0x7; | |
1757 | if (destreg < 2) | |
1758 | destreg += 16; | |
1759 | if (op2 < 2) | |
1760 | op2 += 16; | |
1761 | op2 = GPR[op2]; | |
1762 | if (have_extendval) | |
1763 | { | |
1764 | op1 = (extendval >> 6) & 0x1f; | |
1765 | have_extendval = 0; | |
1766 | } | |
1767 | else | |
1768 | { | |
1769 | if (op1 == 0) | |
1770 | op1 = 8; | |
1771 | } | |
1772 | if (have_extendval) | |
1773 | SignalException (ReservedInstruction, instruction); | |
1774 | { | |
1775 | GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); | |
1776 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
1777 | } | |
1778 | } | |
1779 | ||
1780 | ||
1781 | 00110,ddd,yyy,sss,11:ISHIFT:16::SRA | |
1782 | *mips16: | |
1783 | { | |
1784 | unsigned32 instruction = instruction_0; | |
1785 | int destreg = (instruction >> 8) & 0x7; | |
1786 | signed_word op2 = (instruction >> 5) & 0x7; | |
1787 | int op1 = (instruction >> 2) & 0x7; | |
1788 | if (destreg < 2) | |
1789 | destreg += 16; | |
1790 | if (op2 < 2) | |
1791 | op2 += 16; | |
1792 | op2 = GPR[op2]; | |
1793 | if (have_extendval) | |
1794 | { | |
1795 | op1 = (extendval >> 6) & 0x1f; | |
1796 | have_extendval = 0; | |
1797 | } | |
1798 | else | |
1799 | { | |
1800 | if (op1 == 0) | |
1801 | op1 = 8; | |
1802 | } | |
1803 | if (have_extendval) | |
1804 | SignalException (ReservedInstruction, instruction); | |
1805 | { | |
1806 | unsigned int highbit = (unsigned int)1 << 31; | |
1807 | GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); | |
1808 | GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0); | |
1809 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
1810 | } | |
1811 | } | |
1812 | ||
1813 | ||
1814 | 11101,xxx,vvv,00100:RR:16::SLLV | |
1815 | *mips16: | |
1816 | { | |
1817 | unsigned32 instruction = instruction_0; | |
1818 | signed_word op1 = (instruction >> 8) & 0x7; | |
1819 | signed_word op2 = (instruction >> 5) & 0x7; | |
1820 | int destreg; | |
1821 | if (op1 < 2) | |
1822 | op1 += 16; | |
1823 | op1 = GPR[op1]; | |
1824 | if (op2 < 2) | |
1825 | op2 += 16; | |
1826 | destreg = op2; | |
1827 | op2 = GPR[op2]; | |
1828 | if (have_extendval) | |
1829 | SignalException (ReservedInstruction, instruction); | |
1830 | { | |
1831 | op1 &= 0x1F; | |
1832 | GPR[destreg] = ((unsigned64)op2 << op1); | |
1833 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
1834 | } | |
1835 | } | |
1836 | ||
1837 | ||
1838 | 11101,xxx,vvv,00110:RR:16::SRLV | |
1839 | *mips16: | |
1840 | { | |
1841 | unsigned32 instruction = instruction_0; | |
1842 | signed_word op1 = (instruction >> 8) & 0x7; | |
1843 | signed_word op2 = (instruction >> 5) & 0x7; | |
1844 | int destreg; | |
1845 | if (op1 < 2) | |
1846 | op1 += 16; | |
1847 | op1 = GPR[op1]; | |
1848 | if (op2 < 2) | |
1849 | op2 += 16; | |
1850 | destreg = op2; | |
1851 | op2 = GPR[op2]; | |
1852 | if (have_extendval) | |
1853 | SignalException (ReservedInstruction, instruction); | |
1854 | { | |
1855 | op1 &= 0x1F; | |
1856 | GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); | |
1857 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
1858 | } | |
1859 | } | |
1860 | ||
1861 | ||
1862 | 11101,xxx,vvv,00111:RR:16::SRAV | |
1863 | *mips16: | |
1864 | { | |
1865 | unsigned32 instruction = instruction_0; | |
1866 | signed_word op1 = (instruction >> 8) & 0x7; | |
1867 | signed_word op2 = (instruction >> 5) & 0x7; | |
1868 | int destreg; | |
1869 | if (op1 < 2) | |
1870 | op1 += 16; | |
1871 | op1 = GPR[op1]; | |
1872 | if (op2 < 2) | |
1873 | op2 += 16; | |
1874 | destreg = op2; | |
1875 | op2 = GPR[op2]; | |
1876 | if (have_extendval) | |
1877 | SignalException (ReservedInstruction, instruction); | |
1878 | { | |
1879 | unsigned int highbit = (unsigned int)1 << 31; | |
1880 | op1 &= 0x1F; | |
1881 | GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); | |
1882 | GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0); | |
1883 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
1884 | } | |
1885 | } | |
1886 | ||
1887 | ||
1888 | 00110,ddd,yyy,[[[,01:ISHIFT:16::DSLL | |
1889 | *mips16: | |
1890 | { | |
1891 | unsigned32 instruction = instruction_0; | |
1892 | int destreg = (instruction >> 8) & 0x7; | |
1893 | signed_word op2 = (instruction >> 5) & 0x7; | |
1894 | int op1 = (instruction >> 2) & 0x7; | |
1895 | if (destreg < 2) | |
1896 | destreg += 16; | |
1897 | if (op2 < 2) | |
1898 | op2 += 16; | |
1899 | op2 = GPR[op2]; | |
1900 | if (have_extendval) | |
1901 | { | |
1902 | op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20); | |
1903 | have_extendval = 0; | |
1904 | } | |
1905 | else | |
1906 | { | |
1907 | if (op1 == 0) | |
1908 | op1 = 8; | |
1909 | } | |
1910 | if (have_extendval) | |
1911 | SignalException (ReservedInstruction, instruction); | |
1912 | { | |
1913 | GPR[destreg] = ((unsigned64)op2 << op1); | |
1914 | } | |
1915 | } | |
1916 | ||
1917 | ||
1918 | 11101,XXX,vvv,01000:RR:16::DSRL | |
1919 | *mips16: | |
1920 | { | |
1921 | unsigned32 instruction = instruction_0; | |
1922 | int op1 = (instruction >> 8) & 0x7; | |
1923 | signed_word op2 = (instruction >> 5) & 0x7; | |
1924 | int destreg; | |
1925 | if (have_extendval) | |
1926 | { | |
1927 | op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20); | |
1928 | have_extendval = 0; | |
1929 | } | |
1930 | else | |
1931 | { | |
1932 | if (op1 == 0) | |
1933 | op1 = 8; | |
1934 | } | |
1935 | if (op2 < 2) | |
1936 | op2 += 16; | |
1937 | destreg = op2; | |
1938 | op2 = GPR[op2]; | |
1939 | if (have_extendval) | |
1940 | SignalException (ReservedInstruction, instruction); | |
1941 | { | |
1942 | GPR[destreg] = ((unsigned64)(op2) >> op1); | |
1943 | } | |
1944 | } | |
1945 | ||
1946 | ||
1947 | 11101,xxx,vvv,10011:RR:16::DSRA | |
1948 | *mips16: | |
1949 | { | |
1950 | unsigned32 instruction = instruction_0; | |
1951 | int op1 = (instruction >> 8) & 0x7; | |
1952 | signed_word op2 = (instruction >> 5) & 0x7; | |
1953 | int destreg; | |
1954 | if (have_extendval) | |
1955 | { | |
1956 | op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20); | |
1957 | have_extendval = 0; | |
1958 | } | |
1959 | else | |
1960 | { | |
1961 | if (op1 == 0) | |
1962 | op1 = 8; | |
1963 | } | |
1964 | if (op2 < 2) | |
1965 | op2 += 16; | |
1966 | destreg = op2; | |
1967 | op2 = GPR[op2]; | |
1968 | if (have_extendval) | |
1969 | SignalException (ReservedInstruction, instruction); | |
1970 | { | |
1971 | unsigned64 highbit = (unsigned64)1 << 63; | |
1972 | GPR[destreg] = ((unsigned64)(op2) >> op1); | |
1973 | GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0); | |
1974 | } | |
1975 | } | |
1976 | ||
1977 | ||
1978 | 11101,xxx,vvv,10100:RR:16::DSLLV | |
1979 | *mips16: | |
1980 | { | |
1981 | unsigned32 instruction = instruction_0; | |
1982 | signed_word op1 = (instruction >> 8) & 0x7; | |
1983 | signed_word op2 = (instruction >> 5) & 0x7; | |
1984 | int destreg; | |
1985 | if (op1 < 2) | |
1986 | op1 += 16; | |
1987 | op1 = GPR[op1]; | |
1988 | if (op2 < 2) | |
1989 | op2 += 16; | |
1990 | destreg = op2; | |
1991 | op2 = GPR[op2]; | |
1992 | if (have_extendval) | |
1993 | SignalException (ReservedInstruction, instruction); | |
1994 | { | |
1995 | op1 &= 0x3F; | |
1996 | GPR[destreg] = ((unsigned64)op2 << op1); | |
1997 | } | |
1998 | } | |
1999 | ||
2000 | ||
2001 | 11101,xxx,vvv,10110:RR:16::DSRLV | |
2002 | *mips16: | |
2003 | { | |
2004 | unsigned32 instruction = instruction_0; | |
2005 | signed_word op1 = (instruction >> 8) & 0x7; | |
2006 | signed_word op2 = (instruction >> 5) & 0x7; | |
2007 | int destreg; | |
2008 | if (op1 < 2) | |
2009 | op1 += 16; | |
2010 | op1 = GPR[op1]; | |
2011 | if (op2 < 2) | |
2012 | op2 += 16; | |
2013 | destreg = op2; | |
2014 | op2 = GPR[op2]; | |
2015 | if (have_extendval) | |
2016 | SignalException (ReservedInstruction, instruction); | |
2017 | { | |
2018 | op1 &= 0x3F; | |
2019 | GPR[destreg] = ((unsigned64)(op2) >> op1); | |
2020 | } | |
2021 | } | |
2022 | ||
2023 | ||
2024 | 11101,xxx,vvv,10111:RR:16::DSRAV | |
2025 | *mips16: | |
2026 | { | |
2027 | unsigned32 instruction = instruction_0; | |
2028 | signed_word op1 = (instruction >> 8) & 0x7; | |
2029 | signed_word op2 = (instruction >> 5) & 0x7; | |
2030 | int destreg; | |
2031 | if (op1 < 2) | |
2032 | op1 += 16; | |
2033 | op1 = GPR[op1]; | |
2034 | if (op2 < 2) | |
2035 | op2 += 16; | |
2036 | destreg = op2; | |
2037 | op2 = GPR[op2]; | |
2038 | if (have_extendval) | |
2039 | SignalException (ReservedInstruction, instruction); | |
2040 | { | |
2041 | unsigned64 highbit = (unsigned64)1 << 63; | |
2042 | op1 &= 0x3F; | |
2043 | GPR[destreg] = ((unsigned64)(op2) >> op1); | |
2044 | GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0); | |
2045 | } | |
2046 | } | |
2047 | ||
2048 | ||
2049 | // Multiply /Divide Instructions | |
2050 | ||
2051 | ||
2052 | 11101,xxx,yyy,11000:RR:16::MULT | |
2053 | *mips16: | |
2054 | { | |
2055 | unsigned32 instruction = instruction_0; | |
2056 | signed_word op1 = (instruction >> 8) & 0x7; | |
2057 | signed_word op2 = (instruction >> 5) & 0x7; | |
2058 | if (op1 < 2) | |
2059 | op1 += 16; | |
2060 | op1 = GPR[op1]; | |
2061 | if (op2 < 2) | |
2062 | op2 += 16; | |
2063 | op2 = GPR[op2]; | |
2064 | if (have_extendval) | |
2065 | SignalException (ReservedInstruction, instruction); | |
2066 | { | |
2067 | CHECKHILO("Multiplication"); | |
2068 | { | |
2069 | unsigned64 temp = ((word64) op1 * (word64) op2); | |
2070 | LO = SIGNEXTEND((unsigned64)VL4_8(temp),32); | |
2071 | HI = SIGNEXTEND((unsigned64)VH4_8(temp),32); | |
2072 | } | |
2073 | } | |
2074 | } | |
2075 | ||
2076 | ||
2077 | 11101,xxx,yyy,11001:RR:16::MULTU | |
2078 | *mips16: | |
2079 | { | |
2080 | unsigned32 instruction = instruction_0; | |
2081 | signed_word op1 = (instruction >> 8) & 0x7; | |
2082 | signed_word op2 = (instruction >> 5) & 0x7; | |
2083 | if (op1 < 2) | |
2084 | op1 += 16; | |
2085 | op1 = GPR[op1]; | |
2086 | if (op2 < 2) | |
2087 | op2 += 16; | |
2088 | op2 = GPR[op2]; | |
2089 | if (have_extendval) | |
2090 | SignalException (ReservedInstruction, instruction); | |
2091 | { | |
2092 | CHECKHILO("Multiplication"); | |
2093 | { | |
2094 | unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff)); | |
2095 | LO = SIGNEXTEND((unsigned64)VL4_8(temp),32); | |
2096 | HI = SIGNEXTEND((unsigned64)VH4_8(temp),32); | |
2097 | } | |
2098 | } | |
2099 | } | |
2100 | ||
2101 | ||
2102 | 11101,xxx,yyy,11010:RR:16::DIV | |
2103 | *mips16: | |
2104 | { | |
2105 | unsigned32 instruction = instruction_0; | |
2106 | signed_word op1 = (instruction >> 8) & 0x7; | |
2107 | signed_word op2 = (instruction >> 5) & 0x7; | |
2108 | if (op1 < 2) | |
2109 | op1 += 16; | |
2110 | op1 = GPR[op1]; | |
2111 | if (op2 < 2) | |
2112 | op2 += 16; | |
2113 | op2 = GPR[op2]; | |
2114 | if (have_extendval) | |
2115 | SignalException (ReservedInstruction, instruction); | |
2116 | { | |
2117 | CHECKHILO("Division"); | |
2118 | { | |
2119 | int d1 = op1; | |
2120 | int d2 = op2; | |
2121 | if (d2 == 0) | |
2122 | { | |
2123 | LO = SIGNEXTEND(0x80000000,32); | |
2124 | HI = SIGNEXTEND(0,32); | |
2125 | } | |
2126 | else if (d2 == -1 && d1 == 0x80000000) | |
2127 | { | |
2128 | LO = SIGNEXTEND(0x80000000,32); | |
2129 | HI = SIGNEXTEND(0,32); | |
2130 | } | |
2131 | else | |
2132 | { | |
2133 | LO = SIGNEXTEND((d1 / d2),32); | |
2134 | HI = SIGNEXTEND((d1 % d2),32); | |
2135 | } | |
2136 | } | |
2137 | } | |
2138 | } | |
2139 | ||
2140 | ||
2141 | 11101,xxx,yyy,11011:RR:16::DIVU | |
2142 | *mips16: | |
2143 | { | |
2144 | unsigned32 instruction = instruction_0; | |
2145 | signed_word op1 = (instruction >> 8) & 0x7; | |
2146 | signed_word op2 = (instruction >> 5) & 0x7; | |
2147 | if (op1 < 2) | |
2148 | op1 += 16; | |
2149 | op1 = GPR[op1]; | |
2150 | if (op2 < 2) | |
2151 | op2 += 16; | |
2152 | op2 = GPR[op2]; | |
2153 | if (have_extendval) | |
2154 | SignalException (ReservedInstruction, instruction); | |
2155 | { | |
2156 | CHECKHILO("Division"); | |
2157 | { | |
2158 | unsigned int d1 = op1; | |
2159 | unsigned int d2 = op2; | |
2160 | if (d2 == 0) | |
2161 | { | |
2162 | LO = SIGNEXTEND(0x80000000,32); | |
2163 | HI = SIGNEXTEND(0,32); | |
2164 | } | |
2165 | else if (d2 == -1 && d1 == 0x80000000) | |
2166 | { | |
2167 | LO = SIGNEXTEND(0x80000000,32); | |
2168 | HI = SIGNEXTEND(0,32); | |
2169 | } | |
2170 | else | |
2171 | { | |
2172 | LO = SIGNEXTEND((d1 / d2),32); | |
2173 | HI = SIGNEXTEND((d1 % d2),32); | |
2174 | } | |
2175 | } | |
2176 | } | |
2177 | } | |
2178 | ||
2179 | ||
2180 | 11101,ddd,00010000:RR:16::MFHI | |
2181 | *mips16: | |
2182 | { | |
2183 | unsigned32 instruction = instruction_0; | |
2184 | int destreg = (instruction >> 8) & 0x7; | |
2185 | if (destreg < 2) | |
2186 | destreg += 16; | |
2187 | if (have_extendval) | |
2188 | SignalException (ReservedInstruction, instruction); | |
2189 | { | |
2190 | GPR[destreg] = HI; | |
2191 | HIACCESS = 3; /* 3rd instruction will be safe */ | |
2192 | } | |
2193 | } | |
2194 | ||
2195 | ||
2196 | 11101,ddd,00010010:RR:16::MFLO | |
2197 | *mips16: | |
2198 | { | |
2199 | unsigned32 instruction = instruction_0; | |
2200 | int destreg = (instruction >> 8) & 0x7; | |
2201 | if (destreg < 2) | |
2202 | destreg += 16; | |
2203 | if (have_extendval) | |
2204 | SignalException (ReservedInstruction, instruction); | |
2205 | { | |
2206 | GPR[destreg] = LO; | |
2207 | LOACCESS = 3; /* 3rd instruction will be safe */ | |
2208 | } | |
2209 | } | |
2210 | ||
2211 | ||
2212 | 11101,xxx,yyy,11100:RR:16::DMULT | |
2213 | *mips16: | |
2214 | { | |
2215 | unsigned32 instruction = instruction_0; | |
2216 | signed_word op1 = (instruction >> 8) & 0x7; | |
2217 | signed_word op2 = (instruction >> 5) & 0x7; | |
2218 | if (op1 < 2) | |
2219 | op1 += 16; | |
2220 | op1 = GPR[op1]; | |
2221 | if (op2 < 2) | |
2222 | op2 += 16; | |
2223 | op2 = GPR[op2]; | |
2224 | if (have_extendval) | |
2225 | SignalException (ReservedInstruction, instruction); | |
2226 | { | |
2227 | CHECKHILO("Multiplication"); | |
2228 | { | |
2229 | unsigned64 mid; | |
2230 | unsigned64 midhi; | |
2231 | unsigned64 temp; | |
2232 | int sign = 0; | |
2233 | if (op1 < 0) { op1 = - op1; ++sign; } | |
2234 | if (op2 < 0) { op2 = - op2; ++sign; } | |
2235 | LO = ((unsigned64)VL4_8(op1) * VL4_8(op2)); | |
2236 | HI = ((unsigned64)VH4_8(op1) * VH4_8(op2)); | |
2237 | mid = ((unsigned64)VH4_8(op1) * VL4_8(op2)); | |
2238 | midhi = SET64HI(VL4_8(mid)); | |
2239 | temp = (LO + midhi); | |
2240 | if ((temp == midhi) ? (LO != 0) : (temp < midhi)) | |
2241 | HI += 1; | |
2242 | HI += VH4_8(mid); | |
2243 | mid = ((unsigned64)VL4_8(op1) * VH4_8(op2)); | |
2244 | midhi = SET64HI(VL4_8(mid)); | |
2245 | LO = (temp + midhi); | |
2246 | if ((LO == midhi) ? (temp != 0) : (LO < midhi)) | |
2247 | HI += 1; | |
2248 | HI += VH4_8(mid); | |
2249 | if (sign & 1) { LO = - LO; HI = (LO == 0 ? 0 : -1) - HI; } | |
2250 | } | |
2251 | } | |
2252 | } | |
2253 | ||
2254 | ||
2255 | 11101,xxx,yyy,11101:RR:16::DMULTU | |
2256 | *mips16: | |
2257 | { | |
2258 | unsigned32 instruction = instruction_0; | |
2259 | signed_word op1 = (instruction >> 8) & 0x7; | |
2260 | signed_word op2 = (instruction >> 5) & 0x7; | |
2261 | if (op1 < 2) | |
2262 | op1 += 16; | |
2263 | op1 = GPR[op1]; | |
2264 | if (op2 < 2) | |
2265 | op2 += 16; | |
2266 | op2 = GPR[op2]; | |
2267 | if (have_extendval) | |
2268 | SignalException (ReservedInstruction, instruction); | |
2269 | { | |
2270 | CHECKHILO("Multiplication"); | |
2271 | { | |
2272 | unsigned64 mid; | |
2273 | unsigned64 midhi; | |
2274 | unsigned64 temp; | |
2275 | LO = ((unsigned64)VL4_8(op1) * VL4_8(op2)); | |
2276 | HI = ((unsigned64)VH4_8(op1) * VH4_8(op2)); | |
2277 | mid = ((unsigned64)VH4_8(op1) * VL4_8(op2)); | |
2278 | midhi = SET64HI(VL4_8(mid)); | |
2279 | temp = (LO + midhi); | |
2280 | if ((temp == midhi) ? (LO != 0) : (temp < midhi)) | |
2281 | HI += 1; | |
2282 | HI += VH4_8(mid); | |
2283 | mid = ((unsigned64)VL4_8(op1) * VH4_8(op2)); | |
2284 | midhi = SET64HI(VL4_8(mid)); | |
2285 | LO = (temp + midhi); | |
2286 | if ((LO == midhi) ? (temp != 0) : (LO < midhi)) | |
2287 | HI += 1; | |
2288 | HI += VH4_8(mid); | |
2289 | } | |
2290 | } | |
2291 | } | |
2292 | ||
2293 | ||
2294 | 11101,xxx,yyy,11110:RR:16::DDIV | |
2295 | *mips16: | |
2296 | { | |
2297 | unsigned32 instruction = instruction_0; | |
2298 | signed_word op1 = (instruction >> 8) & 0x7; | |
2299 | signed_word op2 = (instruction >> 5) & 0x7; | |
2300 | if (op1 < 2) | |
2301 | op1 += 16; | |
2302 | op1 = GPR[op1]; | |
2303 | if (op2 < 2) | |
2304 | op2 += 16; | |
2305 | op2 = GPR[op2]; | |
2306 | if (have_extendval) | |
2307 | SignalException (ReservedInstruction, instruction); | |
2308 | { | |
2309 | CHECKHILO("Division"); | |
2310 | { | |
2311 | word64 d1 = op1; | |
2312 | word64 d2 = op2; | |
2313 | if (d2 == 0) | |
2314 | { | |
2315 | LO = SIGNED64 (0x8000000000000000); | |
2316 | HI = 0; | |
2317 | } | |
2318 | else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000)) | |
2319 | { | |
2320 | LO = SIGNED64 (0x8000000000000000); | |
2321 | HI = 0; | |
2322 | } | |
2323 | else | |
2324 | { | |
2325 | LO = (d1 / d2); | |
2326 | HI = (d1 % d2); | |
2327 | } | |
2328 | } | |
2329 | } | |
2330 | } | |
2331 | ||
2332 | ||
2333 | 11101,xxx,yyy,11111:RR:16::DDIVU | |
2334 | *mips16: | |
2335 | { | |
2336 | unsigned32 instruction = instruction_0; | |
2337 | signed_word op1 = (instruction >> 8) & 0x7; | |
2338 | signed_word op2 = (instruction >> 5) & 0x7; | |
2339 | if (op1 < 2) | |
2340 | op1 += 16; | |
2341 | op1 = GPR[op1]; | |
2342 | if (op2 < 2) | |
2343 | op2 += 16; | |
2344 | op2 = GPR[op2]; | |
2345 | if (have_extendval) | |
2346 | SignalException (ReservedInstruction, instruction); | |
2347 | { | |
2348 | CHECKHILO("Division"); | |
2349 | { | |
2350 | unsigned64 d1 = op1; | |
2351 | unsigned64 d2 = op2; | |
2352 | if (d2 == 0) | |
2353 | { | |
2354 | LO = SIGNED64 (0x8000000000000000); | |
2355 | HI = 0; | |
2356 | } | |
2357 | else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000)) | |
2358 | { | |
2359 | LO = SIGNED64 (0x8000000000000000); | |
2360 | HI = 0; | |
2361 | } | |
2362 | else | |
2363 | { | |
2364 | LO = (d1 / d2); | |
2365 | HI = (d1 % d2); | |
2366 | } | |
2367 | } | |
2368 | } | |
2369 | } | |
2370 | ||
2371 | ||
2372 | // Jump and Branch Instructions | |
2373 | ||
2374 | ||
2375 | // JALX | |
2376 | // JAL | |
2377 | 00011,aaaaaaaaaaa:I:16::JAL | |
2378 | *mips16: | |
2379 | { | |
2380 | unsigned32 instruction = instruction_0; | |
2381 | unsigned_word op1 = (instruction >> 0) & 0x7ff; | |
2382 | { | |
2383 | address_word paddr; | |
2384 | int uncached; | |
2385 | if (AddressTranslation (PC &~ (unsigned64) 1, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL)) | |
2386 | { | |
2387 | unsigned64 memval; | |
2388 | unsigned int reverse = (ReverseEndian ? 3 : 0); | |
2389 | unsigned int bigend = (BigEndianCPU ? 3 : 0); | |
2390 | unsigned int byte; | |
2391 | paddr = ((paddr & ~0x7) | ((paddr & 0x7) ^ (reverse << 1))); | |
2392 | LoadMemory (&memval,0,uncached, AccessLength_HALFWORD, paddr, PC, isINSTRUCTION, isREAL); | |
2393 | byte = (((PC &~ (unsigned64) 1) & 0x7) ^ (bigend << 1)); | |
2394 | memval = (memval >> (8 * byte)) & 0xffff; | |
2395 | op1 = (((op1 & 0x1f) << 23) | |
2396 | | ((op1 & 0x3e0) << 13) | |
2397 | | (memval << 2)); | |
2398 | if ((instruction & 0x400) == 0) | |
2399 | op1 |= 1; | |
2400 | PC += 2; | |
2401 | } | |
2402 | } | |
2403 | op1 |= PC & ~ (unsigned64) 0x0fffffff; | |
2404 | if (have_extendval) | |
2405 | SignalException (ReservedInstruction, instruction); | |
2406 | { | |
2407 | int destreg = 31; | |
2408 | GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */ | |
2409 | /* NOTE: ??? Gdb gets confused if the PC is sign-extended, | |
2410 | so we just truncate it to 32 bits here. */ | |
2411 | op1 = VL4_8(op1); | |
2412 | /* NOTE: The jump occurs AFTER the next instruction has been executed */ | |
2413 | DELAY_SLOT op1; | |
2414 | JALDELAYSLOT(); | |
2415 | } | |
2416 | } | |
2417 | ||
2418 | ||
2419 | 11101,xxx,00000000:RR:16::JR | |
2420 | *mips16: | |
2421 | { | |
2422 | unsigned32 instruction = instruction_0; | |
2423 | signed_word op1 = (instruction >> 8) & 0x7; | |
2424 | if (op1 < 2) | |
2425 | op1 += 16; | |
2426 | op1 = GPR[op1]; | |
2427 | if (have_extendval) | |
2428 | SignalException (ReservedInstruction, instruction); | |
2429 | { | |
2430 | /* NOTE: ??? Gdb gets confused if the PC is sign-extended, | |
2431 | so we just truncate it to 32 bits here. */ | |
2432 | op1 = VL4_8(op1); | |
2433 | /* NOTE: The jump occurs AFTER the next instruction has been executed */ | |
2434 | DELAY_SLOT op1; | |
2435 | DELAYSLOT(); | |
2436 | } | |
2437 | } | |
2438 | ||
2439 | ||
2440 | 1110100000100000,r:RR:16::JRRA | |
2441 | *mips16: | |
2442 | { | |
2443 | unsigned32 instruction = instruction_0; | |
2444 | signed_word op1 = 31; | |
2445 | op1 = GPR[op1]; | |
2446 | if (have_extendval) | |
2447 | SignalException (ReservedInstruction, instruction); | |
2448 | { | |
2449 | /* NOTE: ??? Gdb gets confused if the PC is sign-extended, | |
2450 | so we just truncate it to 32 bits here. */ | |
2451 | op1 = VL4_8(op1); | |
2452 | /* NOTE: The jump occurs AFTER the next instruction has been executed */ | |
2453 | DELAY_SLOT op1; | |
2454 | DELAYSLOT(); | |
2455 | } | |
2456 | } | |
2457 | ||
2458 | ||
2459 | 11101,xxx,01000000,R:RR:16::JALR | |
2460 | *mips16: | |
2461 | { | |
2462 | unsigned32 instruction = instruction_0; | |
2463 | signed_word op1 = (instruction >> 8) & 0x7; | |
2464 | int destreg = 31; | |
2465 | if (op1 < 2) | |
2466 | op1 += 16; | |
2467 | op1 = GPR[op1]; | |
2468 | if (have_extendval) | |
2469 | SignalException (ReservedInstruction, instruction); | |
2470 | { | |
2471 | GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */ | |
2472 | /* NOTE: ??? Gdb gets confused if the PC is sign-extended, | |
2473 | so we just truncate it to 32 bits here. */ | |
2474 | op1 = VL4_8(op1); | |
2475 | /* NOTE: The jump occurs AFTER the next instruction has been executed */ | |
2476 | DELAY_SLOT op1; | |
2477 | DELAYSLOT(); | |
2478 | } | |
2479 | } | |
2480 | ||
2481 | ||
2482 | 00100,xxx,pppppppp,z:RI:16::BEQZ | |
2483 | *mips16: | |
2484 | { | |
2485 | unsigned32 instruction = instruction_0; | |
2486 | signed_word op1 = (instruction >> 8) & 0x7; | |
2487 | int offset = (instruction >> 0) & 0xff; | |
2488 | signed_word op2 = 0; | |
2489 | if (op1 < 2) | |
2490 | op1 += 16; | |
2491 | op1 = GPR[op1]; | |
2492 | if (have_extendval) | |
2493 | { | |
2494 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
2495 | if (offset >= 0x8000) | |
2496 | offset -= 0x10000; | |
2497 | have_extendval = 0; | |
2498 | } | |
2499 | else | |
2500 | { | |
2501 | if (offset >= 0x80) | |
2502 | offset -= 0x100; | |
2503 | } | |
2504 | offset *= 2; | |
2505 | if (have_extendval) | |
2506 | SignalException (ReservedInstruction, instruction); | |
2507 | { | |
2508 | int condition = (op1 == op2); | |
2509 | if (condition) | |
2510 | PC = PC + offset; | |
2511 | } | |
2512 | } | |
2513 | ||
2514 | ||
2515 | 00101,xxx,pppppppp,z:RI:16::BNEZ | |
2516 | *mips16: | |
2517 | { | |
2518 | unsigned32 instruction = instruction_0; | |
2519 | signed_word op1 = (instruction >> 8) & 0x7; | |
2520 | int offset = (instruction >> 0) & 0xff; | |
2521 | signed_word op2 = 0; | |
2522 | if (op1 < 2) | |
2523 | op1 += 16; | |
2524 | op1 = GPR[op1]; | |
2525 | if (have_extendval) | |
2526 | { | |
2527 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
2528 | if (offset >= 0x8000) | |
2529 | offset -= 0x10000; | |
2530 | have_extendval = 0; | |
2531 | } | |
2532 | else | |
2533 | { | |
2534 | if (offset >= 0x80) | |
2535 | offset -= 0x100; | |
2536 | } | |
2537 | offset *= 2; | |
2538 | if (have_extendval) | |
2539 | SignalException (ReservedInstruction, instruction); | |
2540 | { | |
2541 | int condition = (op1 != op2); | |
2542 | if (condition) | |
2543 | PC = PC + offset; | |
2544 | } | |
2545 | } | |
2546 | ||
2547 | ||
2548 | 01100000,pppppppp,t,z:I8:16::BTEQZ | |
2549 | *mips16: | |
2550 | { | |
2551 | unsigned32 instruction = instruction_0; | |
2552 | int offset = (instruction >> 0) & 0xff; | |
2553 | signed_word op1 = 24; | |
2554 | signed_word op2 = 0; | |
2555 | if (have_extendval) | |
2556 | { | |
2557 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
2558 | if (offset >= 0x8000) | |
2559 | offset -= 0x10000; | |
2560 | have_extendval = 0; | |
2561 | } | |
2562 | else | |
2563 | { | |
2564 | if (offset >= 0x80) | |
2565 | offset -= 0x100; | |
2566 | } | |
2567 | offset *= 2; | |
2568 | op1 = GPR[op1]; | |
2569 | if (have_extendval) | |
2570 | SignalException (ReservedInstruction, instruction); | |
2571 | { | |
2572 | int condition = (op1 == op2); | |
2573 | if (condition) | |
2574 | PC = PC + offset; | |
2575 | } | |
2576 | } | |
2577 | ||
2578 | ||
2579 | 01100001,pppppppp,t,z:I8:16::BTNEZ | |
2580 | *mips16: | |
2581 | { | |
2582 | unsigned32 instruction = instruction_0; | |
2583 | int offset = (instruction >> 0) & 0xff; | |
2584 | signed_word op1 = 24; | |
2585 | signed_word op2 = 0; | |
2586 | if (have_extendval) | |
2587 | { | |
2588 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
2589 | if (offset >= 0x8000) | |
2590 | offset -= 0x10000; | |
2591 | have_extendval = 0; | |
2592 | } | |
2593 | else | |
2594 | { | |
2595 | if (offset >= 0x80) | |
2596 | offset -= 0x100; | |
2597 | } | |
2598 | offset *= 2; | |
2599 | op1 = GPR[op1]; | |
2600 | if (have_extendval) | |
2601 | SignalException (ReservedInstruction, instruction); | |
2602 | { | |
2603 | int condition = (op1 != op2); | |
2604 | if (condition) | |
2605 | PC = PC + offset; | |
2606 | } | |
2607 | } | |
2608 | ||
2609 | ||
2610 | 00010,qqqqqqqqqqq,z,Z:I:16::B | |
2611 | *mips16: | |
2612 | { | |
2613 | unsigned32 instruction = instruction_0; | |
2614 | int offset = (instruction >> 0) & 0x7ff; | |
2615 | signed_word op2 = 0; | |
2616 | signed_word op1 = 0; | |
2617 | if (have_extendval) | |
2618 | { | |
2619 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
2620 | if (offset >= 0x8000) | |
2621 | offset -= 0x10000; | |
2622 | have_extendval = 0; | |
2623 | } | |
2624 | else | |
2625 | { | |
2626 | if (offset >= 0x400) | |
2627 | offset -= 0x800; | |
2628 | } | |
2629 | offset *= 2; | |
2630 | if (have_extendval) | |
2631 | SignalException (ReservedInstruction, instruction); | |
2632 | { | |
2633 | int condition = (op1 == op2); | |
2634 | if (condition) | |
2635 | PC = PC + offset; | |
2636 | } | |
2637 | } | |
2638 | ||
2639 | ||
2640 | // Special Instructions | |
2641 | ||
2642 | ||
2643 | // See the front of the mips16 doc | |
2644 | 11110,eeeeeeeeeee:I:16::EXTEND | |
2645 | *mips16: | |
2646 | { | |
2647 | unsigned32 instruction = instruction_0; | |
2648 | int ext = (instruction >> 0) & 0x7ff; | |
2649 | if (have_extendval) | |
2650 | SignalException (ReservedInstruction, instruction); | |
2651 | { | |
2652 | extendval = ext; | |
2653 | have_extendval = 1; | |
2654 | } | |
2655 | } | |
2656 | ||
2657 | ||
2658 | 01100,******,00101:RR:16::BREAK | |
2659 | *mips16: | |
2660 | { | |
2661 | unsigned32 instruction = instruction_0; | |
2662 | if (have_extendval) | |
2663 | SignalException (ReservedInstruction, instruction); | |
2664 | { | |
2665 | SignalException(BreakPoint,instruction); | |
2666 | } | |
2667 | } | |
2668 |