[deliverable/binutils-gdb.git] / sim / mips / m16.igen

// -*- C -*-
//
//
// MIPS Architecture:
//
//        CPU Instruction Set (mips16)
//

// The instructions in this section are ordered according
// to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.


// The MIPS16 codes registers in a special way, map from one to the other.
// :<type>:<flags>:<models>:<typedef>:<name>:<field>:<expression>
:compute:::int:TRX:RX:((RX < 2) ? (16 + RX) \: RX)
:compute:::int:TRY:RY:((RY < 2) ? (16 + RY) \: RY)
:compute:::int:TRZ:RZ:((RZ < 2) ? (16 + RZ) \: RZ)
:compute:::int:SHIFT:SHAMT:((SHAMT == 0) ? 8 \: SHAMT)


// FIXME:
//
// Only the `LB' instruction is implemented.  It should be used as a guideline
// when implementing other instructions.
//
// How to handle delayslots (for jumps) and extended lwpc instructions
// has not been resolved.


011101,26.INSTR_INDEX:NORMAL:32::JALX
*r3900:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
/// {
/// }


// Load and Store Instructions


10000,3.RX,3.RY,5.IMMED:RRI:16::LB
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
}


10100,3.RX,3.RY,5.IMMED:RRI:16::LBU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
}


10001,3.RX,3.RY,5.IMMED:RRI:16::LH
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
}


10101,3.RX,3.RY,5.IMMED:RRI:16::LHU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
}


10011,3.RX,3.RY,5.IMMED:RRI:16::LW
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
}


10110,3.RX,8.IMMED:RI:16::LWPC
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD,
				basepc (SD_) & ~3, IMMED << 2));
}


10010,3.RX,8.IMMED:RI:16::LWSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMMED << 2));
}


10111,3.RX,3.RY,5.IMMED:RRI:16::LWU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2);
}


00111,3.RX,3.RY,5.IMMED:RRI:16,64::LD
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3);
}


11111,100,3.RY,5.IMMED:RI64:16::LDPC
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD,
		      basepc (SD_) & ~7, IMMED << 3);
}


11111,000,3.RY,5.IMMED:RI64:16::LDSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3);
}


11000,3.RX,3.RY,5.IMMED:RRI:16::SB
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_BYTE, GPR[TRX], IMMED, GPR[TRY]);
}


11001,3.RX,3.RY,5.IMMED:RRI:16::SH
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1, GPR[TRY]);
}


11011,3.RX,3.RY,5.IMMED:RRI:16::SW
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2, GPR[TRY]);
}


11010,3.RX,8.IMMED:RI:16::SWSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_WORD, SP, IMMED << 2, GPR[TRX]);
}


01100,010,8.IMMED:I8:16::SWRASP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_WORD, SP, IMMED << 2, RA);
}


01111,3.RX,3.RY,5.IMMED:RRI:16::SD
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3, GPR[TRY]);
}


11111,001,3.RY,5.IMMED:RI64:16::SDSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, GPR[TRY]);
}


11111,010,8.IMMED:I64:16::SDRASP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, RA);
}


// ALU Immediate Instructions


01101,3.RX,8.IMMED::RI:16::LI
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_ori (SD_, 0, TRX, IMMED);
}


01000,3.RX,3.RY,0,4.IMMED:RRI_A:16::ADDIU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_addiu (SD_, TRX, TRY, EXTEND4 (IMMED));
}


01001,3.RX,8.IMMED:RI:16::ADDIU8
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_addiu (SD_, TRX, TRX, EXTEND8 (IMMED));
}


01100,011,8.IMMED:I8:16::ADJSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_addiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
}


00001,3.RX,8.IMMED:RI:16::ADDIUPC
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  unsigned32 temp = (basepc (SD_) & ~3) + (EXTEND8 (IMMED) << 2);
  GPR[TRX] = EXTEND32 (temp);
}


00000,3.RX,8.IMMED:RI:16::ADDIUSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_addiu (SD_, SPIDX, TRX, EXTEND8 (IMMED) << 2);
}


01000,3.RX,3.RY,1,4.IMMED:RRI_A:16,64::DADDIU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_daddiu (SD_, TRX, TRY, EXTEND4 (IMMED));
}


11111,101,3.RY,5.IMMED:RI64:16,64::DADDIU5
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMED));
}


11111,011,8.IMMED:I64:16,64::DADJSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_daddiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
}


11111,110,3.RY,5.IMMED:RI64:16,64::DADDIUPC
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = (basepc (SD_) & ~3) + (EXTEND5 (IMMED) << 2);
}


11111,111,3.RY,5.IMMED:RI64:16,64::DADDIUSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_daddiu (SD_, SPIDX, TRY, EXTEND5 (IMMED) << 2);
}


01010,3.RX,8.IMMED:RI:16::SLTI
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_slti (SD_, TRX, T8IDX, IMMED);
}


01011,3.RX,8.IMMED:RI:16::SLTIU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_sltiu (SD_, TRX, T8IDX, IMMED);
}


11101,3.RX,3.RY,01010:RR:16::CMP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_xor (SD_, TRX, TRY, T8IDX);
}


01110,3.RX,8.IMMED:RI:16::CMPI
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_xori (SD_, TRX, T8IDX, IMMED);
}


// Two/Three Operand, Register-Type


11100,3.RX,3.RY,3.RZ,01:RRR:16::ADDU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_addu (SD_, TRX, TRY, TRZ);
}


11100,3.RX,3.RY,3.RZ,11:RRR:16::SUBU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_subu (SD_, TRX, TRY, TRZ);
}


11100,3.RX,3.RY,3.RZ,00:RRR:16,64::DADDU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_daddu (SD_, TRX, TRY, TRZ);
}


11100,3.RX,3.RY,3.RZ,10:RRR:16,64::DSUBU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dsubu (SD_, TRX, TRY, TRZ);
}


11101,3.RX,3.RY,00010:RR:16::SLT
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_slt (SD_, TRX, TRY, T8IDX);
}


11101,3.RX,3.RY,00011:RR:16::SLTU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_sltu (SD_, TRX, TRY, T8IDX);
}


11101,3.RX,3.RY,01011:RR:16::NEG
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_subu (SD_, 0, TRY, TRX);
}


11101,3.RX,3.RY,01100:RR:16::AND
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_and (SD_, TRX, TRY, TRX);
}


11101,3.RX,3.RY,01101:RR:16::OR
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_or (SD_, TRX, TRY, TRX);
}


11101,3.RX,3.RY,01110:RR:16::XOR
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_xor (SD_, TRX, TRY, TRX);
}


11101,3.RX,3.RY,01111:RR:16::NOT
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_nor (SD_, 0, TRY, TRX);
}


01100,111,3.RY,5.R32:I8_MOVR32:16::MOVR32
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_or (SD_, R32, 0, TRY);
}


01100,101,3.R32L,2.R32H,3.RZ:I8_MOV32R:16::MOV32R
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_or (SD_, TRZ, 0, (R32H << 3) | R32L);
}


00110,3.RX,3.RY,3.SHAMT,00:ISHIFT:16::SLL
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_sll (SD_, TRY, TRX, SHIFT);
}


00110,3.RX,3.RY,3.SHAMT,10:ISHIFT:16::SRL
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_srl (SD_, TRY, TRX, SHIFT);
}


00110,3.RX,3.RY,3.SHAMT,11:ISHIFT:16::SRA
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_sra (SD_, TRY, TRX, SHIFT);
}


11101,3.RX,3.RY,00100:RR:16::SLLV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_sllv (SD_, TRX, TRY, TRY);
}


11101,3.RX,3.RY,00110:RR:16::SRLV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_srlv (SD_, TRX, TRY, TRY);
}


11101,3.RX,3.RY,00111:RR:16::SRAV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_srav (SD_, TRX, TRY, TRY);
}


00110,3.RX,3.RY,3.SHAMT,01:ISHIFT:16,64::DSLL
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dsll (SD_, 0, TRY, TRX, SHIFT);
}
  
  
11101,3.SHAMT,3.RY,01000:RR:16,64::DSRL
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dsrl (SD_, 0, TRY, TRY, SHIFT);
}


11101,3.SHAMT,3.RY,10011:RR:16,64::DSRA
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dsra (SD_, 0, TRY, TRY, SHIFT);
}


11101,3.RX,3.RY,10100:RR:16,64::DSLLV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dsllv (SD_, TRX, TRY, TRY);
}


11101,3.RX,3.RY,10110:RR:16,64::DSRLV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dsrlv (SD_, TRX, TRY, TRY);
}


11101,3.RX,3.RY,10111:RR:16,64::DSRAV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dsrav (SD_, TRX, TRY, TRY);
}


// Multiply /Divide Instructions


11101,3.RX,3.RY,11000:RR:16::MULT
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_mult (SD_, TRX, TRY, 0);
}


11101,3.RX,3.RY,11001:RR:16::MULTU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_multu (SD_, TRX, TRY, 0);
}


11101,3.RX,3.RY,11010:RR:16::DIV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_div (SD_, TRX, TRY);
}


11101,3.RX,3.RY,11011:RR:16::DIVU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_divu (SD_, TRX, TRY);
}


11101,3.RX,000,10000:RR:16::MFHI
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_mfhi (SD_, TRX);
}


11101,3.RX,000,10010:RR:16::MFLO
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_mflo (SD_, TRX);
}


11101,3.RX,3.RY,11100:RR:16,64::DMULT
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dmult (SD_, TRX, TRY);
}


11101,3.RX,3.RY,11101:RR:16,64::DMULTU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dmultu (SD_, TRX, TRY);
}


11101,3.RX,3.RY,11110:RR:16,64::DDIV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_ddiv (SD_, TRX, TRY);
}


11101,3.RX,3.RY,11111:RR:16,64::DDIVU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_ddivu (SD_, TRX, TRY);
}


// Jump and Branch Instructions


// Issue instruction in delay slot of branch
:function:::address_word:delayslot16:address_word target
{
  instruction_word delay_insn;
  sim_events_slip (SD, 1);
  DSPC = CIA; /* save current PC somewhere */
  CIA = CIA + 2; /* NOTE: mips16 */
  STATE |= simDELAYSLOT;
  delay_insn = IMEM16 (CIA); /* NOTE: mips16 */
  idecode_issue (CPU_, delay_insn, (CIA));
  STATE &= ~simDELAYSLOT;
  return target;
}
  
// compute basepc dependant on us being in a delay slot
:function:::address_word:basepc:
{
  if (STATE & simDELAYSLOT)
    {
      return DSPC; /* return saved address of preceeding jmp */
    }
  else
    {
      return CIA;
    }
}


// JAL
00011,0,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:I:16::JAL
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  NIA = delayslot16 (SD_,
		     (LSMASKED (NIA, 31, 26)
		      | LSINSERTED (IMM_25_21, 25, 21)
		      | LSINSERTED (IMM_20_16, 20, 16)
		      | LSINSERTED (IMMED_15_0, 15, 0)));
}


// JALX
00011,1,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:I:16::JALX
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  NIA = delayslot16 (SD_,
		     (LSMASKED (NIA, 31, 26)
		      | LSINSERTED (IMM_25_21, 25, 21)
		      | LSINSERTED (IMM_20_16, 20, 16)
		      | LSINSERTED (IMMED_15_0, 15, 0)));
  NIA = NIA ^ 1;
}


11101,3.RX,000,00000:RR:16::JR
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  NIA = delayslot16 (SD_, GPR[TRX]);
}


11101,000,001,00000:RR:16::JRRA
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  NIA = delayslot16 (SD_, RA);
}


11101,3.RX,010,00000:RR:16::JALR
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  RA = NIA + 2;
  NIA = delayslot16 (SD_, GPR[TRX]);
}


00100,3.RX,8.IMMED:RI:16::BEQZ
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  if (GPR[RX] == 0)
    NIA = (NIA + (EXTEND8 (IMMED) << 2));
}


00101,3.RX,8.IMMED:RI:16::BNEZ
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  if (GPR[RX] != 0)
    NIA = (NIA + (EXTEND8 (IMMED) << 2));
}


01100,000,8.IMMED:I8:16::BTEQZ
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  if (T8 == 0)
    NIA = (NIA + (EXTEND8 (IMMED) << 2));
}


01100,001,8.IMMED:I8:16::BTNEZ
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  if (T8 != 0)
    NIA = (NIA + (EXTEND8 (IMMED) << 2));
}


00010,11.IMMED:I:16::B
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  NIA = (NIA + (EXTEND8 (IMMED) << 2));
}


// Special Instructions


// See the front of the mips16 doc
//     -> FIXME need this for most instructions
// 11110,eeeeeeeeeee:I:16::EXTEND
// *mips16:
// // start-sanitize-tx19
// *tx19:
// // end-sanitize-tx19


// 11101,3.RX,3.RY,00101:RR:16::BREAK
// *mips16:
// // start-sanitize-tx19
// *tx19:
// // end-sanitize-tx19
Commit	Line	Data
c0a4c3ba AC	1	// -- C --
c0a4c3ba AC	2	//
16bd5d6e AC	3	//
	4	// MIPS Architecture:
	5	//
	6	// CPU Instruction Set (mips16)
	7	//
	8
	9	// The instructions in this section are ordered according
	10	// to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.
	11
	12
c0a4c3ba AC	13	// The MIPS16 codes registers in a special way, map from one to the other.
	14	// :<type>:<flags>:<models>:<typedef>:<name>:<field>:<expression>
	15	:compute:::int:TRX:RX:((RX < 2) ? (16 + RX) \: RX)
	16	:compute:::int:TRY:RY:((RY < 2) ? (16 + RY) \: RY)
	17	:compute:::int:TRZ:RZ:((RZ < 2) ? (16 + RZ) \: RZ)
	18	:compute:::int:SHIFT:SHAMT:((SHAMT == 0) ? 8 \: SHAMT)
	19
	20
	21	// FIXME:
	22	//
	23	// Only the `LB' instruction is implemented. It should be used as a guideline
	24	// when implementing other instructions.
	25	//
	26	// How to handle delayslots (for jumps) and extended lwpc instructions
	27	// has not been resolved.
	28
	29
	30	011101,26.INSTR_INDEX:NORMAL:32::JALX
	31	*r3900:
	32	// start-sanitize-tx19
	33	*tx19:
	34	// end-sanitize-tx19
	35	/// {
	36	/// }
16bd5d6e AC	37
	38
	39	// Load and Store Instructions
	40
	41
c0a4c3ba	42	10000,3.RX,3.RY,5.IMMED:RRI:16::LB
16bd5d6e	43	*mips16:
c0a4c3ba AC	44	// start-sanitize-tx19
	45	*tx19:
	46	// end-sanitize-tx19
16bd5d6e	47	{
c0a4c3ba	48	GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
16bd5d6e AC	49	}
	50
	51
c0a4c3ba	52	10100,3.RX,3.RY,5.IMMED:RRI:16::LBU
16bd5d6e	53	*mips16:
c0a4c3ba AC	54	// start-sanitize-tx19
	55	*tx19:
	56	// end-sanitize-tx19
16bd5d6e	57	{
c0a4c3ba	58	GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
16bd5d6e AC	59	}
	60
	61
c0a4c3ba	62	10001,3.RX,3.RY,5.IMMED:RRI:16::LH
16bd5d6e	63	*mips16:
c0a4c3ba AC	64	// start-sanitize-tx19
	65	*tx19:
	66	// end-sanitize-tx19
16bd5d6e	67	{
c0a4c3ba	68	GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
16bd5d6e AC	69	}
	70
	71
c0a4c3ba	72	10101,3.RX,3.RY,5.IMMED:RRI:16::LHU
16bd5d6e	73	*mips16:
c0a4c3ba AC	74	// start-sanitize-tx19
	75	*tx19:
	76	// end-sanitize-tx19
16bd5d6e	77	{
c0a4c3ba AC	78	GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
	79	}
	80
	81
	82	10011,3.RX,3.RY,5.IMMED:RRI:16::LW
	83	*mips16:
	84	// start-sanitize-tx19
	85	*tx19:
	86	// end-sanitize-tx19
	87	{
	88	GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
	89	}
	90
	91
	92	10110,3.RX,8.IMMED:RI:16::LWPC
	93	*mips16:
	94	// start-sanitize-tx19
	95	*tx19:
	96	// end-sanitize-tx19
	97	{
	98	GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD,
	99	basepc (SD_) & ~3, IMMED << 2));
	100	}
	101
	102
	103	10010,3.RX,8.IMMED:RI:16::LWSP
	104	*mips16:
	105	// start-sanitize-tx19
	106	*tx19:
	107	// end-sanitize-tx19
	108	{
	109	GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMMED << 2));
	110	}
	111
	112
	113	10111,3.RX,3.RY,5.IMMED:RRI:16::LWU
	114	*mips16:
	115	// start-sanitize-tx19
	116	*tx19:
	117	// end-sanitize-tx19
	118	{
	119	GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2);
	120	}
	121
	122
	123	00111,3.RX,3.RY,5.IMMED:RRI:16,64::LD
	124	*mips16:
	125	// start-sanitize-tx19
	126	*tx19:
	127	// end-sanitize-tx19
	128	{
	129	GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3);
	130	}
	131
	132
	133	11111,100,3.RY,5.IMMED:RI64:16::LDPC
	134	*mips16:
	135	// start-sanitize-tx19
	136	*tx19:
	137	// end-sanitize-tx19
	138	{
	139	GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD,
	140	basepc (SD_) & ~7, IMMED << 3);
	141	}
142
143
144	11111,000,3.RY,5.IMMED:RI64:16::LDSP
145	*mips16:
146	// start-sanitize-tx19
147	*tx19:
148	// end-sanitize-tx19
149	{
150	GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3);
151	}
152
153
154	11000,3.RX,3.RY,5.IMMED:RRI:16::SB
155	*mips16:
156	// start-sanitize-tx19
157	*tx19:
158	// end-sanitize-tx19
159	{
160	do_store (SD_, AccessLength_BYTE, GPR[TRX], IMMED, GPR[TRY]);
161	}
162
163
164	11001,3.RX,3.RY,5.IMMED:RRI:16::SH
165	*mips16:
166	// start-sanitize-tx19
167	*tx19:
168	// end-sanitize-tx19
169	{
170	do_store (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1, GPR[TRY]);
171	}
172
173
174	11011,3.RX,3.RY,5.IMMED:RRI:16::SW
175	*mips16:
176	// start-sanitize-tx19
177	*tx19:
178	// end-sanitize-tx19
179	{
180	do_store (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2, GPR[TRY]);
181	}
182
183
184	11010,3.RX,8.IMMED:RI:16::SWSP
185	*mips16:
186	// start-sanitize-tx19
187	*tx19:
188	// end-sanitize-tx19
189	{
190	do_store (SD_, AccessLength_WORD, SP, IMMED << 2, GPR[TRX]);
191	}
192
193
194	01100,010,8.IMMED:I8:16::SWRASP
195	*mips16:
196	// start-sanitize-tx19
197	*tx19:
198	// end-sanitize-tx19
199	{
200	do_store (SD_, AccessLength_WORD, SP, IMMED << 2, RA);
201	}
202
203
204	01111,3.RX,3.RY,5.IMMED:RRI:16::SD
205	*mips16:
206	// start-sanitize-tx19
207	*tx19:
208	// end-sanitize-tx19
209	{
210	do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3, GPR[TRY]);
211	}
212
213
214	11111,001,3.RY,5.IMMED:RI64:16::SDSP
215	*mips16:
216	// start-sanitize-tx19
217	*tx19:
218	// end-sanitize-tx19
219	{
220	do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, GPR[TRY]);
221	}
222
223
224	11111,010,8.IMMED:I64:16::SDRASP
225	*mips16:
226	// start-sanitize-tx19
227	*tx19:
228	// end-sanitize-tx19
229	{
230	do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, RA);
16bd5d6e AC	231	}
	232
	233
	234	// ALU Immediate Instructions
	235
	236
c0a4c3ba	237	01101,3.RX,8.IMMED::RI:16::LI
16bd5d6e	238	*mips16:
c0a4c3ba AC	239	// start-sanitize-tx19
	240	*tx19:
	241	// end-sanitize-tx19
16bd5d6e	242	{
c0a4c3ba	243	do_ori (SD_, 0, TRX, IMMED);
16bd5d6e AC	244	}
	245
	246
c0a4c3ba	247	01000,3.RX,3.RY,0,4.IMMED:RRI_A:16::ADDIU
16bd5d6e	248	*mips16:
c0a4c3ba AC	249	// start-sanitize-tx19
	250	*tx19:
	251	// end-sanitize-tx19
16bd5d6e	252	{
c0a4c3ba	253	do_addiu (SD_, TRX, TRY, EXTEND4 (IMMED));
16bd5d6e AC	254	}
	255
	256
c0a4c3ba	257	01001,3.RX,8.IMMED:RI:16::ADDIU8
16bd5d6e	258	*mips16:
c0a4c3ba AC	259	// start-sanitize-tx19
	260	*tx19:
	261	// end-sanitize-tx19
16bd5d6e	262	{
c0a4c3ba	263	do_addiu (SD_, TRX, TRX, EXTEND8 (IMMED));
16bd5d6e AC	264	}
	265
	266
c0a4c3ba	267	01100,011,8.IMMED:I8:16::ADJSP
16bd5d6e	268	*mips16:
c0a4c3ba AC	269	// start-sanitize-tx19
	270	*tx19:
	271	// end-sanitize-tx19
16bd5d6e	272	{
c0a4c3ba	273	do_addiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
16bd5d6e AC	274	}
	275
	276
c0a4c3ba	277	00001,3.RX,8.IMMED:RI:16::ADDIUPC
16bd5d6e	278	*mips16:
c0a4c3ba AC	279	// start-sanitize-tx19
	280	*tx19:
	281	// end-sanitize-tx19
16bd5d6e	282	{
c0a4c3ba AC	283	unsigned32 temp = (basepc (SD_) & ~3) + (EXTEND8 (IMMED) << 2);
c0a4c3ba AC	284	GPR[TRX] = EXTEND32 (temp);
16bd5d6e AC	285	}
	286
	287
c0a4c3ba	288	00000,3.RX,8.IMMED:RI:16::ADDIUSP
16bd5d6e	289	*mips16:
c0a4c3ba AC	290	// start-sanitize-tx19
	291	*tx19:
	292	// end-sanitize-tx19
16bd5d6e	293	{
c0a4c3ba	294	do_addiu (SD_, SPIDX, TRX, EXTEND8 (IMMED) << 2);
16bd5d6e AC	295	}
	296
	297
c0a4c3ba	298	01000,3.RX,3.RY,1,4.IMMED:RRI_A:16,64::DADDIU
16bd5d6e	299	*mips16:
c0a4c3ba AC	300	// start-sanitize-tx19
	301	*tx19:
	302	// end-sanitize-tx19
16bd5d6e	303	{
c0a4c3ba	304	do_daddiu (SD_, TRX, TRY, EXTEND4 (IMMED));
16bd5d6e AC	305	}
	306
	307
c0a4c3ba	308	11111,101,3.RY,5.IMMED:RI64:16,64::DADDIU5
16bd5d6e	309	*mips16:
c0a4c3ba AC	310	// start-sanitize-tx19
	311	*tx19:
	312	// end-sanitize-tx19
16bd5d6e	313	{
c0a4c3ba	314	do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMED));
16bd5d6e AC	315	}
	316
	317
c0a4c3ba	318	11111,011,8.IMMED:I64:16,64::DADJSP
16bd5d6e	319	*mips16:
c0a4c3ba AC	320	// start-sanitize-tx19
	321	*tx19:
	322	// end-sanitize-tx19
16bd5d6e	323	{
c0a4c3ba	324	do_daddiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
16bd5d6e AC	325	}
	326
	327
c0a4c3ba	328	11111,110,3.RY,5.IMMED:RI64:16,64::DADDIUPC
16bd5d6e	329	*mips16:
c0a4c3ba AC	330	// start-sanitize-tx19
	331	*tx19:
	332	// end-sanitize-tx19
16bd5d6e	333	{
c0a4c3ba	334	GPR[TRY] = (basepc (SD_) & ~3) + (EXTEND5 (IMMED) << 2);
16bd5d6e AC	335	}
	336
	337
c0a4c3ba	338	11111,111,3.RY,5.IMMED:RI64:16,64::DADDIUSP
16bd5d6e	339	*mips16:
c0a4c3ba AC	340	// start-sanitize-tx19
	341	*tx19:
	342	// end-sanitize-tx19
16bd5d6e	343	{
c0a4c3ba	344	do_daddiu (SD_, SPIDX, TRY, EXTEND5 (IMMED) << 2);
16bd5d6e AC	345	}
	346
	347
c0a4c3ba	348	01010,3.RX,8.IMMED:RI:16::SLTI
16bd5d6e	349	*mips16:
c0a4c3ba AC	350	// start-sanitize-tx19
	351	*tx19:
	352	// end-sanitize-tx19
16bd5d6e	353	{
c0a4c3ba	354	do_slti (SD_, TRX, T8IDX, IMMED);
16bd5d6e AC	355	}
	356
	357
c0a4c3ba	358	01011,3.RX,8.IMMED:RI:16::SLTIU
16bd5d6e	359	*mips16:
c0a4c3ba AC	360	// start-sanitize-tx19
	361	*tx19:
	362	// end-sanitize-tx19
16bd5d6e	363	{
c0a4c3ba	364	do_sltiu (SD_, TRX, T8IDX, IMMED);
16bd5d6e AC	365	}
	366
	367
c0a4c3ba	368	11101,3.RX,3.RY,01010:RR:16::CMP
16bd5d6e	369	*mips16:
c0a4c3ba AC	370	// start-sanitize-tx19
	371	*tx19:
	372	// end-sanitize-tx19
16bd5d6e	373	{
c0a4c3ba AC	374	do_xor (SD_, TRX, TRY, T8IDX);
	375	}
	376
	377
	378	01110,3.RX,8.IMMED:RI:16::CMPI
	379	*mips16:
	380	// start-sanitize-tx19
	381	*tx19:
	382	// end-sanitize-tx19
	383	{
	384	do_xori (SD_, TRX, T8IDX, IMMED);
16bd5d6e AC	385	}
	386
	387
	388	// Two/Three Operand, Register-Type
	389
	390
c0a4c3ba AC	391	11100,3.RX,3.RY,3.RZ,01:RRR:16::ADDU
	392	*mips16:
	393	// start-sanitize-tx19
	394	*tx19:
	395	// end-sanitize-tx19
	396	{
	397	do_addu (SD_, TRX, TRY, TRZ);
16bd5d6e AC	398	}
	399
	400
c0a4c3ba	401	11100,3.RX,3.RY,3.RZ,11:RRR:16::SUBU
16bd5d6e	402	*mips16:
c0a4c3ba AC	403	// start-sanitize-tx19
	404	*tx19:
	405	// end-sanitize-tx19
16bd5d6e	406	{
c0a4c3ba	407	do_subu (SD_, TRX, TRY, TRZ);
16bd5d6e AC	408	}
	409
	410
c0a4c3ba	411	11100,3.RX,3.RY,3.RZ,00:RRR:16,64::DADDU
16bd5d6e	412	*mips16:
c0a4c3ba AC	413	// start-sanitize-tx19
	414	*tx19:
	415	// end-sanitize-tx19
16bd5d6e	416	{
c0a4c3ba AC	417	do_daddu (SD_, TRX, TRY, TRZ);
	418	}
	419
	420
	421	11100,3.RX,3.RY,3.RZ,10:RRR:16,64::DSUBU
	422	*mips16:
	423	// start-sanitize-tx19
	424	*tx19:
	425	// end-sanitize-tx19
	426	{
	427	do_dsubu (SD_, TRX, TRY, TRZ);
	428	}
	429
	430
	431	11101,3.RX,3.RY,00010:RR:16::SLT
	432	*mips16:
	433	// start-sanitize-tx19
	434	*tx19:
	435	// end-sanitize-tx19
	436	{
	437	do_slt (SD_, TRX, TRY, T8IDX);
	438	}
	439
	440
	441	11101,3.RX,3.RY,00011:RR:16::SLTU
	442	*mips16:
	443	// start-sanitize-tx19
	444	*tx19:
	445	// end-sanitize-tx19
	446	{
	447	do_sltu (SD_, TRX, TRY, T8IDX);
	448	}
	449
	450
	451	11101,3.RX,3.RY,01011:RR:16::NEG
	452	*mips16:
	453	// start-sanitize-tx19
	454	*tx19:
	455	// end-sanitize-tx19
	456	{
	457	do_subu (SD_, 0, TRY, TRX);
	458	}
	459
	460
	461	11101,3.RX,3.RY,01100:RR:16::AND
	462	*mips16:
	463	// start-sanitize-tx19
	464	*tx19:
	465	// end-sanitize-tx19
	466	{
	467	do_and (SD_, TRX, TRY, TRX);
	468	}
	469
	470
	471	11101,3.RX,3.RY,01101:RR:16::OR
	472	*mips16:
	473	// start-sanitize-tx19
	474	*tx19:
	475	// end-sanitize-tx19
	476	{
	477	do_or (SD_, TRX, TRY, TRX);
	478	}
	479
	480
481	11101,3.RX,3.RY,01110:RR:16::XOR
482	*mips16:
483	// start-sanitize-tx19
484	*tx19:
485	// end-sanitize-tx19
486	{
487	do_xor (SD_, TRX, TRY, TRX);
488	}
489
490
491	11101,3.RX,3.RY,01111:RR:16::NOT
492	*mips16:
493	// start-sanitize-tx19
494	*tx19:
495	// end-sanitize-tx19
496	{
497	do_nor (SD_, 0, TRY, TRX);
498	}
499
500
501	01100,111,3.RY,5.R32:I8_MOVR32:16::MOVR32
502	*mips16:
503	// start-sanitize-tx19
504	*tx19:
505	// end-sanitize-tx19
506	{
507	do_or (SD_, R32, 0, TRY);
508	}
509
510
511	01100,101,3.R32L,2.R32H,3.RZ:I8_MOV32R:16::MOV32R
512	*mips16:
513	// start-sanitize-tx19
514	*tx19:
515	// end-sanitize-tx19
516	{
517	do_or (SD_, TRZ, 0, (R32H << 3) \| R32L);
518	}
519
520
521	00110,3.RX,3.RY,3.SHAMT,00:ISHIFT:16::SLL
522	*mips16:
523	// start-sanitize-tx19
524	*tx19:
525	// end-sanitize-tx19
526	{
527	do_sll (SD_, TRY, TRX, SHIFT);
528	}
529
530
531	00110,3.RX,3.RY,3.SHAMT,10:ISHIFT:16::SRL
532	*mips16:
533	// start-sanitize-tx19
534	*tx19:
535	// end-sanitize-tx19
536	{
537	do_srl (SD_, TRY, TRX, SHIFT);
538	}
539
540
541	00110,3.RX,3.RY,3.SHAMT,11:ISHIFT:16::SRA
542	*mips16:
543	// start-sanitize-tx19
544	*tx19:
545	// end-sanitize-tx19
546	{
547	do_sra (SD_, TRY, TRX, SHIFT);
548	}
549
550
551	11101,3.RX,3.RY,00100:RR:16::SLLV
552	*mips16:
553	// start-sanitize-tx19
554	*tx19:
555	// end-sanitize-tx19
556	{
557	do_sllv (SD_, TRX, TRY, TRY);
558	}
559
560
561	11101,3.RX,3.RY,00110:RR:16::SRLV
562	*mips16:
563	// start-sanitize-tx19
564	*tx19:
565	// end-sanitize-tx19
566	{
567	do_srlv (SD_, TRX, TRY, TRY);
568	}
569
570
571	11101,3.RX,3.RY,00111:RR:16::SRAV
572	*mips16:
573	// start-sanitize-tx19
574	*tx19:
575	// end-sanitize-tx19
576	{
577	do_srav (SD_, TRX, TRY, TRY);
578	}
579
580
581	00110,3.RX,3.RY,3.SHAMT,01:ISHIFT:16,64::DSLL
582	*mips16:
583	// start-sanitize-tx19
584	*tx19:
585	// end-sanitize-tx19
586	{
587	do_dsll (SD_, 0, TRY, TRX, SHIFT);
16bd5d6e AC	588	}
	589
	590
c0a4c3ba	591	11101,3.SHAMT,3.RY,01000:RR:16,64::DSRL
16bd5d6e	592	*mips16:
c0a4c3ba AC	593	// start-sanitize-tx19
	594	*tx19:
	595	// end-sanitize-tx19
16bd5d6e	596	{
c0a4c3ba	597	do_dsrl (SD_, 0, TRY, TRY, SHIFT);
16bd5d6e AC	598	}
	599
	600
c0a4c3ba	601	11101,3.SHAMT,3.RY,10011:RR:16,64::DSRA
16bd5d6e	602	*mips16:
c0a4c3ba AC	603	// start-sanitize-tx19
	604	*tx19:
	605	// end-sanitize-tx19
16bd5d6e	606	{
c0a4c3ba AC	607	do_dsra (SD_, 0, TRY, TRY, SHIFT);
	608	}
	609
	610
	611	11101,3.RX,3.RY,10100:RR:16,64::DSLLV
	612	*mips16:
	613	// start-sanitize-tx19
	614	*tx19:
	615	// end-sanitize-tx19
	616	{
	617	do_dsllv (SD_, TRX, TRY, TRY);
	618	}
	619
	620
	621	11101,3.RX,3.RY,10110:RR:16,64::DSRLV
	622	*mips16:
	623	// start-sanitize-tx19
	624	*tx19:
	625	// end-sanitize-tx19
	626	{
	627	do_dsrlv (SD_, TRX, TRY, TRY);
	628	}
	629
	630
	631	11101,3.RX,3.RY,10111:RR:16,64::DSRAV
	632	*mips16:
	633	// start-sanitize-tx19
	634	*tx19:
	635	// end-sanitize-tx19
	636	{
	637	do_dsrav (SD_, TRX, TRY, TRY);
16bd5d6e AC	638	}
	639
	640
	641	// Multiply /Divide Instructions
	642
	643
c0a4c3ba	644	11101,3.RX,3.RY,11000:RR:16::MULT
16bd5d6e	645	*mips16:
c0a4c3ba AC	646	// start-sanitize-tx19
	647	*tx19:
	648	// end-sanitize-tx19
16bd5d6e	649	{
c0a4c3ba	650	do_mult (SD_, TRX, TRY, 0);
16bd5d6e AC	651	}
	652
	653
c0a4c3ba	654	11101,3.RX,3.RY,11001:RR:16::MULTU
16bd5d6e	655	*mips16:
c0a4c3ba AC	656	// start-sanitize-tx19
	657	*tx19:
	658	// end-sanitize-tx19
16bd5d6e	659	{
c0a4c3ba	660	do_multu (SD_, TRX, TRY, 0);
16bd5d6e AC	661	}
	662
	663
c0a4c3ba	664	11101,3.RX,3.RY,11010:RR:16::DIV
16bd5d6e	665	*mips16:
c0a4c3ba AC	666	// start-sanitize-tx19
	667	*tx19:
	668	// end-sanitize-tx19
16bd5d6e	669	{
c0a4c3ba	670	do_div (SD_, TRX, TRY);
16bd5d6e AC	671	}
	672
	673
c0a4c3ba	674	11101,3.RX,3.RY,11011:RR:16::DIVU
16bd5d6e	675	*mips16:
c0a4c3ba AC	676	// start-sanitize-tx19
	677	*tx19:
	678	// end-sanitize-tx19
16bd5d6e	679	{
c0a4c3ba	680	do_divu (SD_, TRX, TRY);
16bd5d6e AC	681	}
	682
	683
c0a4c3ba	684	11101,3.RX,000,10000:RR:16::MFHI
16bd5d6e	685	*mips16:
c0a4c3ba AC	686	// start-sanitize-tx19
	687	*tx19:
	688	// end-sanitize-tx19
16bd5d6e	689	{
c0a4c3ba	690	do_mfhi (SD_, TRX);
16bd5d6e AC	691	}
	692
	693
c0a4c3ba	694	11101,3.RX,000,10010:RR:16::MFLO
16bd5d6e	695	*mips16:
c0a4c3ba AC	696	// start-sanitize-tx19
	697	*tx19:
	698	// end-sanitize-tx19
16bd5d6e	699	{
c0a4c3ba	700	do_mflo (SD_, TRX);
16bd5d6e AC	701	}
	702
	703
c0a4c3ba	704	11101,3.RX,3.RY,11100:RR:16,64::DMULT
16bd5d6e	705	*mips16:
c0a4c3ba AC	706	// start-sanitize-tx19
	707	*tx19:
	708	// end-sanitize-tx19
16bd5d6e	709	{
c0a4c3ba	710	do_dmult (SD_, TRX, TRY);
16bd5d6e AC	711	}
	712
	713
c0a4c3ba	714	11101,3.RX,3.RY,11101:RR:16,64::DMULTU
16bd5d6e	715	*mips16:
c0a4c3ba AC	716	// start-sanitize-tx19
	717	*tx19:
	718	// end-sanitize-tx19
16bd5d6e	719	{
c0a4c3ba	720	do_dmultu (SD_, TRX, TRY);
16bd5d6e AC	721	}
	722
	723
c0a4c3ba	724	11101,3.RX,3.RY,11110:RR:16,64::DDIV
16bd5d6e	725	*mips16:
c0a4c3ba AC	726	// start-sanitize-tx19
	727	*tx19:
	728	// end-sanitize-tx19
16bd5d6e	729	{
c0a4c3ba	730	do_ddiv (SD_, TRX, TRY);
16bd5d6e AC	731	}
	732
	733
c0a4c3ba	734	11101,3.RX,3.RY,11111:RR:16,64::DDIVU
16bd5d6e	735	*mips16:
c0a4c3ba AC	736	// start-sanitize-tx19
	737	*tx19:
	738	// end-sanitize-tx19
16bd5d6e	739	{
c0a4c3ba	740	do_ddivu (SD_, TRX, TRY);
16bd5d6e AC	741	}
	742
	743
	744	// Jump and Branch Instructions
	745
	746
c0a4c3ba AC	747
	748	// Issue instruction in delay slot of branch
	749	:function:::address_word:delayslot16:address_word target
	750	{
	751	instruction_word delay_insn;
	752	sim_events_slip (SD, 1);
	753	DSPC = CIA; /* save current PC somewhere */
	754	CIA = CIA + 2; /* NOTE: mips16 */
	755	STATE \|= simDELAYSLOT;
	756	delay_insn = IMEM16 (CIA); /* NOTE: mips16 */
	757	idecode_issue (CPU_, delay_insn, (CIA));
	758	STATE &= ~simDELAYSLOT;
	759	return target;
	760	}
	761
	762	// compute basepc dependant on us being in a delay slot
	763	:function:::address_word:basepc:
	764	{
	765	if (STATE & simDELAYSLOT)
16bd5d6e	766	{
c0a4c3ba	767	return DSPC; /* return saved address of preceeding jmp */
16bd5d6e AC	768	}
	769	else
	770	{
c0a4c3ba	771	return CIA;
16bd5d6e	772	}
16bd5d6e AC	773	}
	774
	775
c0a4c3ba AC	776	// JAL
c0a4c3ba AC	777	00011,0,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:I:16::JAL
16bd5d6e	778	*mips16:
c0a4c3ba AC	779	// start-sanitize-tx19
	780	*tx19:
	781	// end-sanitize-tx19
16bd5d6e	782	{
c0a4c3ba AC	783	NIA = delayslot16 (SD_,
	784	(LSMASKED (NIA, 31, 26)
	785	\| LSINSERTED (IMM_25_21, 25, 21)
	786	\| LSINSERTED (IMM_20_16, 20, 16)
	787	\| LSINSERTED (IMMED_15_0, 15, 0)));
16bd5d6e AC	788	}
	789
	790
c0a4c3ba AC	791	// JALX
c0a4c3ba AC	792	00011,1,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:I:16::JALX
16bd5d6e	793	*mips16:
c0a4c3ba AC	794	// start-sanitize-tx19
	795	*tx19:
	796	// end-sanitize-tx19
16bd5d6e	797	{
c0a4c3ba AC	798	NIA = delayslot16 (SD_,
	799	(LSMASKED (NIA, 31, 26)
	800	\| LSINSERTED (IMM_25_21, 25, 21)
	801	\| LSINSERTED (IMM_20_16, 20, 16)
	802	\| LSINSERTED (IMMED_15_0, 15, 0)));
	803	NIA = NIA ^ 1;
16bd5d6e AC	804	}
	805
	806
c0a4c3ba	807	11101,3.RX,000,00000:RR:16::JR
16bd5d6e	808	*mips16:
c0a4c3ba AC	809	// start-sanitize-tx19
	810	*tx19:
	811	// end-sanitize-tx19
16bd5d6e	812	{
c0a4c3ba	813	NIA = delayslot16 (SD_, GPR[TRX]);
16bd5d6e AC	814	}
	815
	816
c0a4c3ba	817	11101,000,001,00000:RR:16::JRRA
16bd5d6e	818	*mips16:
c0a4c3ba AC	819	// start-sanitize-tx19
	820	*tx19:
	821	// end-sanitize-tx19
16bd5d6e	822	{
c0a4c3ba	823	NIA = delayslot16 (SD_, RA);
16bd5d6e AC	824	}
	825
	826
c0a4c3ba AC	827	11101,3.RX,010,00000:RR:16::JALR
	828	*mips16:
	829	// start-sanitize-tx19
	830	*tx19:
	831	// end-sanitize-tx19
	832	{
	833	RA = NIA + 2;
	834	NIA = delayslot16 (SD_, GPR[TRX]);
	835	}
16bd5d6e AC	836
16bd5d6e AC	837
c0a4c3ba AC	838	00100,3.RX,8.IMMED:RI:16::BEQZ
	839	*mips16:
	840	// start-sanitize-tx19
	841	*tx19:
	842	// end-sanitize-tx19
	843	{
	844	if (GPR[RX] == 0)
	845	NIA = (NIA + (EXTEND8 (IMMED) << 2));
	846	}
	847
	848
	849	00101,3.RX,8.IMMED:RI:16::BNEZ
	850	*mips16:
	851	// start-sanitize-tx19
	852	*tx19:
	853	// end-sanitize-tx19
	854	{
	855	if (GPR[RX] != 0)
	856	NIA = (NIA + (EXTEND8 (IMMED) << 2));
	857	}
	858
	859
	860	01100,000,8.IMMED:I8:16::BTEQZ
	861	*mips16:
	862	// start-sanitize-tx19
	863	*tx19:
	864	// end-sanitize-tx19
	865	{
	866	if (T8 == 0)
	867	NIA = (NIA + (EXTEND8 (IMMED) << 2));
	868	}
	869
	870
	871	01100,001,8.IMMED:I8:16::BTNEZ
16bd5d6e	872	*mips16:
c0a4c3ba AC	873	// start-sanitize-tx19
	874	*tx19:
	875	// end-sanitize-tx19
16bd5d6e	876	{
c0a4c3ba AC	877	if (T8 != 0)
c0a4c3ba AC	878	NIA = (NIA + (EXTEND8 (IMMED) << 2));
16bd5d6e AC	879	}
	880
	881
c0a4c3ba	882	00010,11.IMMED:I:16::B
16bd5d6e	883	*mips16:
c0a4c3ba AC	884	// start-sanitize-tx19
	885	*tx19:
	886	// end-sanitize-tx19
16bd5d6e	887	{
c0a4c3ba	888	NIA = (NIA + (EXTEND8 (IMMED) << 2));
16bd5d6e AC	889	}
16bd5d6e AC	890
c0a4c3ba AC	891
	892	// Special Instructions
	893
	894
	895	// See the front of the mips16 doc
	896	// -> FIXME need this for most instructions
	897	// 11110,eeeeeeeeeee:I:16::EXTEND
	898	// *mips16:
	899	// // start-sanitize-tx19
	900	// *tx19:
	901	// // end-sanitize-tx19
	902
	903
	904	// 11101,3.RX,3.RY,00101:RR:16::BREAK
	905	// *mips16:
	906	// // start-sanitize-tx19
	907	// *tx19:
	908	// // end-sanitize-tx19