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1 | // -*- C -*- |
2 | ||
3 | // Simulator definition for the MIPS MDMX ASE. | |
4 | // Copyright (C) 2002 Free Software Foundation, Inc. | |
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5 | // Contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom |
6 | // Corporation (SiByte). | |
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7 | // |
8 | // This file is part of GDB, the GNU debugger. | |
9 | // | |
10 | // This program is free software; you can redistribute it and/or modify | |
11 | // it under the terms of the GNU General Public License as published by | |
12 | // the Free Software Foundation; either version 2, or (at your option) | |
13 | // any later version. | |
14 | // | |
15 | // This program is distributed in the hope that it will be useful, | |
16 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | // GNU General Public License for more details. | |
19 | // | |
20 | // You should have received a copy of the GNU General Public License along | |
21 | // with this program; if not, write to the Free Software Foundation, Inc., | |
22 | // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
23 | ||
24 | // Reference: MIPS64 Architecture Volume IV-b: | |
25 | // The MDMX Application-Specific Extension | |
26 | ||
27 | // Notes on "format selectors" (FMTSEL): | |
28 | // | |
29 | // A selector with final bit 0 indicates OB format. | |
30 | // A selector with final bits 01 indicates QH format. | |
31 | // A selector with final bits 11 has UNPREDICTABLE result per the spec. | |
32 | // | |
33 | // Similarly, for the single-bit fields which differentiate between | |
34 | // formats (FMTOP), 0 is OB format and 1 is QH format. | |
35 | ||
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36 | // If you change this file to add instructions, please make sure that model |
37 | // "sb1" configurations still build, and that you've added no new | |
38 | // instructions to the "sb1" model. | |
39 | ||
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40 | |
41 | // Helper: | |
42 | // | |
43 | // Check whether MDMX is usable, and if not signal an appropriate exception. | |
44 | // | |
45 | ||
46 | :function:::void:check_mdmx:instruction_word insn | |
47 | *mdmx: | |
48 | { | |
49 | if (! COP_Usable (1)) | |
50 | SignalExceptionCoProcessorUnusable (1); | |
51 | if ((SR & (status_MX|status_FR)) != (status_MX|status_FR)) | |
52 | SignalExceptionMDMX (); | |
53 | check_u64 (SD_, insn); | |
54 | } | |
55 | ||
56 | ||
57 | // Helper: | |
58 | // | |
59 | // Check whether a given MDMX format selector indicates a valid and usable | |
60 | // format, and if not signal an appropriate exception. | |
61 | // | |
62 | ||
63 | :function:::int:check_mdmx_fmtsel:instruction_word insn, int fmtsel | |
64 | *mdmx: | |
65 | { | |
66 | switch (fmtsel & 0x03) | |
67 | { | |
68 | case 0x00: /* ob */ | |
69 | case 0x02: | |
70 | case 0x01: /* qh */ | |
71 | return 1; | |
72 | case 0x03: /* UNPREDICTABLE */ | |
73 | SignalException (ReservedInstruction, insn); | |
74 | return 0; | |
75 | } | |
76 | return 0; | |
77 | } | |
78 | ||
79 | ||
80 | // Helper: | |
81 | // | |
82 | // Check whether a given MDMX format bit indicates a valid and usable | |
83 | // format, and if not signal an appropriate exception. | |
84 | // | |
85 | ||
86 | :function:::int:check_mdmx_fmtop:instruction_word insn, int fmtop | |
87 | *mdmx: | |
88 | { | |
89 | switch (fmtop & 0x01) | |
90 | { | |
91 | case 0x00: /* ob */ | |
92 | case 0x01: /* qh */ | |
93 | return 1; | |
94 | } | |
95 | return 0; | |
96 | } | |
97 | ||
98 | ||
99 | :%s::::FMTSEL:int fmtsel | |
100 | *mdmx: | |
7cbea089 | 101 | *sb1: |
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102 | { |
103 | if ((fmtsel & 0x1) == 0) | |
104 | return "ob"; | |
105 | else if ((fmtsel & 0x3) == 1) | |
106 | return "qh"; | |
107 | else | |
108 | return "?"; | |
109 | } | |
110 | ||
111 | ||
112 | :%s::::FMTOP:int fmtop | |
113 | *mdmx: | |
7cbea089 | 114 | *sb1: |
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115 | { |
116 | switch (fmtop) | |
117 | { | |
118 | case 0: return "ob"; | |
119 | case 1: return "qh"; | |
120 | default: return "?"; | |
121 | } | |
122 | } | |
123 | ||
124 | ||
125 | :%s::::SHOP:int shop | |
126 | *mdmx: | |
7cbea089 | 127 | *sb1: |
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128 | { |
129 | if ((shop & 0x11) == 0x00) | |
130 | switch ((shop >> 1) & 0x07) | |
131 | { | |
132 | case 3: return "upsl.ob"; | |
133 | case 4: return "pach.ob"; | |
134 | case 6: return "mixh.ob"; | |
135 | case 7: return "mixl.ob"; | |
136 | default: return "?"; | |
137 | } | |
138 | else if ((shop & 0x03) == 0x01) | |
139 | switch ((shop >> 2) & 0x07) | |
140 | { | |
141 | case 0: return "mixh.qh"; | |
142 | case 1: return "mixl.qh"; | |
143 | case 2: return "pach.qh"; | |
144 | case 4: return "bfla.qh"; | |
145 | case 6: return "repa.qh"; | |
146 | case 7: return "repb.qh"; | |
147 | default: return "?"; | |
148 | } | |
149 | else | |
150 | return "?"; | |
151 | } | |
152 | ||
153 | ||
154 | 011110,5.FMTSEL,5.VT,5.VS,5.VD,001011:MDMX:64::ADD.fmt | |
155 | "add.%s<FMTSEL> v<VD>, v<VS>, v<VT>" | |
156 | *mdmx: | |
7cbea089 | 157 | *sb1: |
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158 | { |
159 | check_mdmx (SD_, instruction_0); | |
160 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
161 | StoreFPR(VD,fmt_mdmx,MX_Add(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); | |
162 | } | |
163 | ||
164 | ||
165 | 011110,5.FMTSEL,5.VT,5.VS,0,0000,110111:MDMX:64::ADDA.fmt | |
166 | "adda.%s<FMTSEL> v<VS>, v<VT>" | |
167 | *mdmx: | |
7cbea089 | 168 | *sb1: |
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169 | { |
170 | check_mdmx (SD_, instruction_0); | |
171 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
172 | MX_AddA(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); | |
173 | } | |
174 | ||
175 | ||
176 | 011110,5.FMTSEL,5.VT,5.VS,1,0000,110111:MDMX:64::ADDL.fmt | |
177 | "addl.%s<FMTSEL> v<VS>, v<VT>" | |
178 | *mdmx: | |
7cbea089 | 179 | *sb1: |
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180 | { |
181 | check_mdmx (SD_, instruction_0); | |
182 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
183 | MX_AddL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); | |
184 | } | |
185 | ||
186 | ||
187 | 011110,00,3.IMM,5.VT,5.VS,5.VD,0110,1.FMTOP,0:MDMX:64::ALNI.fmt | |
188 | "alni.%s<FMTOP> v<VD>, v<VS>, v<VT>, <IMM>" | |
189 | *mdmx: | |
7cbea089 | 190 | *sb1: |
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191 | { |
192 | unsigned64 result; | |
193 | int s; | |
194 | check_mdmx (SD_, instruction_0); | |
195 | check_mdmx_fmtop (SD_, instruction_0, FMTOP); | |
196 | s = (IMM << 3); | |
197 | result = ValueFPR(VS,fmt_mdmx) << s; | |
198 | if (s != 0) // x86 gcc treats >> 64 as >> 0 | |
199 | result |= ValueFPR(VT,fmt_mdmx) >> (64 - s); | |
200 | StoreFPR(VD,fmt_mdmx,result); | |
201 | } | |
202 | ||
203 | ||
204 | 011110,5.RS,5.VT,5.VS,5.VD,0110,1.FMTOP,1:MDMX:64::ALNV.fmt | |
205 | "alnv.%s<FMTOP> v<VD>, v<VS>, v<VT>, r<RS>" | |
206 | *mdmx: | |
7cbea089 | 207 | *sb1: |
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208 | { |
209 | unsigned64 result; | |
210 | int s; | |
211 | check_mdmx (SD_, instruction_0); | |
212 | check_mdmx_fmtop (SD_, instruction_0, FMTOP); | |
213 | s = ((GPR[RS] & 0x7) << 3); | |
214 | result = ValueFPR(VS,fmt_mdmx) << s; | |
215 | if (s != 0) // x86 gcc treats >> 64 as >> 0 | |
216 | result |= ValueFPR(VT,fmt_mdmx) >> (64 - s); | |
217 | StoreFPR(VD,fmt_mdmx,result); | |
218 | } | |
219 | ||
220 | ||
221 | 011110,5.FMTSEL,5.VT,5.VS,5.VD,001100:MDMX:64::AND.fmt | |
222 | "and.%s<FMTSEL> v<VD>, v<VS>, v<VT>" | |
223 | *mdmx: | |
7cbea089 | 224 | *sb1: |
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225 | { |
226 | check_mdmx (SD_, instruction_0); | |
227 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
228 | StoreFPR(VD,fmt_mdmx,MX_And(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); | |
229 | } | |
230 | ||
231 | ||
232 | 011110,5.FMTSEL,5.VT,5.VS,00000,000001:MDMX:64::C.EQ.fmt | |
233 | "c.eq.%s<FMTSEL> v<VS>, v<VT>" | |
234 | *mdmx: | |
7cbea089 | 235 | *sb1: |
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236 | { |
237 | check_mdmx (SD_, instruction_0); | |
238 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
239 | MX_Comp(ValueFPR(VS,fmt_mdmx),MX_C_EQ,VT,FMTSEL); | |
240 | } | |
241 | ||
242 | ||
243 | 011110,5.FMTSEL,5.VT,5.VS,00000,000101:MDMX:64::C.LE.fmt | |
244 | "c.le.%s<FMTSEL> v<VS>, v<VT>" | |
245 | *mdmx: | |
7cbea089 | 246 | *sb1: |
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247 | { |
248 | check_mdmx (SD_, instruction_0); | |
249 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
250 | MX_Comp(ValueFPR(VS,fmt_mdmx),MX_C_LT|MX_C_EQ,VT,FMTSEL); | |
251 | } | |
252 | ||
253 | ||
254 | 011110,5.FMTSEL,5.VT,5.VS,00000,000100:MDMX:64::C.LT.fmt | |
255 | "c.lt.%s<FMTSEL> v<VS>, v<VT>" | |
256 | *mdmx: | |
7cbea089 | 257 | *sb1: |
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258 | { |
259 | check_mdmx (SD_, instruction_0); | |
260 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
261 | MX_Comp(ValueFPR(VS,fmt_mdmx),MX_C_LT,VT,FMTSEL); | |
262 | } | |
263 | ||
264 | ||
265 | 011110,5.FMTSEL,5.VT,5.VS,5.VD,000111:MDMX:64::MAX.fmt | |
266 | "max.%s<FMTSEL> v<VD>, v<VS>, v<VT>" | |
267 | *mdmx: | |
7cbea089 | 268 | *sb1: |
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269 | { |
270 | check_mdmx (SD_, instruction_0); | |
271 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
272 | StoreFPR(VD,fmt_mdmx,MX_Max(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); | |
273 | } | |
274 | ||
275 | ||
276 | 011110,5.FMTSEL,5.VT,5.VS,5.VD,000110:MDMX:64::MIN.fmt | |
277 | "min.%s<FMTSEL> v<VD>, v<VS>, v<VT>" | |
278 | *mdmx: | |
7cbea089 | 279 | *sb1: |
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280 | { |
281 | check_mdmx (SD_, instruction_0); | |
282 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
283 | StoreFPR(VD,fmt_mdmx,MX_Min(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); | |
284 | } | |
285 | ||
286 | ||
287 | 011110,3.SEL,01,5.VT,5.VS,5.VD,000000:MDMX:64::MSGN.QH | |
288 | "msgn.qh v<VD>, v<VS>, v<VT>" | |
289 | *mdmx: | |
290 | { | |
291 | check_mdmx (SD_, instruction_0); | |
292 | StoreFPR(VD,fmt_mdmx,MX_Msgn(ValueFPR(VS,fmt_mdmx),VT,qh_fmtsel(SEL))); | |
293 | } | |
294 | ||
295 | ||
296 | 011110,5.FMTSEL,5.VT,5.VS,5.VD,110000:MDMX:64::MUL.fmt | |
297 | "mul.%s<FMTSEL> v<VD>, v<VS>, v<VT>" | |
298 | *mdmx: | |
7cbea089 | 299 | *sb1: |
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300 | { |
301 | check_mdmx (SD_, instruction_0); | |
302 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
303 | StoreFPR(VD,fmt_mdmx,MX_Mul(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); | |
304 | } | |
305 | ||
306 | ||
307 | 011110,5.FMTSEL,5.VT,5.VS,0,0000,110011:MDMX:64::MULA.fmt | |
308 | "mula.%s<FMTSEL> v<VS>, v<VT>" | |
309 | *mdmx: | |
7cbea089 | 310 | *sb1: |
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311 | { |
312 | check_mdmx (SD_, instruction_0); | |
313 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
314 | MX_MulA(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); | |
315 | } | |
316 | ||
317 | ||
318 | 011110,5.FMTSEL,5.VT,5.VS,1,0000,110011:MDMX:64::MULL.fmt | |
319 | "mull.%s<FMTSEL> v<VS>, v<VT>" | |
320 | *mdmx: | |
7cbea089 | 321 | *sb1: |
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322 | { |
323 | check_mdmx (SD_, instruction_0); | |
324 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
325 | MX_MulL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); | |
326 | } | |
327 | ||
328 | ||
329 | 011110,5.FMTSEL,5.VT,5.VS,0,0000,110010:MDMX:64::MULS.fmt | |
330 | "muls.%s<FMTSEL> v<VS>, v<VT>" | |
331 | *mdmx: | |
7cbea089 | 332 | *sb1: |
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333 | { |
334 | check_mdmx (SD_, instruction_0); | |
335 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
336 | MX_MulS(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); | |
337 | } | |
338 | ||
339 | ||
340 | 011110,5.FMTSEL,5.VT,5.VS,1,0000,110010:MDMX:64::MULSL.fmt | |
341 | "mulsl.%s<FMTSEL> v<VS>, v<VT>" | |
342 | *mdmx: | |
7cbea089 | 343 | *sb1: |
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344 | { |
345 | check_mdmx (SD_, instruction_0); | |
346 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
347 | MX_MulSL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); | |
348 | } | |
349 | ||
350 | ||
351 | 011110,5.FMTSEL,5.VT,5.VS,5.VD,001111:MDMX:64::NOR.fmt | |
352 | "nor.%s<FMTSEL> v<VD>, v<VS>, v<VT>" | |
353 | *mdmx: | |
7cbea089 | 354 | *sb1: |
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355 | { |
356 | check_mdmx (SD_, instruction_0); | |
357 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
358 | StoreFPR(VD,fmt_mdmx,MX_Nor(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); | |
359 | } | |
360 | ||
361 | ||
362 | 011110,5.FMTSEL,5.VT,5.VS,5.VD,001110:MDMX:64::OR.fmt | |
363 | "or.%s<FMTSEL> v<VD>, v<VS>, v<VT>" | |
364 | *mdmx: | |
7cbea089 | 365 | *sb1: |
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366 | { |
367 | check_mdmx (SD_, instruction_0); | |
368 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
369 | StoreFPR(VD,fmt_mdmx,MX_Or(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); | |
370 | } | |
371 | ||
372 | ||
373 | 011110,5.FMTSEL,5.VT,5.VS,5.VD,000010:MDMX:64::PICKF.fmt | |
374 | "pickf.%s<FMTSEL> v<VD>, v<VS>, v<VT>" | |
375 | *mdmx: | |
7cbea089 | 376 | *sb1: |
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377 | { |
378 | check_mdmx (SD_, instruction_0); | |
379 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
380 | StoreFPR(VD,fmt_mdmx,MX_Pick(0,ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); | |
381 | } | |
382 | ||
383 | ||
384 | 011110,5.FMTSEL,5.VT,5.VS,5.VD,000011:MDMX:64::PICKT.fmt | |
385 | "pickt.%s<FMTSEL> v<VD>, v<VS>, v<VT>" | |
386 | *mdmx: | |
7cbea089 | 387 | *sb1: |
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388 | { |
389 | check_mdmx (SD_, instruction_0); | |
390 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
391 | StoreFPR(VD,fmt_mdmx,MX_Pick(1,ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); | |
392 | } | |
393 | ||
394 | ||
395 | 011110,1000,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACH.fmt | |
396 | "rach.%s<FMTOP> v<VD>" | |
397 | *mdmx: | |
7cbea089 | 398 | *sb1: |
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399 | { |
400 | check_mdmx (SD_, instruction_0); | |
401 | check_mdmx_fmtop (SD_, instruction_0, FMTOP); | |
402 | StoreFPR(VD,fmt_mdmx,MX_RAC(MX_RAC_H,FMTOP)); | |
403 | } | |
404 | ||
405 | ||
406 | 011110,0000,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACL.fmt | |
407 | "racl.%s<FMTOP> v<VD>" | |
408 | *mdmx: | |
7cbea089 | 409 | *sb1: |
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410 | { |
411 | check_mdmx (SD_, instruction_0); | |
412 | check_mdmx_fmtop (SD_, instruction_0, FMTOP); | |
413 | StoreFPR(VD,fmt_mdmx,MX_RAC(MX_RAC_L,FMTOP)); | |
414 | } | |
415 | ||
416 | ||
417 | 011110,0100,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACM.fmt | |
418 | "racm.%s<FMTOP> v<VD>" | |
419 | *mdmx: | |
7cbea089 | 420 | *sb1: |
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421 | { |
422 | check_mdmx (SD_, instruction_0); | |
423 | check_mdmx_fmtop (SD_, instruction_0, FMTOP); | |
424 | StoreFPR(VD,fmt_mdmx,MX_RAC(MX_RAC_M,FMTOP)); | |
425 | } | |
426 | ||
427 | ||
428 | 011110,3.SEL,01,5.VT,00000,5.VD,100101:MDMX:64::RNAS.QH | |
429 | "rnas.qh v<VD>, v<VT>" | |
430 | *mdmx: | |
431 | { | |
432 | check_mdmx (SD_, instruction_0); | |
433 | StoreFPR(VD,fmt_mdmx,MX_RNAS(VT,qh_fmtsel(SEL))); | |
434 | } | |
435 | ||
436 | ||
437 | 011110,5.FMTSEL,5.VT,00000,5.VD,100001:MDMX:64::RNAU.fmt | |
438 | "rnau.%s<FMTSEL> v<VD>, v<VT>" | |
439 | *mdmx: | |
7cbea089 | 440 | *sb1: |
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441 | { |
442 | check_mdmx (SD_, instruction_0); | |
443 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
444 | StoreFPR(VD,fmt_mdmx,MX_RNAU(VT,FMTSEL)); | |
445 | } | |
446 | ||
447 | ||
448 | 011110,3.SEL,01,5.VT,00000,5.VD,100110:MDMX:64::RNES.QH | |
449 | "rnes.qh v<VD>, v<VT>" | |
450 | *mdmx: | |
451 | { | |
452 | check_mdmx (SD_, instruction_0); | |
453 | StoreFPR(VD,fmt_mdmx,MX_RNES(VT,qh_fmtsel(SEL))); | |
454 | } | |
455 | ||
456 | ||
457 | 011110,5.FMTSEL,5.VT,00000,5.VD,100010:MDMX:64::RNEU.fmt | |
458 | "rneu.%s<FMTSEL> v<VD>, v<VT>" | |
459 | *mdmx: | |
7cbea089 | 460 | *sb1: |
f4f1b9f1 CD |
461 | { |
462 | check_mdmx (SD_, instruction_0); | |
463 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
464 | StoreFPR(VD,fmt_mdmx,MX_RNEU(VT,FMTSEL)); | |
465 | } | |
466 | ||
467 | ||
468 | 011110,3.SEL,01,5.VT,00000,5.VD,100100:MDMX:64::RZS.QH | |
469 | "rzs.qh v<VD>, v<VT>" | |
470 | *mdmx: | |
471 | { | |
472 | check_mdmx (SD_, instruction_0); | |
473 | StoreFPR(VD,fmt_mdmx,MX_RZS(VT,qh_fmtsel(SEL))); | |
474 | } | |
475 | ||
476 | ||
477 | 011110,5.FMTSEL,5.VT,00000,5.VD,100000:MDMX:64::RZU.fmt | |
478 | "rzu.%s<FMTSEL> v<VD>, v<VT>" | |
479 | *mdmx: | |
7cbea089 | 480 | *sb1: |
f4f1b9f1 CD |
481 | { |
482 | check_mdmx (SD_, instruction_0); | |
483 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
484 | StoreFPR(VD,fmt_mdmx,MX_RZU(VT,FMTSEL)); | |
485 | } | |
486 | ||
487 | ||
488 | 011110,5.SHOP,5.VT,5.VS,5.VD,011111:MDMX:64::SHFL.op.fmt | |
489 | "shfl.%s<SHOP> v<VD>, v<VS>, v<VT>" | |
490 | *mdmx: | |
7cbea089 | 491 | *sb1: |
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492 | { |
493 | check_mdmx (SD_, instruction_0); | |
494 | if (check_mdmx_fmtsel (SD_, instruction_0, SHOP)) | |
495 | StoreFPR(VD,fmt_mdmx,MX_SHFL(SHOP,ValueFPR(VS,fmt_mdmx),ValueFPR(VT,fmt_mdmx))); | |
496 | } | |
497 | ||
498 | ||
499 | 011110,5.FMTSEL,5.VT,5.VS,5.VD,010000:MDMX:64::SLL.fmt | |
500 | "sll.%s<FMTSEL> v<VD>, v<VS>, v<VT>" | |
501 | *mdmx: | |
7cbea089 | 502 | *sb1: |
f4f1b9f1 CD |
503 | { |
504 | check_mdmx (SD_, instruction_0); | |
505 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
506 | StoreFPR(VD,fmt_mdmx,MX_ShiftLeftLogical(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); | |
507 | } | |
508 | ||
509 | ||
510 | 011110,3.SEL,01,5.VT,5.VS,5.VD,010011:MDMX:64::SRA.QH | |
511 | "sra.qh v<VD>, v<VS>, v<VT>" | |
512 | *mdmx: | |
513 | { | |
514 | check_mdmx (SD_, instruction_0); | |
515 | StoreFPR(VD,fmt_mdmx,MX_ShiftRightArith(ValueFPR(VS,fmt_mdmx),VT,qh_fmtsel(SEL))); | |
516 | } | |
517 | ||
518 | ||
519 | 011110,5.FMTSEL,5.VT,5.VS,5.VD,010010:MDMX:64::SRL.fmt | |
520 | "srl.%s<FMTSEL> v<VD>, v<VS>, v<VT>" | |
521 | *mdmx: | |
7cbea089 | 522 | *sb1: |
f4f1b9f1 CD |
523 | { |
524 | check_mdmx (SD_, instruction_0); | |
525 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
526 | StoreFPR(VD,fmt_mdmx,MX_ShiftRightLogical(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); | |
527 | } | |
528 | ||
529 | ||
530 | 011110,5.FMTSEL,5.VT,5.VS,5.VD,001010:MDMX:64::SUB.fmt | |
531 | "sub.%s<FMTSEL> v<VD>, v<VS>, v<VT>" | |
532 | *mdmx: | |
7cbea089 | 533 | *sb1: |
f4f1b9f1 CD |
534 | { |
535 | check_mdmx (SD_, instruction_0); | |
536 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
537 | StoreFPR(VD,fmt_mdmx,MX_Sub(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); | |
538 | } | |
539 | ||
540 | ||
541 | 011110,5.FMTSEL,5.VT,5.VS,0,0000,110110:MDMX:64::SUBA.fmt | |
542 | "suba.%s<FMTSEL> v<VS>, v<VT>" | |
543 | *mdmx: | |
7cbea089 | 544 | *sb1: |
f4f1b9f1 CD |
545 | { |
546 | check_mdmx (SD_, instruction_0); | |
547 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
548 | MX_SubA(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); | |
549 | } | |
550 | ||
551 | ||
552 | 011110,5.FMTSEL,5.VT,5.VS,1,0000,110110:MDMX:64::SUBL.fmt | |
553 | "subl.%s<FMTSEL> v<VS>, v<VT>" | |
554 | *mdmx: | |
7cbea089 | 555 | *sb1: |
f4f1b9f1 CD |
556 | { |
557 | check_mdmx (SD_, instruction_0); | |
558 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
559 | MX_SubL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); | |
560 | } | |
561 | ||
562 | ||
563 | 011110,1000,1.FMTOP,00000,5.VS,00000,111110:MDMX:64::WACH.fmt | |
564 | "wach.%s<FMTOP> v<VS>" | |
565 | *mdmx: | |
7cbea089 | 566 | *sb1: |
f4f1b9f1 CD |
567 | { |
568 | check_mdmx (SD_, instruction_0); | |
569 | check_mdmx_fmtop (SD_, instruction_0, FMTOP); | |
570 | MX_WACH(FMTOP,ValueFPR(VS,fmt_mdmx)); | |
571 | } | |
572 | ||
573 | ||
574 | 011110,0000,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WACL.fmt | |
575 | "wacl.%s<FMTOP> v<VS>, v<VT>" | |
576 | *mdmx: | |
7cbea089 | 577 | *sb1: |
f4f1b9f1 CD |
578 | { |
579 | check_mdmx (SD_, instruction_0); | |
580 | check_mdmx_fmtop (SD_, instruction_0, FMTOP); | |
581 | MX_WACL(FMTOP,ValueFPR(VS,fmt_mdmx),ValueFPR(VT,fmt_mdmx)); | |
582 | } | |
583 | ||
584 | ||
585 | 011110,5.FMTSEL,5.VT,5.VS,5.VD,001101:MDMX:64::XOR.fmt | |
586 | "xor.%s<FMTSEL> v<VD>, v<VS>, v<VT>" | |
587 | *mdmx: | |
7cbea089 | 588 | *sb1: |
f4f1b9f1 CD |
589 | { |
590 | check_mdmx (SD_, instruction_0); | |
591 | if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) | |
592 | StoreFPR(VD,fmt_mdmx,MX_Xor(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); | |
593 | } |