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Delete -l and -n options, didn't do anything.
[deliverable/binutils-gdb.git] / sim / mips / mips.igen
CommitLineData
f2b30012
AC		 1// <insn> ::=
2// <insn-word> { "+" <insn-word> }
3// ":" <format-name>
4// ":" <filter-flags>
5// ":" <options>
6// ":" <name>
7// <nl>
8// { <insn-model> }
9// { <insn-mnemonic> }
10// <code-block>
11//
12
13
14// IGEN config - mips16
89d09738
AC		 15:option:16::insn-bit-size:16
16:option:16::hi-bit-nr:15
17:option:16::insn-specifying-widths:true
18:option:16::gen-delayed-branch:false
f2b30012 19
90ad43b2 20// IGEN config - mips32/64..
89d09738
AC		 21:option:32::insn-bit-size:32
22:option:32::hi-bit-nr:31
23:option:32::insn-specifying-widths:true
24:option:32::gen-delayed-branch:false
f2b30012
AC		 25
26
49a6eed5 27// Generate separate simulators for each target
89d09738 28// :option:::multi-sim:true
49a6eed5 29
f2b30012
AC		 30
31// Models known by this simulator
89d09738
AC		 32:model:::mipsI:mipsI:
33:model:::mipsII:mipsII:
34:model:::mipsIII:mipsIII:
35:model:::mipsIV:mipsIV:
36:model:::mips16:mips16:
f2b30012 37// start-sanitize-r5900
89d09738 38:model:::r5900:r5900:
f2b30012 39// end-sanitize-r5900
89d09738 40:model:::r3900:r3900:
f2b30012 41// start-sanitize-tx19
89d09738 42:model:::tx19:tx19:
f2b30012 43// end-sanitize-tx19
90ad43b2 44// start-sanitize-vr5400
89d09738 45:model:::vr5400:vr5400:
90ad43b2 46// end-sanitize-vr5400
f2b30012
AC		 47
48
49
50// Pseudo instructions known by IGEN
89d09738 51:internal::::illegal:
f2b30012
AC		 52{
53 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
055ee297 54 (unsigned long) CIA);
f2b30012
AC		 55 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
56}
57
58
59
60
61//
62// MIPS Architecture:
63//
64// CPU Instruction Set (mipsI - mipsIV)
65//
66
67
68000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
69"add r<RD>, r<RS>, r<RT>"
70*mipsI:
71*mipsII:
72*mipsIII:
73*mipsIV:
90ad43b2
AC		 74// start-sanitize-vr5400
75*vr5400:
76// end-sanitize-vr5400
f2b30012
AC		 77// start-sanitize-r5900
78*r5900:
79// end-sanitize-r5900
80*r3900:
81// start-sanitize-tx19
82*tx19:
83// end-sanitize-tx19
84{
055ee297
AC		 85 ALU32_BEGIN (GPR[RS]);
86 ALU32_ADD (GPR[RT]);
87 ALU32_END (GPR[RD]);
f2b30012
AC		 88}
89
90
91001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
92"addi r<RT>, r<RS>, IMMEDIATE"
93*mipsI:
94*mipsII:
95*mipsIII:
96*mipsIV:
90ad43b2
AC		 97// start-sanitize-vr5400
98*vr5400:
99// end-sanitize-vr5400
f2b30012
AC		 100// start-sanitize-r5900
101*r5900:
102// end-sanitize-r5900
103*r3900:
104// start-sanitize-tx19
105*tx19:
106// end-sanitize-tx19
107{
055ee297 108 ALU32_BEGIN (GPR[RS]);
f2b30012 109 ALU32_ADD (EXTEND16 (IMMEDIATE));
055ee297 110 ALU32_END (GPR[RT]);
f2b30012
AC		 111}
112
113
114001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
115"add r<RT>, r<RS>, IMMEDIATE"
116*mipsI:
117*mipsII:
118*mipsIII:
119*mipsIV:
90ad43b2
AC		 120// start-sanitize-vr5400
121*vr5400:
122// end-sanitize-vr5400
f2b30012
AC		 123// start-sanitize-r5900
124*r5900:
125// end-sanitize-r5900
126*r3900:
127// start-sanitize-tx19
128*tx19:
129// end-sanitize-tx19
130{
055ee297
AC		 131 signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
132 GPR[RT] = EXTEND32 (temp);
f2b30012
AC		 133}
134
135
136000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
137*mipsI:
138*mipsII:
139*mipsIII:
140*mipsIV:
90ad43b2
AC		 141// start-sanitize-vr5400
142*vr5400:
143// end-sanitize-vr5400
f2b30012
AC		 144// start-sanitize-r5900
145*r5900:
146// end-sanitize-r5900
147*r3900:
148// start-sanitize-tx19
149*tx19:
150// end-sanitize-tx19
151{
055ee297
AC		 152 signed32 temp = GPR[RS] + GPR[RT];
153 GPR[RD] = EXTEND32 (temp);
f2b30012
AC		 154}
155
156
157000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
158"and r<RD>, r<RS>, r<RT>"
159*mipsI:
160*mipsII:
161*mipsIII:
162*mipsIV:
90ad43b2
AC		 163// start-sanitize-vr5400
164*vr5400:
165// end-sanitize-vr5400
f2b30012
AC		 166// start-sanitize-r5900
167*r5900:
168// end-sanitize-r5900
169*r3900:
170// start-sanitize-tx19
171*tx19:
172// end-sanitize-tx19
173{
055ee297 174 GPR[RD] = GPR[RS] & GPR[RT];
f2b30012
AC		 175}
176
177
178001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
179"and r<RT>, r<RS>, IMMEDIATE"
180*mipsI:
181*mipsII:
182*mipsIII:
90ad43b2
AC		 183// start-sanitize-vr5400
184*vr5400:
185// end-sanitize-vr5400
f2b30012
AC		 186// start-sanitize-r5900
187*r5900:
188// end-sanitize-r5900
189*r3900:
190// start-sanitize-tx19
191*tx19:
192// end-sanitize-tx19
193{
055ee297 194 GPR[RT] = GPR[RS] & IMMEDIATE;
f2b30012
AC		 195}
196
197
198000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
199"beq r<RS>, r<RT>, OFFSET"
200*mipsI:
201*mipsII:
202*mipsIII:
203*mipsIV:
90ad43b2
AC		 204// start-sanitize-vr5400
205*vr5400:
206// end-sanitize-vr5400
f2b30012
AC		 207// start-sanitize-r5900
208*r5900:
209// end-sanitize-r5900
210*r3900:
211// start-sanitize-tx19
212*tx19:
213// end-sanitize-tx19
214{
055ee297
AC		 215 address_word offset = EXTEND16 (OFFSET) << 2;
216 if (GPR[RS] == GPR[RT])
49a76833 217 DELAY_SLOT (PC + offset);
f2b30012
AC		 218}
219
220
221010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
222"beql r<RS>, r<RT>, <OFFSET>"
223*mipsII:
224*mipsIII:
225*mipsIV:
90ad43b2
AC		 226// start-sanitize-vr5400
227*vr5400:
228// end-sanitize-vr5400
f2b30012
AC		 229// start-sanitize-r5900
230*r5900:
231// end-sanitize-r5900
232*r3900:
233// start-sanitize-tx19
234*tx19:
235// end-sanitize-tx19
236{
055ee297
AC		 237 address_word offset = EXTEND16 (OFFSET) << 2;
238 if (GPR[RS] == GPR[RT])
49a76833 239 DELAY_SLOT (PC + offset);
055ee297 240 else
49a76833 241 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 242}
243
244
245000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
246"bgez r<RS>, <OFFSET>"
247*mipsI:
248*mipsII:
249*mipsIII:
250*mipsIV:
90ad43b2
AC		 251// start-sanitize-vr5400
252*vr5400:
253// end-sanitize-vr5400
f2b30012
AC		 254// start-sanitize-r5900
255*r5900:
256// end-sanitize-r5900
257*r3900:
258// start-sanitize-tx19
259*tx19:
260// end-sanitize-tx19
261{
055ee297
AC		 262 address_word offset = EXTEND16 (OFFSET) << 2;
263 if (GPR[RS] >= 0)
49a76833 264 DELAY_SLOT (PC + offset);
f2b30012
AC		 265}
266
267
268000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
269"bgezal r<RS>, <OFFSET>"
270*mipsI:
271*mipsII:
272*mipsIII:
273*mipsIV:
90ad43b2
AC		 274// start-sanitize-vr5400
275*vr5400:
276// end-sanitize-vr5400
f2b30012
AC		 277// start-sanitize-r5900
278*r5900:
279// end-sanitize-r5900
280*r3900:
281// start-sanitize-tx19
282*tx19:
283// end-sanitize-tx19
284{
055ee297
AC		 285 address_word offset = EXTEND16 (OFFSET) << 2;
286 RA = (CIA + 8);
287 if (GPR[RS] >= 0)
49a76833 288 DELAY_SLOT (PC + offset);
f2b30012
AC		 289}
290
291
292000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
293"bgezall r<RS>, <OFFSET>"
294*mipsII:
295*mipsIII:
296*mipsIV:
90ad43b2
AC		 297// start-sanitize-vr5400
298*vr5400:
299// end-sanitize-vr5400
f2b30012
AC		 300// start-sanitize-r5900
301*r5900:
302// end-sanitize-r5900
303*r3900:
304// start-sanitize-tx19
305*tx19:
306// end-sanitize-tx19
307{
055ee297
AC		 308 address_word offset = EXTEND16 (OFFSET) << 2;
309 RA = (CIA + 8);
f2b30012
AC		 310 /* NOTE: The branch occurs AFTER the next instruction has been
311 executed */
055ee297 312 if (GPR[RS] >= 0)
49a76833 313 DELAY_SLOT (PC + offset);
f2b30012 314 else
49a76833 315 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 316}
317
318
319000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
320"bgezl r<RS>, <OFFSET>"
321*mipsII:
322*mipsIII:
323*mipsIV:
90ad43b2
AC		 324// start-sanitize-vr5400
325*vr5400:
326// end-sanitize-vr5400
f2b30012
AC		 327// start-sanitize-r5900
328*r5900:
329// end-sanitize-r5900
330*r3900:
331// start-sanitize-tx19
332*tx19:
333// end-sanitize-tx19
334{
055ee297
AC		 335 address_word offset = EXTEND16 (OFFSET) << 2;
336 if (GPR[RS] >= 0)
49a76833 337 DELAY_SLOT (PC + offset);
f2b30012 338 else
49a76833 339 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 340}
341
342
343000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
344"bgtz r<RS>, <OFFSET>"
345*mipsI:
346*mipsII:
347*mipsIII:
348*mipsIV:
90ad43b2
AC		 349// start-sanitize-vr5400
350*vr5400:
351// end-sanitize-vr5400
f2b30012
AC		 352// start-sanitize-r5900
353*r5900:
354// end-sanitize-r5900
355*r3900:
356// start-sanitize-tx19
357*tx19:
358// end-sanitize-tx19
359{
055ee297
AC		 360 address_word offset = EXTEND16 (OFFSET) << 2;
361 if (GPR[RS] > 0)
49a76833 362 DELAY_SLOT (PC + offset);
f2b30012
AC		 363}
364
365
366010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
367"bgtzl r<RS>, <OFFSET>"
368*mipsII:
369*mipsIII:
370*mipsIV:
90ad43b2
AC		 371// start-sanitize-vr5400
372*vr5400:
373// end-sanitize-vr5400
f2b30012
AC		 374// start-sanitize-r5900
375*r5900:
376// end-sanitize-r5900
377*r3900:
378// start-sanitize-tx19
379*tx19:
380// end-sanitize-tx19
381{
055ee297 382 address_word offset = EXTEND16 (OFFSET) << 2;
f2b30012
AC		 383 /* NOTE: The branch occurs AFTER the next instruction has been
384 executed */
055ee297 385 if (GPR[RS] > 0)
49a76833 386 DELAY_SLOT (PC + offset);
f2b30012 387 else
49a76833 388 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 389}
390
391
392000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
393"blez r<RS>, <OFFSET>"
394*mipsI:
395*mipsII:
396*mipsIII:
397*mipsIV:
90ad43b2
AC		 398// start-sanitize-vr5400
399*vr5400:
400// end-sanitize-vr5400
f2b30012
AC		 401// start-sanitize-r5900
402*r5900:
403// end-sanitize-r5900
404*r3900:
405// start-sanitize-tx19
406*tx19:
407// end-sanitize-tx19
408{
055ee297 409 address_word offset = EXTEND16 (OFFSET) << 2;
f2b30012
AC		 410 /* NOTE: The branch occurs AFTER the next instruction has been
411 executed */
055ee297 412 if (GPR[RS] <= 0)
49a76833 413 DELAY_SLOT (PC + offset);
f2b30012
AC		 414}
415
416
417010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
418"bgezl r<RS>, <OFFSET>"
419*mipsII:
420*mipsIII:
421*mipsIV:
90ad43b2
AC		 422// start-sanitize-vr5400
423*vr5400:
424// end-sanitize-vr5400
f2b30012
AC		 425// start-sanitize-r5900
426*r5900:
427// end-sanitize-r5900
428*r3900:
429// start-sanitize-tx19
430*tx19:
431// end-sanitize-tx19
432{
055ee297 433 address_word offset = EXTEND16 (OFFSET) << 2;
055ee297 434 if (GPR[RS] <= 0)
49a76833 435 DELAY_SLOT (PC + offset);
f2b30012 436 else
49a76833 437 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 438}
439
440
441000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
442"bltz r<RS>, <OFFSET>"
443*mipsI:
444*mipsII:
445*mipsIII:
446*mipsIV:
90ad43b2
AC		 447// start-sanitize-vr5400
448*vr5400:
449// end-sanitize-vr5400
f2b30012
AC		 450// start-sanitize-r5900
451*r5900:
452// end-sanitize-r5900
453*r3900:
454// start-sanitize-tx19
455*tx19:
456// end-sanitize-tx19
457{
055ee297
AC		 458 address_word offset = EXTEND16 (OFFSET) << 2;
459 if (GPR[RS] < 0)
49a76833 460 DELAY_SLOT (PC + offset);
f2b30012
AC		 461}
462
463
464000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
465"bltzal r<RS>, <OFFSET>"
466*mipsI:
467*mipsII:
468*mipsIII:
469*mipsIV:
90ad43b2
AC		 470// start-sanitize-vr5400
471*vr5400:
472// end-sanitize-vr5400
f2b30012
AC		 473// start-sanitize-r5900
474*r5900:
475// end-sanitize-r5900
476*r3900:
477// start-sanitize-tx19
478*tx19:
479// end-sanitize-tx19
480{
055ee297
AC		 481 address_word offset = EXTEND16 (OFFSET) << 2;
482 RA = (CIA + 8);
f2b30012
AC		 483 /* NOTE: The branch occurs AFTER the next instruction has been
484 executed */
055ee297 485 if (GPR[RS] < 0)
49a76833 486 DELAY_SLOT (PC + offset);
f2b30012
AC		 487}
488
489
490000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
491"bltzall r<RS>, <OFFSET>"
492*mipsII:
493*mipsIII:
494*mipsIV:
90ad43b2
AC		 495// start-sanitize-vr5400
496*vr5400:
497// end-sanitize-vr5400
f2b30012
AC		 498// start-sanitize-r5900
499*r5900:
500// end-sanitize-r5900
501*r3900:
502// start-sanitize-tx19
503*tx19:
504// end-sanitize-tx19
505{
055ee297
AC		 506 address_word offset = EXTEND16 (OFFSET) << 2;
507 RA = (CIA + 8);
508 if (GPR[RS] < 0)
49a76833 509 DELAY_SLOT (PC + offset);
f2b30012 510 else
49a76833 511 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 512}
513
514
515000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
516"bltzl r<RS>, <OFFSET>"
517*mipsII:
518*mipsIII:
519*mipsIV:
90ad43b2
AC		 520// start-sanitize-vr5400
521*vr5400:
522// end-sanitize-vr5400
f2b30012
AC		 523// start-sanitize-r5900
524*r5900:
525// end-sanitize-r5900
526*r3900:
527// start-sanitize-tx19
528*tx19:
529// end-sanitize-tx19
530{
055ee297 531 address_word offset = EXTEND16 (OFFSET) << 2;
f2b30012
AC		 532 /* NOTE: The branch occurs AFTER the next instruction has been
533 executed */
055ee297 534 if (GPR[RS] < 0)
49a76833 535 DELAY_SLOT (PC + offset);
f2b30012 536 else
49a76833 537 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 538}
539
540
541000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
542"bne r<RS>, r<RT>, <OFFSET>"
543*mipsI:
544*mipsII:
545*mipsIII:
546*mipsIV:
90ad43b2
AC		 547// start-sanitize-vr5400
548*vr5400:
549// end-sanitize-vr5400
f2b30012
AC		 550// start-sanitize-r5900
551*r5900:
552// end-sanitize-r5900
553*r3900:
554// start-sanitize-tx19
555*tx19:
556// end-sanitize-tx19
557{
055ee297
AC		 558 address_word offset = EXTEND16 (OFFSET) << 2;
559 if (GPR[RS] != GPR[RT])
49a76833 560 DELAY_SLOT (PC + offset);
f2b30012
AC		 561}
562
563
564010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
565"bnel r<RS>, r<RT>, <OFFSET>"
566*mipsII:
567*mipsIII:
568*mipsIV:
90ad43b2
AC		 569// start-sanitize-vr5400
570*vr5400:
571// end-sanitize-vr5400
f2b30012
AC		 572// start-sanitize-r5900
573*r5900:
574// end-sanitize-r5900
575*r3900:
576// start-sanitize-tx19
577*tx19:
578// end-sanitize-tx19
579{
085c1cb9 580 address_word offset = EXTEND16 (OFFSET) << 2;
055ee297 581 if (GPR[RS] != GPR[RT])
49a76833 582 DELAY_SLOT (PC + offset);
f2b30012 583 else
49a76833 584 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 585}
586
587
49a6eed5 588000000,20.CODE,001101:SPECIAL:32::BREAK
f2b30012
AC		 589"break"
590*mipsI:
591*mipsII:
592*mipsIII:
593*mipsIV:
90ad43b2
AC		 594// start-sanitize-vr5400
595*vr5400:
596// end-sanitize-vr5400
f2b30012
AC		 597// start-sanitize-r5900
598*r5900:
599// end-sanitize-r5900
600*r3900:
601// start-sanitize-tx19
602*tx19:
603// end-sanitize-tx19
604{
055ee297 605 SignalException(BreakPoint, instruction_0);
f2b30012
AC		 606}
607
608
49a6eed5 6090100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
f2b30012
AC		 610"cop<ZZ> <COP_FUN>"
611*mipsI:
612*mipsII:
613*mipsIII:
614*mipsIV:
615// start-sanitize-r5900
616*r5900:
617// end-sanitize-r5900
618*r3900:
619// start-sanitize-tx19
620*tx19:
621// end-sanitize-tx19
622{
085c1cb9 623 DecodeCoproc (instruction_0);
f2b30012
AC		 624}
625
626
627000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
628"dadd r<RD>, r<RS>, r<RT>"
629*mipsIII:
630*mipsIV:
90ad43b2
AC		 631// start-sanitize-vr5400
632*vr5400:
633// end-sanitize-vr5400
f2b30012
AC		 634// start-sanitize-r5900
635*r5900:
636// end-sanitize-r5900
637*r3900:
638// start-sanitize-tx19
639*tx19:
640// end-sanitize-tx19
641{
055ee297
AC		 642 ALU64_BEGIN (GPR[RS]);
643 ALU64_ADD (GPR[RT]);
644 ALU64_END (GPR[RT]);
f2b30012
AC		 645}
646
647
648011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
649"daddi r<RT>, r<RS>, <IMMEDIATE>"
650*mipsIII:
651*mipsIV:
90ad43b2
AC		 652// start-sanitize-vr5400
653*vr5400:
654// end-sanitize-vr5400
f2b30012
AC		 655// start-sanitize-r5900
656*r5900:
657// end-sanitize-r5900
658*r3900:
659// start-sanitize-tx19
660*tx19:
661// end-sanitize-tx19
662{
055ee297 663 ALU64_BEGIN (GPR[RS]);
f2b30012 664 ALU64_ADD (EXTEND16 (IMMEDIATE));
055ee297 665 ALU64_END (GPR[RT]);
f2b30012
AC		 666}
667
668
669011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
670"daddu r<RT>, r<RS>, <IMMEDIATE>"
671*mipsIII:
672*mipsIV:
90ad43b2
AC		 673// start-sanitize-vr5400
674*vr5400:
675// end-sanitize-vr5400
f2b30012
AC		 676// start-sanitize-r5900
677*r5900:
678// end-sanitize-r5900
679*r3900:
680// start-sanitize-tx19
681*tx19:
682// end-sanitize-tx19
683{
085c1cb9 684 GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE);
f2b30012
AC		 685}
686
687
688000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
689"daddu r<RD>, r<RS>, r<RT>"
690*mipsIII:
691*mipsIV:
90ad43b2
AC		 692// start-sanitize-vr5400
693*vr5400:
694// end-sanitize-vr5400
f2b30012
AC		 695// start-sanitize-r5900
696*r5900:
697// end-sanitize-r5900
698*r3900:
699// start-sanitize-tx19
700*tx19:
701// end-sanitize-tx19
702{
055ee297 703 GPR[RD] = GPR[RS] + GPR[RT];
f2b30012
AC		 704}
705
706
707000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
708"ddiv r<RS>, r<RT>"
709*mipsIII:
710*mipsIV:
90ad43b2
AC		 711// start-sanitize-vr5400
712*vr5400:
713// end-sanitize-vr5400
f2b30012
AC		 714// start-sanitize-r5900
715*r5900:
716// end-sanitize-r5900
717*r3900:
718// start-sanitize-tx19
719*tx19:
720// end-sanitize-tx19
721{
722 CHECKHILO ("Division");
723 {
055ee297
AC		 724 signed64 n = GPR[RS];
725 signed64 d = GPR[RT];
f2b30012
AC		 726 if (d == 0)
727 {
728 LO = SIGNED64 (0x8000000000000000);
729 HI = 0;
730 }
731 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
732 {
733 LO = SIGNED64 (0x8000000000000000);
734 HI = 0;
735 }
736 else
737 {
738 LO = (n / d);
739 HI = (n % d);
740 }
741 }
742}
743
744
745
746000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
747"ddivu r<RS>, r<RT>"
748*mipsIII:
749*mipsIV:
750*r3900:
90ad43b2
AC		 751// start-sanitize-vr5400
752*vr5400:
753// end-sanitize-vr5400
f2b30012
AC		 754// start-sanitize-tx19
755*tx19:
756// end-sanitize-tx19
757{
758 CHECKHILO ("Division");
759 {
055ee297
AC		 760 unsigned64 n = GPR[RS];
761 unsigned64 d = GPR[RT];
f2b30012
AC		 762 if (d == 0)
763 {
764 LO = SIGNED64 (0x8000000000000000);
765 HI = 0;
766 }
767 else
768 {
769 LO = (n / d);
770 HI = (n % d);
771 }
772 }
773}
774
775
776000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
777"div r<RS>, r<RT>"
778*mipsI:
779*mipsII:
780*mipsIII:
781*mipsIV:
90ad43b2
AC		 782// start-sanitize-vr5400
783*vr5400:
784// end-sanitize-vr5400
f2b30012
AC		 785// start-sanitize-r5900
786*r5900:
787// end-sanitize-r5900
788*r3900:
789// start-sanitize-tx19
790*tx19:
791// end-sanitize-tx19
792{
793 CHECKHILO("Division");
794 {
055ee297
AC		 795 signed32 n = GPR[RS];
796 signed32 d = GPR[RT];
f2b30012
AC		 797 if (d == 0)
798 {
799 LO = EXTEND32 (0x80000000);
800 HI = EXTEND32 (0);
801 }
055ee297 802 else if (d == -1 && d == 0x80000000)
f2b30012
AC		 803 {
804 LO = EXTEND32 (0x80000000);
805 HI = EXTEND32 (0);
806 }
807 else
808 {
809 LO = EXTEND32 (n / d);
810 HI = EXTEND32 (n % d);
811 }
812 }
813}
814
815
816000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
817"divu r<RS>, r<RT>"
818*mipsI:
819*mipsII:
820*mipsIII:
821*mipsIV:
90ad43b2
AC		 822// start-sanitize-vr5400
823*vr5400:
824// end-sanitize-vr5400
f2b30012
AC		 825// start-sanitize-r5900
826*r5900:
827// end-sanitize-r5900
828*r3900:
829// start-sanitize-tx19
830*tx19:
831// end-sanitize-tx19
832{
833 CHECKHILO ("Division");
834 {
055ee297
AC		 835 unsigned32 n = GPR[RS];
836 unsigned32 d = GPR[RT];
f2b30012
AC		 837 if (d == 0)
838 {
839 LO = EXTEND32 (0x80000000);
840 HI = EXTEND32 (0);
841 }
842 else
843 {
844 LO = EXTEND32 (n / d);
845 HI = EXTEND32 (n % d);
846 }
847 }
848}
849
850
851000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
852"dmult r<RS>, r<RT>"
853*mipsIII:
854*mipsIV:
90ad43b2
AC		 855// start-sanitize-vr5400
856*vr5400:
857// end-sanitize-vr5400
f2b30012
AC		 858*r3900:
859// start-sanitize-tx19
860*tx19:
861// end-sanitize-tx19
862{
863 CHECKHILO ("Multiplication");
864 {
055ee297
AC		 865 signed64 op1 = GPR[RS];
866 signed64 op2 = GPR[RT];
f2b30012
AC		 867 unsigned64 lo;
868 unsigned64 hi;
869 unsigned64 m00;
870 unsigned64 m01;
871 unsigned64 m10;
872 unsigned64 m11;
873 unsigned64 mid;
f2b30012
AC		 874 int sign = 0;
875 /* make it unsigned */
876 if (op1 < 0)
877 {
878 op1 = - op1;
879 ++sign;
880 }
881 if (op2 < 0)
882 {
883 op2 = - op2;
884 ++sign;
885 }
886 /* multuply out the 4 sub products */
887 m00 = (VL4_8 (op1) * VL4_8 (op2));
888 m10 = (VH4_8 (op1) * VL4_8 (op2));
889 m01 = (VL4_8 (op1) * VH4_8 (op2));
890 m11 = (VH4_8 (op1) * VH4_8 (op2));
891 /* add the products */
892 mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
893 lo = U8_4 (mid, m00);
894 hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
895 /* save the result */
896 if (sign & 1)
897 {
898 LO = -lo;
899 if (lo == 0)
900 HI = -hi;
901 else
902 HI = -hi - 1;
903 }
904 else
905 {
906 LO = lo;
907 HI = hi;
908 }
909 }
910}
911
912
913000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
914"dmultu r<RS>, r<RT>"
915*mipsIII:
916*mipsIV:
90ad43b2
AC		 917// start-sanitize-vr5400
918*vr5400:
919// end-sanitize-vr5400
f2b30012
AC		 920*r3900:
921// start-sanitize-tx19
922*tx19:
923// end-sanitize-tx19
924{
925 CHECKHILO ("Multiplication");
926 {
055ee297
AC		 927 signed64 op1 = GPR[RS];
928 signed64 op2 = GPR[RT];
f2b30012
AC		 929 unsigned64 lo;
930 unsigned64 hi;
931 unsigned64 m00;
932 unsigned64 m01;
933 unsigned64 m10;
934 unsigned64 m11;
935 unsigned64 mid;
f2b30012
AC		 936 /* multuply out the 4 sub products */
937 m00 = (VL4_8 (op1) * VL4_8 (op2));
938 m10 = (VH4_8 (op1) * VL4_8 (op2));
939 m01 = (VL4_8 (op1) * VH4_8 (op2));
940 m11 = (VH4_8 (op1) * VH4_8 (op2));
941 /* add the products */
942 mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
943 lo = U8_4 (mid, m00);
944 hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
945 /* save the result */
946 LO = lo;
947 HI = hi;
948 }
949}
950
951
055ee297 95200000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
01b9cd49 953"dsll r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 954*mipsIII:
955*mipsIV:
90ad43b2
AC		 956// start-sanitize-vr5400
957*vr5400:
958// end-sanitize-vr5400
f2b30012
AC		 959// start-sanitize-r5900
960*r5900:
961// end-sanitize-r5900
962*r3900:
963// start-sanitize-tx19
964*tx19:
965// end-sanitize-tx19
966{
01b9cd49 967 int s = SHIFT;
055ee297 968 GPR[RD] = GPR[RT] << s;
f2b30012
AC		 969}
970
971
055ee297 97200000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
01b9cd49 973"dsll32 r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 974*mipsIII:
975*mipsIV:
90ad43b2
AC		 976// start-sanitize-vr5400
977*vr5400:
978// end-sanitize-vr5400
f2b30012
AC		 979// start-sanitize-r5900
980*r5900:
981// end-sanitize-r5900
982*r3900:
983// start-sanitize-tx19
984*tx19:
985// end-sanitize-tx19
986{
01b9cd49 987 int s = 32 + SHIFT;
055ee297 988 GPR[RD] = GPR[RT] << s;
f2b30012
AC		 989}
990
991
992000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
993"dsllv r<RD>, r<RT>, r<RS>"
994*mipsIII:
995*mipsIV:
90ad43b2
AC		 996// start-sanitize-vr5400
997*vr5400:
998// end-sanitize-vr5400
f2b30012
AC		 999// start-sanitize-r5900
1000*r5900:
1001// end-sanitize-r5900
1002*r3900:
1003// start-sanitize-tx19
1004*tx19:
1005// end-sanitize-tx19
1006{
055ee297
AC		 1007 int s = MASKED64 (GPR[RS], 5, 0);
1008 GPR[RD] = GPR[RT] << s;
f2b30012
AC		 1009}
1010
1011
055ee297 101200000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
01b9cd49 1013"dsra r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1014*mipsIII:
1015*mipsIV:
90ad43b2
AC		 1016// start-sanitize-vr5400
1017*vr5400:
1018// end-sanitize-vr5400
f2b30012
AC		 1019// start-sanitize-r5900
1020*r5900:
1021// end-sanitize-r5900
1022*r3900:
1023// start-sanitize-tx19
1024*tx19:
1025// end-sanitize-tx19
1026{
01b9cd49 1027 int s = SHIFT;
055ee297 1028 GPR[RD] = ((signed64) GPR[RT]) >> s;
f2b30012
AC		 1029}
1030
1031
055ee297 103200000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
01b9cd49 1033"dsra32 r<RT>, r<RD>, <SHIFT>"
f2b30012
AC		 1034*mipsIII:
1035*mipsIV:
90ad43b2
AC		 1036// start-sanitize-vr5400
1037*vr5400:
1038// end-sanitize-vr5400
f2b30012
AC		 1039// start-sanitize-r5900
1040*r5900:
1041// end-sanitize-r5900
1042*r3900:
1043// start-sanitize-tx19
1044*tx19:
1045// end-sanitize-tx19
1046{
01b9cd49 1047 int s = 32 + SHIFT;
055ee297 1048 GPR[RD] = ((signed64) GPR[RT]) >> s;
f2b30012
AC		 1049}
1050
1051
1052000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1053"dsra32 r<RT>, r<RD>, r<RS>"
1054*mipsIII:
1055*mipsIV:
90ad43b2
AC		 1056// start-sanitize-vr5400
1057*vr5400:
1058// end-sanitize-vr5400
f2b30012
AC		 1059// start-sanitize-r5900
1060*r5900:
1061// end-sanitize-r5900
1062*r3900:
1063// start-sanitize-tx19
1064*tx19:
1065// end-sanitize-tx19
1066{
055ee297
AC		 1067 int s = MASKED64 (GPR[RS], 5, 0);
1068 GPR[RD] = ((signed64) GPR[RT]) >> s;
f2b30012
AC		 1069}
1070
1071
055ee297 107200000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
01b9cd49 1073"dsrav r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1074*mipsIII:
1075*mipsIV:
90ad43b2
AC		 1076// start-sanitize-vr5400
1077*vr5400:
1078// end-sanitize-vr5400
f2b30012
AC		 1079// start-sanitize-r5900
1080*r5900:
1081// end-sanitize-r5900
1082*r3900:
1083// start-sanitize-tx19
1084*tx19:
1085// end-sanitize-tx19
1086{
01b9cd49 1087 int s = SHIFT;
055ee297 1088 GPR[RD] = (unsigned64) GPR[RT] >> s;
f2b30012
AC		 1089}
1090
1091
055ee297 109200000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
01b9cd49 1093"dsrl32 r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1094*mipsIII:
1095*mipsIV:
90ad43b2
AC		 1096// start-sanitize-vr5400
1097*vr5400:
1098// end-sanitize-vr5400
f2b30012
AC		 1099// start-sanitize-r5900
1100*r5900:
1101// end-sanitize-r5900
1102*r3900:
1103// start-sanitize-tx19
1104*tx19:
1105// end-sanitize-tx19
1106{
01b9cd49 1107 int s = 32 + SHIFT;
055ee297 1108 GPR[RD] = (unsigned64) GPR[RT] >> s;
f2b30012
AC		 1109}
1110
1111
1112000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1113"dsrl32 r<RD>, r<RT>, r<RS>"
1114*mipsIII:
1115*mipsIV:
90ad43b2
AC		 1116// start-sanitize-vr5400
1117*vr5400:
1118// end-sanitize-vr5400
f2b30012
AC		 1119// start-sanitize-r5900
1120*r5900:
1121// end-sanitize-r5900
1122*r3900:
1123// start-sanitize-tx19
1124*tx19:
1125// end-sanitize-tx19
1126{
055ee297
AC		 1127 int s = MASKED64 (GPR[RS], 5, 0);
1128 GPR[RD] = (unsigned64) GPR[RT] >> s;
f2b30012
AC		 1129}
1130
1131
1132000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1133"dsub r<RD>, r<RS>, r<RT>"
1134*mipsIII:
1135*mipsIV:
90ad43b2
AC		 1136// start-sanitize-vr5400
1137*vr5400:
1138// end-sanitize-vr5400
f2b30012
AC		 1139// start-sanitize-r5900
1140*r5900:
1141// end-sanitize-r5900
1142*r3900:
1143// start-sanitize-tx19
1144*tx19:
1145// end-sanitize-tx19
1146{
055ee297
AC		 1147 ALU64_BEGIN (GPR[RS]);
1148 ALU64_SUB (GPR[RT]);
1149 ALU64_END (GPR[RD]);
f2b30012
AC		 1150}
1151
1152
1153000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1154"dsubu r<RD>, r<RS>, r<RT>"
1155*mipsIII:
1156*mipsIV:
90ad43b2
AC		 1157// start-sanitize-vr5400
1158*vr5400:
1159// end-sanitize-vr5400
f2b30012
AC		 1160// start-sanitize-r5900
1161*r5900:
1162// end-sanitize-r5900
1163*r3900:
1164// start-sanitize-tx19
1165*tx19:
1166// end-sanitize-tx19
1167{
055ee297 1168 GPR[RD] = GPR[RS] - GPR[RT];
f2b30012
AC		 1169}
1170
1171
1172000010,26.INSTR_INDEX:NORMAL:32::J
1173"j <INSTR_INDEX>"
1174*mipsI:
1175*mipsII:
1176*mipsIII:
1177*mipsIV:
90ad43b2
AC		 1178// start-sanitize-vr5400
1179*vr5400:
1180// end-sanitize-vr5400
f2b30012
AC		 1181// start-sanitize-r5900
1182*r5900:
1183// end-sanitize-r5900
1184*r3900:
1185// start-sanitize-tx19
1186*tx19:
1187// end-sanitize-tx19
1188{
49a76833 1189 /* NOTE: The region used is that of the delay slot NIA and NOT the
f2b30012 1190 current instruction */
49a76833
AC		 1191 address_word region = (NIA & MASK (63, 28));
1192 DELAY_SLOT (region | (INSTR_INDEX << 2));
f2b30012
AC		 1193}
1194
1195
1196000011,26.INSTR_INDEX:NORMAL:32::JAL
1197"jal <INSTR_INDEX>"
1198*mipsI:
1199*mipsII:
1200*mipsIII:
1201*mipsIV:
90ad43b2
AC		 1202// start-sanitize-vr5400
1203*vr5400:
1204// end-sanitize-vr5400
f2b30012
AC		 1205// start-sanitize-r5900
1206*r5900:
1207// end-sanitize-r5900
1208*r3900:
1209// start-sanitize-tx19
1210*tx19:
1211// end-sanitize-tx19
1212{
1213 /* NOTE: The region used is that of the delay slot and NOT the
1214 current instruction */
49a76833 1215 address_word region = (NIA & MASK (63, 28));
055ee297 1216 GPR[31] = CIA + 8;
49a76833 1217 DELAY_SLOT (region | (INSTR_INDEX << 2));
f2b30012
AC		 1218}
1219
1220
1221000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1222"jalr r<RS>":RD == 31
1223"jalr r<RD>, r<RS>"
1224*mipsI:
1225*mipsII:
1226*mipsIII:
1227*mipsIV:
90ad43b2
AC		 1228// start-sanitize-vr5400
1229*vr5400:
1230// end-sanitize-vr5400
f2b30012
AC		 1231// start-sanitize-r5900
1232*r5900:
1233// end-sanitize-r5900
1234*r3900:
1235// start-sanitize-tx19
1236*tx19:
1237// end-sanitize-tx19
1238{
055ee297
AC		 1239 address_word temp = GPR[RS];
1240 GPR[RD] = CIA + 8;
49a76833 1241 DELAY_SLOT (temp);
f2b30012
AC		 1242}
1243
1244
1245000000,5.RS,000000000000000001000:SPECIAL:32::JR
1246"jr r<RS>"
1247*mipsI:
1248*mipsII:
1249*mipsIII:
1250*mipsIV:
90ad43b2
AC		 1251// start-sanitize-vr5400
1252*vr5400:
1253// end-sanitize-vr5400
f2b30012
AC		 1254// start-sanitize-r5900
1255*r5900:
1256// end-sanitize-r5900
1257*r3900:
1258// start-sanitize-tx19
1259*tx19:
1260// end-sanitize-tx19
1261{
49a76833 1262 DELAY_SLOT (GPR[RS]);
f2b30012
AC		 1263}
1264
1265
1266100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1267"lb r<RT>, <OFFSET>(r<BASE>)"
1268*mipsI:
1269*mipsII:
1270*mipsIII:
1271*mipsIV:
90ad43b2
AC		 1272// start-sanitize-vr5400
1273*vr5400:
1274// end-sanitize-vr5400
f2b30012
AC		 1275// start-sanitize-r5900
1276*r5900:
1277// end-sanitize-r5900
1278*r3900:
1279// start-sanitize-tx19
1280*tx19:
1281// end-sanitize-tx19
1282{
1283 unsigned32 instruction = instruction_0;
055ee297
AC		 1284 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1285 int destreg = ((instruction >> 16) & 0x0000001F);
1286 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1287 {
49a76833
AC		 1288 address_word vaddr = ((uword64)op1 + offset);
1289 address_word paddr;
f2b30012
AC		 1290 int uncached;
1291 {
1292 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1293 {
1294 uword64 memval = 0;
1295 uword64 memval1 = 0;
1296 uword64 mask = 0x7;
1297 unsigned int shift = 0;
055ee297
AC		 1298 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1299 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1300 unsigned int byte;
f2b30012
AC		 1301 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1302 LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1303 byte = ((vaddr & mask) ^ (bigend << shift));
1304 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
1305 }
1306 }
1307 }
1308}
1309
1310
1311100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1312"lbu r<RT>, <OFFSET>(r<BASE>)"
1313*mipsI:
1314*mipsII:
1315*mipsIII:
1316*mipsIV:
90ad43b2
AC		 1317// start-sanitize-vr5400
1318*vr5400:
1319// end-sanitize-vr5400
f2b30012
AC		 1320// start-sanitize-r5900
1321*r5900:
1322// end-sanitize-r5900
1323*r3900:
1324// start-sanitize-tx19
1325*tx19:
1326// end-sanitize-tx19
1327{
1328 unsigned32 instruction = instruction_0;
055ee297
AC		 1329 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1330 int destreg = ((instruction >> 16) & 0x0000001F);
1331 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1332 {
49a76833
AC		 1333 address_word vaddr = ((unsigned64)op1 + offset);
1334 address_word paddr;
f2b30012
AC		 1335 int uncached;
1336 {
1337 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1338 {
1339 unsigned64 memval = 0;
1340 unsigned64 memval1 = 0;
1341 unsigned64 mask = 0x7;
1342 unsigned int shift = 0;
055ee297
AC		 1343 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1344 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1345 unsigned int byte;
f2b30012
AC		 1346 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1347 LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1348 byte = ((vaddr & mask) ^ (bigend << shift));
1349 GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
1350 }
1351 }
1352 }
1353}
1354
1355
1356110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1357"ld r<RT>, <OFFSET>(r<BASE>)"
1358*mipsIII:
1359*mipsIV:
90ad43b2
AC		 1360// start-sanitize-vr5400
1361*vr5400:
1362// end-sanitize-vr5400
f2b30012
AC		 1363// start-sanitize-r5900
1364*r5900:
1365// end-sanitize-r5900
1366*r3900:
1367// start-sanitize-tx19
1368*tx19:
1369// end-sanitize-tx19
1370{
1371 unsigned32 instruction = instruction_0;
055ee297
AC		 1372 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1373 int destreg = ((instruction >> 16) & 0x0000001F);
1374 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1375 {
49a76833
AC		 1376 address_word vaddr = ((unsigned64)op1 + offset);
1377 address_word paddr;
f2b30012
AC		 1378 int uncached;
1379 if ((vaddr & 7) != 0)
055ee297 1380 SignalExceptionAddressLoad();
f2b30012
AC		 1381 else
1382 {
1383 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1384 {
1385 unsigned64 memval = 0;
1386 unsigned64 memval1 = 0;
f2b30012
AC		 1387 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1388 GPR[destreg] = memval;
1389 }
1390 }
1391 }
1392}
1393
1394
49a6eed5 13951101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
f2b30012
AC		 1396"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1397*mipsII:
1398*mipsIII:
1399*mipsIV:
90ad43b2
AC		 1400// start-sanitize-vr5400
1401*vr5400:
1402// end-sanitize-vr5400
f2b30012
AC		 1403// start-sanitize-r5900
1404*r5900:
1405// end-sanitize-r5900
1406*r3900:
1407// start-sanitize-tx19
1408*tx19:
1409// end-sanitize-tx19
1410{
1411 unsigned32 instruction = instruction_0;
055ee297
AC		 1412 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1413 int destreg = ((instruction >> 16) & 0x0000001F);
1414 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1415 {
49a76833
AC		 1416 address_word vaddr = ((unsigned64)op1 + offset);
1417 address_word paddr;
f2b30012
AC		 1418 int uncached;
1419 if ((vaddr & 7) != 0)
055ee297 1420 SignalExceptionAddressLoad();
f2b30012
AC		 1421 else
1422 {
1423 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1424 {
1425 unsigned64 memval = 0;
1426 unsigned64 memval1 = 0;
f2b30012
AC		 1427 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1428 COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
1429 }
1430 }
1431 }
1432}
1433
1434
1435011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1436"ldl r<RT>, <OFFSET>(r<BASE>)"
1437*mipsIII:
1438*mipsIV:
90ad43b2
AC		 1439// start-sanitize-vr5400
1440*vr5400:
1441// end-sanitize-vr5400
f2b30012
AC		 1442// start-sanitize-r5900
1443*r5900:
1444// end-sanitize-r5900
1445*r3900:
1446// start-sanitize-tx19
1447*tx19:
1448// end-sanitize-tx19
1449{
1450 unsigned32 instruction = instruction_0;
055ee297
AC		 1451 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1452 int destreg = ((instruction >> 16) & 0x0000001F);
1453 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1454 {
49a76833
AC		 1455 address_word vaddr = ((unsigned64)op1 + offset);
1456 address_word paddr;
f2b30012
AC		 1457 int uncached;
1458 {
1459 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1460 {
1461 unsigned64 memval = 0;
1462 unsigned64 memval1 = 0;
1463 unsigned64 mask = 7;
1464 unsigned int reverse = (ReverseEndian ? mask : 0);
1465 unsigned int bigend = (BigEndianCPU ? mask : 0);
1466 int byte;
1467 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1468 byte = ((vaddr & mask) ^ bigend);
1469 if (!!ByteSwapMem)
1470 paddr &= ~mask;
1471 LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1472 GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
1473 }
1474 }
1475 }
1476}
1477
1478
1479011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1480"ldr r<RT>, <OFFSET>(r<BASE>)"
1481*mipsIII:
1482*mipsIV:
90ad43b2
AC		 1483// start-sanitize-vr5400
1484*vr5400:
1485// end-sanitize-vr5400
f2b30012
AC		 1486// start-sanitize-r5900
1487*r5900:
1488// end-sanitize-r5900
1489*r3900:
1490// start-sanitize-tx19
1491*tx19:
1492// end-sanitize-tx19
1493{
1494 unsigned32 instruction = instruction_0;
055ee297
AC		 1495 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1496 int destreg = ((instruction >> 16) & 0x0000001F);
1497 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1498 {
49a76833
AC		 1499 address_word vaddr = ((unsigned64)op1 + offset);
1500 address_word paddr;
f2b30012
AC		 1501 int uncached;
1502 {
1503 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1504 {
1505 unsigned64 memval = 0;
1506 unsigned64 memval1 = 0;
1507 unsigned64 mask = 7;
1508 unsigned int reverse = (ReverseEndian ? mask : 0);
1509 unsigned int bigend = (BigEndianCPU ? mask : 0);
1510 int byte;
1511 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1512 byte = ((vaddr & mask) ^ bigend);
1513 if (!ByteSwapMem)
1514 paddr &= ~mask;
1515 LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
1516 {
1517 unsigned64 srcmask;
1518 if (byte == 0)
1519 srcmask = 0;
1520 else
1521 srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
1522 GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1523 }
1524 }
1525 }
1526 }
1527}
1528
1529
1530100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1531"lh r<RT>, <OFFSET>(r<BASE>)"
1532*mipsI:
1533*mipsII:
1534*mipsIII:
1535*mipsIV:
90ad43b2
AC		 1536// start-sanitize-vr5400
1537*vr5400:
1538// end-sanitize-vr5400
f2b30012
AC		 1539// start-sanitize-r5900
1540*r5900:
1541// end-sanitize-r5900
1542*r3900:
1543// start-sanitize-tx19
1544*tx19:
1545// end-sanitize-tx19
1546{
1547 unsigned32 instruction = instruction_0;
055ee297
AC		 1548 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1549 int destreg = ((instruction >> 16) & 0x0000001F);
1550 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1551 {
49a76833
AC		 1552 address_word vaddr = ((unsigned64)op1 + offset);
1553 address_word paddr;
f2b30012
AC		 1554 int uncached;
1555 if ((vaddr & 1) != 0)
055ee297 1556 SignalExceptionAddressLoad();
f2b30012
AC		 1557 else
1558 {
1559 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1560 {
1561 unsigned64 memval = 0;
1562 unsigned64 memval1 = 0;
1563 unsigned64 mask = 0x7;
1564 unsigned int shift = 1;
055ee297
AC		 1565 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1566 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1567 unsigned int byte;
f2b30012
AC		 1568 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1569 LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1570 byte = ((vaddr & mask) ^ (bigend << shift));
1571 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
1572 }
1573 }
1574 }
1575}
1576
1577
1578100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1579"lhu r<RT>, <OFFSET>(r<BASE>)"
1580*mipsI:
1581*mipsII:
1582*mipsIII:
1583*mipsIV:
90ad43b2
AC		 1584// start-sanitize-vr5400
1585*vr5400:
1586// end-sanitize-vr5400
f2b30012
AC		 1587// start-sanitize-r5900
1588*r5900:
1589// end-sanitize-r5900
1590*r3900:
1591// start-sanitize-tx19
1592*tx19:
1593// end-sanitize-tx19
1594{
1595 unsigned32 instruction = instruction_0;
055ee297
AC		 1596 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1597 int destreg = ((instruction >> 16) & 0x0000001F);
1598 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1599 {
49a76833
AC		 1600 address_word vaddr = ((unsigned64)op1 + offset);
1601 address_word paddr;
f2b30012
AC		 1602 int uncached;
1603 if ((vaddr & 1) != 0)
055ee297 1604 SignalExceptionAddressLoad();
f2b30012
AC		 1605 else
1606 {
1607 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1608 {
1609 unsigned64 memval = 0;
1610 unsigned64 memval1 = 0;
1611 unsigned64 mask = 0x7;
1612 unsigned int shift = 1;
055ee297
AC		 1613 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1614 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1615 unsigned int byte;
f2b30012
AC		 1616 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1617 LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1618 byte = ((vaddr & mask) ^ (bigend << shift));
1619 GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
1620 }
1621 }
1622 }
1623}
1624
1625
1626110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1627"ll r<RT>, <OFFSET>(r<BASE>)"
1628*mipsII:
1629*mipsIII:
1630*mipsIV:
90ad43b2
AC		 1631// start-sanitize-vr5400
1632*vr5400:
1633// end-sanitize-vr5400
f2b30012
AC		 1634// start-sanitize-r5900
1635*r5900:
1636// end-sanitize-r5900
1637*r3900:
1638// start-sanitize-tx19
1639*tx19:
1640// end-sanitize-tx19
1641{
1642 unsigned32 instruction = instruction_0;
055ee297
AC		 1643 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1644 int destreg = ((instruction >> 16) & 0x0000001F);
1645 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1646 {
49a76833
AC		 1647 address_word vaddr = ((unsigned64)op1 + offset);
1648 address_word paddr;
f2b30012
AC		 1649 int uncached;
1650 if ((vaddr & 3) != 0)
055ee297 1651 SignalExceptionAddressLoad();
f2b30012
AC		 1652 else
1653 {
1654 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1655 {
1656 unsigned64 memval = 0;
1657 unsigned64 memval1 = 0;
1658 unsigned64 mask = 0x7;
1659 unsigned int shift = 2;
055ee297
AC		 1660 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1661 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1662 unsigned int byte;
f2b30012
AC		 1663 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1664 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1665 byte = ((vaddr & mask) ^ (bigend << shift));
1666 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1667 LLBIT = 1;
1668 }
1669 }
1670 }
1671}
1672
1673
1674110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1675"lld r<RT>, <OFFSET>(r<BASE>)"
1676*mipsIII:
1677*mipsIV:
90ad43b2
AC		 1678// start-sanitize-vr5400
1679*vr5400:
1680// end-sanitize-vr5400
f2b30012
AC		 1681// start-sanitize-r5900
1682*r5900:
1683// end-sanitize-r5900
1684*r3900:
1685// start-sanitize-tx19
1686*tx19:
1687// end-sanitize-tx19
1688{
1689 unsigned32 instruction = instruction_0;
055ee297
AC		 1690 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1691 int destreg = ((instruction >> 16) & 0x0000001F);
1692 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1693 {
49a76833
AC		 1694 address_word vaddr = ((unsigned64)op1 + offset);
1695 address_word paddr;
f2b30012
AC		 1696 int uncached;
1697 if ((vaddr & 7) != 0)
055ee297 1698 SignalExceptionAddressLoad();
f2b30012
AC		 1699 else
1700 {
1701 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1702 {
1703 unsigned64 memval = 0;
1704 unsigned64 memval1 = 0;
f2b30012
AC		 1705 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1706 GPR[destreg] = memval;
1707 LLBIT = 1;
1708 }
1709 }
1710 }
1711}
1712
1713
1714001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1715"lui r<RT>, <IMMEDIATE>"
1716*mipsI:
1717*mipsII:
1718*mipsIII:
1719*mipsIV:
90ad43b2
AC		 1720// start-sanitize-vr5400
1721*vr5400:
1722// end-sanitize-vr5400
f2b30012
AC		 1723// start-sanitize-r5900
1724*r5900:
1725// end-sanitize-r5900
1726*r3900:
1727// start-sanitize-tx19
1728*tx19:
1729// end-sanitize-tx19
1730{
055ee297 1731 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
f2b30012
AC		 1732}
1733
1734
1735100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1736"lw r<RT>, <OFFSET>(r<BASE>)"
1737*mipsI:
1738*mipsII:
1739*mipsIII:
1740*mipsIV:
90ad43b2
AC		 1741// start-sanitize-vr5400
1742*vr5400:
1743// end-sanitize-vr5400
f2b30012
AC		 1744// start-sanitize-r5900
1745*r5900:
1746// end-sanitize-r5900
1747*r3900:
1748// start-sanitize-tx19
1749*tx19:
1750// end-sanitize-tx19
1751{
1752 unsigned32 instruction = instruction_0;
055ee297
AC		 1753 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1754 int destreg = ((instruction >> 16) & 0x0000001F);
1755 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1756 {
49a76833
AC		 1757 address_word vaddr = ((unsigned64)op1 + offset);
1758 address_word paddr;
f2b30012
AC		 1759 int uncached;
1760 if ((vaddr & 3) != 0)
055ee297 1761 SignalExceptionAddressLoad();
f2b30012
AC		 1762 else
1763 {
1764 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1765 {
1766 unsigned64 memval = 0;
1767 unsigned64 memval1 = 0;
1768 unsigned64 mask = 0x7;
1769 unsigned int shift = 2;
055ee297
AC		 1770 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1771 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1772 unsigned int byte;
f2b30012
AC		 1773 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1774 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1775 byte = ((vaddr & mask) ^ (bigend << shift));
1776 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1777 }
1778 }
1779 }
1780}
1781
1782
49a6eed5 17831100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
f2b30012
AC		 1784"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1785*mipsI:
1786*mipsII:
1787*mipsIII:
1788*mipsIV:
90ad43b2
AC		 1789// start-sanitize-vr5400
1790*vr5400:
1791// end-sanitize-vr5400
f2b30012
AC		 1792// start-sanitize-r5900
1793*r5900:
1794// end-sanitize-r5900
1795*r3900:
1796// start-sanitize-tx19
1797*tx19:
1798// end-sanitize-tx19
1799{
1800 unsigned32 instruction = instruction_0;
055ee297
AC		 1801 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1802 int destreg = ((instruction >> 16) & 0x0000001F);
1803 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1804 {
49a76833
AC		 1805 address_word vaddr = ((unsigned64)op1 + offset);
1806 address_word paddr;
f2b30012
AC		 1807 int uncached;
1808 if ((vaddr & 3) != 0)
055ee297 1809 SignalExceptionAddressLoad();
f2b30012
AC		 1810 else
1811 {
1812 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1813 {
1814 unsigned64 memval = 0;
1815 unsigned64 memval1 = 0;
1816 unsigned64 mask = 0x7;
1817 unsigned int shift = 2;
055ee297
AC		 1818 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1819 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1820 unsigned int byte;
f2b30012
AC		 1821 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1822 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1823 byte = ((vaddr & mask) ^ (bigend << shift));
1824 COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
1825 }
1826 }
1827 }
1828}
1829
1830
1831100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1832"lwl r<RT>, <OFFSET>(r<BASE>)"
1833*mipsI:
1834*mipsII:
1835*mipsIII:
1836*mipsIV:
90ad43b2
AC		 1837// start-sanitize-vr5400
1838*vr5400:
1839// end-sanitize-vr5400
f2b30012
AC		 1840// start-sanitize-r5900
1841*r5900:
1842// end-sanitize-r5900
1843*r3900:
1844// start-sanitize-tx19
1845*tx19:
1846// end-sanitize-tx19
1847{
1848 unsigned32 instruction = instruction_0;
055ee297
AC		 1849 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1850 int destreg = ((instruction >> 16) & 0x0000001F);
1851 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1852 {
49a76833
AC		 1853 address_word vaddr = ((unsigned64)op1 + offset);
1854 address_word paddr;
f2b30012
AC		 1855 int uncached;
1856 {
1857 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1858 {
1859 unsigned64 memval = 0;
1860 unsigned64 memval1 = 0;
1861 unsigned64 mask = 3;
1862 unsigned int reverse = (ReverseEndian ? mask : 0);
1863 unsigned int bigend = (BigEndianCPU ? mask : 0);
1864 int byte;
1865 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1866 byte = ((vaddr & mask) ^ bigend);
1867 if (!!ByteSwapMem)
1868 paddr &= ~mask;
1869 LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1870 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1871 memval >>= 32;
1872 }
1873 GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
1874 GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1875 }
1876 }
1877 }
1878}
1879
1880
1881100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1882"lwr r<RT>, <OFFSET>(r<BASE>)"
1883*mipsI:
1884*mipsII:
1885*mipsIII:
1886*mipsIV:
90ad43b2
AC		 1887// start-sanitize-vr5400
1888*vr5400:
1889// end-sanitize-vr5400
f2b30012
AC		 1890// start-sanitize-r5900
1891*r5900:
1892// end-sanitize-r5900
1893*r3900:
1894// start-sanitize-tx19
1895*tx19:
1896// end-sanitize-tx19
1897{
1898 unsigned32 instruction = instruction_0;
055ee297
AC		 1899 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1900 int destreg = ((instruction >> 16) & 0x0000001F);
1901 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1902 {
49a76833
AC		 1903 address_word vaddr = ((unsigned64)op1 + offset);
1904 address_word paddr;
f2b30012
AC		 1905 int uncached;
1906 {
1907 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1908 {
1909 unsigned64 memval = 0;
1910 unsigned64 memval1 = 0;
1911 unsigned64 mask = 3;
1912 unsigned int reverse = (ReverseEndian ? mask : 0);
1913 unsigned int bigend = (BigEndianCPU ? mask : 0);
1914 int byte;
1915 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1916 byte = ((vaddr & mask) ^ bigend);
1917 if (!ByteSwapMem)
1918 paddr &= ~mask;
1919 LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
1920 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1921 memval >>= 32;
1922 }
1923 {
1924 unsigned64 srcmask;
1925 if (byte == 0)
1926 srcmask = 0;
1927 else
1928 srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
1929 GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1930 }
1931 GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1932 }
1933 }
1934 }
1935}
1936
1937
1938100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
1939"lwu r<RT>, <OFFSET>(r<BASE>)"
1940*mipsIII:
1941*mipsIV:
90ad43b2
AC		 1942// start-sanitize-vr5400
1943*vr5400:
1944// end-sanitize-vr5400
f2b30012
AC		 1945// start-sanitize-r5900
1946*r5900:
1947// end-sanitize-r5900
1948*r3900:
1949// start-sanitize-tx19
1950*tx19:
1951// end-sanitize-tx19
1952{
1953 unsigned32 instruction = instruction_0;
055ee297
AC		 1954 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1955 int destreg = ((instruction >> 16) & 0x0000001F);
1956 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1957 {
49a76833
AC		 1958 address_word vaddr = ((unsigned64)op1 + offset);
1959 address_word paddr;
f2b30012
AC		 1960 int uncached;
1961 if ((vaddr & 3) != 0)
055ee297 1962 SignalExceptionAddressLoad();
f2b30012
AC		 1963 else
1964 {
1965 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1966 {
1967 unsigned64 memval = 0;
1968 unsigned64 memval1 = 0;
1969 unsigned64 mask = 0x7;
1970 unsigned int shift = 2;
055ee297
AC		 1971 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1972 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1973 unsigned int byte;
f2b30012
AC		 1974 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1975 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1976 byte = ((vaddr & mask) ^ (bigend << shift));
1977 GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
1978 }
1979 }
1980 }
1981}
1982
1983
1984000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1985"mfhi r<RD>"
1986*mipsI:
1987*mipsII:
1988*mipsIII:
1989*mipsIV:
90ad43b2
AC		 1990// start-sanitize-vr5400
1991*vr5400:
1992// end-sanitize-vr5400
f2b30012
AC		 1993// start-sanitize-r5900
1994*r5900:
1995// end-sanitize-r5900
1996*r3900:
1997// start-sanitize-tx19
1998*tx19:
1999// end-sanitize-tx19
2000{
055ee297 2001 GPR[RD] = HI;
f2b30012
AC		 2002 HIACCESS = 3;
2003}
2004
2005
2006000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2007"mflo r<RD>"
2008*mipsI:
2009*mipsII:
2010*mipsIII:
2011*mipsIV:
90ad43b2
AC		 2012// start-sanitize-vr5400
2013*vr5400:
2014// end-sanitize-vr5400
f2b30012
AC		 2015// start-sanitize-r5900
2016*r5900:
2017// end-sanitize-r5900
2018*r3900:
2019// start-sanitize-tx19
2020*tx19:
2021// end-sanitize-tx19
2022{
055ee297 2023 GPR[RD] = LO;
f2b30012
AC		 2024 LOACCESS = 3; /* 3rd instruction will be safe */
2025}
2026
2027
2028000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2029"movn r<RD>, r<RS>, r<RT>"
2030*mipsIV:
90ad43b2
AC		 2031// start-sanitize-vr5400
2032*vr5400:
2033// end-sanitize-vr5400
f2b30012
AC		 2034// start-sanitize-r5900
2035*r5900:
2036// end-sanitize-r5900
2037{
055ee297
AC		 2038 if (GPR[RT] != 0)
2039 GPR[RD] = GPR[RS];
f2b30012
AC		 2040}
2041
2042
2043000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2044"movz r<RD>, r<RS>, r<RT>"
2045*mipsIV:
90ad43b2
AC		 2046// start-sanitize-vr5400
2047*vr5400:
2048// end-sanitize-vr5400
f2b30012
AC		 2049// start-sanitize-r5900
2050*r5900:
2051// end-sanitize-r5900
2052{
055ee297
AC		 2053 if (GPR[RT] == 0)
2054 GPR[RD] = GPR[RS];
f2b30012
AC		 2055}
2056
2057
2058000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2059"mthi r<RS>"
2060*mipsI:
2061*mipsII:
2062*mipsIII:
2063*mipsIV:
90ad43b2
AC		 2064// start-sanitize-vr5400
2065*vr5400:
2066// end-sanitize-vr5400
f2b30012
AC		 2067// start-sanitize-r5900
2068*r5900:
2069// end-sanitize-r5900
2070*r3900:
2071// start-sanitize-tx19
2072*tx19:
2073// end-sanitize-tx19
2074{
2075 if (HIACCESS != 0)
055ee297
AC		 2076 sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
2077 HI = GPR[RS];
f2b30012
AC		 2078 HIACCESS = 3; /* 3rd instruction will be safe */
2079}
2080
2081
2082000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2083"mtlo r<RS>"
2084*mipsI:
2085*mipsII:
2086*mipsIII:
2087*mipsIV:
90ad43b2
AC		 2088// start-sanitize-vr5400
2089*vr5400:
2090// end-sanitize-vr5400
f2b30012
AC		 2091// start-sanitize-r5900
2092*r5900:
2093// end-sanitize-r5900
2094*r3900:
2095// start-sanitize-tx19
2096*tx19:
2097// end-sanitize-tx19
2098{
2099 if (LOACCESS != 0)
055ee297
AC		 2100 sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
2101 LO = GPR[RS];
f2b30012
AC		 2102 LOACCESS = 3; /* 3rd instruction will be safe */
2103}
2104
2105
2106000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2107"mult r<RS>, r<RT>"
2108*mipsI:
2109*mipsII:
2110*mipsIII:
2111*mipsIV:
90ad43b2
AC		 2112// start-sanitize-vr5400
2113*vr5400:
2114// end-sanitize-vr5400
f2b30012
AC		 2115// start-sanitize-r5900
2116*r5900:
2117// end-sanitize-r5900
2118*r3900:
2119// start-sanitize-tx19
2120*tx19:
2121// end-sanitize-tx19
2122{
2123 signed64 prod;
2124 CHECKHILO ("Multiplication");
055ee297
AC		 2125 prod = (((signed64)(signed32) GPR[RS])
2126 * ((signed64)(signed32) GPR[RT]));
f2b30012
AC		 2127 LO = EXTEND32 (VL4_8 (prod));
2128 HI = EXTEND32 (VH4_8 (prod));
2129}
2130
2131
2132000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2133"multu r<RS>, r<RT>"
2134*mipsI:
2135*mipsII:
2136*mipsIII:
2137*mipsIV:
90ad43b2
AC		 2138// start-sanitize-vr5400
2139*vr5400:
2140// end-sanitize-vr5400
f2b30012
AC		 2141// start-sanitize-r5900
2142*r5900:
2143// end-sanitize-r5900
2144*r3900:
2145// start-sanitize-tx19
2146*tx19:
2147// end-sanitize-tx19
2148{
2149 unsigned64 prod;
2150 CHECKHILO ("Multiplication");
055ee297
AC		 2151 prod = (((unsigned64)(unsigned32) GPR[RS])
2152 * ((unsigned64)(unsigned32) GPR[RT]));
f2b30012
AC		 2153 LO = EXTEND32 (VL4_8 (prod));
2154 HI = EXTEND32 (VH4_8 (prod));
2155}
2156
2157
2158000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2159"nor r<RD>, r<RS>, r<RT>"
2160*mipsI:
2161*mipsII:
2162*mipsIII:
2163*mipsIV:
90ad43b2
AC		 2164// start-sanitize-vr5400
2165*vr5400:
2166// end-sanitize-vr5400
f2b30012
AC		 2167// start-sanitize-r5900
2168*r5900:
2169// end-sanitize-r5900
2170*r3900:
2171// start-sanitize-tx19
2172*tx19:
2173// end-sanitize-tx19
2174{
055ee297 2175 GPR[RD] = ~ (GPR[RS] | GPR[RT]);
f2b30012
AC		 2176}
2177
2178
2179000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2180"or r<RD>, r<RS>, r<RT>"
2181*mipsI:
2182*mipsII:
2183*mipsIII:
2184*mipsIV:
90ad43b2
AC		 2185// start-sanitize-vr5400
2186*vr5400:
2187// end-sanitize-vr5400
f2b30012
AC		 2188// start-sanitize-r5900
2189*r5900:
2190// end-sanitize-r5900
2191*r3900:
2192// start-sanitize-tx19
2193*tx19:
2194// end-sanitize-tx19
2195{
055ee297 2196 GPR[RD] = (GPR[RS] | GPR[RT]);
f2b30012
AC		 2197}
2198
2199
2200001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
055ee297 2201"ori r<RT>, r<RS>, <IMMEDIATE>"
f2b30012
AC		 2202*mipsI:
2203*mipsII:
2204*mipsIII:
2205*mipsIV:
90ad43b2
AC		 2206// start-sanitize-vr5400
2207*vr5400:
2208// end-sanitize-vr5400
f2b30012
AC		 2209// start-sanitize-r5900
2210*r5900:
2211// end-sanitize-r5900
2212*r3900:
2213// start-sanitize-tx19
2214*tx19:
2215// end-sanitize-tx19
2216{
055ee297 2217 GPR[RT] = (GPR[RS] | IMMEDIATE);
f2b30012
AC		 2218}
2219
2220
2221110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2222*mipsIV:
90ad43b2
AC		 2223// start-sanitize-vr5400
2224*vr5400:
2225// end-sanitize-vr5400
f2b30012
AC		 2226// start-sanitize-r5900
2227*r5900:
2228// end-sanitize-r5900
2229{
2230 unsigned32 instruction = instruction_0;
055ee297
AC		 2231 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2232 int hint = ((instruction >> 16) & 0x0000001F);
2233 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2234 {
49a76833
AC		 2235 address_word vaddr = ((unsigned64)op1 + offset);
2236 address_word paddr;
f2b30012
AC		 2237 int uncached;
2238 {
2239 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2240 Prefetch(uncached,paddr,vaddr,isDATA,hint);
2241 }
2242 }
2243}
2244
2245101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2246"sb r<RT>, <OFFSET>(r<BASE>)"
2247*mipsI:
2248*mipsII:
2249*mipsIII:
2250*mipsIV:
90ad43b2
AC		 2251// start-sanitize-vr5400
2252*vr5400:
2253// end-sanitize-vr5400
f2b30012
AC		 2254// start-sanitize-r5900
2255*r5900:
2256// end-sanitize-r5900
2257*r3900:
2258// start-sanitize-tx19
2259*tx19:
2260// end-sanitize-tx19
2261{
2262 unsigned32 instruction = instruction_0;
055ee297
AC		 2263 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2264 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2265 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2266 {
49a76833
AC		 2267 address_word vaddr = ((unsigned64)op1 + offset);
2268 address_word paddr;
f2b30012
AC		 2269 int uncached;
2270 {
2271 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2272 {
2273 unsigned64 memval = 0;
2274 unsigned64 memval1 = 0;
2275 unsigned64 mask = 0x7;
2276 unsigned int shift = 0;
2277 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2278 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2279 unsigned int byte;
2280 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2281 byte = ((vaddr & mask) ^ (bigend << shift));
2282 memval = ((unsigned64) op2 << (8 * byte));
2283 {
2284 StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
2285 }
2286 }
2287 }
2288 }
2289}
2290
2291
2292111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2293"sc r<RT>, <OFFSET>(r<BASE>)"
2294*mipsII:
2295*mipsIII:
2296*mipsIV:
90ad43b2
AC		 2297// start-sanitize-vr5400
2298*vr5400:
2299// end-sanitize-vr5400
f2b30012
AC		 2300// start-sanitize-r5900
2301*r5900:
2302// end-sanitize-r5900
2303*r3900:
2304// start-sanitize-tx19
2305*tx19:
2306// end-sanitize-tx19
2307{
2308 unsigned32 instruction = instruction_0;
055ee297
AC		 2309 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2310 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2311 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2312 {
49a76833
AC		 2313 address_word vaddr = ((unsigned64)op1 + offset);
2314 address_word paddr;
f2b30012
AC		 2315 int uncached;
2316 if ((vaddr & 3) != 0)
055ee297 2317 SignalExceptionAddressStore();
f2b30012
AC		 2318 else
2319 {
2320 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2321 {
2322 unsigned64 memval = 0;
2323 unsigned64 memval1 = 0;
2324 unsigned64 mask = 0x7;
2325 unsigned int byte;
2326 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2327 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2328 memval = ((unsigned64) op2 << (8 * byte));
2329 if (LLBIT)
2330 {
2331 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2332 }
2333 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2334 }
2335 }
2336 }
2337}
2338
2339
2340111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2341"scd r<RT>, <OFFSET>(r<BASE>)"
2342*mipsIII:
2343*mipsIV:
90ad43b2
AC		 2344// start-sanitize-vr5400
2345*vr5400:
2346// end-sanitize-vr5400
f2b30012
AC		 2347// start-sanitize-r5900
2348*r5900:
2349// end-sanitize-r5900
2350*r3900:
2351// start-sanitize-tx19
2352*tx19:
2353// end-sanitize-tx19
2354{
2355 unsigned32 instruction = instruction_0;
055ee297
AC		 2356 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2357 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2358 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2359 {
49a76833
AC		 2360 address_word vaddr = ((unsigned64)op1 + offset);
2361 address_word paddr;
f2b30012
AC		 2362 int uncached;
2363 if ((vaddr & 7) != 0)
055ee297 2364 SignalExceptionAddressStore();
f2b30012
AC		 2365 else
2366 {
2367 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2368 {
2369 unsigned64 memval = 0;
2370 unsigned64 memval1 = 0;
2371 memval = op2;
2372 if (LLBIT)
2373 {
2374 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2375 }
2376 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2377 }
2378 }
2379 }
2380}
2381
2382
2383111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2384"sd r<RT>, <OFFSET>(r<BASE>)"
2385*mipsIII:
2386*mipsIV:
90ad43b2
AC		 2387// start-sanitize-vr5400
2388*vr5400:
2389// end-sanitize-vr5400
f2b30012
AC		 2390// start-sanitize-r5900
2391*r5900:
2392// end-sanitize-r5900
2393*r3900:
2394// start-sanitize-tx19
2395*tx19:
2396// end-sanitize-tx19
2397{
2398 unsigned32 instruction = instruction_0;
055ee297
AC		 2399 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2400 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2401 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2402 {
49a76833
AC		 2403 address_word vaddr = ((unsigned64)op1 + offset);
2404 address_word paddr;
f2b30012
AC		 2405 int uncached;
2406 if ((vaddr & 7) != 0)
055ee297 2407 SignalExceptionAddressStore();
f2b30012
AC		 2408 else
2409 {
2410 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2411 {
2412 unsigned64 memval = 0;
2413 unsigned64 memval1 = 0;
2414 memval = op2;
2415 {
2416 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2417 }
2418 }
2419 }
2420 }
2421}
2422
2423
49a6eed5 24241111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
f2b30012
AC		 2425"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2426*mipsII:
2427*mipsIII:
2428*mipsIV:
90ad43b2
AC		 2429// start-sanitize-vr5400
2430*vr5400:
2431// end-sanitize-vr5400
f2b30012
AC		 2432// start-sanitize-r5900
2433*r5900:
2434// end-sanitize-r5900
2435*r3900:
2436// start-sanitize-tx19
2437*tx19:
2438// end-sanitize-tx19
2439{
2440 unsigned32 instruction = instruction_0;
055ee297
AC		 2441 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2442 int destreg = ((instruction >> 16) & 0x0000001F);
2443 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2444 {
49a76833
AC		 2445 address_word vaddr = ((unsigned64)op1 + offset);
2446 address_word paddr;
f2b30012
AC		 2447 int uncached;
2448 if ((vaddr & 7) != 0)
055ee297 2449 SignalExceptionAddressStore();
f2b30012
AC		 2450 else
2451 {
2452 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2453 {
2454 unsigned64 memval = 0;
2455 unsigned64 memval1 = 0;
2456 memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
2457 {
2458 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2459 }
2460 }
2461 }
2462 }
2463}
2464
2465
2466101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2467"sdl r<RT>, <OFFSET>(r<BASE>)"
2468*mipsIII:
2469*mipsIV:
90ad43b2
AC		 2470// start-sanitize-vr5400
2471*vr5400:
2472// end-sanitize-vr5400
f2b30012
AC		 2473// start-sanitize-r5900
2474*r5900:
2475// end-sanitize-r5900
2476*r3900:
2477// start-sanitize-tx19
2478*tx19:
2479// end-sanitize-tx19
2480{
2481 unsigned32 instruction = instruction_0;
055ee297
AC		 2482 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2483 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2484 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2485 {
49a76833
AC		 2486 address_word vaddr = ((unsigned64)op1 + offset);
2487 address_word paddr;
f2b30012
AC		 2488 int uncached;
2489 {
2490 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2491 {
2492 unsigned64 memval = 0;
2493 unsigned64 memval1 = 0;
2494 unsigned64 mask = 7;
2495 unsigned int reverse = (ReverseEndian ? mask : 0);
2496 unsigned int bigend = (BigEndianCPU ? mask : 0);
2497 int byte;
2498 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2499 byte = ((vaddr & mask) ^ bigend);
2500 if (!!ByteSwapMem)
2501 paddr &= ~mask;
2502 memval = (op2 >> (8 * (7 - byte)));
2503 StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2504 }
2505 }
2506 }
2507}
2508
2509
2510101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2511"sdr r<RT>, <OFFSET>(r<BASE>)"
2512*mipsIII:
2513*mipsIV:
90ad43b2
AC		 2514// start-sanitize-vr5400
2515*vr5400:
2516// end-sanitize-vr5400
f2b30012
AC		 2517// start-sanitize-r5900
2518*r5900:
2519// end-sanitize-r5900
2520*r3900:
2521// start-sanitize-tx19
2522*tx19:
2523// end-sanitize-tx19
2524{
2525 unsigned32 instruction = instruction_0;
055ee297
AC		 2526 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2527 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2528 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2529 {
49a76833
AC		 2530 address_word vaddr = ((unsigned64)op1 + offset);
2531 address_word paddr;
f2b30012
AC		 2532 int uncached;
2533 {
2534 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2535 {
2536 unsigned64 memval = 0;
2537 unsigned64 memval1 = 0;
2538 unsigned64 mask = 7;
2539 unsigned int reverse = (ReverseEndian ? mask : 0);
2540 unsigned int bigend = (BigEndianCPU ? mask : 0);
2541 int byte;
2542 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2543 byte = ((vaddr & mask) ^ bigend);
2544 if (!ByteSwapMem)
2545 paddr &= ~mask;
2546 memval = ((unsigned64) op2 << (byte * 8));
2547 StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,memval1,paddr,vaddr,isREAL);
2548 }
2549 }
2550 }
2551}
2552
2553
2554101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2555"sh r<RT>, <OFFSET>(r<BASE>)"
2556*mipsI:
2557*mipsII:
2558*mipsIII:
2559*mipsIV:
90ad43b2
AC		 2560// start-sanitize-vr5400
2561*vr5400:
2562// end-sanitize-vr5400
f2b30012
AC		 2563// start-sanitize-r5900
2564*r5900:
2565// end-sanitize-r5900
2566*r3900:
2567// start-sanitize-tx19
2568*tx19:
2569// end-sanitize-tx19
2570{
2571 unsigned32 instruction = instruction_0;
055ee297
AC		 2572 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2573 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2574 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2575 {
49a76833
AC		 2576 address_word vaddr = ((unsigned64)op1 + offset);
2577 address_word paddr;
f2b30012
AC		 2578 int uncached;
2579 if ((vaddr & 1) != 0)
055ee297 2580 SignalExceptionAddressStore();
f2b30012
AC		 2581 else
2582 {
2583 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2584 {
2585 unsigned64 memval = 0;
2586 unsigned64 memval1 = 0;
2587 unsigned64 mask = 0x7;
2588 unsigned int shift = 1;
2589 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2590 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2591 unsigned int byte;
2592 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2593 byte = ((vaddr & mask) ^ (bigend << shift));
2594 memval = ((unsigned64) op2 << (8 * byte));
2595 {
2596 StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
2597 }
2598 }
2599 }
2600 }
2601}
2602
2603
055ee297
AC		 260400000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2605"sll r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 2606*mipsI:
2607*mipsII:
2608*mipsIII:
2609*mipsIV:
90ad43b2
AC		 2610// start-sanitize-vr5400
2611*vr5400:
2612// end-sanitize-vr5400
f2b30012
AC		 2613// start-sanitize-r5900
2614*r5900:
2615// end-sanitize-r5900
2616*r3900:
2617// start-sanitize-tx19
2618*tx19:
2619// end-sanitize-tx19
2620{
055ee297
AC		 2621 int s = SHIFT;
2622 unsigned32 temp = (GPR[RT] << s);
2623 GPR[RD] = EXTEND32 (temp);
f2b30012
AC		 2624}
2625
2626
055ee297 2627000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
f2b30012
AC		 2628"sllv r<RD>, r<RT>, r<RS>"
2629*mipsI:
2630*mipsII:
2631*mipsIII:
2632*mipsIV:
90ad43b2
AC		 2633// start-sanitize-vr5400
2634*vr5400:
2635// end-sanitize-vr5400
f2b30012
AC		 2636// start-sanitize-r5900
2637*r5900:
2638// end-sanitize-r5900
2639*r3900:
2640// start-sanitize-tx19
2641*tx19:
2642// end-sanitize-tx19
2643{
055ee297
AC		 2644 int s = MASKED (GPR[RS], 4, 0);
2645 unsigned32 temp = (GPR[RT] << s);
2646 GPR[RD] = EXTEND32 (temp);
f2b30012
AC		 2647}
2648
2649
2650000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2651"slt r<RD>, r<RS>, r<RT>"
2652*mipsI:
2653*mipsII:
2654*mipsIII:
2655*mipsIV:
90ad43b2
AC		 2656// start-sanitize-vr5400
2657*vr5400:
2658// end-sanitize-vr5400
f2b30012
AC		 2659// start-sanitize-r5900
2660*r5900:
2661// end-sanitize-r5900
2662*r3900:
2663// start-sanitize-tx19
2664*tx19:
2665// end-sanitize-tx19
2666{
055ee297 2667 GPR[RD] = (GPR[RS] < GPR[RT]);
f2b30012
AC		 2668}
2669
2670
2671001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
055ee297 2672"slti r<RT>, r<RS>, <IMMEDIATE>"
f2b30012
AC		 2673*mipsI:
2674*mipsII:
2675*mipsIII:
2676*mipsIV:
90ad43b2
AC		 2677// start-sanitize-vr5400
2678*vr5400:
2679// end-sanitize-vr5400
f2b30012
AC		 2680// start-sanitize-r5900
2681*r5900:
2682// end-sanitize-r5900
2683*r3900:
2684// start-sanitize-tx19
2685*tx19:
2686// end-sanitize-tx19
2687{
055ee297 2688 GPR[RT] = (GPR[RS] < EXTEND16 (IMMEDIATE));
f2b30012
AC		 2689}
2690
2691
2692001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
055ee297 2693"sltiu r<RT>, r<RS>, <IMMEDIATE>"
f2b30012
AC		 2694*mipsI:
2695*mipsII:
2696*mipsIII:
2697*mipsIV:
90ad43b2
AC		 2698// start-sanitize-vr5400
2699*vr5400:
2700// end-sanitize-vr5400
f2b30012
AC		 2701// start-sanitize-r5900
2702*r5900:
2703// end-sanitize-r5900
2704*r3900:
2705// start-sanitize-tx19
2706*tx19:
2707// end-sanitize-tx19
2708{
055ee297 2709 GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
f2b30012
AC		 2710}
2711
2712000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2713"sltu r<RD>, r<RS>, r<RT>"
2714*mipsI:
2715*mipsII:
2716*mipsIII:
2717*mipsIV:
90ad43b2
AC		 2718// start-sanitize-vr5400
2719*vr5400:
2720// end-sanitize-vr5400
f2b30012
AC		 2721// start-sanitize-r5900
2722*r5900:
2723// end-sanitize-r5900
2724*r3900:
2725// start-sanitize-tx19
2726*tx19:
2727// end-sanitize-tx19
2728{
055ee297 2729 GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
f2b30012
AC		 2730}
2731
2732
055ee297
AC		 2733000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2734"sra r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 2735*mipsI:
2736*mipsII:
2737*mipsIII:
2738*mipsIV:
90ad43b2
AC		 2739// start-sanitize-vr5400
2740*vr5400:
2741// end-sanitize-vr5400
f2b30012
AC		 2742// start-sanitize-r5900
2743*r5900:
2744// end-sanitize-r5900
2745*r3900:
2746// start-sanitize-tx19
2747*tx19:
2748// end-sanitize-tx19
2749{
055ee297
AC		 2750 int s = SHIFT;
2751 signed32 temp = (signed32) GPR[RT] >> s;
2752 GPR[RD] = EXTEND32 (temp);
f2b30012
AC		 2753}
2754
2755
2756000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2757"srav r<RD>, r<RT>, r<RS>"
2758*mipsI:
2759*mipsII:
2760*mipsIII:
2761*mipsIV:
90ad43b2
AC		 2762// start-sanitize-vr5400
2763*vr5400:
2764// end-sanitize-vr5400
f2b30012
AC		 2765// start-sanitize-r5900
2766*r5900:
2767// end-sanitize-r5900
2768*r3900:
2769// start-sanitize-tx19
2770*tx19:
2771// end-sanitize-tx19
2772{
055ee297
AC		 2773 int s = MASKED (GPR[RS], 4, 0);
2774 signed32 temp = (signed32) GPR[RT] >> s;
2775 GPR[RD] = EXTEND32 (temp);
f2b30012
AC		 2776}
2777
2778
055ee297
AC		 2779000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2780"srl r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 2781*mipsI:
2782*mipsII:
2783*mipsIII:
2784*mipsIV:
90ad43b2
AC		 2785// start-sanitize-vr5400
2786*vr5400:
2787// end-sanitize-vr5400
f2b30012
AC		 2788// start-sanitize-r5900
2789*r5900:
2790// end-sanitize-r5900
2791*r3900:
2792// start-sanitize-tx19
2793*tx19:
2794// end-sanitize-tx19
2795{
055ee297
AC		 2796 int s = SHIFT;
2797 unsigned32 temp = (unsigned32) GPR[RT] >> s;
2798 GPR[RD] = EXTEND32 (temp);
f2b30012
AC		 2799}
2800
2801
2802000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2803"srlv r<RD>, r<RT>, r<RS>"
2804*mipsI:
2805*mipsII:
2806*mipsIII:
2807*mipsIV:
90ad43b2
AC		 2808// start-sanitize-vr5400
2809*vr5400:
2810// end-sanitize-vr5400
f2b30012
AC		 2811// start-sanitize-r5900
2812*r5900:
2813// end-sanitize-r5900
2814*r3900:
2815// start-sanitize-tx19
2816*tx19:
2817// end-sanitize-tx19
2818{
055ee297
AC		 2819 int s = MASKED (GPR[RS], 4, 0);
2820 unsigned32 temp = (unsigned32) GPR[RT] >> s;
2821 GPR[RD] = EXTEND32 (temp);
f2b30012
AC		 2822}
2823
2824
2825000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2826"sub r<RD>, r<RS>, r<RT>"
2827*mipsI:
2828*mipsII:
2829*mipsIII:
2830*mipsIV:
90ad43b2
AC		 2831// start-sanitize-vr5400
2832*vr5400:
2833// end-sanitize-vr5400
f2b30012
AC		 2834// start-sanitize-r5900
2835*r5900:
2836// end-sanitize-r5900
2837*r3900:
2838// start-sanitize-tx19
2839*tx19:
2840// end-sanitize-tx19
2841{
055ee297
AC		 2842 ALU32_BEGIN (GPR[RS]);
2843 ALU32_SUB (GPR[RT]);
2844 ALU32_END (GPR[RD]);
f2b30012
AC		 2845}
2846
2847
2848000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2849"subu r<RD>, r<RS>, r<RT>"
2850*mipsI:
2851*mipsII:
2852*mipsIII:
2853*mipsIV:
90ad43b2
AC		 2854// start-sanitize-vr5400
2855*vr5400:
2856// end-sanitize-vr5400
f2b30012
AC		 2857// start-sanitize-r5900
2858*r5900:
2859// end-sanitize-r5900
2860*r3900:
2861// start-sanitize-tx19
2862*tx19:
2863// end-sanitize-tx19
2864{
055ee297 2865 GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
f2b30012
AC		 2866}
2867
2868
2869101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2870"sw r<RT>, <OFFSET>(r<BASE>)"
2871*mipsI:
2872*mipsII:
2873*mipsIII:
2874*mipsIV:
90ad43b2
AC		 2875// start-sanitize-vr5400
2876*vr5400:
2877// end-sanitize-vr5400
f2b30012
AC		 2878// start-sanitize-r5900
2879*r5900:
2880// end-sanitize-r5900
2881*r3900:
2882// start-sanitize-tx19
2883*tx19:
2884// end-sanitize-tx19
2885{
2886 unsigned32 instruction = instruction_0;
055ee297
AC		 2887 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2888 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2889 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2890 {
49a76833
AC		 2891 address_word vaddr = ((unsigned64)op1 + offset);
2892 address_word paddr;
f2b30012
AC		 2893 int uncached;
2894 if ((vaddr & 3) != 0)
055ee297 2895 SignalExceptionAddressStore();
f2b30012
AC		 2896 else
2897 {
2898 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2899 {
2900 unsigned64 memval = 0;
2901 unsigned64 memval1 = 0;
2902 unsigned64 mask = 0x7;
2903 unsigned int byte;
2904 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2905 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2906 memval = ((unsigned64) op2 << (8 * byte));
2907 {
2908 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2909 }
2910 }
2911 }
2912 }
2913}
2914
2915
085c1cb9 29161110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
f2b30012
AC		 2917"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2918*mipsI:
2919*mipsII:
2920*mipsIII:
2921*mipsIV:
90ad43b2
AC		 2922// start-sanitize-vr5400
2923*vr5400:
2924// end-sanitize-vr5400
f2b30012
AC		 2925// start-sanitize-r5900
2926*r5900:
2927// end-sanitize-r5900
2928*r3900:
2929// start-sanitize-tx19
2930*tx19:
2931// end-sanitize-tx19
2932{
2933 unsigned32 instruction = instruction_0;
055ee297
AC		 2934 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2935 int destreg = ((instruction >> 16) & 0x0000001F);
2936 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2937 {
49a76833
AC		 2938 address_word vaddr = ((unsigned64)op1 + offset);
2939 address_word paddr;
f2b30012
AC		 2940 int uncached;
2941 if ((vaddr & 3) != 0)
055ee297 2942 SignalExceptionAddressStore();
f2b30012
AC		 2943 else
2944 {
2945 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2946 {
2947 unsigned64 memval = 0;
2948 unsigned64 memval1 = 0;
2949 unsigned64 mask = 0x7;
2950 unsigned int byte;
2951 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2952 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2953 memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
2954 {
2955 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2956 }
2957 }
2958 }
2959 }
2960}
2961
2962
2963101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2964"swl r<RT>, <OFFSET>(r<BASE>)"
2965*mipsI:
2966*mipsII:
2967*mipsIII:
2968*mipsIV:
90ad43b2
AC		 2969// start-sanitize-vr5400
2970*vr5400:
2971// end-sanitize-vr5400
f2b30012
AC		 2972// start-sanitize-r5900
2973*r5900:
2974// end-sanitize-r5900
2975*r3900:
2976// start-sanitize-tx19
2977*tx19:
2978// end-sanitize-tx19
2979{
2980 unsigned32 instruction = instruction_0;
055ee297
AC		 2981 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2982 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2983 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2984 {
49a76833
AC		 2985 address_word vaddr = ((unsigned64)op1 + offset);
2986 address_word paddr;
f2b30012
AC		 2987 int uncached;
2988 {
2989 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2990 {
2991 unsigned64 memval = 0;
2992 unsigned64 memval1 = 0;
2993 unsigned64 mask = 3;
2994 unsigned int reverse = (ReverseEndian ? mask : 0);
2995 unsigned int bigend = (BigEndianCPU ? mask : 0);
2996 int byte;
2997 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2998 byte = ((vaddr & mask) ^ bigend);
2999 if (!!ByteSwapMem)
3000 paddr &= ~mask;
3001 memval = (op2 >> (8 * (3 - byte)));
3002 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
3003 memval <<= 32;
3004 }
3005 StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
3006 }
3007 }
3008 }
3009}
3010
3011
3012101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3013"swr r<RT>, <OFFSET>(r<BASE>)"
3014*mipsI:
3015*mipsII:
3016*mipsIII:
3017*mipsIV:
90ad43b2
AC		 3018// start-sanitize-vr5400
3019*vr5400:
3020// end-sanitize-vr5400
f2b30012
AC		 3021// start-sanitize-r5900
3022*r5900:
3023// end-sanitize-r5900
3024*r3900:
3025// start-sanitize-tx19
3026*tx19:
3027// end-sanitize-tx19
3028{
3029 unsigned32 instruction = instruction_0;
055ee297
AC		 3030 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3031 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3032 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 3033 {
49a76833
AC		 3034 address_word vaddr = ((unsigned64)op1 + offset);
3035 address_word paddr;
f2b30012
AC		 3036 int uncached;
3037 {
3038 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3039 {
3040 unsigned64 memval = 0;
3041 unsigned64 memval1 = 0;
3042 unsigned64 mask = 3;
3043 unsigned int reverse = (ReverseEndian ? mask : 0);
3044 unsigned int bigend = (BigEndianCPU ? mask : 0);
3045 int byte;
3046 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3047 byte = ((vaddr & mask) ^ bigend);
3048 if (!ByteSwapMem)
3049 paddr &= ~mask;
3050 memval = ((unsigned64) op2 << (byte * 8));
3051 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
3052 memval <<= 32;
3053 }
3054 StoreMemory(uncached,(AccessLength_WORD - byte),memval,memval1,paddr,vaddr,isREAL);
3055 }
3056 }
3057 }
3058}
3059
3060
3061000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3062"sync":STYPE == 0
3063"sync <STYPE>"
3064*mipsII:
3065*mipsIII:
3066*mipsIV:
90ad43b2
AC		 3067// start-sanitize-vr5400
3068*vr5400:
3069// end-sanitize-vr5400
f2b30012
AC		 3070// start-sanitize-r5900
3071*r5900:
3072// end-sanitize-r5900
3073*r3900:
3074// start-sanitize-tx19
3075*tx19:
3076// end-sanitize-tx19
3077{
085c1cb9 3078 SyncOperation (STYPE);
f2b30012
AC		 3079}
3080
3081
3082000000,20.CODE,001100:SPECIAL:32::SYSCALL
3083"syscall <CODE>"
3084*mipsI:
3085*mipsII:
3086*mipsIII:
3087*mipsIV:
90ad43b2
AC		 3088// start-sanitize-vr5400
3089*vr5400:
3090// end-sanitize-vr5400
f2b30012
AC		 3091// start-sanitize-r5900
3092*r5900:
3093// end-sanitize-r5900
3094*r3900:
3095// start-sanitize-tx19
3096*tx19:
3097// end-sanitize-tx19
3098{
055ee297 3099 SignalException(SystemCall, instruction_0);
f2b30012
AC		 3100}
3101
3102
3103000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3104"teq r<RS>, r<RT>"
3105*mipsII:
3106*mipsIII:
3107*mipsIV:
90ad43b2
AC		 3108// start-sanitize-vr5400
3109*vr5400:
3110// end-sanitize-vr5400
f2b30012
AC		 3111// start-sanitize-r5900
3112*r5900:
3113// end-sanitize-r5900
3114*r3900:
3115// start-sanitize-tx19
3116*tx19:
3117// end-sanitize-tx19
3118{
055ee297
AC		 3119 if (GPR[RS] == GPR[RT])
3120 SignalException(Trap, instruction_0);
f2b30012
AC		 3121}
3122
3123
3124000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3125"teqi r<RS>, <IMMEDIATE>"
3126*mipsII:
3127*mipsIII:
3128*mipsIV:
90ad43b2
AC		 3129// start-sanitize-vr5400
3130*vr5400:
3131// end-sanitize-vr5400
f2b30012
AC		 3132// start-sanitize-r5900
3133*r5900:
3134// end-sanitize-r5900
3135*r3900:
3136// start-sanitize-tx19
3137*tx19:
3138// end-sanitize-tx19
3139{
055ee297
AC		 3140 if (GPR[RS] == EXTEND16 (IMMEDIATE))
3141 SignalException(Trap, instruction_0);
f2b30012
AC		 3142}
3143
3144
3145000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3146"tge r<RS>, r<RT>"
3147*mipsII:
3148*mipsIII:
3149*mipsIV:
90ad43b2
AC		 3150// start-sanitize-vr5400
3151*vr5400:
3152// end-sanitize-vr5400
f2b30012
AC		 3153// start-sanitize-r5900
3154*r5900:
3155// end-sanitize-r5900
3156*r3900:
3157// start-sanitize-tx19
3158*tx19:
3159// end-sanitize-tx19
3160{
055ee297
AC		 3161 if (GPR[RS] >= GPR[RT])
3162 SignalException(Trap, instruction_0);
f2b30012
AC		 3163}
3164
3165
3166000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3167"tgei r<RS>, <IMMEDIATE>"
3168*mipsII:
3169*mipsIII:
3170*mipsIV:
90ad43b2
AC		 3171// start-sanitize-vr5400
3172*vr5400:
3173// end-sanitize-vr5400
f2b30012
AC		 3174// start-sanitize-r5900
3175*r5900:
3176// end-sanitize-r5900
3177*r3900:
3178// start-sanitize-tx19
3179*tx19:
3180// end-sanitize-tx19
3181{
055ee297
AC		 3182 if (GPR[RS] >= EXTEND16 (IMMEDIATE))
3183 SignalException(Trap, instruction_0);
f2b30012
AC		 3184}
3185
3186
3187000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3188"tgeiu r<RS>, <IMMEDIATE>"
3189*mipsII:
3190*mipsIII:
3191*mipsIV:
90ad43b2
AC		 3192// start-sanitize-vr5400
3193*vr5400:
3194// end-sanitize-vr5400
f2b30012
AC		 3195// start-sanitize-r5900
3196*r5900:
3197// end-sanitize-r5900
3198*r3900:
3199// start-sanitize-tx19
3200*tx19:
3201// end-sanitize-tx19
3202{
055ee297
AC		 3203 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3204 SignalException(Trap, instruction_0);
f2b30012
AC		 3205}
3206
3207
3208000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3209"tgeu r<RS>, r<RT>"
3210*mipsII:
3211*mipsIII:
3212*mipsIV:
90ad43b2
AC		 3213// start-sanitize-vr5400
3214*vr5400:
3215// end-sanitize-vr5400
f2b30012
AC		 3216// start-sanitize-r5900
3217*r5900:
3218// end-sanitize-r5900
3219*r3900:
3220// start-sanitize-tx19
3221*tx19:
3222// end-sanitize-tx19
3223{
055ee297
AC		 3224 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3225 SignalException(Trap, instruction_0);
f2b30012
AC		 3226}
3227
3228
3229000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3230"tlt r<RS>, r<RT>"
3231*mipsII:
3232*mipsIII:
3233*mipsIV:
90ad43b2
AC		 3234// start-sanitize-vr5400
3235*vr5400:
3236// end-sanitize-vr5400
f2b30012
AC		 3237// start-sanitize-r5900
3238*r5900:
3239// end-sanitize-r5900
3240*r3900:
3241// start-sanitize-tx19
3242*tx19:
3243// end-sanitize-tx19
3244{
055ee297
AC		 3245 if (GPR[RS] < GPR[RT])
3246 SignalException(Trap, instruction_0);
f2b30012
AC		 3247}
3248
3249
3250000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3251"tlti r<RS>, <IMMEDIATE>"
3252*mipsII:
3253*mipsIII:
3254*mipsIV:
90ad43b2
AC		 3255// start-sanitize-vr5400
3256*vr5400:
3257// end-sanitize-vr5400
f2b30012
AC		 3258// start-sanitize-r5900
3259*r5900:
3260// end-sanitize-r5900
3261*r3900:
3262// start-sanitize-tx19
3263*tx19:
3264// end-sanitize-tx19
3265{
055ee297
AC		 3266 if (GPR[RS] < EXTEND16 (IMMEDIATE))
3267 SignalException(Trap, instruction_0);
f2b30012
AC		 3268}
3269
3270
3271000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3272"tltiu r<RS>, <IMMEDIATE>"
3273*mipsII:
3274*mipsIII:
3275*mipsIV:
90ad43b2
AC		 3276// start-sanitize-vr5400
3277*vr5400:
3278// end-sanitize-vr5400
f2b30012
AC		 3279// start-sanitize-r5900
3280*r5900:
3281// end-sanitize-r5900
3282*r3900:
3283// start-sanitize-tx19
3284*tx19:
3285// end-sanitize-tx19
3286{
055ee297
AC		 3287 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3288 SignalException(Trap, instruction_0);
f2b30012
AC		 3289}
3290
3291
3292000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3293"tltu r<RS>, r<RT>"
3294*mipsII:
3295*mipsIII:
3296*mipsIV:
90ad43b2
AC		 3297// start-sanitize-vr5400
3298*vr5400:
3299// end-sanitize-vr5400
f2b30012
AC		 3300// start-sanitize-r5900
3301*r5900:
3302// end-sanitize-r5900
3303*r3900:
3304// start-sanitize-tx19
3305*tx19:
3306// end-sanitize-tx19
3307{
055ee297
AC		 3308 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3309 SignalException(Trap, instruction_0);
f2b30012
AC		 3310}
3311
3312
3313000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3314"tne r<RS>, r<RT>"
3315*mipsII:
3316*mipsIII:
3317*mipsIV:
90ad43b2
AC		 3318// start-sanitize-vr5400
3319*vr5400:
3320// end-sanitize-vr5400
f2b30012
AC		 3321// start-sanitize-r5900
3322*r5900:
3323// end-sanitize-r5900
3324*r3900:
3325// start-sanitize-tx19
3326*tx19:
3327// end-sanitize-tx19
3328{
055ee297
AC		 3329 if (GPR[RS] != GPR[RT])
3330 SignalException(Trap, instruction_0);
f2b30012
AC		 3331}
3332
3333
3334000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3335"tne r<RS>, <IMMEDIATE>"
3336*mipsII:
3337*mipsIII:
3338*mipsIV:
90ad43b2
AC		 3339// start-sanitize-vr5400
3340*vr5400:
3341// end-sanitize-vr5400
f2b30012
AC		 3342// start-sanitize-r5900
3343*r5900:
3344// end-sanitize-r5900
3345*r3900:
3346// start-sanitize-tx19
3347*tx19:
3348// end-sanitize-tx19
3349{
055ee297
AC		 3350 if (GPR[RS] != EXTEND16 (IMMEDIATE))
3351 SignalException(Trap, instruction_0);
f2b30012
AC		 3352}
3353
3354
3355000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3356"xor r<RD>, r<RS>, r<RT>"
3357*mipsI:
3358*mipsII:
3359*mipsIII:
3360*mipsIV:
90ad43b2
AC		 3361// start-sanitize-vr5400
3362*vr5400:
3363// end-sanitize-vr5400
f2b30012
AC		 3364// start-sanitize-r5900
3365*r5900:
3366// end-sanitize-r5900
3367*r3900:
3368// start-sanitize-tx19
3369*tx19:
3370// end-sanitize-tx19
3371{
055ee297 3372 GPR[RD] = GPR[RS] ^ GPR[RT];
f2b30012
AC		 3373}
3374
3375
3376001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
055ee297 3377"xori r<RT>, r<RS>, <IMMEDIATE>"
f2b30012
AC		 3378*mipsI:
3379*mipsII:
3380*mipsIII:
3381*mipsIV:
90ad43b2
AC		 3382// start-sanitize-vr5400
3383*vr5400:
3384// end-sanitize-vr5400
f2b30012
AC		 3385// start-sanitize-r5900
3386*r5900:
3387// end-sanitize-r5900
3388*r3900:
3389// start-sanitize-tx19
3390*tx19:
3391// end-sanitize-tx19
3392{
055ee297 3393 GPR[RT] = GPR[RS] ^ IMMEDIATE;
f2b30012
AC		 3394}
3395
3396\f
3397//
3398// MIPS Architecture:
3399//
3400// FPU Instruction Set (COP1 & COP1X)
3401//
3402
3403
89d09738 3404:%s::::FMT:int fmt
055ee297
AC		 3405{
3406 switch (fmt)
3407 {
3408 case fmt_single: return "s";
3409 case fmt_double: return "d";
3410 case fmt_word: return "w";
3411 case fmt_long: return "l";
3412 default: return "?";
3413 }
3414}
3415
89d09738 3416:%s::::TF:int tf
055ee297
AC		 3417{
3418 if (tf)
3419 return "t";
3420 else
3421 return "f";
3422}
3423
89d09738 3424:%s::::ND:int nd
055ee297
AC		 3425{
3426 if (nd)
3427 return "l";
3428 else
3429 return "";
3430}
3431
89d09738 3432:%s::::COND:int cond
055ee297
AC		 3433{
3434 switch (cond)
3435 {
3436 case 00: return "f";
3437 case 01: return "un";
3438 case 02: return "eq";
3439 case 03: return "ueq";
3440 case 04: return "olt";
3441 case 05: return "ult";
3442 case 06: return "ole";
3443 case 07: return "ule";
3444 case 010: return "sf";
3445 case 011: return "ngle";
3446 case 012: return "seq";
3447 case 013: return "ngl";
3448 case 014: return "lt";
3449 case 015: return "nge";
3450 case 016: return "le";
3451 case 017: return "ngt";
3452 default: return "?";
3453 }
3454}
3455
3456
f2b30012
AC		 3457010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3458"abs.%s<FMT> f<FD>, f<FS>"
3459*mipsI:
3460*mipsII:
3461*mipsIII:
3462*mipsIV:
90ad43b2
AC		 3463// start-sanitize-vr5400
3464*vr5400:
3465// end-sanitize-vr5400
f2b30012
AC		 3466// start-sanitize-r5900
3467*r5900:
3468// end-sanitize-r5900
3469*r3900:
3470// start-sanitize-tx19
3471*tx19:
3472// end-sanitize-tx19
3473{
3474 unsigned32 instruction = instruction_0;
055ee297
AC		 3475 int destreg = ((instruction >> 6) & 0x0000001F);
3476 int fs = ((instruction >> 11) & 0x0000001F);
3477 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3478 {
3479 if ((format != fmt_single) && (format != fmt_double))
3480 SignalException(ReservedInstruction,instruction);
3481 else
3482 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3483 }
3484}
3485
3486
055ee297
AC		 3487
3488
3489010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD
f2b30012
AC		 3490"add.%s<FMT> f<FD>, f<FS>, f<FT>"
3491*mipsI:
3492*mipsII:
3493*mipsIII:
3494*mipsIV:
90ad43b2
AC		 3495// start-sanitize-vr5400
3496*vr5400:
3497// end-sanitize-vr5400
f2b30012
AC		 3498// start-sanitize-r5900
3499*r5900:
3500// end-sanitize-r5900
3501*r3900:
3502// start-sanitize-tx19
3503*tx19:
3504// end-sanitize-tx19
3505{
3506 unsigned32 instruction = instruction_0;
055ee297
AC		 3507 int destreg = ((instruction >> 6) & 0x0000001F);
3508 int fs = ((instruction >> 11) & 0x0000001F);
3509 int ft = ((instruction >> 16) & 0x0000001F);
3510 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3511 {
3512 if ((format != fmt_single) && (format != fmt_double))
055ee297 3513 SignalException(ReservedInstruction, instruction);
f2b30012
AC		 3514 else
3515 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3516 }
3517}
3518
3519
3520//
3521// FIXME: This does not correctly resolve mipsI-mipsIV differences.
3522//
3523// BC1F
3524// BC1FL
3525// BC1T
3526// BC1TL
055ee297
AC		 3527010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3528"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3529"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
f2b30012
AC		 3530*mipsI:
3531*mipsII:
3532*mipsIII:
3533*mipsIV:
90ad43b2
AC		 3534// start-sanitize-vr5400
3535*vr5400:
3536// end-sanitize-vr5400
f2b30012
AC		 3537// start-sanitize-r5900
3538*r5900:
3539// end-sanitize-r5900
3540*r3900:
3541// start-sanitize-tx19
3542*tx19:
3543// end-sanitize-tx19
3544{
3545 unsigned32 instruction = instruction_0;
055ee297
AC		 3546 signed_word offset = SIGNEXTEND((signed_word)(((instruction >> 0) & 0x0000FFFF) << 2),18);
3547 int boolean = ((instruction >> 16) & 0x00000001);
3548 int likely = ((instruction >> 17) & 0x00000001);
3549 int condition_code = ((instruction >> 18) & 0x00000007);
f2b30012
AC		 3550 {
3551 if (condition_code != 0)
3552 SignalException(ReservedInstruction,instruction);
3553 else {
3554 int condition = (PREVCOC1() == boolean);
3555 /* NOTE: The branch occurs AFTER the next instruction has been executed */
3556 if (condition) {
49a76833 3557 DELAY_SLOT (PC + offset);
f2b30012
AC		 3558 }
3559 else if (likely) {
49a76833 3560 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 3561 }
3562 }
3563 }
3564}
3565
3566
3567//
3568// FIXME: This does not correctly differentiate between mips*
3569//
3570010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3571"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3572"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3573*mipsI:
3574*mipsII:
3575*mipsIII:
3576*mipsIV:
90ad43b2
AC		 3577// start-sanitize-vr5400
3578*vr5400:
3579// end-sanitize-vr5400
f2b30012
AC		 3580// start-sanitize-r5900
3581*r5900:
3582// end-sanitize-r5900
3583*r3900:
3584// start-sanitize-tx19
3585*tx19:
3586// end-sanitize-tx19
3587{
3588 unsigned32 instruction = instruction_0;
055ee297
AC		 3589 int cmpflags = ((instruction >> 0) & 0x0000000F);
3590 int condition_code = ((instruction >> 8) & 0x00000007);
3591 int fs = ((instruction >> 11) & 0x0000001F);
3592 int ft = ((instruction >> 16) & 0x0000001F);
3593 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3594 if (condition_code != 0)
3595 {
3596 SignalException(ReservedInstruction,instruction);
3597 }
3598 else
3599 {
3600 if ((format != fmt_single) && (format != fmt_double))
3601 SignalException(ReservedInstruction,instruction);
3602 else {
3603 if (condition_code != 0)
3604 SignalException(ReservedInstruction,instruction);
3605 else
3606 {
3607 int ignore = 0;
3608 int less = 0;
3609 int equal = 0;
3610 int unordered = 1;
3611 unsigned64 ofs = ValueFPR(fs,format);
3612 unsigned64 oft = ValueFPR(ft,format);
3613 if (NaN(ofs,format) || NaN(oft,format)) {
3614 if (FCSR & FP_ENABLE(IO)) {
3615 FCSR |= FP_CAUSE(IO);
055ee297 3616 SignalExceptionFPE();
f2b30012
AC		 3617 ignore = 1;
3618 }
3619 } else {
3620 less = Less(ofs,oft,format);
3621 equal = Equal(ofs,oft,format);
3622 unordered = 0;
3623 }
3624 if (!ignore) {
3625 int condition = (((cmpflags & (1 << 2)) && less) || ((cmpflags & (1 << 1)) && equal) || ((cmpflags & (1 << 0)) && unordered));
3626 SETFCC(condition_code,condition);
3627 }
3628 }
3629 }
3630 }
3631}
3632
3633
3634010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3635"ceil.l.%s<FMT> f<FD>, f<FS>"
3636*mipsIII:
3637*mipsIV:
90ad43b2
AC		 3638// start-sanitize-vr5400
3639*vr5400:
3640// end-sanitize-vr5400
f2b30012
AC		 3641// start-sanitize-r5900
3642*r5900:
3643// end-sanitize-r5900
3644*r3900:
3645// start-sanitize-tx19
3646*tx19:
3647// end-sanitize-tx19
3648{
3649 unsigned32 instruction = instruction_0;
055ee297
AC		 3650 int destreg = ((instruction >> 6) & 0x0000001F);
3651 int fs = ((instruction >> 11) & 0x0000001F);
3652 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3653 {
3654 if ((format != fmt_single) && (format != fmt_double))
3655 SignalException(ReservedInstruction,instruction);
3656 else
3657 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3658 }
3659}
3660
3661
3662010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3663*mipsII:
3664*mipsIII:
3665*mipsIV:
90ad43b2
AC		 3666// start-sanitize-vr5400
3667*vr5400:
3668// end-sanitize-vr5400
f2b30012
AC		 3669// start-sanitize-r5900
3670*r5900:
3671// end-sanitize-r5900
3672*r3900:
3673// start-sanitize-tx19
3674*tx19:
3675// end-sanitize-tx19
3676{
3677 unsigned32 instruction = instruction_0;
055ee297
AC		 3678 int destreg = ((instruction >> 6) & 0x0000001F);
3679 int fs = ((instruction >> 11) & 0x0000001F);
3680 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3681 {
3682 if ((format != fmt_single) && (format != fmt_double))
3683 SignalException(ReservedInstruction,instruction);
3684 else
3685 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3686 }
3687}
3688
3689
3690// CFC1
3691// CTC1
369201000100,x,10,kkkkk,vvvvv,00000000000:COP1S:32::CxC1
3693*mipsI:
3694*mipsII:
3695*mipsIII:
3696*mipsIV:
90ad43b2
AC		 3697// start-sanitize-vr5400
3698*vr5400:
3699// end-sanitize-vr5400
f2b30012
AC		 3700// start-sanitize-r5900
3701*r5900:
3702// end-sanitize-r5900
3703*r3900:
3704// start-sanitize-tx19
3705*tx19:
3706// end-sanitize-tx19
3707{
3708 unsigned32 instruction = instruction_0;
055ee297
AC		 3709 int fs = ((instruction >> 11) & 0x0000001F);
3710 int ft = ((instruction >> 16) & 0x0000001F);
3711 int to = ((instruction >> 23) & 0x00000001);
f2b30012
AC		 3712 {
3713 if (to) {
3714 if (fs == 0) {
3715 PENDING_FILL((fs + FCR0IDX),VL4_8(GPR[ft]));
3716 } else if (fs == 31) {
3717 PENDING_FILL((fs + FCR31IDX),VL4_8(GPR[ft]));
3718 } /* else NOP */
3719 PENDING_FILL(COCIDX,0); /* special case */
3720 } else { /* control from */
3721 if (fs == 0) {
3722 PENDING_FILL(ft,SIGNEXTEND(FCR0,32));
3723 } else if (fs == 31) {
3724 PENDING_FILL(ft,SIGNEXTEND(FCR31,32));
3725 } /* else NOP */
3726 }
3727 }
3728}
3729
3730
3731//
3732// FIXME: Does not correctly differentiate between mips*
3733//
3734010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
3735"cvt.d.%s<FMT> f<FD>, f<FS>"
3736*mipsI:
3737*mipsII:
3738*mipsIII:
3739*mipsIV:
90ad43b2
AC		 3740// start-sanitize-vr5400
3741*vr5400:
3742// end-sanitize-vr5400
f2b30012
AC		 3743// start-sanitize-r5900
3744*r5900:
3745// end-sanitize-r5900
3746*r3900:
3747// start-sanitize-tx19
3748*tx19:
3749// end-sanitize-tx19
3750{
3751 unsigned32 instruction = instruction_0;
055ee297
AC		 3752 int destreg = ((instruction >> 6) & 0x0000001F);
3753 int fs = ((instruction >> 11) & 0x0000001F);
3754 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3755 {
3756 if ((format == fmt_double) | 0)
3757 SignalException(ReservedInstruction,instruction);
3758 else
3759 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
3760 }
3761}
3762
3763
3764010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
3765"cvt.l.%s<FMT> f<FD>, f<FS>"
3766*mipsIII:
3767*mipsIV:
90ad43b2
AC		 3768// start-sanitize-vr5400
3769*vr5400:
3770// end-sanitize-vr5400
f2b30012
AC		 3771// start-sanitize-r5900
3772*r5900:
3773// end-sanitize-r5900
3774*r3900:
3775// start-sanitize-tx19
3776*tx19:
3777// end-sanitize-tx19
3778{
3779 unsigned32 instruction = instruction_0;
055ee297
AC		 3780 int destreg = ((instruction >> 6) & 0x0000001F);
3781 int fs = ((instruction >> 11) & 0x0000001F);
3782 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3783 {
3784 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
3785 SignalException(ReservedInstruction,instruction);
3786 else
3787 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
3788 }
3789}
3790
3791
3792//
3793// FIXME: Does not correctly differentiate between mips*
3794//
3795010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
3796"cvt.s.%s<FMT> f<FD>, f<FS>"
3797*mipsI:
3798*mipsII:
3799*mipsIII:
3800*mipsIV:
90ad43b2
AC		 3801// start-sanitize-vr5400
3802*vr5400:
3803// end-sanitize-vr5400
f2b30012
AC		 3804// start-sanitize-r5900
3805*r5900:
3806// end-sanitize-r5900
3807*r3900:
3808// start-sanitize-tx19
3809*tx19:
3810// end-sanitize-tx19
3811{
3812 unsigned32 instruction = instruction_0;
055ee297
AC		 3813 int destreg = ((instruction >> 6) & 0x0000001F);
3814 int fs = ((instruction >> 11) & 0x0000001F);
3815 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3816 {
3817 if ((format == fmt_single) | 0)
3818 SignalException(ReservedInstruction,instruction);
3819 else
3820 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
3821 }
3822}
3823
3824
3825010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
3826"cvt.w.%s<FMT> f<FD>, f<FS>"
3827*mipsI:
3828*mipsII:
3829*mipsIII:
3830*mipsIV:
90ad43b2
AC		 3831// start-sanitize-vr5400
3832*vr5400:
3833// end-sanitize-vr5400
f2b30012
AC		 3834// start-sanitize-r5900
3835*r5900:
3836// end-sanitize-r5900
3837*r3900:
3838// start-sanitize-tx19
3839*tx19:
3840// end-sanitize-tx19
3841{
3842 unsigned32 instruction = instruction_0;
055ee297
AC		 3843 int destreg = ((instruction >> 6) & 0x0000001F);
3844 int fs = ((instruction >> 11) & 0x0000001F);
3845 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3846 {
3847 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
3848 SignalException(ReservedInstruction,instruction);
3849 else
3850 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
3851 }
3852}
3853
3854
3855010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
3856"div.%s<FMT> f<FD>, f<FS>, f<FT>"
3857*mipsI:
3858*mipsII:
3859*mipsIII:
3860*mipsIV:
90ad43b2
AC		 3861// start-sanitize-vr5400
3862*vr5400:
3863// end-sanitize-vr5400
f2b30012
AC		 3864// start-sanitize-r5900
3865*r5900:
3866// end-sanitize-r5900
3867*r3900:
3868// start-sanitize-tx19
3869*tx19:
3870// end-sanitize-tx19
3871{
3872 unsigned32 instruction = instruction_0;
055ee297
AC		 3873 int destreg = ((instruction >> 6) & 0x0000001F);
3874 int fs = ((instruction >> 11) & 0x0000001F);
3875 int ft = ((instruction >> 16) & 0x0000001F);
3876 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3877 {
3878 if ((format != fmt_single) && (format != fmt_double))
3879 SignalException(ReservedInstruction,instruction);
3880 else
3881 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3882 }
3883}
3884
3885
3886// DMFC1
3887// DMTC1
388801000100,x,01,5.FT,vvvvv,00000000000:COP1S:64::DMxC1
3889*mipsIII:
3890*mipsIV:
90ad43b2
AC		 3891// start-sanitize-vr5400
3892*vr5400:
3893// end-sanitize-vr5400
f2b30012
AC		 3894// start-sanitize-r5900
3895*r5900:
3896// end-sanitize-r5900
3897*r3900:
3898// start-sanitize-tx19
3899*tx19:
3900// end-sanitize-tx19
3901{
3902 unsigned32 instruction = instruction_0;
055ee297
AC		 3903 int fs = ((instruction >> 11) & 0x0000001F);
3904 int ft = ((instruction >> 16) & 0x0000001F);
3905 int to = ((instruction >> 23) & 0x00000001);
f2b30012
AC		 3906 {
3907 if (to) {
3908 if (SizeFGR() == 64) {
3909 PENDING_FILL((fs + FGRIDX),GPR[ft]);
3910 } else
3911 if ((fs & 0x1) == 0)
3912 {
3913 PENDING_FILL(((fs + 1) + FGRIDX),VH4_8(GPR[ft]));
3914 PENDING_FILL((fs + FGRIDX),VL4_8(GPR[ft]));
3915 }
3916 } else {
3917 if (SizeFGR() == 64) {
3918 PENDING_FILL(ft,FGR[fs]);
3919 } else
3920 if ((fs & 0x1) == 0) {
3921 PENDING_FILL(ft,(SET64HI(FGR[fs+1]) | FGR[fs]));
3922 } else {
3923 PENDING_FILL(ft,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3924 }
3925 }
3926 }
3927}
3928
3929
3930010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
3931"floor.l.%s<FMT> f<FD>, f<FS>"
3932*mipsIII:
3933*mipsIV:
90ad43b2
AC		 3934// start-sanitize-vr5400
3935*vr5400:
3936// end-sanitize-vr5400
f2b30012
AC		 3937// start-sanitize-r5900
3938*r5900:
3939// end-sanitize-r5900
3940*r3900:
3941// start-sanitize-tx19
3942*tx19:
3943// end-sanitize-tx19
3944{
3945 unsigned32 instruction = instruction_0;
055ee297
AC		 3946 int destreg = ((instruction >> 6) & 0x0000001F);
3947 int fs = ((instruction >> 11) & 0x0000001F);
3948 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3949 {
3950 if ((format != fmt_single) && (format != fmt_double))
3951 SignalException(ReservedInstruction,instruction);
3952 else
3953 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
3954 }
3955}
3956
3957
3958010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
3959"floor.w.%s<FMT> f<FD>, f<FS>"
3960*mipsII:
3961*mipsIII:
3962*mipsIV:
90ad43b2
AC		 3963// start-sanitize-vr5400
3964*vr5400:
3965// end-sanitize-vr5400
f2b30012
AC		 3966// start-sanitize-r5900
3967*r5900:
3968// end-sanitize-r5900
3969*r3900:
3970// start-sanitize-tx19
3971*tx19:
3972// end-sanitize-tx19
3973{
3974 unsigned32 instruction = instruction_0;
055ee297
AC		 3975 int destreg = ((instruction >> 6) & 0x0000001F);
3976 int fs = ((instruction >> 11) & 0x0000001F);
3977 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3978 {
3979 if ((format != fmt_single) && (format != fmt_double))
3980 SignalException(ReservedInstruction,instruction);
3981 else
3982 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
3983 }
3984}
3985
3986
3987// LDC1
3988110101,5.BASE,5.FT,16.OFFSET:COP1:32::LDC1
3989
3990
3991010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
3992"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3993*mipsIV:
90ad43b2
AC		 3994// start-sanitize-vr5400
3995*vr5400:
3996// end-sanitize-vr5400
f2b30012
AC		 3997// start-sanitize-r5900
3998*r5900:
3999// end-sanitize-r5900
4000{
4001 unsigned32 instruction = instruction_0;
055ee297
AC		 4002 int destreg = ((instruction >> 6) & 0x0000001F);
4003 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4004 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 4005 {
49a76833
AC		 4006 address_word vaddr = ((unsigned64)op1 + op2);
4007 address_word paddr;
f2b30012
AC		 4008 int uncached;
4009 if ((vaddr & 7) != 0)
055ee297 4010 SignalExceptionAddressLoad();
f2b30012
AC		 4011 else
4012 {
4013 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4014 {
4015 unsigned64 memval = 0;
4016 unsigned64 memval1 = 0;
f2b30012
AC		 4017 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4018 COP_LD(1,destreg,memval);;
4019 }
4020 }
4021 }
4022}
4023
4024
4025// LWC1
4026110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4027
4028
4029010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4030"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4031*mipsIV:
90ad43b2
AC		 4032// start-sanitize-vr5400
4033*vr5400:
4034// end-sanitize-vr5400
f2b30012
AC		 4035// start-sanitize-r5900
4036*r5900:
4037// end-sanitize-r5900
4038{
4039 unsigned32 instruction = instruction_0;
055ee297
AC		 4040 int destreg = ((instruction >> 6) & 0x0000001F);
4041 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4042 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 4043 {
49a76833
AC		 4044 address_word vaddr = ((unsigned64)op1 + op2);
4045 address_word paddr;
f2b30012
AC		 4046 int uncached;
4047 if ((vaddr & 3) != 0)
055ee297 4048 SignalExceptionAddressLoad();
f2b30012
AC		 4049 else
4050 {
4051 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4052 {
4053 unsigned64 memval = 0;
4054 unsigned64 memval1 = 0;
4055 unsigned64 mask = 0x7;
4056 unsigned int shift = 2;
055ee297
AC		 4057 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4058 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4059 unsigned int byte;
f2b30012
AC		 4060 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4061 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4062 byte = ((vaddr & mask) ^ (bigend << shift));
4063 COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
4064 }
4065 }
4066 }
4067}
4068
4069
4070
4071//
4072// FIXME: Not correct for mips*
4073//
4074010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D
4075"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4076*mipsIV:
90ad43b2
AC		 4077// start-sanitize-vr5400
4078*vr5400:
4079// end-sanitize-vr5400
f2b30012
AC		 4080// start-sanitize-r5900
4081*r5900:
4082// end-sanitize-r5900
4083{
4084 unsigned32 instruction = instruction_0;
055ee297
AC		 4085 int destreg = ((instruction >> 6) & 0x0000001F);
4086 int fs = ((instruction >> 11) & 0x0000001F);
4087 int ft = ((instruction >> 16) & 0x0000001F);
4088 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4089 {
4090 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4091 }
4092}
4093
4094
4095010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S
4096"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4097*mipsIV:
90ad43b2
AC		 4098// start-sanitize-vr5400
4099*vr5400:
4100// end-sanitize-vr5400
f2b30012
AC		 4101// start-sanitize-r5900
4102*r5900:
4103// end-sanitize-r5900
4104{
4105 unsigned32 instruction = instruction_0;
055ee297
AC		 4106 int destreg = ((instruction >> 6) & 0x0000001F);
4107 int fs = ((instruction >> 11) & 0x0000001F);
4108 int ft = ((instruction >> 16) & 0x0000001F);
4109 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4110 {
4111 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4112 }
4113}
4114
4115
4116// MFC1
4117010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
055ee297 4118"m<X>c1 r<RT>, f<FS>"
f2b30012
AC		 4119*mipsI:
4120*mipsII:
4121*mipsIII:
4122*mipsIV:
90ad43b2
AC		 4123// start-sanitize-vr5400
4124*vr5400:
4125// end-sanitize-vr5400
f2b30012
AC		 4126// start-sanitize-r5900
4127*r5900:
4128// end-sanitize-r5900
4129*r3900:
4130// start-sanitize-tx19
4131*tx19:
4132// end-sanitize-tx19
4133{
4134 unsigned32 instruction = instruction_0;
055ee297
AC		 4135 int fs = ((instruction >> 11) & 0x0000001F);
4136 int ft = ((instruction >> 16) & 0x0000001F);
4137 int to = ((instruction >> 23) & 0x00000001);
f2b30012
AC		 4138 {
4139 if (to) {
4140 if (SizeFGR() == 64) {
055ee297 4141 PENDING_FILL ((fs + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[ft])));
f2b30012 4142 } else {
055ee297 4143 PENDING_FILL ((fs + FGRIDX), VL4_8(GPR[ft]));
f2b30012
AC		 4144 }
4145 } else {
055ee297 4146 PENDING_FILL (ft, SIGNEXTEND(FGR[fs],32));
f2b30012
AC		 4147 }
4148 }
4149}
4150
4151
4152010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4153"mov.%s<FMT> f<FD>, f<FS>"
4154*mipsI:
4155*mipsII:
4156*mipsIII:
4157*mipsIV:
90ad43b2
AC		 4158// start-sanitize-vr5400
4159*vr5400:
4160// end-sanitize-vr5400
f2b30012
AC		 4161// start-sanitize-r5900
4162*r5900:
4163// end-sanitize-r5900
4164*r3900:
4165// start-sanitize-tx19
4166*tx19:
4167// end-sanitize-tx19
4168{
4169 unsigned32 instruction = instruction_0;
055ee297
AC		 4170 int destreg = ((instruction >> 6) & 0x0000001F);
4171 int fs = ((instruction >> 11) & 0x0000001F);
4172 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4173 {
4174 StoreFPR(destreg,format,ValueFPR(fs,format));
4175 }
4176}
4177
4178
4179// MOVF
4180000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
055ee297 4181"mov%s<TF> r<RD>, r<RS>, <CC>"
f2b30012 4182*mipsIV:
90ad43b2
AC		 4183// start-sanitize-vr5400
4184*vr5400:
4185// end-sanitize-vr5400
f2b30012
AC		 4186// start-sanitize-r5900
4187*r5900:
4188// end-sanitize-r5900
4189{
055ee297
AC		 4190 if (GETFCC(CC) == TF)
4191 GPR[RD] = GPR[RS];
f2b30012
AC		 4192}
4193
4194
4195// MOVF.fmt
4196010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
055ee297 4197"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
f2b30012 4198*mipsIV:
90ad43b2
AC		 4199// start-sanitize-vr5400
4200*vr5400:
4201// end-sanitize-vr5400
f2b30012
AC		 4202// start-sanitize-r5900
4203*r5900:
4204// end-sanitize-r5900
4205{
4206 unsigned32 instruction = instruction_0;
055ee297 4207 int format = ((instruction >> 21) & 0x00000007);
f2b30012 4208 {
055ee297
AC		 4209 if (GETFCC(CC) == TF)
4210 StoreFPR (FD, format, ValueFPR (FS, format));
f2b30012 4211 else
055ee297 4212 StoreFPR (FD, format, ValueFPR (FD, format));
f2b30012
AC		 4213 }
4214}
4215
4216
4217010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4218*mipsIV:
90ad43b2
AC		 4219// start-sanitize-vr5400
4220*vr5400:
4221// end-sanitize-vr5400
f2b30012
AC		 4222// start-sanitize-r5900
4223*r5900:
4224// end-sanitize-r5900
4225{
4226 unsigned32 instruction = instruction_0;
055ee297
AC		 4227 int destreg = ((instruction >> 6) & 0x0000001F);
4228 int fs = ((instruction >> 11) & 0x0000001F);
4229 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4230 {
4231 StoreFPR(destreg,format,ValueFPR(fs,format));
4232 }
4233}
4234
4235
4236// MOVT see MOVtf
4237
4238
4239// MOVT.fmt see MOVtf.fmt
4240
4241
4242
4243010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4244"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4245*mipsIV:
90ad43b2
AC		 4246// start-sanitize-vr5400
4247*vr5400:
4248// end-sanitize-vr5400
f2b30012
AC		 4249// start-sanitize-r5900
4250*r5900:
4251// end-sanitize-r5900
4252{
4253 unsigned32 instruction = instruction_0;
055ee297
AC		 4254 int destreg = ((instruction >> 6) & 0x0000001F);
4255 int fs = ((instruction >> 11) & 0x0000001F);
4256 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4257 {
4258 StoreFPR(destreg,format,ValueFPR(fs,format));
4259 }
4260}
4261
4262
4263// MSUB.fmt
4264010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4265"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4266*mipsIV:
90ad43b2
AC		 4267// start-sanitize-vr5400
4268*vr5400:
4269// end-sanitize-vr5400
f2b30012
AC		 4270// start-sanitize-r5900
4271*r5900:
4272// end-sanitize-r5900
4273{
4274 unsigned32 instruction = instruction_0;
055ee297
AC		 4275 int destreg = ((instruction >> 6) & 0x0000001F);
4276 int fs = ((instruction >> 11) & 0x0000001F);
4277 int ft = ((instruction >> 16) & 0x0000001F);
4278 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4279 {
4280 StoreFPR(destreg,fmt_double,(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4281 }
4282}
4283
4284
4285// MSUB.fmt
055ee297 4286010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
f2b30012
AC		 4287"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4288*mipsIV:
90ad43b2
AC		 4289// start-sanitize-vr5400
4290*vr5400:
4291// end-sanitize-vr5400
f2b30012
AC		 4292// start-sanitize-r5900
4293*r5900:
4294// end-sanitize-r5900
4295{
4296 unsigned32 instruction = instruction_0;
055ee297
AC		 4297 int destreg = ((instruction >> 6) & 0x0000001F);
4298 int fs = ((instruction >> 11) & 0x0000001F);
4299 int ft = ((instruction >> 16) & 0x0000001F);
4300 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4301 {
4302 StoreFPR(destreg,fmt_single,(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4303 }
4304}
4305
4306
4307// MTC1 see MxC1
4308
4309
4310010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4311"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4312*mipsI:
4313*mipsII:
4314*mipsIII:
4315*mipsIV:
90ad43b2
AC		 4316// start-sanitize-vr5400
4317*vr5400:
4318// end-sanitize-vr5400
f2b30012
AC		 4319// start-sanitize-r5900
4320*r5900:
4321// end-sanitize-r5900
4322*r3900:
4323// start-sanitize-tx19
4324*tx19:
4325// end-sanitize-tx19
4326{
4327 unsigned32 instruction = instruction_0;
055ee297
AC		 4328 int destreg = ((instruction >> 6) & 0x0000001F);
4329 int fs = ((instruction >> 11) & 0x0000001F);
4330 int ft = ((instruction >> 16) & 0x0000001F);
4331 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4332 {
4333 if ((format != fmt_single) && (format != fmt_double))
4334 SignalException(ReservedInstruction,instruction);
4335 else
4336 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4337 }
4338}
4339
4340
4341010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4342"neg.%s<FMT> f<FD>, f<FS>"
4343*mipsI:
4344*mipsII:
4345*mipsIII:
4346*mipsIV:
90ad43b2
AC		 4347// start-sanitize-vr5400
4348*vr5400:
4349// end-sanitize-vr5400
f2b30012
AC		 4350// start-sanitize-r5900
4351*r5900:
4352// end-sanitize-r5900
4353*r3900:
4354// start-sanitize-tx19
4355*tx19:
4356// end-sanitize-tx19
4357{
4358 unsigned32 instruction = instruction_0;
055ee297
AC		 4359 int destreg = ((instruction >> 6) & 0x0000001F);
4360 int fs = ((instruction >> 11) & 0x0000001F);
4361 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4362 {
4363 if ((format != fmt_single) && (format != fmt_double))
4364 SignalException(ReservedInstruction,instruction);
4365 else
4366 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4367 }
4368}
4369
4370
4371// NMADD.fmt
4372010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4373"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4374*mipsIV:
90ad43b2
AC		 4375// start-sanitize-vr5400
4376*vr5400:
4377// end-sanitize-vr5400
f2b30012
AC		 4378{
4379 unsigned32 instruction = instruction_0;
055ee297
AC		 4380 int destreg = ((instruction >> 6) & 0x0000001F);
4381 int fs = ((instruction >> 11) & 0x0000001F);
4382 int ft = ((instruction >> 16) & 0x0000001F);
4383 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4384 {
4385 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4386 }
4387}
4388
4389
4390// NMADD.fmt
4391010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4392"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4393*mipsIV:
90ad43b2
AC		 4394// start-sanitize-vr5400
4395*vr5400:
4396// end-sanitize-vr5400
f2b30012
AC		 4397{
4398 unsigned32 instruction = instruction_0;
055ee297
AC		 4399 int destreg = ((instruction >> 6) & 0x0000001F);
4400 int fs = ((instruction >> 11) & 0x0000001F);
4401 int ft = ((instruction >> 16) & 0x0000001F);
4402 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4403 {
4404 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4405 }
4406}
4407
4408
4409// NMSUB.fmt
055ee297 4410010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
f2b30012
AC		 4411"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4412*mipsIV:
90ad43b2
AC		 4413// start-sanitize-vr5400
4414*vr5400:
4415// end-sanitize-vr5400
f2b30012
AC		 4416{
4417 unsigned32 instruction = instruction_0;
055ee297
AC		 4418 int destreg = ((instruction >> 6) & 0x0000001F);
4419 int fs = ((instruction >> 11) & 0x0000001F);
4420 int ft = ((instruction >> 16) & 0x0000001F);
4421 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4422 {
4423 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4424 }
4425}
4426
4427
4428// NMSUB.fmt
055ee297 4429010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
f2b30012
AC		 4430"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4431*mipsIV:
90ad43b2
AC		 4432// start-sanitize-vr5400
4433*vr5400:
4434// end-sanitize-vr5400
f2b30012
AC		 4435{
4436 unsigned32 instruction = instruction_0;
055ee297
AC		 4437 int destreg = ((instruction >> 6) & 0x0000001F);
4438 int fs = ((instruction >> 11) & 0x0000001F);
4439 int ft = ((instruction >> 16) & 0x0000001F);
4440 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4441 {
4442 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4443 }
4444}
4445
4446
4447010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
49a6eed5 4448"prefx <HINT>, r<INDEX>(r<BASE>)"
f2b30012 4449*mipsIV:
90ad43b2
AC		 4450// start-sanitize-vr5400
4451*vr5400:
4452// end-sanitize-vr5400
f2b30012
AC		 4453{
4454 unsigned32 instruction = instruction_0;
055ee297
AC		 4455 int fs = ((instruction >> 11) & 0x0000001F);
4456 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4457 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 4458 {
49a76833
AC		 4459 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4460 address_word paddr;
f2b30012
AC		 4461 int uncached;
4462 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4463 Prefetch(uncached,paddr,vaddr,isDATA,fs);
4464 }
4465}
4466
4467010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4468*mipsIV:
4469"recip.%s<FMT> f<FD>, f<FS>"
90ad43b2
AC		 4470// start-sanitize-vr5400
4471*vr5400:
4472// end-sanitize-vr5400
f2b30012
AC		 4473{
4474 unsigned32 instruction = instruction_0;
055ee297
AC		 4475 int destreg = ((instruction >> 6) & 0x0000001F);
4476 int fs = ((instruction >> 11) & 0x0000001F);
4477 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4478 {
4479 if ((format != fmt_single) && (format != fmt_double))
4480 SignalException(ReservedInstruction,instruction);
4481 else
4482 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4483 }
4484}
4485
4486
4487010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
49a6eed5 4488"round.l.%s<FMT> f<FD>, f<FS>"
f2b30012
AC		 4489*mipsIII:
4490*mipsIV:
90ad43b2
AC		 4491// start-sanitize-vr5400
4492*vr5400:
4493// end-sanitize-vr5400
f2b30012
AC		 4494// start-sanitize-r5900
4495*r5900:
4496// end-sanitize-r5900
4497*r3900:
4498// start-sanitize-tx19
4499*tx19:
4500// end-sanitize-tx19
4501{
4502 unsigned32 instruction = instruction_0;
055ee297
AC		 4503 int destreg = ((instruction >> 6) & 0x0000001F);
4504 int fs = ((instruction >> 11) & 0x0000001F);
4505 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4506 {
4507 if ((format != fmt_single) && (format != fmt_double))
4508 SignalException(ReservedInstruction,instruction);
4509 else
4510 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4511 }
4512}
4513
4514
4515010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
49a6eed5 4516"round.w.%s<FMT> f<FD>, f<FS>"
f2b30012
AC		 4517*mipsII:
4518*mipsIII:
4519*mipsIV:
90ad43b2
AC		 4520// start-sanitize-vr5400
4521*vr5400:
4522// end-sanitize-vr5400
f2b30012
AC		 4523// start-sanitize-r5900
4524*r5900:
4525// end-sanitize-r5900
4526*r3900:
4527// start-sanitize-tx19
4528*tx19:
4529// end-sanitize-tx19
4530{
4531 unsigned32 instruction = instruction_0;
055ee297
AC		 4532 int destreg = ((instruction >> 6) & 0x0000001F);
4533 int fs = ((instruction >> 11) & 0x0000001F);
4534 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4535 {
4536 if ((format != fmt_single) && (format != fmt_double))
4537 SignalException(ReservedInstruction,instruction);
4538 else
4539 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4540 }
4541}
4542
4543
4544010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4545*mipsIV:
4546"rsqrt.%s<FMT> f<FD>, f<FS>"
90ad43b2
AC		 4547// start-sanitize-vr5400
4548*vr5400:
4549// end-sanitize-vr5400
f2b30012
AC		 4550{
4551 unsigned32 instruction = instruction_0;
055ee297
AC		 4552 int destreg = ((instruction >> 6) & 0x0000001F);
4553 int fs = ((instruction >> 11) & 0x0000001F);
4554 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4555 {
4556 if ((format != fmt_single) && (format != fmt_double))
4557 SignalException(ReservedInstruction,instruction);
4558 else
085c1cb9 4559 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
f2b30012
AC		 4560 }
4561}
4562
4563
4564// SDC1
4565
4566
4567010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
4568*mipsIV:
90ad43b2
AC		 4569// start-sanitize-vr5400
4570*vr5400:
4571// end-sanitize-vr5400
f2b30012
AC		 4572// start-sanitize-r5900
4573*r5900:
4574// end-sanitize-r5900
4575{
4576 unsigned32 instruction = instruction_0;
055ee297
AC		 4577 int fs = ((instruction >> 11) & 0x0000001F);
4578 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4579 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 4580 {
49a76833
AC		 4581 address_word vaddr = ((unsigned64)op1 + op2);
4582 address_word paddr;
f2b30012
AC		 4583 int uncached;
4584 if ((vaddr & 7) != 0)
055ee297 4585 SignalExceptionAddressStore();
f2b30012
AC		 4586 else
4587 {
4588 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4589 {
4590 unsigned64 memval = 0;
4591 unsigned64 memval1 = 0;
4592 memval = (unsigned64)COP_SD(1,fs);
4593 {
4594 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
4595 }
4596 }
4597 }
4598 }
4599}
4600
4601
4602010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
4603"sqrt.%s<FMT> f<FD>, f<FS>"
4604*mipsII:
4605*mipsIII:
4606*mipsIV:
90ad43b2
AC		 4607// start-sanitize-vr5400
4608*vr5400:
4609// end-sanitize-vr5400
f2b30012
AC		 4610// start-sanitize-r5900
4611*r5900:
4612// end-sanitize-r5900
4613*r3900:
4614// start-sanitize-tx19
4615*tx19:
4616// end-sanitize-tx19
4617{
4618 unsigned32 instruction = instruction_0;
055ee297
AC		 4619 int destreg = ((instruction >> 6) & 0x0000001F);
4620 int fs = ((instruction >> 11) & 0x0000001F);
4621 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4622 {
4623 if ((format != fmt_single) && (format != fmt_double))
4624 SignalException(ReservedInstruction,instruction);
4625 else
4626 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4627 }
4628}
4629
4630
4631010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
4632"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4633*mipsI:
4634*mipsII:
4635*mipsIII:
4636*mipsIV:
90ad43b2
AC		 4637// start-sanitize-vr5400
4638*vr5400:
4639// end-sanitize-vr5400
f2b30012
AC		 4640// start-sanitize-r5900
4641*r5900:
4642// end-sanitize-r5900
4643*r3900:
4644// start-sanitize-tx19
4645*tx19:
4646// end-sanitize-tx19
4647{
4648 unsigned32 instruction = instruction_0;
055ee297
AC		 4649 int destreg = ((instruction >> 6) & 0x0000001F);
4650 int fs = ((instruction >> 11) & 0x0000001F);
4651 int ft = ((instruction >> 16) & 0x0000001F);
4652 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4653 {
4654 if ((format != fmt_single) && (format != fmt_double))
4655 SignalException(ReservedInstruction,instruction);
4656 else
4657 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4658 }
4659}
4660
4661
4662// SWC1
4663
4664
085c1cb9
AC		 4665010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
4666"swxc1 f<FS>, r<INDEX>(r<BASE>)"
f2b30012 4667*mipsIV:
90ad43b2
AC		 4668// start-sanitize-vr5400
4669*vr5400:
4670// end-sanitize-vr5400
f2b30012
AC		 4671// start-sanitize-r5900
4672*r5900:
4673// end-sanitize-r5900
4674{
4675 unsigned32 instruction = instruction_0;
055ee297
AC		 4676 int fs = ((instruction >> 11) & 0x0000001F);
4677 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4678 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 4679 {
49a76833
AC		 4680 address_word vaddr = ((unsigned64)op1 + op2);
4681 address_word paddr;
f2b30012
AC		 4682 int uncached;
4683 if ((vaddr & 3) != 0)
055ee297 4684 SignalExceptionAddressStore();
f2b30012
AC		 4685 else
4686 {
4687 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4688 {
4689 unsigned64 memval = 0;
4690 unsigned64 memval1 = 0;
4691 unsigned64 mask = 0x7;
4692 unsigned int byte;
4693 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4694 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4695 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
4696 {
4697 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4698 }
4699 }
4700 }
4701 }
4702}
4703
4704
4705010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
4706"trunc.l.%s<FMT> f<FD>, f<FS>"
4707*mipsIII:
4708*mipsIV:
90ad43b2
AC		 4709// start-sanitize-vr5400
4710*vr5400:
4711// end-sanitize-vr5400
f2b30012
AC		 4712// start-sanitize-r5900
4713*r5900:
4714// end-sanitize-r5900
4715*r3900:
4716// start-sanitize-tx19
4717*tx19:
4718// end-sanitize-tx19
4719{
4720 unsigned32 instruction = instruction_0;
055ee297
AC		 4721 int destreg = ((instruction >> 6) & 0x0000001F);
4722 int fs = ((instruction >> 11) & 0x0000001F);
4723 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4724 {
4725 if ((format != fmt_single) && (format != fmt_double))
4726 SignalException(ReservedInstruction,instruction);
4727 else
4728 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
4729 }
4730}
4731
4732
4733010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
4734"trunc.w.%s<FMT> f<FD>, f<FS>"
4735*mipsII:
4736*mipsIII:
4737*mipsIV:
90ad43b2
AC		 4738// start-sanitize-vr5400
4739*vr5400:
4740// end-sanitize-vr5400
f2b30012
AC		 4741// start-sanitize-r5900
4742*r5900:
4743// end-sanitize-r5900
4744*r3900:
4745// start-sanitize-tx19
4746*tx19:
4747// end-sanitize-tx19
4748{
4749 unsigned32 instruction = instruction_0;
055ee297
AC		 4750 int destreg = ((instruction >> 6) & 0x0000001F);
4751 int fs = ((instruction >> 11) & 0x0000001F);
4752 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4753 {
4754 if ((format != fmt_single) && (format != fmt_double))
4755 SignalException(ReservedInstruction,instruction);
4756 else
4757 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
4758 }
4759}
4760
4761\f
4762//
4763// MIPS Architecture:
4764//
4765// System Control Instruction Set (COP0)
4766//
4767
4768
4769010000,01000,00000,16.OFFSET:COP0:32::BC0F
4770"bc0f <OFFSET>"
4771*mipsI:
4772*mipsII:
4773*mipsIII:
4774*mipsIV:
90ad43b2
AC		 4775// start-sanitize-vr5400
4776*vr5400:
4777// end-sanitize-vr5400
f2b30012
AC		 4778// start-sanitize-r5900
4779*r5900:
4780// end-sanitize-r5900
4781
4782
4783010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4784"bc0fl <OFFSET>"
4785*mipsI:
4786*mipsII:
4787*mipsIII:
4788*mipsIV:
90ad43b2
AC		 4789// start-sanitize-vr5400
4790*vr5400:
4791// end-sanitize-vr5400
f2b30012
AC		 4792// start-sanitize-r5900
4793*r5900:
4794// end-sanitize-r5900
4795
4796
4797010000,01000,00001,16.OFFSET:COP0:32::BC0T
4798"bc0t <OFFSET>"
4799*mipsI:
4800*mipsII:
4801*mipsIII:
4802*mipsIV:
4803// start-sanitize-r5900
4804*r5900:
4805// end-sanitize-r5900
4806
4807
4808
49a6eed5 4809010000,01000,00011,16.OFFSET:COP0:32::BC0TL
f2b30012
AC		 4810"bc0tl <OFFSET>"
4811*mipsI:
4812*mipsII:
4813*mipsIII:
4814*mipsIV:
90ad43b2
AC		 4815// start-sanitize-vr5400
4816*vr5400:
4817// end-sanitize-vr5400
f2b30012
AC		 4818// start-sanitize-r5900
4819*r5900:
4820// end-sanitize-r5900
4821
4822
4823101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4824*mipsIII:
4825*mipsIV:
90ad43b2
AC		 4826// start-sanitize-vr5400
4827*vr5400:
4828// end-sanitize-vr5400
f2b30012
AC		 4829// start-sanitize-r5900
4830*r5900:
4831// end-sanitize-r5900
4832*r3900:
4833// start-sanitize-tx19
4834*tx19:
4835// end-sanitize-tx19
4836{
4837 unsigned32 instruction = instruction_0;
055ee297
AC		 4838 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
4839 int hint = ((instruction >> 16) & 0x0000001F);
4840 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 4841 {
49a76833
AC		 4842 address_word vaddr = (op1 + offset);
4843 address_word paddr;
f2b30012
AC		 4844 int uncached;
4845 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4846 CacheOp(hint,vaddr,paddr,instruction);
4847 }
4848}
4849
4850
4851010000,10000,000000000000000,111001:COP0:32::DI
4852"di"
4853*mipsI:
4854*mipsII:
4855*mipsIII:
4856*mipsIV:
90ad43b2
AC		 4857// start-sanitize-vr5400
4858*vr5400:
4859// end-sanitize-vr5400
f2b30012
AC		 4860// start-sanitize-r5900
4861*r5900:
4862// end-sanitize-r5900
4863
4864
4865010000,10000,000000000000000,111000:COP0:32::EI
4866"ei"
4867*mipsI:
4868*mipsII:
4869*mipsIII:
4870*mipsIV:
90ad43b2
AC		 4871// start-sanitize-vr5400
4872*vr5400:
4873// end-sanitize-vr5400
f2b30012
AC		 4874// start-sanitize-r5900
4875*r5900:
4876// end-sanitize-r5900
4877
4878
4879010000,10000,000000000000000,011000:COP0:32::ERET
4880"eret"
4881*mipsIII:
4882*mipsIV:
90ad43b2
AC		 4883// start-sanitize-vr5400
4884*vr5400:
4885// end-sanitize-vr5400
f2b30012
AC		 4886// start-sanitize-r5900
4887*r5900:
4888// end-sanitize-r5900
4889
4890
49a6eed5
AC		 4891010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4892"mfc0 r<RT>, r<RD> # <REGX>"
f2b30012
AC		 4893*mipsI:
4894*mipsII:
4895*mipsIII:
4896*mipsIV:
90ad43b2
AC		 4897// start-sanitize-vr5400
4898*vr5400:
4899// end-sanitize-vr5400
f2b30012
AC		 4900// start-sanitize-r5900
4901*r5900:
4902// end-sanitize-r5900
4903
4904
49a6eed5
AC		 4905010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4906"mtc0 r<RT>, r<RD> # <REGX>"
f2b30012
AC		 4907*mipsI:
4908*mipsII:
4909*mipsIII:
4910*mipsIV:
90ad43b2
AC		 4911// start-sanitize-vr5400
4912*vr5400:
4913// end-sanitize-vr5400
f2b30012
AC		 4914// start-sanitize-r5900
4915*r5900:
4916// end-sanitize-r5900
4917
4918
4919010000,10000,000000000000000,001000:COP0:32::TLBP
4920"tlbp"
4921*mipsI:
4922*mipsII:
4923*mipsIII:
4924*mipsIV:
90ad43b2
AC		 4925// start-sanitize-vr5400
4926*vr5400:
4927// end-sanitize-vr5400
f2b30012
AC		 4928// start-sanitize-r5900
4929*r5900:
4930// end-sanitize-r5900
4931
4932
4933010000,10000,000000000000000,000001:COP0:32::TLBR
4934"tlbr"
4935*mipsI:
4936*mipsII:
4937*mipsIII:
4938*mipsIV:
90ad43b2
AC		 4939// start-sanitize-vr5400
4940*vr5400:
4941// end-sanitize-vr5400
f2b30012
AC		 4942// start-sanitize-r5900
4943*r5900:
4944// end-sanitize-r5900
4945
4946
4947010000,10000,000000000000000,000010:COP0:32::TLBWI
4948"tlbwi"
4949*mipsI:
4950*mipsII:
4951*mipsIII:
4952*mipsIV:
90ad43b2
AC		 4953// start-sanitize-vr5400
4954*vr5400:
4955// end-sanitize-vr5400
f2b30012
AC		 4956// start-sanitize-r5900
4957*r5900:
4958// end-sanitize-r5900
4959
4960
4961010000,10000,000000000000000,000110:COP0:32::TLBWR
4962"tlbwr"
4963*mipsI:
4964*mipsII:
4965*mipsIII:
4966*mipsIV:
90ad43b2
AC		 4967// start-sanitize-vr5400
4968*vr5400:
4969// end-sanitize-vr5400
f2b30012
AC		 4970// start-sanitize-r5900
4971*r5900:
4972// end-sanitize-r5900
4973
4974\f
89d09738 4975:include:::m16.igen
16bd5d6e 4976// start-sanitize-vr5400
89d09738 4977:include::vr5400:vr5400.igen
16bd5d6e 4978// end-sanitize-vr5400
f2b30012 4979// start-sanitize-r5900
89d09738 4980:include::r5900:r5900.igen
f2b30012
AC		 4981// end-sanitize-r5900
4982\f
4983// start-sanitize-cygnus-never
4984
49a6eed5
AC		 4985// // FIXME FIXME FIXME What is this instruction?
4986// 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
4987// *mipsI:
4988// *mipsII:
4989// *mipsIII:
4990// *mipsIV:
4991// // start-sanitize-r5900
4992// *r5900:
4993// // end-sanitize-r5900
4994// *r3900:
4995// // start-sanitize-tx19
4996// *tx19:
4997// // end-sanitize-tx19
4998// {
4999// unsigned32 instruction = instruction_0;
055ee297
AC		 5000// signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5001// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5002// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
49a6eed5
AC		 5003// {
5004// if (CoProcPresent(3))
5005// SignalException(CoProcessorUnusable);
5006// else
5007// SignalException(ReservedInstruction,instruction);
5008// }
5009// }
5010
5011// end-sanitize-cygnus-never
5012// start-sanitize-cygnus-never
5013
5014// // FIXME FIXME FIXME What is this?
5015// 11100,******,00001:RR:16::SDBBP
5016// *mips16:
5017// {
5018// unsigned32 instruction = instruction_0;
5019// if (have_extendval)
5020// SignalException (ReservedInstruction, instruction);
5021// {
5022// SignalException(DebugBreakPoint,instruction);
5023// }
5024// }
f2b30012
AC		 5025
5026// end-sanitize-cygnus-never
5027// start-sanitize-cygnus-never
5028
49a6eed5
AC		 5029// // FIXME FIXME FIXME What is this?
5030// 000000,********************,001110:SPECIAL:32::SDBBP
5031// *r3900:
5032// {
5033// unsigned32 instruction = instruction_0;
5034// {
5035// SignalException(DebugBreakPoint,instruction);
5036// }
5037// }
f2b30012
AC		 5038
5039// end-sanitize-cygnus-never
5040// start-sanitize-cygnus-never
5041
49a6eed5
AC		 5042// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5043// // isn't yet reconized by this simulator.
5044// 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5045// *vr4100:
5046// {
5047// unsigned32 instruction = instruction_0;
055ee297
AC		 5048// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5049// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
49a6eed5
AC		 5050// {
5051// CHECKHILO("Multiply-Add");
5052// {
5053// unsigned64 temp = (op1 * op2);
5054// temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5055// LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5056// HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5057// }
5058// }
5059// }
f2b30012
AC		 5060
5061// end-sanitize-cygnus-never
49a6eed5
AC		 5062// start-sanitize-cygnus-never
5063
5064// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5065// // isn't yet reconized by this simulator.
5066// 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5067// *vr4100:
5068// {
5069// unsigned32 instruction = instruction_0;
055ee297
AC		 5070// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5071// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
49a6eed5
AC		 5072// {
5073// CHECKHILO("Multiply-Add");
5074// {
5075// unsigned64 temp = (op1 * op2);
5076// LO = LO + temp;
5077// }
5078// }
5079// }
5080
5081// start-sanitize-cygnus-never
GDB Binutils - Deliverables
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