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Delete profile support from MIPS simulator, use sim/common/sim-profile
[deliverable/binutils-gdb.git] / sim / mips / mips.igen
CommitLineData
f2b30012
AC		 1// <insn> ::=
2// <insn-word> { "+" <insn-word> }
3// ":" <format-name>
4// ":" <filter-flags>
5// ":" <options>
6// ":" <name>
7// <nl>
8// { <insn-model> }
9// { <insn-mnemonic> }
10// <code-block>
11//
12
13
14// IGEN config - mips16
15:option:16:insn-bit-size:16
16:option:16:hi-bit-nr:15
17:option:16:insn-specifying-widths:true
055ee297 18:option:16:gen-delayed-branch:true
f2b30012
AC		 19
20// IGEN config - mipsI..
21:option:32:insn-bit-size:32
22:option:32:hi-bit-nr:31
23:option:32:insn-specifying-widths:true
055ee297 24:option:32:gen-delayed-branch:true
f2b30012
AC		 25
26
49a6eed5
AC		 27// Generate separate simulators for each target
28:option::multi-sim:true
29
f2b30012
AC		 30
31// Models known by this simulator
32:model::mipsI:mipsI:
33:model::mipsII:mipsII:
34:model::mipsIII:mipsIII:
35:model::mipsIV:mipsIV:
36:model::mips16:mips16:
37// start-sanitize-r5900
38:model::r5900:r5900:
39// end-sanitize-r5900
40:model::r3900:r3900:
41// start-sanitize-tx19
42:model::tx19:tx19:
43// end-sanitize-tx19
44
45
46
47// Pseudo instructions known by IGEN
48:internal:::illegal
49{
50 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
055ee297 51 (unsigned long) CIA);
f2b30012
AC		 52 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
53}
54
55
56
57
58//
59// MIPS Architecture:
60//
61// CPU Instruction Set (mipsI - mipsIV)
62//
63
64
65000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
66"add r<RD>, r<RS>, r<RT>"
67*mipsI:
68*mipsII:
69*mipsIII:
70*mipsIV:
71// start-sanitize-r5900
72*r5900:
73// end-sanitize-r5900
74*r3900:
75// start-sanitize-tx19
76*tx19:
77// end-sanitize-tx19
78{
055ee297
AC		 79 ALU32_BEGIN (GPR[RS]);
80 ALU32_ADD (GPR[RT]);
81 ALU32_END (GPR[RD]);
f2b30012
AC		 82}
83
84
85001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
86"addi r<RT>, r<RS>, IMMEDIATE"
87*mipsI:
88*mipsII:
89*mipsIII:
90*mipsIV:
91// start-sanitize-r5900
92*r5900:
93// end-sanitize-r5900
94*r3900:
95// start-sanitize-tx19
96*tx19:
97// end-sanitize-tx19
98{
055ee297 99 ALU32_BEGIN (GPR[RS]);
f2b30012 100 ALU32_ADD (EXTEND16 (IMMEDIATE));
055ee297 101 ALU32_END (GPR[RT]);
f2b30012
AC		 102}
103
104
105001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
106"add r<RT>, r<RS>, IMMEDIATE"
107*mipsI:
108*mipsII:
109*mipsIII:
110*mipsIV:
111// start-sanitize-r5900
112*r5900:
113// end-sanitize-r5900
114*r3900:
115// start-sanitize-tx19
116*tx19:
117// end-sanitize-tx19
118{
055ee297
AC		 119 signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
120 GPR[RT] = EXTEND32 (temp);
f2b30012
AC		 121}
122
123
124000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
125*mipsI:
126*mipsII:
127*mipsIII:
128*mipsIV:
129// start-sanitize-r5900
130*r5900:
131// end-sanitize-r5900
132*r3900:
133// start-sanitize-tx19
134*tx19:
135// end-sanitize-tx19
136{
055ee297
AC		 137 signed32 temp = GPR[RS] + GPR[RT];
138 GPR[RD] = EXTEND32 (temp);
f2b30012
AC		 139}
140
141
142000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
143"and r<RD>, r<RS>, r<RT>"
144*mipsI:
145*mipsII:
146*mipsIII:
147*mipsIV:
148// start-sanitize-r5900
149*r5900:
150// end-sanitize-r5900
151*r3900:
152// start-sanitize-tx19
153*tx19:
154// end-sanitize-tx19
155{
055ee297 156 GPR[RD] = GPR[RS] & GPR[RT];
f2b30012
AC		 157}
158
159
160001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
161"and r<RT>, r<RS>, IMMEDIATE"
162*mipsI:
163*mipsII:
164*mipsIII:
165// start-sanitize-r5900
166*r5900:
167// end-sanitize-r5900
168*r3900:
169// start-sanitize-tx19
170*tx19:
171// end-sanitize-tx19
172{
055ee297 173 GPR[RT] = GPR[RS] & IMMEDIATE;
f2b30012
AC		 174}
175
176
177000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
178"beq r<RS>, r<RT>, OFFSET"
179*mipsI:
180*mipsII:
181*mipsIII:
182*mipsIV:
183// start-sanitize-r5900
184*r5900:
185// end-sanitize-r5900
186*r3900:
187// start-sanitize-tx19
188*tx19:
189// end-sanitize-tx19
190{
055ee297
AC		 191 address_word offset = EXTEND16 (OFFSET) << 2;
192 if (GPR[RS] == GPR[RT])
193 DSPC = (PC + offset);
f2b30012
AC		 194}
195
196
197010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
198"beql r<RS>, r<RT>, <OFFSET>"
199*mipsII:
200*mipsIII:
201*mipsIV:
202// start-sanitize-r5900
203*r5900:
204// end-sanitize-r5900
205*r3900:
206// start-sanitize-tx19
207*tx19:
208// end-sanitize-tx19
209{
055ee297
AC		 210 address_word offset = EXTEND16 (OFFSET) << 2;
211 if (GPR[RS] == GPR[RT])
212 DSPC = (PC + offset);
213 else
214 NULLIFY_NIA ();
f2b30012
AC		 215}
216
217
218000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
219"bgez r<RS>, <OFFSET>"
220*mipsI:
221*mipsII:
222*mipsIII:
223*mipsIV:
224// start-sanitize-r5900
225*r5900:
226// end-sanitize-r5900
227*r3900:
228// start-sanitize-tx19
229*tx19:
230// end-sanitize-tx19
231{
055ee297
AC		 232 address_word offset = EXTEND16 (OFFSET) << 2;
233 if (GPR[RS] >= 0)
234 DSPC = (PC + offset);
f2b30012
AC		 235}
236
237
238000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
239"bgezal r<RS>, <OFFSET>"
240*mipsI:
241*mipsII:
242*mipsIII:
243*mipsIV:
244// start-sanitize-r5900
245*r5900:
246// end-sanitize-r5900
247*r3900:
248// start-sanitize-tx19
249*tx19:
250// end-sanitize-tx19
251{
055ee297
AC		 252 address_word offset = EXTEND16 (OFFSET) << 2;
253 RA = (CIA + 8);
254 if (GPR[RS] >= 0)
255 DSPC = (PC + offset);
f2b30012
AC		 256}
257
258
259000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
260"bgezall r<RS>, <OFFSET>"
261*mipsII:
262*mipsIII:
263*mipsIV:
264// start-sanitize-r5900
265*r5900:
266// end-sanitize-r5900
267*r3900:
268// start-sanitize-tx19
269*tx19:
270// end-sanitize-tx19
271{
055ee297
AC		 272 address_word offset = EXTEND16 (OFFSET) << 2;
273 RA = (CIA + 8);
f2b30012
AC		 274 /* NOTE: The branch occurs AFTER the next instruction has been
275 executed */
055ee297
AC		 276 if (GPR[RS] >= 0)
277 DSPC = (PC + offset);
f2b30012 278 else
055ee297 279 NULLIFY_NIA ();
f2b30012
AC		 280}
281
282
283000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
284"bgezl r<RS>, <OFFSET>"
285*mipsII:
286*mipsIII:
287*mipsIV:
288// start-sanitize-r5900
289*r5900:
290// end-sanitize-r5900
291*r3900:
292// start-sanitize-tx19
293*tx19:
294// end-sanitize-tx19
295{
055ee297
AC		 296 address_word offset = EXTEND16 (OFFSET) << 2;
297 if (GPR[RS] >= 0)
298 DSPC = (PC + offset);
f2b30012 299 else
055ee297 300 NULLIFY_NIA ();
f2b30012
AC		 301}
302
303
304000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
305"bgtz r<RS>, <OFFSET>"
306*mipsI:
307*mipsII:
308*mipsIII:
309*mipsIV:
310// start-sanitize-r5900
311*r5900:
312// end-sanitize-r5900
313*r3900:
314// start-sanitize-tx19
315*tx19:
316// end-sanitize-tx19
317{
055ee297
AC		 318 address_word offset = EXTEND16 (OFFSET) << 2;
319 if (GPR[RS] > 0)
320 DSPC = (PC + offset);
f2b30012
AC		 321}
322
323
324010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
325"bgtzl r<RS>, <OFFSET>"
326*mipsII:
327*mipsIII:
328*mipsIV:
329// start-sanitize-r5900
330*r5900:
331// end-sanitize-r5900
332*r3900:
333// start-sanitize-tx19
334*tx19:
335// end-sanitize-tx19
336{
055ee297 337 address_word offset = EXTEND16 (OFFSET) << 2;
f2b30012
AC		 338 /* NOTE: The branch occurs AFTER the next instruction has been
339 executed */
055ee297
AC		 340 if (GPR[RS] > 0)
341 DSPC = (PC + offset);
f2b30012 342 else
055ee297 343 NULLIFY_NIA ();
f2b30012
AC		 344}
345
346
347000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
348"blez r<RS>, <OFFSET>"
349*mipsI:
350*mipsII:
351*mipsIII:
352*mipsIV:
353// start-sanitize-r5900
354*r5900:
355// end-sanitize-r5900
356*r3900:
357// start-sanitize-tx19
358*tx19:
359// end-sanitize-tx19
360{
055ee297 361 address_word offset = EXTEND16 (OFFSET) << 2;
f2b30012
AC		 362 /* NOTE: The branch occurs AFTER the next instruction has been
363 executed */
055ee297
AC		 364 if (GPR[RS] <= 0)
365 DSPC = (PC + offset);
f2b30012
AC		 366}
367
368
369010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
370"bgezl r<RS>, <OFFSET>"
371*mipsII:
372*mipsIII:
373*mipsIV:
374// start-sanitize-r5900
375*r5900:
376// end-sanitize-r5900
377*r3900:
378// start-sanitize-tx19
379*tx19:
380// end-sanitize-tx19
381{
055ee297 382 address_word offset = EXTEND16 (OFFSET) << 2;
055ee297 383 if (GPR[RS] <= 0)
085c1cb9 384 DSPC = (PC + offset);
f2b30012 385 else
085c1cb9 386 NULLIFY_NIA ();
f2b30012
AC		 387}
388
389
390000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
391"bltz r<RS>, <OFFSET>"
392*mipsI:
393*mipsII:
394*mipsIII:
395*mipsIV:
396// start-sanitize-r5900
397*r5900:
398// end-sanitize-r5900
399*r3900:
400// start-sanitize-tx19
401*tx19:
402// end-sanitize-tx19
403{
055ee297
AC		 404 address_word offset = EXTEND16 (OFFSET) << 2;
405 if (GPR[RS] < 0)
406 DSPC = (PC + offset);
f2b30012
AC		 407}
408
409
410000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
411"bltzal r<RS>, <OFFSET>"
412*mipsI:
413*mipsII:
414*mipsIII:
415*mipsIV:
416// start-sanitize-r5900
417*r5900:
418// end-sanitize-r5900
419*r3900:
420// start-sanitize-tx19
421*tx19:
422// end-sanitize-tx19
423{
055ee297
AC		 424 address_word offset = EXTEND16 (OFFSET) << 2;
425 RA = (CIA + 8);
f2b30012
AC		 426 /* NOTE: The branch occurs AFTER the next instruction has been
427 executed */
055ee297
AC		 428 if (GPR[RS] < 0)
429 DSPC = (PC + offset);
f2b30012
AC		 430}
431
432
433000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
434"bltzall r<RS>, <OFFSET>"
435*mipsII:
436*mipsIII:
437*mipsIV:
438// start-sanitize-r5900
439*r5900:
440// end-sanitize-r5900
441*r3900:
442// start-sanitize-tx19
443*tx19:
444// end-sanitize-tx19
445{
055ee297
AC		 446 address_word offset = EXTEND16 (OFFSET) << 2;
447 RA = (CIA + 8);
448 if (GPR[RS] < 0)
449 DSPC = (PC + offset);
f2b30012 450 else
055ee297 451 NULLIFY_NIA ();
f2b30012
AC		 452}
453
454
455000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
456"bltzl r<RS>, <OFFSET>"
457*mipsII:
458*mipsIII:
459*mipsIV:
460// start-sanitize-r5900
461*r5900:
462// end-sanitize-r5900
463*r3900:
464// start-sanitize-tx19
465*tx19:
466// end-sanitize-tx19
467{
055ee297 468 address_word offset = EXTEND16 (OFFSET) << 2;
f2b30012
AC		 469 /* NOTE: The branch occurs AFTER the next instruction has been
470 executed */
055ee297
AC		 471 if (GPR[RS] < 0)
472 DSPC = (PC + offset);
f2b30012 473 else
055ee297 474 NULLIFY_NIA ();
f2b30012
AC		 475}
476
477
478000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
479"bne r<RS>, r<RT>, <OFFSET>"
480*mipsI:
481*mipsII:
482*mipsIII:
483*mipsIV:
484// start-sanitize-r5900
485*r5900:
486// end-sanitize-r5900
487*r3900:
488// start-sanitize-tx19
489*tx19:
490// end-sanitize-tx19
491{
055ee297
AC		 492 address_word offset = EXTEND16 (OFFSET) << 2;
493 if (GPR[RS] != GPR[RT])
494 DSPC = (PC + offset);
f2b30012
AC		 495}
496
497
498010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
499"bnel r<RS>, r<RT>, <OFFSET>"
500*mipsII:
501*mipsIII:
502*mipsIV:
503// start-sanitize-r5900
504*r5900:
505// end-sanitize-r5900
506*r3900:
507// start-sanitize-tx19
508*tx19:
509// end-sanitize-tx19
510{
085c1cb9 511 address_word offset = EXTEND16 (OFFSET) << 2;
055ee297 512 if (GPR[RS] != GPR[RT])
085c1cb9 513 DSPC = (PC + offset);
f2b30012 514 else
085c1cb9 515 NULLIFY_NIA ();
f2b30012
AC		 516}
517
518
49a6eed5 519000000,20.CODE,001101:SPECIAL:32::BREAK
f2b30012
AC		 520"break"
521*mipsI:
522*mipsII:
523*mipsIII:
524*mipsIV:
525// start-sanitize-r5900
526*r5900:
527// end-sanitize-r5900
528*r3900:
529// start-sanitize-tx19
530*tx19:
531// end-sanitize-tx19
532{
055ee297 533 SignalException(BreakPoint, instruction_0);
f2b30012
AC		 534}
535
536
49a6eed5 5370100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
f2b30012
AC		 538"cop<ZZ> <COP_FUN>"
539*mipsI:
540*mipsII:
541*mipsIII:
542*mipsIV:
543// start-sanitize-r5900
544*r5900:
545// end-sanitize-r5900
546*r3900:
547// start-sanitize-tx19
548*tx19:
549// end-sanitize-tx19
550{
085c1cb9 551 DecodeCoproc (instruction_0);
f2b30012
AC		 552}
553
554
555000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
556"dadd r<RD>, r<RS>, r<RT>"
557*mipsIII:
558*mipsIV:
559// start-sanitize-r5900
560*r5900:
561// end-sanitize-r5900
562*r3900:
563// start-sanitize-tx19
564*tx19:
565// end-sanitize-tx19
566{
055ee297
AC		 567 ALU64_BEGIN (GPR[RS]);
568 ALU64_ADD (GPR[RT]);
569 ALU64_END (GPR[RT]);
f2b30012
AC		 570}
571
572
573011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
574"daddi r<RT>, r<RS>, <IMMEDIATE>"
575*mipsIII:
576*mipsIV:
577// start-sanitize-r5900
578*r5900:
579// end-sanitize-r5900
580*r3900:
581// start-sanitize-tx19
582*tx19:
583// end-sanitize-tx19
584{
055ee297 585 ALU64_BEGIN (GPR[RS]);
f2b30012 586 ALU64_ADD (EXTEND16 (IMMEDIATE));
055ee297 587 ALU64_END (GPR[RT]);
f2b30012
AC		 588}
589
590
591011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
592"daddu r<RT>, r<RS>, <IMMEDIATE>"
593*mipsIII:
594*mipsIV:
595// start-sanitize-r5900
596*r5900:
597// end-sanitize-r5900
598*r3900:
599// start-sanitize-tx19
600*tx19:
601// end-sanitize-tx19
602{
085c1cb9 603 GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE);
f2b30012
AC		 604}
605
606
607000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
608"daddu r<RD>, r<RS>, r<RT>"
609*mipsIII:
610*mipsIV:
611// start-sanitize-r5900
612*r5900:
613// end-sanitize-r5900
614*r3900:
615// start-sanitize-tx19
616*tx19:
617// end-sanitize-tx19
618{
055ee297 619 GPR[RD] = GPR[RS] + GPR[RT];
f2b30012
AC		 620}
621
622
623000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
624"ddiv r<RS>, r<RT>"
625*mipsIII:
626*mipsIV:
627// start-sanitize-r5900
628*r5900:
629// end-sanitize-r5900
630*r3900:
631// start-sanitize-tx19
632*tx19:
633// end-sanitize-tx19
634{
635 CHECKHILO ("Division");
636 {
055ee297
AC		 637 signed64 n = GPR[RS];
638 signed64 d = GPR[RT];
f2b30012
AC		 639 if (d == 0)
640 {
641 LO = SIGNED64 (0x8000000000000000);
642 HI = 0;
643 }
644 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
645 {
646 LO = SIGNED64 (0x8000000000000000);
647 HI = 0;
648 }
649 else
650 {
651 LO = (n / d);
652 HI = (n % d);
653 }
654 }
655}
656
657
658
659000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
660"ddivu r<RS>, r<RT>"
661*mipsIII:
662*mipsIV:
663*r3900:
664// start-sanitize-tx19
665*tx19:
666// end-sanitize-tx19
667{
668 CHECKHILO ("Division");
669 {
055ee297
AC		 670 unsigned64 n = GPR[RS];
671 unsigned64 d = GPR[RT];
f2b30012
AC		 672 if (d == 0)
673 {
674 LO = SIGNED64 (0x8000000000000000);
675 HI = 0;
676 }
677 else
678 {
679 LO = (n / d);
680 HI = (n % d);
681 }
682 }
683}
684
685
686000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
687"div r<RS>, r<RT>"
688*mipsI:
689*mipsII:
690*mipsIII:
691*mipsIV:
692// start-sanitize-r5900
693*r5900:
694// end-sanitize-r5900
695*r3900:
696// start-sanitize-tx19
697*tx19:
698// end-sanitize-tx19
699{
700 CHECKHILO("Division");
701 {
055ee297
AC		 702 signed32 n = GPR[RS];
703 signed32 d = GPR[RT];
f2b30012
AC		 704 if (d == 0)
705 {
706 LO = EXTEND32 (0x80000000);
707 HI = EXTEND32 (0);
708 }
055ee297 709 else if (d == -1 && d == 0x80000000)
f2b30012
AC		 710 {
711 LO = EXTEND32 (0x80000000);
712 HI = EXTEND32 (0);
713 }
714 else
715 {
716 LO = EXTEND32 (n / d);
717 HI = EXTEND32 (n % d);
718 }
719 }
720}
721
722
723000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
724"divu r<RS>, r<RT>"
725*mipsI:
726*mipsII:
727*mipsIII:
728*mipsIV:
729// start-sanitize-r5900
730*r5900:
731// end-sanitize-r5900
732*r3900:
733// start-sanitize-tx19
734*tx19:
735// end-sanitize-tx19
736{
737 CHECKHILO ("Division");
738 {
055ee297
AC		 739 unsigned32 n = GPR[RS];
740 unsigned32 d = GPR[RT];
f2b30012
AC		 741 if (d == 0)
742 {
743 LO = EXTEND32 (0x80000000);
744 HI = EXTEND32 (0);
745 }
746 else
747 {
748 LO = EXTEND32 (n / d);
749 HI = EXTEND32 (n % d);
750 }
751 }
752}
753
754
755000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
756"dmult r<RS>, r<RT>"
757*mipsIII:
758*mipsIV:
759*r3900:
760// start-sanitize-tx19
761*tx19:
762// end-sanitize-tx19
763{
764 CHECKHILO ("Multiplication");
765 {
055ee297
AC		 766 signed64 op1 = GPR[RS];
767 signed64 op2 = GPR[RT];
f2b30012
AC		 768 unsigned64 lo;
769 unsigned64 hi;
770 unsigned64 m00;
771 unsigned64 m01;
772 unsigned64 m10;
773 unsigned64 m11;
774 unsigned64 mid;
f2b30012
AC		 775 int sign = 0;
776 /* make it unsigned */
777 if (op1 < 0)
778 {
779 op1 = - op1;
780 ++sign;
781 }
782 if (op2 < 0)
783 {
784 op2 = - op2;
785 ++sign;
786 }
787 /* multuply out the 4 sub products */
788 m00 = (VL4_8 (op1) * VL4_8 (op2));
789 m10 = (VH4_8 (op1) * VL4_8 (op2));
790 m01 = (VL4_8 (op1) * VH4_8 (op2));
791 m11 = (VH4_8 (op1) * VH4_8 (op2));
792 /* add the products */
793 mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
794 lo = U8_4 (mid, m00);
795 hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
796 /* save the result */
797 if (sign & 1)
798 {
799 LO = -lo;
800 if (lo == 0)
801 HI = -hi;
802 else
803 HI = -hi - 1;
804 }
805 else
806 {
807 LO = lo;
808 HI = hi;
809 }
810 }
811}
812
813
814000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
815"dmultu r<RS>, r<RT>"
816*mipsIII:
817*mipsIV:
818*r3900:
819// start-sanitize-tx19
820*tx19:
821// end-sanitize-tx19
822{
823 CHECKHILO ("Multiplication");
824 {
055ee297
AC		 825 signed64 op1 = GPR[RS];
826 signed64 op2 = GPR[RT];
f2b30012
AC		 827 unsigned64 lo;
828 unsigned64 hi;
829 unsigned64 m00;
830 unsigned64 m01;
831 unsigned64 m10;
832 unsigned64 m11;
833 unsigned64 mid;
f2b30012
AC		 834 /* multuply out the 4 sub products */
835 m00 = (VL4_8 (op1) * VL4_8 (op2));
836 m10 = (VH4_8 (op1) * VL4_8 (op2));
837 m01 = (VL4_8 (op1) * VH4_8 (op2));
838 m11 = (VH4_8 (op1) * VH4_8 (op2));
839 /* add the products */
840 mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
841 lo = U8_4 (mid, m00);
842 hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
843 /* save the result */
844 LO = lo;
845 HI = hi;
846 }
847}
848
849
055ee297 85000000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
f2b30012
AC		 851"dsll r<RD>, r<RT>, <SA>"
852*mipsIII:
853*mipsIV:
854// start-sanitize-r5900
855*r5900:
856// end-sanitize-r5900
857*r3900:
858// start-sanitize-tx19
859*tx19:
860// end-sanitize-tx19
861{
055ee297
AC		 862 int s = SA;
863 GPR[RD] = GPR[RT] << s;
f2b30012
AC		 864}
865
866
055ee297 86700000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
f2b30012
AC		 868"dsll32 r<RD>, r<RT>, <SA>"
869*mipsIII:
870*mipsIV:
871// start-sanitize-r5900
872*r5900:
873// end-sanitize-r5900
874*r3900:
875// start-sanitize-tx19
876*tx19:
877// end-sanitize-tx19
878{
055ee297
AC		 879 int s = 32 + SA;
880 GPR[RD] = GPR[RT] << s;
f2b30012
AC		 881}
882
883
884000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
885"dsllv r<RD>, r<RT>, r<RS>"
886*mipsIII:
887*mipsIV:
888// start-sanitize-r5900
889*r5900:
890// end-sanitize-r5900
891*r3900:
892// start-sanitize-tx19
893*tx19:
894// end-sanitize-tx19
895{
055ee297
AC		 896 int s = MASKED64 (GPR[RS], 5, 0);
897 GPR[RD] = GPR[RT] << s;
f2b30012
AC		 898}
899
900
055ee297 90100000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
f2b30012
AC		 902"dsra r<RD>, r<RT>, <SA>"
903*mipsIII:
904*mipsIV:
905// start-sanitize-r5900
906*r5900:
907// end-sanitize-r5900
908*r3900:
909// start-sanitize-tx19
910*tx19:
911// end-sanitize-tx19
912{
055ee297
AC		 913 int s = SA;
914 GPR[RD] = ((signed64) GPR[RT]) >> s;
f2b30012
AC		 915}
916
917
055ee297 91800000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
f2b30012
AC		 919"dsra32 r<RT>, r<RD>, <SA>"
920*mipsIII:
921*mipsIV:
922// start-sanitize-r5900
923*r5900:
924// end-sanitize-r5900
925*r3900:
926// start-sanitize-tx19
927*tx19:
928// end-sanitize-tx19
929{
055ee297
AC		 930 int s = 32 + SA;
931 GPR[RD] = ((signed64) GPR[RT]) >> s;
f2b30012
AC		 932}
933
934
935000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
936"dsra32 r<RT>, r<RD>, r<RS>"
937*mipsIII:
938*mipsIV:
939// start-sanitize-r5900
940*r5900:
941// end-sanitize-r5900
942*r3900:
943// start-sanitize-tx19
944*tx19:
945// end-sanitize-tx19
946{
055ee297
AC		 947 int s = MASKED64 (GPR[RS], 5, 0);
948 GPR[RD] = ((signed64) GPR[RT]) >> s;
f2b30012
AC		 949}
950
951
055ee297 95200000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
f2b30012
AC		 953"dsrav r<RD>, r<RT>, <SA>"
954*mipsIII:
955*mipsIV:
956// start-sanitize-r5900
957*r5900:
958// end-sanitize-r5900
959*r3900:
960// start-sanitize-tx19
961*tx19:
962// end-sanitize-tx19
963{
964 int s = SA;
055ee297 965 GPR[RD] = (unsigned64) GPR[RT] >> s;
f2b30012
AC		 966}
967
968
055ee297 96900000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
f2b30012
AC		 970"dsrl32 r<RD>, r<RT>, <SA>"
971*mipsIII:
972*mipsIV:
973// start-sanitize-r5900
974*r5900:
975// end-sanitize-r5900
976*r3900:
977// start-sanitize-tx19
978*tx19:
979// end-sanitize-tx19
980{
981 int s = 32 + SA;
055ee297 982 GPR[RD] = (unsigned64) GPR[RT] >> s;
f2b30012
AC		 983}
984
985
986000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
987"dsrl32 r<RD>, r<RT>, r<RS>"
988*mipsIII:
989*mipsIV:
990// start-sanitize-r5900
991*r5900:
992// end-sanitize-r5900
993*r3900:
994// start-sanitize-tx19
995*tx19:
996// end-sanitize-tx19
997{
055ee297
AC		 998 int s = MASKED64 (GPR[RS], 5, 0);
999 GPR[RD] = (unsigned64) GPR[RT] >> s;
f2b30012
AC		 1000}
1001
1002
1003000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1004"dsub r<RD>, r<RS>, r<RT>"
1005*mipsIII:
1006*mipsIV:
1007// start-sanitize-r5900
1008*r5900:
1009// end-sanitize-r5900
1010*r3900:
1011// start-sanitize-tx19
1012*tx19:
1013// end-sanitize-tx19
1014{
055ee297
AC		 1015 ALU64_BEGIN (GPR[RS]);
1016 ALU64_SUB (GPR[RT]);
1017 ALU64_END (GPR[RD]);
f2b30012
AC		 1018}
1019
1020
1021000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1022"dsubu r<RD>, r<RS>, r<RT>"
1023*mipsIII:
1024*mipsIV:
1025// start-sanitize-r5900
1026*r5900:
1027// end-sanitize-r5900
1028*r3900:
1029// start-sanitize-tx19
1030*tx19:
1031// end-sanitize-tx19
1032{
055ee297 1033 GPR[RD] = GPR[RS] - GPR[RT];
f2b30012
AC		 1034}
1035
1036
1037000010,26.INSTR_INDEX:NORMAL:32::J
1038"j <INSTR_INDEX>"
1039*mipsI:
1040*mipsII:
1041*mipsIII:
1042*mipsIV:
1043// start-sanitize-r5900
1044*r5900:
1045// end-sanitize-r5900
1046*r3900:
1047// start-sanitize-tx19
1048*tx19:
1049// end-sanitize-tx19
1050{
1051 /* NOTE: The region used is that of the delay slot and NOT the
1052 current instruction */
055ee297 1053 address_word region = cia.dp & MASK (63, 28);
f2b30012 1054 DSPC = region | (INSTR_INDEX << 2);
f2b30012
AC		 1055}
1056
1057
1058000011,26.INSTR_INDEX:NORMAL:32::JAL
1059"jal <INSTR_INDEX>"
1060*mipsI:
1061*mipsII:
1062*mipsIII:
1063*mipsIV:
1064// start-sanitize-r5900
1065*r5900:
1066// end-sanitize-r5900
1067*r3900:
1068// start-sanitize-tx19
1069*tx19:
1070// end-sanitize-tx19
1071{
1072 /* NOTE: The region used is that of the delay slot and NOT the
1073 current instruction */
055ee297
AC		 1074 address_word region = cia.dp & MASK (63, 28);
1075 GPR[31] = CIA + 8;
f2b30012 1076 DSPC = region | (INSTR_INDEX << 2);
f2b30012
AC		 1077}
1078
1079
1080000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1081"jalr r<RS>":RD == 31
1082"jalr r<RD>, r<RS>"
1083*mipsI:
1084*mipsII:
1085*mipsIII:
1086*mipsIV:
1087// start-sanitize-r5900
1088*r5900:
1089// end-sanitize-r5900
1090*r3900:
1091// start-sanitize-tx19
1092*tx19:
1093// end-sanitize-tx19
1094{
055ee297
AC		 1095 address_word temp = GPR[RS];
1096 GPR[RD] = CIA + 8;
f2b30012 1097 DSPC = temp;
f2b30012
AC		 1098}
1099
1100
1101000000,5.RS,000000000000000001000:SPECIAL:32::JR
1102"jr r<RS>"
1103*mipsI:
1104*mipsII:
1105*mipsIII:
1106*mipsIV:
1107// start-sanitize-r5900
1108*r5900:
1109// end-sanitize-r5900
1110*r3900:
1111// start-sanitize-tx19
1112*tx19:
1113// end-sanitize-tx19
1114{
055ee297 1115 DSPC = GPR[RS];
f2b30012
AC		 1116}
1117
1118
1119100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1120"lb r<RT>, <OFFSET>(r<BASE>)"
1121*mipsI:
1122*mipsII:
1123*mipsIII:
1124*mipsIV:
1125// start-sanitize-r5900
1126*r5900:
1127// end-sanitize-r5900
1128*r3900:
1129// start-sanitize-tx19
1130*tx19:
1131// end-sanitize-tx19
1132{
1133 unsigned32 instruction = instruction_0;
055ee297
AC		 1134 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1135 int destreg = ((instruction >> 16) & 0x0000001F);
1136 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 1137 {
1138 uword64 vaddr = ((uword64)op1 + offset);
1139 uword64 paddr;
1140 int uncached;
1141 {
1142 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1143 {
1144 uword64 memval = 0;
1145 uword64 memval1 = 0;
1146 uword64 mask = 0x7;
1147 unsigned int shift = 0;
055ee297
AC		 1148 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1149 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1150 unsigned int byte;
f2b30012
AC		 1151 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1152 LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1153 byte = ((vaddr & mask) ^ (bigend << shift));
1154 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
1155 }
1156 }
1157 }
1158}
1159
1160
1161100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1162"lbu r<RT>, <OFFSET>(r<BASE>)"
1163*mipsI:
1164*mipsII:
1165*mipsIII:
1166*mipsIV:
1167// start-sanitize-r5900
1168*r5900:
1169// end-sanitize-r5900
1170*r3900:
1171// start-sanitize-tx19
1172*tx19:
1173// end-sanitize-tx19
1174{
1175 unsigned32 instruction = instruction_0;
055ee297
AC		 1176 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1177 int destreg = ((instruction >> 16) & 0x0000001F);
1178 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 1179 {
1180 unsigned64 vaddr = ((unsigned64)op1 + offset);
1181 unsigned64 paddr;
1182 int uncached;
1183 {
1184 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1185 {
1186 unsigned64 memval = 0;
1187 unsigned64 memval1 = 0;
1188 unsigned64 mask = 0x7;
1189 unsigned int shift = 0;
055ee297
AC		 1190 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1191 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1192 unsigned int byte;
f2b30012
AC		 1193 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1194 LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1195 byte = ((vaddr & mask) ^ (bigend << shift));
1196 GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
1197 }
1198 }
1199 }
1200}
1201
1202
1203110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1204"ld r<RT>, <OFFSET>(r<BASE>)"
1205*mipsIII:
1206*mipsIV:
1207// start-sanitize-r5900
1208*r5900:
1209// end-sanitize-r5900
1210*r3900:
1211// start-sanitize-tx19
1212*tx19:
1213// end-sanitize-tx19
1214{
1215 unsigned32 instruction = instruction_0;
055ee297
AC		 1216 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1217 int destreg = ((instruction >> 16) & 0x0000001F);
1218 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 1219 {
1220 unsigned64 vaddr = ((unsigned64)op1 + offset);
1221 unsigned64 paddr;
1222 int uncached;
1223 if ((vaddr & 7) != 0)
055ee297 1224 SignalExceptionAddressLoad();
f2b30012
AC		 1225 else
1226 {
1227 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1228 {
1229 unsigned64 memval = 0;
1230 unsigned64 memval1 = 0;
f2b30012
AC		 1231 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1232 GPR[destreg] = memval;
1233 }
1234 }
1235 }
1236}
1237
1238
49a6eed5 12391101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
f2b30012
AC		 1240"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1241*mipsII:
1242*mipsIII:
1243*mipsIV:
1244// start-sanitize-r5900
1245*r5900:
1246// end-sanitize-r5900
1247*r3900:
1248// start-sanitize-tx19
1249*tx19:
1250// end-sanitize-tx19
1251{
1252 unsigned32 instruction = instruction_0;
055ee297
AC		 1253 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1254 int destreg = ((instruction >> 16) & 0x0000001F);
1255 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 1256 {
1257 unsigned64 vaddr = ((unsigned64)op1 + offset);
1258 unsigned64 paddr;
1259 int uncached;
1260 if ((vaddr & 7) != 0)
055ee297 1261 SignalExceptionAddressLoad();
f2b30012
AC		 1262 else
1263 {
1264 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1265 {
1266 unsigned64 memval = 0;
1267 unsigned64 memval1 = 0;
f2b30012
AC		 1268 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1269 COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
1270 }
1271 }
1272 }
1273}
1274
1275
1276011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1277"ldl r<RT>, <OFFSET>(r<BASE>)"
1278*mipsIII:
1279*mipsIV:
1280// start-sanitize-r5900
1281*r5900:
1282// end-sanitize-r5900
1283*r3900:
1284// start-sanitize-tx19
1285*tx19:
1286// end-sanitize-tx19
1287{
1288 unsigned32 instruction = instruction_0;
055ee297
AC		 1289 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1290 int destreg = ((instruction >> 16) & 0x0000001F);
1291 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 1292 {
1293 unsigned64 vaddr = ((unsigned64)op1 + offset);
1294 unsigned64 paddr;
1295 int uncached;
1296 {
1297 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1298 {
1299 unsigned64 memval = 0;
1300 unsigned64 memval1 = 0;
1301 unsigned64 mask = 7;
1302 unsigned int reverse = (ReverseEndian ? mask : 0);
1303 unsigned int bigend = (BigEndianCPU ? mask : 0);
1304 int byte;
1305 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1306 byte = ((vaddr & mask) ^ bigend);
1307 if (!!ByteSwapMem)
1308 paddr &= ~mask;
1309 LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1310 GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
1311 }
1312 }
1313 }
1314}
1315
1316
1317011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1318"ldr r<RT>, <OFFSET>(r<BASE>)"
1319*mipsIII:
1320*mipsIV:
1321// start-sanitize-r5900
1322*r5900:
1323// end-sanitize-r5900
1324*r3900:
1325// start-sanitize-tx19
1326*tx19:
1327// end-sanitize-tx19
1328{
1329 unsigned32 instruction = instruction_0;
055ee297
AC		 1330 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1331 int destreg = ((instruction >> 16) & 0x0000001F);
1332 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 1333 {
1334 unsigned64 vaddr = ((unsigned64)op1 + offset);
1335 unsigned64 paddr;
1336 int uncached;
1337 {
1338 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1339 {
1340 unsigned64 memval = 0;
1341 unsigned64 memval1 = 0;
1342 unsigned64 mask = 7;
1343 unsigned int reverse = (ReverseEndian ? mask : 0);
1344 unsigned int bigend = (BigEndianCPU ? mask : 0);
1345 int byte;
1346 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1347 byte = ((vaddr & mask) ^ bigend);
1348 if (!ByteSwapMem)
1349 paddr &= ~mask;
1350 LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
1351 {
1352 unsigned64 srcmask;
1353 if (byte == 0)
1354 srcmask = 0;
1355 else
1356 srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
1357 GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1358 }
1359 }
1360 }
1361 }
1362}
1363
1364
1365100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1366"lh r<RT>, <OFFSET>(r<BASE>)"
1367*mipsI:
1368*mipsII:
1369*mipsIII:
1370*mipsIV:
1371// start-sanitize-r5900
1372*r5900:
1373// end-sanitize-r5900
1374*r3900:
1375// start-sanitize-tx19
1376*tx19:
1377// end-sanitize-tx19
1378{
1379 unsigned32 instruction = instruction_0;
055ee297
AC		 1380 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1381 int destreg = ((instruction >> 16) & 0x0000001F);
1382 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 1383 {
1384 unsigned64 vaddr = ((unsigned64)op1 + offset);
1385 unsigned64 paddr;
1386 int uncached;
1387 if ((vaddr & 1) != 0)
055ee297 1388 SignalExceptionAddressLoad();
f2b30012
AC		 1389 else
1390 {
1391 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1392 {
1393 unsigned64 memval = 0;
1394 unsigned64 memval1 = 0;
1395 unsigned64 mask = 0x7;
1396 unsigned int shift = 1;
055ee297
AC		 1397 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1398 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1399 unsigned int byte;
f2b30012
AC		 1400 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1401 LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1402 byte = ((vaddr & mask) ^ (bigend << shift));
1403 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
1404 }
1405 }
1406 }
1407}
1408
1409
1410100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1411"lhu r<RT>, <OFFSET>(r<BASE>)"
1412*mipsI:
1413*mipsII:
1414*mipsIII:
1415*mipsIV:
1416// start-sanitize-r5900
1417*r5900:
1418// end-sanitize-r5900
1419*r3900:
1420// start-sanitize-tx19
1421*tx19:
1422// end-sanitize-tx19
1423{
1424 unsigned32 instruction = instruction_0;
055ee297
AC		 1425 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1426 int destreg = ((instruction >> 16) & 0x0000001F);
1427 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 1428 {
1429 unsigned64 vaddr = ((unsigned64)op1 + offset);
1430 unsigned64 paddr;
1431 int uncached;
1432 if ((vaddr & 1) != 0)
055ee297 1433 SignalExceptionAddressLoad();
f2b30012
AC		 1434 else
1435 {
1436 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1437 {
1438 unsigned64 memval = 0;
1439 unsigned64 memval1 = 0;
1440 unsigned64 mask = 0x7;
1441 unsigned int shift = 1;
055ee297
AC		 1442 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1443 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1444 unsigned int byte;
f2b30012
AC		 1445 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1446 LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1447 byte = ((vaddr & mask) ^ (bigend << shift));
1448 GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
1449 }
1450 }
1451 }
1452}
1453
1454
1455110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1456"ll r<RT>, <OFFSET>(r<BASE>)"
1457*mipsII:
1458*mipsIII:
1459*mipsIV:
1460// start-sanitize-r5900
1461*r5900:
1462// end-sanitize-r5900
1463*r3900:
1464// start-sanitize-tx19
1465*tx19:
1466// end-sanitize-tx19
1467{
1468 unsigned32 instruction = instruction_0;
055ee297
AC		 1469 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1470 int destreg = ((instruction >> 16) & 0x0000001F);
1471 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 1472 {
1473 unsigned64 vaddr = ((unsigned64)op1 + offset);
1474 unsigned64 paddr;
1475 int uncached;
1476 if ((vaddr & 3) != 0)
055ee297 1477 SignalExceptionAddressLoad();
f2b30012
AC		 1478 else
1479 {
1480 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1481 {
1482 unsigned64 memval = 0;
1483 unsigned64 memval1 = 0;
1484 unsigned64 mask = 0x7;
1485 unsigned int shift = 2;
055ee297
AC		 1486 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1487 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1488 unsigned int byte;
f2b30012
AC		 1489 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1490 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1491 byte = ((vaddr & mask) ^ (bigend << shift));
1492 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1493 LLBIT = 1;
1494 }
1495 }
1496 }
1497}
1498
1499
1500110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1501"lld r<RT>, <OFFSET>(r<BASE>)"
1502*mipsIII:
1503*mipsIV:
1504// start-sanitize-r5900
1505*r5900:
1506// end-sanitize-r5900
1507*r3900:
1508// start-sanitize-tx19
1509*tx19:
1510// end-sanitize-tx19
1511{
1512 unsigned32 instruction = instruction_0;
055ee297
AC		 1513 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1514 int destreg = ((instruction >> 16) & 0x0000001F);
1515 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 1516 {
1517 unsigned64 vaddr = ((unsigned64)op1 + offset);
1518 unsigned64 paddr;
1519 int uncached;
1520 if ((vaddr & 7) != 0)
055ee297 1521 SignalExceptionAddressLoad();
f2b30012
AC		 1522 else
1523 {
1524 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1525 {
1526 unsigned64 memval = 0;
1527 unsigned64 memval1 = 0;
f2b30012
AC		 1528 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1529 GPR[destreg] = memval;
1530 LLBIT = 1;
1531 }
1532 }
1533 }
1534}
1535
1536
1537001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1538"lui r<RT>, <IMMEDIATE>"
1539*mipsI:
1540*mipsII:
1541*mipsIII:
1542*mipsIV:
1543// start-sanitize-r5900
1544*r5900:
1545// end-sanitize-r5900
1546*r3900:
1547// start-sanitize-tx19
1548*tx19:
1549// end-sanitize-tx19
1550{
055ee297 1551 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
f2b30012
AC		 1552}
1553
1554
1555100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1556"lw r<RT>, <OFFSET>(r<BASE>)"
1557*mipsI:
1558*mipsII:
1559*mipsIII:
1560*mipsIV:
1561// start-sanitize-r5900
1562*r5900:
1563// end-sanitize-r5900
1564*r3900:
1565// start-sanitize-tx19
1566*tx19:
1567// end-sanitize-tx19
1568{
1569 unsigned32 instruction = instruction_0;
055ee297
AC		 1570 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1571 int destreg = ((instruction >> 16) & 0x0000001F);
1572 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 1573 {
1574 unsigned64 vaddr = ((unsigned64)op1 + offset);
1575 unsigned64 paddr;
1576 int uncached;
1577 if ((vaddr & 3) != 0)
055ee297 1578 SignalExceptionAddressLoad();
f2b30012
AC		 1579 else
1580 {
1581 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1582 {
1583 unsigned64 memval = 0;
1584 unsigned64 memval1 = 0;
1585 unsigned64 mask = 0x7;
1586 unsigned int shift = 2;
055ee297
AC		 1587 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1588 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1589 unsigned int byte;
f2b30012
AC		 1590 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1591 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1592 byte = ((vaddr & mask) ^ (bigend << shift));
1593 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1594 }
1595 }
1596 }
1597}
1598
1599
49a6eed5 16001100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
f2b30012
AC		 1601"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1602*mipsI:
1603*mipsII:
1604*mipsIII:
1605*mipsIV:
1606// start-sanitize-r5900
1607*r5900:
1608// end-sanitize-r5900
1609*r3900:
1610// start-sanitize-tx19
1611*tx19:
1612// end-sanitize-tx19
1613{
1614 unsigned32 instruction = instruction_0;
055ee297
AC		 1615 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1616 int destreg = ((instruction >> 16) & 0x0000001F);
1617 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 1618 {
1619 unsigned64 vaddr = ((unsigned64)op1 + offset);
1620 unsigned64 paddr;
1621 int uncached;
1622 if ((vaddr & 3) != 0)
055ee297 1623 SignalExceptionAddressLoad();
f2b30012
AC		 1624 else
1625 {
1626 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1627 {
1628 unsigned64 memval = 0;
1629 unsigned64 memval1 = 0;
1630 unsigned64 mask = 0x7;
1631 unsigned int shift = 2;
055ee297
AC		 1632 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1633 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1634 unsigned int byte;
f2b30012
AC		 1635 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1636 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1637 byte = ((vaddr & mask) ^ (bigend << shift));
1638 COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
1639 }
1640 }
1641 }
1642}
1643
1644
1645100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1646"lwl r<RT>, <OFFSET>(r<BASE>)"
1647*mipsI:
1648*mipsII:
1649*mipsIII:
1650*mipsIV:
1651// start-sanitize-r5900
1652*r5900:
1653// end-sanitize-r5900
1654*r3900:
1655// start-sanitize-tx19
1656*tx19:
1657// end-sanitize-tx19
1658{
1659 unsigned32 instruction = instruction_0;
055ee297
AC		 1660 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1661 int destreg = ((instruction >> 16) & 0x0000001F);
1662 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 1663 {
1664 unsigned64 vaddr = ((unsigned64)op1 + offset);
1665 unsigned64 paddr;
1666 int uncached;
1667 {
1668 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1669 {
1670 unsigned64 memval = 0;
1671 unsigned64 memval1 = 0;
1672 unsigned64 mask = 3;
1673 unsigned int reverse = (ReverseEndian ? mask : 0);
1674 unsigned int bigend = (BigEndianCPU ? mask : 0);
1675 int byte;
1676 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1677 byte = ((vaddr & mask) ^ bigend);
1678 if (!!ByteSwapMem)
1679 paddr &= ~mask;
1680 LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1681 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1682 memval >>= 32;
1683 }
1684 GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
1685 GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1686 }
1687 }
1688 }
1689}
1690
1691
1692100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1693"lwr r<RT>, <OFFSET>(r<BASE>)"
1694*mipsI:
1695*mipsII:
1696*mipsIII:
1697*mipsIV:
1698// start-sanitize-r5900
1699*r5900:
1700// end-sanitize-r5900
1701*r3900:
1702// start-sanitize-tx19
1703*tx19:
1704// end-sanitize-tx19
1705{
1706 unsigned32 instruction = instruction_0;
055ee297
AC		 1707 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1708 int destreg = ((instruction >> 16) & 0x0000001F);
1709 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 1710 {
1711 unsigned64 vaddr = ((unsigned64)op1 + offset);
1712 unsigned64 paddr;
1713 int uncached;
1714 {
1715 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1716 {
1717 unsigned64 memval = 0;
1718 unsigned64 memval1 = 0;
1719 unsigned64 mask = 3;
1720 unsigned int reverse = (ReverseEndian ? mask : 0);
1721 unsigned int bigend = (BigEndianCPU ? mask : 0);
1722 int byte;
1723 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1724 byte = ((vaddr & mask) ^ bigend);
1725 if (!ByteSwapMem)
1726 paddr &= ~mask;
1727 LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
1728 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1729 memval >>= 32;
1730 }
1731 {
1732 unsigned64 srcmask;
1733 if (byte == 0)
1734 srcmask = 0;
1735 else
1736 srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
1737 GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1738 }
1739 GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1740 }
1741 }
1742 }
1743}
1744
1745
1746100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
1747"lwu r<RT>, <OFFSET>(r<BASE>)"
1748*mipsIII:
1749*mipsIV:
1750// start-sanitize-r5900
1751*r5900:
1752// end-sanitize-r5900
1753*r3900:
1754// start-sanitize-tx19
1755*tx19:
1756// end-sanitize-tx19
1757{
1758 unsigned32 instruction = instruction_0;
055ee297
AC		 1759 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1760 int destreg = ((instruction >> 16) & 0x0000001F);
1761 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 1762 {
1763 unsigned64 vaddr = ((unsigned64)op1 + offset);
1764 unsigned64 paddr;
1765 int uncached;
1766 if ((vaddr & 3) != 0)
055ee297 1767 SignalExceptionAddressLoad();
f2b30012
AC		 1768 else
1769 {
1770 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1771 {
1772 unsigned64 memval = 0;
1773 unsigned64 memval1 = 0;
1774 unsigned64 mask = 0x7;
1775 unsigned int shift = 2;
055ee297
AC		 1776 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1777 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1778 unsigned int byte;
f2b30012
AC		 1779 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1780 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1781 byte = ((vaddr & mask) ^ (bigend << shift));
1782 GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
1783 }
1784 }
1785 }
1786}
1787
1788
1789000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1790"mfhi r<RD>"
1791*mipsI:
1792*mipsII:
1793*mipsIII:
1794*mipsIV:
1795// start-sanitize-r5900
1796*r5900:
1797// end-sanitize-r5900
1798*r3900:
1799// start-sanitize-tx19
1800*tx19:
1801// end-sanitize-tx19
1802{
055ee297 1803 GPR[RD] = HI;
f2b30012
AC		 1804 HIACCESS = 3;
1805}
1806
1807
1808000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
1809"mflo r<RD>"
1810*mipsI:
1811*mipsII:
1812*mipsIII:
1813*mipsIV:
1814// start-sanitize-r5900
1815*r5900:
1816// end-sanitize-r5900
1817*r3900:
1818// start-sanitize-tx19
1819*tx19:
1820// end-sanitize-tx19
1821{
055ee297 1822 GPR[RD] = LO;
f2b30012
AC		 1823 LOACCESS = 3; /* 3rd instruction will be safe */
1824}
1825
1826
1827000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
1828"movn r<RD>, r<RS>, r<RT>"
1829*mipsIV:
1830// start-sanitize-r5900
1831*r5900:
1832// end-sanitize-r5900
1833{
055ee297
AC		 1834 if (GPR[RT] != 0)
1835 GPR[RD] = GPR[RS];
f2b30012
AC		 1836}
1837
1838
1839000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
1840"movz r<RD>, r<RS>, r<RT>"
1841*mipsIV:
1842// start-sanitize-r5900
1843*r5900:
1844// end-sanitize-r5900
1845{
055ee297
AC		 1846 if (GPR[RT] == 0)
1847 GPR[RD] = GPR[RS];
f2b30012
AC		 1848}
1849
1850
1851000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
1852"mthi r<RS>"
1853*mipsI:
1854*mipsII:
1855*mipsIII:
1856*mipsIV:
1857// start-sanitize-r5900
1858*r5900:
1859// end-sanitize-r5900
1860*r3900:
1861// start-sanitize-tx19
1862*tx19:
1863// end-sanitize-tx19
1864{
1865 if (HIACCESS != 0)
055ee297
AC		 1866 sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
1867 HI = GPR[RS];
f2b30012
AC		 1868 HIACCESS = 3; /* 3rd instruction will be safe */
1869}
1870
1871
1872000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
1873"mtlo r<RS>"
1874*mipsI:
1875*mipsII:
1876*mipsIII:
1877*mipsIV:
1878// start-sanitize-r5900
1879*r5900:
1880// end-sanitize-r5900
1881*r3900:
1882// start-sanitize-tx19
1883*tx19:
1884// end-sanitize-tx19
1885{
1886 if (LOACCESS != 0)
055ee297
AC		 1887 sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
1888 LO = GPR[RS];
f2b30012
AC		 1889 LOACCESS = 3; /* 3rd instruction will be safe */
1890}
1891
1892
1893000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
1894"mult r<RS>, r<RT>"
1895*mipsI:
1896*mipsII:
1897*mipsIII:
1898*mipsIV:
1899// start-sanitize-r5900
1900*r5900:
1901// end-sanitize-r5900
1902*r3900:
1903// start-sanitize-tx19
1904*tx19:
1905// end-sanitize-tx19
1906{
1907 signed64 prod;
1908 CHECKHILO ("Multiplication");
055ee297
AC		 1909 prod = (((signed64)(signed32) GPR[RS])
1910 * ((signed64)(signed32) GPR[RT]));
f2b30012
AC		 1911 LO = EXTEND32 (VL4_8 (prod));
1912 HI = EXTEND32 (VH4_8 (prod));
1913}
1914
1915
1916000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
1917"multu r<RS>, r<RT>"
1918*mipsI:
1919*mipsII:
1920*mipsIII:
1921*mipsIV:
1922// start-sanitize-r5900
1923*r5900:
1924// end-sanitize-r5900
1925*r3900:
1926// start-sanitize-tx19
1927*tx19:
1928// end-sanitize-tx19
1929{
1930 unsigned64 prod;
1931 CHECKHILO ("Multiplication");
055ee297
AC		 1932 prod = (((unsigned64)(unsigned32) GPR[RS])
1933 * ((unsigned64)(unsigned32) GPR[RT]));
f2b30012
AC		 1934 LO = EXTEND32 (VL4_8 (prod));
1935 HI = EXTEND32 (VH4_8 (prod));
1936}
1937
1938
1939000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
1940"nor r<RD>, r<RS>, r<RT>"
1941*mipsI:
1942*mipsII:
1943*mipsIII:
1944*mipsIV:
1945// start-sanitize-r5900
1946*r5900:
1947// end-sanitize-r5900
1948*r3900:
1949// start-sanitize-tx19
1950*tx19:
1951// end-sanitize-tx19
1952{
055ee297 1953 GPR[RD] = ~ (GPR[RS] | GPR[RT]);
f2b30012
AC		 1954}
1955
1956
1957000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
1958"or r<RD>, r<RS>, r<RT>"
1959*mipsI:
1960*mipsII:
1961*mipsIII:
1962*mipsIV:
1963// start-sanitize-r5900
1964*r5900:
1965// end-sanitize-r5900
1966*r3900:
1967// start-sanitize-tx19
1968*tx19:
1969// end-sanitize-tx19
1970{
055ee297 1971 GPR[RD] = (GPR[RS] | GPR[RT]);
f2b30012
AC		 1972}
1973
1974
1975001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
055ee297 1976"ori r<RT>, r<RS>, <IMMEDIATE>"
f2b30012
AC		 1977*mipsI:
1978*mipsII:
1979*mipsIII:
1980*mipsIV:
1981// start-sanitize-r5900
1982*r5900:
1983// end-sanitize-r5900
1984*r3900:
1985// start-sanitize-tx19
1986*tx19:
1987// end-sanitize-tx19
1988{
055ee297 1989 GPR[RT] = (GPR[RS] | IMMEDIATE);
f2b30012
AC		 1990}
1991
1992
1993110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
1994*mipsIV:
1995// start-sanitize-r5900
1996*r5900:
1997// end-sanitize-r5900
1998{
1999 unsigned32 instruction = instruction_0;
055ee297
AC		 2000 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2001 int hint = ((instruction >> 16) & 0x0000001F);
2002 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 2003 {
2004 unsigned64 vaddr = ((unsigned64)op1 + offset);
2005 unsigned64 paddr;
2006 int uncached;
2007 {
2008 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2009 Prefetch(uncached,paddr,vaddr,isDATA,hint);
2010 }
2011 }
2012}
2013
2014101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2015"sb r<RT>, <OFFSET>(r<BASE>)"
2016*mipsI:
2017*mipsII:
2018*mipsIII:
2019*mipsIV:
2020// start-sanitize-r5900
2021*r5900:
2022// end-sanitize-r5900
2023*r3900:
2024// start-sanitize-tx19
2025*tx19:
2026// end-sanitize-tx19
2027{
2028 unsigned32 instruction = instruction_0;
055ee297
AC		 2029 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2030 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2031 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 2032 {
2033 unsigned64 vaddr = ((unsigned64)op1 + offset);
2034 unsigned64 paddr;
2035 int uncached;
2036 {
2037 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2038 {
2039 unsigned64 memval = 0;
2040 unsigned64 memval1 = 0;
2041 unsigned64 mask = 0x7;
2042 unsigned int shift = 0;
2043 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2044 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2045 unsigned int byte;
2046 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2047 byte = ((vaddr & mask) ^ (bigend << shift));
2048 memval = ((unsigned64) op2 << (8 * byte));
2049 {
2050 StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
2051 }
2052 }
2053 }
2054 }
2055}
2056
2057
2058111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2059"sc r<RT>, <OFFSET>(r<BASE>)"
2060*mipsII:
2061*mipsIII:
2062*mipsIV:
2063// start-sanitize-r5900
2064*r5900:
2065// end-sanitize-r5900
2066*r3900:
2067// start-sanitize-tx19
2068*tx19:
2069// end-sanitize-tx19
2070{
2071 unsigned32 instruction = instruction_0;
055ee297
AC		 2072 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2073 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2074 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 2075 {
2076 unsigned64 vaddr = ((unsigned64)op1 + offset);
2077 unsigned64 paddr;
2078 int uncached;
2079 if ((vaddr & 3) != 0)
055ee297 2080 SignalExceptionAddressStore();
f2b30012
AC		 2081 else
2082 {
2083 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2084 {
2085 unsigned64 memval = 0;
2086 unsigned64 memval1 = 0;
2087 unsigned64 mask = 0x7;
2088 unsigned int byte;
2089 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2090 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2091 memval = ((unsigned64) op2 << (8 * byte));
2092 if (LLBIT)
2093 {
2094 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2095 }
2096 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2097 }
2098 }
2099 }
2100}
2101
2102
2103111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2104"scd r<RT>, <OFFSET>(r<BASE>)"
2105*mipsIII:
2106*mipsIV:
2107// start-sanitize-r5900
2108*r5900:
2109// end-sanitize-r5900
2110*r3900:
2111// start-sanitize-tx19
2112*tx19:
2113// end-sanitize-tx19
2114{
2115 unsigned32 instruction = instruction_0;
055ee297
AC		 2116 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2117 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2118 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 2119 {
2120 unsigned64 vaddr = ((unsigned64)op1 + offset);
2121 unsigned64 paddr;
2122 int uncached;
2123 if ((vaddr & 7) != 0)
055ee297 2124 SignalExceptionAddressStore();
f2b30012
AC		 2125 else
2126 {
2127 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2128 {
2129 unsigned64 memval = 0;
2130 unsigned64 memval1 = 0;
2131 memval = op2;
2132 if (LLBIT)
2133 {
2134 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2135 }
2136 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2137 }
2138 }
2139 }
2140}
2141
2142
2143111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2144"sd r<RT>, <OFFSET>(r<BASE>)"
2145*mipsIII:
2146*mipsIV:
2147// start-sanitize-r5900
2148*r5900:
2149// end-sanitize-r5900
2150*r3900:
2151// start-sanitize-tx19
2152*tx19:
2153// end-sanitize-tx19
2154{
2155 unsigned32 instruction = instruction_0;
055ee297
AC		 2156 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2157 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2158 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 2159 {
2160 unsigned64 vaddr = ((unsigned64)op1 + offset);
2161 unsigned64 paddr;
2162 int uncached;
2163 if ((vaddr & 7) != 0)
055ee297 2164 SignalExceptionAddressStore();
f2b30012
AC		 2165 else
2166 {
2167 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2168 {
2169 unsigned64 memval = 0;
2170 unsigned64 memval1 = 0;
2171 memval = op2;
2172 {
2173 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2174 }
2175 }
2176 }
2177 }
2178}
2179
2180
49a6eed5 21811111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
f2b30012
AC		 2182"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2183*mipsII:
2184*mipsIII:
2185*mipsIV:
2186// start-sanitize-r5900
2187*r5900:
2188// end-sanitize-r5900
2189*r3900:
2190// start-sanitize-tx19
2191*tx19:
2192// end-sanitize-tx19
2193{
2194 unsigned32 instruction = instruction_0;
055ee297
AC		 2195 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2196 int destreg = ((instruction >> 16) & 0x0000001F);
2197 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 2198 {
2199 unsigned64 vaddr = ((unsigned64)op1 + offset);
2200 unsigned64 paddr;
2201 int uncached;
2202 if ((vaddr & 7) != 0)
055ee297 2203 SignalExceptionAddressStore();
f2b30012
AC		 2204 else
2205 {
2206 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2207 {
2208 unsigned64 memval = 0;
2209 unsigned64 memval1 = 0;
2210 memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
2211 {
2212 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2213 }
2214 }
2215 }
2216 }
2217}
2218
2219
2220101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2221"sdl r<RT>, <OFFSET>(r<BASE>)"
2222*mipsIII:
2223*mipsIV:
2224// start-sanitize-r5900
2225*r5900:
2226// end-sanitize-r5900
2227*r3900:
2228// start-sanitize-tx19
2229*tx19:
2230// end-sanitize-tx19
2231{
2232 unsigned32 instruction = instruction_0;
055ee297
AC		 2233 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2234 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2235 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 2236 {
2237 unsigned64 vaddr = ((unsigned64)op1 + offset);
2238 unsigned64 paddr;
2239 int uncached;
2240 {
2241 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2242 {
2243 unsigned64 memval = 0;
2244 unsigned64 memval1 = 0;
2245 unsigned64 mask = 7;
2246 unsigned int reverse = (ReverseEndian ? mask : 0);
2247 unsigned int bigend = (BigEndianCPU ? mask : 0);
2248 int byte;
2249 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2250 byte = ((vaddr & mask) ^ bigend);
2251 if (!!ByteSwapMem)
2252 paddr &= ~mask;
2253 memval = (op2 >> (8 * (7 - byte)));
2254 StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2255 }
2256 }
2257 }
2258}
2259
2260
2261101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2262"sdr r<RT>, <OFFSET>(r<BASE>)"
2263*mipsIII:
2264*mipsIV:
2265// start-sanitize-r5900
2266*r5900:
2267// end-sanitize-r5900
2268*r3900:
2269// start-sanitize-tx19
2270*tx19:
2271// end-sanitize-tx19
2272{
2273 unsigned32 instruction = instruction_0;
055ee297
AC		 2274 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2275 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2276 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 2277 {
2278 unsigned64 vaddr = ((unsigned64)op1 + offset);
2279 unsigned64 paddr;
2280 int uncached;
2281 {
2282 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2283 {
2284 unsigned64 memval = 0;
2285 unsigned64 memval1 = 0;
2286 unsigned64 mask = 7;
2287 unsigned int reverse = (ReverseEndian ? mask : 0);
2288 unsigned int bigend = (BigEndianCPU ? mask : 0);
2289 int byte;
2290 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2291 byte = ((vaddr & mask) ^ bigend);
2292 if (!ByteSwapMem)
2293 paddr &= ~mask;
2294 memval = ((unsigned64) op2 << (byte * 8));
2295 StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,memval1,paddr,vaddr,isREAL);
2296 }
2297 }
2298 }
2299}
2300
2301
2302101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2303"sh r<RT>, <OFFSET>(r<BASE>)"
2304*mipsI:
2305*mipsII:
2306*mipsIII:
2307*mipsIV:
2308// start-sanitize-r5900
2309*r5900:
2310// end-sanitize-r5900
2311*r3900:
2312// start-sanitize-tx19
2313*tx19:
2314// end-sanitize-tx19
2315{
2316 unsigned32 instruction = instruction_0;
055ee297
AC		 2317 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2318 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2319 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 2320 {
2321 unsigned64 vaddr = ((unsigned64)op1 + offset);
2322 unsigned64 paddr;
2323 int uncached;
2324 if ((vaddr & 1) != 0)
055ee297 2325 SignalExceptionAddressStore();
f2b30012
AC		 2326 else
2327 {
2328 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2329 {
2330 unsigned64 memval = 0;
2331 unsigned64 memval1 = 0;
2332 unsigned64 mask = 0x7;
2333 unsigned int shift = 1;
2334 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2335 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2336 unsigned int byte;
2337 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2338 byte = ((vaddr & mask) ^ (bigend << shift));
2339 memval = ((unsigned64) op2 << (8 * byte));
2340 {
2341 StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
2342 }
2343 }
2344 }
2345 }
2346}
2347
2348
055ee297
AC		 234900000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2350"sll r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 2351*mipsI:
2352*mipsII:
2353*mipsIII:
2354*mipsIV:
2355// start-sanitize-r5900
2356*r5900:
2357// end-sanitize-r5900
2358*r3900:
2359// start-sanitize-tx19
2360*tx19:
2361// end-sanitize-tx19
2362{
055ee297
AC		 2363 int s = SHIFT;
2364 unsigned32 temp = (GPR[RT] << s);
2365 GPR[RD] = EXTEND32 (temp);
f2b30012
AC		 2366}
2367
2368
055ee297 2369000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
f2b30012
AC		 2370"sllv r<RD>, r<RT>, r<RS>"
2371*mipsI:
2372*mipsII:
2373*mipsIII:
2374*mipsIV:
2375// start-sanitize-r5900
2376*r5900:
2377// end-sanitize-r5900
2378*r3900:
2379// start-sanitize-tx19
2380*tx19:
2381// end-sanitize-tx19
2382{
055ee297
AC		 2383 int s = MASKED (GPR[RS], 4, 0);
2384 unsigned32 temp = (GPR[RT] << s);
2385 GPR[RD] = EXTEND32 (temp);
f2b30012
AC		 2386}
2387
2388
2389000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2390"slt r<RD>, r<RS>, r<RT>"
2391*mipsI:
2392*mipsII:
2393*mipsIII:
2394*mipsIV:
2395// start-sanitize-r5900
2396*r5900:
2397// end-sanitize-r5900
2398*r3900:
2399// start-sanitize-tx19
2400*tx19:
2401// end-sanitize-tx19
2402{
055ee297 2403 GPR[RD] = (GPR[RS] < GPR[RT]);
f2b30012
AC		 2404}
2405
2406
2407001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
055ee297 2408"slti r<RT>, r<RS>, <IMMEDIATE>"
f2b30012
AC		 2409*mipsI:
2410*mipsII:
2411*mipsIII:
2412*mipsIV:
2413// start-sanitize-r5900
2414*r5900:
2415// end-sanitize-r5900
2416*r3900:
2417// start-sanitize-tx19
2418*tx19:
2419// end-sanitize-tx19
2420{
055ee297 2421 GPR[RT] = (GPR[RS] < EXTEND16 (IMMEDIATE));
f2b30012
AC		 2422}
2423
2424
2425001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
055ee297 2426"sltiu r<RT>, r<RS>, <IMMEDIATE>"
f2b30012
AC		 2427*mipsI:
2428*mipsII:
2429*mipsIII:
2430*mipsIV:
2431// start-sanitize-r5900
2432*r5900:
2433// end-sanitize-r5900
2434*r3900:
2435// start-sanitize-tx19
2436*tx19:
2437// end-sanitize-tx19
2438{
055ee297 2439 GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
f2b30012
AC		 2440}
2441
2442000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2443"sltu r<RD>, r<RS>, r<RT>"
2444*mipsI:
2445*mipsII:
2446*mipsIII:
2447*mipsIV:
2448// start-sanitize-r5900
2449*r5900:
2450// end-sanitize-r5900
2451*r3900:
2452// start-sanitize-tx19
2453*tx19:
2454// end-sanitize-tx19
2455{
055ee297 2456 GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
f2b30012
AC		 2457}
2458
2459
055ee297
AC		 2460000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2461"sra r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 2462*mipsI:
2463*mipsII:
2464*mipsIII:
2465*mipsIV:
2466// start-sanitize-r5900
2467*r5900:
2468// end-sanitize-r5900
2469*r3900:
2470// start-sanitize-tx19
2471*tx19:
2472// end-sanitize-tx19
2473{
055ee297
AC		 2474 int s = SHIFT;
2475 signed32 temp = (signed32) GPR[RT] >> s;
2476 GPR[RD] = EXTEND32 (temp);
f2b30012
AC		 2477}
2478
2479
2480000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2481"srav r<RD>, r<RT>, r<RS>"
2482*mipsI:
2483*mipsII:
2484*mipsIII:
2485*mipsIV:
2486// start-sanitize-r5900
2487*r5900:
2488// end-sanitize-r5900
2489*r3900:
2490// start-sanitize-tx19
2491*tx19:
2492// end-sanitize-tx19
2493{
055ee297
AC		 2494 int s = MASKED (GPR[RS], 4, 0);
2495 signed32 temp = (signed32) GPR[RT] >> s;
2496 GPR[RD] = EXTEND32 (temp);
f2b30012
AC		 2497}
2498
2499
055ee297
AC		 2500000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2501"srl r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 2502*mipsI:
2503*mipsII:
2504*mipsIII:
2505*mipsIV:
2506// start-sanitize-r5900
2507*r5900:
2508// end-sanitize-r5900
2509*r3900:
2510// start-sanitize-tx19
2511*tx19:
2512// end-sanitize-tx19
2513{
055ee297
AC		 2514 int s = SHIFT;
2515 unsigned32 temp = (unsigned32) GPR[RT] >> s;
2516 GPR[RD] = EXTEND32 (temp);
f2b30012
AC		 2517}
2518
2519
2520000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2521"srlv r<RD>, r<RT>, r<RS>"
2522*mipsI:
2523*mipsII:
2524*mipsIII:
2525*mipsIV:
2526// start-sanitize-r5900
2527*r5900:
2528// end-sanitize-r5900
2529*r3900:
2530// start-sanitize-tx19
2531*tx19:
2532// end-sanitize-tx19
2533{
055ee297
AC		 2534 int s = MASKED (GPR[RS], 4, 0);
2535 unsigned32 temp = (unsigned32) GPR[RT] >> s;
2536 GPR[RD] = EXTEND32 (temp);
f2b30012
AC		 2537}
2538
2539
2540000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2541"sub r<RD>, r<RS>, r<RT>"
2542*mipsI:
2543*mipsII:
2544*mipsIII:
2545*mipsIV:
2546// start-sanitize-r5900
2547*r5900:
2548// end-sanitize-r5900
2549*r3900:
2550// start-sanitize-tx19
2551*tx19:
2552// end-sanitize-tx19
2553{
055ee297
AC		 2554 ALU32_BEGIN (GPR[RS]);
2555 ALU32_SUB (GPR[RT]);
2556 ALU32_END (GPR[RD]);
f2b30012
AC		 2557}
2558
2559
2560000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2561"subu r<RD>, r<RS>, r<RT>"
2562*mipsI:
2563*mipsII:
2564*mipsIII:
2565*mipsIV:
2566// start-sanitize-r5900
2567*r5900:
2568// end-sanitize-r5900
2569*r3900:
2570// start-sanitize-tx19
2571*tx19:
2572// end-sanitize-tx19
2573{
055ee297 2574 GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
f2b30012
AC		 2575}
2576
2577
2578101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2579"sw r<RT>, <OFFSET>(r<BASE>)"
2580*mipsI:
2581*mipsII:
2582*mipsIII:
2583*mipsIV:
2584// start-sanitize-r5900
2585*r5900:
2586// end-sanitize-r5900
2587*r3900:
2588// start-sanitize-tx19
2589*tx19:
2590// end-sanitize-tx19
2591{
2592 unsigned32 instruction = instruction_0;
055ee297
AC		 2593 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2594 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2595 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 2596 {
2597 unsigned64 vaddr = ((unsigned64)op1 + offset);
2598 unsigned64 paddr;
2599 int uncached;
2600 if ((vaddr & 3) != 0)
055ee297 2601 SignalExceptionAddressStore();
f2b30012
AC		 2602 else
2603 {
2604 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2605 {
2606 unsigned64 memval = 0;
2607 unsigned64 memval1 = 0;
2608 unsigned64 mask = 0x7;
2609 unsigned int byte;
2610 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2611 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2612 memval = ((unsigned64) op2 << (8 * byte));
2613 {
2614 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2615 }
2616 }
2617 }
2618 }
2619}
2620
2621
085c1cb9 26221110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
f2b30012
AC		 2623"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2624*mipsI:
2625*mipsII:
2626*mipsIII:
2627*mipsIV:
2628// start-sanitize-r5900
2629*r5900:
2630// end-sanitize-r5900
2631*r3900:
2632// start-sanitize-tx19
2633*tx19:
2634// end-sanitize-tx19
2635{
2636 unsigned32 instruction = instruction_0;
055ee297
AC		 2637 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2638 int destreg = ((instruction >> 16) & 0x0000001F);
2639 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 2640 {
2641 unsigned64 vaddr = ((unsigned64)op1 + offset);
2642 unsigned64 paddr;
2643 int uncached;
2644 if ((vaddr & 3) != 0)
055ee297 2645 SignalExceptionAddressStore();
f2b30012
AC		 2646 else
2647 {
2648 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2649 {
2650 unsigned64 memval = 0;
2651 unsigned64 memval1 = 0;
2652 unsigned64 mask = 0x7;
2653 unsigned int byte;
2654 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2655 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2656 memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
2657 {
2658 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2659 }
2660 }
2661 }
2662 }
2663}
2664
2665
2666101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2667"swl r<RT>, <OFFSET>(r<BASE>)"
2668*mipsI:
2669*mipsII:
2670*mipsIII:
2671*mipsIV:
2672// start-sanitize-r5900
2673*r5900:
2674// end-sanitize-r5900
2675*r3900:
2676// start-sanitize-tx19
2677*tx19:
2678// end-sanitize-tx19
2679{
2680 unsigned32 instruction = instruction_0;
055ee297
AC		 2681 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2682 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2683 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 2684 {
2685 unsigned64 vaddr = ((unsigned64)op1 + offset);
2686 unsigned64 paddr;
2687 int uncached;
2688 {
2689 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2690 {
2691 unsigned64 memval = 0;
2692 unsigned64 memval1 = 0;
2693 unsigned64 mask = 3;
2694 unsigned int reverse = (ReverseEndian ? mask : 0);
2695 unsigned int bigend = (BigEndianCPU ? mask : 0);
2696 int byte;
2697 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2698 byte = ((vaddr & mask) ^ bigend);
2699 if (!!ByteSwapMem)
2700 paddr &= ~mask;
2701 memval = (op2 >> (8 * (3 - byte)));
2702 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
2703 memval <<= 32;
2704 }
2705 StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2706 }
2707 }
2708 }
2709}
2710
2711
2712101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
2713"swr r<RT>, <OFFSET>(r<BASE>)"
2714*mipsI:
2715*mipsII:
2716*mipsIII:
2717*mipsIV:
2718// start-sanitize-r5900
2719*r5900:
2720// end-sanitize-r5900
2721*r3900:
2722// start-sanitize-tx19
2723*tx19:
2724// end-sanitize-tx19
2725{
2726 unsigned32 instruction = instruction_0;
055ee297
AC		 2727 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2728 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2729 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 2730 {
2731 unsigned64 vaddr = ((unsigned64)op1 + offset);
2732 unsigned64 paddr;
2733 int uncached;
2734 {
2735 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2736 {
2737 unsigned64 memval = 0;
2738 unsigned64 memval1 = 0;
2739 unsigned64 mask = 3;
2740 unsigned int reverse = (ReverseEndian ? mask : 0);
2741 unsigned int bigend = (BigEndianCPU ? mask : 0);
2742 int byte;
2743 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2744 byte = ((vaddr & mask) ^ bigend);
2745 if (!ByteSwapMem)
2746 paddr &= ~mask;
2747 memval = ((unsigned64) op2 << (byte * 8));
2748 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
2749 memval <<= 32;
2750 }
2751 StoreMemory(uncached,(AccessLength_WORD - byte),memval,memval1,paddr,vaddr,isREAL);
2752 }
2753 }
2754 }
2755}
2756
2757
2758000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
2759"sync":STYPE == 0
2760"sync <STYPE>"
2761*mipsII:
2762*mipsIII:
2763*mipsIV:
2764// start-sanitize-r5900
2765*r5900:
2766// end-sanitize-r5900
2767*r3900:
2768// start-sanitize-tx19
2769*tx19:
2770// end-sanitize-tx19
2771{
085c1cb9 2772 SyncOperation (STYPE);
f2b30012
AC		 2773}
2774
2775
2776000000,20.CODE,001100:SPECIAL:32::SYSCALL
2777"syscall <CODE>"
2778*mipsI:
2779*mipsII:
2780*mipsIII:
2781*mipsIV:
2782// start-sanitize-r5900
2783*r5900:
2784// end-sanitize-r5900
2785*r3900:
2786// start-sanitize-tx19
2787*tx19:
2788// end-sanitize-tx19
2789{
055ee297 2790 SignalException(SystemCall, instruction_0);
f2b30012
AC		 2791}
2792
2793
2794000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
2795"teq r<RS>, r<RT>"
2796*mipsII:
2797*mipsIII:
2798*mipsIV:
2799// start-sanitize-r5900
2800*r5900:
2801// end-sanitize-r5900
2802*r3900:
2803// start-sanitize-tx19
2804*tx19:
2805// end-sanitize-tx19
2806{
055ee297
AC		 2807 if (GPR[RS] == GPR[RT])
2808 SignalException(Trap, instruction_0);
f2b30012
AC		 2809}
2810
2811
2812000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
2813"teqi r<RS>, <IMMEDIATE>"
2814*mipsII:
2815*mipsIII:
2816*mipsIV:
2817// start-sanitize-r5900
2818*r5900:
2819// end-sanitize-r5900
2820*r3900:
2821// start-sanitize-tx19
2822*tx19:
2823// end-sanitize-tx19
2824{
055ee297
AC		 2825 if (GPR[RS] == EXTEND16 (IMMEDIATE))
2826 SignalException(Trap, instruction_0);
f2b30012
AC		 2827}
2828
2829
2830000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
2831"tge r<RS>, r<RT>"
2832*mipsII:
2833*mipsIII:
2834*mipsIV:
2835// start-sanitize-r5900
2836*r5900:
2837// end-sanitize-r5900
2838*r3900:
2839// start-sanitize-tx19
2840*tx19:
2841// end-sanitize-tx19
2842{
055ee297
AC		 2843 if (GPR[RS] >= GPR[RT])
2844 SignalException(Trap, instruction_0);
f2b30012
AC		 2845}
2846
2847
2848000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
2849"tgei r<RS>, <IMMEDIATE>"
2850*mipsII:
2851*mipsIII:
2852*mipsIV:
2853// start-sanitize-r5900
2854*r5900:
2855// end-sanitize-r5900
2856*r3900:
2857// start-sanitize-tx19
2858*tx19:
2859// end-sanitize-tx19
2860{
055ee297
AC		 2861 if (GPR[RS] >= EXTEND16 (IMMEDIATE))
2862 SignalException(Trap, instruction_0);
f2b30012
AC		 2863}
2864
2865
2866000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
2867"tgeiu r<RS>, <IMMEDIATE>"
2868*mipsII:
2869*mipsIII:
2870*mipsIV:
2871// start-sanitize-r5900
2872*r5900:
2873// end-sanitize-r5900
2874*r3900:
2875// start-sanitize-tx19
2876*tx19:
2877// end-sanitize-tx19
2878{
055ee297
AC		 2879 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
2880 SignalException(Trap, instruction_0);
f2b30012
AC		 2881}
2882
2883
2884000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
2885"tgeu r<RS>, r<RT>"
2886*mipsII:
2887*mipsIII:
2888*mipsIV:
2889// start-sanitize-r5900
2890*r5900:
2891// end-sanitize-r5900
2892*r3900:
2893// start-sanitize-tx19
2894*tx19:
2895// end-sanitize-tx19
2896{
055ee297
AC		 2897 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
2898 SignalException(Trap, instruction_0);
f2b30012
AC		 2899}
2900
2901
2902000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
2903"tlt r<RS>, r<RT>"
2904*mipsII:
2905*mipsIII:
2906*mipsIV:
2907// start-sanitize-r5900
2908*r5900:
2909// end-sanitize-r5900
2910*r3900:
2911// start-sanitize-tx19
2912*tx19:
2913// end-sanitize-tx19
2914{
055ee297
AC		 2915 if (GPR[RS] < GPR[RT])
2916 SignalException(Trap, instruction_0);
f2b30012
AC		 2917}
2918
2919
2920000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
2921"tlti r<RS>, <IMMEDIATE>"
2922*mipsII:
2923*mipsIII:
2924*mipsIV:
2925// start-sanitize-r5900
2926*r5900:
2927// end-sanitize-r5900
2928*r3900:
2929// start-sanitize-tx19
2930*tx19:
2931// end-sanitize-tx19
2932{
055ee297
AC		 2933 if (GPR[RS] < EXTEND16 (IMMEDIATE))
2934 SignalException(Trap, instruction_0);
f2b30012
AC		 2935}
2936
2937
2938000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
2939"tltiu r<RS>, <IMMEDIATE>"
2940*mipsII:
2941*mipsIII:
2942*mipsIV:
2943// start-sanitize-r5900
2944*r5900:
2945// end-sanitize-r5900
2946*r3900:
2947// start-sanitize-tx19
2948*tx19:
2949// end-sanitize-tx19
2950{
055ee297
AC		 2951 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
2952 SignalException(Trap, instruction_0);
f2b30012
AC		 2953}
2954
2955
2956000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
2957"tltu r<RS>, r<RT>"
2958*mipsII:
2959*mipsIII:
2960*mipsIV:
2961// start-sanitize-r5900
2962*r5900:
2963// end-sanitize-r5900
2964*r3900:
2965// start-sanitize-tx19
2966*tx19:
2967// end-sanitize-tx19
2968{
055ee297
AC		 2969 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
2970 SignalException(Trap, instruction_0);
f2b30012
AC		 2971}
2972
2973
2974000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
2975"tne r<RS>, r<RT>"
2976*mipsII:
2977*mipsIII:
2978*mipsIV:
2979// start-sanitize-r5900
2980*r5900:
2981// end-sanitize-r5900
2982*r3900:
2983// start-sanitize-tx19
2984*tx19:
2985// end-sanitize-tx19
2986{
055ee297
AC		 2987 if (GPR[RS] != GPR[RT])
2988 SignalException(Trap, instruction_0);
f2b30012
AC		 2989}
2990
2991
2992000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
2993"tne r<RS>, <IMMEDIATE>"
2994*mipsII:
2995*mipsIII:
2996*mipsIV:
2997// start-sanitize-r5900
2998*r5900:
2999// end-sanitize-r5900
3000*r3900:
3001// start-sanitize-tx19
3002*tx19:
3003// end-sanitize-tx19
3004{
055ee297
AC		 3005 if (GPR[RS] != EXTEND16 (IMMEDIATE))
3006 SignalException(Trap, instruction_0);
f2b30012
AC		 3007}
3008
3009
3010000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3011"xor r<RD>, r<RS>, r<RT>"
3012*mipsI:
3013*mipsII:
3014*mipsIII:
3015*mipsIV:
3016// start-sanitize-r5900
3017*r5900:
3018// end-sanitize-r5900
3019*r3900:
3020// start-sanitize-tx19
3021*tx19:
3022// end-sanitize-tx19
3023{
055ee297 3024 GPR[RD] = GPR[RS] ^ GPR[RT];
f2b30012
AC		 3025}
3026
3027
3028001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
055ee297 3029"xori r<RT>, r<RS>, <IMMEDIATE>"
f2b30012
AC		 3030*mipsI:
3031*mipsII:
3032*mipsIII:
3033*mipsIV:
3034// start-sanitize-r5900
3035*r5900:
3036// end-sanitize-r5900
3037*r3900:
3038// start-sanitize-tx19
3039*tx19:
3040// end-sanitize-tx19
3041{
055ee297 3042 GPR[RT] = GPR[RS] ^ IMMEDIATE;
f2b30012
AC		 3043}
3044
3045\f
3046//
3047// MIPS Architecture:
3048//
3049// FPU Instruction Set (COP1 & COP1X)
3050//
3051
3052
055ee297
AC		 3053:%s:::FMT:int fmt
3054{
3055 switch (fmt)
3056 {
3057 case fmt_single: return "s";
3058 case fmt_double: return "d";
3059 case fmt_word: return "w";
3060 case fmt_long: return "l";
3061 default: return "?";
3062 }
3063}
3064
3065:%s:::TF:int tf
3066{
3067 if (tf)
3068 return "t";
3069 else
3070 return "f";
3071}
3072
3073:%s:::ND:int nd
3074{
3075 if (nd)
3076 return "l";
3077 else
3078 return "";
3079}
3080
3081:%s:::COND:int cond
3082{
3083 switch (cond)
3084 {
3085 case 00: return "f";
3086 case 01: return "un";
3087 case 02: return "eq";
3088 case 03: return "ueq";
3089 case 04: return "olt";
3090 case 05: return "ult";
3091 case 06: return "ole";
3092 case 07: return "ule";
3093 case 010: return "sf";
3094 case 011: return "ngle";
3095 case 012: return "seq";
3096 case 013: return "ngl";
3097 case 014: return "lt";
3098 case 015: return "nge";
3099 case 016: return "le";
3100 case 017: return "ngt";
3101 default: return "?";
3102 }
3103}
3104
3105
f2b30012
AC		 3106010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3107"abs.%s<FMT> f<FD>, f<FS>"
3108*mipsI:
3109*mipsII:
3110*mipsIII:
3111*mipsIV:
3112// start-sanitize-r5900
3113*r5900:
3114// end-sanitize-r5900
3115*r3900:
3116// start-sanitize-tx19
3117*tx19:
3118// end-sanitize-tx19
3119{
3120 unsigned32 instruction = instruction_0;
055ee297
AC		 3121 int destreg = ((instruction >> 6) & 0x0000001F);
3122 int fs = ((instruction >> 11) & 0x0000001F);
3123 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3124 {
3125 if ((format != fmt_single) && (format != fmt_double))
3126 SignalException(ReservedInstruction,instruction);
3127 else
3128 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3129 }
3130}
3131
3132
055ee297
AC		 3133
3134
3135010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD
f2b30012
AC		 3136"add.%s<FMT> f<FD>, f<FS>, f<FT>"
3137*mipsI:
3138*mipsII:
3139*mipsIII:
3140*mipsIV:
3141// start-sanitize-r5900
3142*r5900:
3143// end-sanitize-r5900
3144*r3900:
3145// start-sanitize-tx19
3146*tx19:
3147// end-sanitize-tx19
3148{
3149 unsigned32 instruction = instruction_0;
055ee297
AC		 3150 int destreg = ((instruction >> 6) & 0x0000001F);
3151 int fs = ((instruction >> 11) & 0x0000001F);
3152 int ft = ((instruction >> 16) & 0x0000001F);
3153 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3154 {
3155 if ((format != fmt_single) && (format != fmt_double))
055ee297 3156 SignalException(ReservedInstruction, instruction);
f2b30012
AC		 3157 else
3158 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3159 }
3160}
3161
3162
3163//
3164// FIXME: This does not correctly resolve mipsI-mipsIV differences.
3165//
3166// BC1F
3167// BC1FL
3168// BC1T
3169// BC1TL
055ee297
AC		 3170010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3171"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3172"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
f2b30012
AC		 3173*mipsI:
3174*mipsII:
3175*mipsIII:
3176*mipsIV:
3177// start-sanitize-r5900
3178*r5900:
3179// end-sanitize-r5900
3180*r3900:
3181// start-sanitize-tx19
3182*tx19:
3183// end-sanitize-tx19
3184{
3185 unsigned32 instruction = instruction_0;
055ee297
AC		 3186 signed_word offset = SIGNEXTEND((signed_word)(((instruction >> 0) & 0x0000FFFF) << 2),18);
3187 int boolean = ((instruction >> 16) & 0x00000001);
3188 int likely = ((instruction >> 17) & 0x00000001);
3189 int condition_code = ((instruction >> 18) & 0x00000007);
f2b30012
AC		 3190 {
3191 if (condition_code != 0)
3192 SignalException(ReservedInstruction,instruction);
3193 else {
3194 int condition = (PREVCOC1() == boolean);
3195 /* NOTE: The branch occurs AFTER the next instruction has been executed */
3196 if (condition) {
3197 DSPC = (PC + offset);
f2b30012
AC		 3198 }
3199 else if (likely) {
055ee297 3200 NULLIFY_NIA ();
f2b30012
AC		 3201 }
3202 }
3203 }
3204}
3205
3206
3207//
3208// FIXME: This does not correctly differentiate between mips*
3209//
3210010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3211"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3212"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3213*mipsI:
3214*mipsII:
3215*mipsIII:
3216*mipsIV:
3217// start-sanitize-r5900
3218*r5900:
3219// end-sanitize-r5900
3220*r3900:
3221// start-sanitize-tx19
3222*tx19:
3223// end-sanitize-tx19
3224{
3225 unsigned32 instruction = instruction_0;
055ee297
AC		 3226 int cmpflags = ((instruction >> 0) & 0x0000000F);
3227 int condition_code = ((instruction >> 8) & 0x00000007);
3228 int fs = ((instruction >> 11) & 0x0000001F);
3229 int ft = ((instruction >> 16) & 0x0000001F);
3230 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3231 if (condition_code != 0)
3232 {
3233 SignalException(ReservedInstruction,instruction);
3234 }
3235 else
3236 {
3237 if ((format != fmt_single) && (format != fmt_double))
3238 SignalException(ReservedInstruction,instruction);
3239 else {
3240 if (condition_code != 0)
3241 SignalException(ReservedInstruction,instruction);
3242 else
3243 {
3244 int ignore = 0;
3245 int less = 0;
3246 int equal = 0;
3247 int unordered = 1;
3248 unsigned64 ofs = ValueFPR(fs,format);
3249 unsigned64 oft = ValueFPR(ft,format);
3250 if (NaN(ofs,format) || NaN(oft,format)) {
3251 if (FCSR & FP_ENABLE(IO)) {
3252 FCSR |= FP_CAUSE(IO);
055ee297 3253 SignalExceptionFPE();
f2b30012
AC		 3254 ignore = 1;
3255 }
3256 } else {
3257 less = Less(ofs,oft,format);
3258 equal = Equal(ofs,oft,format);
3259 unordered = 0;
3260 }
3261 if (!ignore) {
3262 int condition = (((cmpflags & (1 << 2)) && less) || ((cmpflags & (1 << 1)) && equal) || ((cmpflags & (1 << 0)) && unordered));
3263 SETFCC(condition_code,condition);
3264 }
3265 }
3266 }
3267 }
3268}
3269
3270
3271010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3272"ceil.l.%s<FMT> f<FD>, f<FS>"
3273*mipsIII:
3274*mipsIV:
3275// start-sanitize-r5900
3276*r5900:
3277// end-sanitize-r5900
3278*r3900:
3279// start-sanitize-tx19
3280*tx19:
3281// end-sanitize-tx19
3282{
3283 unsigned32 instruction = instruction_0;
055ee297
AC		 3284 int destreg = ((instruction >> 6) & 0x0000001F);
3285 int fs = ((instruction >> 11) & 0x0000001F);
3286 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3287 {
3288 if ((format != fmt_single) && (format != fmt_double))
3289 SignalException(ReservedInstruction,instruction);
3290 else
3291 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3292 }
3293}
3294
3295
3296010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3297*mipsII:
3298*mipsIII:
3299*mipsIV:
3300// start-sanitize-r5900
3301*r5900:
3302// end-sanitize-r5900
3303*r3900:
3304// start-sanitize-tx19
3305*tx19:
3306// end-sanitize-tx19
3307{
3308 unsigned32 instruction = instruction_0;
055ee297
AC		 3309 int destreg = ((instruction >> 6) & 0x0000001F);
3310 int fs = ((instruction >> 11) & 0x0000001F);
3311 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3312 {
3313 if ((format != fmt_single) && (format != fmt_double))
3314 SignalException(ReservedInstruction,instruction);
3315 else
3316 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3317 }
3318}
3319
3320
3321// CFC1
3322// CTC1
332301000100,x,10,kkkkk,vvvvv,00000000000:COP1S:32::CxC1
3324*mipsI:
3325*mipsII:
3326*mipsIII:
3327*mipsIV:
3328// start-sanitize-r5900
3329*r5900:
3330// end-sanitize-r5900
3331*r3900:
3332// start-sanitize-tx19
3333*tx19:
3334// end-sanitize-tx19
3335{
3336 unsigned32 instruction = instruction_0;
055ee297
AC		 3337 int fs = ((instruction >> 11) & 0x0000001F);
3338 int ft = ((instruction >> 16) & 0x0000001F);
3339 int to = ((instruction >> 23) & 0x00000001);
f2b30012
AC		 3340 {
3341 if (to) {
3342 if (fs == 0) {
3343 PENDING_FILL((fs + FCR0IDX),VL4_8(GPR[ft]));
3344 } else if (fs == 31) {
3345 PENDING_FILL((fs + FCR31IDX),VL4_8(GPR[ft]));
3346 } /* else NOP */
3347 PENDING_FILL(COCIDX,0); /* special case */
3348 } else { /* control from */
3349 if (fs == 0) {
3350 PENDING_FILL(ft,SIGNEXTEND(FCR0,32));
3351 } else if (fs == 31) {
3352 PENDING_FILL(ft,SIGNEXTEND(FCR31,32));
3353 } /* else NOP */
3354 }
3355 }
3356}
3357
3358
3359//
3360// FIXME: Does not correctly differentiate between mips*
3361//
3362010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
3363"cvt.d.%s<FMT> f<FD>, f<FS>"
3364*mipsI:
3365*mipsII:
3366*mipsIII:
3367*mipsIV:
3368// start-sanitize-r5900
3369*r5900:
3370// end-sanitize-r5900
3371*r3900:
3372// start-sanitize-tx19
3373*tx19:
3374// end-sanitize-tx19
3375{
3376 unsigned32 instruction = instruction_0;
055ee297
AC		 3377 int destreg = ((instruction >> 6) & 0x0000001F);
3378 int fs = ((instruction >> 11) & 0x0000001F);
3379 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3380 {
3381 if ((format == fmt_double) | 0)
3382 SignalException(ReservedInstruction,instruction);
3383 else
3384 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
3385 }
3386}
3387
3388
3389010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
3390"cvt.l.%s<FMT> f<FD>, f<FS>"
3391*mipsIII:
3392*mipsIV:
3393// start-sanitize-r5900
3394*r5900:
3395// end-sanitize-r5900
3396*r3900:
3397// start-sanitize-tx19
3398*tx19:
3399// end-sanitize-tx19
3400{
3401 unsigned32 instruction = instruction_0;
055ee297
AC		 3402 int destreg = ((instruction >> 6) & 0x0000001F);
3403 int fs = ((instruction >> 11) & 0x0000001F);
3404 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3405 {
3406 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
3407 SignalException(ReservedInstruction,instruction);
3408 else
3409 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
3410 }
3411}
3412
3413
3414//
3415// FIXME: Does not correctly differentiate between mips*
3416//
3417010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
3418"cvt.s.%s<FMT> f<FD>, f<FS>"
3419*mipsI:
3420*mipsII:
3421*mipsIII:
3422*mipsIV:
3423// start-sanitize-r5900
3424*r5900:
3425// end-sanitize-r5900
3426*r3900:
3427// start-sanitize-tx19
3428*tx19:
3429// end-sanitize-tx19
3430{
3431 unsigned32 instruction = instruction_0;
055ee297
AC		 3432 int destreg = ((instruction >> 6) & 0x0000001F);
3433 int fs = ((instruction >> 11) & 0x0000001F);
3434 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3435 {
3436 if ((format == fmt_single) | 0)
3437 SignalException(ReservedInstruction,instruction);
3438 else
3439 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
3440 }
3441}
3442
3443
3444010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
3445"cvt.w.%s<FMT> f<FD>, f<FS>"
3446*mipsI:
3447*mipsII:
3448*mipsIII:
3449*mipsIV:
3450// start-sanitize-r5900
3451*r5900:
3452// end-sanitize-r5900
3453*r3900:
3454// start-sanitize-tx19
3455*tx19:
3456// end-sanitize-tx19
3457{
3458 unsigned32 instruction = instruction_0;
055ee297
AC		 3459 int destreg = ((instruction >> 6) & 0x0000001F);
3460 int fs = ((instruction >> 11) & 0x0000001F);
3461 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3462 {
3463 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
3464 SignalException(ReservedInstruction,instruction);
3465 else
3466 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
3467 }
3468}
3469
3470
3471010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
3472"div.%s<FMT> f<FD>, f<FS>, f<FT>"
3473*mipsI:
3474*mipsII:
3475*mipsIII:
3476*mipsIV:
3477// start-sanitize-r5900
3478*r5900:
3479// end-sanitize-r5900
3480*r3900:
3481// start-sanitize-tx19
3482*tx19:
3483// end-sanitize-tx19
3484{
3485 unsigned32 instruction = instruction_0;
055ee297
AC		 3486 int destreg = ((instruction >> 6) & 0x0000001F);
3487 int fs = ((instruction >> 11) & 0x0000001F);
3488 int ft = ((instruction >> 16) & 0x0000001F);
3489 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3490 {
3491 if ((format != fmt_single) && (format != fmt_double))
3492 SignalException(ReservedInstruction,instruction);
3493 else
3494 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3495 }
3496}
3497
3498
3499// DMFC1
3500// DMTC1
350101000100,x,01,5.FT,vvvvv,00000000000:COP1S:64::DMxC1
3502*mipsIII:
3503*mipsIV:
3504// start-sanitize-r5900
3505*r5900:
3506// end-sanitize-r5900
3507*r3900:
3508// start-sanitize-tx19
3509*tx19:
3510// end-sanitize-tx19
3511{
3512 unsigned32 instruction = instruction_0;
055ee297
AC		 3513 int fs = ((instruction >> 11) & 0x0000001F);
3514 int ft = ((instruction >> 16) & 0x0000001F);
3515 int to = ((instruction >> 23) & 0x00000001);
f2b30012
AC		 3516 {
3517 if (to) {
3518 if (SizeFGR() == 64) {
3519 PENDING_FILL((fs + FGRIDX),GPR[ft]);
3520 } else
3521 if ((fs & 0x1) == 0)
3522 {
3523 PENDING_FILL(((fs + 1) + FGRIDX),VH4_8(GPR[ft]));
3524 PENDING_FILL((fs + FGRIDX),VL4_8(GPR[ft]));
3525 }
3526 } else {
3527 if (SizeFGR() == 64) {
3528 PENDING_FILL(ft,FGR[fs]);
3529 } else
3530 if ((fs & 0x1) == 0) {
3531 PENDING_FILL(ft,(SET64HI(FGR[fs+1]) | FGR[fs]));
3532 } else {
3533 PENDING_FILL(ft,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3534 }
3535 }
3536 }
3537}
3538
3539
3540010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
3541"floor.l.%s<FMT> f<FD>, f<FS>"
3542*mipsIII:
3543*mipsIV:
3544// start-sanitize-r5900
3545*r5900:
3546// end-sanitize-r5900
3547*r3900:
3548// start-sanitize-tx19
3549*tx19:
3550// end-sanitize-tx19
3551{
3552 unsigned32 instruction = instruction_0;
055ee297
AC		 3553 int destreg = ((instruction >> 6) & 0x0000001F);
3554 int fs = ((instruction >> 11) & 0x0000001F);
3555 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3556 {
3557 if ((format != fmt_single) && (format != fmt_double))
3558 SignalException(ReservedInstruction,instruction);
3559 else
3560 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
3561 }
3562}
3563
3564
3565010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
3566"floor.w.%s<FMT> f<FD>, f<FS>"
3567*mipsII:
3568*mipsIII:
3569*mipsIV:
3570// start-sanitize-r5900
3571*r5900:
3572// end-sanitize-r5900
3573*r3900:
3574// start-sanitize-tx19
3575*tx19:
3576// end-sanitize-tx19
3577{
3578 unsigned32 instruction = instruction_0;
055ee297
AC		 3579 int destreg = ((instruction >> 6) & 0x0000001F);
3580 int fs = ((instruction >> 11) & 0x0000001F);
3581 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3582 {
3583 if ((format != fmt_single) && (format != fmt_double))
3584 SignalException(ReservedInstruction,instruction);
3585 else
3586 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
3587 }
3588}
3589
3590
3591// LDC1
3592110101,5.BASE,5.FT,16.OFFSET:COP1:32::LDC1
3593
3594
3595010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
3596"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3597*mipsIV:
3598// start-sanitize-r5900
3599*r5900:
3600// end-sanitize-r5900
3601{
3602 unsigned32 instruction = instruction_0;
055ee297
AC		 3603 int destreg = ((instruction >> 6) & 0x0000001F);
3604 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3605 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 3606 {
3607 unsigned64 vaddr = ((unsigned64)op1 + op2);
3608 unsigned64 paddr;
3609 int uncached;
3610 if ((vaddr & 7) != 0)
055ee297 3611 SignalExceptionAddressLoad();
f2b30012
AC		 3612 else
3613 {
3614 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3615 {
3616 unsigned64 memval = 0;
3617 unsigned64 memval1 = 0;
f2b30012
AC		 3618 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
3619 COP_LD(1,destreg,memval);;
3620 }
3621 }
3622 }
3623}
3624
3625
3626// LWC1
3627110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
3628
3629
3630010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
3631"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
3632*mipsIV:
3633// start-sanitize-r5900
3634*r5900:
3635// end-sanitize-r5900
3636{
3637 unsigned32 instruction = instruction_0;
055ee297
AC		 3638 int destreg = ((instruction >> 6) & 0x0000001F);
3639 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3640 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 3641 {
3642 unsigned64 vaddr = ((unsigned64)op1 + op2);
3643 unsigned64 paddr;
3644 int uncached;
3645 if ((vaddr & 3) != 0)
055ee297 3646 SignalExceptionAddressLoad();
f2b30012
AC		 3647 else
3648 {
3649 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3650 {
3651 unsigned64 memval = 0;
3652 unsigned64 memval1 = 0;
3653 unsigned64 mask = 0x7;
3654 unsigned int shift = 2;
055ee297
AC		 3655 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
3656 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
3657 unsigned int byte;
f2b30012
AC		 3658 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
3659 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
3660 byte = ((vaddr & mask) ^ (bigend << shift));
3661 COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
3662 }
3663 }
3664 }
3665}
3666
3667
3668
3669//
3670// FIXME: Not correct for mips*
3671//
3672010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D
3673"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
3674*mipsIV:
3675// start-sanitize-r5900
3676*r5900:
3677// end-sanitize-r5900
3678{
3679 unsigned32 instruction = instruction_0;
055ee297
AC		 3680 int destreg = ((instruction >> 6) & 0x0000001F);
3681 int fs = ((instruction >> 11) & 0x0000001F);
3682 int ft = ((instruction >> 16) & 0x0000001F);
3683 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 3684 {
3685 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3686 }
3687}
3688
3689
3690010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S
3691"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
3692*mipsIV:
3693// start-sanitize-r5900
3694*r5900:
3695// end-sanitize-r5900
3696{
3697 unsigned32 instruction = instruction_0;
055ee297
AC		 3698 int destreg = ((instruction >> 6) & 0x0000001F);
3699 int fs = ((instruction >> 11) & 0x0000001F);
3700 int ft = ((instruction >> 16) & 0x0000001F);
3701 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 3702 {
3703 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3704 }
3705}
3706
3707
3708// MFC1
3709010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
055ee297 3710"m<X>c1 r<RT>, f<FS>"
f2b30012
AC		 3711*mipsI:
3712*mipsII:
3713*mipsIII:
3714*mipsIV:
3715// start-sanitize-r5900
3716*r5900:
3717// end-sanitize-r5900
3718*r3900:
3719// start-sanitize-tx19
3720*tx19:
3721// end-sanitize-tx19
3722{
3723 unsigned32 instruction = instruction_0;
055ee297
AC		 3724 int fs = ((instruction >> 11) & 0x0000001F);
3725 int ft = ((instruction >> 16) & 0x0000001F);
3726 int to = ((instruction >> 23) & 0x00000001);
f2b30012
AC		 3727 {
3728 if (to) {
3729 if (SizeFGR() == 64) {
055ee297 3730 PENDING_FILL ((fs + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[ft])));
f2b30012 3731 } else {
055ee297 3732 PENDING_FILL ((fs + FGRIDX), VL4_8(GPR[ft]));
f2b30012
AC		 3733 }
3734 } else {
055ee297 3735 PENDING_FILL (ft, SIGNEXTEND(FGR[fs],32));
f2b30012
AC		 3736 }
3737 }
3738}
3739
3740
3741010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
3742"mov.%s<FMT> f<FD>, f<FS>"
3743*mipsI:
3744*mipsII:
3745*mipsIII:
3746*mipsIV:
3747// start-sanitize-r5900
3748*r5900:
3749// end-sanitize-r5900
3750*r3900:
3751// start-sanitize-tx19
3752*tx19:
3753// end-sanitize-tx19
3754{
3755 unsigned32 instruction = instruction_0;
055ee297
AC		 3756 int destreg = ((instruction >> 6) & 0x0000001F);
3757 int fs = ((instruction >> 11) & 0x0000001F);
3758 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3759 {
3760 StoreFPR(destreg,format,ValueFPR(fs,format));
3761 }
3762}
3763
3764
3765// MOVF
3766000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
055ee297 3767"mov%s<TF> r<RD>, r<RS>, <CC>"
f2b30012
AC		 3768*mipsIV:
3769// start-sanitize-r5900
3770*r5900:
3771// end-sanitize-r5900
3772{
055ee297
AC		 3773 if (GETFCC(CC) == TF)
3774 GPR[RD] = GPR[RS];
f2b30012
AC		 3775}
3776
3777
3778// MOVF.fmt
3779010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
055ee297 3780"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
f2b30012
AC		 3781*mipsIV:
3782// start-sanitize-r5900
3783*r5900:
3784// end-sanitize-r5900
3785{
3786 unsigned32 instruction = instruction_0;
055ee297 3787 int format = ((instruction >> 21) & 0x00000007);
f2b30012 3788 {
055ee297
AC		 3789 if (GETFCC(CC) == TF)
3790 StoreFPR (FD, format, ValueFPR (FS, format));
f2b30012 3791 else
055ee297 3792 StoreFPR (FD, format, ValueFPR (FD, format));
f2b30012
AC		 3793 }
3794}
3795
3796
3797010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
3798*mipsIV:
3799// start-sanitize-r5900
3800*r5900:
3801// end-sanitize-r5900
3802{
3803 unsigned32 instruction = instruction_0;
055ee297
AC		 3804 int destreg = ((instruction >> 6) & 0x0000001F);
3805 int fs = ((instruction >> 11) & 0x0000001F);
3806 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3807 {
3808 StoreFPR(destreg,format,ValueFPR(fs,format));
3809 }
3810}
3811
3812
3813// MOVT see MOVtf
3814
3815
3816// MOVT.fmt see MOVtf.fmt
3817
3818
3819
3820010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
3821"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
3822*mipsIV:
3823// start-sanitize-r5900
3824*r5900:
3825// end-sanitize-r5900
3826{
3827 unsigned32 instruction = instruction_0;
055ee297
AC		 3828 int destreg = ((instruction >> 6) & 0x0000001F);
3829 int fs = ((instruction >> 11) & 0x0000001F);
3830 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3831 {
3832 StoreFPR(destreg,format,ValueFPR(fs,format));
3833 }
3834}
3835
3836
3837// MSUB.fmt
3838010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
3839"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
3840*mipsIV:
3841// start-sanitize-r5900
3842*r5900:
3843// end-sanitize-r5900
3844{
3845 unsigned32 instruction = instruction_0;
055ee297
AC		 3846 int destreg = ((instruction >> 6) & 0x0000001F);
3847 int fs = ((instruction >> 11) & 0x0000001F);
3848 int ft = ((instruction >> 16) & 0x0000001F);
3849 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 3850 {
3851 StoreFPR(destreg,fmt_double,(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3852 }
3853}
3854
3855
3856// MSUB.fmt
055ee297 3857010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
f2b30012
AC		 3858"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
3859*mipsIV:
3860// start-sanitize-r5900
3861*r5900:
3862// end-sanitize-r5900
3863{
3864 unsigned32 instruction = instruction_0;
055ee297
AC		 3865 int destreg = ((instruction >> 6) & 0x0000001F);
3866 int fs = ((instruction >> 11) & 0x0000001F);
3867 int ft = ((instruction >> 16) & 0x0000001F);
3868 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 3869 {
3870 StoreFPR(destreg,fmt_single,(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3871 }
3872}
3873
3874
3875// MTC1 see MxC1
3876
3877
3878010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
3879"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
3880*mipsI:
3881*mipsII:
3882*mipsIII:
3883*mipsIV:
3884// start-sanitize-r5900
3885*r5900:
3886// end-sanitize-r5900
3887*r3900:
3888// start-sanitize-tx19
3889*tx19:
3890// end-sanitize-tx19
3891{
3892 unsigned32 instruction = instruction_0;
055ee297
AC		 3893 int destreg = ((instruction >> 6) & 0x0000001F);
3894 int fs = ((instruction >> 11) & 0x0000001F);
3895 int ft = ((instruction >> 16) & 0x0000001F);
3896 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3897 {
3898 if ((format != fmt_single) && (format != fmt_double))
3899 SignalException(ReservedInstruction,instruction);
3900 else
3901 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
3902 }
3903}
3904
3905
3906010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
3907"neg.%s<FMT> f<FD>, f<FS>"
3908*mipsI:
3909*mipsII:
3910*mipsIII:
3911*mipsIV:
3912// start-sanitize-r5900
3913*r5900:
3914// end-sanitize-r5900
3915*r3900:
3916// start-sanitize-tx19
3917*tx19:
3918// end-sanitize-tx19
3919{
3920 unsigned32 instruction = instruction_0;
055ee297
AC		 3921 int destreg = ((instruction >> 6) & 0x0000001F);
3922 int fs = ((instruction >> 11) & 0x0000001F);
3923 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3924 {
3925 if ((format != fmt_single) && (format != fmt_double))
3926 SignalException(ReservedInstruction,instruction);
3927 else
3928 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
3929 }
3930}
3931
3932
3933// NMADD.fmt
3934010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
3935"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
3936*mipsIV:
3937{
3938 unsigned32 instruction = instruction_0;
055ee297
AC		 3939 int destreg = ((instruction >> 6) & 0x0000001F);
3940 int fs = ((instruction >> 11) & 0x0000001F);
3941 int ft = ((instruction >> 16) & 0x0000001F);
3942 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 3943 {
3944 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3945 }
3946}
3947
3948
3949// NMADD.fmt
3950010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
3951"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
3952*mipsIV:
3953{
3954 unsigned32 instruction = instruction_0;
055ee297
AC		 3955 int destreg = ((instruction >> 6) & 0x0000001F);
3956 int fs = ((instruction >> 11) & 0x0000001F);
3957 int ft = ((instruction >> 16) & 0x0000001F);
3958 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 3959 {
3960 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3961 }
3962}
3963
3964
3965// NMSUB.fmt
055ee297 3966010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
f2b30012
AC		 3967"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
3968*mipsIV:
3969{
3970 unsigned32 instruction = instruction_0;
055ee297
AC		 3971 int destreg = ((instruction >> 6) & 0x0000001F);
3972 int fs = ((instruction >> 11) & 0x0000001F);
3973 int ft = ((instruction >> 16) & 0x0000001F);
3974 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 3975 {
3976 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3977 }
3978}
3979
3980
3981// NMSUB.fmt
055ee297 3982010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
f2b30012
AC		 3983"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
3984*mipsIV:
3985{
3986 unsigned32 instruction = instruction_0;
055ee297
AC		 3987 int destreg = ((instruction >> 6) & 0x0000001F);
3988 int fs = ((instruction >> 11) & 0x0000001F);
3989 int ft = ((instruction >> 16) & 0x0000001F);
3990 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 3991 {
3992 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3993 }
3994}
3995
3996
3997010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
49a6eed5 3998"prefx <HINT>, r<INDEX>(r<BASE>)"
f2b30012
AC		 3999*mipsIV:
4000{
4001 unsigned32 instruction = instruction_0;
055ee297
AC		 4002 int fs = ((instruction >> 11) & 0x0000001F);
4003 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4004 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 4005 {
4006 unsigned64 vaddr = ((unsigned64)op1 + (unsigned64)op2);
4007 unsigned64 paddr;
4008 int uncached;
4009 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4010 Prefetch(uncached,paddr,vaddr,isDATA,fs);
4011 }
4012}
4013
4014010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4015*mipsIV:
4016"recip.%s<FMT> f<FD>, f<FS>"
4017{
4018 unsigned32 instruction = instruction_0;
055ee297
AC		 4019 int destreg = ((instruction >> 6) & 0x0000001F);
4020 int fs = ((instruction >> 11) & 0x0000001F);
4021 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4022 {
4023 if ((format != fmt_single) && (format != fmt_double))
4024 SignalException(ReservedInstruction,instruction);
4025 else
4026 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4027 }
4028}
4029
4030
4031010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
49a6eed5 4032"round.l.%s<FMT> f<FD>, f<FS>"
f2b30012
AC		 4033*mipsIII:
4034*mipsIV:
4035// start-sanitize-r5900
4036*r5900:
4037// end-sanitize-r5900
4038*r3900:
4039// start-sanitize-tx19
4040*tx19:
4041// end-sanitize-tx19
4042{
4043 unsigned32 instruction = instruction_0;
055ee297
AC		 4044 int destreg = ((instruction >> 6) & 0x0000001F);
4045 int fs = ((instruction >> 11) & 0x0000001F);
4046 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4047 {
4048 if ((format != fmt_single) && (format != fmt_double))
4049 SignalException(ReservedInstruction,instruction);
4050 else
4051 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4052 }
4053}
4054
4055
4056010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
49a6eed5 4057"round.w.%s<FMT> f<FD>, f<FS>"
f2b30012
AC		 4058*mipsII:
4059*mipsIII:
4060*mipsIV:
4061// start-sanitize-r5900
4062*r5900:
4063// end-sanitize-r5900
4064*r3900:
4065// start-sanitize-tx19
4066*tx19:
4067// end-sanitize-tx19
4068{
4069 unsigned32 instruction = instruction_0;
055ee297
AC		 4070 int destreg = ((instruction >> 6) & 0x0000001F);
4071 int fs = ((instruction >> 11) & 0x0000001F);
4072 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4073 {
4074 if ((format != fmt_single) && (format != fmt_double))
4075 SignalException(ReservedInstruction,instruction);
4076 else
4077 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4078 }
4079}
4080
4081
4082010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4083*mipsIV:
4084"rsqrt.%s<FMT> f<FD>, f<FS>"
4085{
4086 unsigned32 instruction = instruction_0;
055ee297
AC		 4087 int destreg = ((instruction >> 6) & 0x0000001F);
4088 int fs = ((instruction >> 11) & 0x0000001F);
4089 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4090 {
4091 if ((format != fmt_single) && (format != fmt_double))
4092 SignalException(ReservedInstruction,instruction);
4093 else
085c1cb9 4094 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
f2b30012
AC		 4095 }
4096}
4097
4098
4099// SDC1
4100
4101
4102010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
4103*mipsIV:
4104// start-sanitize-r5900
4105*r5900:
4106// end-sanitize-r5900
4107{
4108 unsigned32 instruction = instruction_0;
055ee297
AC		 4109 int fs = ((instruction >> 11) & 0x0000001F);
4110 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4111 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 4112 {
4113 unsigned64 vaddr = ((unsigned64)op1 + op2);
4114 unsigned64 paddr;
4115 int uncached;
4116 if ((vaddr & 7) != 0)
055ee297 4117 SignalExceptionAddressStore();
f2b30012
AC		 4118 else
4119 {
4120 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4121 {
4122 unsigned64 memval = 0;
4123 unsigned64 memval1 = 0;
4124 memval = (unsigned64)COP_SD(1,fs);
4125 {
4126 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
4127 }
4128 }
4129 }
4130 }
4131}
4132
4133
4134010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
4135"sqrt.%s<FMT> f<FD>, f<FS>"
4136*mipsII:
4137*mipsIII:
4138*mipsIV:
4139// start-sanitize-r5900
4140*r5900:
4141// end-sanitize-r5900
4142*r3900:
4143// start-sanitize-tx19
4144*tx19:
4145// end-sanitize-tx19
4146{
4147 unsigned32 instruction = instruction_0;
055ee297
AC		 4148 int destreg = ((instruction >> 6) & 0x0000001F);
4149 int fs = ((instruction >> 11) & 0x0000001F);
4150 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4151 {
4152 if ((format != fmt_single) && (format != fmt_double))
4153 SignalException(ReservedInstruction,instruction);
4154 else
4155 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4156 }
4157}
4158
4159
4160010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
4161"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4162*mipsI:
4163*mipsII:
4164*mipsIII:
4165*mipsIV:
4166// start-sanitize-r5900
4167*r5900:
4168// end-sanitize-r5900
4169*r3900:
4170// start-sanitize-tx19
4171*tx19:
4172// end-sanitize-tx19
4173{
4174 unsigned32 instruction = instruction_0;
055ee297
AC		 4175 int destreg = ((instruction >> 6) & 0x0000001F);
4176 int fs = ((instruction >> 11) & 0x0000001F);
4177 int ft = ((instruction >> 16) & 0x0000001F);
4178 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4179 {
4180 if ((format != fmt_single) && (format != fmt_double))
4181 SignalException(ReservedInstruction,instruction);
4182 else
4183 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4184 }
4185}
4186
4187
4188// SWC1
4189
4190
085c1cb9
AC		 4191010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
4192"swxc1 f<FS>, r<INDEX>(r<BASE>)"
f2b30012
AC		 4193*mipsIV:
4194// start-sanitize-r5900
4195*r5900:
4196// end-sanitize-r5900
4197{
4198 unsigned32 instruction = instruction_0;
055ee297
AC		 4199 int fs = ((instruction >> 11) & 0x0000001F);
4200 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4201 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 4202 {
4203 unsigned64 vaddr = ((unsigned64)op1 + op2);
4204 unsigned64 paddr;
4205 int uncached;
4206 if ((vaddr & 3) != 0)
055ee297 4207 SignalExceptionAddressStore();
f2b30012
AC		 4208 else
4209 {
4210 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4211 {
4212 unsigned64 memval = 0;
4213 unsigned64 memval1 = 0;
4214 unsigned64 mask = 0x7;
4215 unsigned int byte;
4216 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4217 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4218 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
4219 {
4220 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4221 }
4222 }
4223 }
4224 }
4225}
4226
4227
4228010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
4229"trunc.l.%s<FMT> f<FD>, f<FS>"
4230*mipsIII:
4231*mipsIV:
4232// start-sanitize-r5900
4233*r5900:
4234// end-sanitize-r5900
4235*r3900:
4236// start-sanitize-tx19
4237*tx19:
4238// end-sanitize-tx19
4239{
4240 unsigned32 instruction = instruction_0;
055ee297
AC		 4241 int destreg = ((instruction >> 6) & 0x0000001F);
4242 int fs = ((instruction >> 11) & 0x0000001F);
4243 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4244 {
4245 if ((format != fmt_single) && (format != fmt_double))
4246 SignalException(ReservedInstruction,instruction);
4247 else
4248 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
4249 }
4250}
4251
4252
4253010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
4254"trunc.w.%s<FMT> f<FD>, f<FS>"
4255*mipsII:
4256*mipsIII:
4257*mipsIV:
4258// start-sanitize-r5900
4259*r5900:
4260// end-sanitize-r5900
4261*r3900:
4262// start-sanitize-tx19
4263*tx19:
4264// end-sanitize-tx19
4265{
4266 unsigned32 instruction = instruction_0;
055ee297
AC		 4267 int destreg = ((instruction >> 6) & 0x0000001F);
4268 int fs = ((instruction >> 11) & 0x0000001F);
4269 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4270 {
4271 if ((format != fmt_single) && (format != fmt_double))
4272 SignalException(ReservedInstruction,instruction);
4273 else
4274 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
4275 }
4276}
4277
4278\f
4279//
4280// MIPS Architecture:
4281//
4282// System Control Instruction Set (COP0)
4283//
4284
4285
4286010000,01000,00000,16.OFFSET:COP0:32::BC0F
4287"bc0f <OFFSET>"
4288*mipsI:
4289*mipsII:
4290*mipsIII:
4291*mipsIV:
4292// start-sanitize-r5900
4293*r5900:
4294// end-sanitize-r5900
4295
4296
4297010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4298"bc0fl <OFFSET>"
4299*mipsI:
4300*mipsII:
4301*mipsIII:
4302*mipsIV:
4303// start-sanitize-r5900
4304*r5900:
4305// end-sanitize-r5900
4306
4307
4308010000,01000,00001,16.OFFSET:COP0:32::BC0T
4309"bc0t <OFFSET>"
4310*mipsI:
4311*mipsII:
4312*mipsIII:
4313*mipsIV:
4314// start-sanitize-r5900
4315*r5900:
4316// end-sanitize-r5900
4317
4318
4319
49a6eed5 4320010000,01000,00011,16.OFFSET:COP0:32::BC0TL
f2b30012
AC		 4321"bc0tl <OFFSET>"
4322*mipsI:
4323*mipsII:
4324*mipsIII:
4325*mipsIV:
4326// start-sanitize-r5900
4327*r5900:
4328// end-sanitize-r5900
4329
4330
4331101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4332*mipsIII:
4333*mipsIV:
4334// start-sanitize-r5900
4335*r5900:
4336// end-sanitize-r5900
4337*r3900:
4338// start-sanitize-tx19
4339*tx19:
4340// end-sanitize-tx19
4341{
4342 unsigned32 instruction = instruction_0;
055ee297
AC		 4343 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
4344 int hint = ((instruction >> 16) & 0x0000001F);
4345 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 4346 {
4347 unsigned64 vaddr = (op1 + offset);
4348 unsigned64 paddr;
4349 int uncached;
4350 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4351 CacheOp(hint,vaddr,paddr,instruction);
4352 }
4353}
4354
4355
4356010000,10000,000000000000000,111001:COP0:32::DI
4357"di"
4358*mipsI:
4359*mipsII:
4360*mipsIII:
4361*mipsIV:
4362// start-sanitize-r5900
4363*r5900:
4364// end-sanitize-r5900
4365
4366
4367010000,10000,000000000000000,111000:COP0:32::EI
4368"ei"
4369*mipsI:
4370*mipsII:
4371*mipsIII:
4372*mipsIV:
4373// start-sanitize-r5900
4374*r5900:
4375// end-sanitize-r5900
4376
4377
4378010000,10000,000000000000000,011000:COP0:32::ERET
4379"eret"
4380*mipsIII:
4381*mipsIV:
4382// start-sanitize-r5900
4383*r5900:
4384// end-sanitize-r5900
4385
4386
49a6eed5
AC		 4387010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4388"mfc0 r<RT>, r<RD> # <REGX>"
f2b30012
AC		 4389*mipsI:
4390*mipsII:
4391*mipsIII:
4392*mipsIV:
4393// start-sanitize-r5900
4394*r5900:
4395// end-sanitize-r5900
4396
4397
49a6eed5
AC		 4398010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4399"mtc0 r<RT>, r<RD> # <REGX>"
f2b30012
AC		 4400*mipsI:
4401*mipsII:
4402*mipsIII:
4403*mipsIV:
4404// start-sanitize-r5900
4405*r5900:
4406// end-sanitize-r5900
4407
4408
4409010000,10000,000000000000000,001000:COP0:32::TLBP
4410"tlbp"
4411*mipsI:
4412*mipsII:
4413*mipsIII:
4414*mipsIV:
4415// start-sanitize-r5900
4416*r5900:
4417// end-sanitize-r5900
4418
4419
4420010000,10000,000000000000000,000001:COP0:32::TLBR
4421"tlbr"
4422*mipsI:
4423*mipsII:
4424*mipsIII:
4425*mipsIV:
4426// start-sanitize-r5900
4427*r5900:
4428// end-sanitize-r5900
4429
4430
4431010000,10000,000000000000000,000010:COP0:32::TLBWI
4432"tlbwi"
4433*mipsI:
4434*mipsII:
4435*mipsIII:
4436*mipsIV:
4437// start-sanitize-r5900
4438*r5900:
4439// end-sanitize-r5900
4440
4441
4442010000,10000,000000000000000,000110:COP0:32::TLBWR
4443"tlbwr"
4444*mipsI:
4445*mipsII:
4446*mipsIII:
4447*mipsIV:
4448// start-sanitize-r5900
4449*r5900:
4450// end-sanitize-r5900
4451
4452\f
4453//
4454// MIPS Architecture:
4455//
4456// CPU Instruction Set (mips16)
4457//
4458
4459// The instructions in this section are ordered according
4460// to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.
4461
4462
4463// Load and Store Instructions
4464
4465
446610000,xxx,ddd,55555:RRI:16::LB
4467*mips16:
4468{
4469 unsigned32 instruction = instruction_0;
055ee297 4470 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012
AC		 4471 int destreg = (instruction >> 5) & 0x7;
4472 int offset = (instruction >> 0) & 0x1f;
4473 if (op1 < 2)
4474 op1 += 16;
4475 op1 = GPR[op1];
4476 if (destreg < 2)
4477 destreg += 16;
4478 if (have_extendval)
4479 {
4480 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4481 if (offset >= 0x8000)
4482 offset -= 0x10000;
4483 have_extendval = 0;
4484 }
4485 else
4486 {
4487 }
4488 if (have_extendval)
4489 SignalException (ReservedInstruction, instruction);
4490 {
4491 unsigned64 vaddr = ((unsigned64)op1 + offset);
4492 unsigned64 paddr;
4493 int uncached;
4494 {
4495 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4496 {
4497 unsigned64 memval = 0;
4498 unsigned64 memval1 = 0;
4499 unsigned64 mask = 0x7;
4500 unsigned int shift = 0;
055ee297
AC		 4501 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4502 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4503 unsigned int byte;
f2b30012
AC		 4504 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4505 LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
4506 byte = ((vaddr & mask) ^ (bigend << shift));
4507 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
4508 }
4509 }
4510 }
4511}
4512
4513
451410100,xxx,ddd,55555:RRI:16::LBU
4515*mips16:
4516{
4517 unsigned32 instruction = instruction_0;
055ee297 4518 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012
AC		 4519 int destreg = (instruction >> 5) & 0x7;
4520 int offset = (instruction >> 0) & 0x1f;
4521 if (op1 < 2)
4522 op1 += 16;
4523 op1 = GPR[op1];
4524 if (destreg < 2)
4525 destreg += 16;
4526 if (have_extendval)
4527 {
4528 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4529 if (offset >= 0x8000)
4530 offset -= 0x10000;
4531 have_extendval = 0;
4532 }
4533 else
4534 {
4535 }
4536 if (have_extendval)
4537 SignalException (ReservedInstruction, instruction);
4538 {
4539 unsigned64 vaddr = ((unsigned64)op1 + offset);
4540 unsigned64 paddr;
4541 int uncached;
4542 {
4543 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4544 {
4545 unsigned64 memval = 0;
4546 unsigned64 memval1 = 0;
4547 unsigned64 mask = 0x7;
4548 unsigned int shift = 0;
055ee297
AC		 4549 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4550 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4551 unsigned int byte;
f2b30012
AC		 4552 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4553 LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
4554 byte = ((vaddr & mask) ^ (bigend << shift));
4555 GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
4556 }
4557 }
4558 }
4559}
4560
4561
456210001,xxx,ddd,HHHHH:RRI:16::LH
4563*mips16:
4564{
4565 unsigned32 instruction = instruction_0;
055ee297 4566 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012
AC		 4567 int destreg = (instruction >> 5) & 0x7;
4568 int offset = (instruction >> 0) & 0x1f;
4569 if (op1 < 2)
4570 op1 += 16;
4571 op1 = GPR[op1];
4572 if (destreg < 2)
4573 destreg += 16;
4574 if (have_extendval)
4575 {
4576 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4577 if (offset >= 0x8000)
4578 offset -= 0x10000;
4579 have_extendval = 0;
4580 }
4581 else
4582 {
4583 offset <<= 1;
4584 }
4585 if (have_extendval)
4586 SignalException (ReservedInstruction, instruction);
4587 {
4588 unsigned64 vaddr = ((unsigned64)op1 + offset);
4589 unsigned64 paddr;
4590 int uncached;
4591 if ((vaddr & 1) != 0)
055ee297 4592 SignalExceptionAddressLoad();
f2b30012
AC		 4593 else
4594 {
4595 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4596 {
4597 unsigned64 memval = 0;
4598 unsigned64 memval1 = 0;
4599 unsigned64 mask = 0x7;
4600 unsigned int shift = 1;
055ee297
AC		 4601 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4602 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4603 unsigned int byte;
f2b30012
AC		 4604 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4605 LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
4606 byte = ((vaddr & mask) ^ (bigend << shift));
4607 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
4608 }
4609 }
4610 }
4611}
4612
4613
461410101,xxx,ddd,HHHHH:RRI:16::LHU
4615*mips16:
4616{
4617 unsigned32 instruction = instruction_0;
055ee297 4618 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012
AC		 4619 int destreg = (instruction >> 5) & 0x7;
4620 int offset = (instruction >> 0) & 0x1f;
4621 if (op1 < 2)
4622 op1 += 16;
4623 op1 = GPR[op1];
4624 if (destreg < 2)
4625 destreg += 16;
4626 if (have_extendval)
4627 {
4628 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4629 if (offset >= 0x8000)
4630 offset -= 0x10000;
4631 have_extendval = 0;
4632 }
4633 else
4634 {
4635 offset <<= 1;
4636 }
4637 if (have_extendval)
4638 SignalException (ReservedInstruction, instruction);
4639 {
4640 unsigned64 vaddr = ((unsigned64)op1 + offset);
4641 unsigned64 paddr;
4642 int uncached;
4643 if ((vaddr & 1) != 0)
055ee297 4644 SignalExceptionAddressLoad();
f2b30012
AC		 4645 else
4646 {
4647 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4648 {
4649 unsigned64 memval = 0;
4650 unsigned64 memval1 = 0;
4651 unsigned64 mask = 0x7;
4652 unsigned int shift = 1;
055ee297
AC		 4653 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4654 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4655 unsigned int byte;
f2b30012
AC		 4656 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4657 LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
4658 byte = ((vaddr & mask) ^ (bigend << shift));
4659 GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
4660 }
4661 }
4662 }
4663}
4664
4665
466610011,xxx,ddd,WWWWW:RRI:16::LW
4667*mips16:
4668{
4669 unsigned32 instruction = instruction_0;
055ee297 4670 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012
AC		 4671 int destreg = (instruction >> 5) & 0x7;
4672 int offset = (instruction >> 0) & 0x1f;
4673 if (op1 < 2)
4674 op1 += 16;
4675 op1 = GPR[op1];
4676 if (destreg < 2)
4677 destreg += 16;
4678 if (have_extendval)
4679 {
4680 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4681 if (offset >= 0x8000)
4682 offset -= 0x10000;
4683 have_extendval = 0;
4684 }
4685 else
4686 {
4687 offset <<= 2;
4688 }
4689 if (have_extendval)
4690 SignalException (ReservedInstruction, instruction);
4691 {
4692 unsigned64 vaddr = ((unsigned64)op1 + offset);
4693 unsigned64 paddr;
4694 int uncached;
4695 if ((vaddr & 3) != 0)
055ee297 4696 SignalExceptionAddressLoad();
f2b30012
AC		 4697 else
4698 {
4699 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4700 {
4701 unsigned64 memval = 0;
4702 unsigned64 memval1 = 0;
4703 unsigned64 mask = 0x7;
4704 unsigned int shift = 2;
055ee297
AC		 4705 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4706 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4707 unsigned int byte;
f2b30012
AC		 4708 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4709 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4710 byte = ((vaddr & mask) ^ (bigend << shift));
4711 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
4712 }
4713 }
4714 }
4715}
4716
4717
471810110,ddd,VVVVVVVV,P:RI:16::LWPC
4719*mips16:
4720{
4721 unsigned32 instruction = instruction_0;
4722 int destreg = (instruction >> 8) & 0x7;
4723 int offset = (instruction >> 0) & 0xff;
055ee297 4724 signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
f2b30012
AC		 4725 if (destreg < 2)
4726 destreg += 16;
4727 if (have_extendval)
4728 {
4729 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4730 if (offset >= 0x8000)
4731 offset -= 0x10000;
4732 have_extendval = 0;
4733 }
4734 else
4735 {
4736 offset <<= 2;
4737 }
4738 if (have_extendval)
4739 SignalException (ReservedInstruction, instruction);
4740 {
4741 unsigned64 vaddr = ((unsigned64)op1 + offset);
4742 unsigned64 paddr;
4743 int uncached;
4744 if ((vaddr & 3) != 0)
055ee297 4745 SignalExceptionAddressLoad();
f2b30012
AC		 4746 else
4747 {
4748 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4749 {
4750 unsigned64 memval = 0;
4751 unsigned64 memval1 = 0;
4752 unsigned64 mask = 0x7;
4753 unsigned int shift = 2;
055ee297
AC		 4754 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4755 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4756 unsigned int byte;
f2b30012
AC		 4757 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4758 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4759 byte = ((vaddr & mask) ^ (bigend << shift));
4760 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
4761 }
4762 }
4763 }
4764}
4765
4766
476710010,ddd,VVVVVVVV,s:RI:16::LWSP
4768*mips16:
4769{
4770 unsigned32 instruction = instruction_0;
4771 int destreg = (instruction >> 8) & 0x7;
4772 int offset = (instruction >> 0) & 0xff;
055ee297 4773 signed_word op1 = 29;
f2b30012
AC		 4774 if (destreg < 2)
4775 destreg += 16;
4776 if (have_extendval)
4777 {
4778 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4779 if (offset >= 0x8000)
4780 offset -= 0x10000;
4781 have_extendval = 0;
4782 }
4783 else
4784 {
4785 offset <<= 2;
4786 }
4787 op1 = GPR[op1];
4788 if (have_extendval)
4789 SignalException (ReservedInstruction, instruction);
4790 {
4791 unsigned64 vaddr = ((unsigned64)op1 + offset);
4792 unsigned64 paddr;
4793 int uncached;
4794 if ((vaddr & 3) != 0)
055ee297 4795 SignalExceptionAddressLoad();
f2b30012
AC		 4796 else
4797 {
4798 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4799 {
4800 unsigned64 memval = 0;
4801 unsigned64 memval1 = 0;
4802 unsigned64 mask = 0x7;
4803 unsigned int shift = 2;
055ee297
AC		 4804 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4805 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4806 unsigned int byte;
f2b30012
AC		 4807 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4808 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4809 byte = ((vaddr & mask) ^ (bigend << shift));
4810 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
4811 }
4812 }
4813 }
4814}
4815
4816
481710111,xxx,ddd,WWWWW:RRI:16::LWU
4818*mips16:
4819{
4820 unsigned32 instruction = instruction_0;
055ee297 4821 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012
AC		 4822 int destreg = (instruction >> 5) & 0x7;
4823 int offset = (instruction >> 0) & 0x1f;
4824 if (op1 < 2)
4825 op1 += 16;
4826 op1 = GPR[op1];
4827 if (destreg < 2)
4828 destreg += 16;
4829 if (have_extendval)
4830 {
4831 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4832 if (offset >= 0x8000)
4833 offset -= 0x10000;
4834 have_extendval = 0;
4835 }
4836 else
4837 {
4838 offset <<= 2;
4839 }
4840 if (have_extendval)
4841 SignalException (ReservedInstruction, instruction);
4842 {
4843 unsigned64 vaddr = ((unsigned64)op1 + offset);
4844 unsigned64 paddr;
4845 int uncached;
4846 if ((vaddr & 3) != 0)
055ee297 4847 SignalExceptionAddressLoad();
f2b30012
AC		 4848 else
4849 {
4850 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4851 {
4852 unsigned64 memval = 0;
4853 unsigned64 memval1 = 0;
4854 unsigned64 mask = 0x7;
4855 unsigned int shift = 2;
055ee297
AC		 4856 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4857 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4858 unsigned int byte;
f2b30012
AC		 4859 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4860 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4861 byte = ((vaddr & mask) ^ (bigend << shift));
4862 GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
4863 }
4864 }
4865 }
4866}
4867
4868
486900111,xxx,ddd,DDDDD:RRI:16::LD
4870*mips16:
4871{
4872 unsigned32 instruction = instruction_0;
055ee297 4873 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012
AC		 4874 int destreg = (instruction >> 5) & 0x7;
4875 int offset = (instruction >> 0) & 0x1f;
4876 if (op1 < 2)
4877 op1 += 16;
4878 op1 = GPR[op1];
4879 if (destreg < 2)
4880 destreg += 16;
4881 if (have_extendval)
4882 {
4883 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4884 if (offset >= 0x8000)
4885 offset -= 0x10000;
4886 have_extendval = 0;
4887 }
4888 else
4889 {
4890 offset <<= 3;
4891 }
4892 if (have_extendval)
4893 SignalException (ReservedInstruction, instruction);
4894 {
4895 unsigned64 vaddr = ((unsigned64)op1 + offset);
4896 unsigned64 paddr;
4897 int uncached;
4898 if ((vaddr & 7) != 0)
055ee297 4899 SignalExceptionAddressLoad();
f2b30012
AC		 4900 else
4901 {
4902 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4903 {
4904 unsigned64 memval = 0;
4905 unsigned64 memval1 = 0;
4906 unsigned64 mask = 0x7;
4907 unsigned int shift = 4;
055ee297
AC		 4908 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4909 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4910 unsigned int byte;
f2b30012
AC		 4911 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4912 GPR[destreg] = memval;
4913 }
4914 }
4915 }
4916}
4917
4918
491911111100,ddd,5.RD,P:RI64:16::LDPC
4920*mips16:
4921{
4922 unsigned32 instruction = instruction_0;
4923 int destreg = (instruction >> 5) & 0x7;
4924 int offset = (instruction >> 0) & 0x1f;
055ee297 4925 signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x7;
f2b30012
AC		 4926 if (destreg < 2)
4927 destreg += 16;
4928 if (have_extendval)
4929 {
4930 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4931 if (offset >= 0x8000)
4932 offset -= 0x10000;
4933 have_extendval = 0;
4934 }
4935 else
4936 {
4937 offset <<= 3;
4938 }
4939 if (have_extendval)
4940 SignalException (ReservedInstruction, instruction);
4941 {
4942 unsigned64 vaddr = ((unsigned64)op1 + offset);
4943 unsigned64 paddr;
4944 int uncached;
4945 if ((vaddr & 7) != 0)
055ee297 4946 SignalExceptionAddressLoad();
f2b30012
AC		 4947 else
4948 {
4949 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4950 {
4951 unsigned64 memval = 0;
4952 unsigned64 memval1 = 0;
4953 unsigned64 mask = 0x7;
4954 unsigned int shift = 4;
055ee297
AC		 4955 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4956 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4957 unsigned int byte;
f2b30012
AC		 4958 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4959 GPR[destreg] = memval;
4960 }
4961 }
4962 }
4963}
4964
4965
496611111000,ddd,5.RD,s:RI64:16::LDSP
4967*mips16:
4968{
4969 unsigned32 instruction = instruction_0;
4970 int destreg = (instruction >> 5) & 0x7;
4971 int offset = (instruction >> 0) & 0x1f;
055ee297 4972 signed_word op1 = 29;
f2b30012
AC		 4973 if (destreg < 2)
4974 destreg += 16;
4975 if (have_extendval)
4976 {
4977 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
4978 if (offset >= 0x8000)
4979 offset -= 0x10000;
4980 have_extendval = 0;
4981 }
4982 else
4983 {
4984 offset <<= 3;
4985 }
4986 op1 = GPR[op1];
4987 if (have_extendval)
4988 SignalException (ReservedInstruction, instruction);
4989 {
4990 unsigned64 vaddr = ((unsigned64)op1 + offset);
4991 unsigned64 paddr;
4992 int uncached;
4993 if ((vaddr & 7) != 0)
055ee297 4994 SignalExceptionAddressLoad();
f2b30012
AC		 4995 else
4996 {
4997 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4998 {
4999 unsigned64 memval = 0;
5000 unsigned64 memval1 = 0;
5001 unsigned64 mask = 0x7;
5002 unsigned int shift = 4;
055ee297
AC		 5003 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5004 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5005 unsigned int byte;
f2b30012
AC		 5006 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
5007 GPR[destreg] = memval;
5008 }
5009 }
5010 }
5011}
5012
5013
501411000,xxx,yyy,55555:RRI:16::SB
5015*mips16:
5016{
5017 unsigned32 instruction = instruction_0;
055ee297
AC		 5018 signed_word op1 = (instruction >> 8) & 0x7;
5019 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 5020 int offset = (instruction >> 0) & 0x1f;
5021 if (op1 < 2)
5022 op1 += 16;
5023 op1 = GPR[op1];
5024 if (op2 < 2)
5025 op2 += 16;
5026 op2 = GPR[op2];
5027 if (have_extendval)
5028 {
5029 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5030 if (offset >= 0x8000)
5031 offset -= 0x10000;
5032 have_extendval = 0;
5033 }
5034 else
5035 {
5036 }
5037 if (have_extendval)
5038 SignalException (ReservedInstruction, instruction);
5039 {
5040 unsigned64 vaddr = ((unsigned64)op1 + offset);
5041 unsigned64 paddr;
5042 int uncached;
5043 {
5044 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5045 {
5046 unsigned64 memval = 0;
5047 unsigned64 memval1 = 0;
5048 unsigned64 mask = 0x7;
5049 unsigned int shift = 0;
5050 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5051 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5052 unsigned int byte;
5053 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5054 byte = ((vaddr & mask) ^ (bigend << shift));
5055 memval = ((unsigned64) op2 << (8 * byte));
5056 {
5057 StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
5058 }
5059 }
5060 }
5061 }
5062}
5063
5064
506511001,xxx,yyy,HHHHH:RRI:16::SH
5066*mips16:
5067{
5068 unsigned32 instruction = instruction_0;
055ee297
AC		 5069 signed_word op1 = (instruction >> 8) & 0x7;
5070 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 5071 int offset = (instruction >> 0) & 0x1f;
5072 if (op1 < 2)
5073 op1 += 16;
5074 op1 = GPR[op1];
5075 if (op2 < 2)
5076 op2 += 16;
5077 op2 = GPR[op2];
5078 if (have_extendval)
5079 {
5080 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5081 if (offset >= 0x8000)
5082 offset -= 0x10000;
5083 have_extendval = 0;
5084 }
5085 else
5086 {
5087 offset <<= 1;
5088 }
5089 if (have_extendval)
5090 SignalException (ReservedInstruction, instruction);
5091 {
5092 unsigned64 vaddr = ((unsigned64)op1 + offset);
5093 unsigned64 paddr;
5094 int uncached;
5095 if ((vaddr & 1) != 0)
055ee297 5096 SignalExceptionAddressStore();
f2b30012
AC		 5097 else
5098 {
5099 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5100 {
5101 unsigned64 memval = 0;
5102 unsigned64 memval1 = 0;
5103 unsigned64 mask = 0x7;
5104 unsigned int shift = 1;
5105 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5106 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5107 unsigned int byte;
5108 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5109 byte = ((vaddr & mask) ^ (bigend << shift));
5110 memval = ((unsigned64) op2 << (8 * byte));
5111 {
5112 StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
5113 }
5114 }
5115 }
5116 }
5117}
5118
5119
512011011,xxx,yyy,WWWWW:RRI:16::SW
5121*mips16:
5122{
5123 unsigned32 instruction = instruction_0;
055ee297
AC		 5124 signed_word op1 = (instruction >> 8) & 0x7;
5125 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 5126 int offset = (instruction >> 0) & 0x1f;
5127 if (op1 < 2)
5128 op1 += 16;
5129 op1 = GPR[op1];
5130 if (op2 < 2)
5131 op2 += 16;
5132 op2 = GPR[op2];
5133 if (have_extendval)
5134 {
5135 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5136 if (offset >= 0x8000)
5137 offset -= 0x10000;
5138 have_extendval = 0;
5139 }
5140 else
5141 {
5142 offset <<= 2;
5143 }
5144 if (have_extendval)
5145 SignalException (ReservedInstruction, instruction);
5146 {
5147 unsigned64 vaddr = ((unsigned64)op1 + offset);
5148 unsigned64 paddr;
5149 int uncached;
5150 if ((vaddr & 3) != 0)
055ee297 5151 SignalExceptionAddressStore();
f2b30012
AC		 5152 else
5153 {
5154 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5155 {
5156 unsigned64 memval = 0;
5157 unsigned64 memval1 = 0;
5158 unsigned64 mask = 0x7;
5159 unsigned int byte;
5160 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5161 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5162 memval = ((unsigned64) op2 << (8 * byte));
5163 {
5164 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5165 }
5166 }
5167 }
5168 }
5169}
5170
5171
517211010,yyy,VVVVVVVV,s:RI:16::SWSP
5173*mips16:
5174{
5175 unsigned32 instruction = instruction_0;
055ee297 5176 signed_word op2 = (instruction >> 8) & 0x7;
f2b30012 5177 int offset = (instruction >> 0) & 0xff;
055ee297 5178 signed_word op1 = 29;
f2b30012
AC		 5179 if (op2 < 2)
5180 op2 += 16;
5181 op2 = GPR[op2];
5182 if (have_extendval)
5183 {
5184 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5185 if (offset >= 0x8000)
5186 offset -= 0x10000;
5187 have_extendval = 0;
5188 }
5189 else
5190 {
5191 offset <<= 2;
5192 }
5193 op1 = GPR[op1];
5194 if (have_extendval)
5195 SignalException (ReservedInstruction, instruction);
5196 {
5197 unsigned64 vaddr = ((unsigned64)op1 + offset);
5198 unsigned64 paddr;
5199 int uncached;
5200 if ((vaddr & 3) != 0)
055ee297 5201 SignalExceptionAddressStore();
f2b30012
AC		 5202 else
5203 {
5204 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5205 {
5206 unsigned64 memval = 0;
5207 unsigned64 memval1 = 0;
5208 unsigned64 mask = 0x7;
5209 unsigned int byte;
5210 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5211 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5212 memval = ((unsigned64) op2 << (8 * byte));
5213 {
5214 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5215 }
5216 }
5217 }
5218 }
5219}
5220
5221
522201100010,VVVVVVVV,Q,s:I8:16::SWRASP
5223*mips16:
5224{
5225 unsigned32 instruction = instruction_0;
5226 int offset = (instruction >> 0) & 0xff;
055ee297
AC		 5227 signed_word op2 = 31;
5228 signed_word op1 = 29;
f2b30012
AC		 5229 if (have_extendval)
5230 {
5231 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5232 if (offset >= 0x8000)
5233 offset -= 0x10000;
5234 have_extendval = 0;
5235 }
5236 else
5237 {
5238 offset <<= 2;
5239 }
5240 op2 = GPR[op2];
5241 op1 = GPR[op1];
5242 if (have_extendval)
5243 SignalException (ReservedInstruction, instruction);
5244 {
5245 unsigned64 vaddr = ((unsigned64)op1 + offset);
5246 unsigned64 paddr;
5247 int uncached;
5248 if ((vaddr & 3) != 0)
055ee297 5249 SignalExceptionAddressStore();
f2b30012
AC		 5250 else
5251 {
5252 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5253 {
5254 unsigned64 memval = 0;
5255 unsigned64 memval1 = 0;
5256 unsigned64 mask = 0x7;
5257 unsigned int byte;
5258 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5259 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5260 memval = ((unsigned64) op2 << (8 * byte));
5261 {
5262 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5263 }
5264 }
5265 }
5266 }
5267}
5268
5269
527001111,xxx,yyy,DDDDD:RRI:16::SD
5271*mips16:
5272{
5273 unsigned32 instruction = instruction_0;
055ee297
AC		 5274 signed_word op1 = (instruction >> 8) & 0x7;
5275 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 5276 int offset = (instruction >> 0) & 0x1f;
5277 if (op1 < 2)
5278 op1 += 16;
5279 op1 = GPR[op1];
5280 if (op2 < 2)
5281 op2 += 16;
5282 op2 = GPR[op2];
5283 if (have_extendval)
5284 {
5285 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5286 if (offset >= 0x8000)
5287 offset -= 0x10000;
5288 have_extendval = 0;
5289 }
5290 else
5291 {
5292 offset <<= 3;
5293 }
5294 if (have_extendval)
5295 SignalException (ReservedInstruction, instruction);
5296 {
5297 unsigned64 vaddr = ((unsigned64)op1 + offset);
5298 unsigned64 paddr;
5299 int uncached;
5300 if ((vaddr & 7) != 0)
055ee297 5301 SignalExceptionAddressStore();
f2b30012
AC		 5302 else
5303 {
5304 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5305 {
5306 unsigned64 memval = 0;
5307 unsigned64 memval1 = 0;
5308 memval = op2;
5309 {
5310 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
5311 }
5312 }
5313 }
5314 }
5315}
5316
5317
531811111001,yyy,5.RD,s:RI64:16::SDSP
5319*mips16:
5320{
5321 unsigned32 instruction = instruction_0;
055ee297 5322 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012 5323 int offset = (instruction >> 0) & 0x1f;
055ee297 5324 signed_word op1 = 29;
f2b30012
AC		 5325 if (op2 < 2)
5326 op2 += 16;
5327 op2 = GPR[op2];
5328 if (have_extendval)
5329 {
5330 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5331 if (offset >= 0x8000)
5332 offset -= 0x10000;
5333 have_extendval = 0;
5334 }
5335 else
5336 {
5337 offset <<= 3;
5338 }
5339 op1 = GPR[op1];
5340 if (have_extendval)
5341 SignalException (ReservedInstruction, instruction);
5342 {
5343 unsigned64 vaddr = ((unsigned64)op1 + offset);
5344 unsigned64 paddr;
5345 int uncached;
5346 if ((vaddr & 7) != 0)
055ee297 5347 SignalExceptionAddressStore();
f2b30012
AC		 5348 else
5349 {
5350 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5351 {
5352 unsigned64 memval = 0;
5353 unsigned64 memval1 = 0;
5354 memval = op2;
5355 {
5356 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
5357 }
5358 }
5359 }
5360 }
5361}
5362
5363
536411111010,CCCCCCCC,s,Q:I64:16::SDRASP
5365*mips16:
5366{
5367 unsigned32 instruction = instruction_0;
5368 int offset = (instruction >> 0) & 0xff;
055ee297
AC		 5369 signed_word op1 = 29;
5370 signed_word op2 = 31;
f2b30012
AC		 5371 if (have_extendval)
5372 {
5373 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5374 if (offset >= 0x8000)
5375 offset -= 0x10000;
5376 have_extendval = 0;
5377 }
5378 else
5379 {
5380 offset <<= 3;
5381 }
5382 op1 = GPR[op1];
5383 op2 = GPR[op2];
5384 if (have_extendval)
5385 SignalException (ReservedInstruction, instruction);
5386 {
5387 unsigned64 vaddr = ((unsigned64)op1 + offset);
5388 unsigned64 paddr;
5389 int uncached;
5390 if ((vaddr & 7) != 0)
055ee297 5391 SignalExceptionAddressStore();
f2b30012
AC		 5392 else
5393 {
5394 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5395 {
5396 unsigned64 memval = 0;
5397 unsigned64 memval1 = 0;
5398 memval = op2;
5399 {
5400 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
5401 }
5402 }
5403 }
5404 }
5405}
5406
5407
5408// ALU Immediate Instructions
5409
5410
541101101,ddd,UUUUUUUU,Z:RI:16::LI
5412*mips16:
5413{
5414 unsigned32 instruction = instruction_0;
5415 int destreg = (instruction >> 8) & 0x7;
5416 int op2 = (instruction >> 0) & 0xff;
055ee297 5417 signed_word op1 = 0;
f2b30012
AC		 5418 if (destreg < 2)
5419 destreg += 16;
5420 if (have_extendval)
5421 {
5422 op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5423 have_extendval = 0;
5424 }
5425 else
5426 {
5427 }
5428 if (have_extendval)
5429 SignalException (ReservedInstruction, instruction);
5430 {
5431 if (destreg != 0)
5432 GPR[destreg] = (op1 | op2);
5433 }
5434}
5435
5436
543701000,xxx,ddd,04444:RRI_A:16::ADDIU
5438*mips16:
5439{
5440 unsigned32 instruction = instruction_0;
055ee297 5441 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012
AC		 5442 int destreg = (instruction >> 5) & 0x7;
5443 int op2 = (instruction >> 0) & 0xf;
5444 if (op1 < 2)
5445 op1 += 16;
5446 op1 = GPR[op1];
5447 if (destreg < 2)
5448 destreg += 16;
5449 if (have_extendval)
5450 {
5451 op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0);
5452 if (op2 >= 0x4000)
5453 op2 -= 0x8000;
5454 have_extendval = 0;
5455 }
5456 else
5457 {
5458 if (op2 >= 0x8)
5459 op2 -= 0x10;
5460 }
5461 if (have_extendval)
5462 SignalException (ReservedInstruction, instruction);
5463 {
5464 unsigned int temp = (unsigned int)(op1 + op2);
055ee297 5465 signed int tempS = (signed int)temp;
f2b30012
AC		 5466 GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5467 }
5468}
5469
5470
547101001,www,kkkkkkkk:RI:16::ADDIU8
5472*mips16:
5473{
5474 unsigned32 instruction = instruction_0;
055ee297 5475 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012
AC		 5476 int destreg;
5477 int op2 = (instruction >> 0) & 0xff;
5478 if (op1 < 2)
5479 op1 += 16;
5480 destreg = op1;
5481 op1 = GPR[op1];
5482 if (have_extendval)
5483 {
5484 op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5485 if (op2 >= 0x8000)
5486 op2 -= 0x10000;
5487 have_extendval = 0;
5488 }
5489 else
5490 {
5491 if (op2 >= 0x80)
5492 op2 -= 0x100;
5493 }
5494 if (have_extendval)
5495 SignalException (ReservedInstruction, instruction);
5496 {
5497 unsigned int temp = (unsigned int)(op1 + op2);
055ee297 5498 signed int tempS = (signed int)temp;
f2b30012
AC		 5499 GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5500 }
5501}
5502
5503
550401100011,KKKKKKKK,S:I8:16::ADJSP
5505*mips16:
5506{
5507 unsigned32 instruction = instruction_0;
5508 int op2 = (instruction >> 0) & 0xff;
055ee297 5509 signed_word op1 = 29;
f2b30012
AC		 5510 int destreg;
5511 if (have_extendval)
5512 {
5513 op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5514 if (op2 >= 0x8000)
5515 op2 -= 0x10000;
5516 have_extendval = 0;
5517 }
5518 else
5519 {
5520 if (op2 >= 0x80)
5521 op2 -= 0x100;
5522 op2 <<= 3;
5523 }
5524 destreg = op1;
5525 op1 = GPR[op1];
5526 if (have_extendval)
5527 SignalException (ReservedInstruction, instruction);
5528 {
5529 unsigned int temp = (unsigned int)(op1 + op2);
055ee297 5530 signed int tempS = (signed int)temp;
f2b30012
AC		 5531 GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5532 }
5533}
5534
5535
553600001,ddd,AAAAAAAA,P:RI:16::ADDIUPC
5537*mips16:
5538{
5539 unsigned32 instruction = instruction_0;
5540 int destreg = (instruction >> 8) & 0x7;
5541 int op2 = (instruction >> 0) & 0xff;
055ee297 5542 signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
f2b30012
AC		 5543 if (destreg < 2)
5544 destreg += 16;
5545 if (have_extendval)
5546 {
5547 op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5548 if (op2 >= 0x8000)
5549 op2 -= 0x10000;
5550 have_extendval = 0;
5551 }
5552 else
5553 {
5554 op2 <<= 2;
5555 }
5556 if (have_extendval)
5557 SignalException (ReservedInstruction, instruction);
5558 {
5559 unsigned int temp = (unsigned int)(op1 + op2);
055ee297 5560 signed int tempS = (signed int)temp;
f2b30012
AC		 5561 GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5562 }
5563}
5564
5565
556600000,ddd,AAAAAAAA,s:RI:16::ADDIUSP
5567*mips16:
5568{
5569 unsigned32 instruction = instruction_0;
5570 int destreg = (instruction >> 8) & 0x7;
5571 int op2 = (instruction >> 0) & 0xff;
055ee297 5572 signed_word op1 = 29;
f2b30012
AC		 5573 if (destreg < 2)
5574 destreg += 16;
5575 if (have_extendval)
5576 {
5577 op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5578 if (op2 >= 0x8000)
5579 op2 -= 0x10000;
5580 have_extendval = 0;
5581 }
5582 else
5583 {
5584 op2 <<= 2;
5585 }
5586 op1 = GPR[op1];
5587 if (have_extendval)
5588 SignalException (ReservedInstruction, instruction);
5589 {
5590 unsigned int temp = (unsigned int)(op1 + op2);
055ee297 5591 signed int tempS = (signed int)temp;
f2b30012
AC		 5592 GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5593 }
5594}
5595
5596
559701000,xxx,ddd,14444:RRI_A:16::DADDIU
5598*mips16:
5599{
5600 unsigned32 instruction = instruction_0;
055ee297 5601 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012
AC		 5602 int destreg = (instruction >> 5) & 0x7;
5603 int op2 = (instruction >> 0) & 0xf;
5604 if (op1 < 2)
5605 op1 += 16;
5606 op1 = GPR[op1];
5607 if (destreg < 2)
5608 destreg += 16;
5609 if (have_extendval)
5610 {
5611 op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0);
5612 if (op2 >= 0x4000)
5613 op2 -= 0x8000;
5614 have_extendval = 0;
5615 }
5616 else
5617 {
5618 if (op2 >= 0x8)
5619 op2 -= 0x10;
5620 }
5621 if (have_extendval)
5622 SignalException (ReservedInstruction, instruction);
5623 {
5624 unsigned64 temp = (unsigned64)(op1 + op2);
055ee297 5625 word64 tempS = (word64)temp;
f2b30012
AC		 5626 GPR[destreg] = (unsigned64)temp;
5627 }
5628}
5629
5630
563111111101,www,jjjjj:RI64:16::DADDIU5
5632*mips16:
5633{
5634 unsigned32 instruction = instruction_0;
055ee297 5635 signed_word op1 = (instruction >> 5) & 0x7;
f2b30012
AC		 5636 int destreg;
5637 int op2 = (instruction >> 0) & 0x1f;
5638 if (op1 < 2)
5639 op1 += 16;
5640 destreg = op1;
5641 op1 = GPR[op1];
5642 if (have_extendval)
5643 {
5644 op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5645 if (op2 >= 0x8000)
5646 op2 -= 0x10000;
5647 have_extendval = 0;
5648 }
5649 else
5650 {
5651 if (op2 >= 0x10)
5652 op2 -= 0x20;
5653 }
5654 if (have_extendval)
5655 SignalException (ReservedInstruction, instruction);
5656 {
5657 unsigned64 temp = (unsigned64)(op1 + op2);
055ee297 5658 word64 tempS = (word64)temp;
f2b30012
AC		 5659 GPR[destreg] = (unsigned64)temp;
5660 }
5661}
5662
5663
566411111011,KKKKKKKK,S:I64:16::DADJSP
5665*mips16:
5666{
5667 unsigned32 instruction = instruction_0;
5668 int op2 = (instruction >> 0) & 0xff;
055ee297 5669 signed_word op1 = 29;
f2b30012
AC		 5670 int destreg;
5671 if (have_extendval)
5672 {
5673 op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5674 if (op2 >= 0x8000)
5675 op2 -= 0x10000;
5676 have_extendval = 0;
5677 }
5678 else
5679 {
5680 if (op2 >= 0x80)
5681 op2 -= 0x100;
5682 op2 <<= 3;
5683 }
5684 destreg = op1;
5685 op1 = GPR[op1];
5686 if (have_extendval)
5687 SignalException (ReservedInstruction, instruction);
5688 {
5689 unsigned64 temp = (unsigned64)(op1 + op2);
055ee297 5690 word64 tempS = (word64)temp;
f2b30012
AC		 5691 GPR[destreg] = (unsigned64)temp;
5692 }
5693}
5694
5695
569611111110,ddd,EEEEE,P:RI64:16::DADDIUPC
5697*mips16:
5698{
5699 unsigned32 instruction = instruction_0;
5700 int destreg = (instruction >> 5) & 0x7;
5701 int op2 = (instruction >> 0) & 0x1f;
055ee297 5702 signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
f2b30012
AC		 5703 if (destreg < 2)
5704 destreg += 16;
5705 if (have_extendval)
5706 {
5707 op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5708 if (op2 >= 0x8000)
5709 op2 -= 0x10000;
5710 have_extendval = 0;
5711 }
5712 else
5713 {
5714 op2 <<= 2;
5715 }
5716 if (have_extendval)
5717 SignalException (ReservedInstruction, instruction);
5718 {
5719 unsigned64 temp = (unsigned64)(op1 + op2);
055ee297 5720 word64 tempS = (word64)temp;
f2b30012
AC		 5721 GPR[destreg] = (unsigned64)temp;
5722 }
5723}
5724
5725
572611111111,ddd,EEEEE,s:RI64:16::DADDIUSP
5727*mips16:
5728{
5729 unsigned32 instruction = instruction_0;
5730 int destreg = (instruction >> 5) & 0x7;
5731 int op2 = (instruction >> 0) & 0x1f;
055ee297 5732 signed_word op1 = 29;
f2b30012
AC		 5733 if (destreg < 2)
5734 destreg += 16;
5735 if (have_extendval)
5736 {
5737 op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5738 if (op2 >= 0x8000)
5739 op2 -= 0x10000;
5740 have_extendval = 0;
5741 }
5742 else
5743 {
5744 op2 <<= 2;
5745 }
5746 op1 = GPR[op1];
5747 if (have_extendval)
5748 SignalException (ReservedInstruction, instruction);
5749 {
5750 unsigned64 temp = (unsigned64)(op1 + op2);
055ee297 5751 word64 tempS = (word64)temp;
f2b30012
AC		 5752 GPR[destreg] = (unsigned64)temp;
5753 }
5754}
5755
5756
575701010,xxx,88888888,T:RI:16::SLTI
5758*mips16:
5759{
5760 unsigned32 instruction = instruction_0;
055ee297 5761 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012
AC		 5762 int op2 = (instruction >> 0) & 0xff;
5763 int destreg = 24;
5764 if (op1 < 2)
5765 op1 += 16;
5766 op1 = GPR[op1];
5767 if (have_extendval)
5768 {
5769 op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5770 if (op2 >= 0x8000)
5771 op2 -= 0x10000;
5772 have_extendval = 0;
5773 }
5774 else
5775 {
5776 }
5777 if (have_extendval)
5778 SignalException (ReservedInstruction, instruction);
5779 {
5780 if ((word64)op1 < (word64)op2)
5781 GPR[destreg] = 1;
5782 else
5783 GPR[destreg] = 0;
5784 }
5785}
5786
5787
578801011,xxx,88888888,T:RI:16::SLTIU
5789*mips16:
5790{
5791 unsigned32 instruction = instruction_0;
055ee297 5792 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012
AC		 5793 int op2 = (instruction >> 0) & 0xff;
5794 int destreg = 24;
5795 if (op1 < 2)
5796 op1 += 16;
5797 op1 = GPR[op1];
5798 if (have_extendval)
5799 {
5800 op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5801 if (op2 >= 0x8000)
5802 op2 -= 0x10000;
5803 have_extendval = 0;
5804 }
5805 else
5806 {
5807 }
5808 if (have_extendval)
5809 SignalException (ReservedInstruction, instruction);
5810 {
5811 if ((unsigned64)op1 < (unsigned64)op2)
5812 GPR[destreg] = 1;
5813 else
5814 GPR[destreg] = 0;
5815 }
5816}
5817
5818
581911101,xxx,yyy,01010,T:RR:16::CMP
5820*mips16:
5821{
5822 unsigned32 instruction = instruction_0;
055ee297
AC		 5823 signed_word op1 = (instruction >> 8) & 0x7;
5824 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 5825 int destreg = 24;
5826 if (op1 < 2)
5827 op1 += 16;
5828 op1 = GPR[op1];
5829 if (op2 < 2)
5830 op2 += 16;
5831 op2 = GPR[op2];
5832 if (have_extendval)
5833 SignalException (ReservedInstruction, instruction);
5834 {
5835 GPR[destreg] = (op1 ^ op2);
5836 }
5837}
5838
5839
584001110,xxx,UUUUUUUU,T:RI:16::CMPI
5841*mips16:
5842{
5843 unsigned32 instruction = instruction_0;
055ee297 5844 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012
AC		 5845 int op2 = (instruction >> 0) & 0xff;
5846 int destreg = 24;
5847 if (op1 < 2)
5848 op1 += 16;
5849 op1 = GPR[op1];
5850 if (have_extendval)
5851 {
5852 op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5853 have_extendval = 0;
5854 }
5855 else
5856 {
5857 }
5858 if (have_extendval)
5859 SignalException (ReservedInstruction, instruction);
5860 {
5861 GPR[destreg] = (op1 ^ op2);
5862 }
5863}
5864
5865
5866// Two/Three Operand, Register-Type
5867
5868
586911100,xxx,yyy,ddd,01:RRR:16::ADDU
5870*mips16:
5871{
5872 unsigned32 instruction = instruction_0;
055ee297
AC		 5873 signed_word op1 = (instruction >> 8) & 0x7;
5874 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 5875 int destreg = (instruction >> 2) & 0x7;
5876 if (op1 < 2)
5877 op1 += 16;
5878 op1 = GPR[op1];
5879 if (op2 < 2)
5880 op2 += 16;
5881 op2 = GPR[op2];
5882 if (destreg < 2)
5883 destreg += 16;
5884 if (have_extendval)
5885 SignalException (ReservedInstruction, instruction);
5886 {
5887 unsigned int temp = (unsigned int)(op1 + op2);
055ee297 5888 signed int tempS = (signed int)temp;
f2b30012
AC		 5889 GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5890 }
5891}
5892
5893
589411100,xxx,yyy,ddd,11:RRR:16::SUBU
5895*mips16:
5896{
5897 unsigned32 instruction = instruction_0;
055ee297
AC		 5898 signed_word op1 = (instruction >> 8) & 0x7;
5899 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 5900 int destreg = (instruction >> 2) & 0x7;
5901 if (op1 < 2)
5902 op1 += 16;
5903 op1 = GPR[op1];
5904 if (op2 < 2)
5905 op2 += 16;
5906 op2 = GPR[op2];
5907 if (destreg < 2)
5908 destreg += 16;
5909 if (have_extendval)
5910 SignalException (ReservedInstruction, instruction);
5911 {
5912 unsigned int temp = (unsigned int)(op1 - op2);
055ee297 5913 signed int tempS = (signed int)temp;
f2b30012
AC		 5914 GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5915 }
5916}
5917
5918
591911100,xxx,yyy,ddd,00:RRR:16::DADDU
5920*mips16:
5921{
5922 unsigned32 instruction = instruction_0;
055ee297
AC		 5923 signed_word op1 = (instruction >> 8) & 0x7;
5924 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 5925 int destreg = (instruction >> 2) & 0x7;
5926 if (op1 < 2)
5927 op1 += 16;
5928 op1 = GPR[op1];
5929 if (op2 < 2)
5930 op2 += 16;
5931 op2 = GPR[op2];
5932 if (destreg < 2)
5933 destreg += 16;
5934 if (have_extendval)
5935 SignalException (ReservedInstruction, instruction);
5936 {
5937 unsigned64 temp = (unsigned64)(op1 + op2);
055ee297 5938 word64 tempS = (word64)temp;
f2b30012
AC		 5939 GPR[destreg] = (unsigned64)temp;
5940 }
5941}
5942
5943
594411100,xxx,yyy,ddd,10:RRR:16::DSUBU
5945*mips16:
5946{
5947 unsigned32 instruction = instruction_0;
055ee297
AC		 5948 signed_word op1 = (instruction >> 8) & 0x7;
5949 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 5950 int destreg = (instruction >> 2) & 0x7;
5951 if (op1 < 2)
5952 op1 += 16;
5953 op1 = GPR[op1];
5954 if (op2 < 2)
5955 op2 += 16;
5956 op2 = GPR[op2];
5957 if (destreg < 2)
5958 destreg += 16;
5959 if (have_extendval)
5960 SignalException (ReservedInstruction, instruction);
5961 {
5962 unsigned64 temp = (unsigned64)(op1 - op2);
055ee297 5963 word64 tempS = (word64)temp;
f2b30012
AC		 5964 GPR[destreg] = (unsigned64)temp;
5965 }
5966}
5967
5968
596911101,xxx,yyy,00010,T:RR:16::SLT
5970*mips16:
5971{
5972 unsigned32 instruction = instruction_0;
055ee297
AC		 5973 signed_word op1 = (instruction >> 8) & 0x7;
5974 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 5975 int destreg = 24;
5976 if (op1 < 2)
5977 op1 += 16;
5978 op1 = GPR[op1];
5979 if (op2 < 2)
5980 op2 += 16;
5981 op2 = GPR[op2];
5982 if (have_extendval)
5983 SignalException (ReservedInstruction, instruction);
5984 {
5985 if ((word64)op1 < (word64)op2)
5986 GPR[destreg] = 1;
5987 else
5988 GPR[destreg] = 0;
5989 }
5990}
5991
5992
599311101,xxx,yyy,00011,T:RR:16::SLTU
5994*mips16:
5995{
5996 unsigned32 instruction = instruction_0;
055ee297
AC		 5997 signed_word op1 = (instruction >> 8) & 0x7;
5998 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 5999 int destreg = 24;
6000 if (op1 < 2)
6001 op1 += 16;
6002 op1 = GPR[op1];
6003 if (op2 < 2)
6004 op2 += 16;
6005 op2 = GPR[op2];
6006 if (have_extendval)
6007 SignalException (ReservedInstruction, instruction);
6008 {
6009 if ((unsigned64)op1 < (unsigned64)op2)
6010 GPR[destreg] = 1;
6011 else
6012 GPR[destreg] = 0;
6013 }
6014}
6015
6016
601711101,ddd,yyy,01011,Z:RR:16::NEG
6018*mips16:
6019{
6020 unsigned32 instruction = instruction_0;
6021 int destreg = (instruction >> 8) & 0x7;
055ee297
AC		 6022 signed_word op2 = (instruction >> 5) & 0x7;
6023 signed_word op1 = 0;
f2b30012
AC		 6024 if (destreg < 2)
6025 destreg += 16;
6026 if (op2 < 2)
6027 op2 += 16;
6028 op2 = GPR[op2];
6029 if (have_extendval)
6030 SignalException (ReservedInstruction, instruction);
6031 {
6032 unsigned int temp = (unsigned int)(op1 - op2);
055ee297 6033 signed int tempS = (signed int)temp;
f2b30012
AC		 6034 GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
6035 }
6036}
6037
6038
603911101,www,yyy,01100:RR:16::AND
6040*mips16:
6041{
6042 unsigned32 instruction = instruction_0;
055ee297 6043 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012 6044 int destreg;
055ee297 6045 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6046 if (op1 < 2)
6047 op1 += 16;
6048 destreg = op1;
6049 op1 = GPR[op1];
6050 if (op2 < 2)
6051 op2 += 16;
6052 op2 = GPR[op2];
6053 if (have_extendval)
6054 SignalException (ReservedInstruction, instruction);
6055 {
6056 GPR[destreg] = (op1 & op2);
6057 }
6058}
6059
6060
606111101,www,yyy,01101:RR:16::OR
6062*mips16:
6063{
6064 unsigned32 instruction = instruction_0;
055ee297 6065 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012 6066 int destreg;
055ee297 6067 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6068 if (op1 < 2)
6069 op1 += 16;
6070 destreg = op1;
6071 op1 = GPR[op1];
6072 if (op2 < 2)
6073 op2 += 16;
6074 op2 = GPR[op2];
6075 if (have_extendval)
6076 SignalException (ReservedInstruction, instruction);
6077 {
6078 if (destreg != 0)
6079 GPR[destreg] = (op1 | op2);
6080 }
6081}
6082
6083
608411101,www,yyy,01110:RR:16::XOR
6085*mips16:
6086{
6087 unsigned32 instruction = instruction_0;
055ee297 6088 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012 6089 int destreg;
055ee297 6090 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6091 if (op1 < 2)
6092 op1 += 16;
6093 destreg = op1;
6094 op1 = GPR[op1];
6095 if (op2 < 2)
6096 op2 += 16;
6097 op2 = GPR[op2];
6098 if (have_extendval)
6099 SignalException (ReservedInstruction, instruction);
6100 {
6101 GPR[destreg] = (op1 ^ op2);
6102 }
6103}
6104
6105
610611101,ddd,yyy,01111,Z:RR:16::NOT
6107*mips16:
6108{
6109 unsigned32 instruction = instruction_0;
6110 int destreg = (instruction >> 8) & 0x7;
055ee297
AC		 6111 signed_word op2 = (instruction >> 5) & 0x7;
6112 signed_word op1 = 0;
f2b30012
AC		 6113 if (destreg < 2)
6114 destreg += 16;
6115 if (op2 < 2)
6116 op2 += 16;
6117 op2 = GPR[op2];
6118 if (have_extendval)
6119 SignalException (ReservedInstruction, instruction);
6120 {
6121 if (destreg != 0)
6122 GPR[destreg] = ~(op1 | op2);
6123 }
6124}
6125
6126
612701100111,ddd,XXXXX,z:I8_MOVR32:16::MOVR32
6128*mips16:
6129{
6130 unsigned32 instruction = instruction_0;
6131 int destreg = (instruction >> 5) & 0x7;
055ee297
AC		 6132 signed_word op1 = (instruction >> 0) & 0x1f;
6133 signed_word op2 = 0;
f2b30012
AC		 6134 if (destreg < 2)
6135 destreg += 16;
6136 op1 = GPR[op1];
6137 if (have_extendval)
6138 SignalException (ReservedInstruction, instruction);
6139 {
6140 if (destreg != 0)
6141 GPR[destreg] = (op1 | op2);
6142 }
6143}
6144
6145
614601100101,YYYYY,xxx,z:I8_MOV32R:16::MOV32R
6147*mips16:
6148{
6149 unsigned32 instruction = instruction_0;
6150 int destreg = (instruction >> 3) & 0x1f;
055ee297
AC		 6151 signed_word op1 = (instruction >> 0) & 0x7;
6152 signed_word op2 = 0;
f2b30012
AC		 6153 destreg = (destreg >> 2) | ((destreg & 3) << 3);
6154 if (op1 < 2)
6155 op1 += 16;
6156 op1 = GPR[op1];
6157 if (have_extendval)
6158 SignalException (ReservedInstruction, instruction);
6159 {
6160 if (destreg != 0)
6161 GPR[destreg] = (op1 | op2);
6162 }
6163}
6164
6165
616600110,ddd,yyy,sss,00:ISHIFT:16::SLL
6167*mips16:
6168{
6169 unsigned32 instruction = instruction_0;
6170 int destreg = (instruction >> 8) & 0x7;
055ee297 6171 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6172 int op1 = (instruction >> 2) & 0x7;
6173 if (destreg < 2)
6174 destreg += 16;
6175 if (op2 < 2)
6176 op2 += 16;
6177 op2 = GPR[op2];
6178 if (have_extendval)
6179 {
6180 op1 = (extendval >> 6) & 0x1f;
6181 have_extendval = 0;
6182 }
6183 else
6184 {
6185 if (op1 == 0)
6186 op1 = 8;
6187 }
6188 if (have_extendval)
6189 SignalException (ReservedInstruction, instruction);
6190 {
6191 GPR[destreg] = ((unsigned64)op2 << op1);
6192 GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6193 }
6194}
6195
6196
619700110,ddd,yyy,sss,10:ISHIFT:16::SRL
6198*mips16:
6199{
6200 unsigned32 instruction = instruction_0;
6201 int destreg = (instruction >> 8) & 0x7;
055ee297 6202 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6203 int op1 = (instruction >> 2) & 0x7;
6204 if (destreg < 2)
6205 destreg += 16;
6206 if (op2 < 2)
6207 op2 += 16;
6208 op2 = GPR[op2];
6209 if (have_extendval)
6210 {
6211 op1 = (extendval >> 6) & 0x1f;
6212 have_extendval = 0;
6213 }
6214 else
6215 {
6216 if (op1 == 0)
6217 op1 = 8;
6218 }
6219 if (have_extendval)
6220 SignalException (ReservedInstruction, instruction);
6221 {
6222 GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6223 GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6224 }
6225}
6226
6227
622800110,ddd,yyy,sss,11:ISHIFT:16::SRA
6229*mips16:
6230{
6231 unsigned32 instruction = instruction_0;
6232 int destreg = (instruction >> 8) & 0x7;
055ee297 6233 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6234 int op1 = (instruction >> 2) & 0x7;
6235 if (destreg < 2)
6236 destreg += 16;
6237 if (op2 < 2)
6238 op2 += 16;
6239 op2 = GPR[op2];
6240 if (have_extendval)
6241 {
6242 op1 = (extendval >> 6) & 0x1f;
6243 have_extendval = 0;
6244 }
6245 else
6246 {
6247 if (op1 == 0)
6248 op1 = 8;
6249 }
6250 if (have_extendval)
6251 SignalException (ReservedInstruction, instruction);
6252 {
6253 unsigned int highbit = (unsigned int)1 << 31;
6254 GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6255 GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0);
6256 GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6257 }
6258}
6259
6260
626111101,xxx,vvv,00100:RR:16::SLLV
6262*mips16:
6263{
6264 unsigned32 instruction = instruction_0;
055ee297
AC		 6265 signed_word op1 = (instruction >> 8) & 0x7;
6266 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6267 int destreg;
6268 if (op1 < 2)
6269 op1 += 16;
6270 op1 = GPR[op1];
6271 if (op2 < 2)
6272 op2 += 16;
6273 destreg = op2;
6274 op2 = GPR[op2];
6275 if (have_extendval)
6276 SignalException (ReservedInstruction, instruction);
6277 {
6278 op1 &= 0x1F;
6279 GPR[destreg] = ((unsigned64)op2 << op1);
6280 GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6281 }
6282}
6283
6284
628511101,xxx,vvv,00110:RR:16::SRLV
6286*mips16:
6287{
6288 unsigned32 instruction = instruction_0;
055ee297
AC		 6289 signed_word op1 = (instruction >> 8) & 0x7;
6290 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6291 int destreg;
6292 if (op1 < 2)
6293 op1 += 16;
6294 op1 = GPR[op1];
6295 if (op2 < 2)
6296 op2 += 16;
6297 destreg = op2;
6298 op2 = GPR[op2];
6299 if (have_extendval)
6300 SignalException (ReservedInstruction, instruction);
6301 {
6302 op1 &= 0x1F;
6303 GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6304 GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6305 }
6306}
6307
6308
630911101,xxx,vvv,00111:RR:16::SRAV
6310*mips16:
6311{
6312 unsigned32 instruction = instruction_0;
055ee297
AC		 6313 signed_word op1 = (instruction >> 8) & 0x7;
6314 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6315 int destreg;
6316 if (op1 < 2)
6317 op1 += 16;
6318 op1 = GPR[op1];
6319 if (op2 < 2)
6320 op2 += 16;
6321 destreg = op2;
6322 op2 = GPR[op2];
6323 if (have_extendval)
6324 SignalException (ReservedInstruction, instruction);
6325 {
6326 unsigned int highbit = (unsigned int)1 << 31;
6327 op1 &= 0x1F;
6328 GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6329 GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0);
6330 GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6331 }
6332}
6333
6334
633500110,ddd,yyy,[[[,01:ISHIFT:16::DSLL
6336*mips16:
6337{
6338 unsigned32 instruction = instruction_0;
6339 int destreg = (instruction >> 8) & 0x7;
055ee297 6340 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6341 int op1 = (instruction >> 2) & 0x7;
6342 if (destreg < 2)
6343 destreg += 16;
6344 if (op2 < 2)
6345 op2 += 16;
6346 op2 = GPR[op2];
6347 if (have_extendval)
6348 {
6349 op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
6350 have_extendval = 0;
6351 }
6352 else
6353 {
6354 if (op1 == 0)
6355 op1 = 8;
6356 }
6357 if (have_extendval)
6358 SignalException (ReservedInstruction, instruction);
6359 {
6360 GPR[destreg] = ((unsigned64)op2 << op1);
6361 }
6362}
6363
6364
636511101,XXX,vvv,01000:RR:16::DSRL
6366*mips16:
6367{
6368 unsigned32 instruction = instruction_0;
6369 int op1 = (instruction >> 8) & 0x7;
055ee297 6370 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6371 int destreg;
6372 if (have_extendval)
6373 {
6374 op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
6375 have_extendval = 0;
6376 }
6377 else
6378 {
6379 if (op1 == 0)
6380 op1 = 8;
6381 }
6382 if (op2 < 2)
6383 op2 += 16;
6384 destreg = op2;
6385 op2 = GPR[op2];
6386 if (have_extendval)
6387 SignalException (ReservedInstruction, instruction);
6388 {
6389 GPR[destreg] = ((unsigned64)(op2) >> op1);
6390 }
6391}
6392
6393
639411101,xxx,vvv,10011:RR:16::DSRA
6395*mips16:
6396{
6397 unsigned32 instruction = instruction_0;
6398 int op1 = (instruction >> 8) & 0x7;
055ee297 6399 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6400 int destreg;
6401 if (have_extendval)
6402 {
6403 op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
6404 have_extendval = 0;
6405 }
6406 else
6407 {
6408 if (op1 == 0)
6409 op1 = 8;
6410 }
6411 if (op2 < 2)
6412 op2 += 16;
6413 destreg = op2;
6414 op2 = GPR[op2];
6415 if (have_extendval)
6416 SignalException (ReservedInstruction, instruction);
6417 {
6418 unsigned64 highbit = (unsigned64)1 << 63;
6419 GPR[destreg] = ((unsigned64)(op2) >> op1);
6420 GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0);
6421 }
6422}
6423
6424
642511101,xxx,vvv,10100:RR:16::DSLLV
6426*mips16:
6427{
6428 unsigned32 instruction = instruction_0;
055ee297
AC		 6429 signed_word op1 = (instruction >> 8) & 0x7;
6430 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6431 int destreg;
6432 if (op1 < 2)
6433 op1 += 16;
6434 op1 = GPR[op1];
6435 if (op2 < 2)
6436 op2 += 16;
6437 destreg = op2;
6438 op2 = GPR[op2];
6439 if (have_extendval)
6440 SignalException (ReservedInstruction, instruction);
6441 {
6442 op1 &= 0x3F;
6443 GPR[destreg] = ((unsigned64)op2 << op1);
6444 }
6445}
6446
6447
644811101,xxx,vvv,10110:RR:16::DSRLV
6449*mips16:
6450{
6451 unsigned32 instruction = instruction_0;
055ee297
AC		 6452 signed_word op1 = (instruction >> 8) & 0x7;
6453 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6454 int destreg;
6455 if (op1 < 2)
6456 op1 += 16;
6457 op1 = GPR[op1];
6458 if (op2 < 2)
6459 op2 += 16;
6460 destreg = op2;
6461 op2 = GPR[op2];
6462 if (have_extendval)
6463 SignalException (ReservedInstruction, instruction);
6464 {
6465 op1 &= 0x3F;
6466 GPR[destreg] = ((unsigned64)(op2) >> op1);
6467 }
6468}
6469
6470
647111101,xxx,vvv,10111:RR:16::DSRAV
6472*mips16:
6473{
6474 unsigned32 instruction = instruction_0;
055ee297
AC		 6475 signed_word op1 = (instruction >> 8) & 0x7;
6476 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6477 int destreg;
6478 if (op1 < 2)
6479 op1 += 16;
6480 op1 = GPR[op1];
6481 if (op2 < 2)
6482 op2 += 16;
6483 destreg = op2;
6484 op2 = GPR[op2];
6485 if (have_extendval)
6486 SignalException (ReservedInstruction, instruction);
6487 {
6488 unsigned64 highbit = (unsigned64)1 << 63;
6489 op1 &= 0x3F;
6490 GPR[destreg] = ((unsigned64)(op2) >> op1);
6491 GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0);
6492 }
6493}
6494
6495
6496// Multiply /Divide Instructions
6497
6498
649911101,xxx,yyy,11000:RR:16::MULT
6500*mips16:
6501{
6502 unsigned32 instruction = instruction_0;
055ee297
AC		 6503 signed_word op1 = (instruction >> 8) & 0x7;
6504 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6505 if (op1 < 2)
6506 op1 += 16;
6507 op1 = GPR[op1];
6508 if (op2 < 2)
6509 op2 += 16;
6510 op2 = GPR[op2];
6511 if (have_extendval)
6512 SignalException (ReservedInstruction, instruction);
6513 {
6514 CHECKHILO("Multiplication");
6515 {
6516 unsigned64 temp = ((word64) op1 * (word64) op2);
6517 LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
6518 HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
6519 }
6520 }
6521}
6522
6523
652411101,xxx,yyy,11001:RR:16::MULTU
6525*mips16:
6526{
6527 unsigned32 instruction = instruction_0;
055ee297
AC		 6528 signed_word op1 = (instruction >> 8) & 0x7;
6529 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6530 if (op1 < 2)
6531 op1 += 16;
6532 op1 = GPR[op1];
6533 if (op2 < 2)
6534 op2 += 16;
6535 op2 = GPR[op2];
6536 if (have_extendval)
6537 SignalException (ReservedInstruction, instruction);
6538 {
6539 CHECKHILO("Multiplication");
6540 {
6541 unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff));
6542 LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
6543 HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
6544 }
6545 }
6546}
6547
6548
654911101,xxx,yyy,11010:RR:16::DIV
6550*mips16:
6551{
6552 unsigned32 instruction = instruction_0;
055ee297
AC		 6553 signed_word op1 = (instruction >> 8) & 0x7;
6554 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6555 if (op1 < 2)
6556 op1 += 16;
6557 op1 = GPR[op1];
6558 if (op2 < 2)
6559 op2 += 16;
6560 op2 = GPR[op2];
6561 if (have_extendval)
6562 SignalException (ReservedInstruction, instruction);
6563 {
6564 CHECKHILO("Division");
6565 {
6566 int d1 = op1;
6567 int d2 = op2;
6568 if (d2 == 0)
6569 {
6570 LO = SIGNEXTEND(0x80000000,32);
6571 HI = SIGNEXTEND(0,32);
6572 }
6573 else if (d2 == -1 && d1 == 0x80000000)
6574 {
6575 LO = SIGNEXTEND(0x80000000,32);
6576 HI = SIGNEXTEND(0,32);
6577 }
6578 else
6579 {
6580 LO = SIGNEXTEND((d1 / d2),32);
6581 HI = SIGNEXTEND((d1 % d2),32);
6582 }
6583 }
6584 }
6585}
6586
6587
658811101,xxx,yyy,11011:RR:16::DIVU
6589*mips16:
6590{
6591 unsigned32 instruction = instruction_0;
055ee297
AC		 6592 signed_word op1 = (instruction >> 8) & 0x7;
6593 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6594 if (op1 < 2)
6595 op1 += 16;
6596 op1 = GPR[op1];
6597 if (op2 < 2)
6598 op2 += 16;
6599 op2 = GPR[op2];
6600 if (have_extendval)
6601 SignalException (ReservedInstruction, instruction);
6602 {
6603 CHECKHILO("Division");
6604 {
6605 unsigned int d1 = op1;
6606 unsigned int d2 = op2;
6607 if (d2 == 0)
6608 {
6609 LO = SIGNEXTEND(0x80000000,32);
6610 HI = SIGNEXTEND(0,32);
6611 }
6612 else if (d2 == -1 && d1 == 0x80000000)
6613 {
6614 LO = SIGNEXTEND(0x80000000,32);
6615 HI = SIGNEXTEND(0,32);
6616 }
6617 else
6618 {
6619 LO = SIGNEXTEND((d1 / d2),32);
6620 HI = SIGNEXTEND((d1 % d2),32);
6621 }
6622 }
6623 }
6624}
6625
6626
662711101,ddd,00010000:RR:16::MFHI
6628*mips16:
6629{
6630 unsigned32 instruction = instruction_0;
6631 int destreg = (instruction >> 8) & 0x7;
6632 if (destreg < 2)
6633 destreg += 16;
6634 if (have_extendval)
6635 SignalException (ReservedInstruction, instruction);
6636 {
6637 GPR[destreg] = HI;
6638 HIACCESS = 3; /* 3rd instruction will be safe */
6639 }
6640}
6641
6642
664311101,ddd,00010010:RR:16::MFLO
6644*mips16:
6645{
6646 unsigned32 instruction = instruction_0;
6647 int destreg = (instruction >> 8) & 0x7;
6648 if (destreg < 2)
6649 destreg += 16;
6650 if (have_extendval)
6651 SignalException (ReservedInstruction, instruction);
6652 {
6653 GPR[destreg] = LO;
6654 LOACCESS = 3; /* 3rd instruction will be safe */
6655 }
6656}
6657
6658
665911101,xxx,yyy,11100:RR:16::DMULT
6660*mips16:
6661{
6662 unsigned32 instruction = instruction_0;
055ee297
AC		 6663 signed_word op1 = (instruction >> 8) & 0x7;
6664 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6665 if (op1 < 2)
6666 op1 += 16;
6667 op1 = GPR[op1];
6668 if (op2 < 2)
6669 op2 += 16;
6670 op2 = GPR[op2];
6671 if (have_extendval)
6672 SignalException (ReservedInstruction, instruction);
6673 {
6674 CHECKHILO("Multiplication");
6675 {
6676 unsigned64 mid;
6677 unsigned64 midhi;
6678 unsigned64 temp;
6679 int sign = 0;
6680 if (op1 < 0) { op1 = - op1; ++sign; }
6681 if (op2 < 0) { op2 = - op2; ++sign; }
6682 LO = ((unsigned64)VL4_8(op1) * VL4_8(op2));
6683 HI = ((unsigned64)VH4_8(op1) * VH4_8(op2));
6684 mid = ((unsigned64)VH4_8(op1) * VL4_8(op2));
6685 midhi = SET64HI(VL4_8(mid));
6686 temp = (LO + midhi);
6687 if ((temp == midhi) ? (LO != 0) : (temp < midhi))
6688 HI += 1;
6689 HI += VH4_8(mid);
6690 mid = ((unsigned64)VL4_8(op1) * VH4_8(op2));
6691 midhi = SET64HI(VL4_8(mid));
6692 LO = (temp + midhi);
6693 if ((LO == midhi) ? (temp != 0) : (LO < midhi))
6694 HI += 1;
6695 HI += VH4_8(mid);
6696 if (sign & 1) { LO = - LO; HI = (LO == 0 ? 0 : -1) - HI; }
6697 }
6698 }
6699}
6700
6701
670211101,xxx,yyy,11101:RR:16::DMULTU
6703*mips16:
6704{
6705 unsigned32 instruction = instruction_0;
055ee297
AC		 6706 signed_word op1 = (instruction >> 8) & 0x7;
6707 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6708 if (op1 < 2)
6709 op1 += 16;
6710 op1 = GPR[op1];
6711 if (op2 < 2)
6712 op2 += 16;
6713 op2 = GPR[op2];
6714 if (have_extendval)
6715 SignalException (ReservedInstruction, instruction);
6716 {
6717 CHECKHILO("Multiplication");
6718 {
6719 unsigned64 mid;
6720 unsigned64 midhi;
6721 unsigned64 temp;
6722 LO = ((unsigned64)VL4_8(op1) * VL4_8(op2));
6723 HI = ((unsigned64)VH4_8(op1) * VH4_8(op2));
6724 mid = ((unsigned64)VH4_8(op1) * VL4_8(op2));
6725 midhi = SET64HI(VL4_8(mid));
6726 temp = (LO + midhi);
6727 if ((temp == midhi) ? (LO != 0) : (temp < midhi))
6728 HI += 1;
6729 HI += VH4_8(mid);
6730 mid = ((unsigned64)VL4_8(op1) * VH4_8(op2));
6731 midhi = SET64HI(VL4_8(mid));
6732 LO = (temp + midhi);
6733 if ((LO == midhi) ? (temp != 0) : (LO < midhi))
6734 HI += 1;
6735 HI += VH4_8(mid);
6736 }
6737 }
6738}
6739
6740
674111101,xxx,yyy,11110:RR:16::DDIV
6742*mips16:
6743{
6744 unsigned32 instruction = instruction_0;
055ee297
AC		 6745 signed_word op1 = (instruction >> 8) & 0x7;
6746 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6747 if (op1 < 2)
6748 op1 += 16;
6749 op1 = GPR[op1];
6750 if (op2 < 2)
6751 op2 += 16;
6752 op2 = GPR[op2];
6753 if (have_extendval)
6754 SignalException (ReservedInstruction, instruction);
6755 {
6756 CHECKHILO("Division");
6757 {
6758 word64 d1 = op1;
6759 word64 d2 = op2;
6760 if (d2 == 0)
6761 {
6762 LO = SIGNED64 (0x8000000000000000);
6763 HI = 0;
6764 }
6765 else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000))
6766 {
6767 LO = SIGNED64 (0x8000000000000000);
6768 HI = 0;
6769 }
6770 else
6771 {
6772 LO = (d1 / d2);
6773 HI = (d1 % d2);
6774 }
6775 }
6776 }
6777}
6778
6779
678011101,xxx,yyy,11111:RR:16::DDIVU
6781*mips16:
6782{
6783 unsigned32 instruction = instruction_0;
055ee297
AC		 6784 signed_word op1 = (instruction >> 8) & 0x7;
6785 signed_word op2 = (instruction >> 5) & 0x7;
f2b30012
AC		 6786 if (op1 < 2)
6787 op1 += 16;
6788 op1 = GPR[op1];
6789 if (op2 < 2)
6790 op2 += 16;
6791 op2 = GPR[op2];
6792 if (have_extendval)
6793 SignalException (ReservedInstruction, instruction);
6794 {
6795 CHECKHILO("Division");
6796 {
6797 unsigned64 d1 = op1;
6798 unsigned64 d2 = op2;
6799 if (d2 == 0)
6800 {
6801 LO = SIGNED64 (0x8000000000000000);
6802 HI = 0;
6803 }
6804 else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000))
6805 {
6806 LO = SIGNED64 (0x8000000000000000);
6807 HI = 0;
6808 }
6809 else
6810 {
6811 LO = (d1 / d2);
6812 HI = (d1 % d2);
6813 }
6814 }
6815 }
6816}
6817
6818
6819// Jump and Branch Instructions
6820
6821
6822// JALX
6823// JAL
682400011,aaaaaaaaaaa:I:16::JAL
6825*mips16:
6826{
6827 unsigned32 instruction = instruction_0;
055ee297 6828 unsigned_word op1 = (instruction >> 0) & 0x7ff;
f2b30012
AC		 6829 {
6830 unsigned64 paddr;
6831 int uncached;
6832 if (AddressTranslation (PC &~ (unsigned64) 1, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL))
6833 {
6834 unsigned64 memval;
6835 unsigned int reverse = (ReverseEndian ? 3 : 0);
6836 unsigned int bigend = (BigEndianCPU ? 3 : 0);
6837 unsigned int byte;
6838 paddr = ((paddr & ~0x7) | ((paddr & 0x7) ^ (reverse << 1)));
6839 LoadMemory (&memval,0,uncached, AccessLength_HALFWORD, paddr, PC, isINSTRUCTION, isREAL);
6840 byte = (((PC &~ (unsigned64) 1) & 0x7) ^ (bigend << 1));
6841 memval = (memval >> (8 * byte)) & 0xffff;
6842 op1 = (((op1 & 0x1f) << 23)
6843 | ((op1 & 0x3e0) << 13)
6844 | (memval << 2));
6845 if ((instruction & 0x400) == 0)
6846 op1 |= 1;
6847 PC += 2;
6848 }
6849 }
6850 op1 |= PC & ~ (unsigned64) 0x0fffffff;
6851 if (have_extendval)
6852 SignalException (ReservedInstruction, instruction);
6853 {
6854 int destreg = 31;
6855 GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */
6856 /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
6857 so we just truncate it to 32 bits here. */
6858 op1 = VL4_8(op1);
6859 /* NOTE: The jump occurs AFTER the next instruction has been executed */
6860 DSPC = op1;
6861 JALDELAYSLOT();
6862 }
6863}
6864
6865
686611101,xxx,00000000:RR:16::JR
6867*mips16:
6868{
6869 unsigned32 instruction = instruction_0;
055ee297 6870 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012
AC		 6871 if (op1 < 2)
6872 op1 += 16;
6873 op1 = GPR[op1];
6874 if (have_extendval)
6875 SignalException (ReservedInstruction, instruction);
6876 {
6877 /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
6878 so we just truncate it to 32 bits here. */
6879 op1 = VL4_8(op1);
6880 /* NOTE: The jump occurs AFTER the next instruction has been executed */
6881 DSPC = op1;
6882 DELAYSLOT();
6883 }
6884}
6885
6886
68871110100000100000,r:RR:16::JRRA
6888*mips16:
6889{
6890 unsigned32 instruction = instruction_0;
055ee297 6891 signed_word op1 = 31;
f2b30012
AC		 6892 op1 = GPR[op1];
6893 if (have_extendval)
6894 SignalException (ReservedInstruction, instruction);
6895 {
6896 /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
6897 so we just truncate it to 32 bits here. */
6898 op1 = VL4_8(op1);
6899 /* NOTE: The jump occurs AFTER the next instruction has been executed */
6900 DSPC = op1;
6901 DELAYSLOT();
6902 }
6903}
6904
6905
690611101,xxx,01000000,R:RR:16::JALR
6907*mips16:
6908{
6909 unsigned32 instruction = instruction_0;
055ee297 6910 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012
AC		 6911 int destreg = 31;
6912 if (op1 < 2)
6913 op1 += 16;
6914 op1 = GPR[op1];
6915 if (have_extendval)
6916 SignalException (ReservedInstruction, instruction);
6917 {
6918 GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */
6919 /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
6920 so we just truncate it to 32 bits here. */
6921 op1 = VL4_8(op1);
6922 /* NOTE: The jump occurs AFTER the next instruction has been executed */
6923 DSPC = op1;
6924 DELAYSLOT();
6925 }
6926}
6927
6928
692900100,xxx,pppppppp,z:RI:16::BEQZ
6930*mips16:
6931{
6932 unsigned32 instruction = instruction_0;
055ee297 6933 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012 6934 int offset = (instruction >> 0) & 0xff;
055ee297 6935 signed_word op2 = 0;
f2b30012
AC		 6936 if (op1 < 2)
6937 op1 += 16;
6938 op1 = GPR[op1];
6939 if (have_extendval)
6940 {
6941 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6942 if (offset >= 0x8000)
6943 offset -= 0x10000;
6944 have_extendval = 0;
6945 }
6946 else
6947 {
6948 if (offset >= 0x80)
6949 offset -= 0x100;
6950 }
6951 offset *= 2;
6952 if (have_extendval)
6953 SignalException (ReservedInstruction, instruction);
6954 {
6955 int condition = (op1 == op2);
6956 if (condition)
6957 PC = PC + offset;
6958 }
6959}
6960
6961
696200101,xxx,pppppppp,z:RI:16::BNEZ
6963*mips16:
6964{
6965 unsigned32 instruction = instruction_0;
055ee297 6966 signed_word op1 = (instruction >> 8) & 0x7;
f2b30012 6967 int offset = (instruction >> 0) & 0xff;
055ee297 6968 signed_word op2 = 0;
f2b30012
AC		 6969 if (op1 < 2)
6970 op1 += 16;
6971 op1 = GPR[op1];
6972 if (have_extendval)
6973 {
6974 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6975 if (offset >= 0x8000)
6976 offset -= 0x10000;
6977 have_extendval = 0;
6978 }
6979 else
6980 {
6981 if (offset >= 0x80)
6982 offset -= 0x100;
6983 }
6984 offset *= 2;
6985 if (have_extendval)
6986 SignalException (ReservedInstruction, instruction);
6987 {
6988 int condition = (op1 != op2);
6989 if (condition)
6990 PC = PC + offset;
6991 }
6992}
6993
6994
699501100000,pppppppp,t,z:I8:16::BTEQZ
6996*mips16:
6997{
6998 unsigned32 instruction = instruction_0;
6999 int offset = (instruction >> 0) & 0xff;
055ee297
AC		 7000 signed_word op1 = 24;
7001 signed_word op2 = 0;
f2b30012
AC		 7002 if (have_extendval)
7003 {
7004 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
7005 if (offset >= 0x8000)
7006 offset -= 0x10000;
7007 have_extendval = 0;
7008 }
7009 else
7010 {
7011 if (offset >= 0x80)
7012 offset -= 0x100;
7013 }
7014 offset *= 2;
7015 op1 = GPR[op1];
7016 if (have_extendval)
7017 SignalException (ReservedInstruction, instruction);
7018 {
7019 int condition = (op1 == op2);
7020 if (condition)
7021 PC = PC + offset;
7022 }
7023}
7024
7025
702601100001,pppppppp,t,z:I8:16::BTNEZ
7027*mips16:
7028{
7029 unsigned32 instruction = instruction_0;
7030 int offset = (instruction >> 0) & 0xff;
055ee297
AC		 7031 signed_word op1 = 24;
7032 signed_word op2 = 0;
f2b30012
AC		 7033 if (have_extendval)
7034 {
7035 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
7036 if (offset >= 0x8000)
7037 offset -= 0x10000;
7038 have_extendval = 0;
7039 }
7040 else
7041 {
7042 if (offset >= 0x80)
7043 offset -= 0x100;
7044 }
7045 offset *= 2;
7046 op1 = GPR[op1];
7047 if (have_extendval)
7048 SignalException (ReservedInstruction, instruction);
7049 {
7050 int condition = (op1 != op2);
7051 if (condition)
7052 PC = PC + offset;
7053 }
7054}
7055
7056
705700010,qqqqqqqqqqq,z,Z:I:16::B
7058*mips16:
7059{
7060 unsigned32 instruction = instruction_0;
7061 int offset = (instruction >> 0) & 0x7ff;
055ee297
AC		 7062 signed_word op2 = 0;
7063 signed_word op1 = 0;
f2b30012
AC		 7064 if (have_extendval)
7065 {
7066 offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
7067 if (offset >= 0x8000)
7068 offset -= 0x10000;
7069 have_extendval = 0;
7070 }
7071 else
7072 {
7073 if (offset >= 0x400)
7074 offset -= 0x800;
7075 }
7076 offset *= 2;
7077 if (have_extendval)
7078 SignalException (ReservedInstruction, instruction);
7079 {
7080 int condition = (op1 == op2);
7081 if (condition)
7082 PC = PC + offset;
7083 }
7084}
7085
7086
7087// Special Instructions
7088
7089
7090// See the front of the mips16 doc
709111110,eeeeeeeeeee:I:16::EXTEND
7092*mips16:
7093{
7094 unsigned32 instruction = instruction_0;
7095 int ext = (instruction >> 0) & 0x7ff;
7096 if (have_extendval)
7097 SignalException (ReservedInstruction, instruction);
7098 {
7099 extendval = ext;
7100 have_extendval = 1;
7101 }
7102}
7103
7104
710501100,******,00101:RR:16::BREAK
7106*mips16:
7107{
7108 unsigned32 instruction = instruction_0;
7109 if (have_extendval)
7110 SignalException (ReservedInstruction, instruction);
7111 {
7112 SignalException(BreakPoint,instruction);
7113 }
7114}
7115
7116\f
7117// start-sanitize-r5900
7118
7119// FIXME: The instructions below which are typically r5900 specific
7120// need to be merged back into the above.
7121
7122// end-sanitize-r5900
7123// start-sanitize-r5900
7124
7125011100,5.RS,5.RT,0000000000011010:MMINORM:32::DIV1
7126*r5900:
7127{
7128 unsigned32 instruction = instruction_0;
055ee297
AC		 7129 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7130 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 7131 {
7132 CHECKHILO("Division");
7133 {
7134 int d1 = op1;
7135 int d2 = op2;
7136 if (d2 == 0)
7137 {
7138 LO1 = SIGNEXTEND(0x80000000,32);
7139 HI1 = SIGNEXTEND(0,32);
7140 }
7141 else if (d2 == -1 && d1 == 0x80000000)
7142 {
7143 LO1 = SIGNEXTEND(0x80000000,32);
7144 HI1 = SIGNEXTEND(0,32);
7145 }
7146 else
7147 {
7148 LO1 = SIGNEXTEND((d1 / d2),32);
7149 HI1 = SIGNEXTEND((d1 % d2),32);
7150 }
7151 }
7152 }
7153}
7154
7155// end-sanitize-r5900
7156// start-sanitize-r5900
7157
7158011100,5.RS,5.RT,0000000000011011:MMINORM:32::DIVU1
7159*r5900:
7160{
7161 unsigned32 instruction = instruction_0;
055ee297
AC		 7162 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7163 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 7164 {
7165 CHECKHILO("Division");
7166 {
7167 unsigned int d1 = op1;
7168 unsigned int d2 = op2;
7169 if (d2 == 0)
7170 {
7171 LO1 = SIGNEXTEND(0x80000000,32);
7172 HI1 = SIGNEXTEND(0,32);
7173 }
7174 else if (d2 == -1 && d1 == 0x80000000)
7175 {
7176 LO1 = SIGNEXTEND(0x80000000,32);
7177 HI1 = SIGNEXTEND(0,32);
7178 }
7179 else
7180 {
7181 LO1 = SIGNEXTEND((d1 / d2),32);
7182 HI1 = SIGNEXTEND((d1 % d2),32);
7183 }
7184 }
7185 }
7186}
7187
7188// end-sanitize-r5900
7189
f2b30012 7190011101,26.INSTR_INDEX:NORMAL:32::JALX
f2b30012
AC		 7191// start-sanitize-r5900
7192*r5900:
7193// end-sanitize-r5900
7194*r3900:
7195// start-sanitize-tx19
7196*tx19:
7197// end-sanitize-tx19
7198{
7199 unsigned32 instruction = instruction_0;
055ee297 7200 unsigned_word op1 = (((instruction >> 0) & 0x03FFFFFF) << 2);
f2b30012
AC		 7201 op1 |= (PC & ~0x0FFFFFFF); /* address of instruction in delay slot for the jump */
7202 {
7203 int destreg = 31;
7204 GPR[destreg] = (PC + 4); /* NOTE: The PC is already 4 ahead within the simulator */
7205 op1 ^= 1;
7206 /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
7207 so we just truncate it to 32 bits here. */
7208 op1 = VL4_8(op1);
7209 /* NOTE: The jump occurs AFTER the next instruction has been executed */
7210 DSPC = op1;
085c1cb9 7211 /* JALDELAYSLOT(); FIXME */
f2b30012
AC		 7212 }
7213}
7214
7215// start-sanitize-r5900
7216
7217011110,5.RS,5.RT,16.OFFSET:NORMAL:128::LQ
7218*r5900:
7219{
7220 unsigned32 instruction = instruction_0;
055ee297
AC		 7221 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
7222 int destreg = ((instruction >> 16) & 0x0000001F);
7223 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 7224 {
7225 unsigned64 vaddr = ((unsigned64)op1 + offset);
7226 unsigned64 paddr;
7227 int uncached;
7228 if ((vaddr & 15) != 0)
055ee297 7229 SignalExceptionAddressLoad();
f2b30012
AC		 7230 else
7231 {
7232 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
7233 {
7234 unsigned64 memval = 0;
7235 unsigned64 memval1 = 0;
7236 unsigned64 mask = 0x7;
7237 unsigned int shift = 8;
055ee297
AC		 7238 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
7239 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
7240 unsigned int byte;
f2b30012
AC		 7241 LoadMemory(&memval,&memval1,uncached,AccessLength_QUADWORD,paddr,vaddr,isDATA,isREAL);
7242 GPR[destreg] = memval;
7243 GPR1[destreg] = memval1;
7244 }
7245 }
7246 }
7247}
7248
7249// end-sanitize-r5900
7250// start-sanitize-r5900
7251
7252011100,5.RS,5.RT,5.RD,00000000000:MMINORM:32::MADD
7253*r5900:
7254*r3900:
7255{
7256 unsigned32 instruction = instruction_0;
055ee297
AC		 7257 int destreg = ((instruction >> 11) & 0x0000001F);
7258 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7259 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 7260 {
7261 word64 prod = (word64)WORD64(VL4_8(HI),VL4_8(LO)) + ((word64)SIGNEXTEND(op1,32) * (word64)SIGNEXTEND(op2,32));
7262 LO = SIGNEXTEND(prod,32);
7263 HI = SIGNEXTEND( VH4_8(prod), 32);
7264 if( destreg != 0 ) GPR[destreg] = LO;
7265 }
7266}
7267
7268// end-sanitize-r5900
7269// start-sanitize-r5900
7270
7271011100,5.RS,5.RT,5.RD,00000000001:MMINORM:32::MADDU
7272*r5900:
7273*r3900:
7274{
7275 unsigned32 instruction = instruction_0;
055ee297
AC		 7276 int destreg = ((instruction >> 11) & 0x0000001F);
7277 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7278 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 7279 {
7280 unsigned64 prod = (unsigned64)WORD64(VL4_8(HI),VL4_8(LO)) + ((unsigned64)VL4_8(op1) * (unsigned64)VL4_8(op2));
7281 LO = SIGNEXTEND(prod,32);
7282 HI = SIGNEXTEND( VH4_8(prod), 32);
7283 if( destreg != 0 ) GPR[destreg] = LO;
7284 }
7285}
7286
7287// end-sanitize-r5900
7288// start-sanitize-r5900
7289
7290011100,5.RS,5.RT,5.RD,00000100000:MMINORM:32::MADD1
7291*r5900:
7292{
7293 unsigned32 instruction = instruction_0;
055ee297
AC		 7294 int destreg = ((instruction >> 11) & 0x0000001F);
7295 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7296 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 7297 {
7298 word64 prod = (word64)WORD64(VL4_8(HI1),VL4_8(LO1)) + ((word64)SIGNEXTEND(op1,32) * (word64)SIGNEXTEND(op2,32));
7299 LO1 = SIGNEXTEND(prod,32);
7300 HI1 = SIGNEXTEND( VH4_8(prod), 32);
7301 if( destreg != 0 ) GPR[destreg] = LO1;
7302 }
7303}
7304
7305// end-sanitize-r5900
7306// start-sanitize-r5900
7307
7308011100,5.RS,5.RT,5.RD,00000100001:MMINORM:32::MADDU1
7309*r5900:
7310{
7311 unsigned32 instruction = instruction_0;
055ee297
AC		 7312 int destreg = ((instruction >> 11) & 0x0000001F);
7313 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7314 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 7315 {
7316 unsigned64 prod = (unsigned64)WORD64(VL4_8(HI1),VL4_8(LO1)) + ((unsigned64)VL4_8(op1) * (unsigned64)VL4_8(op2));
7317 LO1 = SIGNEXTEND(prod,32);
7318 HI1 = SIGNEXTEND( VH4_8(prod), 32);
7319 if( destreg != 0 ) GPR[destreg] = LO1;
7320 }
7321}
7322
7323// end-sanitize-r5900
f2b30012
AC		 7324// start-sanitize-r5900
7325
73260111000000000000,5.RD,00000010000:MMINORM:32::MFHI1
7327*r5900:
7328{
7329 unsigned32 instruction = instruction_0;
055ee297 7330 int destreg = ((instruction >> 11) & 0x0000001F);
f2b30012
AC		 7331 {
7332 GPR[destreg] = HI1;
7333 HI1ACCESS = 3; /* 3rd instruction will be safe */
7334 }
7335}
7336
7337// end-sanitize-r5900
7338// start-sanitize-r5900
7339
73400111000000000000,5.RD,00000010010:MMINORM:32::MFLO1
7341*r5900:
7342{
7343 unsigned32 instruction = instruction_0;
055ee297 7344 int destreg = ((instruction >> 11) & 0x0000001F);
f2b30012
AC		 7345 {
7346 GPR[destreg] = LO1;
7347 LO1ACCESS = 3; /* 3rd instruction will be safe */
7348 }
7349}
7350
7351// end-sanitize-r5900
7352// start-sanitize-r5900
7353
73540000000000000000,5.RD,00000101000:SPECIAL:32::MFSA
7355*r5900:
7356{
7357 unsigned32 instruction = instruction_0;
055ee297 7358 int destreg = ((instruction >> 11) & 0x0000001F);
f2b30012
AC		 7359 {
7360 GPR[destreg] = SA;
7361 }
7362}
7363
7364// end-sanitize-r5900
7365// start-sanitize-r5900
7366
7367011100,5.RS,000000000000000010001:MMINORM:32::MTHI1
7368*r5900:
7369{
7370 unsigned32 instruction = instruction_0;
055ee297 7371 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 7372 {
7373 if (HI1ACCESS != 0)
085c1cb9 7374 sim_io_error(sd,"MT (move-to) over-writing HI register value\n");
f2b30012
AC		 7375 HI1 = op1;
7376 HI1ACCESS = 3; /* 3rd instruction will be safe */
7377 }
7378}
7379
7380// end-sanitize-r5900
7381// start-sanitize-r5900
7382
7383011100,5.RS,000000000000000010011:MMINORM:32::MTLO1
7384*r5900:
7385{
7386 unsigned32 instruction = instruction_0;
055ee297 7387 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 7388 {
7389 if (LO1ACCESS != 0)
085c1cb9 7390 sim_io_error(sd,"MT (move-to) over-writing LO register value");
f2b30012
AC		 7391 LO1 = op1;
7392 LO1ACCESS = 3; /* 3rd instruction will be safe */
7393 }
7394}
7395
7396// end-sanitize-r5900
7397// start-sanitize-r5900
7398
7399000000,5.RS,000000000000000101001:SPECIAL:32::MTSA
7400*r5900:
7401{
7402 unsigned32 instruction = instruction_0;
055ee297 7403 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 7404 {
7405 SA = op1;
7406 }
7407}
7408
7409// end-sanitize-r5900
7410// start-sanitize-r5900
7411
7412000001,5.RS,11000,16.IMMEDIATE:REGIMM:32::MTSAB
7413*r5900:
7414{
055ee297 7415 SA = ((GPR[RA] & 0xF) ^ (IMMEDIATE & 0xF)) * 8;
f2b30012
AC		 7416}
7417
7418// end-sanitize-r5900
7419// start-sanitize-r5900
7420
7421000001,5.RS,11001,16.IMMEDIATE:REGIMM:32::MTSAH
7422*r5900:
7423{
055ee297 7424 SA = ((GPR[RS] & 0x7) ^ (IMMEDIATE & 0x7)) * 16;
f2b30012
AC		 7425}
7426
7427// end-sanitize-r5900
7428// start-sanitize-r5900
7429
7430011100,5.RS,5.RT,5.RD,00000011000:MMINORM:32::MULT1
7431*r5900:
7432{
7433 unsigned32 instruction = instruction_0;
055ee297
AC		 7434 int destreg = ((instruction >> 11) & 0x0000001F);
7435 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7436 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 7437 {
7438 CHECKHILO("Multiplication");
7439 {
7440 unsigned64 temp = ((word64) op1 * (word64) op2);
7441 LO1 = SIGNEXTEND((unsigned64)VL4_8(temp),32);
7442 HI1 = SIGNEXTEND((unsigned64)VH4_8(temp),32);
7443 if ( destreg != 0 )
7444 GPR[destreg] = LO1;
7445 }
7446 }
7447}
7448
7449// end-sanitize-r5900
7450// start-sanitize-r5900
7451
7452011100,5.RS,5.RT,5.RD,00000011001:MMINORM:32::MULTU1
7453*r5900:
7454{
7455 unsigned32 instruction = instruction_0;
055ee297
AC		 7456 int destreg = ((instruction >> 11) & 0x0000001F);
7457 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7458 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 7459 {
7460 CHECKHILO("Multiplication");
7461 {
7462 unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff));
7463 LO1 = SIGNEXTEND((unsigned64)VL4_8(temp),32);
7464 HI1 = SIGNEXTEND((unsigned64)VH4_8(temp),32);
7465 if ( destreg != 0 )
7466 GPR[destreg] = LO1;
7467 }
7468 }
7469}
7470
7471// end-sanitize-r5900
7472// start-sanitize-r5900
7473
747401110000000,5.RT,5.RD,00101101000:MMI1:32::PABSH
7475*r5900:
7476{
7477 unsigned32 instruction = instruction_0;
055ee297 7478 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7479 signed_word rt_reg = GPR[RT];
7480 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7481 {
7482 int i;
7483 for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
7484 {
7485 if (RT_SH(i) >= 0)
7486 GPR_SH(destreg,i) = RT_SH(i);
7487 else if (RT_SH(i) == -32768)
7488 GPR_SH(destreg,i) = 32767;
7489 else
7490 GPR_SH(destreg,i) = -RT_SH(i);
7491 }
7492 }
7493}
7494
7495// end-sanitize-r5900
7496// start-sanitize-r5900
7497
749801110000000,5.RT,5.RD,00001101000:MMI1:32::PABSW
7499*r5900:
7500{
7501 unsigned32 instruction = instruction_0;
055ee297 7502 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7503 signed_word rt_reg = GPR[RT];
7504 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7505 {
7506 int i;
7507 for(i=0;i<WORDS_IN_MMI_REGS;i++)
7508 {
7509 if (RT_SW(i) >= 0)
7510 GPR_SW(destreg,i) = RT_SW(i);
7511 else if (RT_SW(i) == (int)0x80000000)
7512 GPR_SW(destreg,i) = (int)0x7FFFFFFF;
7513 else
7514 GPR_SW(destreg,i) = -RT_SW(i);
7515 }
7516 }
7517}
7518
7519// end-sanitize-r5900
7520// start-sanitize-r5900
7521
7522011100,5.RS,5.RT,5.RD,01000001000:MMI0:32::PADDB
7523*r5900:
7524{
7525 unsigned32 instruction = instruction_0;
055ee297 7526 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 7527 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7528 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 7529 signed_word rt_reg = GPR[RT];
7530 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7531 {
7532 int i;
7533 for (i=0; i < BYTES_IN_MMI_REGS; i++)
7534 {
7535 int s = RS_SB(i);
7536 int t = RT_SB(i);
7537 int r = s + t;
7538 GPR_SB(destreg,i) = r;
7539 }
7540 }
7541}
7542
7543// end-sanitize-r5900
7544// start-sanitize-r5900
7545
7546011100,5.RS,5.RT,5.RD,00100001000:MMI0:32::PADDH
7547*r5900:
7548{
7549 unsigned32 instruction = instruction_0;
055ee297 7550 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 7551 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
7552 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 7553 signed_word rt_reg = GPR[RT];
7554 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7555 {
7556 int i;
7557 for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
7558 {
7559 int s = RS_SH(i);
7560 int t = RT_SH(i);
7561 int r = s + t;
7562 GPR_SH(destreg,i) = r;
7563 }
7564 }
7565}
7566
7567// end-sanitize-r5900
7568// start-sanitize-r5900
7569
7570011100,5.RS,5.RT,5.RD,00000001000:MMI0:32::PADDW
7571*r5900:
7572{
7573 unsigned32 instruction = instruction_0;
055ee297 7574 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7575 signed_word rs_reg = GPR[RS];
7576 signed_word rs_reg1 = GPR1[RS];
7577 signed_word rt_reg = GPR[RT];
7578 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7579 {
7580 int i;
7581 for (i=0; i < WORDS_IN_MMI_REGS; i++)
7582 {
7583 signed64 s = RS_SW(i);
7584 signed64 t = RT_SW(i);
7585 signed64 r = s + t;
7586 GPR_SW(destreg,i) = r;
7587 }
7588 }
7589}
7590
7591// end-sanitize-r5900
7592// start-sanitize-r5900
7593
7594011100,5.RS,5.RT,5.RD,11000001000:MMI0:32::PADDSB
7595*r5900:
7596{
7597 unsigned32 instruction = instruction_0;
055ee297 7598 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7599 signed_word rs_reg = GPR[RS];
7600 signed_word rs_reg1 = GPR1[RS];
7601 signed_word rt_reg = GPR[RT];
7602 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7603 {
7604 int i;
7605 for (i=0; i < BYTES_IN_MMI_REGS; i++)
7606 {
7607 int s = RS_SB(i);
7608 int t = RT_SB(i);
7609 int r = s + t;
7610 if (r > 127)
7611 GPR_SB(destreg,i) = 127;
7612 else if (r < -128)
7613 GPR_SB(destreg,i) = -128;
7614 else
7615 GPR_SB(destreg,i) = r;
7616 }
7617 }
7618}
7619
7620// end-sanitize-r5900
7621// start-sanitize-r5900
7622
7623011100,5.RS,5.RT,5.RD,10100001000:MMI0:32::PADDSH
7624*r5900:
7625{
7626 unsigned32 instruction = instruction_0;
055ee297 7627 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7628 signed_word rs_reg = GPR[RS];
7629 signed_word rs_reg1 = GPR1[RS];
7630 signed_word rt_reg = GPR[RT];
7631 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7632 {
7633 int i;
7634 for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
7635 {
7636 int s = RS_SH(i);
7637 int t = RT_SH(i);
7638 int r = s + t;
7639 if (r > 32767)
7640 GPR_SH(destreg,i) = 32767;
7641 else if (r < -32768)
7642 GPR_SH(destreg,i) = -32768;
7643 else
7644 GPR_SH(destreg,i) = r;
7645 }
7646 }
7647}
7648
7649// end-sanitize-r5900
7650// start-sanitize-r5900
7651
7652011100,5.RS,5.RT,5.RD,10000001000:MMI0:32::PADDSW
7653*r5900:
7654{
7655 unsigned32 instruction = instruction_0;
055ee297 7656 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7657 signed_word rs_reg = GPR[RS];
7658 signed_word rs_reg1 = GPR1[RS];
7659 signed_word rt_reg = GPR[RT];
7660 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7661 {
7662 int i;
7663 for (i=0; i < WORDS_IN_MMI_REGS; i++)
7664 {
7665 signed64 s = RS_SW(i);
7666 signed64 t = RT_SW(i);
7667 signed64 r = s + t;
7668 if (r > (int)0x7FFFFFFF)
7669 GPR_SW(destreg,i) = (int)0x7FFFFFFF;
7670 else if (r < (int)0x80000000)
7671 GPR_SW(destreg,i) = (int)0x80000000;
7672 else
7673 GPR_SW(destreg,i) = r;
7674 }
7675 }
7676}
7677
7678// end-sanitize-r5900
7679// start-sanitize-r5900
7680
7681011100,5.RS,5.RT,5.RD,11000101000:MMI1:32::PADDUB
7682*r5900:
7683{
7684 unsigned32 instruction = instruction_0;
055ee297 7685 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7686 signed_word rs_reg = GPR[RS];
7687 signed_word rs_reg1 = GPR1[RS];
7688 signed_word rt_reg = GPR[RT];
7689 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7690 {
7691 int i;
7692 for (i=0; i < BYTES_IN_MMI_REGS; i++)
7693 {
7694 unsigned int s = RS_UB(i);
7695 unsigned int t = RT_UB(i);
7696 unsigned int r = s + t;
7697 if (r > 0xFF)
7698 GPR_UB(destreg,i) = 0xFF;
7699 else
7700 GPR_UB(destreg,i) = r;
7701 }
7702 }
7703}
7704
7705// end-sanitize-r5900
7706// start-sanitize-r5900
7707
7708011100,5.RS,5.RT,5.RD,10100101000:MMI1:32::PADDUH
7709*r5900:
7710{
7711 unsigned32 instruction = instruction_0;
055ee297 7712 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7713 signed_word rs_reg = GPR[RS];
7714 signed_word rs_reg1 = GPR1[RS];
7715 signed_word rt_reg = GPR[RT];
7716 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7717 {
7718 int i;
7719 for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
7720 {
7721 unsigned int s = RS_UH(i);
7722 unsigned int t = RT_UH(i);
7723 unsigned int r = s + t;
7724 if (r > 0xFFFF)
7725 GPR_UH(destreg,i) = 0xFFFF;
7726 else
7727 GPR_UH(destreg,i) = r;
7728 }
7729 }
7730}
7731
7732// end-sanitize-r5900
7733// start-sanitize-r5900
7734
7735011100,5.RS,5.RT,5.RD,10000101000:MMI1:32::PADDUW
7736*r5900:
7737{
7738 unsigned32 instruction = instruction_0;
055ee297 7739 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7740 signed_word rs_reg = GPR[RS];
7741 signed_word rs_reg1 = GPR1[RS];
7742 signed_word rt_reg = GPR[RT];
7743 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7744 {
7745 int i;
7746 for (i=0; i < WORDS_IN_MMI_REGS; i++)
7747 {
7748 unsigned64 s = RS_UW(i);
7749 unsigned64 t = RT_UW(i);
7750 unsigned64 r = s + t;
7751 if (r > 0xFFFFFFFF)
7752 GPR_UW(destreg,i) = 0xFFFFFFFF;
7753 else
7754 GPR_UW(destreg,i) = r;
7755 }
7756 }
7757}
7758
7759// end-sanitize-r5900
7760// start-sanitize-r5900
7761
7762011100,5.RS,5.RT,5.RD,00100101000:MMI1:32::PADSBH
7763*r5900:
7764{
7765 unsigned32 instruction = instruction_0;
055ee297 7766 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7767 signed_word rs_reg = GPR[RS];
7768 signed_word rs_reg1 = GPR1[RS];
7769 signed_word rt_reg = GPR[RT];
7770 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7771 {
7772 int i;
7773 for(i=0;i<HALFWORDS_IN_MMI_REGS/2;i++)
7774 GPR_SH(destreg,i) = RS_SH(i) - RT_SH(i);
7775 for(;i<HALFWORDS_IN_MMI_REGS;i++)
7776 GPR_SH(destreg,i) = RS_SH(i) + RT_SH(i);
7777 }
7778}
7779
7780// end-sanitize-r5900
7781// start-sanitize-r5900
7782
7783011100,5.RS,5.RT,5.RD,10010001001:MMI2:32::PAND
7784*r5900:
7785{
7786 unsigned32 instruction = instruction_0;
055ee297 7787 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7788 signed_word rs_reg = GPR[RS];
7789 signed_word rs_reg1 = GPR1[RS];
7790 signed_word rt_reg = GPR[RT];
7791 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7792 {
7793 int i;
7794 for(i=0;i<WORDS_IN_MMI_REGS;i++)
7795 GPR_UW(destreg,i) = (RS_UW(i) & RT_UW(i));
7796 }
7797}
7798
7799// end-sanitize-r5900
7800// start-sanitize-r5900
7801
7802011100,5.RS,5.RT,5.RD,01010101000:MMI1:32::PCEQB
7803*r5900:
7804{
7805 unsigned32 instruction = instruction_0;
055ee297 7806 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7807 signed_word rs_reg = GPR[RS];
7808 signed_word rs_reg1 = GPR1[RS];
7809 signed_word rt_reg = GPR[RT];
7810 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7811 {
7812 int i;
7813 for(i=0;i<BYTES_IN_MMI_REGS;i++)
7814 {
7815 if (RS_SB(i) == RT_SB(i)) GPR_SB(destreg,i) = 0xFF;
7816 else GPR_SB(destreg,i) = 0;
7817 }
7818 }
7819}
7820
7821// end-sanitize-r5900
7822// start-sanitize-r5900
7823
7824011100,5.RS,5.RT,5.RD,00110101000:MMI1:32::PCEQH
7825*r5900:
7826{
7827 unsigned32 instruction = instruction_0;
055ee297 7828 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7829 signed_word rs_reg = GPR[RS];
7830 signed_word rs_reg1 = GPR1[RS];
7831 signed_word rt_reg = GPR[RT];
7832 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7833 {
7834 int i;
7835 for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
7836 {
7837 if (RS_SH(i) == RT_SH(i)) GPR_SH(destreg,i) = 0xFFFF;
7838 else GPR_SH(destreg,i) = 0;
7839 }
7840 }
7841}
7842
7843// end-sanitize-r5900
7844// start-sanitize-r5900
7845
7846011100,5.RS,5.RT,5.RD,00010101000:MMI1:32::PCEQW
7847*r5900:
7848{
7849 unsigned32 instruction = instruction_0;
055ee297 7850 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7851 signed_word rs_reg = GPR[RS];
7852 signed_word rs_reg1 = GPR1[RS];
7853 signed_word rt_reg = GPR[RT];
7854 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7855 {
7856 int i;
7857 for(i=0;i<WORDS_IN_MMI_REGS;i++)
7858 {
7859 if (RS_SW(i) == RT_SW(i)) GPR_SW(destreg,i) = 0xFFFFFFFF;
7860 else GPR_SW(destreg,i) = 0;
7861 }
7862 }
7863}
7864
7865// end-sanitize-r5900
7866// start-sanitize-r5900
7867
7868011100,5.RS,5.RT,5.RD,01010001000:MMI0:32::PCGTB
7869*r5900:
7870{
7871 unsigned32 instruction = instruction_0;
055ee297 7872 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7873 signed_word rs_reg = GPR[RS];
7874 signed_word rs_reg1 = GPR1[RS];
7875 signed_word rt_reg = GPR[RT];
7876 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7877 {
7878 int i;
7879 for(i=0;i<BYTES_IN_MMI_REGS;i++)
7880 {
7881 if (RS_SB(i) > RT_SB(i)) GPR_SB(destreg,i) = 0xFF;
7882 else GPR_SB(destreg,i) = 0;
7883 }
7884 }
7885}
7886
7887// end-sanitize-r5900
7888// start-sanitize-r5900
7889
7890011100,5.RS,5.RT,5.RD,00110001000:MMI0:32::PCGTH
7891*r5900:
7892{
7893 unsigned32 instruction = instruction_0;
055ee297 7894 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7895 signed_word rs_reg = GPR[RS];
7896 signed_word rs_reg1 = GPR1[RS];
7897 signed_word rt_reg = GPR[RT];
7898 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7899 {
7900 int i;
7901 for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
7902 {
7903 if (RS_SH(i) > RT_SH(i)) GPR_SH(destreg,i) = 0xFFFF;
7904 else GPR_SH(destreg,i) = 0;
7905 }
7906 }
7907}
7908
7909// end-sanitize-r5900
7910// start-sanitize-r5900
7911
7912011100,5.RS,5.RT,5.RD,00010001000:MMI0:32::PCGTW
7913*r5900:
7914{
7915 unsigned32 instruction = instruction_0;
055ee297 7916 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7917 signed_word rs_reg = GPR[RS];
7918 signed_word rs_reg1 = GPR1[RS];
7919 signed_word rt_reg = GPR[RT];
7920 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7921 {
7922 int i;
7923 for(i=0;i<WORDS_IN_MMI_REGS;i++)
7924 {
7925 if (RS_SW(i) > RT_SW(i)) GPR_SW(destreg,i) = 0xFFFFFFFF;
7926 else GPR_SW(destreg,i) = 0;
7927 }
7928 }
7929}
7930
7931// end-sanitize-r5900
7932// start-sanitize-r5900
7933
793401110000000,5.RT,5.RD,11011101001:MMI3:32::PCPYH
7935*r5900:
7936{
7937 unsigned32 instruction = instruction_0;
055ee297 7938 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7939 signed_word rt_reg = GPR[RT];
7940 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7941 {
7942 GPR_UH(destreg,7) = GPR_UH(destreg,6) = GPR_UH(destreg,5) = GPR_UH(destreg,4) = RT_UH(4);
7943 GPR_UH(destreg,3) = GPR_UH(destreg,2) = GPR_UH(destreg,1) = GPR_UH(destreg,0) = RT_UH(0);
7944 }
7945}
7946
7947// end-sanitize-r5900
7948// start-sanitize-r5900
7949
7950011100,5.RS,5.RT,5.RD,01110001001:MMI2:32::PCPYLD
7951*r5900:
7952{
7953 unsigned32 instruction = instruction_0;
055ee297 7954 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7955 signed_word rs_reg = GPR[RS];
7956 signed_word rs_reg1 = GPR1[RS];
7957 signed_word rt_reg = GPR[RT];
7958 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7959 {
7960 GPR_UD(destreg,0) = RT_UD(0);
7961 GPR_UD(destreg,1) = RS_UD(0);
7962 }
7963}
7964
7965// end-sanitize-r5900
7966// start-sanitize-r5900
7967
7968011100,5.RS,5.RT,5.RD,01110101001:MMI3:32::PCPYUD
7969*r5900:
7970{
7971 unsigned32 instruction = instruction_0;
055ee297 7972 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 7973 signed_word rs_reg = GPR[RS];
7974 signed_word rs_reg1 = GPR1[RS];
7975 signed_word rt_reg = GPR[RT];
7976 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7977 {
7978 GPR_UD(destreg,0) = RS_UD(1);
7979 GPR_UD(destreg,1) = RT_UD(1);
7980 }
7981}
7982
7983// end-sanitize-r5900
7984// start-sanitize-r5900
7985
7986011100,5.RS,5.RT,0000011101001001:MMI2:32::PDIVBW
7987*r5900:
7988{
085c1cb9
AC		 7989 signed_word rs_reg = GPR[RS];
7990 signed_word rs_reg1 = GPR1[RS];
7991 signed_word rt_reg = GPR[RT];
7992 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 7993 {
7994 signed32 devisor = RT_SH(0);
7995 if (devisor == -1)
7996 {
7997 LO_SW(0) = -RS_SW(0);
7998 HI_SW(0) = 0;
7999 LO_SW(1) = -RS_SW(1);
8000 HI_SW(1) = 0;
8001 LO_SW(2) = -RS_SW(2);
8002 HI_SW(2) = 0;
8003 LO_SW(3) = -RS_SW(3);
8004 HI_SW(3) = 0;
8005 }
8006 else if (devisor != 0)
8007 {
8008 LO_SW(0) = RS_SW(0) / devisor;
8009 HI_SW(0) = SIGNEXTEND( (RS_SW(0) % devisor), 16 );
8010 LO_SW(1) = RS_SW(1) / devisor;
8011 HI_SW(1) = SIGNEXTEND( (RS_SW(1) % devisor), 16 );
8012 LO_SW(2) = RS_SW(2) / devisor;
8013 HI_SW(2) = SIGNEXTEND( (RS_SW(2) % devisor), 16 );
8014 LO_SW(3) = RS_SW(3) / devisor;
8015 HI_SW(3) = SIGNEXTEND( (RS_SW(3) % devisor), 16 );
8016 }
8017 }
8018}
8019
8020// end-sanitize-r5900
8021// start-sanitize-r5900
8022
8023011100,5.RS,5.RT,0000001101101001:MMI3:32::PDIVUW
8024*r5900:
8025{
085c1cb9
AC		 8026 signed_word rs_reg = GPR[RS];
8027 signed_word rs_reg1 = GPR1[RS];
8028 signed_word rt_reg = GPR[RT];
8029 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8030 {
8031 if (RT_UW(0) != 0)
8032 {
8033 LO = (signed32)(RS_UW(0) / RT_UW(0));
8034 HI = (signed32)(RS_UW(0) % RT_UW(0));
8035 }
8036 if (RT_UW(2) != 0)
8037 {
8038 LO1 = (signed32)(RS_UW(2) / RT_UW(2));
8039 HI1 = (signed32)(RS_UW(2) % RT_UW(2));
8040 }
8041 }
8042}
8043
8044// end-sanitize-r5900
8045// start-sanitize-r5900
8046
8047011100,5.RS,5.RT,0000001101001001:MMI2:32::PDIVW
8048*r5900:
8049{
085c1cb9
AC		 8050 signed_word rs_reg = GPR[RS];
8051 signed_word rs_reg1 = GPR1[RS];
8052 signed_word rt_reg = GPR[RT];
8053 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8054 {
8055 if (RT_SW(0) == -1)
8056 {
8057 LO = -RS_SW(0);
8058 HI = 0;
8059 }
8060 else if (RT_UW(0) != 0)
8061 {
8062 LO = (signed32)(RS_SW(0) / RT_SW(0));
8063 HI = (signed32)(RS_SW(0) % RT_SW(0));
8064 }
8065 if (RT_SW(2) == -1)
8066 {
8067 LO1 = -RS_SW(2);
8068 HI1 = 0;
8069 }
8070 else if (RT_UW(2) != 0)
8071 {
8072 LO1 = (signed32)(RS_SW(2) / RT_SW(2));
8073 HI1 = (signed32)(RS_SW(2) % RT_SW(2));
8074 }
8075 }
8076}
8077
8078// end-sanitize-r5900
8079// start-sanitize-r5900
8080
808101110000000,5.RT,5.RD,11010101001:MMI3:32::PEXCH
8082*r5900:
8083{
8084 unsigned32 instruction = instruction_0;
055ee297 8085 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 8086 signed_word rt_reg = GPR[RT];
8087 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8088 {
8089 GPR_UH(destreg,0) = RT_UH(0);
8090 GPR_UH(destreg,1) = RT_UH(2);
8091 GPR_UH(destreg,2) = RT_UH(1);
8092 GPR_UH(destreg,3) = RT_UH(3);
8093 GPR_UH(destreg,4) = RT_UH(4);
8094 GPR_UH(destreg,5) = RT_UH(6);
8095 GPR_UH(destreg,6) = RT_UH(5);
8096 GPR_UH(destreg,7) = RT_UH(7);
8097 }
8098}
8099
8100// end-sanitize-r5900
8101// start-sanitize-r5900
8102
810301110000000,5.RT,5.RD,11110101001:MMI3:32::PEXCW
8104*r5900:
8105{
8106 unsigned32 instruction = instruction_0;
055ee297 8107 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 8108 signed_word rt_reg = GPR[RT];
8109 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8110 {
8111 GPR_UW(destreg,0) = RT_UW(0);
8112 GPR_UW(destreg,1) = RT_UW(2);
8113 GPR_UW(destreg,2) = RT_UW(1);
8114 GPR_UW(destreg,3) = RT_UW(3);
8115 }
8116}
8117
8118// end-sanitize-r5900
8119// start-sanitize-r5900
8120
812101110000000,5.RT,5.RD,11010001001:MMI2:32::PEXOH
8122*r5900:
8123{
8124 unsigned32 instruction = instruction_0;
055ee297 8125 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 8126 signed_word rt_reg = GPR[RT];
8127 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8128 {
8129 GPR_UH(destreg,0) = RT_UH(2);
8130 GPR_UH(destreg,1) = RT_UH(1);
8131 GPR_UH(destreg,2) = RT_UH(0);
8132 GPR_UH(destreg,3) = RT_UH(3);
8133 GPR_UH(destreg,4) = RT_UH(6);
8134 GPR_UH(destreg,5) = RT_UH(5);
8135 GPR_UH(destreg,6) = RT_UH(4);
8136 GPR_UH(destreg,7) = RT_UH(7);
8137 }
8138}
8139
8140// end-sanitize-r5900
8141// start-sanitize-r5900
8142
814301110000000,5.RT,5.RD,11110001001:MMI2:32::PEXOW
8144*r5900:
8145{
8146 unsigned32 instruction = instruction_0;
055ee297 8147 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 8148 signed_word rt_reg = GPR[RT];
8149 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8150 {
8151 GPR_UW(destreg,0) = RT_UW(2);
8152 GPR_UW(destreg,1) = RT_UW(1);
8153 GPR_UW(destreg,2) = RT_UW(0);
8154 GPR_UW(destreg,3) = RT_UW(3);
8155 }
8156}
8157
8158// end-sanitize-r5900
8159// start-sanitize-r5900
8160
816101110000000,5.RT,5.RD,11110001000:MMI0:32::PEXT5
8162*r5900:
8163{
8164 unsigned32 instruction = instruction_0;
055ee297 8165 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 8166 signed_word rt_reg = GPR[RT];
8167 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8168 {
8169 int i;
8170 for(i=0;i<WORDS_IN_MMI_REGS;i++)
8171 {
8172 unsigned32 x = RT_UW(i);
8173 GPR_UW(destreg,i) = ((x & (1 << 15)) << (31 - 15))
8174 | ((x & (31 << 10)) << (19 - 10))
8175 | ((x & (31 << 5)) << (11 - 5))
8176 | ((x & (31 << 0)) << (3 - 0));
8177 }
8178 }
8179}
8180
8181// end-sanitize-r5900
8182// start-sanitize-r5900
8183
8184011100,5.RS,5.RT,5.RD,11010001000:MMI0:32::PEXTLB
8185*r5900:
8186{
8187 unsigned32 instruction = instruction_0;
055ee297 8188 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8189 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8190 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8191 signed_word rt_reg = GPR[RT];
8192 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8193 {
8194 GPR_UB(destreg,0) = RT_UB(0);
8195 GPR_UB(destreg,1) = RS_UB(0);
8196 GPR_UB(destreg,2) = RT_UB(1);
8197 GPR_UB(destreg,3) = RS_UB(1);
8198 GPR_UB(destreg,4) = RT_UB(2);
8199 GPR_UB(destreg,5) = RS_UB(2);
8200 GPR_UB(destreg,6) = RT_UB(3);
8201 GPR_UB(destreg,7) = RS_UB(3);
8202 GPR_UB(destreg,8) = RT_UB(4);
8203 GPR_UB(destreg,9) = RS_UB(4);
8204 GPR_UB(destreg,10) = RT_UB(5);
8205 GPR_UB(destreg,11) = RS_UB(5);
8206 GPR_UB(destreg,12) = RT_UB(6);
8207 GPR_UB(destreg,13) = RS_UB(6);
8208 GPR_UB(destreg,14) = RT_UB(7);
8209 GPR_UB(destreg,15) = RS_UB(7);
8210 }
8211}
8212
8213// end-sanitize-r5900
8214// start-sanitize-r5900
8215
8216011100,5.RS,5.RT,5.RD,10110001000:MMI0:32::PEXTLH
8217*r5900:
8218{
8219 unsigned32 instruction = instruction_0;
055ee297 8220 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8221 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8222 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8223 signed_word rt_reg = GPR[RT];
8224 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8225 {
8226 GPR_UH(destreg,0) = RT_UH(0);
8227 GPR_UH(destreg,1) = RS_UH(0);
8228 GPR_UH(destreg,2) = RT_UH(1);
8229 GPR_UH(destreg,3) = RS_UH(1);
8230 GPR_UH(destreg,4) = RT_UH(2);
8231 GPR_UH(destreg,5) = RS_UH(2);
8232 GPR_UH(destreg,6) = RT_UH(3);
8233 GPR_UH(destreg,7) = RS_UH(3);
8234 }
8235}
8236
8237// end-sanitize-r5900
8238// start-sanitize-r5900
8239
8240011100,5.RS,5.RT,5.RD,10010001000:MMI0:32::PEXTLW
8241*r5900:
8242{
8243 unsigned32 instruction = instruction_0;
055ee297 8244 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8245 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8246 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8247 signed_word rt_reg = GPR[RT];
8248 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8249 {
8250 GPR_UW(destreg,0) = RT_UW(0);
8251 GPR_UW(destreg,1) = RS_UW(0);
8252 GPR_UW(destreg,2) = RT_UW(1);
8253 GPR_UW(destreg,3) = RS_UW(1);
8254 }
8255}
8256
8257// end-sanitize-r5900
8258// start-sanitize-r5900
8259
8260011100,5.RS,5.RT,5.RD,11010101000:MMI1:32::PEXTUB
8261*r5900:
8262{
8263 unsigned32 instruction = instruction_0;
055ee297 8264 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8265 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8266 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8267 signed_word rt_reg = GPR[RT];
8268 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8269 {
8270 GPR_UB(destreg,0) = RT_UB(8);
8271 GPR_UB(destreg,1) = RS_UB(8);
8272 GPR_UB(destreg,2) = RT_UB(9);
8273 GPR_UB(destreg,3) = RS_UB(9);
8274 GPR_UB(destreg,4) = RT_UB(10);
8275 GPR_UB(destreg,5) = RS_UB(10);
8276 GPR_UB(destreg,6) = RT_UB(11);
8277 GPR_UB(destreg,7) = RS_UB(11);
8278 GPR_UB(destreg,8) = RT_UB(12);
8279 GPR_UB(destreg,9) = RS_UB(12);
8280 GPR_UB(destreg,10) = RT_UB(13);
8281 GPR_UB(destreg,11) = RS_UB(13);
8282 GPR_UB(destreg,12) = RT_UB(14);
8283 GPR_UB(destreg,13) = RS_UB(14);
8284 GPR_UB(destreg,14) = RT_UB(15);
8285 GPR_UB(destreg,15) = RS_UB(15);
8286 }
8287}
8288
8289// end-sanitize-r5900
8290// start-sanitize-r5900
8291
8292011100,5.RS,5.RT,5.RD,10110101000:MMI1:32::PEXTUH
8293*r5900:
8294{
8295 unsigned32 instruction = instruction_0;
055ee297 8296 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8297 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8298 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8299 signed_word rt_reg = GPR[RT];
8300 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8301 {
8302 GPR_UH(destreg,0) = RT_UH(4);
8303 GPR_UH(destreg,1) = RS_UH(4);
8304 GPR_UH(destreg,2) = RT_UH(5);
8305 GPR_UH(destreg,3) = RS_UH(5);
8306 GPR_UH(destreg,4) = RT_UH(6);
8307 GPR_UH(destreg,5) = RS_UH(6);
8308 GPR_UH(destreg,6) = RT_UH(7);
8309 GPR_UH(destreg,7) = RS_UH(7);
8310 }
8311}
8312
8313// end-sanitize-r5900
8314// start-sanitize-r5900
8315
8316011100,5.RS,5.RT,5.RD,10010101000:MMI1:32::PEXTUW
8317*r5900:
8318{
8319 unsigned32 instruction = instruction_0;
055ee297 8320 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8321 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8322 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8323 signed_word rt_reg = GPR[RT];
8324 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8325 {
8326 GPR_UW(destreg,0) = RT_UW(2);
8327 GPR_UW(destreg,1) = RS_UW(2);
8328 GPR_UW(destreg,2) = RT_UW(3);
8329 GPR_UW(destreg,3) = RS_UW(3);
8330 }
8331}
8332
8333// end-sanitize-r5900
8334// start-sanitize-r5900
8335
8336011100,5.RS,5.RT,5.RD,10001001001:MMI2:32::PHMADDH
8337*r5900:
8338{
8339 unsigned32 instruction = instruction_0;
055ee297 8340 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8341 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8342 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8343 signed_word rt_reg = GPR[RT];
8344 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8345 {
8346 GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(1) * RT_SH(1)) + (RS_SH(0) * RT_SH(0));
8347 GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(3) * RT_SH(3)) + (RS_SH(2) * RT_SH(2));
8348 GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(5) * RT_SH(5)) + (RS_SH(4) * RT_SH(4));
8349 GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(7) * RT_SH(7)) + (RS_SH(6) * RT_SH(6));
8350 }
8351}
8352
8353// end-sanitize-r5900
8354// start-sanitize-r5900
8355
8356011100,5.RS,5.RT,5.RD,10101001001:MMI2:32::PHMSUBH
8357*r5900:
8358{
8359 unsigned32 instruction = instruction_0;
055ee297 8360 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8361 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8362 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8363 signed_word rt_reg = GPR[RT];
8364 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8365 {
8366 GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(1) * RT_SH(1)) - (RS_SH(0) * RT_SH(0));
8367 GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(3) * RT_SH(3)) - (RS_SH(2) * RT_SH(2));
8368 GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(5) * RT_SH(5)) - (RS_SH(4) * RT_SH(4));
8369 GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(7) * RT_SH(7)) - (RS_SH(6) * RT_SH(6));
8370 }
8371}
8372
8373// end-sanitize-r5900
8374// start-sanitize-r5900
8375
8376011100,5.RS,5.RT,5.RD,01010001001:MMI2:32::PINTH
8377*r5900:
8378{
8379 unsigned32 instruction = instruction_0;
055ee297 8380 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8381 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8382 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8383 signed_word rt_reg = GPR[RT];
8384 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8385 {
8386 GPR_UH(destreg,0) = RT_UH(0);
8387 GPR_UH(destreg,1) = RS_UH(4);
8388 GPR_UH(destreg,2) = RT_UH(1);
8389 GPR_UH(destreg,3) = RS_UH(5);
8390 GPR_UH(destreg,4) = RT_UH(2);
8391 GPR_UH(destreg,5) = RS_UH(6);
8392 GPR_UH(destreg,6) = RT_UH(3);
8393 GPR_UH(destreg,7) = RS_UH(7);
8394 }
8395}
8396
8397// end-sanitize-r5900
8398// start-sanitize-r5900
8399
8400011100,5.RS,5.RT,5.RD,01010101001:MMI3:32::PINTOH
8401*r5900:
8402{
8403 unsigned32 instruction = instruction_0;
055ee297 8404 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8405 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8406 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8407 signed_word rt_reg = GPR[RT];
8408 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8409 {
8410 GPR_UH(destreg,0) = RT_UH(0);
8411 GPR_UH(destreg,1) = RS_UH(0);
8412 GPR_UH(destreg,2) = RT_UH(2);
8413 GPR_UH(destreg,3) = RS_UH(2);
8414 GPR_UH(destreg,4) = RT_UH(4);
8415 GPR_UH(destreg,5) = RS_UH(4);
8416 GPR_UH(destreg,6) = RT_UH(6);
8417 GPR_UH(destreg,7) = RS_UH(6);
8418 }
8419}
8420
8421// end-sanitize-r5900
8422// start-sanitize-r5900
8423
8424011100,5.RS,00000,5.RD,00000000100:MMINORM:32::PLZCW
8425*r5900:
8426{
8427 unsigned32 instruction = instruction_0;
055ee297
AC		 8428 int destreg = ((instruction >> 11) & 0x0000001F);
8429 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8430 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 8431 {
8432 unsigned long value;
8433 int test;
8434 int count;
8435 int i;
8436 value = RS_UW(0);
8437 count = 0;
8438 test = !!(value & (1 << 31));
8439 for(i=30; i>=0 && (test == !!(value & (1 << i))); i--)
8440 count++;
8441 GPR_UW(destreg,0) = count;
8442 value = RS_UW(1);
8443 count = 0;
8444 test = !!(value & (1 << 31));
8445 for(i=30; i>=0 && (test == !!(value & (1 << i))); i--)
8446 count++;
8447 GPR_UW(destreg,1) = count;
8448 }
8449}
8450
8451// end-sanitize-r5900
8452// start-sanitize-r5900
8453
8454011100,5.RS,5.RT,5.RD,10000001001:MMI2:32::PMADDH
8455*r5900:
8456{
8457 unsigned32 instruction = instruction_0;
055ee297 8458 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8459 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8460 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8461 signed_word rt_reg = GPR[RT];
8462 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8463 {
8464 GPR_SW(destreg,0) = LO_SW(0) += (RS_SH(0) * RT_SH(0));
8465 LO_SW(1) += (RS_SH(1) * RT_SH(1));
8466 GPR_SW(destreg,1) = HI_SW(0) += (RS_SH(2) * RT_SH(2));
8467 HI_SW(1) += (RS_SH(3) * RT_SH(3));
8468 GPR_SW(destreg,2) = LO_SW(2) += (RS_SH(4) * RT_SH(4));
8469 LO_SW(3) += (RS_SH(5) * RT_SH(5));
8470 GPR_SW(destreg,3) = HI_SW(2) += (RS_SH(6) * RT_SH(6));
8471 HI_SW(3) += (RS_SH(7) * RT_SH(7));
8472 }
8473}
8474
8475// end-sanitize-r5900
8476// start-sanitize-r5900
8477
8478011100,5.RS,5.RT,5.RD,00000101001:MMI3:32::PMADDUW
8479*r5900:
8480{
8481 unsigned32 instruction = instruction_0;
055ee297 8482 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8483 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8484 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8485 signed_word rt_reg = GPR[RT];
8486 signed_word rt_reg1 = GPR1[RT];
f2b30012 8487 {
055ee297 8488 unsigned64 sum0 = U8_4 (HI_SW(0), LO_SW(0));
085c1cb9 8489 unsigned64 sum1 = U8_4 (HI_SW(2), LO_SW(2));
f2b30012
AC		 8490 unsigned64 prod0 = (unsigned64)RS_UW(0) * (unsigned64)RT_UW(0);
8491 unsigned64 prod1 = (unsigned64)RS_UW(2) * (unsigned64)RT_UW(2);
8492 sum0 += prod0;
8493 sum1 += prod1;
8494 GPR_UD(destreg,0) = sum0;
8495 GPR_UD(destreg,1) = sum1;
8496 LO = SIGNEXTEND( sum0, 32 );
8497 HI = SIGNEXTEND( VH4_8(sum0), 32 );
8498 LO1 = SIGNEXTEND( sum1, 32 );
8499 HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
8500 }
8501}
8502
8503// end-sanitize-r5900
8504// start-sanitize-r5900
8505
8506011100,5.RS,5.RT,5.RD,00000001001:MMI2:32::PMADDW
8507*r5900:
8508{
8509 unsigned32 instruction = instruction_0;
055ee297 8510 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8511 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8512 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8513 signed_word rt_reg = GPR[RT];
8514 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8515 {
8516 signed64 sum0 = WORD64( HI_SW(0), LO_SW(0) );
8517 signed64 sum1 = WORD64( HI_SW(2), LO_SW(2) );
8518 signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0);
8519 signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2);
8520 sum0 += prod0;
8521 sum1 += prod1;
8522 GPR_SD(destreg,0) = sum0;
8523 GPR_SD(destreg,1) = sum1;
8524 LO = SIGNEXTEND( sum0, 32 );
8525 HI = SIGNEXTEND( VH4_8(sum0), 32 );
8526 LO1 = SIGNEXTEND( sum1, 32 );
8527 HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
8528 }
8529}
8530
8531// end-sanitize-r5900
8532// start-sanitize-r5900
8533
8534011100,5.RS,5.RT,5.RD,00111001000:MMI0:32::PMAXH
8535*r5900:
8536{
8537 unsigned32 instruction = instruction_0;
055ee297 8538 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8539 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8540 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8541 signed_word rt_reg = GPR[RT];
8542 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8543 {
8544 int i;
8545 for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
8546 {
8547 if (RS_SH(i) > RT_SH(i)) GPR_SH(destreg,i) = RS_SH(i);
8548 else GPR_SH(destreg,i) = RT_SH(i);
8549 }
8550 }
8551}
8552
8553// end-sanitize-r5900
8554// start-sanitize-r5900
8555
8556011100,5.RS,5.RT,5.RD,00011001000:MMI0:32::PMAXW
8557*r5900:
8558{
8559 unsigned32 instruction = instruction_0;
055ee297 8560 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8561 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8562 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8563 signed_word rt_reg = GPR[RT];
8564 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8565 {
8566 int i;
8567 for(i=0;i<WORDS_IN_MMI_REGS;i++)
8568 {
8569 if (RS_SW(i) > RT_SW(i)) GPR_SW(destreg,i) = RS_SW(i);
8570 else GPR_SW(destreg,i) = RT_SW(i);
8571 }
8572 }
8573}
8574
8575// end-sanitize-r5900
8576// start-sanitize-r5900
8577
85780111000000000000,5.RD,01000001001:MMI2:32::PMFHI
8579*r5900:
8580{
8581 unsigned32 instruction = instruction_0;
055ee297 8582 int destreg = ((instruction >> 11) & 0x0000001F);
f2b30012
AC		 8583 {
8584 GPR_SD(destreg,0) = HI;
8585 GPR_SD(destreg,1) = HI1;
8586 }
8587}
8588
8589// end-sanitize-r5900
8590// start-sanitize-r5900
8591
85920111000000000000,5.RD,01001001001:MMI2:32::PMFLO
8593*r5900:
8594{
8595 unsigned32 instruction = instruction_0;
055ee297 8596 int destreg = ((instruction >> 11) & 0x0000001F);
f2b30012
AC		 8597 {
8598 GPR_SD(destreg,0) = LO;
8599 GPR_SD(destreg,1) = LO1;
8600 }
8601}
8602
8603// end-sanitize-r5900
8604// start-sanitize-r5900
8605
055ee297 86060111000000000000,5.RD,5.SHIFT,110000:MMINORM:32::PMFHL
f2b30012
AC		 8607*r5900:
8608{
8609 unsigned32 instruction = instruction_0;
055ee297
AC		 8610 int op1 = ((instruction >> 6) & 0x0000001F);
8611 int destreg = ((instruction >> 11) & 0x0000001F);
f2b30012
AC		 8612 {
8613 if (op1 == 0)
8614 {
8615 GPR_UW(destreg,0) = LO_UW(0);
8616 GPR_UW(destreg,1) = HI_UW(0);
8617 GPR_UW(destreg,2) = LO_UW(2);
8618 GPR_UW(destreg,3) = HI_UW(2);
8619 }
8620 else if (op1 == 1)
8621 {
8622 GPR_UW(destreg,0) = LO_UW(1);
8623 GPR_UW(destreg,1) = HI_UW(1);
8624 GPR_UW(destreg,2) = LO_UW(3);
8625 GPR_UW(destreg,3) = HI_UW(3);
8626 }
8627 else if (op1 == 2)
8628 {
8629 /* NOTE: This code implements a saturate according to the
8630 figure on page B-115 and not according to the
8631 definition on page B-113 */
8632 signed64 t = ((unsigned64)HI_UW(0) << 32) | (unsigned64)LO_UW(0);
8633 signed64 u = ((unsigned64)HI_UW(2) << 32) | (unsigned64)LO_UW(2);
8634 if ( t > SIGNED64 (0x000000007FFFFFFF) )
8635 GPR_SD(destreg,0) = SIGNED64 (0x000000007FFFFFFF);
8636 else if ( t < - SIGNED64 (0x0000000080000000) )
8637 GPR_SD(destreg,0) = - SIGNED64 (0x0000000080000000);
8638 else
8639 GPR_SD(destreg,0) = t;
8640 if ( u > SIGNED64 (0x000000007FFFFFFF) )
8641 GPR_SD(destreg,1) = SIGNED64 (0x000000007FFFFFFF);
8642 else if ( u < - SIGNED64 (0x0000000080000000) )
8643 GPR_SD(destreg,1) = - SIGNED64 (0x0000000080000000);
8644 else
8645 GPR_SD(destreg,1) = u;
8646 }
8647 else if (op1 == 3)
8648 {
8649 GPR_UH(destreg,0) = LO_UH(0);
8650 GPR_UH(destreg,1) = LO_UH(2);
8651 GPR_UH(destreg,2) = HI_UH(0);
8652 GPR_UH(destreg,3) = HI_UH(2);
8653 GPR_UH(destreg,4) = LO_UH(4);
8654 GPR_UH(destreg,5) = LO_UH(6);
8655 GPR_UH(destreg,6) = HI_UH(4);
8656 GPR_UH(destreg,7) = HI_UH(6);
8657 }
8658 else if (op1 == 4)
8659 {
8660 if (LO_SW(0) > 0x7FFF)
8661 GPR_UH(destreg,0) = 0x7FFF;
8662 else if (LO_SW(0) < -0x8000)
8663 GPR_UH(destreg,0) = 0x8000;
8664 else
8665 GPR_UH(destreg,0) = LO_UH(0);
8666 if (LO_SW(1) > 0x7FFF)
8667 GPR_UH(destreg,1) = 0x7FFF;
8668 else if (LO_SW(1) < -0x8000)
8669 GPR_UH(destreg,1) = 0x8000;
8670 else
8671 GPR_UH(destreg,1) = LO_UH(2);
8672 if (HI_SW(0) > 0x7FFF)
8673 GPR_UH(destreg,2) = 0x7FFF;
8674 else if (HI_SW(0) < -0x8000)
8675 GPR_UH(destreg,2) = 0x8000;
8676 else
8677 GPR_UH(destreg,2) = HI_UH(0);
8678 if (HI_SW(1) > 0x7FFF)
8679 GPR_UH(destreg,3) = 0x7FFF;
8680 else if (HI_SW(1) < -0x8000)
8681 GPR_UH(destreg,3) = 0x8000;
8682 else
8683 GPR_UH(destreg,3) = HI_UH(2);
8684 if (LO_SW(2) > 0x7FFF)
8685 GPR_UH(destreg,4) = 0x7FFF;
8686 else if (LO_SW(2) < -0x8000)
8687 GPR_UH(destreg,4) = 0x8000;
8688 else
8689 GPR_UH(destreg,4) = LO_UH(4);
8690 if (LO_SW(3) > 0x7FFF)
8691 GPR_UH(destreg,5) = 0x7FFF;
8692 else if (LO_SW(3) < -0x8000)
8693 GPR_UH(destreg,5) = 0x8000;
8694 else
8695 GPR_UH(destreg,5) = LO_UH(6);
8696 if (HI_SW(2) > 0x7FFF)
8697 GPR_UH(destreg,6) = 0x7FFF;
8698 else if (HI_SW(2) < -0x8000)
8699 GPR_UH(destreg,6) = 0x8000;
8700 else
8701 GPR_UH(destreg,6) = HI_UH(4);
8702 if (HI_SW(3) > 0x7FFF)
8703 GPR_UH(destreg,7) = 0x7FFF;
8704 else if (HI_SW(3) < -0x8000)
8705 GPR_UH(destreg,7) = 0x8000;
8706 else
8707 GPR_UH(destreg,7) = HI_UH(6);
8708 }
8709 }
8710}
8711
8712// end-sanitize-r5900
8713// start-sanitize-r5900
8714
8715011100,5.RS,5.RT,5.RD,00111101000:MMI1:32::PMINH
8716*r5900:
8717{
8718 unsigned32 instruction = instruction_0;
055ee297 8719 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8720 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8721 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8722 signed_word rt_reg = GPR[RT];
8723 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8724 {
8725 int i;
8726 for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
8727 {
8728 if (RS_SH(i) < RT_SH(i)) GPR_SH(destreg,i) = RS_SH(i);
8729 else GPR_SH(destreg,i) = RT_SH(i);
8730 }
8731 }
8732}
8733
8734// end-sanitize-r5900
8735// start-sanitize-r5900
8736
8737011100,5.RS,5.RT,5.RD,00011101000:MMI1:32::PMINW
8738*r5900:
8739{
8740 unsigned32 instruction = instruction_0;
055ee297 8741 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8742 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8743 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8744 signed_word rt_reg = GPR[RT];
8745 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8746 {
8747 int i;
8748 for(i=0;i<WORDS_IN_MMI_REGS;i++)
8749 {
8750 if (RS_SW(i) < RT_SW(i)) GPR_SW(destreg,i) = RS_SW(i);
8751 else GPR_SW(destreg,i) = RT_SW(i);
8752 }
8753 }
8754}
8755
8756// end-sanitize-r5900
8757// start-sanitize-r5900
8758
8759011100,5.RS,5.RT,5.RD,10100001001:MMI2:32::PMSUBH
8760*r5900:
8761{
8762 unsigned32 instruction = instruction_0;
055ee297 8763 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8764 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8765 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8766 signed_word rt_reg = GPR[RT];
8767 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8768 {
8769 GPR_SW(destreg,0) = LO_SW(0) -= (RS_SH(0) * RT_SH(0));
8770 LO_SW(1) -= (RS_SH(1) * RT_SH(1));
8771 GPR_SW(destreg,1) = HI_SW(0) -= (RS_SH(2) * RT_SH(2));
8772 HI_SW(1) -= (RS_SH(3) * RT_SH(3));
8773 GPR_SW(destreg,2) = LO_SW(2) -= (RS_SH(4) * RT_SH(4));
8774 LO_SW(3) -= (RS_SH(5) * RT_SH(5));
8775 GPR_SW(destreg,3) = HI_SW(2) -= (RS_SH(6) * RT_SH(6));
8776 HI_SW(3) -= (RS_SH(7) * RT_SH(7));
8777 }
8778}
8779
8780// end-sanitize-r5900
8781// start-sanitize-r5900
8782
8783011100,5.RS,5.RT,5.RD,00100001001:MMI2:32::PMSUBW
8784*r5900:
8785{
8786 unsigned32 instruction = instruction_0;
055ee297 8787 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8788 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8789 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8790 signed_word rt_reg = GPR[RT];
8791 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8792 {
8793 signed64 sum0 = WORD64( HI_SW(0), LO_SW(0) );
8794 signed64 sum1 = WORD64( HI_SW(2), LO_SW(2) );
8795 signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0);
8796 signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2);
8797 sum0 -= prod0;
8798 sum1 -= prod1;
8799 GPR_SD(destreg,0) = sum0;
8800 GPR_SD(destreg,1) = sum1;
8801 LO = SIGNEXTEND( sum0, 32 );
8802 HI = SIGNEXTEND( VH4_8(sum0), 32 );
8803 LO1 = SIGNEXTEND( sum1, 32 );
8804 HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
8805 }
8806}
8807
8808// end-sanitize-r5900
8809// start-sanitize-r5900
8810
8811011100,5.RS,000000000001000101001:MMI3:32::PMTHI
8812*r5900:
8813{
8814 unsigned32 instruction = instruction_0;
055ee297
AC		 8815 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8816 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 8817 {
8818 HI = RS_SD(0);
8819 HI1 = RS_SD(1);
8820 }
8821}
8822
8823// end-sanitize-r5900
8824// start-sanitize-r5900
8825
8826011100,5.RS,000000000001001101001:MMI3:32::PMTLO
8827*r5900:
8828{
8829 unsigned32 instruction = instruction_0;
055ee297
AC		 8830 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8831 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 8832 {
8833 LO = RS_SD(0);
8834 LO1 = RS_SD(1);
8835 }
8836}
8837
8838// end-sanitize-r5900
8839// start-sanitize-r5900
8840
8841011100,5.RS,000000000000000110001:MMINORM:32::PMTHL.LW
8842*r5900:
8843{
8844 unsigned32 instruction = instruction_0;
055ee297
AC		 8845 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8846 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
f2b30012
AC		 8847 {
8848 LO_UW(0) = RS_UW(0);
8849 HI_UW(0) = RS_UW(1);
8850 LO_UW(2) = RS_UW(2);
8851 HI_UW(2) = RS_UW(3);
8852 }
8853}
8854
8855// end-sanitize-r5900
8856// start-sanitize-r5900
8857
8858011100,5.RS,5.RT,5.RD,11100001001:MMI2:32::PMULTH
8859*r5900:
8860{
8861 unsigned32 instruction = instruction_0;
055ee297 8862 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8863 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8864 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8865 signed_word rt_reg = GPR[RT];
8866 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8867 {
8868 GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(0) * RT_SH(0));
8869 LO_SW(1) = (RS_SH(1) * RT_SH(1));
8870 GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(2) * RT_SH(2));
8871 HI_SW(1) = (RS_SH(3) * RT_SH(3));
8872 GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(4) * RT_SH(4));
8873 LO_SW(3) = (RS_SH(5) * RT_SH(5));
8874 GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(6) * RT_SH(6));
8875 HI_SW(3) = (RS_SH(7) * RT_SH(7));
8876 }
8877}
8878
8879// end-sanitize-r5900
8880// start-sanitize-r5900
8881
8882011100,5.RS,5.RT,5.RD,01100101001:MMI3:32::PMULTUW
8883*r5900:
8884{
8885 unsigned32 instruction = instruction_0;
055ee297 8886 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8887 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8888 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8889 signed_word rt_reg = GPR[RT];
8890 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8891 {
8892 unsigned64 sum0 = 0;
8893 unsigned64 sum1 = 0;
8894 unsigned64 prod0 = (unsigned64)RS_UW(0) * (unsigned64)RT_UW(0);
8895 unsigned64 prod1 = (unsigned64)RS_UW(2) * (unsigned64)RT_UW(2);
8896 sum0 = prod0;
8897 sum1 = prod1;
8898 GPR_UD(destreg,0) = sum0;
8899 GPR_UD(destreg,1) = sum1;
8900 LO = SIGNEXTEND( sum0, 32 );
8901 HI = SIGNEXTEND( VH4_8(sum0), 32 );
8902 LO1 = SIGNEXTEND( sum1, 32 );
8903 HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
8904 }
8905}
8906
8907// end-sanitize-r5900
8908// start-sanitize-r5900
8909
8910011100,5.RS,5.RT,5.RD,01100001001:MMI2:32::PMULTW
8911*r5900:
8912{
8913 unsigned32 instruction = instruction_0;
055ee297 8914 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8915 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8916 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8917 signed_word rt_reg = GPR[RT];
8918 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8919 {
8920 signed64 sum0 = 0;
8921 signed64 sum1 = 0;
8922 signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0);
8923 signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2);
8924 sum0 = prod0;
8925 sum1 = prod1;
8926 GPR_SD(destreg,0) = sum0;
8927 GPR_SD(destreg,1) = sum1;
8928 LO = SIGNEXTEND( sum0, 32 );
8929 HI = SIGNEXTEND( VH4_8(sum0), 32 );
8930 LO1 = SIGNEXTEND( sum1, 32 );
8931 HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
8932 }
8933}
8934
8935// end-sanitize-r5900
8936// start-sanitize-r5900
8937
8938011100,5.RS,5.RT,5.RD,10011101001:MMI3:32::PNOR
8939*r5900:
8940{
8941 unsigned32 instruction = instruction_0;
055ee297 8942 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8943 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8944 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8945 signed_word rt_reg = GPR[RT];
8946 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8947 {
8948 int i;
8949 for(i=0;i<WORDS_IN_MMI_REGS;i++)
8950 GPR_UW(destreg,i) = ~(RS_UW(i) | RT_UW(i));
8951 }
8952}
8953
8954// end-sanitize-r5900
8955// start-sanitize-r5900
8956
8957011100,5.RS,5.RT,5.RD,10010101001:MMI3:32::POR
8958*r5900:
8959{
8960 unsigned32 instruction = instruction_0;
055ee297 8961 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 8962 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8963 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 8964 signed_word rt_reg = GPR[RT];
8965 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8966 {
8967 int i;
8968 for(i=0;i<WORDS_IN_MMI_REGS;i++)
8969 GPR_UW(destreg,i) = (RS_UW(i) | RT_UW(i));
8970 }
8971}
8972
8973// end-sanitize-r5900
8974// start-sanitize-r5900
8975
897601110000000,5.RT,5.RD,11111001000:MMI0:32::PPAC5
8977*r5900:
8978{
8979 unsigned32 instruction = instruction_0;
055ee297 8980 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 8981 signed_word rt_reg = GPR[RT];
8982 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 8983 {
8984 int i;
8985 for(i=0;i<WORDS_IN_MMI_REGS;i++)
8986 {
8987 unsigned32 x = RT_UW(i);
8988 GPR_UW(destreg,i) = ((x & (1 << 31)) >> (31 - 15))
8989 | ((x & (31 << 19)) >> (19 - 10))
8990 | ((x & (31 << 11)) >> (11 - 5))
8991 | ((x & (31 << 3)) >> (3 - 0));
8992 }
8993 }
8994}
8995
8996// end-sanitize-r5900
8997// start-sanitize-r5900
8998
8999011100,5.RS,5.RT,5.RD,11011001000:MMI0:32::PPACB
9000*r5900:
9001{
9002 unsigned32 instruction = instruction_0;
055ee297 9003 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9004 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9005 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9006 signed_word rt_reg = GPR[RT];
9007 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9008 {
9009 GPR_UB(destreg,0) = RT_UB(0);
9010 GPR_UB(destreg,1) = RT_UB(2);
9011 GPR_UB(destreg,2) = RT_UB(4);
9012 GPR_UB(destreg,3) = RT_UB(6);
9013 GPR_UB(destreg,4) = RT_UB(8);
9014 GPR_UB(destreg,5) = RT_UB(10);
9015 GPR_UB(destreg,6) = RT_UB(12);
9016 GPR_UB(destreg,7) = RT_UB(14);
9017 GPR_UB(destreg,8) = RS_UB(0);
9018 GPR_UB(destreg,9) = RS_UB(2);
9019 GPR_UB(destreg,10) = RS_UB(4);
9020 GPR_UB(destreg,11) = RS_UB(6);
9021 GPR_UB(destreg,12) = RS_UB(8);
9022 GPR_UB(destreg,13) = RS_UB(10);
9023 GPR_UB(destreg,14) = RS_UB(12);
9024 GPR_UB(destreg,15) = RS_UB(14);
9025 }
9026}
9027
9028// end-sanitize-r5900
9029// start-sanitize-r5900
9030
9031011100,5.RS,5.RT,5.RD,10111001000:MMI0:32::PPACH
9032*r5900:
9033{
9034 unsigned32 instruction = instruction_0;
055ee297 9035 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9036 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9037 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9038 signed_word rt_reg = GPR[RT];
9039 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9040 {
9041 GPR_UH(destreg,0) = RT_UH(0);
9042 GPR_UH(destreg,1) = RT_UH(2);
9043 GPR_UH(destreg,2) = RT_UH(4);
9044 GPR_UH(destreg,3) = RT_UH(6);
9045 GPR_UH(destreg,4) = RS_UH(0);
9046 GPR_UH(destreg,5) = RS_UH(2);
9047 GPR_UH(destreg,6) = RS_UH(4);
9048 GPR_UH(destreg,7) = RS_UH(6);
9049 }
9050}
9051
9052// end-sanitize-r5900
9053// start-sanitize-r5900
9054
9055011100,5.RS,5.RT,5.RD,10011001000:MMI0:32::PPACW
9056*r5900:
9057{
9058 unsigned32 instruction = instruction_0;
055ee297 9059 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9060 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9061 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9062 signed_word rt_reg = GPR[RT];
9063 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9064 {
9065 GPR_UW(destreg,0) = RT_UW(0);
9066 GPR_UW(destreg,1) = RT_UW(2);
9067 GPR_UW(destreg,2) = RS_UW(0);
9068 GPR_UW(destreg,3) = RS_UW(2);
9069 }
9070}
9071
9072// end-sanitize-r5900
9073// start-sanitize-r5900
9074
907501110000000,5.RT,5.RD,11011001001:MMI2:32::PREVH
9076*r5900:
9077{
9078 unsigned32 instruction = instruction_0;
055ee297 9079 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 9080 signed_word rt_reg = GPR[RT];
9081 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9082 {
9083 GPR_UH(destreg,0) = RT_UH(3);
9084 GPR_UH(destreg,1) = RT_UH(2);
9085 GPR_UH(destreg,2) = RT_UH(1);
9086 GPR_UH(destreg,3) = RT_UH(0);
9087 GPR_UH(destreg,4) = RT_UH(7);
9088 GPR_UH(destreg,5) = RT_UH(6);
9089 GPR_UH(destreg,6) = RT_UH(5);
9090 GPR_UH(destreg,7) = RT_UH(4);
9091 }
9092}
9093
9094// end-sanitize-r5900
9095// start-sanitize-r5900
9096
909701110000000,5.RT,5.RD,11111001001:MMI2:32::PROT3W
9098*r5900:
9099{
9100 unsigned32 instruction = instruction_0;
055ee297 9101 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 9102 signed_word rt_reg = GPR[RT];
9103 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9104 {
9105 GPR_UW(destreg,0) = RT_UW(0);
9106 GPR_UW(destreg,1) = RT_UW(3);
9107 GPR_UW(destreg,2) = RT_UW(1);
9108 GPR_UW(destreg,3) = RT_UW(2);
9109 }
9110}
9111
9112// end-sanitize-r5900
9113// start-sanitize-r5900
9114
055ee297 911501110000000,5.RT,5.RD,5.SHIFT,110100:MMINORM:32::PSLLH
f2b30012
AC		 9116*r5900:
9117{
9118 unsigned32 instruction = instruction_0;
055ee297
AC		 9119 int op1 = ((instruction >> 6) & 0x0000001F);
9120 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 9121 signed_word rt_reg = GPR[RT];
9122 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9123 {
9124 int shift_by = op1 & (16-1);
9125 int i;
9126 for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
9127 GPR_UH(destreg,i) = (RT_UH(i) << shift_by);
9128 }
9129}
9130
9131// end-sanitize-r5900
9132// start-sanitize-r5900
9133
9134011100,5.RS,5.RT,5.RD,00010001001:MMI2:32::PSLLVW
9135*r5900:
9136{
9137 unsigned32 instruction = instruction_0;
055ee297 9138 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9139 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9140 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9141 signed_word rt_reg = GPR[RT];
9142 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9143 {
9144 int s0 = (RS_UB(0) & 0x1F);
9145 int s1 = (RS_UB(8) & 0x1F);
9146 signed32 temp0 = RT_UW(0) << s0;
9147 signed32 temp1 = RT_UW(2) << s1;
9148 GPR_SD(destreg,0) = (signed64)temp0;
9149 GPR_SD(destreg,1) = (signed64)temp1;
9150 }
9151}
9152
9153// end-sanitize-r5900
9154// start-sanitize-r5900
9155
055ee297 915601110000000,5.RT,5.RD,5.SHIFT,111100:MMINORM:32::PSLLW
f2b30012
AC		 9157*r5900:
9158{
9159 unsigned32 instruction = instruction_0;
055ee297
AC		 9160 int op1 = ((instruction >> 6) & 0x0000001F);
9161 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 9162 signed_word rt_reg = GPR[RT];
9163 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9164 {
9165 int shift_by = op1 & (32-1);
9166 int i;
9167 for(i=0;i<WORDS_IN_MMI_REGS;i++)
9168 GPR_UW(destreg,i) = (RT_UW(i) << shift_by);
9169 }
9170}
9171
9172// end-sanitize-r5900
9173// start-sanitize-r5900
9174
055ee297 917501110000000,5.RT,5.RD,5.SHIFT,110111:MMINORM:32::PSRAH
f2b30012
AC		 9176*r5900:
9177{
9178 unsigned32 instruction = instruction_0;
055ee297
AC		 9179 int op1 = ((instruction >> 6) & 0x0000001F);
9180 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 9181 signed_word rt_reg = GPR[RT];
9182 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9183 {
9184 int shift_by = op1 & (16-1);
9185 int i;
9186 for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
9187 GPR_SH(destreg,i) = SIGNEXTEND( (RT_SH(i) >> shift_by), (16-shift_by) );
9188 }
9189}
9190
9191// end-sanitize-r5900
9192// start-sanitize-r5900
9193
9194011100,5.RS,5.RT,5.RD,00011101001:MMI3:32::PSRAVW
9195*r5900:
9196{
9197 unsigned32 instruction = instruction_0;
055ee297 9198 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9199 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9200 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9201 signed_word rt_reg = GPR[RT];
9202 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9203 {
9204 GPR_SD(destreg,0) = SIGNEXTEND( (RT_SW (0) >> (RS_UB(0) & 0x1F)), 32-(RS_UB(0) & 0x1F) );
9205 GPR_SD(destreg,1) = SIGNEXTEND( (RT_SW (2) >> (RS_UB(8) & 0x1F)), 32-(RS_UB(8) & 0x1F) );
9206 }
9207}
9208
9209// end-sanitize-r5900
9210// start-sanitize-r5900
9211
055ee297 921201110000000,5.RT,5.RD,5.SHIFT,111111:MMINORM:32::PSRAW
f2b30012
AC		 9213*r5900:
9214{
9215 unsigned32 instruction = instruction_0;
055ee297
AC		 9216 int op1 = ((instruction >> 6) & 0x0000001F);
9217 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 9218 signed_word rt_reg = GPR[RT];
9219 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9220 {
9221 int shift_by = op1 & (32-1);
9222 int i;
9223 for(i=0;i<WORDS_IN_MMI_REGS;i++)
9224 GPR_SW(destreg,i) = SIGNEXTEND( (RT_SW(i) >> shift_by), (32-shift_by) );
9225 }
9226}
9227
9228// end-sanitize-r5900
9229// start-sanitize-r5900
9230
055ee297 923101110000000,5.RT,5.RD,5.SHIFT,110110:MMINORM:32::PSRLH
f2b30012
AC		 9232*r5900:
9233{
9234 unsigned32 instruction = instruction_0;
055ee297
AC		 9235 int op1 = ((instruction >> 6) & 0x0000001F);
9236 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 9237 signed_word rt_reg = GPR[RT];
9238 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9239 {
9240 int shift_by = op1 & (16-1);
9241 int i;
9242 for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
9243 GPR_UH(destreg,i) = (RT_UH(i) >> shift_by);
9244 }
9245}
9246
9247// end-sanitize-r5900
9248// start-sanitize-r5900
9249
9250011100,5.RS,5.RT,5.RD,00011001001:MMI2:32::PSRLVW
9251*r5900:
9252{
9253 unsigned32 instruction = instruction_0;
055ee297 9254 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9255 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9256 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9257 signed_word rt_reg = GPR[RT];
9258 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9259 {
9260 GPR_UD(destreg,0) = SIGNEXTEND ( RT_UW(0) >> (RS_UB(0) & 0x1F), 31);
9261 GPR_UD(destreg,1) = SIGNEXTEND ( RT_UW(2) >> (RS_UB(8) & 0x1F), 31);
9262 }
9263}
9264
9265// end-sanitize-r5900
9266// start-sanitize-r5900
9267
055ee297 926801110000000,5.RT,5.RD,5.SHIFT,111110:MMINORM:32::PSRLW
f2b30012
AC		 9269*r5900:
9270{
9271 unsigned32 instruction = instruction_0;
055ee297
AC		 9272 int op1 = ((instruction >> 6) & 0x0000001F);
9273 int destreg = ((instruction >> 11) & 0x0000001F);
085c1cb9
AC		 9274 signed_word rt_reg = GPR[RT];
9275 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9276 {
9277 int shift_by = op1 & (32-1);
9278 int i;
9279 for(i=0;i<WORDS_IN_MMI_REGS;i++)
9280 GPR_UW(destreg,i) = (RT_UW(i) >> shift_by);
9281 }
9282}
9283
9284// end-sanitize-r5900
9285// start-sanitize-r5900
9286
9287011100,5.RS,5.RT,5.RD,01001001000:MMI0:32::PSUBB
9288*r5900:
9289{
9290 unsigned32 instruction = instruction_0;
055ee297 9291 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9292 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9293 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9294 signed_word rt_reg = GPR[RT];
9295 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9296 {
9297 int i;
9298 for (i=0; i < BYTES_IN_MMI_REGS; i++)
9299 {
9300 int s = RS_SB(i);
9301 int t = RT_SB(i);
9302 int r = s - t;
9303 GPR_SB(destreg,i) = r;
9304 }
9305 }
9306}
9307
9308// end-sanitize-r5900
9309// start-sanitize-r5900
9310
9311011100,5.RS,5.RT,5.RD,00101001000:MMI0:32::PSUBH
9312*r5900:
9313{
9314 unsigned32 instruction = instruction_0;
055ee297 9315 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9316 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9317 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9318 signed_word rt_reg = GPR[RT];
9319 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9320 {
9321 int i;
9322 for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
9323 {
9324 int s = RS_SH(i);
9325 int t = RT_SH(i);
9326 int r = s - t;
9327 GPR_SH(destreg,i) = r;
9328 }
9329 }
9330}
9331
9332// end-sanitize-r5900
9333// start-sanitize-r5900
9334
9335011100,5.RS,5.RT,5.RD,11001001000:MMI0:32::PSUBSB
9336*r5900:
9337{
9338 unsigned32 instruction = instruction_0;
055ee297 9339 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9340 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9341 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9342 signed_word rt_reg = GPR[RT];
9343 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9344 {
9345 int i;
9346 for (i=0; i < BYTES_IN_MMI_REGS; i++)
9347 {
9348 int s = RS_SB(i);
9349 int t = RT_SB(i);
9350 int r = s - t;
9351 if (r > 127)
9352 GPR_SB(destreg,i) = 127;
9353 else if (r < -128)
9354 GPR_SB(destreg,i) = -128;
9355 else
9356 GPR_SB(destreg,i) = r;
9357 }
9358 }
9359}
9360
9361// end-sanitize-r5900
9362// start-sanitize-r5900
9363
9364011100,5.RS,5.RT,5.RD,10101001000:MMI0:32::PSUBSH
9365*r5900:
9366{
9367 unsigned32 instruction = instruction_0;
055ee297 9368 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9369 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9370 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9371 signed_word rt_reg = GPR[RT];
9372 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9373 {
9374 int i;
9375 for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
9376 {
9377 int s = RS_SH(i);
9378 int t = RT_SH(i);
9379 int r = s - t;
9380 if (r > 32767)
9381 GPR_SH(destreg,i) = 32767;
9382 else if (r < -32768)
9383 GPR_SH(destreg,i) = -32768;
9384 else
9385 GPR_SH(destreg,i) = r;
9386 }
9387 }
9388}
9389
9390// end-sanitize-r5900
9391// start-sanitize-r5900
9392
9393011100,5.RS,5.RT,5.RD,10001001000:MMI0:32::PSUBSW
9394*r5900:
9395{
9396 unsigned32 instruction = instruction_0;
055ee297 9397 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9398 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9399 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9400 signed_word rt_reg = GPR[RT];
9401 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9402 {
9403 int i;
9404 for (i=0; i < WORDS_IN_MMI_REGS; i++)
9405 {
9406 signed64 s = RS_SW(i);
9407 signed64 t = RT_SW(i);
9408 signed64 r = s - t;
9409 if (r > (int)0x7FFFFFFF)
9410 GPR_SW(destreg,i) = (int)0x7FFFFFFF;
9411 else if (r < (int)0x80000000)
9412 GPR_SW(destreg,i) = (int)0x80000000;
9413 else
9414 GPR_SW(destreg,i) = r;
9415 }
9416 }
9417}
9418
9419// end-sanitize-r5900
9420// start-sanitize-r5900
9421
9422011100,5.RS,5.RT,5.RD,11001101000:MMI1:32::PSUBUB
9423*r5900:
9424{
9425 unsigned32 instruction = instruction_0;
055ee297 9426 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9427 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9428 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9429 signed_word rt_reg = GPR[RT];
9430 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9431 {
9432 int i;
9433 for (i=0; i < BYTES_IN_MMI_REGS; i++)
9434 {
9435 unsigned int s = RS_UB(i);
9436 unsigned int t = RT_UB(i);
9437 unsigned int r = s - t;
9438 if (r > 0xFF)
9439 GPR_UB(destreg,i) = 0;
9440 else
9441 GPR_UB(destreg,i) = r;
9442 }
9443 }
9444}
9445
9446// end-sanitize-r5900
9447// start-sanitize-r5900
9448
9449011100,5.RS,5.RT,5.RD,10101101000:MMI1:32::PSUBUH
9450*r5900:
9451{
9452 unsigned32 instruction = instruction_0;
055ee297 9453 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9454 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9455 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9456 signed_word rt_reg = GPR[RT];
9457 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9458 {
9459 int i;
9460 for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
9461 {
9462 unsigned int s = RS_UH(i);
9463 unsigned int t = RT_UH(i);
9464 unsigned int r = s - t;
9465 if (r > 0xFFFF)
9466 GPR_UH(destreg,i) = 0;
9467 else
9468 GPR_UH(destreg,i) = r;
9469 }
9470 }
9471}
9472
9473// end-sanitize-r5900
9474// start-sanitize-r5900
9475
9476011100,5.RS,5.RT,5.RD,10001101000:MMI1:32::PSUBUW
9477*r5900:
9478{
9479 unsigned32 instruction = instruction_0;
055ee297 9480 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9481 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9482 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9483 signed_word rt_reg = GPR[RT];
9484 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9485 {
9486 int i;
9487 for (i=0; i < WORDS_IN_MMI_REGS; i++)
9488 {
9489 unsigned64 s = RS_UW(i);
9490 unsigned64 t = RT_UW(i);
9491 unsigned64 r = s - t;
9492 if (r > 0xFFFFFFFF)
9493 GPR_UW(destreg,i) = 0;
9494 else
9495 GPR_UW(destreg,i) = r;
9496 }
9497 }
9498}
9499
9500// end-sanitize-r5900
9501// start-sanitize-r5900
9502
9503011100,5.RS,5.RT,5.RD,00001001000:MMI0:32::PSUBW
9504*r5900:
9505{
9506 unsigned32 instruction = instruction_0;
055ee297 9507 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9508 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9509 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9510 signed_word rt_reg = GPR[RT];
9511 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9512 {
9513 int i;
9514 for (i=0; i < WORDS_IN_MMI_REGS; i++)
9515 {
9516 signed64 s = RS_SW(i);
9517 signed64 t = RT_SW(i);
9518 signed64 r = s - t;
9519 GPR_SW(destreg,i) = r;
9520 }
9521 }
9522}
9523
9524// end-sanitize-r5900
9525// start-sanitize-r5900
9526
9527011100,5.RS,5.RT,5.RD,10011001001:MMI2:32::PXOR
9528*r5900:
9529{
9530 unsigned32 instruction = instruction_0;
055ee297 9531 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9532 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9533 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9534 signed_word rt_reg = GPR[RT];
9535 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9536 {
9537 int i;
9538 for(i=0;i<WORDS_IN_MMI_REGS;i++)
9539 GPR_UW(destreg,i) = (RS_UW(i) ^ RT_UW(i));
9540 }
9541}
9542
9543// end-sanitize-r5900
9544// start-sanitize-r5900
9545
9546011100,5.RS,5.RT,5.RD,11011101000:MMI1:32::QFSRV
9547*r5900:
9548{
9549 unsigned32 instruction = instruction_0;
055ee297 9550 int destreg = ((instruction >> 11) & 0x0000001F);
055ee297
AC		 9551 signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9552 signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9553 signed_word rt_reg = GPR[RT];
9554 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9555 {
9556 int bytes = (SA / 8) % 16;
9557 if (SA % 8)
9558 SignalException(ReservedInstruction,instruction);
9559 else
9560 {
9561 int i;
9562 for(i=0;i<(16-bytes);i++)
9563 GPR_SB(destreg,i) = RT_SB(bytes+i);
9564 for(;i<16;i++)
9565 GPR_SB(destreg,i) = RS_SB(i-(16-bytes));
9566 }
9567 }
9568}
9569
9570// end-sanitize-r5900
9571// start-sanitize-r5900
9572
9573011111,5.RS,5.RT,16.OFFSET:NORMAL:128::SQ
9574*r5900:
9575{
9576 unsigned32 instruction = instruction_0;
055ee297
AC		 9577 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
9578 signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
9579 signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
9580 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
085c1cb9
AC		 9581 signed_word rt_reg = GPR[RT];
9582 signed_word rt_reg1 = GPR1[RT];
f2b30012
AC		 9583 {
9584 unsigned64 vaddr = ((unsigned64)op1 + offset);
9585 unsigned64 paddr;
9586 int uncached;
9587 if ((vaddr & 15) != 0)
055ee297 9588 SignalExceptionAddressStore();
f2b30012
AC		 9589 else
9590 {
9591 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
9592 {
9593 unsigned64 memval = 0;
9594 unsigned64 memval1 = 0;
055ee297
AC		 9595 memval = rsigned_word;
9596 memval1 = rsigned_word1;
f2b30012
AC		 9597 {
9598 StoreMemory(uncached,AccessLength_QUADWORD,memval,memval1,paddr,vaddr,isREAL);
9599 }
9600 }
9601 }
9602 }
9603}
9604
9605// end-sanitize-r5900
9606\f
9607// start-sanitize-cygnus-never
9608
49a6eed5
AC		 9609// // FIXME FIXME FIXME What is this instruction?
9610// 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
9611// *mipsI:
9612// *mipsII:
9613// *mipsIII:
9614// *mipsIV:
9615// // start-sanitize-r5900
9616// *r5900:
9617// // end-sanitize-r5900
9618// *r3900:
9619// // start-sanitize-tx19
9620// *tx19:
9621// // end-sanitize-tx19
9622// {
9623// unsigned32 instruction = instruction_0;
055ee297
AC		 9624// signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
9625// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
9626// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
49a6eed5
AC		 9627// {
9628// if (CoProcPresent(3))
9629// SignalException(CoProcessorUnusable);
9630// else
9631// SignalException(ReservedInstruction,instruction);
9632// }
9633// }
9634
9635// end-sanitize-cygnus-never
9636// start-sanitize-cygnus-never
9637
9638// // FIXME FIXME FIXME What is this?
9639// 11100,******,00001:RR:16::SDBBP
9640// *mips16:
9641// {
9642// unsigned32 instruction = instruction_0;
9643// if (have_extendval)
9644// SignalException (ReservedInstruction, instruction);
9645// {
9646// SignalException(DebugBreakPoint,instruction);
9647// }
9648// }
f2b30012
AC		 9649
9650// end-sanitize-cygnus-never
9651// start-sanitize-cygnus-never
9652
49a6eed5
AC		 9653// // FIXME FIXME FIXME What is this?
9654// 000000,********************,001110:SPECIAL:32::SDBBP
9655// *r3900:
9656// {
9657// unsigned32 instruction = instruction_0;
9658// {
9659// SignalException(DebugBreakPoint,instruction);
9660// }
9661// }
f2b30012
AC		 9662
9663// end-sanitize-cygnus-never
9664// start-sanitize-cygnus-never
9665
49a6eed5
AC		 9666// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
9667// // isn't yet reconized by this simulator.
9668// 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
9669// *vr4100:
9670// {
9671// unsigned32 instruction = instruction_0;
055ee297
AC		 9672// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
9673// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
49a6eed5
AC		 9674// {
9675// CHECKHILO("Multiply-Add");
9676// {
9677// unsigned64 temp = (op1 * op2);
9678// temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
9679// LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
9680// HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
9681// }
9682// }
9683// }
f2b30012
AC		 9684
9685// end-sanitize-cygnus-never
49a6eed5
AC		 9686// start-sanitize-cygnus-never
9687
9688// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
9689// // isn't yet reconized by this simulator.
9690// 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
9691// *vr4100:
9692// {
9693// unsigned32 instruction = instruction_0;
055ee297
AC		 9694// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
9695// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
49a6eed5
AC		 9696// {
9697// CHECKHILO("Multiply-Add");
9698// {
9699// unsigned64 temp = (op1 * op2);
9700// LO = LO + temp;
9701// }
9702// }
9703// }
9704
9705// start-sanitize-cygnus-never
GDB Binutils - Deliverables
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