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* tuiSourceWin.c (tuiSetIsExecPointAt): Redraw the previous and
[deliverable/binutils-gdb.git] / sim / mips / mips.igen
CommitLineData
c906108c
SS		 1// -*- C -*-
2//
c906108c
SS		 3// <insn> ::=
4// <insn-word> { "+" <insn-word> }
5// ":" <format-name>
6// ":" <filter-flags>
7// ":" <options>
8// ":" <name>
9// <nl>
10// { <insn-model> }
11// { <insn-mnemonic> }
12// <code-block>
13//
14
15
16// IGEN config - mips16
17// :option:16::insn-bit-size:16
18// :option:16::hi-bit-nr:15
19:option:16::insn-specifying-widths:true
20:option:16::gen-delayed-branch:false
21
22// IGEN config - mips32/64..
23// :option:32::insn-bit-size:32
24// :option:32::hi-bit-nr:31
25:option:32::insn-specifying-widths:true
26:option:32::gen-delayed-branch:false
27
28
29// Generate separate simulators for each target
30// :option:::multi-sim:true
31
32
074e9cb8 33// Models known by this simulator are defined below.
c5d00cc7
CD		 34//
35// When placing models in the instruction descriptions, please place
36// them one per line, in the order given here.
074e9cb8
CD		 37
38// MIPS ISAs:
39//
40// Instructions and related functions for these models are included in
41// this file.
c906108c
SS		 42:model:::mipsI:mips3000:
43:model:::mipsII:mips6000:
44:model:::mipsIII:mips4000:
45:model:::mipsIV:mips8000:
603a98e7 46:model:::mipsV:mipsisaV:
1e799e28
CD		 47:model:::mips32:mipsisa32:
48:model:::mips64:mipsisa64:
074e9cb8
CD		 49
50// Vendor ISAs:
51//
52// Standard MIPS ISA instructions used for these models are listed here,
53// as are functions needed by those standard instructions. Instructions
54// which are model-dependent and which are not in the standard MIPS ISAs
55// (or which pre-date or use different encodings than the standard
56// instructions) are (for the most part) in separate .igen files.
57:model:::vr4100:mips4100: // vr.igen
c906108c 58:model:::vr5000:mips5000:
074e9cb8 59:model:::r3900:mips3900: // tx.igen
c906108c 60
074e9cb8
CD		 61// MIPS Application Specific Extensions (ASEs)
62//
63// Instructions for the ASEs are in separate .igen files.
f4f1b9f1 64// ASEs add instructions on to a base ISA.
074e9cb8 65:model:::mips16:mips16: // m16.igen (and m16.dc)
e7e81181 66:model:::mips3d:mips3d: // mips3d.igen
f4f1b9f1 67:model:::mdmx:mdmx: // mdmx.igen
c906108c 68
7cbea089
CD		 69// Vendor Extensions
70//
71// Instructions specific to these extensions are in separate .igen files.
72// Extensions add instructions on to a base ISA.
73:model:::sb1:sb1: // sb1.igen
74
c906108c
SS		 75
76// Pseudo instructions known by IGEN
77:internal::::illegal:
78{
79 SignalException (ReservedInstruction, 0);
80}
81
82
83// Pseudo instructions known by interp.c
84// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
85000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
86"rsvd <OP>"
87{
88 SignalException (ReservedInstruction, instruction_0);
89}
90
91
92
93// Helper:
94//
95// Simulate a 32 bit delayslot instruction
96//
97
98:function:::address_word:delayslot32:address_word target
99{
100 instruction_word delay_insn;
101 sim_events_slip (SD, 1);
102 DSPC = CIA;
103 CIA = CIA + 4; /* NOTE not mips16 */
104 STATE |= simDELAYSLOT;
105 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
d4f3574e 106 ENGINE_ISSUE_PREFIX_HOOK();
c906108c
SS		 107 idecode_issue (CPU_, delay_insn, (CIA));
108 STATE &= ~simDELAYSLOT;
109 return target;
110}
111
112:function:::address_word:nullify_next_insn32:
113{
114 sim_events_slip (SD, 1);
115 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
116 return CIA + 8;
117}
118
09297648
CD		 119
120// Helper:
121//
122// Calculate an effective address given a base and an offset.
123//
124
125:function:::address_word:loadstore_ea:address_word base, address_word offset
126*mipsI:
127*mipsII:
128*mipsIII:
129*mipsIV:
130*mipsV:
1e799e28 131*mips32:
09297648
CD		 132*vr4100:
133*vr5000:
134*r3900:
135{
136 return base + offset;
137}
138
1e799e28
CD		 139:function:::address_word:loadstore_ea:address_word base, address_word offset
140*mips64:
141{
142#if 0 /* XXX FIXME: enable this only after some additional testing. */
143 /* If in user mode and UX is not set, use 32-bit compatibility effective
144 address computations as defined in the MIPS64 Architecture for
145 Programmers Volume III, Revision 0.95, section 4.9. */
146 if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
147 == (ksu_user << status_KSU_shift))
148 return (address_word)((signed32)base + (signed32)offset);
149#endif
150 return base + offset;
151}
152
09297648 153
402586aa
CD		 154// Helper:
155//
156// Check that a 32-bit register value is properly sign-extended.
157// (See NotWordValue in ISA spec.)
158//
159
160:function:::int:not_word_value:unsigned_word value
161*mipsI:
162*mipsII:
163*mipsIII:
164*mipsIV:
165*mipsV:
166*vr4100:
167*vr5000:
168*r3900:
169{
170 /* For historical simulator compatibility (until documentation is
171 found that makes these operations unpredictable on some of these
172 architectures), this check never returns true. */
173 return 0;
174}
175
176:function:::int:not_word_value:unsigned_word value
177*mips32:
178{
179 /* On MIPS32, since registers are 32-bits, there's no check to be done. */
180 return 0;
181}
182
183:function:::int:not_word_value:unsigned_word value
184*mips64:
185{
186 return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
187}
188
189
190// Helper:
191//
192// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
193// theoretically portable code which invokes non-portable behaviour from
194// running with no indication of the portability issue.
195// (See definition of UNPREDICTABLE in ISA spec.)
196//
197
198:function:::void:unpredictable:
199*mipsI:
200*mipsII:
201*mipsIII:
202*mipsIV:
203*mipsV:
204*vr4100:
205*vr5000:
206*r3900:
207{
208}
209
210:function:::void:unpredictable:
211*mips32:
212*mips64:
213{
214 unpredictable_action (CPU, CIA);
215}
216
217
c906108c 218// Helper:
4a0bd876 219//
c906108c
SS		 220// Check that an access to a HI/LO register meets timing requirements
221//
222// The following requirements exist:
223//
224// - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
225// - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
226// - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
227// corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
228//
229
230:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
231{
232 if (history->mf.timestamp + 3 > time)
233 {
234 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
235 itable[MY_INDEX].name,
236 new, (long) CIA,
4a0bd876 237 (long) history->mf.cia);
c906108c
SS		 238 return 0;
239 }
240 return 1;
241}
242
243:function:::int:check_mt_hilo:hilo_history *history
c5d00cc7
CD		 244*mipsI:
245*mipsII:
246*mipsIII:
247*mipsIV:
603a98e7 248*mipsV:
c906108c
SS		 249*vr4100:
250*vr5000:
251{
252 signed64 time = sim_events_time (SD);
253 int ok = check_mf_cycles (SD_, history, time, "MT");
254 history->mt.timestamp = time;
255 history->mt.cia = CIA;
256 return ok;
257}
258
259:function:::int:check_mt_hilo:hilo_history *history
1e799e28
CD		 260*mips32:
261*mips64:
c906108c
SS		 262*r3900:
263{
264 signed64 time = sim_events_time (SD);
265 history->mt.timestamp = time;
266 history->mt.cia = CIA;
267 return 1;
268}
269
270
271:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
c5d00cc7
CD		 272*mipsI:
273*mipsII:
274*mipsIII:
275*mipsIV:
603a98e7 276*mipsV:
1e799e28
CD		 277*mips32:
278*mips64:
c906108c
SS		 279*vr4100:
280*vr5000:
281*r3900:
282{
283 signed64 time = sim_events_time (SD);
284 int ok = 1;
285 if (peer != NULL
286 && peer->mt.timestamp > history->op.timestamp
287 && history->mt.timestamp < history->op.timestamp
288 && ! (history->mf.timestamp > history->op.timestamp
289 && history->mf.timestamp < peer->mt.timestamp)
290 && ! (peer->mf.timestamp > history->op.timestamp
291 && peer->mf.timestamp < peer->mt.timestamp))
292 {
293 /* The peer has been written to since the last OP yet we have
294 not */
295 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
296 itable[MY_INDEX].name,
297 (long) CIA,
298 (long) history->op.cia,
4a0bd876 299 (long) peer->mt.cia);
c906108c
SS		 300 ok = 0;
301 }
302 history->mf.timestamp = time;
303 history->mf.cia = CIA;
304 return ok;
305}
306
307
308
309:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
c5d00cc7
CD		 310*mipsI:
311*mipsII:
312*mipsIII:
313*mipsIV:
603a98e7 314*mipsV:
c906108c
SS		 315*vr4100:
316*vr5000:
317{
318 signed64 time = sim_events_time (SD);
319 int ok = (check_mf_cycles (SD_, hi, time, "OP")
320 && check_mf_cycles (SD_, lo, time, "OP"));
321 hi->op.timestamp = time;
322 lo->op.timestamp = time;
323 hi->op.cia = CIA;
324 lo->op.cia = CIA;
325 return ok;
326}
327
328// The r3900 mult and multu insns _can_ be exectuted immediatly after
329// a mf{hi,lo}
330:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
1e799e28
CD		 331*mips32:
332*mips64:
c906108c
SS		 333*r3900:
334{
335 /* FIXME: could record the fact that a stall occured if we want */
336 signed64 time = sim_events_time (SD);
337 hi->op.timestamp = time;
338 lo->op.timestamp = time;
339 hi->op.cia = CIA;
340 lo->op.cia = CIA;
341 return 1;
342}
343
344
345:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
c5d00cc7
CD		 346*mipsI:
347*mipsII:
348*mipsIII:
349*mipsIV:
603a98e7 350*mipsV:
1e799e28
CD		 351*mips32:
352*mips64:
c906108c
SS		 353*vr4100:
354*vr5000:
355*r3900:
356{
357 signed64 time = sim_events_time (SD);
358 int ok = (check_mf_cycles (SD_, hi, time, "OP")
359 && check_mf_cycles (SD_, lo, time, "OP"));
360 hi->op.timestamp = time;
361 lo->op.timestamp = time;
362 hi->op.cia = CIA;
363 lo->op.cia = CIA;
364 return ok;
365}
366
367
ca971540 368// Helper:
4a0bd876 369//
ca971540 370// Check that the 64-bit instruction can currently be used, and signal
b5040d49 371// a ReservedInstruction exception if not.
ca971540
CD		 372//
373
374:function:::void:check_u64:instruction_word insn
375*mipsIII:
376*mipsIV:
377*mipsV:
378*vr4100:
379*vr5000:
380{
ca971540
CD		 381 // The check should be similar to mips64 for any with PX/UX bit equivalents.
382}
c906108c 383
1e799e28
CD		 384:function:::void:check_u64:instruction_word insn
385*mips64:
386{
387#if 0 /* XXX FIXME: enable this only after some additional testing. */
388 if (UserMode && (SR & (status_UX|status_PX)) == 0)
389 SignalException (ReservedInstruction, insn);
390#endif
391}
392
c906108c
SS		 393
394
395//
074e9cb8 396// MIPS Architecture:
c906108c 397//
1e799e28 398// CPU Instruction Set (mipsI - mipsV, mips32, mips64)
c906108c
SS		 399//
400
401
402
403000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
404"add r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 405*mipsI:
406*mipsII:
407*mipsIII:
408*mipsIV:
603a98e7 409*mipsV:
1e799e28
CD		 410*mips32:
411*mips64:
c906108c
SS		 412*vr4100:
413*vr5000:
414*r3900:
415{
402586aa
CD		 416 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
417 Unpredictable ();
c906108c
SS		 418 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
419 {
420 ALU32_BEGIN (GPR[RS]);
421 ALU32_ADD (GPR[RT]);
9805e229 422 ALU32_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 423 }
424 TRACE_ALU_RESULT (GPR[RD]);
425}
426
427
428
429001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
20ae0098 430"addi r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 431*mipsI:
432*mipsII:
433*mipsIII:
434*mipsIV:
603a98e7 435*mipsV:
1e799e28
CD		 436*mips32:
437*mips64:
c906108c
SS		 438*vr4100:
439*vr5000:
440*r3900:
441{
402586aa
CD		 442 if (NotWordValue (GPR[RS]))
443 Unpredictable ();
c906108c
SS		 444 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
445 {
446 ALU32_BEGIN (GPR[RS]);
447 ALU32_ADD (EXTEND16 (IMMEDIATE));
9805e229 448 ALU32_END (GPR[RT]); /* This checks for overflow. */
c906108c
SS		 449 }
450 TRACE_ALU_RESULT (GPR[RT]);
451}
452
453
454
455:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
456{
402586aa
CD		 457 if (NotWordValue (GPR[rs]))
458 Unpredictable ();
c906108c
SS		 459 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
460 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
461 TRACE_ALU_RESULT (GPR[rt]);
462}
463
464001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
465"addiu r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 466*mipsI:
467*mipsII:
468*mipsIII:
469*mipsIV:
603a98e7 470*mipsV:
1e799e28
CD		 471*mips32:
472*mips64:
c906108c
SS		 473*vr4100:
474*vr5000:
475*r3900:
476{
477 do_addiu (SD_, RS, RT, IMMEDIATE);
478}
479
480
481
482:function:::void:do_addu:int rs, int rt, int rd
483{
402586aa
CD		 484 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
485 Unpredictable ();
c906108c
SS		 486 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
487 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
488 TRACE_ALU_RESULT (GPR[rd]);
489}
490
491000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
492"addu r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 493*mipsI:
494*mipsII:
495*mipsIII:
496*mipsIV:
603a98e7 497*mipsV:
1e799e28
CD		 498*mips32:
499*mips64:
c906108c
SS		 500*vr4100:
501*vr5000:
502*r3900:
503{
504 do_addu (SD_, RS, RT, RD);
505}
506
507
508
509:function:::void:do_and:int rs, int rt, int rd
510{
511 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
512 GPR[rd] = GPR[rs] & GPR[rt];
513 TRACE_ALU_RESULT (GPR[rd]);
514}
515
516000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
517"and r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 518*mipsI:
519*mipsII:
520*mipsIII:
521*mipsIV:
603a98e7 522*mipsV:
1e799e28
CD		 523*mips32:
524*mips64:
c906108c
SS		 525*vr4100:
526*vr5000:
527*r3900:
528{
529 do_and (SD_, RS, RT, RD);
530}
531
532
533
534001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
82f728db 535"andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
c5d00cc7
CD		 536*mipsI:
537*mipsII:
538*mipsIII:
539*mipsIV:
603a98e7 540*mipsV:
1e799e28
CD		 541*mips32:
542*mips64:
c906108c
SS		 543*vr4100:
544*vr5000:
545*r3900:
546{
547 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
548 GPR[RT] = GPR[RS] & IMMEDIATE;
549 TRACE_ALU_RESULT (GPR[RT]);
550}
551
552
553
554000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
555"beq r<RS>, r<RT>, <OFFSET>"
c5d00cc7
CD		 556*mipsI:
557*mipsII:
558*mipsIII:
559*mipsIV:
603a98e7 560*mipsV:
1e799e28
CD		 561*mips32:
562*mips64:
c906108c
SS		 563*vr4100:
564*vr5000:
565*r3900:
566{
567 address_word offset = EXTEND16 (OFFSET) << 2;
568 check_branch_bug ();
569 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
570 {
571 mark_branch_bug (NIA+offset);
572 DELAY_SLOT (NIA + offset);
573 }
574}
575
576
577
578010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
579"beql r<RS>, r<RT>, <OFFSET>"
580*mipsII:
581*mipsIII:
582*mipsIV:
603a98e7 583*mipsV:
1e799e28
CD		 584*mips32:
585*mips64:
c906108c
SS		 586*vr4100:
587*vr5000:
588*r3900:
589{
590 address_word offset = EXTEND16 (OFFSET) << 2;
591 check_branch_bug ();
592 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
593 {
594 mark_branch_bug (NIA+offset);
595 DELAY_SLOT (NIA + offset);
596 }
597 else
598 NULLIFY_NEXT_INSTRUCTION ();
599}
600
601
602
603000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
604"bgez r<RS>, <OFFSET>"
c5d00cc7
CD		 605*mipsI:
606*mipsII:
607*mipsIII:
608*mipsIV:
603a98e7 609*mipsV:
1e799e28
CD		 610*mips32:
611*mips64:
c906108c
SS		 612*vr4100:
613*vr5000:
614*r3900:
615{
616 address_word offset = EXTEND16 (OFFSET) << 2;
617 check_branch_bug ();
618 if ((signed_word) GPR[RS] >= 0)
619 {
620 mark_branch_bug (NIA+offset);
621 DELAY_SLOT (NIA + offset);
622 }
623}
624
625
626
627000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
628"bgezal r<RS>, <OFFSET>"
c5d00cc7
CD		 629*mipsI:
630*mipsII:
631*mipsIII:
632*mipsIV:
603a98e7 633*mipsV:
1e799e28
CD		 634*mips32:
635*mips64:
c906108c
SS		 636*vr4100:
637*vr5000:
638*r3900:
639{
640 address_word offset = EXTEND16 (OFFSET) << 2;
641 check_branch_bug ();
402586aa
CD		 642 if (RS == 31)
643 Unpredictable ();
c906108c
SS		 644 RA = (CIA + 8);
645 if ((signed_word) GPR[RS] >= 0)
646 {
647 mark_branch_bug (NIA+offset);
648 DELAY_SLOT (NIA + offset);
649 }
650}
651
652
653
654000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
655"bgezall r<RS>, <OFFSET>"
656*mipsII:
657*mipsIII:
658*mipsIV:
603a98e7 659*mipsV:
1e799e28
CD		 660*mips32:
661*mips64:
c906108c
SS		 662*vr4100:
663*vr5000:
664*r3900:
665{
666 address_word offset = EXTEND16 (OFFSET) << 2;
667 check_branch_bug ();
402586aa
CD		 668 if (RS == 31)
669 Unpredictable ();
c906108c
SS		 670 RA = (CIA + 8);
671 /* NOTE: The branch occurs AFTER the next instruction has been
672 executed */
673 if ((signed_word) GPR[RS] >= 0)
674 {
675 mark_branch_bug (NIA+offset);
676 DELAY_SLOT (NIA + offset);
677 }
678 else
679 NULLIFY_NEXT_INSTRUCTION ();
680}
681
682
683
684000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
685"bgezl r<RS>, <OFFSET>"
686*mipsII:
687*mipsIII:
688*mipsIV:
603a98e7 689*mipsV:
1e799e28
CD		 690*mips32:
691*mips64:
c906108c
SS		 692*vr4100:
693*vr5000:
694*r3900:
695{
696 address_word offset = EXTEND16 (OFFSET) << 2;
697 check_branch_bug ();
698 if ((signed_word) GPR[RS] >= 0)
699 {
700 mark_branch_bug (NIA+offset);
701 DELAY_SLOT (NIA + offset);
702 }
703 else
704 NULLIFY_NEXT_INSTRUCTION ();
705}
706
707
708
709000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
710"bgtz r<RS>, <OFFSET>"
c5d00cc7
CD		 711*mipsI:
712*mipsII:
713*mipsIII:
714*mipsIV:
603a98e7 715*mipsV:
1e799e28
CD		 716*mips32:
717*mips64:
c906108c
SS		 718*vr4100:
719*vr5000:
720*r3900:
721{
722 address_word offset = EXTEND16 (OFFSET) << 2;
723 check_branch_bug ();
724 if ((signed_word) GPR[RS] > 0)
725 {
726 mark_branch_bug (NIA+offset);
727 DELAY_SLOT (NIA + offset);
728 }
729}
730
731
732
733010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
734"bgtzl r<RS>, <OFFSET>"
735*mipsII:
736*mipsIII:
737*mipsIV:
603a98e7 738*mipsV:
1e799e28
CD		 739*mips32:
740*mips64:
c906108c
SS		 741*vr4100:
742*vr5000:
743*r3900:
744{
745 address_word offset = EXTEND16 (OFFSET) << 2;
746 check_branch_bug ();
747 /* NOTE: The branch occurs AFTER the next instruction has been
748 executed */
749 if ((signed_word) GPR[RS] > 0)
750 {
751 mark_branch_bug (NIA+offset);
752 DELAY_SLOT (NIA + offset);
753 }
754 else
755 NULLIFY_NEXT_INSTRUCTION ();
756}
757
758
759
760000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
761"blez r<RS>, <OFFSET>"
c5d00cc7
CD		 762*mipsI:
763*mipsII:
764*mipsIII:
765*mipsIV:
603a98e7 766*mipsV:
1e799e28
CD		 767*mips32:
768*mips64:
c906108c
SS		 769*vr4100:
770*vr5000:
771*r3900:
772{
773 address_word offset = EXTEND16 (OFFSET) << 2;
774 check_branch_bug ();
775 /* NOTE: The branch occurs AFTER the next instruction has been
776 executed */
777 if ((signed_word) GPR[RS] <= 0)
778 {
779 mark_branch_bug (NIA+offset);
780 DELAY_SLOT (NIA + offset);
781 }
782}
783
784
785
786010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
787"bgezl r<RS>, <OFFSET>"
788*mipsII:
789*mipsIII:
790*mipsIV:
603a98e7 791*mipsV:
1e799e28
CD		 792*mips32:
793*mips64:
c906108c
SS		 794*vr4100:
795*vr5000:
796*r3900:
797{
798 address_word offset = EXTEND16 (OFFSET) << 2;
799 check_branch_bug ();
800 if ((signed_word) GPR[RS] <= 0)
801 {
802 mark_branch_bug (NIA+offset);
803 DELAY_SLOT (NIA + offset);
804 }
805 else
806 NULLIFY_NEXT_INSTRUCTION ();
807}
808
809
810
811000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
812"bltz r<RS>, <OFFSET>"
c5d00cc7
CD		 813*mipsI:
814*mipsII:
815*mipsIII:
816*mipsIV:
603a98e7 817*mipsV:
1e799e28
CD		 818*mips32:
819*mips64:
c906108c
SS		 820*vr4100:
821*vr5000:
822*r3900:
823{
824 address_word offset = EXTEND16 (OFFSET) << 2;
825 check_branch_bug ();
826 if ((signed_word) GPR[RS] < 0)
827 {
828 mark_branch_bug (NIA+offset);
829 DELAY_SLOT (NIA + offset);
830 }
831}
832
833
834
835000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
836"bltzal r<RS>, <OFFSET>"
c5d00cc7
CD		 837*mipsI:
838*mipsII:
839*mipsIII:
840*mipsIV:
603a98e7 841*mipsV:
1e799e28
CD		 842*mips32:
843*mips64:
c906108c
SS		 844*vr4100:
845*vr5000:
846*r3900:
847{
848 address_word offset = EXTEND16 (OFFSET) << 2;
849 check_branch_bug ();
402586aa
CD		 850 if (RS == 31)
851 Unpredictable ();
c906108c
SS		 852 RA = (CIA + 8);
853 /* NOTE: The branch occurs AFTER the next instruction has been
854 executed */
855 if ((signed_word) GPR[RS] < 0)
856 {
857 mark_branch_bug (NIA+offset);
858 DELAY_SLOT (NIA + offset);
859 }
860}
861
862
863
864000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
865"bltzall r<RS>, <OFFSET>"
866*mipsII:
867*mipsIII:
868*mipsIV:
603a98e7 869*mipsV:
1e799e28
CD		 870*mips32:
871*mips64:
c906108c
SS		 872*vr4100:
873*vr5000:
874*r3900:
875{
876 address_word offset = EXTEND16 (OFFSET) << 2;
877 check_branch_bug ();
402586aa
CD		 878 if (RS == 31)
879 Unpredictable ();
c906108c
SS		 880 RA = (CIA + 8);
881 if ((signed_word) GPR[RS] < 0)
882 {
883 mark_branch_bug (NIA+offset);
884 DELAY_SLOT (NIA + offset);
885 }
886 else
887 NULLIFY_NEXT_INSTRUCTION ();
888}
889
890
891
892000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
893"bltzl r<RS>, <OFFSET>"
894*mipsII:
895*mipsIII:
896*mipsIV:
603a98e7 897*mipsV:
1e799e28
CD		 898*mips32:
899*mips64:
c906108c
SS		 900*vr4100:
901*vr5000:
902*r3900:
903{
904 address_word offset = EXTEND16 (OFFSET) << 2;
905 check_branch_bug ();
906 /* NOTE: The branch occurs AFTER the next instruction has been
907 executed */
908 if ((signed_word) GPR[RS] < 0)
909 {
910 mark_branch_bug (NIA+offset);
911 DELAY_SLOT (NIA + offset);
912 }
913 else
914 NULLIFY_NEXT_INSTRUCTION ();
915}
916
917
918
919000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
920"bne r<RS>, r<RT>, <OFFSET>"
c5d00cc7
CD		 921*mipsI:
922*mipsII:
923*mipsIII:
924*mipsIV:
603a98e7 925*mipsV:
1e799e28
CD		 926*mips32:
927*mips64:
c906108c
SS		 928*vr4100:
929*vr5000:
930*r3900:
931{
932 address_word offset = EXTEND16 (OFFSET) << 2;
933 check_branch_bug ();
934 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
935 {
936 mark_branch_bug (NIA+offset);
937 DELAY_SLOT (NIA + offset);
938 }
939}
940
941
942
943010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
944"bnel r<RS>, r<RT>, <OFFSET>"
945*mipsII:
946*mipsIII:
947*mipsIV:
603a98e7 948*mipsV:
1e799e28
CD		 949*mips32:
950*mips64:
c906108c
SS		 951*vr4100:
952*vr5000:
953*r3900:
954{
955 address_word offset = EXTEND16 (OFFSET) << 2;
956 check_branch_bug ();
957 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
958 {
959 mark_branch_bug (NIA+offset);
960 DELAY_SLOT (NIA + offset);
961 }
962 else
963 NULLIFY_NEXT_INSTRUCTION ();
964}
965
966
967
968000000,20.CODE,001101:SPECIAL:32::BREAK
82f728db 969"break %#lx<CODE>"
c5d00cc7
CD		 970*mipsI:
971*mipsII:
972*mipsIII:
973*mipsIV:
603a98e7 974*mipsV:
1e799e28
CD		 975*mips32:
976*mips64:
c906108c
SS		 977*vr4100:
978*vr5000:
979*r3900:
980{
981 /* Check for some break instruction which are reserved for use by the simulator. */
982 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
983 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
984 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
985 {
986 sim_engine_halt (SD, CPU, NULL, cia,
987 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
988 }
989 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
990 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
991 {
992 if (STATE & simDELAYSLOT)
993 PC = cia - 4; /* reference the branch instruction */
994 else
995 PC = cia;
86b77b47 996 SignalException (BreakPoint, instruction_0);
c906108c
SS		 997 }
998
999 else
1000 {
4a0bd876 1001 /* If we get this far, we're not an instruction reserved by the sim. Raise
c906108c 1002 the exception. */
86b77b47 1003 SignalException (BreakPoint, instruction_0);
c906108c
SS		 1004 }
1005}
1006
1007
1008
1e799e28
CD		 1009011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1010"clo r<RD>, r<RS>"
1011*mips32:
1012*mips64:
1013{
1014 unsigned32 temp = GPR[RS];
1015 unsigned32 i, mask;
1016 if (RT != RD)
c9b9995a 1017 Unpredictable ();
402586aa
CD		 1018 if (NotWordValue (GPR[RS]))
1019 Unpredictable ();
1e799e28
CD		 1020 TRACE_ALU_INPUT1 (GPR[RS]);
1021 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1022 {
1023 if ((temp & mask) == 0)
1024 break;
1025 mask >>= 1;
1026 }
1027 GPR[RD] = EXTEND32 (i);
1028 TRACE_ALU_RESULT (GPR[RD]);
1029}
1030
1031
1032
1033011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1034"clz r<RD>, r<RS>"
1035*mips32:
1036*mips64:
1037{
1038 unsigned32 temp = GPR[RS];
1039 unsigned32 i, mask;
1040 if (RT != RD)
c9b9995a 1041 Unpredictable ();
402586aa
CD		 1042 if (NotWordValue (GPR[RS]))
1043 Unpredictable ();
1e799e28
CD		 1044 TRACE_ALU_INPUT1 (GPR[RS]);
1045 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1046 {
1047 if ((temp & mask) != 0)
1048 break;
1049 mask >>= 1;
1050 }
1051 GPR[RD] = EXTEND32 (i);
1052 TRACE_ALU_RESULT (GPR[RD]);
1053}
1054
1055
1056
c906108c
SS		 1057000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1058"dadd r<RD>, r<RS>, r<RT>"
1059*mipsIII:
1060*mipsIV:
603a98e7 1061*mipsV:
1e799e28 1062*mips64:
c906108c
SS		 1063*vr4100:
1064*vr5000:
1065{
ca971540 1066 check_u64 (SD_, instruction_0);
c906108c
SS		 1067 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1068 {
1069 ALU64_BEGIN (GPR[RS]);
1070 ALU64_ADD (GPR[RT]);
9805e229 1071 ALU64_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 1072 }
1073 TRACE_ALU_RESULT (GPR[RD]);
1074}
1075
1076
1077
1078011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1079"daddi r<RT>, r<RS>, <IMMEDIATE>"
1080*mipsIII:
1081*mipsIV:
603a98e7 1082*mipsV:
1e799e28 1083*mips64:
c906108c
SS		 1084*vr4100:
1085*vr5000:
1086{
ca971540 1087 check_u64 (SD_, instruction_0);
c906108c
SS		 1088 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1089 {
1090 ALU64_BEGIN (GPR[RS]);
1091 ALU64_ADD (EXTEND16 (IMMEDIATE));
9805e229 1092 ALU64_END (GPR[RT]); /* This checks for overflow. */
c906108c
SS		 1093 }
1094 TRACE_ALU_RESULT (GPR[RT]);
1095}
1096
1097
1098
1099:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1100{
1101 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1102 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1103 TRACE_ALU_RESULT (GPR[rt]);
1104}
1105
1106011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
20ae0098 1107"daddiu r<RT>, r<RS>, <IMMEDIATE>"
c906108c
SS		 1108*mipsIII:
1109*mipsIV:
603a98e7 1110*mipsV:
1e799e28 1111*mips64:
c906108c
SS		 1112*vr4100:
1113*vr5000:
1114{
ca971540 1115 check_u64 (SD_, instruction_0);
c906108c
SS		 1116 do_daddiu (SD_, RS, RT, IMMEDIATE);
1117}
1118
1119
1120
1121:function:::void:do_daddu:int rs, int rt, int rd
1122{
1123 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1124 GPR[rd] = GPR[rs] + GPR[rt];
1125 TRACE_ALU_RESULT (GPR[rd]);
1126}
1127
1128000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1129"daddu r<RD>, r<RS>, r<RT>"
1130*mipsIII:
1131*mipsIV:
603a98e7 1132*mipsV:
1e799e28 1133*mips64:
c906108c
SS		 1134*vr4100:
1135*vr5000:
1136{
ca971540 1137 check_u64 (SD_, instruction_0);
c906108c
SS		 1138 do_daddu (SD_, RS, RT, RD);
1139}
1140
1141
1142
1e799e28
CD		 1143011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1144"dclo r<RD>, r<RS>"
1145*mips64:
1146{
1147 unsigned64 temp = GPR[RS];
1148 unsigned32 i;
1149 unsigned64 mask;
1150 check_u64 (SD_, instruction_0);
1151 if (RT != RD)
c9b9995a 1152 Unpredictable ();
1e799e28
CD		 1153 TRACE_ALU_INPUT1 (GPR[RS]);
1154 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1155 {
1156 if ((temp & mask) == 0)
1157 break;
1158 mask >>= 1;
1159 }
1160 GPR[RD] = EXTEND32 (i);
1161 TRACE_ALU_RESULT (GPR[RD]);
1162}
1163
1164
1165
1166011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1167"dclz r<RD>, r<RS>"
1168*mips64:
1169{
1170 unsigned64 temp = GPR[RS];
1171 unsigned32 i;
1172 unsigned64 mask;
1173 check_u64 (SD_, instruction_0);
1174 if (RT != RD)
c9b9995a 1175 Unpredictable ();
1e799e28
CD		 1176 TRACE_ALU_INPUT1 (GPR[RS]);
1177 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1178 {
1179 if ((temp & mask) != 0)
1180 break;
1181 mask >>= 1;
1182 }
1183 GPR[RD] = EXTEND32 (i);
1184 TRACE_ALU_RESULT (GPR[RD]);
1185}
1186
1187
1188
c906108c
SS		 1189:function:::void:do_ddiv:int rs, int rt
1190{
1191 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1192 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1193 {
1194 signed64 n = GPR[rs];
1195 signed64 d = GPR[rt];
1196 signed64 hi;
1197 signed64 lo;
1198 if (d == 0)
1199 {
1200 lo = SIGNED64 (0x8000000000000000);
1201 hi = 0;
1202 }
1203 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1204 {
1205 lo = SIGNED64 (0x8000000000000000);
1206 hi = 0;
1207 }
1208 else
1209 {
1210 lo = (n / d);
1211 hi = (n % d);
1212 }
1213 HI = hi;
1214 LO = lo;
1215 }
1216 TRACE_ALU_RESULT2 (HI, LO);
1217}
1218
f701dad2 1219000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
c906108c
SS		 1220"ddiv r<RS>, r<RT>"
1221*mipsIII:
1222*mipsIV:
603a98e7 1223*mipsV:
1e799e28 1224*mips64:
c906108c
SS		 1225*vr4100:
1226*vr5000:
1227{
ca971540 1228 check_u64 (SD_, instruction_0);
c906108c
SS		 1229 do_ddiv (SD_, RS, RT);
1230}
1231
1232
1233
1234:function:::void:do_ddivu:int rs, int rt
1235{
1236 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1237 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1238 {
1239 unsigned64 n = GPR[rs];
1240 unsigned64 d = GPR[rt];
1241 unsigned64 hi;
1242 unsigned64 lo;
1243 if (d == 0)
1244 {
1245 lo = SIGNED64 (0x8000000000000000);
1246 hi = 0;
1247 }
1248 else
1249 {
1250 lo = (n / d);
1251 hi = (n % d);
1252 }
1253 HI = hi;
1254 LO = lo;
1255 }
1256 TRACE_ALU_RESULT2 (HI, LO);
1257}
1258
1259000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1260"ddivu r<RS>, r<RT>"
1261*mipsIII:
1262*mipsIV:
603a98e7 1263*mipsV:
1e799e28 1264*mips64:
c906108c
SS		 1265*vr4100:
1266*vr5000:
1267{
ca971540 1268 check_u64 (SD_, instruction_0);
c906108c
SS		 1269 do_ddivu (SD_, RS, RT);
1270}
1271
1272
1273
1274:function:::void:do_div:int rs, int rt
1275{
1276 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1277 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1278 {
1279 signed32 n = GPR[rs];
1280 signed32 d = GPR[rt];
1281 if (d == 0)
1282 {
1283 LO = EXTEND32 (0x80000000);
1284 HI = EXTEND32 (0);
1285 }
1286 else if (n == SIGNED32 (0x80000000) && d == -1)
1287 {
1288 LO = EXTEND32 (0x80000000);
1289 HI = EXTEND32 (0);
1290 }
1291 else
1292 {
1293 LO = EXTEND32 (n / d);
1294 HI = EXTEND32 (n % d);
1295 }
1296 }
1297 TRACE_ALU_RESULT2 (HI, LO);
1298}
1299
f701dad2 1300000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
c906108c 1301"div r<RS>, r<RT>"
c5d00cc7
CD		 1302*mipsI:
1303*mipsII:
1304*mipsIII:
1305*mipsIV:
603a98e7 1306*mipsV:
1e799e28
CD		 1307*mips32:
1308*mips64:
c906108c
SS		 1309*vr4100:
1310*vr5000:
1311*r3900:
1312{
1313 do_div (SD_, RS, RT);
1314}
1315
1316
1317
1318:function:::void:do_divu:int rs, int rt
1319{
1320 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1321 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1322 {
1323 unsigned32 n = GPR[rs];
1324 unsigned32 d = GPR[rt];
1325 if (d == 0)
1326 {
1327 LO = EXTEND32 (0x80000000);
1328 HI = EXTEND32 (0);
1329 }
3e1dca16
CD		 1330 else
1331 {
1332 LO = EXTEND32 (n / d);
1333 HI = EXTEND32 (n % d);
1334 }
c906108c
SS		 1335 }
1336 TRACE_ALU_RESULT2 (HI, LO);
1337}
1338
f701dad2 1339000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
c906108c 1340"divu r<RS>, r<RT>"
c5d00cc7
CD		 1341*mipsI:
1342*mipsII:
1343*mipsIII:
1344*mipsIV:
603a98e7 1345*mipsV:
1e799e28
CD		 1346*mips32:
1347*mips64:
c906108c
SS		 1348*vr4100:
1349*vr5000:
1350*r3900:
1351{
1352 do_divu (SD_, RS, RT);
1353}
1354
1355
1356
1357:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1358{
1359 unsigned64 lo;
1360 unsigned64 hi;
1361 unsigned64 m00;
1362 unsigned64 m01;
1363 unsigned64 m10;
1364 unsigned64 m11;
1365 unsigned64 mid;
1366 int sign;
1367 unsigned64 op1 = GPR[rs];
1368 unsigned64 op2 = GPR[rt];
1369 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1370 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4a0bd876 1371 /* make signed multiply unsigned */
c906108c
SS		 1372 sign = 0;
1373 if (signed_p)
1374 {
1375 if (op1 < 0)
1376 {
1377 op1 = - op1;
1378 ++sign;
1379 }
1380 if (op2 < 0)
1381 {
1382 op2 = - op2;
1383 ++sign;
1384 }
1385 }
67f5c7ef 1386 /* multiply out the 4 sub products */
c906108c
SS		 1387 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1388 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1389 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1390 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1391 /* add the products */
1392 mid = ((unsigned64) VH4_8 (m00)
1393 + (unsigned64) VL4_8 (m10)
1394 + (unsigned64) VL4_8 (m01));
1395 lo = U8_4 (mid, m00);
1396 hi = (m11
1397 + (unsigned64) VH4_8 (mid)
1398 + (unsigned64) VH4_8 (m01)
1399 + (unsigned64) VH4_8 (m10));
1400 /* fix the sign */
1401 if (sign & 1)
1402 {
1403 lo = -lo;
1404 if (lo == 0)
1405 hi = -hi;
1406 else
1407 hi = -hi - 1;
1408 }
1409 /* save the result HI/LO (and a gpr) */
1410 LO = lo;
1411 HI = hi;
1412 if (rd != 0)
1413 GPR[rd] = lo;
1414 TRACE_ALU_RESULT2 (HI, LO);
1415}
1416
1417:function:::void:do_dmult:int rs, int rt, int rd
1418{
1419 do_dmultx (SD_, rs, rt, rd, 1);
1420}
1421
f701dad2 1422000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
c906108c 1423"dmult r<RS>, r<RT>"
c5d00cc7
CD		 1424*mipsIII:
1425*mipsIV:
603a98e7 1426*mipsV:
1e799e28 1427*mips64:
c906108c
SS		 1428*vr4100:
1429{
ca971540 1430 check_u64 (SD_, instruction_0);
c906108c
SS		 1431 do_dmult (SD_, RS, RT, 0);
1432}
1433
f701dad2 1434000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
c906108c
SS		 1435"dmult r<RS>, r<RT>":RD == 0
1436"dmult r<RD>, r<RS>, r<RT>"
1437*vr5000:
1438{
ca971540 1439 check_u64 (SD_, instruction_0);
c906108c
SS		 1440 do_dmult (SD_, RS, RT, RD);
1441}
1442
1443
1444
1445:function:::void:do_dmultu:int rs, int rt, int rd
1446{
1447 do_dmultx (SD_, rs, rt, rd, 0);
1448}
1449
f701dad2 1450000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
c906108c 1451"dmultu r<RS>, r<RT>"
c5d00cc7
CD		 1452*mipsIII:
1453*mipsIV:
603a98e7 1454*mipsV:
1e799e28 1455*mips64:
c906108c
SS		 1456*vr4100:
1457{
ca971540 1458 check_u64 (SD_, instruction_0);
c906108c
SS		 1459 do_dmultu (SD_, RS, RT, 0);
1460}
1461
f701dad2 1462000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
c906108c
SS		 1463"dmultu r<RD>, r<RS>, r<RT>":RD == 0
1464"dmultu r<RS>, r<RT>"
1465*vr5000:
1466{
ca971540 1467 check_u64 (SD_, instruction_0);
c906108c
SS		 1468 do_dmultu (SD_, RS, RT, RD);
1469}
1470
1471:function:::void:do_dsll:int rt, int rd, int shift
1472{
fff8d27d 1473 TRACE_ALU_INPUT2 (GPR[rt], shift);
c906108c 1474 GPR[rd] = GPR[rt] << shift;
fff8d27d 1475 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 1476}
1477
f701dad2 1478000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
c906108c
SS		 1479"dsll r<RD>, r<RT>, <SHIFT>"
1480*mipsIII:
1481*mipsIV:
603a98e7 1482*mipsV:
1e799e28 1483*mips64:
c906108c
SS		 1484*vr4100:
1485*vr5000:
1486{
ca971540 1487 check_u64 (SD_, instruction_0);
c906108c
SS		 1488 do_dsll (SD_, RT, RD, SHIFT);
1489}
1490
1491
f701dad2 1492000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
c906108c
SS		 1493"dsll32 r<RD>, r<RT>, <SHIFT>"
1494*mipsIII:
1495*mipsIV:
603a98e7 1496*mipsV:
1e799e28 1497*mips64:
c906108c
SS		 1498*vr4100:
1499*vr5000:
1500{
1501 int s = 32 + SHIFT;
ca971540 1502 check_u64 (SD_, instruction_0);
fff8d27d 1503 TRACE_ALU_INPUT2 (GPR[RT], s);
c906108c 1504 GPR[RD] = GPR[RT] << s;
fff8d27d 1505 TRACE_ALU_RESULT (GPR[RD]);
c906108c
SS		 1506}
1507
3e1dca16
CD		 1508:function:::void:do_dsllv:int rs, int rt, int rd
1509{
1510 int s = MASKED64 (GPR[rs], 5, 0);
1511 TRACE_ALU_INPUT2 (GPR[rt], s);
1512 GPR[rd] = GPR[rt] << s;
1513 TRACE_ALU_RESULT (GPR[rd]);
1514}
1515
f701dad2 1516000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
c906108c
SS		 1517"dsllv r<RD>, r<RT>, r<RS>"
1518*mipsIII:
1519*mipsIV:
603a98e7 1520*mipsV:
1e799e28 1521*mips64:
c906108c
SS		 1522*vr4100:
1523*vr5000:
1524{
ca971540 1525 check_u64 (SD_, instruction_0);
c906108c
SS		 1526 do_dsllv (SD_, RS, RT, RD);
1527}
1528
1529:function:::void:do_dsra:int rt, int rd, int shift
1530{
fff8d27d 1531 TRACE_ALU_INPUT2 (GPR[rt], shift);
c906108c 1532 GPR[rd] = ((signed64) GPR[rt]) >> shift;
fff8d27d 1533 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 1534}
1535
1536
f701dad2 1537000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
c906108c
SS		 1538"dsra r<RD>, r<RT>, <SHIFT>"
1539*mipsIII:
1540*mipsIV:
603a98e7 1541*mipsV:
1e799e28 1542*mips64:
c906108c
SS		 1543*vr4100:
1544*vr5000:
1545{
ca971540 1546 check_u64 (SD_, instruction_0);
c906108c
SS		 1547 do_dsra (SD_, RT, RD, SHIFT);
1548}
1549
1550
f701dad2 1551000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
bb22bd7d 1552"dsra32 r<RD>, r<RT>, <SHIFT>"
c906108c
SS		 1553*mipsIII:
1554*mipsIV:
603a98e7 1555*mipsV:
1e799e28 1556*mips64:
c906108c
SS		 1557*vr4100:
1558*vr5000:
1559{
1560 int s = 32 + SHIFT;
ca971540 1561 check_u64 (SD_, instruction_0);
fff8d27d 1562 TRACE_ALU_INPUT2 (GPR[RT], s);
c906108c 1563 GPR[RD] = ((signed64) GPR[RT]) >> s;
fff8d27d 1564 TRACE_ALU_RESULT (GPR[RD]);
c906108c
SS		 1565}
1566
1567
1568:function:::void:do_dsrav:int rs, int rt, int rd
1569{
1570 int s = MASKED64 (GPR[rs], 5, 0);
1571 TRACE_ALU_INPUT2 (GPR[rt], s);
1572 GPR[rd] = ((signed64) GPR[rt]) >> s;
1573 TRACE_ALU_RESULT (GPR[rd]);
1574}
1575
f701dad2 1576000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
bb22bd7d 1577"dsrav r<RD>, r<RT>, r<RS>"
c906108c
SS		 1578*mipsIII:
1579*mipsIV:
603a98e7 1580*mipsV:
1e799e28 1581*mips64:
c906108c
SS		 1582*vr4100:
1583*vr5000:
1584{
ca971540 1585 check_u64 (SD_, instruction_0);
c906108c
SS		 1586 do_dsrav (SD_, RS, RT, RD);
1587}
1588
1589:function:::void:do_dsrl:int rt, int rd, int shift
1590{
fff8d27d 1591 TRACE_ALU_INPUT2 (GPR[rt], shift);
c906108c 1592 GPR[rd] = (unsigned64) GPR[rt] >> shift;
fff8d27d 1593 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 1594}
1595
1596
f701dad2 1597000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
c906108c
SS		 1598"dsrl r<RD>, r<RT>, <SHIFT>"
1599*mipsIII:
1600*mipsIV:
603a98e7 1601*mipsV:
1e799e28 1602*mips64:
c906108c
SS		 1603*vr4100:
1604*vr5000:
1605{
ca971540 1606 check_u64 (SD_, instruction_0);
c906108c
SS		 1607 do_dsrl (SD_, RT, RD, SHIFT);
1608}
1609
1610
f701dad2 1611000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
c906108c
SS		 1612"dsrl32 r<RD>, r<RT>, <SHIFT>"
1613*mipsIII:
1614*mipsIV:
603a98e7 1615*mipsV:
1e799e28 1616*mips64:
c906108c
SS		 1617*vr4100:
1618*vr5000:
1619{
1620 int s = 32 + SHIFT;
ca971540 1621 check_u64 (SD_, instruction_0);
fff8d27d 1622 TRACE_ALU_INPUT2 (GPR[RT], s);
c906108c 1623 GPR[RD] = (unsigned64) GPR[RT] >> s;
fff8d27d 1624 TRACE_ALU_RESULT (GPR[RD]);
c906108c
SS		 1625}
1626
1627
1628:function:::void:do_dsrlv:int rs, int rt, int rd
1629{
1630 int s = MASKED64 (GPR[rs], 5, 0);
fff8d27d 1631 TRACE_ALU_INPUT2 (GPR[rt], s);
c906108c 1632 GPR[rd] = (unsigned64) GPR[rt] >> s;
fff8d27d 1633 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 1634}
1635
1636
1637
f701dad2 1638000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
20ae0098 1639"dsrlv r<RD>, r<RT>, r<RS>"
c906108c
SS		 1640*mipsIII:
1641*mipsIV:
603a98e7 1642*mipsV:
1e799e28 1643*mips64:
c906108c
SS		 1644*vr4100:
1645*vr5000:
1646{
ca971540 1647 check_u64 (SD_, instruction_0);
c906108c
SS		 1648 do_dsrlv (SD_, RS, RT, RD);
1649}
1650
1651
f701dad2 1652000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
c906108c
SS		 1653"dsub r<RD>, r<RS>, r<RT>"
1654*mipsIII:
1655*mipsIV:
603a98e7 1656*mipsV:
1e799e28 1657*mips64:
c906108c
SS		 1658*vr4100:
1659*vr5000:
1660{
ca971540 1661 check_u64 (SD_, instruction_0);
c906108c
SS		 1662 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1663 {
1664 ALU64_BEGIN (GPR[RS]);
1665 ALU64_SUB (GPR[RT]);
9805e229 1666 ALU64_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 1667 }
1668 TRACE_ALU_RESULT (GPR[RD]);
1669}
1670
1671
1672:function:::void:do_dsubu:int rs, int rt, int rd
1673{
1674 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1675 GPR[rd] = GPR[rs] - GPR[rt];
1676 TRACE_ALU_RESULT (GPR[rd]);
1677}
1678
f701dad2 1679000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
c906108c
SS		 1680"dsubu r<RD>, r<RS>, r<RT>"
1681*mipsIII:
1682*mipsIV:
603a98e7 1683*mipsV:
1e799e28 1684*mips64:
c906108c
SS		 1685*vr4100:
1686*vr5000:
1687{
ca971540 1688 check_u64 (SD_, instruction_0);
c906108c
SS		 1689 do_dsubu (SD_, RS, RT, RD);
1690}
1691
1692
1693000010,26.INSTR_INDEX:NORMAL:32::J
1694"j <INSTR_INDEX>"
c5d00cc7
CD		 1695*mipsI:
1696*mipsII:
1697*mipsIII:
1698*mipsIV:
603a98e7 1699*mipsV:
1e799e28
CD		 1700*mips32:
1701*mips64:
c906108c
SS		 1702*vr4100:
1703*vr5000:
1704*r3900:
1705{
1706 /* NOTE: The region used is that of the delay slot NIA and NOT the
1707 current instruction */
1708 address_word region = (NIA & MASK (63, 28));
1709 DELAY_SLOT (region | (INSTR_INDEX << 2));
1710}
1711
1712
1713000011,26.INSTR_INDEX:NORMAL:32::JAL
1714"jal <INSTR_INDEX>"
c5d00cc7
CD		 1715*mipsI:
1716*mipsII:
1717*mipsIII:
1718*mipsIV:
603a98e7 1719*mipsV:
1e799e28
CD		 1720*mips32:
1721*mips64:
c906108c
SS		 1722*vr4100:
1723*vr5000:
1724*r3900:
1725{
1726 /* NOTE: The region used is that of the delay slot and NOT the
1727 current instruction */
1728 address_word region = (NIA & MASK (63, 28));
1729 GPR[31] = CIA + 8;
1730 DELAY_SLOT (region | (INSTR_INDEX << 2));
1731}
1732
f701dad2 1733000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
c906108c
SS		 1734"jalr r<RS>":RD == 31
1735"jalr r<RD>, r<RS>"
c5d00cc7
CD		 1736*mipsI:
1737*mipsII:
1738*mipsIII:
1739*mipsIV:
603a98e7 1740*mipsV:
1e799e28
CD		 1741*mips32:
1742*mips64:
c906108c
SS		 1743*vr4100:
1744*vr5000:
1745*r3900:
1746{
1747 address_word temp = GPR[RS];
1748 GPR[RD] = CIA + 8;
1749 DELAY_SLOT (temp);
1750}
1751
1752
f701dad2 1753000000,5.RS,000000000000000,001000:SPECIAL:32::JR
c906108c 1754"jr r<RS>"
c5d00cc7
CD		 1755*mipsI:
1756*mipsII:
1757*mipsIII:
1758*mipsIV:
603a98e7 1759*mipsV:
1e799e28
CD		 1760*mips32:
1761*mips64:
c906108c
SS		 1762*vr4100:
1763*vr5000:
1764*r3900:
1765{
1766 DELAY_SLOT (GPR[RS]);
1767}
1768
1769
1770:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1771{
1772 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1773 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1774 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1775 unsigned int byte;
1776 address_word paddr;
1777 int uncached;
1778 unsigned64 memval;
1779 address_word vaddr;
1780
09297648 1781 vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 1782 if ((vaddr & access) != 0)
1783 {
1784 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1785 }
1786 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1787 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1788 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1789 byte = ((vaddr & mask) ^ bigendiancpu);
1790 return (memval >> (8 * byte));
1791}
1792
1c47a468
CD		 1793:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1794{
1795 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1796 address_word reverseendian = (ReverseEndian ? -1 : 0);
1797 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1798 unsigned int byte;
1799 unsigned int word;
1800 address_word paddr;
1801 int uncached;
1802 unsigned64 memval;
1803 address_word vaddr;
1804 int nr_lhs_bits;
1805 int nr_rhs_bits;
1806 unsigned_word lhs_mask;
1807 unsigned_word temp;
1808
09297648 1809 vaddr = loadstore_ea (SD_, base, offset);
1c47a468
CD		 1810 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1811 paddr = (paddr ^ (reverseendian & mask));
1812 if (BigEndianMem == 0)
1813 paddr = paddr & ~access;
1814
1815 /* compute where within the word/mem we are */
1816 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1817 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1818 nr_lhs_bits = 8 * byte + 8;
1819 nr_rhs_bits = 8 * access - 8 * byte;
1820 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1821
1822 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1823 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1824 (long) ((unsigned64) paddr >> 32), (long) paddr,
1825 word, byte, nr_lhs_bits, nr_rhs_bits); */
1826
1827 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1828 if (word == 0)
1829 {
1830 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1831 temp = (memval << nr_rhs_bits);
1832 }
1833 else
1834 {
1835 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1836 temp = (memval >> nr_lhs_bits);
1837 }
1838 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1839 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1840
1841 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1842 (long) ((unsigned64) memval >> 32), (long) memval,
1843 (long) ((unsigned64) temp >> 32), (long) temp,
1844 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1845 (long) (rt >> 32), (long) rt); */
1846 return rt;
1847}
1848
1849:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1850{
1851 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1852 address_word reverseendian = (ReverseEndian ? -1 : 0);
1853 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1854 unsigned int byte;
1855 address_word paddr;
1856 int uncached;
1857 unsigned64 memval;
1858 address_word vaddr;
1859
09297648 1860 vaddr = loadstore_ea (SD_, base, offset);
1c47a468
CD		 1861 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1862 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1863 paddr = (paddr ^ (reverseendian & mask));
1864 if (BigEndianMem != 0)
1865 paddr = paddr & ~access;
1866 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1867 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
1868 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1869 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1870 (long) paddr, byte, (long) paddr, (long) memval); */
1871 {
1872 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1873 rt &= ~screen;
1874 rt |= (memval >> (8 * byte)) & screen;
1875 }
1876 return rt;
1877}
1878
c906108c
SS		 1879
1880100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1881"lb r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 1882*mipsI:
1883*mipsII:
1884*mipsIII:
1885*mipsIV:
603a98e7 1886*mipsV:
1e799e28
CD		 1887*mips32:
1888*mips64:
c906108c
SS		 1889*vr4100:
1890*vr5000:
1891*r3900:
1892{
1893 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1894}
1895
1896
1897100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1898"lbu r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 1899*mipsI:
1900*mipsII:
1901*mipsIII:
1902*mipsIV:
603a98e7 1903*mipsV:
1e799e28
CD		 1904*mips32:
1905*mips64:
c906108c
SS		 1906*vr4100:
1907*vr5000:
1908*r3900:
1909{
1910 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1911}
1912
1913
1914110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1915"ld r<RT>, <OFFSET>(r<BASE>)"
1916*mipsIII:
1917*mipsIV:
603a98e7 1918*mipsV:
1e799e28 1919*mips64:
c906108c
SS		 1920*vr4100:
1921*vr5000:
1922{
ca971540 1923 check_u64 (SD_, instruction_0);
c906108c
SS		 1924 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1925}
1926
1927
19281101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1929"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1930*mipsII:
1931*mipsIII:
1932*mipsIV:
603a98e7 1933*mipsV:
1e799e28
CD		 1934*mips32:
1935*mips64:
c906108c
SS		 1936*vr4100:
1937*vr5000:
1938*r3900:
1939{
1940 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1941}
1942
1943
1944
1945
1946011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1947"ldl r<RT>, <OFFSET>(r<BASE>)"
1948*mipsIII:
1949*mipsIV:
603a98e7 1950*mipsV:
1e799e28 1951*mips64:
c906108c
SS		 1952*vr4100:
1953*vr5000:
1954{
ca971540 1955 check_u64 (SD_, instruction_0);
c906108c
SS		 1956 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1957}
1958
1959
1960011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1961"ldr r<RT>, <OFFSET>(r<BASE>)"
1962*mipsIII:
1963*mipsIV:
603a98e7 1964*mipsV:
1e799e28 1965*mips64:
c906108c
SS		 1966*vr4100:
1967*vr5000:
1968{
ca971540 1969 check_u64 (SD_, instruction_0);
c906108c
SS		 1970 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1971}
1972
1973
1974100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1975"lh r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 1976*mipsI:
1977*mipsII:
1978*mipsIII:
1979*mipsIV:
603a98e7 1980*mipsV:
1e799e28
CD		 1981*mips32:
1982*mips64:
c906108c
SS		 1983*vr4100:
1984*vr5000:
1985*r3900:
1986{
1987 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1988}
1989
1990
1991100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1992"lhu r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 1993*mipsI:
1994*mipsII:
1995*mipsIII:
1996*mipsIV:
603a98e7 1997*mipsV:
1e799e28
CD		 1998*mips32:
1999*mips64:
c906108c
SS		 2000*vr4100:
2001*vr5000:
2002*r3900:
2003{
2004 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2005}
2006
2007
2008110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2009"ll r<RT>, <OFFSET>(r<BASE>)"
2010*mipsII:
2011*mipsIII:
2012*mipsIV:
603a98e7 2013*mipsV:
1e799e28
CD		 2014*mips32:
2015*mips64:
c906108c
SS		 2016*vr4100:
2017*vr5000:
2018{
c1e8ada4
CD		 2019 address_word base = GPR[BASE];
2020 address_word offset = EXTEND16 (OFFSET);
c906108c 2021 {
09297648 2022 address_word vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 2023 address_word paddr;
2024 int uncached;
2025 if ((vaddr & 3) != 0)
2026 {
2027 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2028 }
2029 else
2030 {
2031 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2032 {
2033 unsigned64 memval = 0;
2034 unsigned64 memval1 = 0;
2035 unsigned64 mask = 0x7;
2036 unsigned int shift = 2;
2037 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2038 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2039 unsigned int byte;
2040 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2041 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2042 byte = ((vaddr & mask) ^ (bigend << shift));
043b7057 2043 GPR[RT] = EXTEND32 (memval >> (8 * byte));
c906108c
SS		 2044 LLBIT = 1;
2045 }
2046 }
2047 }
2048}
2049
2050
2051110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2052"lld r<RT>, <OFFSET>(r<BASE>)"
2053*mipsIII:
2054*mipsIV:
603a98e7 2055*mipsV:
1e799e28 2056*mips64:
c906108c
SS		 2057*vr4100:
2058*vr5000:
2059{
c1e8ada4
CD		 2060 address_word base = GPR[BASE];
2061 address_word offset = EXTEND16 (OFFSET);
ca971540 2062 check_u64 (SD_, instruction_0);
c906108c 2063 {
09297648 2064 address_word vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 2065 address_word paddr;
2066 int uncached;
2067 if ((vaddr & 7) != 0)
2068 {
2069 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2070 }
2071 else
2072 {
2073 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2074 {
2075 unsigned64 memval = 0;
2076 unsigned64 memval1 = 0;
2077 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
c1e8ada4 2078 GPR[RT] = memval;
c906108c
SS		 2079 LLBIT = 1;
2080 }
2081 }
2082 }
2083}
2084
2085
2086001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
82f728db 2087"lui r<RT>, %#lx<IMMEDIATE>"
c5d00cc7
CD		 2088*mipsI:
2089*mipsII:
2090*mipsIII:
2091*mipsIV:
603a98e7 2092*mipsV:
1e799e28
CD		 2093*mips32:
2094*mips64:
c906108c
SS		 2095*vr4100:
2096*vr5000:
2097*r3900:
2098{
2099 TRACE_ALU_INPUT1 (IMMEDIATE);
2100 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2101 TRACE_ALU_RESULT (GPR[RT]);
2102}
2103
2104
2105100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2106"lw r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2107*mipsI:
2108*mipsII:
2109*mipsIII:
2110*mipsIV:
603a98e7 2111*mipsV:
1e799e28
CD		 2112*mips32:
2113*mips64:
c906108c
SS		 2114*vr4100:
2115*vr5000:
2116*r3900:
2117{
2118 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2119}
2120
2121
21221100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2123"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2124*mipsI:
2125*mipsII:
2126*mipsIII:
2127*mipsIV:
603a98e7 2128*mipsV:
1e799e28
CD		 2129*mips32:
2130*mips64:
c906108c
SS		 2131*vr4100:
2132*vr5000:
2133*r3900:
2134{
2135 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2136}
2137
2138
c906108c
SS		 2139100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2140"lwl r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2141*mipsI:
2142*mipsII:
2143*mipsIII:
2144*mipsIV:
603a98e7 2145*mipsV:
1e799e28
CD		 2146*mips32:
2147*mips64:
c906108c
SS		 2148*vr4100:
2149*vr5000:
2150*r3900:
2151{
7a292a7a 2152 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
c906108c
SS		 2153}
2154
2155
c906108c
SS		 2156100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2157"lwr r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2158*mipsI:
2159*mipsII:
2160*mipsIII:
2161*mipsIV:
603a98e7 2162*mipsV:
1e799e28
CD		 2163*mips32:
2164*mips64:
c906108c
SS		 2165*vr4100:
2166*vr5000:
2167*r3900:
2168{
2169 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2170}
2171
2172
bb22bd7d 2173100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
c906108c
SS		 2174"lwu r<RT>, <OFFSET>(r<BASE>)"
2175*mipsIII:
2176*mipsIV:
603a98e7 2177*mipsV:
1e799e28 2178*mips64:
c906108c
SS		 2179*vr4100:
2180*vr5000:
2181{
ca971540 2182 check_u64 (SD_, instruction_0);
c906108c
SS		 2183 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2184}
2185
2186
1e799e28
CD		 2187
2188011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2189"madd r<RS>, r<RT>"
2190*mips32:
2191*mips64:
2192{
2193 signed64 temp;
2194 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
402586aa
CD		 2195 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2196 Unpredictable ();
1e799e28
CD		 2197 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2198 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2199 + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2200 LO = EXTEND32 (temp);
2201 HI = EXTEND32 (VH4_8 (temp));
2202 TRACE_ALU_RESULT2 (HI, LO);
2203}
2204
2205
2206
2207011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2208"maddu r<RS>, r<RT>"
2209*mips32:
2210*mips64:
2211{
2212 unsigned64 temp;
2213 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
402586aa
CD		 2214 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2215 Unpredictable ();
1e799e28
CD		 2216 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2217 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2218 + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2219 LO = EXTEND32 (temp);
2220 HI = EXTEND32 (VH4_8 (temp));
2221 TRACE_ALU_RESULT2 (HI, LO);
2222}
2223
2224
c906108c
SS		 2225:function:::void:do_mfhi:int rd
2226{
2227 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2228 TRACE_ALU_INPUT1 (HI);
2229 GPR[rd] = HI;
2230 TRACE_ALU_RESULT (GPR[rd]);
2231}
2232
2233000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2234"mfhi r<RD>"
c5d00cc7
CD		 2235*mipsI:
2236*mipsII:
2237*mipsIII:
2238*mipsIV:
603a98e7 2239*mipsV:
1e799e28
CD		 2240*mips32:
2241*mips64:
c906108c
SS		 2242*vr4100:
2243*vr5000:
2244*r3900:
2245{
2246 do_mfhi (SD_, RD);
2247}
2248
2249
2250
2251:function:::void:do_mflo:int rd
2252{
2253 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2254 TRACE_ALU_INPUT1 (LO);
2255 GPR[rd] = LO;
2256 TRACE_ALU_RESULT (GPR[rd]);
2257}
2258
2259000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2260"mflo r<RD>"
c5d00cc7
CD		 2261*mipsI:
2262*mipsII:
2263*mipsIII:
2264*mipsIV:
603a98e7 2265*mipsV:
1e799e28
CD		 2266*mips32:
2267*mips64:
c906108c
SS		 2268*vr4100:
2269*vr5000:
2270*r3900:
2271{
2272 do_mflo (SD_, RD);
2273}
2274
2275
2276
f701dad2 2277000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
c906108c
SS		 2278"movn r<RD>, r<RS>, r<RT>"
2279*mipsIV:
603a98e7 2280*mipsV:
1e799e28
CD		 2281*mips32:
2282*mips64:
c906108c
SS		 2283*vr5000:
2284{
2285 if (GPR[RT] != 0)
95fd5cee
CD		 2286 {
2287 GPR[RD] = GPR[RS];
2288 TRACE_ALU_RESULT (GPR[RD]);
2289 }
c906108c
SS		 2290}
2291
2292
2293
f701dad2 2294000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
c906108c
SS		 2295"movz r<RD>, r<RS>, r<RT>"
2296*mipsIV:
603a98e7 2297*mipsV:
1e799e28
CD		 2298*mips32:
2299*mips64:
c906108c
SS		 2300*vr5000:
2301{
2302 if (GPR[RT] == 0)
95fd5cee
CD		 2303 {
2304 GPR[RD] = GPR[RS];
2305 TRACE_ALU_RESULT (GPR[RD]);
2306 }
c906108c
SS		 2307}
2308
2309
2310
1e799e28
CD		 2311011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2312"msub r<RS>, r<RT>"
2313*mips32:
2314*mips64:
2315{
2316 signed64 temp;
2317 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
402586aa
CD		 2318 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2319 Unpredictable ();
1e799e28
CD		 2320 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2321 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2322 - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2323 LO = EXTEND32 (temp);
2324 HI = EXTEND32 (VH4_8 (temp));
2325 TRACE_ALU_RESULT2 (HI, LO);
2326}
2327
2328
2329
2330011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2331"msubu r<RS>, r<RT>"
2332*mips32:
2333*mips64:
2334{
2335 unsigned64 temp;
2336 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
402586aa
CD		 2337 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2338 Unpredictable ();
1e799e28
CD		 2339 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2340 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2341 - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2342 LO = EXTEND32 (temp);
2343 HI = EXTEND32 (VH4_8 (temp));
2344 TRACE_ALU_RESULT2 (HI, LO);
2345}
2346
2347
2348
c906108c
SS		 2349000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2350"mthi r<RS>"
c5d00cc7
CD		 2351*mipsI:
2352*mipsII:
2353*mipsIII:
2354*mipsIV:
603a98e7 2355*mipsV:
1e799e28
CD		 2356*mips32:
2357*mips64:
c906108c
SS		 2358*vr4100:
2359*vr5000:
2360*r3900:
2361{
2362 check_mt_hilo (SD_, HIHISTORY);
2363 HI = GPR[RS];
2364}
2365
2366
2367
f701dad2 2368000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
c906108c 2369"mtlo r<RS>"
c5d00cc7
CD		 2370*mipsI:
2371*mipsII:
2372*mipsIII:
2373*mipsIV:
603a98e7 2374*mipsV:
1e799e28
CD		 2375*mips32:
2376*mips64:
c906108c
SS		 2377*vr4100:
2378*vr5000:
2379*r3900:
2380{
2381 check_mt_hilo (SD_, LOHISTORY);
2382 LO = GPR[RS];
2383}
2384
2385
2386
1e799e28
CD		 2387011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2388"mul r<RD>, r<RS>, r<RT>"
2389*mips32:
2390*mips64:
2391{
2392 signed64 prod;
402586aa
CD		 2393 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2394 Unpredictable ();
1e799e28
CD		 2395 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2396 prod = (((signed64)(signed32) GPR[RS])
2397 * ((signed64)(signed32) GPR[RT]));
2398 GPR[RD] = EXTEND32 (VL4_8 (prod));
2399 TRACE_ALU_RESULT (GPR[RD]);
2400}
2401
2402
2403
c906108c
SS		 2404:function:::void:do_mult:int rs, int rt, int rd
2405{
2406 signed64 prod;
2407 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
402586aa
CD		 2408 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2409 Unpredictable ();
c906108c
SS		 2410 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2411 prod = (((signed64)(signed32) GPR[rs])
2412 * ((signed64)(signed32) GPR[rt]));
2413 LO = EXTEND32 (VL4_8 (prod));
2414 HI = EXTEND32 (VH4_8 (prod));
2415 if (rd != 0)
2416 GPR[rd] = LO;
2417 TRACE_ALU_RESULT2 (HI, LO);
2418}
2419
f701dad2 2420000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
c906108c 2421"mult r<RS>, r<RT>"
c5d00cc7
CD		 2422*mipsI:
2423*mipsII:
2424*mipsIII:
2425*mipsIV:
603a98e7 2426*mipsV:
1e799e28
CD		 2427*mips32:
2428*mips64:
c906108c
SS		 2429*vr4100:
2430{
2431 do_mult (SD_, RS, RT, 0);
2432}
2433
2434
f701dad2 2435000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
9846de1b 2436"mult r<RS>, r<RT>":RD == 0
c906108c
SS		 2437"mult r<RD>, r<RS>, r<RT>"
2438*vr5000:
2439*r3900:
2440{
2441 do_mult (SD_, RS, RT, RD);
2442}
2443
2444
2445:function:::void:do_multu:int rs, int rt, int rd
2446{
2447 unsigned64 prod;
2448 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
402586aa
CD		 2449 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2450 Unpredictable ();
c906108c
SS		 2451 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2452 prod = (((unsigned64)(unsigned32) GPR[rs])
2453 * ((unsigned64)(unsigned32) GPR[rt]));
2454 LO = EXTEND32 (VL4_8 (prod));
2455 HI = EXTEND32 (VH4_8 (prod));
2456 if (rd != 0)
2457 GPR[rd] = LO;
2458 TRACE_ALU_RESULT2 (HI, LO);
2459}
2460
f701dad2 2461000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
c906108c 2462"multu r<RS>, r<RT>"
c5d00cc7
CD		 2463*mipsI:
2464*mipsII:
2465*mipsIII:
2466*mipsIV:
603a98e7 2467*mipsV:
1e799e28
CD		 2468*mips32:
2469*mips64:
c906108c
SS		 2470*vr4100:
2471{
cff3e48b 2472 do_multu (SD_, RS, RT, 0);
c906108c
SS		 2473}
2474
f701dad2 2475000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
9846de1b 2476"multu r<RS>, r<RT>":RD == 0
c906108c
SS		 2477"multu r<RD>, r<RS>, r<RT>"
2478*vr5000:
2479*r3900:
2480{
cff3e48b 2481 do_multu (SD_, RS, RT, RD);
c906108c
SS		 2482}
2483
2484
2485:function:::void:do_nor:int rs, int rt, int rd
2486{
2487 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2488 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2489 TRACE_ALU_RESULT (GPR[rd]);
2490}
2491
2492000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2493"nor r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 2494*mipsI:
2495*mipsII:
2496*mipsIII:
2497*mipsIV:
603a98e7 2498*mipsV:
1e799e28
CD		 2499*mips32:
2500*mips64:
c906108c
SS		 2501*vr4100:
2502*vr5000:
2503*r3900:
2504{
2505 do_nor (SD_, RS, RT, RD);
2506}
2507
2508
2509:function:::void:do_or:int rs, int rt, int rd
2510{
2511 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2512 GPR[rd] = (GPR[rs] | GPR[rt]);
2513 TRACE_ALU_RESULT (GPR[rd]);
2514}
2515
2516000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2517"or r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 2518*mipsI:
2519*mipsII:
2520*mipsIII:
2521*mipsIV:
603a98e7 2522*mipsV:
1e799e28
CD		 2523*mips32:
2524*mips64:
c906108c
SS		 2525*vr4100:
2526*vr5000:
2527*r3900:
2528{
2529 do_or (SD_, RS, RT, RD);
2530}
2531
2532
2533
2534:function:::void:do_ori:int rs, int rt, unsigned immediate
2535{
2536 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2537 GPR[rt] = (GPR[rs] | immediate);
2538 TRACE_ALU_RESULT (GPR[rt]);
2539}
2540
2541001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
82f728db 2542"ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
c5d00cc7
CD		 2543*mipsI:
2544*mipsII:
2545*mipsIII:
2546*mipsIV:
603a98e7 2547*mipsV:
1e799e28
CD		 2548*mips32:
2549*mips64:
c906108c
SS		 2550*vr4100:
2551*vr5000:
2552*r3900:
2553{
2554 do_ori (SD_, RS, RT, IMMEDIATE);
2555}
2556
2557
af5107af
CD		 2558110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2559"pref <HINT>, <OFFSET>(r<BASE>)"
c906108c 2560*mipsIV:
603a98e7 2561*mipsV:
1e799e28
CD		 2562*mips32:
2563*mips64:
c906108c
SS		 2564*vr5000:
2565{
c1e8ada4
CD		 2566 address_word base = GPR[BASE];
2567 address_word offset = EXTEND16 (OFFSET);
c906108c 2568 {
09297648 2569 address_word vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 2570 address_word paddr;
2571 int uncached;
2572 {
2573 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
c1e8ada4 2574 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
c906108c
SS		 2575 }
2576 }
2577}
2578
1c47a468 2579
c906108c
SS		 2580:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2581{
2582 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2583 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2584 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2585 unsigned int byte;
2586 address_word paddr;
2587 int uncached;
2588 unsigned64 memval;
2589 address_word vaddr;
2590
09297648 2591 vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 2592 if ((vaddr & access) != 0)
2593 {
2594 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2595 }
2596 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2597 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2598 byte = ((vaddr & mask) ^ bigendiancpu);
2599 memval = (word << (8 * byte));
2600 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2601}
2602
1c47a468
CD		 2603:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2604{
2605 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2606 address_word reverseendian = (ReverseEndian ? -1 : 0);
2607 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2608 unsigned int byte;
2609 unsigned int word;
2610 address_word paddr;
2611 int uncached;
2612 unsigned64 memval;
2613 address_word vaddr;
2614 int nr_lhs_bits;
2615 int nr_rhs_bits;
2616
09297648 2617 vaddr = loadstore_ea (SD_, base, offset);
1c47a468
CD		 2618 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2619 paddr = (paddr ^ (reverseendian & mask));
2620 if (BigEndianMem == 0)
2621 paddr = paddr & ~access;
2622
2623 /* compute where within the word/mem we are */
2624 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2625 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2626 nr_lhs_bits = 8 * byte + 8;
2627 nr_rhs_bits = 8 * access - 8 * byte;
2628 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2629 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2630 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2631 (long) ((unsigned64) paddr >> 32), (long) paddr,
2632 word, byte, nr_lhs_bits, nr_rhs_bits); */
2633
2634 if (word == 0)
2635 {
2636 memval = (rt >> nr_rhs_bits);
2637 }
2638 else
2639 {
2640 memval = (rt << nr_lhs_bits);
2641 }
2642 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2643 (long) ((unsigned64) rt >> 32), (long) rt,
2644 (long) ((unsigned64) memval >> 32), (long) memval); */
2645 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2646}
2647
2648:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2649{
2650 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2651 address_word reverseendian = (ReverseEndian ? -1 : 0);
2652 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2653 unsigned int byte;
2654 address_word paddr;
2655 int uncached;
2656 unsigned64 memval;
2657 address_word vaddr;
2658
09297648 2659 vaddr = loadstore_ea (SD_, base, offset);
1c47a468
CD		 2660 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2661 paddr = (paddr ^ (reverseendian & mask));
2662 if (BigEndianMem != 0)
2663 paddr &= ~access;
2664 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2665 memval = (rt << (byte * 8));
2666 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2667}
2668
c906108c
SS		 2669
2670101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2671"sb r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2672*mipsI:
2673*mipsII:
2674*mipsIII:
2675*mipsIV:
603a98e7 2676*mipsV:
1e799e28
CD		 2677*mips32:
2678*mips64:
c906108c
SS		 2679*vr4100:
2680*vr5000:
2681*r3900:
2682{
2683 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2684}
2685
2686
2687111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2688"sc r<RT>, <OFFSET>(r<BASE>)"
2689*mipsII:
2690*mipsIII:
2691*mipsIV:
603a98e7 2692*mipsV:
1e799e28
CD		 2693*mips32:
2694*mips64:
c906108c
SS		 2695*vr4100:
2696*vr5000:
2697{
2698 unsigned32 instruction = instruction_0;
c1e8ada4
CD		 2699 address_word base = GPR[BASE];
2700 address_word offset = EXTEND16 (OFFSET);
c906108c 2701 {
09297648 2702 address_word vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 2703 address_word paddr;
2704 int uncached;
2705 if ((vaddr & 3) != 0)
2706 {
2707 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2708 }
2709 else
2710 {
2711 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2712 {
2713 unsigned64 memval = 0;
2714 unsigned64 memval1 = 0;
2715 unsigned64 mask = 0x7;
2716 unsigned int byte;
2717 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2718 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
c1e8ada4 2719 memval = ((unsigned64) GPR[RT] << (8 * byte));
c906108c
SS		 2720 if (LLBIT)
2721 {
2722 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2723 }
c1e8ada4 2724 GPR[RT] = LLBIT;
c906108c
SS		 2725 }
2726 }
2727 }
2728}
2729
2730
2731111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2732"scd r<RT>, <OFFSET>(r<BASE>)"
2733*mipsIII:
2734*mipsIV:
603a98e7 2735*mipsV:
1e799e28 2736*mips64:
c906108c
SS		 2737*vr4100:
2738*vr5000:
2739{
c1e8ada4
CD		 2740 address_word base = GPR[BASE];
2741 address_word offset = EXTEND16 (OFFSET);
ca971540 2742 check_u64 (SD_, instruction_0);
c906108c 2743 {
09297648 2744 address_word vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 2745 address_word paddr;
2746 int uncached;
2747 if ((vaddr & 7) != 0)
2748 {
2749 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2750 }
2751 else
2752 {
2753 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2754 {
2755 unsigned64 memval = 0;
2756 unsigned64 memval1 = 0;
c1e8ada4 2757 memval = GPR[RT];
c906108c
SS		 2758 if (LLBIT)
2759 {
2760 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2761 }
c1e8ada4 2762 GPR[RT] = LLBIT;
c906108c
SS		 2763 }
2764 }
2765 }
2766}
2767
2768
2769111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2770"sd r<RT>, <OFFSET>(r<BASE>)"
2771*mipsIII:
2772*mipsIV:
603a98e7 2773*mipsV:
1e799e28 2774*mips64:
c906108c
SS		 2775*vr4100:
2776*vr5000:
2777{
ca971540 2778 check_u64 (SD_, instruction_0);
c906108c
SS		 2779 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2780}
2781
2782
27831111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2784"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2785*mipsII:
2786*mipsIII:
2787*mipsIV:
603a98e7 2788*mipsV:
1e799e28
CD		 2789*mips32:
2790*mips64:
c906108c
SS		 2791*vr4100:
2792*vr5000:
2793{
2794 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2795}
2796
2797
2798101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2799"sdl r<RT>, <OFFSET>(r<BASE>)"
2800*mipsIII:
2801*mipsIV:
603a98e7 2802*mipsV:
1e799e28 2803*mips64:
c906108c
SS		 2804*vr4100:
2805*vr5000:
2806{
ca971540 2807 check_u64 (SD_, instruction_0);
c906108c
SS		 2808 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2809}
2810
2811
2812101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2813"sdr r<RT>, <OFFSET>(r<BASE>)"
2814*mipsIII:
2815*mipsIV:
603a98e7 2816*mipsV:
1e799e28 2817*mips64:
c906108c
SS		 2818*vr4100:
2819*vr5000:
2820{
ca971540 2821 check_u64 (SD_, instruction_0);
c906108c
SS		 2822 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2823}
2824
2825
2826101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2827"sh r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2828*mipsI:
2829*mipsII:
2830*mipsIII:
2831*mipsIV:
603a98e7 2832*mipsV:
1e799e28
CD		 2833*mips32:
2834*mips64:
c906108c
SS		 2835*vr4100:
2836*vr5000:
2837*r3900:
2838{
2839 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2840}
2841
2842
2843:function:::void:do_sll:int rt, int rd, int shift
2844{
2845 unsigned32 temp = (GPR[rt] << shift);
2846 TRACE_ALU_INPUT2 (GPR[rt], shift);
2847 GPR[rd] = EXTEND32 (temp);
2848 TRACE_ALU_RESULT (GPR[rd]);
2849}
2850
1e799e28 2851000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
20ae0098 2852"nop":RD == 0 && RT == 0 && SHIFT == 0
c906108c 2853"sll r<RD>, r<RT>, <SHIFT>"
c5d00cc7
CD		 2854*mipsI:
2855*mipsII:
2856*mipsIII:
2857*mipsIV:
603a98e7 2858*mipsV:
c906108c
SS		 2859*vr4100:
2860*vr5000:
2861*r3900:
2862{
20ae0098
CD		 2863 /* Skip shift for NOP, so that there won't be lots of extraneous
2864 trace output. */
2865 if (RD != 0 || RT != 0 || SHIFT != 0)
2866 do_sll (SD_, RT, RD, SHIFT);
c906108c
SS		 2867}
2868
1e799e28
CD		 2869000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
2870"nop":RD == 0 && RT == 0 && SHIFT == 0
2871"ssnop":RD == 0 && RT == 0 && SHIFT == 1
2872"sll r<RD>, r<RT>, <SHIFT>"
2873*mips32:
2874*mips64:
2875{
2876 /* Skip shift for NOP and SSNOP, so that there won't be lots of
2877 extraneous trace output. */
2878 if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
2879 do_sll (SD_, RT, RD, SHIFT);
2880}
2881
c906108c
SS		 2882
2883:function:::void:do_sllv:int rs, int rt, int rd
2884{
2885 int s = MASKED (GPR[rs], 4, 0);
2886 unsigned32 temp = (GPR[rt] << s);
2887 TRACE_ALU_INPUT2 (GPR[rt], s);
2888 GPR[rd] = EXTEND32 (temp);
2889 TRACE_ALU_RESULT (GPR[rd]);
2890}
2891
f701dad2 2892000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
c906108c 2893"sllv r<RD>, r<RT>, r<RS>"
c5d00cc7
CD		 2894*mipsI:
2895*mipsII:
2896*mipsIII:
2897*mipsIV:
603a98e7 2898*mipsV:
1e799e28
CD		 2899*mips32:
2900*mips64:
c906108c
SS		 2901*vr4100:
2902*vr5000:
2903*r3900:
2904{
2905 do_sllv (SD_, RS, RT, RD);
2906}
2907
2908
2909:function:::void:do_slt:int rs, int rt, int rd
2910{
2911 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2912 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2913 TRACE_ALU_RESULT (GPR[rd]);
2914}
2915
f701dad2 2916000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
c906108c 2917"slt r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 2918*mipsI:
2919*mipsII:
2920*mipsIII:
2921*mipsIV:
603a98e7 2922*mipsV:
1e799e28
CD		 2923*mips32:
2924*mips64:
c906108c
SS		 2925*vr4100:
2926*vr5000:
2927*r3900:
2928{
2929 do_slt (SD_, RS, RT, RD);
2930}
2931
2932
2933:function:::void:do_slti:int rs, int rt, unsigned16 immediate
2934{
2935 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2936 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2937 TRACE_ALU_RESULT (GPR[rt]);
2938}
2939
2940001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2941"slti r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 2942*mipsI:
2943*mipsII:
2944*mipsIII:
2945*mipsIV:
603a98e7 2946*mipsV:
1e799e28
CD		 2947*mips32:
2948*mips64:
c906108c
SS		 2949*vr4100:
2950*vr5000:
2951*r3900:
2952{
2953 do_slti (SD_, RS, RT, IMMEDIATE);
2954}
2955
2956
2957:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2958{
2959 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2960 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2961 TRACE_ALU_RESULT (GPR[rt]);
2962}
2963
2964001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2965"sltiu r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 2966*mipsI:
2967*mipsII:
2968*mipsIII:
2969*mipsIV:
603a98e7 2970*mipsV:
1e799e28
CD		 2971*mips32:
2972*mips64:
c906108c
SS		 2973*vr4100:
2974*vr5000:
2975*r3900:
2976{
2977 do_sltiu (SD_, RS, RT, IMMEDIATE);
2978}
2979
2980
2981
2982:function:::void:do_sltu:int rs, int rt, int rd
2983{
2984 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2985 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2986 TRACE_ALU_RESULT (GPR[rd]);
2987}
2988
f701dad2 2989000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
c906108c 2990"sltu r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 2991*mipsI:
2992*mipsII:
2993*mipsIII:
2994*mipsIV:
603a98e7 2995*mipsV:
1e799e28
CD		 2996*mips32:
2997*mips64:
c906108c
SS		 2998*vr4100:
2999*vr5000:
3000*r3900:
3001{
3002 do_sltu (SD_, RS, RT, RD);
3003}
3004
3005
3006:function:::void:do_sra:int rt, int rd, int shift
3007{
3008 signed32 temp = (signed32) GPR[rt] >> shift;
402586aa
CD		 3009 if (NotWordValue (GPR[rt]))
3010 Unpredictable ();
c906108c
SS		 3011 TRACE_ALU_INPUT2 (GPR[rt], shift);
3012 GPR[rd] = EXTEND32 (temp);
3013 TRACE_ALU_RESULT (GPR[rd]);
3014}
3015
3016000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3017"sra r<RD>, r<RT>, <SHIFT>"
c5d00cc7
CD		 3018*mipsI:
3019*mipsII:
3020*mipsIII:
3021*mipsIV:
603a98e7 3022*mipsV:
1e799e28
CD		 3023*mips32:
3024*mips64:
c906108c
SS		 3025*vr4100:
3026*vr5000:
3027*r3900:
3028{
3029 do_sra (SD_, RT, RD, SHIFT);
3030}
3031
3032
3033
3034:function:::void:do_srav:int rs, int rt, int rd
3035{
3036 int s = MASKED (GPR[rs], 4, 0);
3037 signed32 temp = (signed32) GPR[rt] >> s;
402586aa
CD		 3038 if (NotWordValue (GPR[rt]))
3039 Unpredictable ();
c906108c
SS		 3040 TRACE_ALU_INPUT2 (GPR[rt], s);
3041 GPR[rd] = EXTEND32 (temp);
3042 TRACE_ALU_RESULT (GPR[rd]);
3043}
3044
f701dad2 3045000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
c906108c 3046"srav r<RD>, r<RT>, r<RS>"
c5d00cc7
CD		 3047*mipsI:
3048*mipsII:
3049*mipsIII:
3050*mipsIV:
603a98e7 3051*mipsV:
1e799e28
CD		 3052*mips32:
3053*mips64:
c906108c
SS		 3054*vr4100:
3055*vr5000:
3056*r3900:
3057{
3058 do_srav (SD_, RS, RT, RD);
3059}
3060
3061
3062
3063:function:::void:do_srl:int rt, int rd, int shift
3064{
3065 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
402586aa
CD		 3066 if (NotWordValue (GPR[rt]))
3067 Unpredictable ();
c906108c
SS		 3068 TRACE_ALU_INPUT2 (GPR[rt], shift);
3069 GPR[rd] = EXTEND32 (temp);
3070 TRACE_ALU_RESULT (GPR[rd]);
3071}
3072
3073000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3074"srl r<RD>, r<RT>, <SHIFT>"
c5d00cc7
CD		 3075*mipsI:
3076*mipsII:
3077*mipsIII:
3078*mipsIV:
603a98e7 3079*mipsV:
1e799e28
CD		 3080*mips32:
3081*mips64:
c906108c
SS		 3082*vr4100:
3083*vr5000:
3084*r3900:
3085{
3086 do_srl (SD_, RT, RD, SHIFT);
3087}
3088
3089
3090:function:::void:do_srlv:int rs, int rt, int rd
3091{
3092 int s = MASKED (GPR[rs], 4, 0);
3093 unsigned32 temp = (unsigned32) GPR[rt] >> s;
402586aa
CD		 3094 if (NotWordValue (GPR[rt]))
3095 Unpredictable ();
c906108c
SS		 3096 TRACE_ALU_INPUT2 (GPR[rt], s);
3097 GPR[rd] = EXTEND32 (temp);
3098 TRACE_ALU_RESULT (GPR[rd]);
3099}
3100
f701dad2 3101000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
c906108c 3102"srlv r<RD>, r<RT>, r<RS>"
c5d00cc7
CD		 3103*mipsI:
3104*mipsII:
3105*mipsIII:
3106*mipsIV:
603a98e7 3107*mipsV:
1e799e28
CD		 3108*mips32:
3109*mips64:
c906108c
SS		 3110*vr4100:
3111*vr5000:
3112*r3900:
3113{
3114 do_srlv (SD_, RS, RT, RD);
3115}
3116
3117
f701dad2 3118000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
c906108c 3119"sub r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 3120*mipsI:
3121*mipsII:
3122*mipsIII:
3123*mipsIV:
603a98e7 3124*mipsV:
1e799e28
CD		 3125*mips32:
3126*mips64:
c906108c
SS		 3127*vr4100:
3128*vr5000:
3129*r3900:
3130{
402586aa
CD		 3131 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3132 Unpredictable ();
c906108c
SS		 3133 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3134 {
3135 ALU32_BEGIN (GPR[RS]);
3136 ALU32_SUB (GPR[RT]);
9805e229 3137 ALU32_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 3138 }
3139 TRACE_ALU_RESULT (GPR[RD]);
3140}
3141
3142
3143:function:::void:do_subu:int rs, int rt, int rd
3144{
402586aa
CD		 3145 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3146 Unpredictable ();
c906108c
SS		 3147 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3148 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3149 TRACE_ALU_RESULT (GPR[rd]);
3150}
3151
f701dad2 3152000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
c906108c 3153"subu r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 3154*mipsI:
3155*mipsII:
3156*mipsIII:
3157*mipsIV:
603a98e7 3158*mipsV:
1e799e28
CD		 3159*mips32:
3160*mips64:
c906108c
SS		 3161*vr4100:
3162*vr5000:
3163*r3900:
3164{
3165 do_subu (SD_, RS, RT, RD);
3166}
3167
3168
3169101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3170"sw r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3171*mipsI:
3172*mipsII:
3173*mipsIII:
3174*mipsIV:
603a98e7 3175*mipsV:
1e799e28
CD		 3176*mips32:
3177*mips64:
c906108c
SS		 3178*vr4100:
3179*r3900:
3180*vr5000:
3181{
3182 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3183}
3184
3185
31861110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3187"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3188*mipsI:
3189*mipsII:
3190*mipsIII:
3191*mipsIV:
603a98e7 3192*mipsV:
1e799e28
CD		 3193*mips32:
3194*mips64:
c906108c
SS		 3195*vr4100:
3196*vr5000:
3197*r3900:
3198{
3199 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3200}
3201
3202
c906108c
SS		 3203101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3204"swl r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3205*mipsI:
3206*mipsII:
3207*mipsIII:
3208*mipsIV:
603a98e7 3209*mipsV:
1e799e28
CD		 3210*mips32:
3211*mips64:
c906108c
SS		 3212*vr4100:
3213*vr5000:
3214*r3900:
3215{
3216 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3217}
3218
3219
c906108c
SS		 3220101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3221"swr r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3222*mipsI:
3223*mipsII:
3224*mipsIII:
3225*mipsIV:
603a98e7 3226*mipsV:
1e799e28
CD		 3227*mips32:
3228*mips64:
c906108c
SS		 3229*vr4100:
3230*vr5000:
3231*r3900:
3232{
3233 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3234}
3235
3236
f701dad2 3237000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
c906108c
SS		 3238"sync":STYPE == 0
3239"sync <STYPE>"
3240*mipsII:
3241*mipsIII:
3242*mipsIV:
603a98e7 3243*mipsV:
1e799e28
CD		 3244*mips32:
3245*mips64:
c906108c
SS		 3246*vr4100:
3247*vr5000:
3248*r3900:
3249{
3250 SyncOperation (STYPE);
3251}
3252
3253
3254000000,20.CODE,001100:SPECIAL:32::SYSCALL
82f728db 3255"syscall %#lx<CODE>"
c5d00cc7
CD		 3256*mipsI:
3257*mipsII:
3258*mipsIII:
3259*mipsIV:
603a98e7 3260*mipsV:
1e799e28
CD		 3261*mips32:
3262*mips64:
c906108c
SS		 3263*vr4100:
3264*vr5000:
3265*r3900:
3266{
86b77b47 3267 SignalException (SystemCall, instruction_0);
c906108c
SS		 3268}
3269
3270
3271000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3272"teq r<RS>, r<RT>"
3273*mipsII:
3274*mipsIII:
3275*mipsIV:
603a98e7 3276*mipsV:
1e799e28
CD		 3277*mips32:
3278*mips64:
c906108c
SS		 3279*vr4100:
3280*vr5000:
3281{
3282 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
86b77b47 3283 SignalException (Trap, instruction_0);
c906108c
SS		 3284}
3285
3286
3287000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3288"teqi r<RS>, <IMMEDIATE>"
3289*mipsII:
3290*mipsIII:
3291*mipsIV:
603a98e7 3292*mipsV:
1e799e28
CD		 3293*mips32:
3294*mips64:
c906108c
SS		 3295*vr4100:
3296*vr5000:
3297{
3298 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
86b77b47 3299 SignalException (Trap, instruction_0);
c906108c
SS		 3300}
3301
3302
3303000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3304"tge r<RS>, r<RT>"
3305*mipsII:
3306*mipsIII:
3307*mipsIV:
603a98e7 3308*mipsV:
1e799e28
CD		 3309*mips32:
3310*mips64:
c906108c
SS		 3311*vr4100:
3312*vr5000:
3313{
3314 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
86b77b47 3315 SignalException (Trap, instruction_0);
c906108c
SS		 3316}
3317
3318
3319000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3320"tgei r<RS>, <IMMEDIATE>"
3321*mipsII:
3322*mipsIII:
3323*mipsIV:
603a98e7 3324*mipsV:
1e799e28
CD		 3325*mips32:
3326*mips64:
c906108c
SS		 3327*vr4100:
3328*vr5000:
3329{
3330 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
86b77b47 3331 SignalException (Trap, instruction_0);
c906108c
SS		 3332}
3333
3334
3335000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3336"tgeiu r<RS>, <IMMEDIATE>"
3337*mipsII:
3338*mipsIII:
3339*mipsIV:
603a98e7 3340*mipsV:
1e799e28
CD		 3341*mips32:
3342*mips64:
c906108c
SS		 3343*vr4100:
3344*vr5000:
3345{
3346 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
86b77b47 3347 SignalException (Trap, instruction_0);
c906108c
SS		 3348}
3349
3350
3351000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3352"tgeu r<RS>, r<RT>"
3353*mipsII:
3354*mipsIII:
3355*mipsIV:
603a98e7 3356*mipsV:
1e799e28
CD		 3357*mips32:
3358*mips64:
c906108c
SS		 3359*vr4100:
3360*vr5000:
3361{
3362 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
86b77b47 3363 SignalException (Trap, instruction_0);
c906108c
SS		 3364}
3365
3366
3367000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3368"tlt r<RS>, r<RT>"
3369*mipsII:
3370*mipsIII:
3371*mipsIV:
603a98e7 3372*mipsV:
1e799e28
CD		 3373*mips32:
3374*mips64:
c906108c
SS		 3375*vr4100:
3376*vr5000:
3377{
3378 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
86b77b47 3379 SignalException (Trap, instruction_0);
c906108c
SS		 3380}
3381
3382
3383000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3384"tlti r<RS>, <IMMEDIATE>"
3385*mipsII:
3386*mipsIII:
3387*mipsIV:
603a98e7 3388*mipsV:
1e799e28
CD		 3389*mips32:
3390*mips64:
c906108c
SS		 3391*vr4100:
3392*vr5000:
3393{
3394 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
86b77b47 3395 SignalException (Trap, instruction_0);
c906108c
SS		 3396}
3397
3398
3399000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3400"tltiu r<RS>, <IMMEDIATE>"
3401*mipsII:
3402*mipsIII:
3403*mipsIV:
603a98e7 3404*mipsV:
1e799e28
CD		 3405*mips32:
3406*mips64:
c906108c
SS		 3407*vr4100:
3408*vr5000:
3409{
3410 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
86b77b47 3411 SignalException (Trap, instruction_0);
c906108c
SS		 3412}
3413
3414
3415000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3416"tltu r<RS>, r<RT>"
3417*mipsII:
3418*mipsIII:
3419*mipsIV:
603a98e7 3420*mipsV:
1e799e28
CD		 3421*mips32:
3422*mips64:
c906108c
SS		 3423*vr4100:
3424*vr5000:
3425{
3426 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
86b77b47 3427 SignalException (Trap, instruction_0);
c906108c
SS		 3428}
3429
3430
3431000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3432"tne r<RS>, r<RT>"
3433*mipsII:
3434*mipsIII:
3435*mipsIV:
603a98e7 3436*mipsV:
1e799e28
CD		 3437*mips32:
3438*mips64:
c906108c
SS		 3439*vr4100:
3440*vr5000:
3441{
3442 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
86b77b47 3443 SignalException (Trap, instruction_0);
c906108c
SS		 3444}
3445
3446
3447000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
95fd5cee 3448"tnei r<RS>, <IMMEDIATE>"
c906108c
SS		 3449*mipsII:
3450*mipsIII:
3451*mipsIV:
603a98e7 3452*mipsV:
1e799e28
CD		 3453*mips32:
3454*mips64:
c906108c
SS		 3455*vr4100:
3456*vr5000:
3457{
3458 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
86b77b47 3459 SignalException (Trap, instruction_0);
c906108c
SS		 3460}
3461
3462
3463:function:::void:do_xor:int rs, int rt, int rd
3464{
3465 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3466 GPR[rd] = GPR[rs] ^ GPR[rt];
3467 TRACE_ALU_RESULT (GPR[rd]);
3468}
3469
f701dad2 3470000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
c906108c 3471"xor r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 3472*mipsI:
3473*mipsII:
3474*mipsIII:
3475*mipsIV:
603a98e7 3476*mipsV:
1e799e28
CD		 3477*mips32:
3478*mips64:
c906108c
SS		 3479*vr4100:
3480*vr5000:
3481*r3900:
3482{
3483 do_xor (SD_, RS, RT, RD);
3484}
3485
3486
3487:function:::void:do_xori:int rs, int rt, unsigned16 immediate
3488{
3489 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3490 GPR[rt] = GPR[rs] ^ immediate;
3491 TRACE_ALU_RESULT (GPR[rt]);
3492}
3493
3494001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
82f728db 3495"xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
c5d00cc7
CD		 3496*mipsI:
3497*mipsII:
3498*mipsIII:
3499*mipsIV:
603a98e7 3500*mipsV:
1e799e28
CD		 3501*mips32:
3502*mips64:
c906108c
SS		 3503*vr4100:
3504*vr5000:
3505*r3900:
3506{
3507 do_xori (SD_, RS, RT, IMMEDIATE);
3508}
3509
3510\f
3511//
3512// MIPS Architecture:
3513//
3514// FPU Instruction Set (COP1 & COP1X)
3515//
3516
3517
3518:%s::::FMT:int fmt
3519{
3520 switch (fmt)
3521 {
3522 case fmt_single: return "s";
3523 case fmt_double: return "d";
3524 case fmt_word: return "w";
3525 case fmt_long: return "l";
3a2b820e 3526 case fmt_ps: return "ps";
c906108c
SS		 3527 default: return "?";
3528 }
3529}
3530
c906108c
SS		 3531:%s::::TF:int tf
3532{
3533 if (tf)
3534 return "t";
3535 else
3536 return "f";
3537}
3538
3539:%s::::ND:int nd
3540{
3541 if (nd)
3542 return "l";
3543 else
3544 return "";
3545}
3546
3547:%s::::COND:int cond
3548{
3549 switch (cond)
3550 {
3551 case 00: return "f";
3552 case 01: return "un";
3553 case 02: return "eq";
3554 case 03: return "ueq";
3555 case 04: return "olt";
3556 case 05: return "ult";
3557 case 06: return "ole";
3558 case 07: return "ule";
3559 case 010: return "sf";
3560 case 011: return "ngle";
3561 case 012: return "seq";
3562 case 013: return "ngl";
3563 case 014: return "lt";
3564 case 015: return "nge";
3565 case 016: return "le";
3566 case 017: return "ngt";
3567 default: return "?";
3568 }
3569}
3570
8612006b
CD		 3571
3572// Helpers:
3573//
3574// Check that the given FPU format is usable, and signal a
3575// ReservedInstruction exception if not.
3576//
3577
3578// check_fmt checks that the format is single or double.
3579:function:::void:check_fmt:int fmt, instruction_word insn
3580*mipsI:
3581*mipsII:
3582*mipsIII:
3583*mipsIV:
3584*mipsV:
1e799e28
CD		 3585*mips32:
3586*mips64:
8612006b
CD		 3587*vr4100:
3588*vr5000:
3589*r3900:
3590{
3591 if ((fmt != fmt_single) && (fmt != fmt_double))
3592 SignalException (ReservedInstruction, insn);
3593}
3594
3595// check_fmt_p checks that the format is single, double, or paired single.
3596:function:::void:check_fmt_p:int fmt, instruction_word insn
3597*mipsI:
3598*mipsII:
3599*mipsIII:
3600*mipsIV:
1e799e28 3601*mips32:
8612006b
CD		 3602*vr4100:
3603*vr5000:
3604*r3900:
3605{
3606 /* None of these ISAs support Paired Single, so just fall back to
3607 the single/double check. */
8612006b
CD		 3608 check_fmt (SD_, fmt, insn);
3609}
3610
1e799e28
CD		 3611:function:::void:check_fmt_p:int fmt, instruction_word insn
3612*mipsV:
3613*mips64:
3614{
1e799e28
CD		 3615 if ((fmt != fmt_single) && (fmt != fmt_double)
3616 && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3617 SignalException (ReservedInstruction, insn);
1e799e28
CD		 3618}
3619
8612006b 3620
ca971540 3621// Helper:
4a0bd876 3622//
ca971540
CD		 3623// Check that the FPU is currently usable, and signal a CoProcessorUnusable
3624// exception if not.
3625//
3626
3627:function:::void:check_fpu:
4a0bd876 3628*mipsI:
ca971540
CD		 3629*mipsII:
3630*mipsIII:
3631*mipsIV:
3632*mipsV:
1e799e28
CD		 3633*mips32:
3634*mips64:
ca971540
CD		 3635*vr4100:
3636*vr5000:
3637*r3900:
3638{
ca971540
CD		 3639 if (! COP_Usable (1))
3640 SignalExceptionCoProcessorUnusable (1);
ca971540
CD		 3641}
3642
c906108c 3643
06e7837e
CD		 3644// Helper:
3645//
3646// Load a double word FP value using 2 32-bit memory cycles a la MIPS II
3647// or MIPS32. do_load cannot be used instead because it returns an
3648// unsigned_word, which is limited to the size of the machine's registers.
3649//
3650
3651:function:::unsigned64:do_load_double:address_word base, address_word offset
3652*mipsII:
3653*mips32:
3654{
3655 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
3656 address_word vaddr;
3657 address_word paddr;
3658 int uncached;
3659 unsigned64 memval;
3660 unsigned64 v;
3661
3662 vaddr = loadstore_ea (SD_, base, offset);
3663 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
3664 {
3665 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
3666 AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
3667 sim_core_unaligned_signal);
3668 }
3669 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
3670 isREAL);
3671 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
3672 isDATA, isREAL);
3673 v = (unsigned64)memval;
3674 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
3675 isDATA, isREAL);
3676 return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
3677}
3678
3679
3680// Helper:
3681//
3682// Store a double word FP value using 2 32-bit memory cycles a la MIPS II
3683// or MIPS32. do_load cannot be used instead because it returns an
3684// unsigned_word, which is limited to the size of the machine's registers.
3685//
3686
3687:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
3688*mipsII:
3689*mips32:
3690{
3691 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
3692 address_word vaddr;
3693 address_word paddr;
3694 int uncached;
3695 unsigned64 memval;
3696
3697 vaddr = loadstore_ea (SD_, base, offset);
3698 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
3699 {
3700 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
3701 AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
3702 sim_core_unaligned_signal);
3703 }
3704 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
3705 isREAL);
3706 memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
3707 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
3708 isREAL);
3709 memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
3710 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
3711 isREAL);
3712}
3713
3714
c906108c
SS		 3715010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3716"abs.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 3717*mipsI:
3718*mipsII:
3719*mipsIII:
3720*mipsIV:
603a98e7 3721*mipsV:
1e799e28
CD		 3722*mips32:
3723*mips64:
c906108c
SS		 3724*vr4100:
3725*vr5000:
3726*r3900:
3727{
c1e8ada4 3728 int fmt = FMT;
9b17d183 3729 check_fpu (SD_);
8612006b 3730 check_fmt_p (SD_, fmt, instruction_0);
d18ea9c2 3731 StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
c906108c
SS		 3732}
3733
3734
3735
3736010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3737"add.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 3738*mipsI:
3739*mipsII:
3740*mipsIII:
3741*mipsIV:
603a98e7 3742*mipsV:
1e799e28
CD		 3743*mips32:
3744*mips64:
c906108c
SS		 3745*vr4100:
3746*vr5000:
3747*r3900:
3748{
c1e8ada4 3749 int fmt = FMT;
9b17d183 3750 check_fpu (SD_);
8612006b 3751 check_fmt_p (SD_, fmt, instruction_0);
d18ea9c2 3752 StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
c906108c
SS		 3753}
3754
3755
3a2b820e
CD		 3756010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
3757"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
3758*mipsV:
3759*mips64:
3760{
3761 unsigned64 fs;
3762 unsigned64 ft;
3763 unsigned64 fd;
3764 check_fpu (SD_);
3765 check_u64 (SD_, instruction_0);
3766 fs = ValueFPR (FS, fmt_ps);
3767 if ((GPR[RS] & 0x3) != 0)
3768 Unpredictable ();
3769 if ((GPR[RS] & 0x4) == 0)
3770 fd = fs;
3771 else
3772 {
3773 ft = ValueFPR (FT, fmt_ps);
3774 if (BigEndianCPU)
3775 fd = PackPS (PSLower (fs), PSUpper (ft));
3776 else
3777 fd = PackPS (PSLower (ft), PSUpper (fs));
3778 }
3779 StoreFPR (FD, fmt_ps, fd);
3780}
3781
c906108c
SS		 3782
3783// BC1F
3784// BC1FL
3785// BC1T
3786// BC1TL
3787
3788010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3789"bc1%s<TF>%s<ND> <OFFSET>"
c5d00cc7
CD		 3790*mipsI:
3791*mipsII:
3792*mipsIII:
c906108c 3793{
9b17d183 3794 check_fpu (SD_);
c906108c
SS		 3795 check_branch_bug ();
3796 TRACE_BRANCH_INPUT (PREVCOC1());
3797 if (PREVCOC1() == TF)
3798 {
3799 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3800 TRACE_BRANCH_RESULT (dest);
3801 mark_branch_bug (dest);
3802 DELAY_SLOT (dest);
3803 }
3804 else if (ND)
3805 {
3806 TRACE_BRANCH_RESULT (0);
3807 NULLIFY_NEXT_INSTRUCTION ();
3808 }
3809 else
3810 {
3811 TRACE_BRANCH_RESULT (NIA);
3812 }
3813}
3814
3815010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3816"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3817"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3818*mipsIV:
603a98e7 3819*mipsV:
1e799e28
CD		 3820*mips32:
3821*mips64:
c906108c 3822#*vr4100:
074e9cb8 3823*vr5000:
c906108c
SS		 3824*r3900:
3825{
9b17d183 3826 check_fpu (SD_);
c906108c
SS		 3827 check_branch_bug ();
3828 if (GETFCC(CC) == TF)
3829 {
3830 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3831 mark_branch_bug (dest);
3832 DELAY_SLOT (dest);
3833 }
3834 else if (ND)
3835 {
3836 NULLIFY_NEXT_INSTRUCTION ();
3837 }
3838}
3839
3840
eb5fcf93 3841010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
c906108c 3842"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
c5d00cc7
CD		 3843*mipsI:
3844*mipsII:
3845*mipsIII:
c906108c 3846{
8612006b 3847 int fmt = FMT;
9b17d183 3848 check_fpu (SD_);
8612006b 3849 check_fmt_p (SD_, fmt, instruction_0);
cfe9ea23
CD		 3850 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
3851 TRACE_ALU_RESULT (ValueFCR (31));
c906108c
SS		 3852}
3853
eb5fcf93 3854010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
c906108c
SS		 3855"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3856"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3857*mipsIV:
603a98e7 3858*mipsV:
1e799e28
CD		 3859*mips32:
3860*mips64:
c906108c
SS		 3861*vr4100:
3862*vr5000:
3863*r3900:
3864{
8612006b 3865 int fmt = FMT;
9b17d183 3866 check_fpu (SD_);
8612006b 3867 check_fmt_p (SD_, fmt, instruction_0);
cfe9ea23
CD		 3868 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
3869 TRACE_ALU_RESULT (ValueFCR (31));
c906108c
SS		 3870}
3871
3872
eb5fcf93 3873010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
c906108c
SS		 3874"ceil.l.%s<FMT> f<FD>, f<FS>"
3875*mipsIII:
3876*mipsIV:
603a98e7 3877*mipsV:
1e799e28 3878*mips64:
c906108c
SS		 3879*vr4100:
3880*vr5000:
3881*r3900:
3882{
c1e8ada4 3883 int fmt = FMT;
9b17d183 3884 check_fpu (SD_);
8612006b 3885 check_fmt (SD_, fmt, instruction_0);
d18ea9c2
CD		 3886 StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3887 fmt_long));
c906108c
SS		 3888}
3889
3890
eb5fcf93 3891010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
95fd5cee 3892"ceil.w.%s<FMT> f<FD>, f<FS>"
c906108c
SS		 3893*mipsII:
3894*mipsIII:
3895*mipsIV:
603a98e7 3896*mipsV:
1e799e28
CD		 3897*mips32:
3898*mips64:
c906108c
SS		 3899*vr4100:
3900*vr5000:
3901*r3900:
3902{
c1e8ada4 3903 int fmt = FMT;
9b17d183 3904 check_fpu (SD_);
8612006b 3905 check_fmt (SD_, fmt, instruction_0);
d18ea9c2
CD		 3906 StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3907 fmt_word));
c906108c
SS		 3908}
3909
3910
cfe9ea23
CD		 3911010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
3912"cfc1 r<RT>, f<FS>"
c906108c
SS		 3913*mipsI:
3914*mipsII:
3915*mipsIII:
3916{
9b17d183 3917 check_fpu (SD_);
cfe9ea23
CD		 3918 if (FS == 0)
3919 PENDING_FILL (RT, EXTEND32 (FCR0));
3920 else if (FS == 31)
3921 PENDING_FILL (RT, EXTEND32 (FCR31));
3922 /* else NOP */
3923}
3924
3925010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
3926"cfc1 r<RT>, f<FS>"
3927*mipsIV:
3928*vr4100:
3929*vr5000:
3930*r3900:
3931{
3932 check_fpu (SD_);
3933 if (FS == 0 || FS == 31)
c906108c 3934 {
cfe9ea23
CD		 3935 unsigned_word fcr = ValueFCR (FS);
3936 TRACE_ALU_INPUT1 (fcr);
3937 GPR[RT] = fcr;
c906108c 3938 }
cfe9ea23
CD		 3939 /* else NOP */
3940 TRACE_ALU_RESULT (GPR[RT]);
c906108c 3941}
cfe9ea23
CD		 3942
3943010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
3944"cfc1 r<RT>, f<FS>"
603a98e7 3945*mipsV:
1e799e28
CD		 3946*mips32:
3947*mips64:
cfe9ea23
CD		 3948{
3949 check_fpu (SD_);
3950 if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
3951 {
3952 unsigned_word fcr = ValueFCR (FS);
3953 TRACE_ALU_INPUT1 (fcr);
3954 GPR[RT] = fcr;
3955 }
3956 /* else NOP */
3957 TRACE_ALU_RESULT (GPR[RT]);
3958}
3959
3960010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
3961"ctc1 r<RT>, f<FS>"
3962*mipsI:
3963*mipsII:
3964*mipsIII:
3965{
3966 check_fpu (SD_);
3967 if (FS == 31)
3968 PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
3969 /* else NOP */
3970}
3971
3972010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
3973"ctc1 r<RT>, f<FS>"
3974*mipsIV:
c906108c
SS		 3975*vr4100:
3976*vr5000:
3977*r3900:
3978{
9b17d183 3979 check_fpu (SD_);
cfe9ea23
CD		 3980 TRACE_ALU_INPUT1 (GPR[RT]);
3981 if (FS == 31)
3982 StoreFCR (FS, GPR[RT]);
3983 /* else NOP */
3984}
3985
3986010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
3987"ctc1 r<RT>, f<FS>"
3988*mipsV:
3989*mips32:
3990*mips64:
3991{
3992 check_fpu (SD_);
3993 TRACE_ALU_INPUT1 (GPR[RT]);
3994 if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
3995 StoreFCR (FS, GPR[RT]);
3996 /* else NOP */
c906108c
SS		 3997}
3998
3999
4000//
4001// FIXME: Does not correctly differentiate between mips*
4002//
eb5fcf93 4003010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
c906108c 4004"cvt.d.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 4005*mipsI:
4006*mipsII:
4007*mipsIII:
4008*mipsIV:
603a98e7 4009*mipsV:
1e799e28
CD		 4010*mips32:
4011*mips64:
c906108c
SS		 4012*vr4100:
4013*vr5000:
4014*r3900:
4015{
c1e8ada4 4016 int fmt = FMT;
9b17d183 4017 check_fpu (SD_);
d18ea9c2
CD		 4018 if ((fmt == fmt_double) | 0)
4019 SignalException (ReservedInstruction, instruction_0);
4020 StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4021 fmt_double));
c906108c
SS		 4022}
4023
4024
eb5fcf93 4025010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
c906108c
SS		 4026"cvt.l.%s<FMT> f<FD>, f<FS>"
4027*mipsIII:
4028*mipsIV:
603a98e7 4029*mipsV:
1e799e28 4030*mips64:
c906108c
SS		 4031*vr4100:
4032*vr5000:
4033*r3900:
4034{
c1e8ada4 4035 int fmt = FMT;
9b17d183 4036 check_fpu (SD_);
d18ea9c2
CD		 4037 if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
4038 SignalException (ReservedInstruction, instruction_0);
4039 StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4040 fmt_long));
c906108c
SS		 4041}
4042
4043
3a2b820e
CD		 4044010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
4045"cvt.ps.s f<FD>, f<FS>, f<FT>"
4046*mipsV:
4047*mips64:
4048{
4049 check_fpu (SD_);
4050 check_u64 (SD_, instruction_0);
4051 StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
4052 ValueFPR (FT, fmt_single)));
4053}
4054
4055
c906108c
SS		 4056//
4057// FIXME: Does not correctly differentiate between mips*
4058//
3a2b820e 4059010001,10,3.FMT!6,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
c906108c 4060"cvt.s.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 4061*mipsI:
4062*mipsII:
4063*mipsIII:
4064*mipsIV:
603a98e7 4065*mipsV:
1e799e28
CD		 4066*mips32:
4067*mips64:
c906108c
SS		 4068*vr4100:
4069*vr5000:
4070*r3900:
4071{
c1e8ada4 4072 int fmt = FMT;
9b17d183 4073 check_fpu (SD_);
d18ea9c2
CD		 4074 if ((fmt == fmt_single) | 0)
4075 SignalException (ReservedInstruction, instruction_0);
4076 StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4077 fmt_single));
c906108c
SS		 4078}
4079
4080
3a2b820e
CD		 4081010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4082"cvt.s.pl f<FD>, f<FS>"
4083*mipsV:
4084*mips64:
4085{
4086 check_fpu (SD_);
4087 check_u64 (SD_, instruction_0);
4088 StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4089}
4090
4091
4092010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4093"cvt.s.pu f<FD>, f<FS>"
4094*mipsV:
4095*mips64:
4096{
4097 check_fpu (SD_);
4098 check_u64 (SD_, instruction_0);
4099 StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4100}
4101
4102
e7e81181 4103010001,10,3.FMT!6,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
c906108c 4104"cvt.w.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 4105*mipsI:
4106*mipsII:
4107*mipsIII:
4108*mipsIV:
603a98e7 4109*mipsV:
1e799e28
CD		 4110*mips32:
4111*mips64:
c906108c
SS		 4112*vr4100:
4113*vr5000:
4114*r3900:
4115{
c1e8ada4 4116 int fmt = FMT;
9b17d183 4117 check_fpu (SD_);
d18ea9c2
CD		 4118 if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4119 SignalException (ReservedInstruction, instruction_0);
4120 StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4121 fmt_word));
c906108c
SS		 4122}
4123
4124
eb5fcf93 4125010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
c906108c 4126"div.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 4127*mipsI:
4128*mipsII:
4129*mipsIII:
4130*mipsIV:
603a98e7 4131*mipsV:
1e799e28
CD		 4132*mips32:
4133*mips64:
c906108c
SS		 4134*vr4100:
4135*vr5000:
4136*r3900:
4137{
c1e8ada4 4138 int fmt = FMT;
9b17d183 4139 check_fpu (SD_);
8612006b 4140 check_fmt (SD_, fmt, instruction_0);
d18ea9c2 4141 StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
c906108c
SS		 4142}
4143
4144
cfe9ea23
CD		 4145010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4146"dmfc1 r<RT>, f<FS>"
c906108c
SS		 4147*mipsIII:
4148{
cfe9ea23 4149 unsigned64 v;
9b17d183 4150 check_fpu (SD_);
ca971540 4151 check_u64 (SD_, instruction_0);
cfe9ea23
CD		 4152 if (SizeFGR () == 64)
4153 v = FGR[FS];
4154 else if ((FS & 0x1) == 0)
4155 v = SET64HI (FGR[FS+1]) | FGR[FS];
c906108c 4156 else
cfe9ea23
CD		 4157 v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4158 PENDING_FILL (RT, v);
4159 TRACE_ALU_RESULT (v);
c906108c 4160}
cfe9ea23
CD		 4161
4162010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4163"dmfc1 r<RT>, f<FS>"
c906108c 4164*mipsIV:
603a98e7 4165*mipsV:
1e799e28 4166*mips64:
c906108c
SS		 4167*vr4100:
4168*vr5000:
4169*r3900:
4170{
9b17d183 4171 check_fpu (SD_);
ca971540 4172 check_u64 (SD_, instruction_0);
cfe9ea23
CD		 4173 if (SizeFGR () == 64)
4174 GPR[RT] = FGR[FS];
4175 else if ((FS & 0x1) == 0)
4176 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
c906108c 4177 else
cfe9ea23
CD		 4178 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4179 TRACE_ALU_RESULT (GPR[RT]);
4180}
4181
4182
4183010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4184"dmtc1 r<RT>, f<FS>"
4185*mipsIII:
4186{
4187 unsigned64 v;
4188 check_fpu (SD_);
4189 check_u64 (SD_, instruction_0);
4190 if (SizeFGR () == 64)
4191 PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4192 else if ((FS & 0x1) == 0)
c906108c 4193 {
cfe9ea23
CD		 4194 PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4195 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
c906108c 4196 }
cfe9ea23
CD		 4197 else
4198 Unpredictable ();
4199 TRACE_FP_RESULT (GPR[RT]);
4200}
4201
4202010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4203"dmtc1 r<RT>, f<FS>"
4204*mipsIV:
4205*mipsV:
4206*mips64:
4207*vr4100:
4208*vr5000:
4209*r3900:
4210{
4211 check_fpu (SD_);
4212 check_u64 (SD_, instruction_0);
4213 if (SizeFGR () == 64)
4214 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4215 else if ((FS & 0x1) == 0)
4216 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4217 else
4218 Unpredictable ();
c906108c
SS		 4219}
4220
4221
eb5fcf93 4222010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
c906108c
SS		 4223"floor.l.%s<FMT> f<FD>, f<FS>"
4224*mipsIII:
4225*mipsIV:
603a98e7 4226*mipsV:
1e799e28 4227*mips64:
c906108c
SS		 4228*vr4100:
4229*vr5000:
4230*r3900:
4231{
c1e8ada4 4232 int fmt = FMT;
9b17d183 4233 check_fpu (SD_);
8612006b 4234 check_fmt (SD_, fmt, instruction_0);
d18ea9c2
CD		 4235 StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4236 fmt_long));
c906108c
SS		 4237}
4238
4239
eb5fcf93 4240010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
c906108c
SS		 4241"floor.w.%s<FMT> f<FD>, f<FS>"
4242*mipsII:
4243*mipsIII:
4244*mipsIV:
603a98e7 4245*mipsV:
1e799e28
CD		 4246*mips32:
4247*mips64:
c906108c
SS		 4248*vr4100:
4249*vr5000:
4250*r3900:
4251{
c1e8ada4 4252 int fmt = FMT;
9b17d183 4253 check_fpu (SD_);
8612006b 4254 check_fmt (SD_, fmt, instruction_0);
d18ea9c2
CD		 4255 StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4256 fmt_word));
c906108c
SS		 4257}
4258
4259
06e7837e 4260110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
c906108c
SS		 4261"ldc1 f<FT>, <OFFSET>(r<BASE>)"
4262*mipsII:
06e7837e
CD		 4263*mips32:
4264{
4265 check_fpu (SD_);
4266 COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
4267}
4268
4269
4270110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
4271"ldc1 f<FT>, <OFFSET>(r<BASE>)"
c906108c
SS		 4272*mipsIII:
4273*mipsIV:
603a98e7 4274*mipsV:
1e799e28 4275*mips64:
c906108c
SS		 4276*vr4100:
4277*vr5000:
4278*r3900:
4279{
9b17d183 4280 check_fpu (SD_);
c906108c
SS		 4281 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4282}
4283
4284
eb5fcf93 4285010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
c906108c
SS		 4286"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4287*mipsIV:
603a98e7 4288*mipsV:
1e799e28 4289*mips64:
c906108c
SS		 4290*vr5000:
4291{
9b17d183 4292 check_fpu (SD_);
ca971540 4293 check_u64 (SD_, instruction_0);
c906108c
SS		 4294 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4295}
4296
4297
4298
4a0bd876 4299110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
c906108c 4300"lwc1 f<FT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 4301*mipsI:
4302*mipsII:
4303*mipsIII:
4304*mipsIV:
603a98e7 4305*mipsV:
1e799e28
CD		 4306*mips32:
4307*mips64:
c906108c
SS		 4308*vr4100:
4309*vr5000:
4310*r3900:
4311{
9b17d183 4312 check_fpu (SD_);
c906108c
SS		 4313 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4314}
4315
4316
eb5fcf93 4317010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
c906108c
SS		 4318"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4319*mipsIV:
603a98e7 4320*mipsV:
1e799e28 4321*mips64:
c906108c
SS		 4322*vr5000:
4323{
9b17d183 4324 check_fpu (SD_);
ca971540 4325 check_u64 (SD_, instruction_0);
c906108c
SS		 4326 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4327}
4328
4329
4330
f3c08b7e
CD		 4331010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP1X:64,f::MADD.fmt
4332"madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
c906108c 4333*mipsIV:
603a98e7 4334*mipsV:
1e799e28 4335*mips64:
c906108c
SS		 4336*vr5000:
4337{
f3c08b7e 4338 int fmt = FMT;
9b17d183 4339 check_fpu (SD_);
f3c08b7e
CD		 4340 check_u64 (SD_, instruction_0);
4341 check_fmt_p (SD_, fmt, instruction_0);
4342 StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4343 ValueFPR (FR, fmt), fmt));
c906108c
SS		 4344}
4345
4346
cfe9ea23
CD		 4347010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4348"mfc1 r<RT>, f<FS>"
c906108c
SS		 4349*mipsI:
4350*mipsII:
4351*mipsIII:
4352{
cfe9ea23 4353 unsigned64 v;
9b17d183 4354 check_fpu (SD_);
cfe9ea23
CD		 4355 v = EXTEND32 (FGR[FS]);
4356 PENDING_FILL (RT, v);
4357 TRACE_ALU_RESULT (v);
c906108c 4358}
cfe9ea23
CD		 4359
4360010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4361"mfc1 r<RT>, f<FS>"
c906108c 4362*mipsIV:
603a98e7 4363*mipsV:
1e799e28
CD		 4364*mips32:
4365*mips64:
c906108c
SS		 4366*vr4100:
4367*vr5000:
4368*r3900:
cfe9ea23 4369{
9b17d183 4370 check_fpu (SD_);
cfe9ea23
CD		 4371 GPR[RT] = EXTEND32 (FGR[FS]);
4372 TRACE_ALU_RESULT (GPR[RT]);
c906108c
SS		 4373}
4374
4375
eb5fcf93 4376010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
c906108c 4377"mov.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 4378*mipsI:
4379*mipsII:
4380*mipsIII:
4381*mipsIV:
603a98e7 4382*mipsV:
1e799e28
CD		 4383*mips32:
4384*mips64:
c906108c
SS		 4385*vr4100:
4386*vr5000:
4387*r3900:
4388{
c1e8ada4 4389 int fmt = FMT;
9b17d183 4390 check_fpu (SD_);
8612006b 4391 check_fmt_p (SD_, fmt, instruction_0);
d18ea9c2 4392 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
c906108c
SS		 4393}
4394
4395
4396// MOVF
c2d11a7d 4397// MOVT
eb5fcf93 4398000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
c906108c
SS		 4399"mov%s<TF> r<RD>, r<RS>, <CC>"
4400*mipsIV:
603a98e7 4401*mipsV:
1e799e28
CD		 4402*mips32:
4403*mips64:
c906108c
SS		 4404*vr5000:
4405{
9b17d183 4406 check_fpu (SD_);
c906108c
SS		 4407 if (GETFCC(CC) == TF)
4408 GPR[RD] = GPR[RS];
4409}
4410
4411
4412// MOVF.fmt
c2d11a7d 4413// MOVT.fmt
eb5fcf93 4414010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
c906108c
SS		 4415"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4416*mipsIV:
603a98e7 4417*mipsV:
1e799e28
CD		 4418*mips32:
4419*mips64:
c906108c
SS		 4420*vr5000:
4421{
c1e8ada4 4422 int fmt = FMT;
9b17d183 4423 check_fpu (SD_);
3a2b820e
CD		 4424 if (fmt != fmt_ps)
4425 {
4426 if (GETFCC(CC) == TF)
4427 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4428 else
4429 StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */
4430 }
4431 else
4432 {
4433 unsigned64 fd;
4434 fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
4435 fmt_ps)),
4436 PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
4437 fmt_ps)));
4438 StoreFPR (FD, fmt_ps, fd);
4439 }
c906108c
SS		 4440}
4441
4442
eb5fcf93 4443010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
80ee11fa 4444"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
c906108c 4445*mipsIV:
603a98e7 4446*mipsV:
1e799e28
CD		 4447*mips32:
4448*mips64:
c906108c
SS		 4449*vr5000:
4450{
9b17d183 4451 check_fpu (SD_);
80ee11fa
AC		 4452 if (GPR[RT] != 0)
4453 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4454 else
4455 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
c906108c
SS		 4456}
4457
4458
4459// MOVT see MOVtf
4460
4461
4462// MOVT.fmt see MOVtf.fmt
4463
4464
4465
eb5fcf93 4466010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
c906108c
SS		 4467"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4468*mipsIV:
603a98e7 4469*mipsV:
1e799e28
CD		 4470*mips32:
4471*mips64:
c906108c
SS		 4472*vr5000:
4473{
9b17d183 4474 check_fpu (SD_);
80ee11fa
AC		 4475 if (GPR[RT] == 0)
4476 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4477 else
4478 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
c906108c
SS		 4479}
4480
4481
f3c08b7e
CD		 4482010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP1X:64,f::MSUB.fmt
4483"msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
c906108c 4484*mipsIV:
603a98e7 4485*mipsV:
1e799e28 4486*mips64:
c906108c
SS		 4487*vr5000:
4488{
f3c08b7e 4489 int fmt = FMT;
9b17d183 4490 check_fpu (SD_);
f3c08b7e
CD		 4491 check_u64 (SD_, instruction_0);
4492 check_fmt_p (SD_, fmt, instruction_0);
4493 StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4494 ValueFPR (FR, fmt), fmt));
c906108c
SS		 4495}
4496
4497
cfe9ea23
CD		 4498010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4499"mtc1 r<RT>, f<FS>"
4500*mipsI:
4501*mipsII:
4502*mipsIII:
4503{
4504 check_fpu (SD_);
4505 if (SizeFGR () == 64)
4506 PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4507 else
4508 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4509 TRACE_FP_RESULT (GPR[RT]);
4510}
4511
4512010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4513"mtc1 r<RT>, f<FS>"
4514*mipsIV:
4515*mipsV:
4516*mips32:
4517*mips64:
4518*vr4100:
4519*vr5000:
4520*r3900:
4521{
4522 check_fpu (SD_);
4523 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4524}
c906108c
SS		 4525
4526
eb5fcf93 4527010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
c906108c 4528"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 4529*mipsI:
4530*mipsII:
4531*mipsIII:
4532*mipsIV:
603a98e7 4533*mipsV:
1e799e28
CD		 4534*mips32:
4535*mips64:
c906108c
SS		 4536*vr4100:
4537*vr5000:
4538*r3900:
4539{
c1e8ada4 4540 int fmt = FMT;
9b17d183 4541 check_fpu (SD_);
8612006b 4542 check_fmt_p (SD_, fmt, instruction_0);
d18ea9c2 4543 StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
c906108c
SS		 4544}
4545
4546
eb5fcf93 4547010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
c906108c 4548"neg.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 4549*mipsI:
4550*mipsII:
4551*mipsIII:
4552*mipsIV:
603a98e7 4553*mipsV:
1e799e28
CD		 4554*mips32:
4555*mips64:
c906108c
SS		 4556*vr4100:
4557*vr5000:
4558*r3900:
4559{
c1e8ada4 4560 int fmt = FMT;
9b17d183 4561 check_fpu (SD_);
8612006b 4562 check_fmt_p (SD_, fmt, instruction_0);
d18ea9c2 4563 StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
c906108c
SS		 4564}
4565
4566
f3c08b7e
CD		 4567010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP1X:64,f::NMADD.fmt
4568"nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
c906108c 4569*mipsIV:
603a98e7 4570*mipsV:
1e799e28 4571*mips64:
c906108c
SS		 4572*vr5000:
4573{
f3c08b7e 4574 int fmt = FMT;
9b17d183 4575 check_fpu (SD_);
f3c08b7e
CD		 4576 check_u64 (SD_, instruction_0);
4577 check_fmt_p (SD_, fmt, instruction_0);
4578 StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4579 ValueFPR (FR, fmt), fmt));
c906108c
SS		 4580}
4581
4582
f3c08b7e
CD		 4583010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP1X:64,f::NMSUB.fmt
4584"nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
c906108c 4585*mipsIV:
603a98e7 4586*mipsV:
1e799e28 4587*mips64:
c906108c
SS		 4588*vr5000:
4589{
f3c08b7e 4590 int fmt = FMT;
9b17d183 4591 check_fpu (SD_);
f3c08b7e
CD		 4592 check_u64 (SD_, instruction_0);
4593 check_fmt_p (SD_, fmt, instruction_0);
4594 StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4595 ValueFPR (FR, fmt), fmt));
c906108c
SS		 4596}
4597
4598
3a2b820e
CD		 4599010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
4600"pll.ps f<FD>, f<FS>, f<FT>"
4601*mipsV:
4602*mips64:
4603{
4604 check_fpu (SD_);
4605 check_u64 (SD_, instruction_0);
4606 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
4607 PSLower (ValueFPR (FT, fmt_ps))));
4608}
4609
4610
4611010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
4612"plu.ps f<FD>, f<FS>, f<FT>"
4613*mipsV:
4614*mips64:
4615{
4616 check_fpu (SD_);
4617 check_u64 (SD_, instruction_0);
4618 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
4619 PSUpper (ValueFPR (FT, fmt_ps))));
4620}
4621
4622
3d81f391 4623010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
c906108c
SS		 4624"prefx <HINT>, r<INDEX>(r<BASE>)"
4625*mipsIV:
603a98e7 4626*mipsV:
1e799e28 4627*mips64:
c906108c
SS		 4628*vr5000:
4629{
c1e8ada4
CD		 4630 address_word base = GPR[BASE];
4631 address_word index = GPR[INDEX];
c906108c 4632 {
09297648 4633 address_word vaddr = loadstore_ea (SD_, base, index);
c906108c
SS		 4634 address_word paddr;
4635 int uncached;
4636 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
c1e8ada4 4637 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
c906108c
SS		 4638 }
4639}
4640
3a2b820e
CD		 4641
4642010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
4643"pul.ps f<FD>, f<FS>, f<FT>"
4644*mipsV:
4645*mips64:
4646{
4647 check_fpu (SD_);
4648 check_u64 (SD_, instruction_0);
4649 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
4650 PSLower (ValueFPR (FT, fmt_ps))));
4651}
4652
4653
4654010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
4655"puu.ps f<FD>, f<FS>, f<FT>"
4656*mipsV:
4657*mips64:
4658{
4659 check_fpu (SD_);
4660 check_u64 (SD_, instruction_0);
4661 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
4662 PSUpper (ValueFPR (FT, fmt_ps))));
4663}
4664
4665
eb5fcf93 4666010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
c906108c 4667"recip.%s<FMT> f<FD>, f<FS>"
e514a9d6 4668*mipsIV:
603a98e7 4669*mipsV:
1e799e28 4670*mips64:
c906108c
SS		 4671*vr5000:
4672{
c1e8ada4 4673 int fmt = FMT;
9b17d183 4674 check_fpu (SD_);
8612006b 4675 check_fmt (SD_, fmt, instruction_0);
d18ea9c2 4676 StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
c906108c
SS		 4677}
4678
4679
eb5fcf93 4680010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
c906108c
SS		 4681"round.l.%s<FMT> f<FD>, f<FS>"
4682*mipsIII:
4683*mipsIV:
603a98e7 4684*mipsV:
1e799e28 4685*mips64:
c906108c
SS		 4686*vr4100:
4687*vr5000:
4688*r3900:
4689{
c1e8ada4 4690 int fmt = FMT;
9b17d183 4691 check_fpu (SD_);
8612006b 4692 check_fmt (SD_, fmt, instruction_0);
d18ea9c2
CD		 4693 StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4694 fmt_long));
c906108c
SS		 4695}
4696
4697
eb5fcf93 4698010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
c906108c
SS		 4699"round.w.%s<FMT> f<FD>, f<FS>"
4700*mipsII:
4701*mipsIII:
4702*mipsIV:
603a98e7 4703*mipsV:
1e799e28
CD		 4704*mips32:
4705*mips64:
c906108c
SS		 4706*vr4100:
4707*vr5000:
4708*r3900:
4709{
c1e8ada4 4710 int fmt = FMT;
9b17d183 4711 check_fpu (SD_);
8612006b 4712 check_fmt (SD_, fmt, instruction_0);
d18ea9c2
CD		 4713 StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4714 fmt_word));
c906108c
SS		 4715}
4716
4717
eb5fcf93 4718010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
95fd5cee 4719"rsqrt.%s<FMT> f<FD>, f<FS>"
c906108c 4720*mipsIV:
603a98e7 4721*mipsV:
1e799e28 4722*mips64:
c906108c
SS		 4723*vr5000:
4724{
c1e8ada4 4725 int fmt = FMT;
9b17d183 4726 check_fpu (SD_);
8612006b 4727 check_fmt (SD_, fmt, instruction_0);
f3c08b7e 4728 StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
c906108c
SS		 4729}
4730
4731
06e7837e 4732111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
c906108c
SS		 4733"sdc1 f<FT>, <OFFSET>(r<BASE>)"
4734*mipsII:
06e7837e
CD		 4735*mips32:
4736{
4737 check_fpu (SD_);
4738 do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4739}
4740
4741
4742111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
4743"sdc1 f<FT>, <OFFSET>(r<BASE>)"
c906108c
SS		 4744*mipsIII:
4745*mipsIV:
603a98e7 4746*mipsV:
1e799e28 4747*mips64:
c906108c
SS		 4748*vr4100:
4749*vr5000:
4750*r3900:
4751{
9b17d183 4752 check_fpu (SD_);
c906108c
SS		 4753 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4754}
4755
4756
eb5fcf93 4757010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
91a177cf 4758"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
c906108c 4759*mipsIV:
603a98e7 4760*mipsV:
1e799e28 4761*mips64:
c906108c
SS		 4762*vr5000:
4763{
9b17d183 4764 check_fpu (SD_);
ca971540 4765 check_u64 (SD_, instruction_0);
c906108c
SS		 4766 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4767}
4768
4769
eb5fcf93 4770010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
c906108c
SS		 4771"sqrt.%s<FMT> f<FD>, f<FS>"
4772*mipsII:
4773*mipsIII:
4774*mipsIV:
603a98e7 4775*mipsV:
1e799e28
CD		 4776*mips32:
4777*mips64:
c906108c
SS		 4778*vr4100:
4779*vr5000:
4780*r3900:
4781{
c1e8ada4 4782 int fmt = FMT;
9b17d183 4783 check_fpu (SD_);
8612006b 4784 check_fmt (SD_, fmt, instruction_0);
d18ea9c2 4785 StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
c906108c
SS		 4786}
4787
4788
eb5fcf93 4789010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
c906108c 4790"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 4791*mipsI:
4792*mipsII:
4793*mipsIII:
4794*mipsIV:
603a98e7 4795*mipsV:
1e799e28
CD		 4796*mips32:
4797*mips64:
c906108c
SS		 4798*vr4100:
4799*vr5000:
4800*r3900:
4801{
c1e8ada4 4802 int fmt = FMT;
9b17d183 4803 check_fpu (SD_);
8612006b 4804 check_fmt_p (SD_, fmt, instruction_0);
d18ea9c2 4805 StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
c906108c
SS		 4806}
4807
4808
4809
eb5fcf93 4810111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
c906108c 4811"swc1 f<FT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 4812*mipsI:
4813*mipsII:
4814*mipsIII:
4815*mipsIV:
603a98e7 4816*mipsV:
1e799e28
CD		 4817*mips32:
4818*mips64:
c906108c
SS		 4819*vr4100:
4820*vr5000:
4821*r3900:
4822{
09297648
CD		 4823 address_word base = GPR[BASE];
4824 address_word offset = EXTEND16 (OFFSET);
9b17d183 4825 check_fpu (SD_);
c906108c 4826 {
09297648 4827 address_word vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 4828 address_word paddr;
4829 int uncached;
4830 if ((vaddr & 3) != 0)
4831 {
4832 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4833 }
4834 else
4835 {
4836 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4837 {
4838 uword64 memval = 0;
4839 uword64 memval1 = 0;
4840 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4841 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4842 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4843 unsigned int byte;
4844 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4845 byte = ((vaddr & mask) ^ bigendiancpu);
c1e8ada4 4846 memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
c906108c
SS		 4847 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4848 }
4849 }
4850 }
4851}
4852
4853
eb5fcf93 4854010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
c906108c
SS		 4855"swxc1 f<FS>, r<INDEX>(r<BASE>)"
4856*mipsIV:
603a98e7 4857*mipsV:
1e799e28 4858*mips64:
c906108c
SS		 4859*vr5000:
4860{
c1e8ada4
CD		 4861
4862 address_word base = GPR[BASE];
4863 address_word index = GPR[INDEX];
9b17d183 4864 check_fpu (SD_);
ca971540 4865 check_u64 (SD_, instruction_0);
c906108c 4866 {
09297648 4867 address_word vaddr = loadstore_ea (SD_, base, index);
c906108c
SS		 4868 address_word paddr;
4869 int uncached;
4870 if ((vaddr & 3) != 0)
4871 {
4872 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4873 }
4874 else
4875 {
4876 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4877 {
4878 unsigned64 memval = 0;
4879 unsigned64 memval1 = 0;
4880 unsigned64 mask = 0x7;
4881 unsigned int byte;
4882 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4883 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
c1e8ada4 4884 memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
c906108c
SS		 4885 {
4886 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4887 }
4888 }
4889 }
4890 }
4891}
4892
4893
eb5fcf93 4894010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
c906108c
SS		 4895"trunc.l.%s<FMT> f<FD>, f<FS>"
4896*mipsIII:
4897*mipsIV:
603a98e7 4898*mipsV:
1e799e28 4899*mips64:
c906108c
SS		 4900*vr4100:
4901*vr5000:
4902*r3900:
4903{
c1e8ada4 4904 int fmt = FMT;
9b17d183 4905 check_fpu (SD_);
8612006b 4906 check_fmt (SD_, fmt, instruction_0);
d18ea9c2
CD		 4907 StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
4908 fmt_long));
c906108c
SS		 4909}
4910
4911
eb5fcf93 4912010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
c906108c
SS		 4913"trunc.w.%s<FMT> f<FD>, f<FS>"
4914*mipsII:
4915*mipsIII:
4916*mipsIV:
603a98e7 4917*mipsV:
1e799e28
CD		 4918*mips32:
4919*mips64:
c906108c
SS		 4920*vr4100:
4921*vr5000:
4922*r3900:
4923{
c1e8ada4 4924 int fmt = FMT;
9b17d183 4925 check_fpu (SD_);
8612006b 4926 check_fmt (SD_, fmt, instruction_0);
d18ea9c2
CD		 4927 StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
4928 fmt_word));
c906108c
SS		 4929}
4930
4931\f
4932//
4933// MIPS Architecture:
4934//
4935// System Control Instruction Set (COP0)
4936//
4937
4938
4939010000,01000,00000,16.OFFSET:COP0:32::BC0F
4940"bc0f <OFFSET>"
c5d00cc7
CD		 4941*mipsI:
4942*mipsII:
4943*mipsIII:
4944*mipsIV:
603a98e7 4945*mipsV:
1e799e28
CD		 4946*mips32:
4947*mips64:
c906108c
SS		 4948*vr4100:
4949*vr5000:
4950
7a292a7a
SS		 4951010000,01000,00000,16.OFFSET:COP0:32::BC0F
4952"bc0f <OFFSET>"
4953// stub needed for eCos as tx39 hardware bug workaround
4954*r3900:
4955{
4956 /* do nothing */
4957}
4958
c906108c
SS		 4959
4960010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4961"bc0fl <OFFSET>"
c5d00cc7
CD		 4962*mipsI:
4963*mipsII:
4964*mipsIII:
4965*mipsIV:
603a98e7 4966*mipsV:
1e799e28
CD		 4967*mips32:
4968*mips64:
c906108c
SS		 4969*vr4100:
4970*vr5000:
4971
4972
4973010000,01000,00001,16.OFFSET:COP0:32::BC0T
4974"bc0t <OFFSET>"
c5d00cc7
CD		 4975*mipsI:
4976*mipsII:
4977*mipsIII:
4978*mipsIV:
603a98e7 4979*mipsV:
1e799e28
CD		 4980*mips32:
4981*mips64:
c906108c
SS		 4982*vr4100:
4983
4984
4985010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4986"bc0tl <OFFSET>"
c5d00cc7
CD		 4987*mipsI:
4988*mipsII:
4989*mipsIII:
4990*mipsIV:
603a98e7 4991*mipsV:
1e799e28
CD		 4992*mips32:
4993*mips64:
c906108c
SS		 4994*vr4100:
4995*vr5000:
4996
4997
4998101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
0d3e762b 4999"cache <OP>, <OFFSET>(r<BASE>)"
c906108c
SS		 5000*mipsIII:
5001*mipsIV:
603a98e7 5002*mipsV:
1e799e28
CD		 5003*mips32:
5004*mips64:
c906108c
SS		 5005*vr4100:
5006*vr5000:
5007*r3900:
5008{
c1e8ada4
CD		 5009 address_word base = GPR[BASE];
5010 address_word offset = EXTEND16 (OFFSET);
c906108c 5011 {
09297648 5012 address_word vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 5013 address_word paddr;
5014 int uncached;
5015 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
c1e8ada4 5016 CacheOp(OP,vaddr,paddr,instruction_0);
c906108c
SS		 5017 }
5018}
5019
5020
f701dad2 5021010000,1,0000000000000000000,111001:COP0:32::DI
c906108c 5022"di"
c5d00cc7
CD		 5023*mipsI:
5024*mipsII:
5025*mipsIII:
5026*mipsIV:
603a98e7 5027*mipsV:
c906108c
SS		 5028*vr4100:
5029*vr5000:
5030
5031
f701dad2 5032010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
9846de1b 5033"dmfc0 r<RT>, r<RD>"
c5d00cc7
CD		 5034*mipsIII:
5035*mipsIV:
603a98e7 5036*mipsV:
1e799e28 5037*mips64:
9846de1b 5038{
ca971540 5039 check_u64 (SD_, instruction_0);
9846de1b
JM		 5040 DecodeCoproc (instruction_0);
5041}
5042
5043
f701dad2 5044010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
9846de1b 5045"dmtc0 r<RT>, r<RD>"
c5d00cc7
CD		 5046*mipsIII:
5047*mipsIV:
603a98e7 5048*mipsV:
1e799e28 5049*mips64:
9846de1b 5050{
ca971540 5051 check_u64 (SD_, instruction_0);
9846de1b
JM		 5052 DecodeCoproc (instruction_0);
5053}
5054
5055
f701dad2 5056010000,1,0000000000000000000,111000:COP0:32::EI
c906108c 5057"ei"
c5d00cc7
CD		 5058*mipsI:
5059*mipsII:
5060*mipsIII:
5061*mipsIV:
603a98e7 5062*mipsV:
1e799e28 5063*mips64:
c906108c
SS		 5064*vr4100:
5065*vr5000:
5066
5067
f701dad2 5068010000,1,0000000000000000000,011000:COP0:32::ERET
c906108c
SS		 5069"eret"
5070*mipsIII:
5071*mipsIV:
603a98e7 5072*mipsV:
1e799e28
CD		 5073*mips32:
5074*mips64:
c906108c
SS		 5075*vr4100:
5076*vr5000:
5077{
5078 if (SR & status_ERL)
5079 {
5080 /* Oops, not yet available */
5081 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5082 NIA = EPC;
5083 SR &= ~status_ERL;
5084 }
5085 else
5086 {
5087 NIA = EPC;
5088 SR &= ~status_EXL;
5089 }
5090}
5091
5092
5093010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5094"mfc0 r<RT>, r<RD> # <REGX>"
c5d00cc7
CD		 5095*mipsI:
5096*mipsII:
5097*mipsIII:
5098*mipsIV:
603a98e7 5099*mipsV:
1e799e28
CD		 5100*mips32:
5101*mips64:
c906108c
SS		 5102*vr4100:
5103*vr5000:
074e9cb8 5104*r3900:
c906108c
SS		 5105{
5106 TRACE_ALU_INPUT0 ();
5107 DecodeCoproc (instruction_0);
5108 TRACE_ALU_RESULT (GPR[RT]);
5109}
5110
5111010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5112"mtc0 r<RT>, r<RD> # <REGX>"
c5d00cc7
CD		 5113*mipsI:
5114*mipsII:
5115*mipsIII:
5116*mipsIV:
603a98e7 5117*mipsV:
1e799e28
CD		 5118*mips32:
5119*mips64:
c906108c
SS		 5120*vr4100:
5121*vr5000:
074e9cb8 5122*r3900:
c906108c
SS		 5123{
5124 DecodeCoproc (instruction_0);
5125}
5126
5127
f701dad2 5128010000,1,0000000000000000000,010000:COP0:32::RFE
c906108c 5129"rfe"
c5d00cc7
CD		 5130*mipsI:
5131*mipsII:
5132*mipsIII:
5133*mipsIV:
603a98e7 5134*mipsV:
c906108c
SS		 5135*vr4100:
5136*vr5000:
074e9cb8 5137*r3900:
c906108c
SS		 5138{
5139 DecodeCoproc (instruction_0);
5140}
5141
5142
51430100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5144"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
c5d00cc7
CD		 5145*mipsI:
5146*mipsII:
5147*mipsIII:
5148*mipsIV:
603a98e7 5149*mipsV:
1e799e28
CD		 5150*mips32:
5151*mips64:
c906108c
SS		 5152*vr4100:
5153*r3900:
5154{
5155 DecodeCoproc (instruction_0);
5156}
5157
5158
5159
f701dad2 5160010000,1,0000000000000000000,001000:COP0:32::TLBP
c906108c 5161"tlbp"
c5d00cc7
CD		 5162*mipsI:
5163*mipsII:
5164*mipsIII:
5165*mipsIV:
603a98e7 5166*mipsV:
1e799e28
CD		 5167*mips32:
5168*mips64:
c906108c
SS		 5169*vr4100:
5170*vr5000:
5171
5172
f701dad2 5173010000,1,0000000000000000000,000001:COP0:32::TLBR
c906108c 5174"tlbr"
c5d00cc7
CD		 5175*mipsI:
5176*mipsII:
5177*mipsIII:
5178*mipsIV:
603a98e7 5179*mipsV:
1e799e28
CD		 5180*mips32:
5181*mips64:
c906108c
SS		 5182*vr4100:
5183*vr5000:
5184
5185
f701dad2 5186010000,1,0000000000000000000,000010:COP0:32::TLBWI
c906108c 5187"tlbwi"
c5d00cc7
CD		 5188*mipsI:
5189*mipsII:
5190*mipsIII:
5191*mipsIV:
603a98e7 5192*mipsV:
1e799e28
CD		 5193*mips32:
5194*mips64:
c906108c
SS		 5195*vr4100:
5196*vr5000:
5197
5198
f701dad2 5199010000,1,0000000000000000000,000110:COP0:32::TLBWR
c906108c 5200"tlbwr"
c5d00cc7
CD		 5201*mipsI:
5202*mipsII:
5203*mipsIII:
5204*mipsIV:
603a98e7 5205*mipsV:
1e799e28
CD		 5206*mips32:
5207*mips64:
c906108c
SS		 5208*vr4100:
5209*vr5000:
5210
5211\f
5212:include:::m16.igen
f4f1b9f1 5213:include:::mdmx.igen
e7e81181 5214:include:::mips3d.igen
7cbea089 5215:include:::sb1.igen
c906108c
SS		 5216:include:::tx.igen
5217:include:::vr.igen
5218\f
GDB Binutils - Deliverables
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