Commit | Line | Data |
---|---|---|
f2b30012 AC |
1 | // <insn> ::= |
2 | // <insn-word> { "+" <insn-word> } | |
3 | // ":" <format-name> | |
4 | // ":" <filter-flags> | |
5 | // ":" <options> | |
6 | // ":" <name> | |
7 | // <nl> | |
8 | // { <insn-model> } | |
9 | // { <insn-mnemonic> } | |
10 | // <code-block> | |
11 | // | |
12 | ||
13 | ||
14 | // IGEN config - mips16 | |
89d09738 AC |
15 | :option:16::insn-bit-size:16 |
16 | :option:16::hi-bit-nr:15 | |
17 | :option:16::insn-specifying-widths:true | |
18 | :option:16::gen-delayed-branch:false | |
f2b30012 | 19 | |
90ad43b2 | 20 | // IGEN config - mips32/64.. |
89d09738 AC |
21 | :option:32::insn-bit-size:32 |
22 | :option:32::hi-bit-nr:31 | |
23 | :option:32::insn-specifying-widths:true | |
24 | :option:32::gen-delayed-branch:false | |
f2b30012 AC |
25 | |
26 | ||
49a6eed5 | 27 | // Generate separate simulators for each target |
89d09738 | 28 | // :option:::multi-sim:true |
49a6eed5 | 29 | |
f2b30012 AC |
30 | |
31 | // Models known by this simulator | |
89d09738 AC |
32 | :model:::mipsI:mipsI: |
33 | :model:::mipsII:mipsII: | |
34 | :model:::mipsIII:mipsIII: | |
35 | :model:::mipsIV:mipsIV: | |
36 | :model:::mips16:mips16: | |
f2b30012 | 37 | // start-sanitize-r5900 |
89d09738 | 38 | :model:::r5900:r5900: |
f2b30012 | 39 | // end-sanitize-r5900 |
89d09738 | 40 | :model:::r3900:r3900: |
f2b30012 | 41 | // start-sanitize-tx19 |
89d09738 | 42 | :model:::tx19:tx19: |
f2b30012 | 43 | // end-sanitize-tx19 |
90ad43b2 | 44 | // start-sanitize-vr5400 |
89d09738 | 45 | :model:::vr5400:vr5400: |
90ad43b2 | 46 | // end-sanitize-vr5400 |
f2b30012 AC |
47 | |
48 | ||
49 | ||
50 | // Pseudo instructions known by IGEN | |
89d09738 | 51 | :internal::::illegal: |
f2b30012 | 52 | { |
7ce8b917 AC |
53 | /* FIXME: This ifetch causes a double count of a fetch at CIA */ |
54 | SignalException (ReservedInstruction, IMEM (CIA)); | |
f2b30012 AC |
55 | } |
56 | ||
57 | ||
58 | ||
59 | ||
60 | // | |
7ce8b917 | 61 | // Mips Architecture: |
f2b30012 AC |
62 | // |
63 | // CPU Instruction Set (mipsI - mipsIV) | |
64 | // | |
65 | ||
66 | ||
67 | 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD | |
68 | "add r<RD>, r<RS>, r<RT>" | |
69 | *mipsI: | |
70 | *mipsII: | |
71 | *mipsIII: | |
72 | *mipsIV: | |
90ad43b2 AC |
73 | // start-sanitize-vr5400 |
74 | *vr5400: | |
75 | // end-sanitize-vr5400 | |
f2b30012 AC |
76 | // start-sanitize-r5900 |
77 | *r5900: | |
78 | // end-sanitize-r5900 | |
79 | *r3900: | |
80 | // start-sanitize-tx19 | |
81 | *tx19: | |
82 | // end-sanitize-tx19 | |
83 | { | |
055ee297 AC |
84 | ALU32_BEGIN (GPR[RS]); |
85 | ALU32_ADD (GPR[RT]); | |
86 | ALU32_END (GPR[RD]); | |
f2b30012 AC |
87 | } |
88 | ||
89 | ||
90 | 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI | |
91 | "addi r<RT>, r<RS>, IMMEDIATE" | |
92 | *mipsI: | |
93 | *mipsII: | |
94 | *mipsIII: | |
95 | *mipsIV: | |
90ad43b2 AC |
96 | // start-sanitize-vr5400 |
97 | *vr5400: | |
98 | // end-sanitize-vr5400 | |
f2b30012 AC |
99 | // start-sanitize-r5900 |
100 | *r5900: | |
101 | // end-sanitize-r5900 | |
102 | *r3900: | |
103 | // start-sanitize-tx19 | |
104 | *tx19: | |
105 | // end-sanitize-tx19 | |
106 | { | |
055ee297 | 107 | ALU32_BEGIN (GPR[RS]); |
f2b30012 | 108 | ALU32_ADD (EXTEND16 (IMMEDIATE)); |
055ee297 | 109 | ALU32_END (GPR[RT]); |
f2b30012 AC |
110 | } |
111 | ||
112 | ||
113 | 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU | |
7ce8b917 | 114 | "add r<RT>, r<RS>, <IMMEDIATE>" |
f2b30012 AC |
115 | *mipsI: |
116 | *mipsII: | |
117 | *mipsIII: | |
118 | *mipsIV: | |
90ad43b2 AC |
119 | // start-sanitize-vr5400 |
120 | *vr5400: | |
121 | // end-sanitize-vr5400 | |
f2b30012 AC |
122 | // start-sanitize-r5900 |
123 | *r5900: | |
124 | // end-sanitize-r5900 | |
125 | *r3900: | |
126 | // start-sanitize-tx19 | |
127 | *tx19: | |
128 | // end-sanitize-tx19 | |
129 | { | |
055ee297 AC |
130 | signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE); |
131 | GPR[RT] = EXTEND32 (temp); | |
f2b30012 AC |
132 | } |
133 | ||
134 | ||
135 | 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU | |
136 | *mipsI: | |
137 | *mipsII: | |
138 | *mipsIII: | |
139 | *mipsIV: | |
90ad43b2 AC |
140 | // start-sanitize-vr5400 |
141 | *vr5400: | |
142 | // end-sanitize-vr5400 | |
f2b30012 AC |
143 | // start-sanitize-r5900 |
144 | *r5900: | |
145 | // end-sanitize-r5900 | |
146 | *r3900: | |
147 | // start-sanitize-tx19 | |
148 | *tx19: | |
149 | // end-sanitize-tx19 | |
150 | { | |
055ee297 AC |
151 | signed32 temp = GPR[RS] + GPR[RT]; |
152 | GPR[RD] = EXTEND32 (temp); | |
f2b30012 AC |
153 | } |
154 | ||
155 | ||
156 | 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND | |
157 | "and r<RD>, r<RS>, r<RT>" | |
158 | *mipsI: | |
159 | *mipsII: | |
160 | *mipsIII: | |
161 | *mipsIV: | |
90ad43b2 AC |
162 | // start-sanitize-vr5400 |
163 | *vr5400: | |
164 | // end-sanitize-vr5400 | |
f2b30012 AC |
165 | // start-sanitize-r5900 |
166 | *r5900: | |
167 | // end-sanitize-r5900 | |
168 | *r3900: | |
169 | // start-sanitize-tx19 | |
170 | *tx19: | |
171 | // end-sanitize-tx19 | |
172 | { | |
055ee297 | 173 | GPR[RD] = GPR[RS] & GPR[RT]; |
f2b30012 AC |
174 | } |
175 | ||
176 | ||
177 | 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI | |
178 | "and r<RT>, r<RS>, IMMEDIATE" | |
179 | *mipsI: | |
180 | *mipsII: | |
181 | *mipsIII: | |
90ad43b2 AC |
182 | // start-sanitize-vr5400 |
183 | *vr5400: | |
184 | // end-sanitize-vr5400 | |
f2b30012 AC |
185 | // start-sanitize-r5900 |
186 | *r5900: | |
187 | // end-sanitize-r5900 | |
188 | *r3900: | |
189 | // start-sanitize-tx19 | |
190 | *tx19: | |
191 | // end-sanitize-tx19 | |
192 | { | |
055ee297 | 193 | GPR[RT] = GPR[RS] & IMMEDIATE; |
f2b30012 AC |
194 | } |
195 | ||
196 | ||
197 | 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ | |
7ce8b917 | 198 | "beq r<RS>, r<RT>, <OFFSET>" |
f2b30012 AC |
199 | *mipsI: |
200 | *mipsII: | |
201 | *mipsIII: | |
202 | *mipsIV: | |
90ad43b2 AC |
203 | // start-sanitize-vr5400 |
204 | *vr5400: | |
205 | // end-sanitize-vr5400 | |
f2b30012 AC |
206 | // start-sanitize-r5900 |
207 | *r5900: | |
208 | // end-sanitize-r5900 | |
209 | *r3900: | |
210 | // start-sanitize-tx19 | |
211 | *tx19: | |
212 | // end-sanitize-tx19 | |
213 | { | |
055ee297 AC |
214 | address_word offset = EXTEND16 (OFFSET) << 2; |
215 | if (GPR[RS] == GPR[RT]) | |
7ce8b917 | 216 | DELAY_SLOT (CIA + offset); |
f2b30012 AC |
217 | } |
218 | ||
219 | ||
220 | 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL | |
221 | "beql r<RS>, r<RT>, <OFFSET>" | |
222 | *mipsII: | |
223 | *mipsIII: | |
224 | *mipsIV: | |
90ad43b2 AC |
225 | // start-sanitize-vr5400 |
226 | *vr5400: | |
227 | // end-sanitize-vr5400 | |
f2b30012 AC |
228 | // start-sanitize-r5900 |
229 | *r5900: | |
230 | // end-sanitize-r5900 | |
231 | *r3900: | |
232 | // start-sanitize-tx19 | |
233 | *tx19: | |
234 | // end-sanitize-tx19 | |
235 | { | |
055ee297 AC |
236 | address_word offset = EXTEND16 (OFFSET) << 2; |
237 | if (GPR[RS] == GPR[RT]) | |
7ce8b917 | 238 | DELAY_SLOT (CIA + offset); |
055ee297 | 239 | else |
49a76833 | 240 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
241 | } |
242 | ||
243 | ||
244 | 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ | |
245 | "bgez r<RS>, <OFFSET>" | |
246 | *mipsI: | |
247 | *mipsII: | |
248 | *mipsIII: | |
249 | *mipsIV: | |
90ad43b2 AC |
250 | // start-sanitize-vr5400 |
251 | *vr5400: | |
252 | // end-sanitize-vr5400 | |
f2b30012 AC |
253 | // start-sanitize-r5900 |
254 | *r5900: | |
255 | // end-sanitize-r5900 | |
256 | *r3900: | |
257 | // start-sanitize-tx19 | |
258 | *tx19: | |
259 | // end-sanitize-tx19 | |
260 | { | |
055ee297 AC |
261 | address_word offset = EXTEND16 (OFFSET) << 2; |
262 | if (GPR[RS] >= 0) | |
7ce8b917 | 263 | DELAY_SLOT (CIA + offset); |
f2b30012 AC |
264 | } |
265 | ||
266 | ||
267 | 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL | |
268 | "bgezal r<RS>, <OFFSET>" | |
269 | *mipsI: | |
270 | *mipsII: | |
271 | *mipsIII: | |
272 | *mipsIV: | |
90ad43b2 AC |
273 | // start-sanitize-vr5400 |
274 | *vr5400: | |
275 | // end-sanitize-vr5400 | |
f2b30012 AC |
276 | // start-sanitize-r5900 |
277 | *r5900: | |
278 | // end-sanitize-r5900 | |
279 | *r3900: | |
280 | // start-sanitize-tx19 | |
281 | *tx19: | |
282 | // end-sanitize-tx19 | |
283 | { | |
055ee297 AC |
284 | address_word offset = EXTEND16 (OFFSET) << 2; |
285 | RA = (CIA + 8); | |
286 | if (GPR[RS] >= 0) | |
7ce8b917 | 287 | DELAY_SLOT (CIA + offset); |
f2b30012 AC |
288 | } |
289 | ||
290 | ||
291 | 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL | |
292 | "bgezall r<RS>, <OFFSET>" | |
293 | *mipsII: | |
294 | *mipsIII: | |
295 | *mipsIV: | |
90ad43b2 AC |
296 | // start-sanitize-vr5400 |
297 | *vr5400: | |
298 | // end-sanitize-vr5400 | |
f2b30012 AC |
299 | // start-sanitize-r5900 |
300 | *r5900: | |
301 | // end-sanitize-r5900 | |
302 | *r3900: | |
303 | // start-sanitize-tx19 | |
304 | *tx19: | |
305 | // end-sanitize-tx19 | |
306 | { | |
055ee297 AC |
307 | address_word offset = EXTEND16 (OFFSET) << 2; |
308 | RA = (CIA + 8); | |
f2b30012 AC |
309 | /* NOTE: The branch occurs AFTER the next instruction has been |
310 | executed */ | |
055ee297 | 311 | if (GPR[RS] >= 0) |
7ce8b917 | 312 | DELAY_SLOT (CIA + offset); |
f2b30012 | 313 | else |
49a76833 | 314 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
315 | } |
316 | ||
317 | ||
318 | 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL | |
319 | "bgezl r<RS>, <OFFSET>" | |
320 | *mipsII: | |
321 | *mipsIII: | |
322 | *mipsIV: | |
90ad43b2 AC |
323 | // start-sanitize-vr5400 |
324 | *vr5400: | |
325 | // end-sanitize-vr5400 | |
f2b30012 AC |
326 | // start-sanitize-r5900 |
327 | *r5900: | |
328 | // end-sanitize-r5900 | |
329 | *r3900: | |
330 | // start-sanitize-tx19 | |
331 | *tx19: | |
332 | // end-sanitize-tx19 | |
333 | { | |
055ee297 AC |
334 | address_word offset = EXTEND16 (OFFSET) << 2; |
335 | if (GPR[RS] >= 0) | |
7ce8b917 | 336 | DELAY_SLOT (CIA + offset); |
f2b30012 | 337 | else |
49a76833 | 338 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
339 | } |
340 | ||
341 | ||
342 | 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ | |
343 | "bgtz r<RS>, <OFFSET>" | |
344 | *mipsI: | |
345 | *mipsII: | |
346 | *mipsIII: | |
347 | *mipsIV: | |
90ad43b2 AC |
348 | // start-sanitize-vr5400 |
349 | *vr5400: | |
350 | // end-sanitize-vr5400 | |
f2b30012 AC |
351 | // start-sanitize-r5900 |
352 | *r5900: | |
353 | // end-sanitize-r5900 | |
354 | *r3900: | |
355 | // start-sanitize-tx19 | |
356 | *tx19: | |
357 | // end-sanitize-tx19 | |
358 | { | |
055ee297 AC |
359 | address_word offset = EXTEND16 (OFFSET) << 2; |
360 | if (GPR[RS] > 0) | |
7ce8b917 | 361 | DELAY_SLOT (CIA + offset); |
f2b30012 AC |
362 | } |
363 | ||
364 | ||
365 | 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL | |
366 | "bgtzl r<RS>, <OFFSET>" | |
367 | *mipsII: | |
368 | *mipsIII: | |
369 | *mipsIV: | |
90ad43b2 AC |
370 | // start-sanitize-vr5400 |
371 | *vr5400: | |
372 | // end-sanitize-vr5400 | |
f2b30012 AC |
373 | // start-sanitize-r5900 |
374 | *r5900: | |
375 | // end-sanitize-r5900 | |
376 | *r3900: | |
377 | // start-sanitize-tx19 | |
378 | *tx19: | |
379 | // end-sanitize-tx19 | |
380 | { | |
055ee297 | 381 | address_word offset = EXTEND16 (OFFSET) << 2; |
f2b30012 AC |
382 | /* NOTE: The branch occurs AFTER the next instruction has been |
383 | executed */ | |
055ee297 | 384 | if (GPR[RS] > 0) |
7ce8b917 | 385 | DELAY_SLOT (CIA + offset); |
f2b30012 | 386 | else |
49a76833 | 387 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
388 | } |
389 | ||
390 | ||
391 | 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ | |
392 | "blez r<RS>, <OFFSET>" | |
393 | *mipsI: | |
394 | *mipsII: | |
395 | *mipsIII: | |
396 | *mipsIV: | |
90ad43b2 AC |
397 | // start-sanitize-vr5400 |
398 | *vr5400: | |
399 | // end-sanitize-vr5400 | |
f2b30012 AC |
400 | // start-sanitize-r5900 |
401 | *r5900: | |
402 | // end-sanitize-r5900 | |
403 | *r3900: | |
404 | // start-sanitize-tx19 | |
405 | *tx19: | |
406 | // end-sanitize-tx19 | |
407 | { | |
055ee297 | 408 | address_word offset = EXTEND16 (OFFSET) << 2; |
f2b30012 AC |
409 | /* NOTE: The branch occurs AFTER the next instruction has been |
410 | executed */ | |
055ee297 | 411 | if (GPR[RS] <= 0) |
7ce8b917 | 412 | DELAY_SLOT (CIA + offset); |
f2b30012 AC |
413 | } |
414 | ||
415 | ||
416 | 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL | |
417 | "bgezl r<RS>, <OFFSET>" | |
418 | *mipsII: | |
419 | *mipsIII: | |
420 | *mipsIV: | |
90ad43b2 AC |
421 | // start-sanitize-vr5400 |
422 | *vr5400: | |
423 | // end-sanitize-vr5400 | |
f2b30012 AC |
424 | // start-sanitize-r5900 |
425 | *r5900: | |
426 | // end-sanitize-r5900 | |
427 | *r3900: | |
428 | // start-sanitize-tx19 | |
429 | *tx19: | |
430 | // end-sanitize-tx19 | |
431 | { | |
055ee297 | 432 | address_word offset = EXTEND16 (OFFSET) << 2; |
055ee297 | 433 | if (GPR[RS] <= 0) |
7ce8b917 | 434 | DELAY_SLOT (CIA + offset); |
f2b30012 | 435 | else |
49a76833 | 436 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
437 | } |
438 | ||
439 | ||
440 | 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ | |
441 | "bltz r<RS>, <OFFSET>" | |
442 | *mipsI: | |
443 | *mipsII: | |
444 | *mipsIII: | |
445 | *mipsIV: | |
90ad43b2 AC |
446 | // start-sanitize-vr5400 |
447 | *vr5400: | |
448 | // end-sanitize-vr5400 | |
f2b30012 AC |
449 | // start-sanitize-r5900 |
450 | *r5900: | |
451 | // end-sanitize-r5900 | |
452 | *r3900: | |
453 | // start-sanitize-tx19 | |
454 | *tx19: | |
455 | // end-sanitize-tx19 | |
456 | { | |
055ee297 AC |
457 | address_word offset = EXTEND16 (OFFSET) << 2; |
458 | if (GPR[RS] < 0) | |
7ce8b917 | 459 | DELAY_SLOT (CIA + offset); |
f2b30012 AC |
460 | } |
461 | ||
462 | ||
463 | 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL | |
464 | "bltzal r<RS>, <OFFSET>" | |
465 | *mipsI: | |
466 | *mipsII: | |
467 | *mipsIII: | |
468 | *mipsIV: | |
90ad43b2 AC |
469 | // start-sanitize-vr5400 |
470 | *vr5400: | |
471 | // end-sanitize-vr5400 | |
f2b30012 AC |
472 | // start-sanitize-r5900 |
473 | *r5900: | |
474 | // end-sanitize-r5900 | |
475 | *r3900: | |
476 | // start-sanitize-tx19 | |
477 | *tx19: | |
478 | // end-sanitize-tx19 | |
479 | { | |
055ee297 AC |
480 | address_word offset = EXTEND16 (OFFSET) << 2; |
481 | RA = (CIA + 8); | |
f2b30012 AC |
482 | /* NOTE: The branch occurs AFTER the next instruction has been |
483 | executed */ | |
055ee297 | 484 | if (GPR[RS] < 0) |
7ce8b917 | 485 | DELAY_SLOT (CIA + offset); |
f2b30012 AC |
486 | } |
487 | ||
488 | ||
489 | 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL | |
490 | "bltzall r<RS>, <OFFSET>" | |
491 | *mipsII: | |
492 | *mipsIII: | |
493 | *mipsIV: | |
90ad43b2 AC |
494 | // start-sanitize-vr5400 |
495 | *vr5400: | |
496 | // end-sanitize-vr5400 | |
f2b30012 AC |
497 | // start-sanitize-r5900 |
498 | *r5900: | |
499 | // end-sanitize-r5900 | |
500 | *r3900: | |
501 | // start-sanitize-tx19 | |
502 | *tx19: | |
503 | // end-sanitize-tx19 | |
504 | { | |
055ee297 AC |
505 | address_word offset = EXTEND16 (OFFSET) << 2; |
506 | RA = (CIA + 8); | |
507 | if (GPR[RS] < 0) | |
7ce8b917 | 508 | DELAY_SLOT (CIA + offset); |
f2b30012 | 509 | else |
49a76833 | 510 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
511 | } |
512 | ||
513 | ||
514 | 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL | |
515 | "bltzl r<RS>, <OFFSET>" | |
516 | *mipsII: | |
517 | *mipsIII: | |
518 | *mipsIV: | |
90ad43b2 AC |
519 | // start-sanitize-vr5400 |
520 | *vr5400: | |
521 | // end-sanitize-vr5400 | |
f2b30012 AC |
522 | // start-sanitize-r5900 |
523 | *r5900: | |
524 | // end-sanitize-r5900 | |
525 | *r3900: | |
526 | // start-sanitize-tx19 | |
527 | *tx19: | |
528 | // end-sanitize-tx19 | |
529 | { | |
055ee297 | 530 | address_word offset = EXTEND16 (OFFSET) << 2; |
f2b30012 AC |
531 | /* NOTE: The branch occurs AFTER the next instruction has been |
532 | executed */ | |
055ee297 | 533 | if (GPR[RS] < 0) |
7ce8b917 | 534 | DELAY_SLOT (CIA + offset); |
f2b30012 | 535 | else |
49a76833 | 536 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
537 | } |
538 | ||
539 | ||
540 | 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE | |
541 | "bne r<RS>, r<RT>, <OFFSET>" | |
542 | *mipsI: | |
543 | *mipsII: | |
544 | *mipsIII: | |
545 | *mipsIV: | |
90ad43b2 AC |
546 | // start-sanitize-vr5400 |
547 | *vr5400: | |
548 | // end-sanitize-vr5400 | |
f2b30012 AC |
549 | // start-sanitize-r5900 |
550 | *r5900: | |
551 | // end-sanitize-r5900 | |
552 | *r3900: | |
553 | // start-sanitize-tx19 | |
554 | *tx19: | |
555 | // end-sanitize-tx19 | |
556 | { | |
055ee297 AC |
557 | address_word offset = EXTEND16 (OFFSET) << 2; |
558 | if (GPR[RS] != GPR[RT]) | |
7ce8b917 | 559 | DELAY_SLOT (CIA + offset); |
f2b30012 AC |
560 | } |
561 | ||
562 | ||
563 | 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL | |
564 | "bnel r<RS>, r<RT>, <OFFSET>" | |
565 | *mipsII: | |
566 | *mipsIII: | |
567 | *mipsIV: | |
90ad43b2 AC |
568 | // start-sanitize-vr5400 |
569 | *vr5400: | |
570 | // end-sanitize-vr5400 | |
f2b30012 AC |
571 | // start-sanitize-r5900 |
572 | *r5900: | |
573 | // end-sanitize-r5900 | |
574 | *r3900: | |
575 | // start-sanitize-tx19 | |
576 | *tx19: | |
577 | // end-sanitize-tx19 | |
578 | { | |
085c1cb9 | 579 | address_word offset = EXTEND16 (OFFSET) << 2; |
055ee297 | 580 | if (GPR[RS] != GPR[RT]) |
7ce8b917 | 581 | DELAY_SLOT (CIA + offset); |
f2b30012 | 582 | else |
49a76833 | 583 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
584 | } |
585 | ||
586 | ||
49a6eed5 | 587 | 000000,20.CODE,001101:SPECIAL:32::BREAK |
f2b30012 AC |
588 | "break" |
589 | *mipsI: | |
590 | *mipsII: | |
591 | *mipsIII: | |
592 | *mipsIV: | |
90ad43b2 AC |
593 | // start-sanitize-vr5400 |
594 | *vr5400: | |
595 | // end-sanitize-vr5400 | |
f2b30012 AC |
596 | // start-sanitize-r5900 |
597 | *r5900: | |
598 | // end-sanitize-r5900 | |
599 | *r3900: | |
600 | // start-sanitize-tx19 | |
601 | *tx19: | |
602 | // end-sanitize-tx19 | |
603 | { | |
055ee297 | 604 | SignalException(BreakPoint, instruction_0); |
f2b30012 AC |
605 | } |
606 | ||
607 | ||
49a6eed5 | 608 | 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz |
f2b30012 AC |
609 | "cop<ZZ> <COP_FUN>" |
610 | *mipsI: | |
611 | *mipsII: | |
612 | *mipsIII: | |
613 | *mipsIV: | |
614 | // start-sanitize-r5900 | |
615 | *r5900: | |
616 | // end-sanitize-r5900 | |
617 | *r3900: | |
618 | // start-sanitize-tx19 | |
619 | *tx19: | |
620 | // end-sanitize-tx19 | |
621 | { | |
085c1cb9 | 622 | DecodeCoproc (instruction_0); |
f2b30012 AC |
623 | } |
624 | ||
625 | ||
626 | 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD | |
627 | "dadd r<RD>, r<RS>, r<RT>" | |
628 | *mipsIII: | |
629 | *mipsIV: | |
90ad43b2 AC |
630 | // start-sanitize-vr5400 |
631 | *vr5400: | |
632 | // end-sanitize-vr5400 | |
f2b30012 AC |
633 | // start-sanitize-r5900 |
634 | *r5900: | |
635 | // end-sanitize-r5900 | |
636 | *r3900: | |
637 | // start-sanitize-tx19 | |
638 | *tx19: | |
639 | // end-sanitize-tx19 | |
640 | { | |
055ee297 AC |
641 | ALU64_BEGIN (GPR[RS]); |
642 | ALU64_ADD (GPR[RT]); | |
643 | ALU64_END (GPR[RT]); | |
f2b30012 AC |
644 | } |
645 | ||
646 | ||
647 | 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI | |
648 | "daddi r<RT>, r<RS>, <IMMEDIATE>" | |
649 | *mipsIII: | |
650 | *mipsIV: | |
90ad43b2 AC |
651 | // start-sanitize-vr5400 |
652 | *vr5400: | |
653 | // end-sanitize-vr5400 | |
f2b30012 AC |
654 | // start-sanitize-r5900 |
655 | *r5900: | |
656 | // end-sanitize-r5900 | |
657 | *r3900: | |
658 | // start-sanitize-tx19 | |
659 | *tx19: | |
660 | // end-sanitize-tx19 | |
661 | { | |
055ee297 | 662 | ALU64_BEGIN (GPR[RS]); |
f2b30012 | 663 | ALU64_ADD (EXTEND16 (IMMEDIATE)); |
055ee297 | 664 | ALU64_END (GPR[RT]); |
f2b30012 AC |
665 | } |
666 | ||
667 | ||
668 | 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU | |
669 | "daddu r<RT>, r<RS>, <IMMEDIATE>" | |
670 | *mipsIII: | |
671 | *mipsIV: | |
90ad43b2 AC |
672 | // start-sanitize-vr5400 |
673 | *vr5400: | |
674 | // end-sanitize-vr5400 | |
f2b30012 AC |
675 | // start-sanitize-r5900 |
676 | *r5900: | |
677 | // end-sanitize-r5900 | |
678 | *r3900: | |
679 | // start-sanitize-tx19 | |
680 | *tx19: | |
681 | // end-sanitize-tx19 | |
682 | { | |
085c1cb9 | 683 | GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE); |
f2b30012 AC |
684 | } |
685 | ||
686 | ||
687 | 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU | |
688 | "daddu r<RD>, r<RS>, r<RT>" | |
689 | *mipsIII: | |
690 | *mipsIV: | |
90ad43b2 AC |
691 | // start-sanitize-vr5400 |
692 | *vr5400: | |
693 | // end-sanitize-vr5400 | |
f2b30012 AC |
694 | // start-sanitize-r5900 |
695 | *r5900: | |
696 | // end-sanitize-r5900 | |
697 | *r3900: | |
698 | // start-sanitize-tx19 | |
699 | *tx19: | |
700 | // end-sanitize-tx19 | |
701 | { | |
055ee297 | 702 | GPR[RD] = GPR[RS] + GPR[RT]; |
f2b30012 AC |
703 | } |
704 | ||
705 | ||
706 | 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV | |
707 | "ddiv r<RS>, r<RT>" | |
708 | *mipsIII: | |
709 | *mipsIV: | |
90ad43b2 AC |
710 | // start-sanitize-vr5400 |
711 | *vr5400: | |
712 | // end-sanitize-vr5400 | |
f2b30012 AC |
713 | // start-sanitize-r5900 |
714 | *r5900: | |
715 | // end-sanitize-r5900 | |
716 | *r3900: | |
717 | // start-sanitize-tx19 | |
718 | *tx19: | |
719 | // end-sanitize-tx19 | |
720 | { | |
721 | CHECKHILO ("Division"); | |
722 | { | |
055ee297 AC |
723 | signed64 n = GPR[RS]; |
724 | signed64 d = GPR[RT]; | |
f2b30012 AC |
725 | if (d == 0) |
726 | { | |
727 | LO = SIGNED64 (0x8000000000000000); | |
728 | HI = 0; | |
729 | } | |
730 | else if (d == -1 && n == SIGNED64 (0x8000000000000000)) | |
731 | { | |
732 | LO = SIGNED64 (0x8000000000000000); | |
733 | HI = 0; | |
734 | } | |
735 | else | |
736 | { | |
737 | LO = (n / d); | |
738 | HI = (n % d); | |
739 | } | |
740 | } | |
741 | } | |
742 | ||
743 | ||
744 | ||
745 | 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU | |
746 | "ddivu r<RS>, r<RT>" | |
747 | *mipsIII: | |
748 | *mipsIV: | |
749 | *r3900: | |
90ad43b2 AC |
750 | // start-sanitize-vr5400 |
751 | *vr5400: | |
752 | // end-sanitize-vr5400 | |
f2b30012 AC |
753 | // start-sanitize-tx19 |
754 | *tx19: | |
755 | // end-sanitize-tx19 | |
756 | { | |
757 | CHECKHILO ("Division"); | |
758 | { | |
055ee297 AC |
759 | unsigned64 n = GPR[RS]; |
760 | unsigned64 d = GPR[RT]; | |
f2b30012 AC |
761 | if (d == 0) |
762 | { | |
763 | LO = SIGNED64 (0x8000000000000000); | |
764 | HI = 0; | |
765 | } | |
766 | else | |
767 | { | |
768 | LO = (n / d); | |
769 | HI = (n % d); | |
770 | } | |
771 | } | |
772 | } | |
773 | ||
774 | ||
775 | 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV | |
776 | "div r<RS>, r<RT>" | |
777 | *mipsI: | |
778 | *mipsII: | |
779 | *mipsIII: | |
780 | *mipsIV: | |
90ad43b2 AC |
781 | // start-sanitize-vr5400 |
782 | *vr5400: | |
783 | // end-sanitize-vr5400 | |
f2b30012 AC |
784 | // start-sanitize-r5900 |
785 | *r5900: | |
786 | // end-sanitize-r5900 | |
787 | *r3900: | |
788 | // start-sanitize-tx19 | |
789 | *tx19: | |
790 | // end-sanitize-tx19 | |
791 | { | |
792 | CHECKHILO("Division"); | |
793 | { | |
055ee297 AC |
794 | signed32 n = GPR[RS]; |
795 | signed32 d = GPR[RT]; | |
f2b30012 AC |
796 | if (d == 0) |
797 | { | |
798 | LO = EXTEND32 (0x80000000); | |
799 | HI = EXTEND32 (0); | |
800 | } | |
055ee297 | 801 | else if (d == -1 && d == 0x80000000) |
f2b30012 AC |
802 | { |
803 | LO = EXTEND32 (0x80000000); | |
804 | HI = EXTEND32 (0); | |
805 | } | |
806 | else | |
807 | { | |
808 | LO = EXTEND32 (n / d); | |
809 | HI = EXTEND32 (n % d); | |
810 | } | |
811 | } | |
812 | } | |
813 | ||
814 | ||
815 | 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU | |
816 | "divu r<RS>, r<RT>" | |
817 | *mipsI: | |
818 | *mipsII: | |
819 | *mipsIII: | |
820 | *mipsIV: | |
90ad43b2 AC |
821 | // start-sanitize-vr5400 |
822 | *vr5400: | |
823 | // end-sanitize-vr5400 | |
f2b30012 AC |
824 | // start-sanitize-r5900 |
825 | *r5900: | |
826 | // end-sanitize-r5900 | |
827 | *r3900: | |
828 | // start-sanitize-tx19 | |
829 | *tx19: | |
830 | // end-sanitize-tx19 | |
831 | { | |
832 | CHECKHILO ("Division"); | |
833 | { | |
055ee297 AC |
834 | unsigned32 n = GPR[RS]; |
835 | unsigned32 d = GPR[RT]; | |
f2b30012 AC |
836 | if (d == 0) |
837 | { | |
838 | LO = EXTEND32 (0x80000000); | |
839 | HI = EXTEND32 (0); | |
840 | } | |
841 | else | |
842 | { | |
843 | LO = EXTEND32 (n / d); | |
844 | HI = EXTEND32 (n % d); | |
845 | } | |
846 | } | |
847 | } | |
848 | ||
849 | ||
850 | 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT | |
851 | "dmult r<RS>, r<RT>" | |
852 | *mipsIII: | |
853 | *mipsIV: | |
90ad43b2 AC |
854 | // start-sanitize-vr5400 |
855 | *vr5400: | |
856 | // end-sanitize-vr5400 | |
f2b30012 AC |
857 | *r3900: |
858 | // start-sanitize-tx19 | |
859 | *tx19: | |
860 | // end-sanitize-tx19 | |
861 | { | |
862 | CHECKHILO ("Multiplication"); | |
863 | { | |
055ee297 AC |
864 | signed64 op1 = GPR[RS]; |
865 | signed64 op2 = GPR[RT]; | |
f2b30012 AC |
866 | unsigned64 lo; |
867 | unsigned64 hi; | |
868 | unsigned64 m00; | |
869 | unsigned64 m01; | |
870 | unsigned64 m10; | |
871 | unsigned64 m11; | |
872 | unsigned64 mid; | |
f2b30012 AC |
873 | int sign = 0; |
874 | /* make it unsigned */ | |
875 | if (op1 < 0) | |
876 | { | |
877 | op1 = - op1; | |
878 | ++sign; | |
879 | } | |
880 | if (op2 < 0) | |
881 | { | |
882 | op2 = - op2; | |
883 | ++sign; | |
884 | } | |
885 | /* multuply out the 4 sub products */ | |
886 | m00 = (VL4_8 (op1) * VL4_8 (op2)); | |
887 | m10 = (VH4_8 (op1) * VL4_8 (op2)); | |
888 | m01 = (VL4_8 (op1) * VH4_8 (op2)); | |
889 | m11 = (VH4_8 (op1) * VH4_8 (op2)); | |
890 | /* add the products */ | |
891 | mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01); | |
892 | lo = U8_4 (mid, m00); | |
893 | hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10); | |
894 | /* save the result */ | |
895 | if (sign & 1) | |
896 | { | |
897 | LO = -lo; | |
898 | if (lo == 0) | |
899 | HI = -hi; | |
900 | else | |
901 | HI = -hi - 1; | |
902 | } | |
903 | else | |
904 | { | |
905 | LO = lo; | |
906 | HI = hi; | |
907 | } | |
908 | } | |
909 | } | |
910 | ||
911 | ||
912 | 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU | |
913 | "dmultu r<RS>, r<RT>" | |
914 | *mipsIII: | |
915 | *mipsIV: | |
90ad43b2 AC |
916 | // start-sanitize-vr5400 |
917 | *vr5400: | |
918 | // end-sanitize-vr5400 | |
f2b30012 AC |
919 | *r3900: |
920 | // start-sanitize-tx19 | |
921 | *tx19: | |
922 | // end-sanitize-tx19 | |
923 | { | |
924 | CHECKHILO ("Multiplication"); | |
925 | { | |
055ee297 AC |
926 | signed64 op1 = GPR[RS]; |
927 | signed64 op2 = GPR[RT]; | |
f2b30012 AC |
928 | unsigned64 lo; |
929 | unsigned64 hi; | |
930 | unsigned64 m00; | |
931 | unsigned64 m01; | |
932 | unsigned64 m10; | |
933 | unsigned64 m11; | |
934 | unsigned64 mid; | |
f2b30012 AC |
935 | /* multuply out the 4 sub products */ |
936 | m00 = (VL4_8 (op1) * VL4_8 (op2)); | |
937 | m10 = (VH4_8 (op1) * VL4_8 (op2)); | |
938 | m01 = (VL4_8 (op1) * VH4_8 (op2)); | |
939 | m11 = (VH4_8 (op1) * VH4_8 (op2)); | |
940 | /* add the products */ | |
941 | mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01); | |
942 | lo = U8_4 (mid, m00); | |
943 | hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10); | |
944 | /* save the result */ | |
945 | LO = lo; | |
946 | HI = hi; | |
947 | } | |
948 | } | |
949 | ||
950 | ||
055ee297 | 951 | 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL |
01b9cd49 | 952 | "dsll r<RD>, r<RT>, <SHIFT>" |
f2b30012 AC |
953 | *mipsIII: |
954 | *mipsIV: | |
90ad43b2 AC |
955 | // start-sanitize-vr5400 |
956 | *vr5400: | |
957 | // end-sanitize-vr5400 | |
f2b30012 AC |
958 | // start-sanitize-r5900 |
959 | *r5900: | |
960 | // end-sanitize-r5900 | |
961 | *r3900: | |
962 | // start-sanitize-tx19 | |
963 | *tx19: | |
964 | // end-sanitize-tx19 | |
965 | { | |
01b9cd49 | 966 | int s = SHIFT; |
055ee297 | 967 | GPR[RD] = GPR[RT] << s; |
f2b30012 AC |
968 | } |
969 | ||
970 | ||
055ee297 | 971 | 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32 |
01b9cd49 | 972 | "dsll32 r<RD>, r<RT>, <SHIFT>" |
f2b30012 AC |
973 | *mipsIII: |
974 | *mipsIV: | |
90ad43b2 AC |
975 | // start-sanitize-vr5400 |
976 | *vr5400: | |
977 | // end-sanitize-vr5400 | |
f2b30012 AC |
978 | // start-sanitize-r5900 |
979 | *r5900: | |
980 | // end-sanitize-r5900 | |
981 | *r3900: | |
982 | // start-sanitize-tx19 | |
983 | *tx19: | |
984 | // end-sanitize-tx19 | |
985 | { | |
01b9cd49 | 986 | int s = 32 + SHIFT; |
055ee297 | 987 | GPR[RD] = GPR[RT] << s; |
f2b30012 AC |
988 | } |
989 | ||
990 | ||
991 | 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV | |
992 | "dsllv r<RD>, r<RT>, r<RS>" | |
993 | *mipsIII: | |
994 | *mipsIV: | |
90ad43b2 AC |
995 | // start-sanitize-vr5400 |
996 | *vr5400: | |
997 | // end-sanitize-vr5400 | |
f2b30012 AC |
998 | // start-sanitize-r5900 |
999 | *r5900: | |
1000 | // end-sanitize-r5900 | |
1001 | *r3900: | |
1002 | // start-sanitize-tx19 | |
1003 | *tx19: | |
1004 | // end-sanitize-tx19 | |
1005 | { | |
055ee297 AC |
1006 | int s = MASKED64 (GPR[RS], 5, 0); |
1007 | GPR[RD] = GPR[RT] << s; | |
f2b30012 AC |
1008 | } |
1009 | ||
1010 | ||
055ee297 | 1011 | 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA |
01b9cd49 | 1012 | "dsra r<RD>, r<RT>, <SHIFT>" |
f2b30012 AC |
1013 | *mipsIII: |
1014 | *mipsIV: | |
90ad43b2 AC |
1015 | // start-sanitize-vr5400 |
1016 | *vr5400: | |
1017 | // end-sanitize-vr5400 | |
f2b30012 AC |
1018 | // start-sanitize-r5900 |
1019 | *r5900: | |
1020 | // end-sanitize-r5900 | |
1021 | *r3900: | |
1022 | // start-sanitize-tx19 | |
1023 | *tx19: | |
1024 | // end-sanitize-tx19 | |
1025 | { | |
01b9cd49 | 1026 | int s = SHIFT; |
055ee297 | 1027 | GPR[RD] = ((signed64) GPR[RT]) >> s; |
f2b30012 AC |
1028 | } |
1029 | ||
1030 | ||
055ee297 | 1031 | 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32 |
01b9cd49 | 1032 | "dsra32 r<RT>, r<RD>, <SHIFT>" |
f2b30012 AC |
1033 | *mipsIII: |
1034 | *mipsIV: | |
90ad43b2 AC |
1035 | // start-sanitize-vr5400 |
1036 | *vr5400: | |
1037 | // end-sanitize-vr5400 | |
f2b30012 AC |
1038 | // start-sanitize-r5900 |
1039 | *r5900: | |
1040 | // end-sanitize-r5900 | |
1041 | *r3900: | |
1042 | // start-sanitize-tx19 | |
1043 | *tx19: | |
1044 | // end-sanitize-tx19 | |
1045 | { | |
01b9cd49 | 1046 | int s = 32 + SHIFT; |
055ee297 | 1047 | GPR[RD] = ((signed64) GPR[RT]) >> s; |
f2b30012 AC |
1048 | } |
1049 | ||
1050 | ||
1051 | 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV | |
1052 | "dsra32 r<RT>, r<RD>, r<RS>" | |
1053 | *mipsIII: | |
1054 | *mipsIV: | |
90ad43b2 AC |
1055 | // start-sanitize-vr5400 |
1056 | *vr5400: | |
1057 | // end-sanitize-vr5400 | |
f2b30012 AC |
1058 | // start-sanitize-r5900 |
1059 | *r5900: | |
1060 | // end-sanitize-r5900 | |
1061 | *r3900: | |
1062 | // start-sanitize-tx19 | |
1063 | *tx19: | |
1064 | // end-sanitize-tx19 | |
1065 | { | |
055ee297 AC |
1066 | int s = MASKED64 (GPR[RS], 5, 0); |
1067 | GPR[RD] = ((signed64) GPR[RT]) >> s; | |
f2b30012 AC |
1068 | } |
1069 | ||
1070 | ||
055ee297 | 1071 | 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL |
01b9cd49 | 1072 | "dsrav r<RD>, r<RT>, <SHIFT>" |
f2b30012 AC |
1073 | *mipsIII: |
1074 | *mipsIV: | |
90ad43b2 AC |
1075 | // start-sanitize-vr5400 |
1076 | *vr5400: | |
1077 | // end-sanitize-vr5400 | |
f2b30012 AC |
1078 | // start-sanitize-r5900 |
1079 | *r5900: | |
1080 | // end-sanitize-r5900 | |
1081 | *r3900: | |
1082 | // start-sanitize-tx19 | |
1083 | *tx19: | |
1084 | // end-sanitize-tx19 | |
1085 | { | |
01b9cd49 | 1086 | int s = SHIFT; |
055ee297 | 1087 | GPR[RD] = (unsigned64) GPR[RT] >> s; |
f2b30012 AC |
1088 | } |
1089 | ||
1090 | ||
055ee297 | 1091 | 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32 |
01b9cd49 | 1092 | "dsrl32 r<RD>, r<RT>, <SHIFT>" |
f2b30012 AC |
1093 | *mipsIII: |
1094 | *mipsIV: | |
90ad43b2 AC |
1095 | // start-sanitize-vr5400 |
1096 | *vr5400: | |
1097 | // end-sanitize-vr5400 | |
f2b30012 AC |
1098 | // start-sanitize-r5900 |
1099 | *r5900: | |
1100 | // end-sanitize-r5900 | |
1101 | *r3900: | |
1102 | // start-sanitize-tx19 | |
1103 | *tx19: | |
1104 | // end-sanitize-tx19 | |
1105 | { | |
01b9cd49 | 1106 | int s = 32 + SHIFT; |
055ee297 | 1107 | GPR[RD] = (unsigned64) GPR[RT] >> s; |
f2b30012 AC |
1108 | } |
1109 | ||
1110 | ||
1111 | 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV | |
1112 | "dsrl32 r<RD>, r<RT>, r<RS>" | |
1113 | *mipsIII: | |
1114 | *mipsIV: | |
90ad43b2 AC |
1115 | // start-sanitize-vr5400 |
1116 | *vr5400: | |
1117 | // end-sanitize-vr5400 | |
f2b30012 AC |
1118 | // start-sanitize-r5900 |
1119 | *r5900: | |
1120 | // end-sanitize-r5900 | |
1121 | *r3900: | |
1122 | // start-sanitize-tx19 | |
1123 | *tx19: | |
1124 | // end-sanitize-tx19 | |
1125 | { | |
055ee297 AC |
1126 | int s = MASKED64 (GPR[RS], 5, 0); |
1127 | GPR[RD] = (unsigned64) GPR[RT] >> s; | |
f2b30012 AC |
1128 | } |
1129 | ||
1130 | ||
1131 | 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB | |
1132 | "dsub r<RD>, r<RS>, r<RT>" | |
1133 | *mipsIII: | |
1134 | *mipsIV: | |
90ad43b2 AC |
1135 | // start-sanitize-vr5400 |
1136 | *vr5400: | |
1137 | // end-sanitize-vr5400 | |
f2b30012 AC |
1138 | // start-sanitize-r5900 |
1139 | *r5900: | |
1140 | // end-sanitize-r5900 | |
1141 | *r3900: | |
1142 | // start-sanitize-tx19 | |
1143 | *tx19: | |
1144 | // end-sanitize-tx19 | |
1145 | { | |
055ee297 AC |
1146 | ALU64_BEGIN (GPR[RS]); |
1147 | ALU64_SUB (GPR[RT]); | |
1148 | ALU64_END (GPR[RD]); | |
f2b30012 AC |
1149 | } |
1150 | ||
1151 | ||
1152 | 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU | |
1153 | "dsubu r<RD>, r<RS>, r<RT>" | |
1154 | *mipsIII: | |
1155 | *mipsIV: | |
90ad43b2 AC |
1156 | // start-sanitize-vr5400 |
1157 | *vr5400: | |
1158 | // end-sanitize-vr5400 | |
f2b30012 AC |
1159 | // start-sanitize-r5900 |
1160 | *r5900: | |
1161 | // end-sanitize-r5900 | |
1162 | *r3900: | |
1163 | // start-sanitize-tx19 | |
1164 | *tx19: | |
1165 | // end-sanitize-tx19 | |
1166 | { | |
055ee297 | 1167 | GPR[RD] = GPR[RS] - GPR[RT]; |
f2b30012 AC |
1168 | } |
1169 | ||
1170 | ||
1171 | 000010,26.INSTR_INDEX:NORMAL:32::J | |
1172 | "j <INSTR_INDEX>" | |
1173 | *mipsI: | |
1174 | *mipsII: | |
1175 | *mipsIII: | |
1176 | *mipsIV: | |
90ad43b2 AC |
1177 | // start-sanitize-vr5400 |
1178 | *vr5400: | |
1179 | // end-sanitize-vr5400 | |
f2b30012 AC |
1180 | // start-sanitize-r5900 |
1181 | *r5900: | |
1182 | // end-sanitize-r5900 | |
1183 | *r3900: | |
1184 | // start-sanitize-tx19 | |
1185 | *tx19: | |
1186 | // end-sanitize-tx19 | |
1187 | { | |
49a76833 | 1188 | /* NOTE: The region used is that of the delay slot NIA and NOT the |
f2b30012 | 1189 | current instruction */ |
49a76833 AC |
1190 | address_word region = (NIA & MASK (63, 28)); |
1191 | DELAY_SLOT (region | (INSTR_INDEX << 2)); | |
f2b30012 AC |
1192 | } |
1193 | ||
1194 | ||
1195 | 000011,26.INSTR_INDEX:NORMAL:32::JAL | |
1196 | "jal <INSTR_INDEX>" | |
1197 | *mipsI: | |
1198 | *mipsII: | |
1199 | *mipsIII: | |
1200 | *mipsIV: | |
90ad43b2 AC |
1201 | // start-sanitize-vr5400 |
1202 | *vr5400: | |
1203 | // end-sanitize-vr5400 | |
f2b30012 AC |
1204 | // start-sanitize-r5900 |
1205 | *r5900: | |
1206 | // end-sanitize-r5900 | |
1207 | *r3900: | |
1208 | // start-sanitize-tx19 | |
1209 | *tx19: | |
1210 | // end-sanitize-tx19 | |
1211 | { | |
1212 | /* NOTE: The region used is that of the delay slot and NOT the | |
1213 | current instruction */ | |
49a76833 | 1214 | address_word region = (NIA & MASK (63, 28)); |
055ee297 | 1215 | GPR[31] = CIA + 8; |
49a76833 | 1216 | DELAY_SLOT (region | (INSTR_INDEX << 2)); |
f2b30012 AC |
1217 | } |
1218 | ||
1219 | ||
1220 | 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR | |
1221 | "jalr r<RS>":RD == 31 | |
1222 | "jalr r<RD>, r<RS>" | |
1223 | *mipsI: | |
1224 | *mipsII: | |
1225 | *mipsIII: | |
1226 | *mipsIV: | |
90ad43b2 AC |
1227 | // start-sanitize-vr5400 |
1228 | *vr5400: | |
1229 | // end-sanitize-vr5400 | |
f2b30012 AC |
1230 | // start-sanitize-r5900 |
1231 | *r5900: | |
1232 | // end-sanitize-r5900 | |
1233 | *r3900: | |
1234 | // start-sanitize-tx19 | |
1235 | *tx19: | |
1236 | // end-sanitize-tx19 | |
1237 | { | |
055ee297 AC |
1238 | address_word temp = GPR[RS]; |
1239 | GPR[RD] = CIA + 8; | |
49a76833 | 1240 | DELAY_SLOT (temp); |
f2b30012 AC |
1241 | } |
1242 | ||
1243 | ||
1244 | 000000,5.RS,000000000000000001000:SPECIAL:32::JR | |
1245 | "jr r<RS>" | |
1246 | *mipsI: | |
1247 | *mipsII: | |
1248 | *mipsIII: | |
1249 | *mipsIV: | |
90ad43b2 AC |
1250 | // start-sanitize-vr5400 |
1251 | *vr5400: | |
1252 | // end-sanitize-vr5400 | |
f2b30012 AC |
1253 | // start-sanitize-r5900 |
1254 | *r5900: | |
1255 | // end-sanitize-r5900 | |
1256 | *r3900: | |
1257 | // start-sanitize-tx19 | |
1258 | *tx19: | |
1259 | // end-sanitize-tx19 | |
1260 | { | |
49a76833 | 1261 | DELAY_SLOT (GPR[RS]); |
f2b30012 AC |
1262 | } |
1263 | ||
1264 | ||
1265 | 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB | |
1266 | "lb r<RT>, <OFFSET>(r<BASE>)" | |
1267 | *mipsI: | |
1268 | *mipsII: | |
1269 | *mipsIII: | |
1270 | *mipsIV: | |
90ad43b2 AC |
1271 | // start-sanitize-vr5400 |
1272 | *vr5400: | |
1273 | // end-sanitize-vr5400 | |
f2b30012 AC |
1274 | // start-sanitize-r5900 |
1275 | *r5900: | |
1276 | // end-sanitize-r5900 | |
1277 | *r3900: | |
1278 | // start-sanitize-tx19 | |
1279 | *tx19: | |
1280 | // end-sanitize-tx19 | |
1281 | { | |
1282 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1283 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1284 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1285 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1286 | { |
49a76833 AC |
1287 | address_word vaddr = ((uword64)op1 + offset); |
1288 | address_word paddr; | |
f2b30012 AC |
1289 | int uncached; |
1290 | { | |
1291 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1292 | { | |
1293 | uword64 memval = 0; | |
1294 | uword64 memval1 = 0; | |
1295 | uword64 mask = 0x7; | |
1296 | unsigned int shift = 0; | |
055ee297 AC |
1297 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1298 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1299 | unsigned int byte; | |
f2b30012 AC |
1300 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1301 | LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); | |
1302 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1303 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8)); | |
1304 | } | |
1305 | } | |
1306 | } | |
1307 | } | |
1308 | ||
1309 | ||
1310 | 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU | |
1311 | "lbu r<RT>, <OFFSET>(r<BASE>)" | |
1312 | *mipsI: | |
1313 | *mipsII: | |
1314 | *mipsIII: | |
1315 | *mipsIV: | |
90ad43b2 AC |
1316 | // start-sanitize-vr5400 |
1317 | *vr5400: | |
1318 | // end-sanitize-vr5400 | |
f2b30012 AC |
1319 | // start-sanitize-r5900 |
1320 | *r5900: | |
1321 | // end-sanitize-r5900 | |
1322 | *r3900: | |
1323 | // start-sanitize-tx19 | |
1324 | *tx19: | |
1325 | // end-sanitize-tx19 | |
1326 | { | |
1327 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1328 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1329 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1330 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1331 | { |
49a76833 AC |
1332 | address_word vaddr = ((unsigned64)op1 + offset); |
1333 | address_word paddr; | |
f2b30012 AC |
1334 | int uncached; |
1335 | { | |
1336 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1337 | { | |
1338 | unsigned64 memval = 0; | |
1339 | unsigned64 memval1 = 0; | |
1340 | unsigned64 mask = 0x7; | |
1341 | unsigned int shift = 0; | |
055ee297 AC |
1342 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1343 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1344 | unsigned int byte; | |
f2b30012 AC |
1345 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1346 | LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); | |
1347 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1348 | GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF)); | |
1349 | } | |
1350 | } | |
1351 | } | |
1352 | } | |
1353 | ||
1354 | ||
1355 | 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD | |
1356 | "ld r<RT>, <OFFSET>(r<BASE>)" | |
1357 | *mipsIII: | |
1358 | *mipsIV: | |
90ad43b2 AC |
1359 | // start-sanitize-vr5400 |
1360 | *vr5400: | |
1361 | // end-sanitize-vr5400 | |
f2b30012 AC |
1362 | // start-sanitize-r5900 |
1363 | *r5900: | |
1364 | // end-sanitize-r5900 | |
1365 | *r3900: | |
1366 | // start-sanitize-tx19 | |
1367 | *tx19: | |
1368 | // end-sanitize-tx19 | |
1369 | { | |
1370 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1371 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1372 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1373 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1374 | { |
49a76833 AC |
1375 | address_word vaddr = ((unsigned64)op1 + offset); |
1376 | address_word paddr; | |
f2b30012 AC |
1377 | int uncached; |
1378 | if ((vaddr & 7) != 0) | |
055ee297 | 1379 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1380 | else |
1381 | { | |
1382 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1383 | { | |
1384 | unsigned64 memval = 0; | |
1385 | unsigned64 memval1 = 0; | |
f2b30012 AC |
1386 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); |
1387 | GPR[destreg] = memval; | |
1388 | } | |
1389 | } | |
1390 | } | |
1391 | } | |
1392 | ||
1393 | ||
49a6eed5 | 1394 | 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz |
f2b30012 AC |
1395 | "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
1396 | *mipsII: | |
1397 | *mipsIII: | |
1398 | *mipsIV: | |
90ad43b2 AC |
1399 | // start-sanitize-vr5400 |
1400 | *vr5400: | |
1401 | // end-sanitize-vr5400 | |
f2b30012 AC |
1402 | // start-sanitize-r5900 |
1403 | *r5900: | |
1404 | // end-sanitize-r5900 | |
1405 | *r3900: | |
1406 | // start-sanitize-tx19 | |
1407 | *tx19: | |
1408 | // end-sanitize-tx19 | |
1409 | { | |
1410 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1411 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1412 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1413 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1414 | { |
49a76833 AC |
1415 | address_word vaddr = ((unsigned64)op1 + offset); |
1416 | address_word paddr; | |
f2b30012 AC |
1417 | int uncached; |
1418 | if ((vaddr & 7) != 0) | |
055ee297 | 1419 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1420 | else |
1421 | { | |
1422 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1423 | { | |
1424 | unsigned64 memval = 0; | |
1425 | unsigned64 memval1 = 0; | |
f2b30012 AC |
1426 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); |
1427 | COP_LD(((instruction >> 26) & 0x3),destreg,memval);; | |
1428 | } | |
1429 | } | |
1430 | } | |
1431 | } | |
1432 | ||
1433 | ||
1434 | 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL | |
1435 | "ldl r<RT>, <OFFSET>(r<BASE>)" | |
1436 | *mipsIII: | |
1437 | *mipsIV: | |
90ad43b2 AC |
1438 | // start-sanitize-vr5400 |
1439 | *vr5400: | |
1440 | // end-sanitize-vr5400 | |
f2b30012 AC |
1441 | // start-sanitize-r5900 |
1442 | *r5900: | |
1443 | // end-sanitize-r5900 | |
1444 | *r3900: | |
1445 | // start-sanitize-tx19 | |
1446 | *tx19: | |
1447 | // end-sanitize-tx19 | |
1448 | { | |
1449 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1450 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1451 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1452 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1453 | { |
49a76833 AC |
1454 | address_word vaddr = ((unsigned64)op1 + offset); |
1455 | address_word paddr; | |
f2b30012 AC |
1456 | int uncached; |
1457 | { | |
1458 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1459 | { | |
1460 | unsigned64 memval = 0; | |
1461 | unsigned64 memval1 = 0; | |
1462 | unsigned64 mask = 7; | |
1463 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
1464 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
1465 | int byte; | |
1466 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
1467 | byte = ((vaddr & mask) ^ bigend); | |
63be8feb | 1468 | if (!BigEndianMem) |
f2b30012 AC |
1469 | paddr &= ~mask; |
1470 | LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL); | |
1471 | GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1))); | |
1472 | } | |
1473 | } | |
1474 | } | |
1475 | } | |
1476 | ||
1477 | ||
1478 | 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR | |
1479 | "ldr r<RT>, <OFFSET>(r<BASE>)" | |
1480 | *mipsIII: | |
1481 | *mipsIV: | |
90ad43b2 AC |
1482 | // start-sanitize-vr5400 |
1483 | *vr5400: | |
1484 | // end-sanitize-vr5400 | |
f2b30012 AC |
1485 | // start-sanitize-r5900 |
1486 | *r5900: | |
1487 | // end-sanitize-r5900 | |
1488 | *r3900: | |
1489 | // start-sanitize-tx19 | |
1490 | *tx19: | |
1491 | // end-sanitize-tx19 | |
1492 | { | |
1493 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1494 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1495 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1496 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1497 | { |
49a76833 AC |
1498 | address_word vaddr = ((unsigned64)op1 + offset); |
1499 | address_word paddr; | |
f2b30012 AC |
1500 | int uncached; |
1501 | { | |
1502 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1503 | { | |
1504 | unsigned64 memval = 0; | |
1505 | unsigned64 memval1 = 0; | |
1506 | unsigned64 mask = 7; | |
1507 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
1508 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
1509 | int byte; | |
1510 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
1511 | byte = ((vaddr & mask) ^ bigend); | |
63be8feb | 1512 | if (BigEndianMem) |
f2b30012 AC |
1513 | paddr &= ~mask; |
1514 | LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL); | |
1515 | { | |
1516 | unsigned64 srcmask; | |
1517 | if (byte == 0) | |
1518 | srcmask = 0; | |
1519 | else | |
1520 | srcmask = ((unsigned64)-1 << (8 * (8 - byte))); | |
1521 | GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte))); | |
1522 | } | |
1523 | } | |
1524 | } | |
1525 | } | |
1526 | } | |
1527 | ||
1528 | ||
1529 | 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH | |
1530 | "lh r<RT>, <OFFSET>(r<BASE>)" | |
1531 | *mipsI: | |
1532 | *mipsII: | |
1533 | *mipsIII: | |
1534 | *mipsIV: | |
90ad43b2 AC |
1535 | // start-sanitize-vr5400 |
1536 | *vr5400: | |
1537 | // end-sanitize-vr5400 | |
f2b30012 AC |
1538 | // start-sanitize-r5900 |
1539 | *r5900: | |
1540 | // end-sanitize-r5900 | |
1541 | *r3900: | |
1542 | // start-sanitize-tx19 | |
1543 | *tx19: | |
1544 | // end-sanitize-tx19 | |
1545 | { | |
1546 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1547 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1548 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1549 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1550 | { |
49a76833 AC |
1551 | address_word vaddr = ((unsigned64)op1 + offset); |
1552 | address_word paddr; | |
f2b30012 AC |
1553 | int uncached; |
1554 | if ((vaddr & 1) != 0) | |
055ee297 | 1555 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1556 | else |
1557 | { | |
1558 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1559 | { | |
1560 | unsigned64 memval = 0; | |
1561 | unsigned64 memval1 = 0; | |
1562 | unsigned64 mask = 0x7; | |
1563 | unsigned int shift = 1; | |
055ee297 AC |
1564 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1565 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1566 | unsigned int byte; | |
f2b30012 AC |
1567 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1568 | LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); | |
1569 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1570 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16)); | |
1571 | } | |
1572 | } | |
1573 | } | |
1574 | } | |
1575 | ||
1576 | ||
1577 | 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU | |
1578 | "lhu r<RT>, <OFFSET>(r<BASE>)" | |
1579 | *mipsI: | |
1580 | *mipsII: | |
1581 | *mipsIII: | |
1582 | *mipsIV: | |
90ad43b2 AC |
1583 | // start-sanitize-vr5400 |
1584 | *vr5400: | |
1585 | // end-sanitize-vr5400 | |
f2b30012 AC |
1586 | // start-sanitize-r5900 |
1587 | *r5900: | |
1588 | // end-sanitize-r5900 | |
1589 | *r3900: | |
1590 | // start-sanitize-tx19 | |
1591 | *tx19: | |
1592 | // end-sanitize-tx19 | |
1593 | { | |
1594 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1595 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1596 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1597 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1598 | { |
49a76833 AC |
1599 | address_word vaddr = ((unsigned64)op1 + offset); |
1600 | address_word paddr; | |
f2b30012 AC |
1601 | int uncached; |
1602 | if ((vaddr & 1) != 0) | |
055ee297 | 1603 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1604 | else |
1605 | { | |
1606 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1607 | { | |
1608 | unsigned64 memval = 0; | |
1609 | unsigned64 memval1 = 0; | |
1610 | unsigned64 mask = 0x7; | |
1611 | unsigned int shift = 1; | |
055ee297 AC |
1612 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1613 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1614 | unsigned int byte; | |
f2b30012 AC |
1615 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1616 | LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); | |
1617 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1618 | GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF)); | |
1619 | } | |
1620 | } | |
1621 | } | |
1622 | } | |
1623 | ||
1624 | ||
1625 | 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL | |
1626 | "ll r<RT>, <OFFSET>(r<BASE>)" | |
1627 | *mipsII: | |
1628 | *mipsIII: | |
1629 | *mipsIV: | |
90ad43b2 AC |
1630 | // start-sanitize-vr5400 |
1631 | *vr5400: | |
1632 | // end-sanitize-vr5400 | |
f2b30012 AC |
1633 | // start-sanitize-r5900 |
1634 | *r5900: | |
1635 | // end-sanitize-r5900 | |
1636 | *r3900: | |
1637 | // start-sanitize-tx19 | |
1638 | *tx19: | |
1639 | // end-sanitize-tx19 | |
1640 | { | |
1641 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1642 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1643 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1644 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1645 | { |
49a76833 AC |
1646 | address_word vaddr = ((unsigned64)op1 + offset); |
1647 | address_word paddr; | |
f2b30012 AC |
1648 | int uncached; |
1649 | if ((vaddr & 3) != 0) | |
055ee297 | 1650 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1651 | else |
1652 | { | |
1653 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1654 | { | |
1655 | unsigned64 memval = 0; | |
1656 | unsigned64 memval1 = 0; | |
1657 | unsigned64 mask = 0x7; | |
1658 | unsigned int shift = 2; | |
055ee297 AC |
1659 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1660 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1661 | unsigned int byte; | |
f2b30012 AC |
1662 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1663 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
1664 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1665 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); | |
1666 | LLBIT = 1; | |
1667 | } | |
1668 | } | |
1669 | } | |
1670 | } | |
1671 | ||
1672 | ||
1673 | 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD | |
1674 | "lld r<RT>, <OFFSET>(r<BASE>)" | |
1675 | *mipsIII: | |
1676 | *mipsIV: | |
90ad43b2 AC |
1677 | // start-sanitize-vr5400 |
1678 | *vr5400: | |
1679 | // end-sanitize-vr5400 | |
f2b30012 AC |
1680 | // start-sanitize-r5900 |
1681 | *r5900: | |
1682 | // end-sanitize-r5900 | |
1683 | *r3900: | |
1684 | // start-sanitize-tx19 | |
1685 | *tx19: | |
1686 | // end-sanitize-tx19 | |
1687 | { | |
1688 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1689 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1690 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1691 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1692 | { |
49a76833 AC |
1693 | address_word vaddr = ((unsigned64)op1 + offset); |
1694 | address_word paddr; | |
f2b30012 AC |
1695 | int uncached; |
1696 | if ((vaddr & 7) != 0) | |
055ee297 | 1697 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1698 | else |
1699 | { | |
1700 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1701 | { | |
1702 | unsigned64 memval = 0; | |
1703 | unsigned64 memval1 = 0; | |
f2b30012 AC |
1704 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); |
1705 | GPR[destreg] = memval; | |
1706 | LLBIT = 1; | |
1707 | } | |
1708 | } | |
1709 | } | |
1710 | } | |
1711 | ||
1712 | ||
1713 | 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI | |
1714 | "lui r<RT>, <IMMEDIATE>" | |
1715 | *mipsI: | |
1716 | *mipsII: | |
1717 | *mipsIII: | |
1718 | *mipsIV: | |
90ad43b2 AC |
1719 | // start-sanitize-vr5400 |
1720 | *vr5400: | |
1721 | // end-sanitize-vr5400 | |
f2b30012 AC |
1722 | // start-sanitize-r5900 |
1723 | *r5900: | |
1724 | // end-sanitize-r5900 | |
1725 | *r3900: | |
1726 | // start-sanitize-tx19 | |
1727 | *tx19: | |
1728 | // end-sanitize-tx19 | |
1729 | { | |
055ee297 | 1730 | GPR[RT] = EXTEND32 (IMMEDIATE << 16); |
f2b30012 AC |
1731 | } |
1732 | ||
1733 | ||
1734 | 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW | |
1735 | "lw r<RT>, <OFFSET>(r<BASE>)" | |
1736 | *mipsI: | |
1737 | *mipsII: | |
1738 | *mipsIII: | |
1739 | *mipsIV: | |
90ad43b2 AC |
1740 | // start-sanitize-vr5400 |
1741 | *vr5400: | |
1742 | // end-sanitize-vr5400 | |
f2b30012 AC |
1743 | // start-sanitize-r5900 |
1744 | *r5900: | |
1745 | // end-sanitize-r5900 | |
1746 | *r3900: | |
1747 | // start-sanitize-tx19 | |
1748 | *tx19: | |
1749 | // end-sanitize-tx19 | |
1750 | { | |
1751 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1752 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1753 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1754 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1755 | { |
49a76833 AC |
1756 | address_word vaddr = ((unsigned64)op1 + offset); |
1757 | address_word paddr; | |
f2b30012 AC |
1758 | int uncached; |
1759 | if ((vaddr & 3) != 0) | |
055ee297 | 1760 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1761 | else |
1762 | { | |
1763 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1764 | { | |
1765 | unsigned64 memval = 0; | |
1766 | unsigned64 memval1 = 0; | |
1767 | unsigned64 mask = 0x7; | |
1768 | unsigned int shift = 2; | |
055ee297 AC |
1769 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1770 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1771 | unsigned int byte; | |
f2b30012 AC |
1772 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1773 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
1774 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1775 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); | |
1776 | } | |
1777 | } | |
1778 | } | |
1779 | } | |
1780 | ||
1781 | ||
49a6eed5 | 1782 | 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz |
f2b30012 AC |
1783 | "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
1784 | *mipsI: | |
1785 | *mipsII: | |
1786 | *mipsIII: | |
1787 | *mipsIV: | |
90ad43b2 AC |
1788 | // start-sanitize-vr5400 |
1789 | *vr5400: | |
1790 | // end-sanitize-vr5400 | |
f2b30012 AC |
1791 | // start-sanitize-r5900 |
1792 | *r5900: | |
1793 | // end-sanitize-r5900 | |
1794 | *r3900: | |
1795 | // start-sanitize-tx19 | |
1796 | *tx19: | |
1797 | // end-sanitize-tx19 | |
1798 | { | |
1799 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1800 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1801 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1802 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1803 | { |
49a76833 AC |
1804 | address_word vaddr = ((unsigned64)op1 + offset); |
1805 | address_word paddr; | |
f2b30012 AC |
1806 | int uncached; |
1807 | if ((vaddr & 3) != 0) | |
055ee297 | 1808 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1809 | else |
1810 | { | |
1811 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1812 | { | |
1813 | unsigned64 memval = 0; | |
1814 | unsigned64 memval1 = 0; | |
1815 | unsigned64 mask = 0x7; | |
1816 | unsigned int shift = 2; | |
055ee297 AC |
1817 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1818 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1819 | unsigned int byte; | |
f2b30012 AC |
1820 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1821 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
1822 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1823 | COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF)); | |
1824 | } | |
1825 | } | |
1826 | } | |
1827 | } | |
1828 | ||
1829 | ||
1830 | 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL | |
1831 | "lwl r<RT>, <OFFSET>(r<BASE>)" | |
1832 | *mipsI: | |
1833 | *mipsII: | |
1834 | *mipsIII: | |
1835 | *mipsIV: | |
90ad43b2 AC |
1836 | // start-sanitize-vr5400 |
1837 | *vr5400: | |
1838 | // end-sanitize-vr5400 | |
f2b30012 AC |
1839 | // start-sanitize-r5900 |
1840 | *r5900: | |
1841 | // end-sanitize-r5900 | |
1842 | *r3900: | |
1843 | // start-sanitize-tx19 | |
1844 | *tx19: | |
1845 | // end-sanitize-tx19 | |
1846 | { | |
1847 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1848 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1849 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1850 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1851 | { |
49a76833 AC |
1852 | address_word vaddr = ((unsigned64)op1 + offset); |
1853 | address_word paddr; | |
f2b30012 AC |
1854 | int uncached; |
1855 | { | |
1856 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1857 | { | |
1858 | unsigned64 memval = 0; | |
1859 | unsigned64 memval1 = 0; | |
1860 | unsigned64 mask = 3; | |
1861 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
1862 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
1863 | int byte; | |
1864 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
1865 | byte = ((vaddr & mask) ^ bigend); | |
63be8feb | 1866 | if (!BigEndianMem) |
f2b30012 AC |
1867 | paddr &= ~mask; |
1868 | LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL); | |
1869 | if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { | |
1870 | memval >>= 32; | |
1871 | } | |
1872 | GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1))); | |
1873 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
1874 | } | |
1875 | } | |
1876 | } | |
1877 | } | |
1878 | ||
1879 | ||
1880 | 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR | |
1881 | "lwr r<RT>, <OFFSET>(r<BASE>)" | |
1882 | *mipsI: | |
1883 | *mipsII: | |
1884 | *mipsIII: | |
1885 | *mipsIV: | |
90ad43b2 AC |
1886 | // start-sanitize-vr5400 |
1887 | *vr5400: | |
1888 | // end-sanitize-vr5400 | |
f2b30012 AC |
1889 | // start-sanitize-r5900 |
1890 | *r5900: | |
1891 | // end-sanitize-r5900 | |
1892 | *r3900: | |
1893 | // start-sanitize-tx19 | |
1894 | *tx19: | |
1895 | // end-sanitize-tx19 | |
1896 | { | |
1897 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1898 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1899 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1900 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1901 | { |
49a76833 AC |
1902 | address_word vaddr = ((unsigned64)op1 + offset); |
1903 | address_word paddr; | |
f2b30012 AC |
1904 | int uncached; |
1905 | { | |
1906 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1907 | { | |
1908 | unsigned64 memval = 0; | |
1909 | unsigned64 memval1 = 0; | |
1910 | unsigned64 mask = 3; | |
1911 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
1912 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
1913 | int byte; | |
1914 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
1915 | byte = ((vaddr & mask) ^ bigend); | |
63be8feb | 1916 | if (BigEndianMem) |
f2b30012 AC |
1917 | paddr &= ~mask; |
1918 | LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL); | |
1919 | if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { | |
1920 | memval >>= 32; | |
1921 | } | |
1922 | { | |
1923 | unsigned64 srcmask; | |
1924 | if (byte == 0) | |
1925 | srcmask = 0; | |
1926 | else | |
1927 | srcmask = ((unsigned64)-1 << (8 * (4 - byte))); | |
1928 | GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte))); | |
1929 | } | |
1930 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
1931 | } | |
1932 | } | |
1933 | } | |
1934 | } | |
1935 | ||
1936 | ||
1937 | 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU | |
1938 | "lwu r<RT>, <OFFSET>(r<BASE>)" | |
1939 | *mipsIII: | |
1940 | *mipsIV: | |
90ad43b2 AC |
1941 | // start-sanitize-vr5400 |
1942 | *vr5400: | |
1943 | // end-sanitize-vr5400 | |
f2b30012 AC |
1944 | // start-sanitize-r5900 |
1945 | *r5900: | |
1946 | // end-sanitize-r5900 | |
1947 | *r3900: | |
1948 | // start-sanitize-tx19 | |
1949 | *tx19: | |
1950 | // end-sanitize-tx19 | |
1951 | { | |
1952 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1953 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1954 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1955 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1956 | { |
49a76833 AC |
1957 | address_word vaddr = ((unsigned64)op1 + offset); |
1958 | address_word paddr; | |
f2b30012 AC |
1959 | int uncached; |
1960 | if ((vaddr & 3) != 0) | |
055ee297 | 1961 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1962 | else |
1963 | { | |
1964 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1965 | { | |
1966 | unsigned64 memval = 0; | |
1967 | unsigned64 memval1 = 0; | |
1968 | unsigned64 mask = 0x7; | |
1969 | unsigned int shift = 2; | |
055ee297 AC |
1970 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1971 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1972 | unsigned int byte; | |
f2b30012 AC |
1973 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1974 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
1975 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1976 | GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF)); | |
1977 | } | |
1978 | } | |
1979 | } | |
1980 | } | |
1981 | ||
1982 | ||
1983 | 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI | |
1984 | "mfhi r<RD>" | |
1985 | *mipsI: | |
1986 | *mipsII: | |
1987 | *mipsIII: | |
1988 | *mipsIV: | |
90ad43b2 AC |
1989 | // start-sanitize-vr5400 |
1990 | *vr5400: | |
1991 | // end-sanitize-vr5400 | |
f2b30012 AC |
1992 | // start-sanitize-r5900 |
1993 | *r5900: | |
1994 | // end-sanitize-r5900 | |
1995 | *r3900: | |
1996 | // start-sanitize-tx19 | |
1997 | *tx19: | |
1998 | // end-sanitize-tx19 | |
1999 | { | |
055ee297 | 2000 | GPR[RD] = HI; |
f2b30012 AC |
2001 | HIACCESS = 3; |
2002 | } | |
2003 | ||
2004 | ||
2005 | 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO | |
2006 | "mflo r<RD>" | |
2007 | *mipsI: | |
2008 | *mipsII: | |
2009 | *mipsIII: | |
2010 | *mipsIV: | |
90ad43b2 AC |
2011 | // start-sanitize-vr5400 |
2012 | *vr5400: | |
2013 | // end-sanitize-vr5400 | |
f2b30012 AC |
2014 | // start-sanitize-r5900 |
2015 | *r5900: | |
2016 | // end-sanitize-r5900 | |
2017 | *r3900: | |
2018 | // start-sanitize-tx19 | |
2019 | *tx19: | |
2020 | // end-sanitize-tx19 | |
2021 | { | |
055ee297 | 2022 | GPR[RD] = LO; |
f2b30012 AC |
2023 | LOACCESS = 3; /* 3rd instruction will be safe */ |
2024 | } | |
2025 | ||
2026 | ||
2027 | 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN | |
2028 | "movn r<RD>, r<RS>, r<RT>" | |
2029 | *mipsIV: | |
90ad43b2 AC |
2030 | // start-sanitize-vr5400 |
2031 | *vr5400: | |
2032 | // end-sanitize-vr5400 | |
f2b30012 AC |
2033 | // start-sanitize-r5900 |
2034 | *r5900: | |
2035 | // end-sanitize-r5900 | |
2036 | { | |
055ee297 AC |
2037 | if (GPR[RT] != 0) |
2038 | GPR[RD] = GPR[RS]; | |
f2b30012 AC |
2039 | } |
2040 | ||
2041 | ||
2042 | 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ | |
2043 | "movz r<RD>, r<RS>, r<RT>" | |
2044 | *mipsIV: | |
90ad43b2 AC |
2045 | // start-sanitize-vr5400 |
2046 | *vr5400: | |
2047 | // end-sanitize-vr5400 | |
f2b30012 AC |
2048 | // start-sanitize-r5900 |
2049 | *r5900: | |
2050 | // end-sanitize-r5900 | |
2051 | { | |
055ee297 AC |
2052 | if (GPR[RT] == 0) |
2053 | GPR[RD] = GPR[RS]; | |
f2b30012 AC |
2054 | } |
2055 | ||
2056 | ||
2057 | 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI | |
2058 | "mthi r<RS>" | |
2059 | *mipsI: | |
2060 | *mipsII: | |
2061 | *mipsIII: | |
2062 | *mipsIV: | |
90ad43b2 AC |
2063 | // start-sanitize-vr5400 |
2064 | *vr5400: | |
2065 | // end-sanitize-vr5400 | |
f2b30012 AC |
2066 | // start-sanitize-r5900 |
2067 | *r5900: | |
2068 | // end-sanitize-r5900 | |
2069 | *r3900: | |
2070 | // start-sanitize-tx19 | |
2071 | *tx19: | |
2072 | // end-sanitize-tx19 | |
2073 | { | |
2074 | if (HIACCESS != 0) | |
055ee297 AC |
2075 | sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n"); |
2076 | HI = GPR[RS]; | |
f2b30012 AC |
2077 | HIACCESS = 3; /* 3rd instruction will be safe */ |
2078 | } | |
2079 | ||
2080 | ||
2081 | 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO | |
2082 | "mtlo r<RS>" | |
2083 | *mipsI: | |
2084 | *mipsII: | |
2085 | *mipsIII: | |
2086 | *mipsIV: | |
90ad43b2 AC |
2087 | // start-sanitize-vr5400 |
2088 | *vr5400: | |
2089 | // end-sanitize-vr5400 | |
f2b30012 AC |
2090 | // start-sanitize-r5900 |
2091 | *r5900: | |
2092 | // end-sanitize-r5900 | |
2093 | *r3900: | |
2094 | // start-sanitize-tx19 | |
2095 | *tx19: | |
2096 | // end-sanitize-tx19 | |
2097 | { | |
2098 | if (LOACCESS != 0) | |
055ee297 AC |
2099 | sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n"); |
2100 | LO = GPR[RS]; | |
f2b30012 AC |
2101 | LOACCESS = 3; /* 3rd instruction will be safe */ |
2102 | } | |
2103 | ||
2104 | ||
2105 | 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT | |
2106 | "mult r<RS>, r<RT>" | |
2107 | *mipsI: | |
2108 | *mipsII: | |
2109 | *mipsIII: | |
2110 | *mipsIV: | |
90ad43b2 AC |
2111 | // start-sanitize-vr5400 |
2112 | *vr5400: | |
2113 | // end-sanitize-vr5400 | |
f2b30012 AC |
2114 | // start-sanitize-r5900 |
2115 | *r5900: | |
2116 | // end-sanitize-r5900 | |
2117 | *r3900: | |
2118 | // start-sanitize-tx19 | |
2119 | *tx19: | |
2120 | // end-sanitize-tx19 | |
2121 | { | |
2122 | signed64 prod; | |
2123 | CHECKHILO ("Multiplication"); | |
055ee297 AC |
2124 | prod = (((signed64)(signed32) GPR[RS]) |
2125 | * ((signed64)(signed32) GPR[RT])); | |
f2b30012 AC |
2126 | LO = EXTEND32 (VL4_8 (prod)); |
2127 | HI = EXTEND32 (VH4_8 (prod)); | |
2128 | } | |
2129 | ||
2130 | ||
2131 | 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU | |
2132 | "multu r<RS>, r<RT>" | |
2133 | *mipsI: | |
2134 | *mipsII: | |
2135 | *mipsIII: | |
2136 | *mipsIV: | |
90ad43b2 AC |
2137 | // start-sanitize-vr5400 |
2138 | *vr5400: | |
2139 | // end-sanitize-vr5400 | |
f2b30012 AC |
2140 | // start-sanitize-r5900 |
2141 | *r5900: | |
2142 | // end-sanitize-r5900 | |
2143 | *r3900: | |
2144 | // start-sanitize-tx19 | |
2145 | *tx19: | |
2146 | // end-sanitize-tx19 | |
2147 | { | |
2148 | unsigned64 prod; | |
2149 | CHECKHILO ("Multiplication"); | |
055ee297 AC |
2150 | prod = (((unsigned64)(unsigned32) GPR[RS]) |
2151 | * ((unsigned64)(unsigned32) GPR[RT])); | |
f2b30012 AC |
2152 | LO = EXTEND32 (VL4_8 (prod)); |
2153 | HI = EXTEND32 (VH4_8 (prod)); | |
2154 | } | |
2155 | ||
2156 | ||
2157 | 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR | |
2158 | "nor r<RD>, r<RS>, r<RT>" | |
2159 | *mipsI: | |
2160 | *mipsII: | |
2161 | *mipsIII: | |
2162 | *mipsIV: | |
90ad43b2 AC |
2163 | // start-sanitize-vr5400 |
2164 | *vr5400: | |
2165 | // end-sanitize-vr5400 | |
f2b30012 AC |
2166 | // start-sanitize-r5900 |
2167 | *r5900: | |
2168 | // end-sanitize-r5900 | |
2169 | *r3900: | |
2170 | // start-sanitize-tx19 | |
2171 | *tx19: | |
2172 | // end-sanitize-tx19 | |
2173 | { | |
055ee297 | 2174 | GPR[RD] = ~ (GPR[RS] | GPR[RT]); |
f2b30012 AC |
2175 | } |
2176 | ||
2177 | ||
2178 | 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR | |
2179 | "or r<RD>, r<RS>, r<RT>" | |
2180 | *mipsI: | |
2181 | *mipsII: | |
2182 | *mipsIII: | |
2183 | *mipsIV: | |
90ad43b2 AC |
2184 | // start-sanitize-vr5400 |
2185 | *vr5400: | |
2186 | // end-sanitize-vr5400 | |
f2b30012 AC |
2187 | // start-sanitize-r5900 |
2188 | *r5900: | |
2189 | // end-sanitize-r5900 | |
2190 | *r3900: | |
2191 | // start-sanitize-tx19 | |
2192 | *tx19: | |
2193 | // end-sanitize-tx19 | |
2194 | { | |
055ee297 | 2195 | GPR[RD] = (GPR[RS] | GPR[RT]); |
f2b30012 AC |
2196 | } |
2197 | ||
2198 | ||
2199 | 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI | |
055ee297 | 2200 | "ori r<RT>, r<RS>, <IMMEDIATE>" |
f2b30012 AC |
2201 | *mipsI: |
2202 | *mipsII: | |
2203 | *mipsIII: | |
2204 | *mipsIV: | |
90ad43b2 AC |
2205 | // start-sanitize-vr5400 |
2206 | *vr5400: | |
2207 | // end-sanitize-vr5400 | |
f2b30012 AC |
2208 | // start-sanitize-r5900 |
2209 | *r5900: | |
2210 | // end-sanitize-r5900 | |
2211 | *r3900: | |
2212 | // start-sanitize-tx19 | |
2213 | *tx19: | |
2214 | // end-sanitize-tx19 | |
2215 | { | |
055ee297 | 2216 | GPR[RT] = (GPR[RS] | IMMEDIATE); |
f2b30012 AC |
2217 | } |
2218 | ||
2219 | ||
2220 | 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF | |
2221 | *mipsIV: | |
90ad43b2 AC |
2222 | // start-sanitize-vr5400 |
2223 | *vr5400: | |
2224 | // end-sanitize-vr5400 | |
f2b30012 AC |
2225 | // start-sanitize-r5900 |
2226 | *r5900: | |
2227 | // end-sanitize-r5900 | |
2228 | { | |
2229 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2230 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2231 | int hint = ((instruction >> 16) & 0x0000001F); | |
2232 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2233 | { |
49a76833 AC |
2234 | address_word vaddr = ((unsigned64)op1 + offset); |
2235 | address_word paddr; | |
f2b30012 AC |
2236 | int uncached; |
2237 | { | |
2238 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
2239 | Prefetch(uncached,paddr,vaddr,isDATA,hint); | |
2240 | } | |
2241 | } | |
2242 | } | |
2243 | ||
2244 | 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB | |
2245 | "sb r<RT>, <OFFSET>(r<BASE>)" | |
2246 | *mipsI: | |
2247 | *mipsII: | |
2248 | *mipsIII: | |
2249 | *mipsIV: | |
90ad43b2 AC |
2250 | // start-sanitize-vr5400 |
2251 | *vr5400: | |
2252 | // end-sanitize-vr5400 | |
f2b30012 AC |
2253 | // start-sanitize-r5900 |
2254 | *r5900: | |
2255 | // end-sanitize-r5900 | |
2256 | *r3900: | |
2257 | // start-sanitize-tx19 | |
2258 | *tx19: | |
2259 | // end-sanitize-tx19 | |
2260 | { | |
2261 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2262 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2263 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2264 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2265 | { |
49a76833 AC |
2266 | address_word vaddr = ((unsigned64)op1 + offset); |
2267 | address_word paddr; | |
f2b30012 AC |
2268 | int uncached; |
2269 | { | |
2270 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2271 | { | |
2272 | unsigned64 memval = 0; | |
2273 | unsigned64 memval1 = 0; | |
2274 | unsigned64 mask = 0x7; | |
2275 | unsigned int shift = 0; | |
2276 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
2277 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
2278 | unsigned int byte; | |
2279 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
2280 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
2281 | memval = ((unsigned64) op2 << (8 * byte)); | |
2282 | { | |
2283 | StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL); | |
2284 | } | |
2285 | } | |
2286 | } | |
2287 | } | |
2288 | } | |
2289 | ||
2290 | ||
2291 | 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC | |
2292 | "sc r<RT>, <OFFSET>(r<BASE>)" | |
2293 | *mipsII: | |
2294 | *mipsIII: | |
2295 | *mipsIV: | |
90ad43b2 AC |
2296 | // start-sanitize-vr5400 |
2297 | *vr5400: | |
2298 | // end-sanitize-vr5400 | |
f2b30012 AC |
2299 | // start-sanitize-r5900 |
2300 | *r5900: | |
2301 | // end-sanitize-r5900 | |
2302 | *r3900: | |
2303 | // start-sanitize-tx19 | |
2304 | *tx19: | |
2305 | // end-sanitize-tx19 | |
2306 | { | |
2307 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2308 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2309 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2310 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2311 | { |
49a76833 AC |
2312 | address_word vaddr = ((unsigned64)op1 + offset); |
2313 | address_word paddr; | |
f2b30012 AC |
2314 | int uncached; |
2315 | if ((vaddr & 3) != 0) | |
055ee297 | 2316 | SignalExceptionAddressStore(); |
f2b30012 AC |
2317 | else |
2318 | { | |
2319 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2320 | { | |
2321 | unsigned64 memval = 0; | |
2322 | unsigned64 memval1 = 0; | |
2323 | unsigned64 mask = 0x7; | |
2324 | unsigned int byte; | |
2325 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
2326 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
2327 | memval = ((unsigned64) op2 << (8 * byte)); | |
2328 | if (LLBIT) | |
2329 | { | |
2330 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
2331 | } | |
2332 | GPR[(instruction >> 16) & 0x0000001F] = LLBIT; | |
2333 | } | |
2334 | } | |
2335 | } | |
2336 | } | |
2337 | ||
2338 | ||
2339 | 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD | |
2340 | "scd r<RT>, <OFFSET>(r<BASE>)" | |
2341 | *mipsIII: | |
2342 | *mipsIV: | |
90ad43b2 AC |
2343 | // start-sanitize-vr5400 |
2344 | *vr5400: | |
2345 | // end-sanitize-vr5400 | |
f2b30012 AC |
2346 | // start-sanitize-r5900 |
2347 | *r5900: | |
2348 | // end-sanitize-r5900 | |
2349 | *r3900: | |
2350 | // start-sanitize-tx19 | |
2351 | *tx19: | |
2352 | // end-sanitize-tx19 | |
2353 | { | |
2354 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2355 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2356 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2357 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2358 | { |
49a76833 AC |
2359 | address_word vaddr = ((unsigned64)op1 + offset); |
2360 | address_word paddr; | |
f2b30012 AC |
2361 | int uncached; |
2362 | if ((vaddr & 7) != 0) | |
055ee297 | 2363 | SignalExceptionAddressStore(); |
f2b30012 AC |
2364 | else |
2365 | { | |
2366 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2367 | { | |
2368 | unsigned64 memval = 0; | |
2369 | unsigned64 memval1 = 0; | |
2370 | memval = op2; | |
2371 | if (LLBIT) | |
2372 | { | |
2373 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
2374 | } | |
2375 | GPR[(instruction >> 16) & 0x0000001F] = LLBIT; | |
2376 | } | |
2377 | } | |
2378 | } | |
2379 | } | |
2380 | ||
2381 | ||
2382 | 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD | |
2383 | "sd r<RT>, <OFFSET>(r<BASE>)" | |
2384 | *mipsIII: | |
2385 | *mipsIV: | |
90ad43b2 AC |
2386 | // start-sanitize-vr5400 |
2387 | *vr5400: | |
2388 | // end-sanitize-vr5400 | |
f2b30012 AC |
2389 | // start-sanitize-r5900 |
2390 | *r5900: | |
2391 | // end-sanitize-r5900 | |
2392 | *r3900: | |
2393 | // start-sanitize-tx19 | |
2394 | *tx19: | |
2395 | // end-sanitize-tx19 | |
2396 | { | |
2397 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2398 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2399 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2400 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2401 | { |
49a76833 AC |
2402 | address_word vaddr = ((unsigned64)op1 + offset); |
2403 | address_word paddr; | |
f2b30012 AC |
2404 | int uncached; |
2405 | if ((vaddr & 7) != 0) | |
055ee297 | 2406 | SignalExceptionAddressStore(); |
f2b30012 AC |
2407 | else |
2408 | { | |
2409 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2410 | { | |
2411 | unsigned64 memval = 0; | |
2412 | unsigned64 memval1 = 0; | |
2413 | memval = op2; | |
2414 | { | |
2415 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
2416 | } | |
2417 | } | |
2418 | } | |
2419 | } | |
2420 | } | |
2421 | ||
2422 | ||
49a6eed5 | 2423 | 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz |
f2b30012 AC |
2424 | "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
2425 | *mipsII: | |
2426 | *mipsIII: | |
2427 | *mipsIV: | |
90ad43b2 AC |
2428 | // start-sanitize-vr5400 |
2429 | *vr5400: | |
2430 | // end-sanitize-vr5400 | |
f2b30012 AC |
2431 | // start-sanitize-r5900 |
2432 | *r5900: | |
2433 | // end-sanitize-r5900 | |
2434 | *r3900: | |
2435 | // start-sanitize-tx19 | |
2436 | *tx19: | |
2437 | // end-sanitize-tx19 | |
2438 | { | |
2439 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2440 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2441 | int destreg = ((instruction >> 16) & 0x0000001F); | |
2442 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2443 | { |
49a76833 AC |
2444 | address_word vaddr = ((unsigned64)op1 + offset); |
2445 | address_word paddr; | |
f2b30012 AC |
2446 | int uncached; |
2447 | if ((vaddr & 7) != 0) | |
055ee297 | 2448 | SignalExceptionAddressStore(); |
f2b30012 AC |
2449 | else |
2450 | { | |
2451 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2452 | { | |
2453 | unsigned64 memval = 0; | |
2454 | unsigned64 memval1 = 0; | |
2455 | memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg); | |
2456 | { | |
2457 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
2458 | } | |
2459 | } | |
2460 | } | |
2461 | } | |
2462 | } | |
2463 | ||
2464 | ||
2465 | 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL | |
2466 | "sdl r<RT>, <OFFSET>(r<BASE>)" | |
2467 | *mipsIII: | |
2468 | *mipsIV: | |
90ad43b2 AC |
2469 | // start-sanitize-vr5400 |
2470 | *vr5400: | |
2471 | // end-sanitize-vr5400 | |
f2b30012 AC |
2472 | // start-sanitize-r5900 |
2473 | *r5900: | |
2474 | // end-sanitize-r5900 | |
2475 | *r3900: | |
2476 | // start-sanitize-tx19 | |
2477 | *tx19: | |
2478 | // end-sanitize-tx19 | |
2479 | { | |
2480 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2481 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2482 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2483 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2484 | { |
49a76833 AC |
2485 | address_word vaddr = ((unsigned64)op1 + offset); |
2486 | address_word paddr; | |
f2b30012 AC |
2487 | int uncached; |
2488 | { | |
2489 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2490 | { | |
2491 | unsigned64 memval = 0; | |
2492 | unsigned64 memval1 = 0; | |
2493 | unsigned64 mask = 7; | |
2494 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
2495 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
2496 | int byte; | |
2497 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
2498 | byte = ((vaddr & mask) ^ bigend); | |
63be8feb | 2499 | if (!BigEndianMem) |
f2b30012 AC |
2500 | paddr &= ~mask; |
2501 | memval = (op2 >> (8 * (7 - byte))); | |
2502 | StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL); | |
2503 | } | |
2504 | } | |
2505 | } | |
2506 | } | |
2507 | ||
2508 | ||
2509 | 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR | |
2510 | "sdr r<RT>, <OFFSET>(r<BASE>)" | |
2511 | *mipsIII: | |
2512 | *mipsIV: | |
90ad43b2 AC |
2513 | // start-sanitize-vr5400 |
2514 | *vr5400: | |
2515 | // end-sanitize-vr5400 | |
f2b30012 AC |
2516 | // start-sanitize-r5900 |
2517 | *r5900: | |
2518 | // end-sanitize-r5900 | |
2519 | *r3900: | |
2520 | // start-sanitize-tx19 | |
2521 | *tx19: | |
2522 | // end-sanitize-tx19 | |
2523 | { | |
2524 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2525 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2526 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2527 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2528 | { |
49a76833 AC |
2529 | address_word vaddr = ((unsigned64)op1 + offset); |
2530 | address_word paddr; | |
f2b30012 AC |
2531 | int uncached; |
2532 | { | |
2533 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2534 | { | |
2535 | unsigned64 memval = 0; | |
2536 | unsigned64 memval1 = 0; | |
2537 | unsigned64 mask = 7; | |
2538 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
2539 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
2540 | int byte; | |
2541 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
2542 | byte = ((vaddr & mask) ^ bigend); | |
63be8feb | 2543 | if (!BigEndianMem) |
f2b30012 AC |
2544 | paddr &= ~mask; |
2545 | memval = ((unsigned64) op2 << (byte * 8)); | |
2546 | StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,memval1,paddr,vaddr,isREAL); | |
2547 | } | |
2548 | } | |
2549 | } | |
2550 | } | |
2551 | ||
2552 | ||
2553 | 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH | |
2554 | "sh r<RT>, <OFFSET>(r<BASE>)" | |
2555 | *mipsI: | |
2556 | *mipsII: | |
2557 | *mipsIII: | |
2558 | *mipsIV: | |
90ad43b2 AC |
2559 | // start-sanitize-vr5400 |
2560 | *vr5400: | |
2561 | // end-sanitize-vr5400 | |
f2b30012 AC |
2562 | // start-sanitize-r5900 |
2563 | *r5900: | |
2564 | // end-sanitize-r5900 | |
2565 | *r3900: | |
2566 | // start-sanitize-tx19 | |
2567 | *tx19: | |
2568 | // end-sanitize-tx19 | |
2569 | { | |
2570 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2571 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2572 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2573 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2574 | { |
49a76833 AC |
2575 | address_word vaddr = ((unsigned64)op1 + offset); |
2576 | address_word paddr; | |
f2b30012 AC |
2577 | int uncached; |
2578 | if ((vaddr & 1) != 0) | |
055ee297 | 2579 | SignalExceptionAddressStore(); |
f2b30012 AC |
2580 | else |
2581 | { | |
2582 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2583 | { | |
2584 | unsigned64 memval = 0; | |
2585 | unsigned64 memval1 = 0; | |
2586 | unsigned64 mask = 0x7; | |
2587 | unsigned int shift = 1; | |
2588 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
2589 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
2590 | unsigned int byte; | |
2591 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
2592 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
2593 | memval = ((unsigned64) op2 << (8 * byte)); | |
2594 | { | |
2595 | StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL); | |
2596 | } | |
2597 | } | |
2598 | } | |
2599 | } | |
2600 | } | |
2601 | ||
2602 | ||
055ee297 AC |
2603 | 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL |
2604 | "sll r<RD>, r<RT>, <SHIFT>" | |
f2b30012 AC |
2605 | *mipsI: |
2606 | *mipsII: | |
2607 | *mipsIII: | |
2608 | *mipsIV: | |
90ad43b2 AC |
2609 | // start-sanitize-vr5400 |
2610 | *vr5400: | |
2611 | // end-sanitize-vr5400 | |
f2b30012 AC |
2612 | // start-sanitize-r5900 |
2613 | *r5900: | |
2614 | // end-sanitize-r5900 | |
2615 | *r3900: | |
2616 | // start-sanitize-tx19 | |
2617 | *tx19: | |
2618 | // end-sanitize-tx19 | |
2619 | { | |
055ee297 AC |
2620 | int s = SHIFT; |
2621 | unsigned32 temp = (GPR[RT] << s); | |
2622 | GPR[RD] = EXTEND32 (temp); | |
f2b30012 AC |
2623 | } |
2624 | ||
2625 | ||
055ee297 | 2626 | 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV |
f2b30012 AC |
2627 | "sllv r<RD>, r<RT>, r<RS>" |
2628 | *mipsI: | |
2629 | *mipsII: | |
2630 | *mipsIII: | |
2631 | *mipsIV: | |
90ad43b2 AC |
2632 | // start-sanitize-vr5400 |
2633 | *vr5400: | |
2634 | // end-sanitize-vr5400 | |
f2b30012 AC |
2635 | // start-sanitize-r5900 |
2636 | *r5900: | |
2637 | // end-sanitize-r5900 | |
2638 | *r3900: | |
2639 | // start-sanitize-tx19 | |
2640 | *tx19: | |
2641 | // end-sanitize-tx19 | |
2642 | { | |
055ee297 AC |
2643 | int s = MASKED (GPR[RS], 4, 0); |
2644 | unsigned32 temp = (GPR[RT] << s); | |
2645 | GPR[RD] = EXTEND32 (temp); | |
f2b30012 AC |
2646 | } |
2647 | ||
2648 | ||
2649 | 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT | |
2650 | "slt r<RD>, r<RS>, r<RT>" | |
2651 | *mipsI: | |
2652 | *mipsII: | |
2653 | *mipsIII: | |
2654 | *mipsIV: | |
90ad43b2 AC |
2655 | // start-sanitize-vr5400 |
2656 | *vr5400: | |
2657 | // end-sanitize-vr5400 | |
f2b30012 AC |
2658 | // start-sanitize-r5900 |
2659 | *r5900: | |
2660 | // end-sanitize-r5900 | |
2661 | *r3900: | |
2662 | // start-sanitize-tx19 | |
2663 | *tx19: | |
2664 | // end-sanitize-tx19 | |
2665 | { | |
055ee297 | 2666 | GPR[RD] = (GPR[RS] < GPR[RT]); |
f2b30012 AC |
2667 | } |
2668 | ||
2669 | ||
2670 | 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI | |
055ee297 | 2671 | "slti r<RT>, r<RS>, <IMMEDIATE>" |
f2b30012 AC |
2672 | *mipsI: |
2673 | *mipsII: | |
2674 | *mipsIII: | |
2675 | *mipsIV: | |
90ad43b2 AC |
2676 | // start-sanitize-vr5400 |
2677 | *vr5400: | |
2678 | // end-sanitize-vr5400 | |
f2b30012 AC |
2679 | // start-sanitize-r5900 |
2680 | *r5900: | |
2681 | // end-sanitize-r5900 | |
2682 | *r3900: | |
2683 | // start-sanitize-tx19 | |
2684 | *tx19: | |
2685 | // end-sanitize-tx19 | |
2686 | { | |
055ee297 | 2687 | GPR[RT] = (GPR[RS] < EXTEND16 (IMMEDIATE)); |
f2b30012 AC |
2688 | } |
2689 | ||
2690 | ||
2691 | 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU | |
055ee297 | 2692 | "sltiu r<RT>, r<RS>, <IMMEDIATE>" |
f2b30012 AC |
2693 | *mipsI: |
2694 | *mipsII: | |
2695 | *mipsIII: | |
2696 | *mipsIV: | |
90ad43b2 AC |
2697 | // start-sanitize-vr5400 |
2698 | *vr5400: | |
2699 | // end-sanitize-vr5400 | |
f2b30012 AC |
2700 | // start-sanitize-r5900 |
2701 | *r5900: | |
2702 | // end-sanitize-r5900 | |
2703 | *r3900: | |
2704 | // start-sanitize-tx19 | |
2705 | *tx19: | |
2706 | // end-sanitize-tx19 | |
2707 | { | |
055ee297 | 2708 | GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE)); |
f2b30012 AC |
2709 | } |
2710 | ||
2711 | 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU | |
2712 | "sltu r<RD>, r<RS>, r<RT>" | |
2713 | *mipsI: | |
2714 | *mipsII: | |
2715 | *mipsIII: | |
2716 | *mipsIV: | |
90ad43b2 AC |
2717 | // start-sanitize-vr5400 |
2718 | *vr5400: | |
2719 | // end-sanitize-vr5400 | |
f2b30012 AC |
2720 | // start-sanitize-r5900 |
2721 | *r5900: | |
2722 | // end-sanitize-r5900 | |
2723 | *r3900: | |
2724 | // start-sanitize-tx19 | |
2725 | *tx19: | |
2726 | // end-sanitize-tx19 | |
2727 | { | |
055ee297 | 2728 | GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]); |
f2b30012 AC |
2729 | } |
2730 | ||
2731 | ||
055ee297 AC |
2732 | 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA |
2733 | "sra r<RD>, r<RT>, <SHIFT>" | |
f2b30012 AC |
2734 | *mipsI: |
2735 | *mipsII: | |
2736 | *mipsIII: | |
2737 | *mipsIV: | |
90ad43b2 AC |
2738 | // start-sanitize-vr5400 |
2739 | *vr5400: | |
2740 | // end-sanitize-vr5400 | |
f2b30012 AC |
2741 | // start-sanitize-r5900 |
2742 | *r5900: | |
2743 | // end-sanitize-r5900 | |
2744 | *r3900: | |
2745 | // start-sanitize-tx19 | |
2746 | *tx19: | |
2747 | // end-sanitize-tx19 | |
2748 | { | |
055ee297 AC |
2749 | int s = SHIFT; |
2750 | signed32 temp = (signed32) GPR[RT] >> s; | |
2751 | GPR[RD] = EXTEND32 (temp); | |
f2b30012 AC |
2752 | } |
2753 | ||
2754 | ||
2755 | 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV | |
2756 | "srav r<RD>, r<RT>, r<RS>" | |
2757 | *mipsI: | |
2758 | *mipsII: | |
2759 | *mipsIII: | |
2760 | *mipsIV: | |
90ad43b2 AC |
2761 | // start-sanitize-vr5400 |
2762 | *vr5400: | |
2763 | // end-sanitize-vr5400 | |
f2b30012 AC |
2764 | // start-sanitize-r5900 |
2765 | *r5900: | |
2766 | // end-sanitize-r5900 | |
2767 | *r3900: | |
2768 | // start-sanitize-tx19 | |
2769 | *tx19: | |
2770 | // end-sanitize-tx19 | |
2771 | { | |
055ee297 AC |
2772 | int s = MASKED (GPR[RS], 4, 0); |
2773 | signed32 temp = (signed32) GPR[RT] >> s; | |
2774 | GPR[RD] = EXTEND32 (temp); | |
f2b30012 AC |
2775 | } |
2776 | ||
2777 | ||
055ee297 AC |
2778 | 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL |
2779 | "srl r<RD>, r<RT>, <SHIFT>" | |
f2b30012 AC |
2780 | *mipsI: |
2781 | *mipsII: | |
2782 | *mipsIII: | |
2783 | *mipsIV: | |
90ad43b2 AC |
2784 | // start-sanitize-vr5400 |
2785 | *vr5400: | |
2786 | // end-sanitize-vr5400 | |
f2b30012 AC |
2787 | // start-sanitize-r5900 |
2788 | *r5900: | |
2789 | // end-sanitize-r5900 | |
2790 | *r3900: | |
2791 | // start-sanitize-tx19 | |
2792 | *tx19: | |
2793 | // end-sanitize-tx19 | |
2794 | { | |
055ee297 AC |
2795 | int s = SHIFT; |
2796 | unsigned32 temp = (unsigned32) GPR[RT] >> s; | |
2797 | GPR[RD] = EXTEND32 (temp); | |
f2b30012 AC |
2798 | } |
2799 | ||
2800 | ||
2801 | 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV | |
2802 | "srlv r<RD>, r<RT>, r<RS>" | |
2803 | *mipsI: | |
2804 | *mipsII: | |
2805 | *mipsIII: | |
2806 | *mipsIV: | |
90ad43b2 AC |
2807 | // start-sanitize-vr5400 |
2808 | *vr5400: | |
2809 | // end-sanitize-vr5400 | |
f2b30012 AC |
2810 | // start-sanitize-r5900 |
2811 | *r5900: | |
2812 | // end-sanitize-r5900 | |
2813 | *r3900: | |
2814 | // start-sanitize-tx19 | |
2815 | *tx19: | |
2816 | // end-sanitize-tx19 | |
2817 | { | |
055ee297 AC |
2818 | int s = MASKED (GPR[RS], 4, 0); |
2819 | unsigned32 temp = (unsigned32) GPR[RT] >> s; | |
2820 | GPR[RD] = EXTEND32 (temp); | |
f2b30012 AC |
2821 | } |
2822 | ||
2823 | ||
2824 | 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB | |
2825 | "sub r<RD>, r<RS>, r<RT>" | |
2826 | *mipsI: | |
2827 | *mipsII: | |
2828 | *mipsIII: | |
2829 | *mipsIV: | |
90ad43b2 AC |
2830 | // start-sanitize-vr5400 |
2831 | *vr5400: | |
2832 | // end-sanitize-vr5400 | |
f2b30012 AC |
2833 | // start-sanitize-r5900 |
2834 | *r5900: | |
2835 | // end-sanitize-r5900 | |
2836 | *r3900: | |
2837 | // start-sanitize-tx19 | |
2838 | *tx19: | |
2839 | // end-sanitize-tx19 | |
2840 | { | |
055ee297 AC |
2841 | ALU32_BEGIN (GPR[RS]); |
2842 | ALU32_SUB (GPR[RT]); | |
2843 | ALU32_END (GPR[RD]); | |
f2b30012 AC |
2844 | } |
2845 | ||
2846 | ||
2847 | 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU | |
2848 | "subu r<RD>, r<RS>, r<RT>" | |
2849 | *mipsI: | |
2850 | *mipsII: | |
2851 | *mipsIII: | |
2852 | *mipsIV: | |
90ad43b2 AC |
2853 | // start-sanitize-vr5400 |
2854 | *vr5400: | |
2855 | // end-sanitize-vr5400 | |
f2b30012 AC |
2856 | // start-sanitize-r5900 |
2857 | *r5900: | |
2858 | // end-sanitize-r5900 | |
2859 | *r3900: | |
2860 | // start-sanitize-tx19 | |
2861 | *tx19: | |
2862 | // end-sanitize-tx19 | |
2863 | { | |
055ee297 | 2864 | GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]); |
f2b30012 AC |
2865 | } |
2866 | ||
2867 | ||
2868 | 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW | |
2869 | "sw r<RT>, <OFFSET>(r<BASE>)" | |
2870 | *mipsI: | |
2871 | *mipsII: | |
2872 | *mipsIII: | |
2873 | *mipsIV: | |
90ad43b2 AC |
2874 | // start-sanitize-vr5400 |
2875 | *vr5400: | |
2876 | // end-sanitize-vr5400 | |
f2b30012 AC |
2877 | // start-sanitize-r5900 |
2878 | *r5900: | |
2879 | // end-sanitize-r5900 | |
2880 | *r3900: | |
2881 | // start-sanitize-tx19 | |
2882 | *tx19: | |
2883 | // end-sanitize-tx19 | |
2884 | { | |
2885 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2886 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2887 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2888 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2889 | { |
49a76833 AC |
2890 | address_word vaddr = ((unsigned64)op1 + offset); |
2891 | address_word paddr; | |
f2b30012 AC |
2892 | int uncached; |
2893 | if ((vaddr & 3) != 0) | |
055ee297 | 2894 | SignalExceptionAddressStore(); |
f2b30012 AC |
2895 | else |
2896 | { | |
2897 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2898 | { | |
2899 | unsigned64 memval = 0; | |
2900 | unsigned64 memval1 = 0; | |
2901 | unsigned64 mask = 0x7; | |
2902 | unsigned int byte; | |
2903 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
2904 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
2905 | memval = ((unsigned64) op2 << (8 * byte)); | |
2906 | { | |
2907 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
2908 | } | |
2909 | } | |
2910 | } | |
2911 | } | |
2912 | } | |
2913 | ||
2914 | ||
085c1cb9 | 2915 | 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz |
f2b30012 AC |
2916 | "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
2917 | *mipsI: | |
2918 | *mipsII: | |
2919 | *mipsIII: | |
2920 | *mipsIV: | |
90ad43b2 AC |
2921 | // start-sanitize-vr5400 |
2922 | *vr5400: | |
2923 | // end-sanitize-vr5400 | |
f2b30012 AC |
2924 | // start-sanitize-r5900 |
2925 | *r5900: | |
2926 | // end-sanitize-r5900 | |
2927 | *r3900: | |
2928 | // start-sanitize-tx19 | |
2929 | *tx19: | |
2930 | // end-sanitize-tx19 | |
2931 | { | |
2932 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2933 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2934 | int destreg = ((instruction >> 16) & 0x0000001F); | |
2935 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2936 | { |
49a76833 AC |
2937 | address_word vaddr = ((unsigned64)op1 + offset); |
2938 | address_word paddr; | |
f2b30012 AC |
2939 | int uncached; |
2940 | if ((vaddr & 3) != 0) | |
055ee297 | 2941 | SignalExceptionAddressStore(); |
f2b30012 AC |
2942 | else |
2943 | { | |
2944 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2945 | { | |
2946 | unsigned64 memval = 0; | |
2947 | unsigned64 memval1 = 0; | |
2948 | unsigned64 mask = 0x7; | |
2949 | unsigned int byte; | |
2950 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
2951 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
2952 | memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte)); | |
2953 | { | |
2954 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
2955 | } | |
2956 | } | |
2957 | } | |
2958 | } | |
2959 | } | |
2960 | ||
2961 | ||
2962 | 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL | |
2963 | "swl r<RT>, <OFFSET>(r<BASE>)" | |
2964 | *mipsI: | |
2965 | *mipsII: | |
2966 | *mipsIII: | |
2967 | *mipsIV: | |
90ad43b2 AC |
2968 | // start-sanitize-vr5400 |
2969 | *vr5400: | |
2970 | // end-sanitize-vr5400 | |
f2b30012 AC |
2971 | // start-sanitize-r5900 |
2972 | *r5900: | |
2973 | // end-sanitize-r5900 | |
2974 | *r3900: | |
2975 | // start-sanitize-tx19 | |
2976 | *tx19: | |
2977 | // end-sanitize-tx19 | |
2978 | { | |
2979 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2980 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2981 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2982 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2983 | { |
49a76833 AC |
2984 | address_word vaddr = ((unsigned64)op1 + offset); |
2985 | address_word paddr; | |
f2b30012 AC |
2986 | int uncached; |
2987 | { | |
2988 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2989 | { | |
2990 | unsigned64 memval = 0; | |
2991 | unsigned64 memval1 = 0; | |
2992 | unsigned64 mask = 3; | |
2993 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
2994 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
2995 | int byte; | |
2996 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
2997 | byte = ((vaddr & mask) ^ bigend); | |
63be8feb | 2998 | if (!BigEndianMem) |
f2b30012 AC |
2999 | paddr &= ~mask; |
3000 | memval = (op2 >> (8 * (3 - byte))); | |
3001 | if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { | |
3002 | memval <<= 32; | |
3003 | } | |
3004 | StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL); | |
3005 | } | |
3006 | } | |
3007 | } | |
3008 | } | |
3009 | ||
3010 | ||
3011 | 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR | |
3012 | "swr r<RT>, <OFFSET>(r<BASE>)" | |
3013 | *mipsI: | |
3014 | *mipsII: | |
3015 | *mipsIII: | |
3016 | *mipsIV: | |
90ad43b2 AC |
3017 | // start-sanitize-vr5400 |
3018 | *vr5400: | |
3019 | // end-sanitize-vr5400 | |
f2b30012 AC |
3020 | // start-sanitize-r5900 |
3021 | *r5900: | |
3022 | // end-sanitize-r5900 | |
3023 | *r3900: | |
3024 | // start-sanitize-tx19 | |
3025 | *tx19: | |
3026 | // end-sanitize-tx19 | |
3027 | { | |
3028 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3029 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
3030 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
3031 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 3032 | { |
49a76833 AC |
3033 | address_word vaddr = ((unsigned64)op1 + offset); |
3034 | address_word paddr; | |
f2b30012 AC |
3035 | int uncached; |
3036 | { | |
3037 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
3038 | { | |
3039 | unsigned64 memval = 0; | |
3040 | unsigned64 memval1 = 0; | |
3041 | unsigned64 mask = 3; | |
3042 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
3043 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
3044 | int byte; | |
3045 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
3046 | byte = ((vaddr & mask) ^ bigend); | |
63be8feb | 3047 | if (!BigEndianMem) |
f2b30012 AC |
3048 | paddr &= ~mask; |
3049 | memval = ((unsigned64) op2 << (byte * 8)); | |
3050 | if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { | |
3051 | memval <<= 32; | |
3052 | } | |
3053 | StoreMemory(uncached,(AccessLength_WORD - byte),memval,memval1,paddr,vaddr,isREAL); | |
3054 | } | |
3055 | } | |
3056 | } | |
3057 | } | |
3058 | ||
3059 | ||
3060 | 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC | |
3061 | "sync":STYPE == 0 | |
3062 | "sync <STYPE>" | |
3063 | *mipsII: | |
3064 | *mipsIII: | |
3065 | *mipsIV: | |
90ad43b2 AC |
3066 | // start-sanitize-vr5400 |
3067 | *vr5400: | |
3068 | // end-sanitize-vr5400 | |
f2b30012 AC |
3069 | // start-sanitize-r5900 |
3070 | *r5900: | |
3071 | // end-sanitize-r5900 | |
3072 | *r3900: | |
3073 | // start-sanitize-tx19 | |
3074 | *tx19: | |
3075 | // end-sanitize-tx19 | |
3076 | { | |
085c1cb9 | 3077 | SyncOperation (STYPE); |
f2b30012 AC |
3078 | } |
3079 | ||
3080 | ||
3081 | 000000,20.CODE,001100:SPECIAL:32::SYSCALL | |
3082 | "syscall <CODE>" | |
3083 | *mipsI: | |
3084 | *mipsII: | |
3085 | *mipsIII: | |
3086 | *mipsIV: | |
90ad43b2 AC |
3087 | // start-sanitize-vr5400 |
3088 | *vr5400: | |
3089 | // end-sanitize-vr5400 | |
f2b30012 AC |
3090 | // start-sanitize-r5900 |
3091 | *r5900: | |
3092 | // end-sanitize-r5900 | |
3093 | *r3900: | |
3094 | // start-sanitize-tx19 | |
3095 | *tx19: | |
3096 | // end-sanitize-tx19 | |
3097 | { | |
055ee297 | 3098 | SignalException(SystemCall, instruction_0); |
f2b30012 AC |
3099 | } |
3100 | ||
3101 | ||
3102 | 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ | |
3103 | "teq r<RS>, r<RT>" | |
3104 | *mipsII: | |
3105 | *mipsIII: | |
3106 | *mipsIV: | |
90ad43b2 AC |
3107 | // start-sanitize-vr5400 |
3108 | *vr5400: | |
3109 | // end-sanitize-vr5400 | |
f2b30012 AC |
3110 | // start-sanitize-r5900 |
3111 | *r5900: | |
3112 | // end-sanitize-r5900 | |
3113 | *r3900: | |
3114 | // start-sanitize-tx19 | |
3115 | *tx19: | |
3116 | // end-sanitize-tx19 | |
3117 | { | |
055ee297 AC |
3118 | if (GPR[RS] == GPR[RT]) |
3119 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3120 | } |
3121 | ||
3122 | ||
3123 | 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI | |
3124 | "teqi r<RS>, <IMMEDIATE>" | |
3125 | *mipsII: | |
3126 | *mipsIII: | |
3127 | *mipsIV: | |
90ad43b2 AC |
3128 | // start-sanitize-vr5400 |
3129 | *vr5400: | |
3130 | // end-sanitize-vr5400 | |
f2b30012 AC |
3131 | // start-sanitize-r5900 |
3132 | *r5900: | |
3133 | // end-sanitize-r5900 | |
3134 | *r3900: | |
3135 | // start-sanitize-tx19 | |
3136 | *tx19: | |
3137 | // end-sanitize-tx19 | |
3138 | { | |
055ee297 AC |
3139 | if (GPR[RS] == EXTEND16 (IMMEDIATE)) |
3140 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3141 | } |
3142 | ||
3143 | ||
3144 | 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE | |
3145 | "tge r<RS>, r<RT>" | |
3146 | *mipsII: | |
3147 | *mipsIII: | |
3148 | *mipsIV: | |
90ad43b2 AC |
3149 | // start-sanitize-vr5400 |
3150 | *vr5400: | |
3151 | // end-sanitize-vr5400 | |
f2b30012 AC |
3152 | // start-sanitize-r5900 |
3153 | *r5900: | |
3154 | // end-sanitize-r5900 | |
3155 | *r3900: | |
3156 | // start-sanitize-tx19 | |
3157 | *tx19: | |
3158 | // end-sanitize-tx19 | |
3159 | { | |
055ee297 AC |
3160 | if (GPR[RS] >= GPR[RT]) |
3161 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3162 | } |
3163 | ||
3164 | ||
3165 | 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI | |
3166 | "tgei r<RS>, <IMMEDIATE>" | |
3167 | *mipsII: | |
3168 | *mipsIII: | |
3169 | *mipsIV: | |
90ad43b2 AC |
3170 | // start-sanitize-vr5400 |
3171 | *vr5400: | |
3172 | // end-sanitize-vr5400 | |
f2b30012 AC |
3173 | // start-sanitize-r5900 |
3174 | *r5900: | |
3175 | // end-sanitize-r5900 | |
3176 | *r3900: | |
3177 | // start-sanitize-tx19 | |
3178 | *tx19: | |
3179 | // end-sanitize-tx19 | |
3180 | { | |
055ee297 AC |
3181 | if (GPR[RS] >= EXTEND16 (IMMEDIATE)) |
3182 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3183 | } |
3184 | ||
3185 | ||
3186 | 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU | |
3187 | "tgeiu r<RS>, <IMMEDIATE>" | |
3188 | *mipsII: | |
3189 | *mipsIII: | |
3190 | *mipsIV: | |
90ad43b2 AC |
3191 | // start-sanitize-vr5400 |
3192 | *vr5400: | |
3193 | // end-sanitize-vr5400 | |
f2b30012 AC |
3194 | // start-sanitize-r5900 |
3195 | *r5900: | |
3196 | // end-sanitize-r5900 | |
3197 | *r3900: | |
3198 | // start-sanitize-tx19 | |
3199 | *tx19: | |
3200 | // end-sanitize-tx19 | |
3201 | { | |
055ee297 AC |
3202 | if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE)) |
3203 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3204 | } |
3205 | ||
3206 | ||
3207 | 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU | |
3208 | "tgeu r<RS>, r<RT>" | |
3209 | *mipsII: | |
3210 | *mipsIII: | |
3211 | *mipsIV: | |
90ad43b2 AC |
3212 | // start-sanitize-vr5400 |
3213 | *vr5400: | |
3214 | // end-sanitize-vr5400 | |
f2b30012 AC |
3215 | // start-sanitize-r5900 |
3216 | *r5900: | |
3217 | // end-sanitize-r5900 | |
3218 | *r3900: | |
3219 | // start-sanitize-tx19 | |
3220 | *tx19: | |
3221 | // end-sanitize-tx19 | |
3222 | { | |
055ee297 AC |
3223 | if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT]) |
3224 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3225 | } |
3226 | ||
3227 | ||
3228 | 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT | |
3229 | "tlt r<RS>, r<RT>" | |
3230 | *mipsII: | |
3231 | *mipsIII: | |
3232 | *mipsIV: | |
90ad43b2 AC |
3233 | // start-sanitize-vr5400 |
3234 | *vr5400: | |
3235 | // end-sanitize-vr5400 | |
f2b30012 AC |
3236 | // start-sanitize-r5900 |
3237 | *r5900: | |
3238 | // end-sanitize-r5900 | |
3239 | *r3900: | |
3240 | // start-sanitize-tx19 | |
3241 | *tx19: | |
3242 | // end-sanitize-tx19 | |
3243 | { | |
055ee297 AC |
3244 | if (GPR[RS] < GPR[RT]) |
3245 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3246 | } |
3247 | ||
3248 | ||
3249 | 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI | |
3250 | "tlti r<RS>, <IMMEDIATE>" | |
3251 | *mipsII: | |
3252 | *mipsIII: | |
3253 | *mipsIV: | |
90ad43b2 AC |
3254 | // start-sanitize-vr5400 |
3255 | *vr5400: | |
3256 | // end-sanitize-vr5400 | |
f2b30012 AC |
3257 | // start-sanitize-r5900 |
3258 | *r5900: | |
3259 | // end-sanitize-r5900 | |
3260 | *r3900: | |
3261 | // start-sanitize-tx19 | |
3262 | *tx19: | |
3263 | // end-sanitize-tx19 | |
3264 | { | |
055ee297 AC |
3265 | if (GPR[RS] < EXTEND16 (IMMEDIATE)) |
3266 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3267 | } |
3268 | ||
3269 | ||
3270 | 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU | |
3271 | "tltiu r<RS>, <IMMEDIATE>" | |
3272 | *mipsII: | |
3273 | *mipsIII: | |
3274 | *mipsIV: | |
90ad43b2 AC |
3275 | // start-sanitize-vr5400 |
3276 | *vr5400: | |
3277 | // end-sanitize-vr5400 | |
f2b30012 AC |
3278 | // start-sanitize-r5900 |
3279 | *r5900: | |
3280 | // end-sanitize-r5900 | |
3281 | *r3900: | |
3282 | // start-sanitize-tx19 | |
3283 | *tx19: | |
3284 | // end-sanitize-tx19 | |
3285 | { | |
055ee297 AC |
3286 | if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE)) |
3287 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3288 | } |
3289 | ||
3290 | ||
3291 | 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU | |
3292 | "tltu r<RS>, r<RT>" | |
3293 | *mipsII: | |
3294 | *mipsIII: | |
3295 | *mipsIV: | |
90ad43b2 AC |
3296 | // start-sanitize-vr5400 |
3297 | *vr5400: | |
3298 | // end-sanitize-vr5400 | |
f2b30012 AC |
3299 | // start-sanitize-r5900 |
3300 | *r5900: | |
3301 | // end-sanitize-r5900 | |
3302 | *r3900: | |
3303 | // start-sanitize-tx19 | |
3304 | *tx19: | |
3305 | // end-sanitize-tx19 | |
3306 | { | |
055ee297 AC |
3307 | if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]) |
3308 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3309 | } |
3310 | ||
3311 | ||
3312 | 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE | |
3313 | "tne r<RS>, r<RT>" | |
3314 | *mipsII: | |
3315 | *mipsIII: | |
3316 | *mipsIV: | |
90ad43b2 AC |
3317 | // start-sanitize-vr5400 |
3318 | *vr5400: | |
3319 | // end-sanitize-vr5400 | |
f2b30012 AC |
3320 | // start-sanitize-r5900 |
3321 | *r5900: | |
3322 | // end-sanitize-r5900 | |
3323 | *r3900: | |
3324 | // start-sanitize-tx19 | |
3325 | *tx19: | |
3326 | // end-sanitize-tx19 | |
3327 | { | |
055ee297 AC |
3328 | if (GPR[RS] != GPR[RT]) |
3329 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3330 | } |
3331 | ||
3332 | ||
3333 | 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI | |
3334 | "tne r<RS>, <IMMEDIATE>" | |
3335 | *mipsII: | |
3336 | *mipsIII: | |
3337 | *mipsIV: | |
90ad43b2 AC |
3338 | // start-sanitize-vr5400 |
3339 | *vr5400: | |
3340 | // end-sanitize-vr5400 | |
f2b30012 AC |
3341 | // start-sanitize-r5900 |
3342 | *r5900: | |
3343 | // end-sanitize-r5900 | |
3344 | *r3900: | |
3345 | // start-sanitize-tx19 | |
3346 | *tx19: | |
3347 | // end-sanitize-tx19 | |
3348 | { | |
055ee297 AC |
3349 | if (GPR[RS] != EXTEND16 (IMMEDIATE)) |
3350 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3351 | } |
3352 | ||
3353 | ||
3354 | 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR | |
3355 | "xor r<RD>, r<RS>, r<RT>" | |
3356 | *mipsI: | |
3357 | *mipsII: | |
3358 | *mipsIII: | |
3359 | *mipsIV: | |
90ad43b2 AC |
3360 | // start-sanitize-vr5400 |
3361 | *vr5400: | |
3362 | // end-sanitize-vr5400 | |
f2b30012 AC |
3363 | // start-sanitize-r5900 |
3364 | *r5900: | |
3365 | // end-sanitize-r5900 | |
3366 | *r3900: | |
3367 | // start-sanitize-tx19 | |
3368 | *tx19: | |
3369 | // end-sanitize-tx19 | |
3370 | { | |
055ee297 | 3371 | GPR[RD] = GPR[RS] ^ GPR[RT]; |
f2b30012 AC |
3372 | } |
3373 | ||
3374 | ||
3375 | 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI | |
055ee297 | 3376 | "xori r<RT>, r<RS>, <IMMEDIATE>" |
f2b30012 AC |
3377 | *mipsI: |
3378 | *mipsII: | |
3379 | *mipsIII: | |
3380 | *mipsIV: | |
90ad43b2 AC |
3381 | // start-sanitize-vr5400 |
3382 | *vr5400: | |
3383 | // end-sanitize-vr5400 | |
f2b30012 AC |
3384 | // start-sanitize-r5900 |
3385 | *r5900: | |
3386 | // end-sanitize-r5900 | |
3387 | *r3900: | |
3388 | // start-sanitize-tx19 | |
3389 | *tx19: | |
3390 | // end-sanitize-tx19 | |
3391 | { | |
055ee297 | 3392 | GPR[RT] = GPR[RS] ^ IMMEDIATE; |
f2b30012 AC |
3393 | } |
3394 | ||
3395 | \f | |
3396 | // | |
3397 | // MIPS Architecture: | |
3398 | // | |
3399 | // FPU Instruction Set (COP1 & COP1X) | |
3400 | // | |
3401 | ||
3402 | ||
89d09738 | 3403 | :%s::::FMT:int fmt |
055ee297 AC |
3404 | { |
3405 | switch (fmt) | |
3406 | { | |
3407 | case fmt_single: return "s"; | |
3408 | case fmt_double: return "d"; | |
3409 | case fmt_word: return "w"; | |
3410 | case fmt_long: return "l"; | |
3411 | default: return "?"; | |
3412 | } | |
3413 | } | |
3414 | ||
89d09738 | 3415 | :%s::::TF:int tf |
055ee297 AC |
3416 | { |
3417 | if (tf) | |
3418 | return "t"; | |
3419 | else | |
3420 | return "f"; | |
3421 | } | |
3422 | ||
89d09738 | 3423 | :%s::::ND:int nd |
055ee297 AC |
3424 | { |
3425 | if (nd) | |
3426 | return "l"; | |
3427 | else | |
3428 | return ""; | |
3429 | } | |
3430 | ||
89d09738 | 3431 | :%s::::COND:int cond |
055ee297 AC |
3432 | { |
3433 | switch (cond) | |
3434 | { | |
3435 | case 00: return "f"; | |
3436 | case 01: return "un"; | |
3437 | case 02: return "eq"; | |
3438 | case 03: return "ueq"; | |
3439 | case 04: return "olt"; | |
3440 | case 05: return "ult"; | |
3441 | case 06: return "ole"; | |
3442 | case 07: return "ule"; | |
3443 | case 010: return "sf"; | |
3444 | case 011: return "ngle"; | |
3445 | case 012: return "seq"; | |
3446 | case 013: return "ngl"; | |
3447 | case 014: return "lt"; | |
3448 | case 015: return "nge"; | |
3449 | case 016: return "le"; | |
3450 | case 017: return "ngt"; | |
3451 | default: return "?"; | |
3452 | } | |
3453 | } | |
3454 | ||
3455 | ||
f2b30012 AC |
3456 | 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt |
3457 | "abs.%s<FMT> f<FD>, f<FS>" | |
3458 | *mipsI: | |
3459 | *mipsII: | |
3460 | *mipsIII: | |
3461 | *mipsIV: | |
90ad43b2 AC |
3462 | // start-sanitize-vr5400 |
3463 | *vr5400: | |
3464 | // end-sanitize-vr5400 | |
f2b30012 AC |
3465 | // start-sanitize-r5900 |
3466 | *r5900: | |
3467 | // end-sanitize-r5900 | |
3468 | *r3900: | |
3469 | // start-sanitize-tx19 | |
3470 | *tx19: | |
3471 | // end-sanitize-tx19 | |
3472 | { | |
3473 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3474 | int destreg = ((instruction >> 6) & 0x0000001F); |
3475 | int fs = ((instruction >> 11) & 0x0000001F); | |
3476 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3477 | { |
3478 | if ((format != fmt_single) && (format != fmt_double)) | |
3479 | SignalException(ReservedInstruction,instruction); | |
3480 | else | |
3481 | StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format)); | |
3482 | } | |
3483 | } | |
3484 | ||
3485 | ||
055ee297 AC |
3486 | |
3487 | ||
3488 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD | |
f2b30012 AC |
3489 | "add.%s<FMT> f<FD>, f<FS>, f<FT>" |
3490 | *mipsI: | |
3491 | *mipsII: | |
3492 | *mipsIII: | |
3493 | *mipsIV: | |
90ad43b2 AC |
3494 | // start-sanitize-vr5400 |
3495 | *vr5400: | |
3496 | // end-sanitize-vr5400 | |
f2b30012 AC |
3497 | // start-sanitize-r5900 |
3498 | *r5900: | |
3499 | // end-sanitize-r5900 | |
3500 | *r3900: | |
3501 | // start-sanitize-tx19 | |
3502 | *tx19: | |
3503 | // end-sanitize-tx19 | |
3504 | { | |
3505 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3506 | int destreg = ((instruction >> 6) & 0x0000001F); |
3507 | int fs = ((instruction >> 11) & 0x0000001F); | |
3508 | int ft = ((instruction >> 16) & 0x0000001F); | |
3509 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3510 | { |
3511 | if ((format != fmt_single) && (format != fmt_double)) | |
055ee297 | 3512 | SignalException(ReservedInstruction, instruction); |
f2b30012 AC |
3513 | else |
3514 | StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format)); | |
3515 | } | |
3516 | } | |
3517 | ||
3518 | ||
3519 | // | |
3520 | // FIXME: This does not correctly resolve mipsI-mipsIV differences. | |
3521 | // | |
3522 | // BC1F | |
3523 | // BC1FL | |
3524 | // BC1T | |
3525 | // BC1TL | |
055ee297 AC |
3526 | 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1 |
3527 | "bc1%s<TF>%s<ND> <OFFSET>":CC == 0 | |
3528 | "bc1%s<TF>%s<ND> <CC>, <OFFSET>" | |
f2b30012 AC |
3529 | *mipsI: |
3530 | *mipsII: | |
3531 | *mipsIII: | |
3532 | *mipsIV: | |
90ad43b2 AC |
3533 | // start-sanitize-vr5400 |
3534 | *vr5400: | |
3535 | // end-sanitize-vr5400 | |
f2b30012 AC |
3536 | // start-sanitize-r5900 |
3537 | *r5900: | |
3538 | // end-sanitize-r5900 | |
3539 | *r3900: | |
3540 | // start-sanitize-tx19 | |
3541 | *tx19: | |
3542 | // end-sanitize-tx19 | |
3543 | { | |
3544 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3545 | signed_word offset = SIGNEXTEND((signed_word)(((instruction >> 0) & 0x0000FFFF) << 2),18); |
3546 | int boolean = ((instruction >> 16) & 0x00000001); | |
3547 | int likely = ((instruction >> 17) & 0x00000001); | |
3548 | int condition_code = ((instruction >> 18) & 0x00000007); | |
f2b30012 AC |
3549 | { |
3550 | if (condition_code != 0) | |
3551 | SignalException(ReservedInstruction,instruction); | |
3552 | else { | |
3553 | int condition = (PREVCOC1() == boolean); | |
3554 | /* NOTE: The branch occurs AFTER the next instruction has been executed */ | |
3555 | if (condition) { | |
7ce8b917 | 3556 | DELAY_SLOT (CIA + offset); |
f2b30012 AC |
3557 | } |
3558 | else if (likely) { | |
49a76833 | 3559 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
3560 | } |
3561 | } | |
3562 | } | |
3563 | } | |
3564 | ||
3565 | ||
3566 | // | |
3567 | // FIXME: This does not correctly differentiate between mips* | |
3568 | // | |
3569 | 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt | |
3570 | "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0 | |
3571 | "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>" | |
3572 | *mipsI: | |
3573 | *mipsII: | |
3574 | *mipsIII: | |
3575 | *mipsIV: | |
90ad43b2 AC |
3576 | // start-sanitize-vr5400 |
3577 | *vr5400: | |
3578 | // end-sanitize-vr5400 | |
f2b30012 AC |
3579 | // start-sanitize-r5900 |
3580 | *r5900: | |
3581 | // end-sanitize-r5900 | |
3582 | *r3900: | |
3583 | // start-sanitize-tx19 | |
3584 | *tx19: | |
3585 | // end-sanitize-tx19 | |
3586 | { | |
3587 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3588 | int cmpflags = ((instruction >> 0) & 0x0000000F); |
3589 | int condition_code = ((instruction >> 8) & 0x00000007); | |
3590 | int fs = ((instruction >> 11) & 0x0000001F); | |
3591 | int ft = ((instruction >> 16) & 0x0000001F); | |
3592 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3593 | if (condition_code != 0) |
3594 | { | |
3595 | SignalException(ReservedInstruction,instruction); | |
3596 | } | |
3597 | else | |
3598 | { | |
3599 | if ((format != fmt_single) && (format != fmt_double)) | |
3600 | SignalException(ReservedInstruction,instruction); | |
3601 | else { | |
3602 | if (condition_code != 0) | |
3603 | SignalException(ReservedInstruction,instruction); | |
3604 | else | |
3605 | { | |
3606 | int ignore = 0; | |
3607 | int less = 0; | |
3608 | int equal = 0; | |
3609 | int unordered = 1; | |
3610 | unsigned64 ofs = ValueFPR(fs,format); | |
3611 | unsigned64 oft = ValueFPR(ft,format); | |
3612 | if (NaN(ofs,format) || NaN(oft,format)) { | |
3613 | if (FCSR & FP_ENABLE(IO)) { | |
3614 | FCSR |= FP_CAUSE(IO); | |
055ee297 | 3615 | SignalExceptionFPE(); |
f2b30012 AC |
3616 | ignore = 1; |
3617 | } | |
3618 | } else { | |
3619 | less = Less(ofs,oft,format); | |
3620 | equal = Equal(ofs,oft,format); | |
3621 | unordered = 0; | |
3622 | } | |
3623 | if (!ignore) { | |
3624 | int condition = (((cmpflags & (1 << 2)) && less) || ((cmpflags & (1 << 1)) && equal) || ((cmpflags & (1 << 0)) && unordered)); | |
3625 | SETFCC(condition_code,condition); | |
3626 | } | |
3627 | } | |
3628 | } | |
3629 | } | |
3630 | } | |
3631 | ||
3632 | ||
3633 | 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt | |
3634 | "ceil.l.%s<FMT> f<FD>, f<FS>" | |
3635 | *mipsIII: | |
3636 | *mipsIV: | |
90ad43b2 AC |
3637 | // start-sanitize-vr5400 |
3638 | *vr5400: | |
3639 | // end-sanitize-vr5400 | |
f2b30012 AC |
3640 | // start-sanitize-r5900 |
3641 | *r5900: | |
3642 | // end-sanitize-r5900 | |
3643 | *r3900: | |
3644 | // start-sanitize-tx19 | |
3645 | *tx19: | |
3646 | // end-sanitize-tx19 | |
3647 | { | |
3648 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3649 | int destreg = ((instruction >> 6) & 0x0000001F); |
3650 | int fs = ((instruction >> 11) & 0x0000001F); | |
3651 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3652 | { |
3653 | if ((format != fmt_single) && (format != fmt_double)) | |
3654 | SignalException(ReservedInstruction,instruction); | |
3655 | else | |
3656 | StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long)); | |
3657 | } | |
3658 | } | |
3659 | ||
3660 | ||
3661 | 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W | |
3662 | *mipsII: | |
3663 | *mipsIII: | |
3664 | *mipsIV: | |
90ad43b2 AC |
3665 | // start-sanitize-vr5400 |
3666 | *vr5400: | |
3667 | // end-sanitize-vr5400 | |
f2b30012 AC |
3668 | // start-sanitize-r5900 |
3669 | *r5900: | |
3670 | // end-sanitize-r5900 | |
3671 | *r3900: | |
3672 | // start-sanitize-tx19 | |
3673 | *tx19: | |
3674 | // end-sanitize-tx19 | |
3675 | { | |
3676 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3677 | int destreg = ((instruction >> 6) & 0x0000001F); |
3678 | int fs = ((instruction >> 11) & 0x0000001F); | |
3679 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3680 | { |
3681 | if ((format != fmt_single) && (format != fmt_double)) | |
3682 | SignalException(ReservedInstruction,instruction); | |
3683 | else | |
3684 | StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word)); | |
3685 | } | |
3686 | } | |
3687 | ||
3688 | ||
3689 | // CFC1 | |
3690 | // CTC1 | |
3691 | 01000100,x,10,kkkkk,vvvvv,00000000000:COP1S:32::CxC1 | |
3692 | *mipsI: | |
3693 | *mipsII: | |
3694 | *mipsIII: | |
3695 | *mipsIV: | |
90ad43b2 AC |
3696 | // start-sanitize-vr5400 |
3697 | *vr5400: | |
3698 | // end-sanitize-vr5400 | |
f2b30012 AC |
3699 | // start-sanitize-r5900 |
3700 | *r5900: | |
3701 | // end-sanitize-r5900 | |
3702 | *r3900: | |
3703 | // start-sanitize-tx19 | |
3704 | *tx19: | |
3705 | // end-sanitize-tx19 | |
3706 | { | |
3707 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3708 | int fs = ((instruction >> 11) & 0x0000001F); |
3709 | int ft = ((instruction >> 16) & 0x0000001F); | |
3710 | int to = ((instruction >> 23) & 0x00000001); | |
f2b30012 AC |
3711 | { |
3712 | if (to) { | |
3713 | if (fs == 0) { | |
3714 | PENDING_FILL((fs + FCR0IDX),VL4_8(GPR[ft])); | |
3715 | } else if (fs == 31) { | |
3716 | PENDING_FILL((fs + FCR31IDX),VL4_8(GPR[ft])); | |
3717 | } /* else NOP */ | |
3718 | PENDING_FILL(COCIDX,0); /* special case */ | |
3719 | } else { /* control from */ | |
3720 | if (fs == 0) { | |
3721 | PENDING_FILL(ft,SIGNEXTEND(FCR0,32)); | |
3722 | } else if (fs == 31) { | |
3723 | PENDING_FILL(ft,SIGNEXTEND(FCR31,32)); | |
3724 | } /* else NOP */ | |
3725 | } | |
3726 | } | |
3727 | } | |
3728 | ||
3729 | ||
3730 | // | |
3731 | // FIXME: Does not correctly differentiate between mips* | |
3732 | // | |
3733 | 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt | |
3734 | "cvt.d.%s<FMT> f<FD>, f<FS>" | |
3735 | *mipsI: | |
3736 | *mipsII: | |
3737 | *mipsIII: | |
3738 | *mipsIV: | |
90ad43b2 AC |
3739 | // start-sanitize-vr5400 |
3740 | *vr5400: | |
3741 | // end-sanitize-vr5400 | |
f2b30012 AC |
3742 | // start-sanitize-r5900 |
3743 | *r5900: | |
3744 | // end-sanitize-r5900 | |
3745 | *r3900: | |
3746 | // start-sanitize-tx19 | |
3747 | *tx19: | |
3748 | // end-sanitize-tx19 | |
3749 | { | |
3750 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3751 | int destreg = ((instruction >> 6) & 0x0000001F); |
3752 | int fs = ((instruction >> 11) & 0x0000001F); | |
3753 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3754 | { |
3755 | if ((format == fmt_double) | 0) | |
3756 | SignalException(ReservedInstruction,instruction); | |
3757 | else | |
3758 | StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double)); | |
3759 | } | |
3760 | } | |
3761 | ||
3762 | ||
3763 | 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt | |
3764 | "cvt.l.%s<FMT> f<FD>, f<FS>" | |
3765 | *mipsIII: | |
3766 | *mipsIV: | |
90ad43b2 AC |
3767 | // start-sanitize-vr5400 |
3768 | *vr5400: | |
3769 | // end-sanitize-vr5400 | |
f2b30012 AC |
3770 | // start-sanitize-r5900 |
3771 | *r5900: | |
3772 | // end-sanitize-r5900 | |
3773 | *r3900: | |
3774 | // start-sanitize-tx19 | |
3775 | *tx19: | |
3776 | // end-sanitize-tx19 | |
3777 | { | |
3778 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3779 | int destreg = ((instruction >> 6) & 0x0000001F); |
3780 | int fs = ((instruction >> 11) & 0x0000001F); | |
3781 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3782 | { |
3783 | if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word))) | |
3784 | SignalException(ReservedInstruction,instruction); | |
3785 | else | |
3786 | StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long)); | |
3787 | } | |
3788 | } | |
3789 | ||
3790 | ||
3791 | // | |
3792 | // FIXME: Does not correctly differentiate between mips* | |
3793 | // | |
3794 | 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt | |
3795 | "cvt.s.%s<FMT> f<FD>, f<FS>" | |
3796 | *mipsI: | |
3797 | *mipsII: | |
3798 | *mipsIII: | |
3799 | *mipsIV: | |
90ad43b2 AC |
3800 | // start-sanitize-vr5400 |
3801 | *vr5400: | |
3802 | // end-sanitize-vr5400 | |
f2b30012 AC |
3803 | // start-sanitize-r5900 |
3804 | *r5900: | |
3805 | // end-sanitize-r5900 | |
3806 | *r3900: | |
3807 | // start-sanitize-tx19 | |
3808 | *tx19: | |
3809 | // end-sanitize-tx19 | |
3810 | { | |
3811 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3812 | int destreg = ((instruction >> 6) & 0x0000001F); |
3813 | int fs = ((instruction >> 11) & 0x0000001F); | |
3814 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3815 | { |
3816 | if ((format == fmt_single) | 0) | |
3817 | SignalException(ReservedInstruction,instruction); | |
3818 | else | |
3819 | StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single)); | |
3820 | } | |
3821 | } | |
3822 | ||
3823 | ||
3824 | 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt | |
3825 | "cvt.w.%s<FMT> f<FD>, f<FS>" | |
3826 | *mipsI: | |
3827 | *mipsII: | |
3828 | *mipsIII: | |
3829 | *mipsIV: | |
90ad43b2 AC |
3830 | // start-sanitize-vr5400 |
3831 | *vr5400: | |
3832 | // end-sanitize-vr5400 | |
f2b30012 AC |
3833 | // start-sanitize-r5900 |
3834 | *r5900: | |
3835 | // end-sanitize-r5900 | |
3836 | *r3900: | |
3837 | // start-sanitize-tx19 | |
3838 | *tx19: | |
3839 | // end-sanitize-tx19 | |
3840 | { | |
3841 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3842 | int destreg = ((instruction >> 6) & 0x0000001F); |
3843 | int fs = ((instruction >> 11) & 0x0000001F); | |
3844 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3845 | { |
3846 | if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word))) | |
3847 | SignalException(ReservedInstruction,instruction); | |
3848 | else | |
3849 | StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word)); | |
3850 | } | |
3851 | } | |
3852 | ||
3853 | ||
3854 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt | |
3855 | "div.%s<FMT> f<FD>, f<FS>, f<FT>" | |
3856 | *mipsI: | |
3857 | *mipsII: | |
3858 | *mipsIII: | |
3859 | *mipsIV: | |
90ad43b2 AC |
3860 | // start-sanitize-vr5400 |
3861 | *vr5400: | |
3862 | // end-sanitize-vr5400 | |
f2b30012 AC |
3863 | // start-sanitize-r5900 |
3864 | *r5900: | |
3865 | // end-sanitize-r5900 | |
3866 | *r3900: | |
3867 | // start-sanitize-tx19 | |
3868 | *tx19: | |
3869 | // end-sanitize-tx19 | |
3870 | { | |
3871 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3872 | int destreg = ((instruction >> 6) & 0x0000001F); |
3873 | int fs = ((instruction >> 11) & 0x0000001F); | |
3874 | int ft = ((instruction >> 16) & 0x0000001F); | |
3875 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3876 | { |
3877 | if ((format != fmt_single) && (format != fmt_double)) | |
3878 | SignalException(ReservedInstruction,instruction); | |
3879 | else | |
3880 | StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format)); | |
3881 | } | |
3882 | } | |
3883 | ||
3884 | ||
3885 | // DMFC1 | |
3886 | // DMTC1 | |
3887 | 01000100,x,01,5.FT,vvvvv,00000000000:COP1S:64::DMxC1 | |
3888 | *mipsIII: | |
3889 | *mipsIV: | |
90ad43b2 AC |
3890 | // start-sanitize-vr5400 |
3891 | *vr5400: | |
3892 | // end-sanitize-vr5400 | |
f2b30012 AC |
3893 | // start-sanitize-r5900 |
3894 | *r5900: | |
3895 | // end-sanitize-r5900 | |
3896 | *r3900: | |
3897 | // start-sanitize-tx19 | |
3898 | *tx19: | |
3899 | // end-sanitize-tx19 | |
3900 | { | |
3901 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3902 | int fs = ((instruction >> 11) & 0x0000001F); |
3903 | int ft = ((instruction >> 16) & 0x0000001F); | |
3904 | int to = ((instruction >> 23) & 0x00000001); | |
f2b30012 AC |
3905 | { |
3906 | if (to) { | |
3907 | if (SizeFGR() == 64) { | |
3908 | PENDING_FILL((fs + FGRIDX),GPR[ft]); | |
3909 | } else | |
3910 | if ((fs & 0x1) == 0) | |
3911 | { | |
3912 | PENDING_FILL(((fs + 1) + FGRIDX),VH4_8(GPR[ft])); | |
3913 | PENDING_FILL((fs + FGRIDX),VL4_8(GPR[ft])); | |
3914 | } | |
3915 | } else { | |
3916 | if (SizeFGR() == 64) { | |
3917 | PENDING_FILL(ft,FGR[fs]); | |
3918 | } else | |
3919 | if ((fs & 0x1) == 0) { | |
3920 | PENDING_FILL(ft,(SET64HI(FGR[fs+1]) | FGR[fs])); | |
3921 | } else { | |
3922 | PENDING_FILL(ft,SET64HI(0xDEADC0DE) | 0xBAD0BAD0); | |
3923 | } | |
3924 | } | |
3925 | } | |
3926 | } | |
3927 | ||
3928 | ||
3929 | 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt | |
3930 | "floor.l.%s<FMT> f<FD>, f<FS>" | |
3931 | *mipsIII: | |
3932 | *mipsIV: | |
90ad43b2 AC |
3933 | // start-sanitize-vr5400 |
3934 | *vr5400: | |
3935 | // end-sanitize-vr5400 | |
f2b30012 AC |
3936 | // start-sanitize-r5900 |
3937 | *r5900: | |
3938 | // end-sanitize-r5900 | |
3939 | *r3900: | |
3940 | // start-sanitize-tx19 | |
3941 | *tx19: | |
3942 | // end-sanitize-tx19 | |
3943 | { | |
3944 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3945 | int destreg = ((instruction >> 6) & 0x0000001F); |
3946 | int fs = ((instruction >> 11) & 0x0000001F); | |
3947 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3948 | { |
3949 | if ((format != fmt_single) && (format != fmt_double)) | |
3950 | SignalException(ReservedInstruction,instruction); | |
3951 | else | |
3952 | StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long)); | |
3953 | } | |
3954 | } | |
3955 | ||
3956 | ||
3957 | 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt | |
3958 | "floor.w.%s<FMT> f<FD>, f<FS>" | |
3959 | *mipsII: | |
3960 | *mipsIII: | |
3961 | *mipsIV: | |
90ad43b2 AC |
3962 | // start-sanitize-vr5400 |
3963 | *vr5400: | |
3964 | // end-sanitize-vr5400 | |
f2b30012 AC |
3965 | // start-sanitize-r5900 |
3966 | *r5900: | |
3967 | // end-sanitize-r5900 | |
3968 | *r3900: | |
3969 | // start-sanitize-tx19 | |
3970 | *tx19: | |
3971 | // end-sanitize-tx19 | |
3972 | { | |
3973 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3974 | int destreg = ((instruction >> 6) & 0x0000001F); |
3975 | int fs = ((instruction >> 11) & 0x0000001F); | |
3976 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3977 | { |
3978 | if ((format != fmt_single) && (format != fmt_double)) | |
3979 | SignalException(ReservedInstruction,instruction); | |
3980 | else | |
3981 | StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word)); | |
3982 | } | |
3983 | } | |
3984 | ||
3985 | ||
3986 | // LDC1 | |
3987 | 110101,5.BASE,5.FT,16.OFFSET:COP1:32::LDC1 | |
3988 | ||
3989 | ||
3990 | 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1 | |
3991 | "ldxc1 f<FD>, r<INDEX>(r<BASE>)" | |
3992 | *mipsIV: | |
90ad43b2 AC |
3993 | // start-sanitize-vr5400 |
3994 | *vr5400: | |
3995 | // end-sanitize-vr5400 | |
f2b30012 AC |
3996 | // start-sanitize-r5900 |
3997 | *r5900: | |
3998 | // end-sanitize-r5900 | |
3999 | { | |
4000 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4001 | int destreg = ((instruction >> 6) & 0x0000001F); |
4002 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
4003 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 4004 | { |
49a76833 AC |
4005 | address_word vaddr = ((unsigned64)op1 + op2); |
4006 | address_word paddr; | |
f2b30012 AC |
4007 | int uncached; |
4008 | if ((vaddr & 7) != 0) | |
055ee297 | 4009 | SignalExceptionAddressLoad(); |
f2b30012 AC |
4010 | else |
4011 | { | |
4012 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4013 | { | |
4014 | unsigned64 memval = 0; | |
4015 | unsigned64 memval1 = 0; | |
f2b30012 AC |
4016 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); |
4017 | COP_LD(1,destreg,memval);; | |
4018 | } | |
4019 | } | |
4020 | } | |
4021 | } | |
4022 | ||
4023 | ||
4024 | // LWC1 | |
4025 | 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1 | |
4026 | ||
4027 | ||
4028 | 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1 | |
4029 | "lwxc1 f<FD>, r<INDEX>(r<BASE>)" | |
4030 | *mipsIV: | |
90ad43b2 AC |
4031 | // start-sanitize-vr5400 |
4032 | *vr5400: | |
4033 | // end-sanitize-vr5400 | |
f2b30012 AC |
4034 | // start-sanitize-r5900 |
4035 | *r5900: | |
4036 | // end-sanitize-r5900 | |
4037 | { | |
4038 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4039 | int destreg = ((instruction >> 6) & 0x0000001F); |
4040 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
4041 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 4042 | { |
49a76833 AC |
4043 | address_word vaddr = ((unsigned64)op1 + op2); |
4044 | address_word paddr; | |
f2b30012 AC |
4045 | int uncached; |
4046 | if ((vaddr & 3) != 0) | |
055ee297 | 4047 | SignalExceptionAddressLoad(); |
f2b30012 AC |
4048 | else |
4049 | { | |
4050 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4051 | { | |
4052 | unsigned64 memval = 0; | |
4053 | unsigned64 memval1 = 0; | |
4054 | unsigned64 mask = 0x7; | |
4055 | unsigned int shift = 2; | |
055ee297 AC |
4056 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
4057 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
4058 | unsigned int byte; | |
f2b30012 AC |
4059 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
4060 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
4061 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
4062 | COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF)); | |
4063 | } | |
4064 | } | |
4065 | } | |
4066 | } | |
4067 | ||
4068 | ||
4069 | ||
4070 | // | |
4071 | // FIXME: Not correct for mips* | |
4072 | // | |
4073 | 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D | |
4074 | "madd.d f<FD>, f<FR>, f<FS>, f<FT>" | |
4075 | *mipsIV: | |
90ad43b2 AC |
4076 | // start-sanitize-vr5400 |
4077 | *vr5400: | |
4078 | // end-sanitize-vr5400 | |
f2b30012 AC |
4079 | // start-sanitize-r5900 |
4080 | *r5900: | |
4081 | // end-sanitize-r5900 | |
4082 | { | |
4083 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4084 | int destreg = ((instruction >> 6) & 0x0000001F); |
4085 | int fs = ((instruction >> 11) & 0x0000001F); | |
4086 | int ft = ((instruction >> 16) & 0x0000001F); | |
4087 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 AC |
4088 | { |
4089 | StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double)); | |
4090 | } | |
4091 | } | |
4092 | ||
4093 | ||
4094 | 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S | |
4095 | "madd.s f<FD>, f<FR>, f<FS>, f<FT>" | |
4096 | *mipsIV: | |
90ad43b2 AC |
4097 | // start-sanitize-vr5400 |
4098 | *vr5400: | |
4099 | // end-sanitize-vr5400 | |
f2b30012 AC |
4100 | // start-sanitize-r5900 |
4101 | *r5900: | |
4102 | // end-sanitize-r5900 | |
4103 | { | |
4104 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4105 | int destreg = ((instruction >> 6) & 0x0000001F); |
4106 | int fs = ((instruction >> 11) & 0x0000001F); | |
4107 | int ft = ((instruction >> 16) & 0x0000001F); | |
4108 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 AC |
4109 | { |
4110 | StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single)); | |
4111 | } | |
4112 | } | |
4113 | ||
4114 | ||
4115 | // MFC1 | |
4116 | 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1 | |
055ee297 | 4117 | "m<X>c1 r<RT>, f<FS>" |
f2b30012 AC |
4118 | *mipsI: |
4119 | *mipsII: | |
4120 | *mipsIII: | |
4121 | *mipsIV: | |
90ad43b2 AC |
4122 | // start-sanitize-vr5400 |
4123 | *vr5400: | |
4124 | // end-sanitize-vr5400 | |
f2b30012 AC |
4125 | // start-sanitize-r5900 |
4126 | *r5900: | |
4127 | // end-sanitize-r5900 | |
4128 | *r3900: | |
4129 | // start-sanitize-tx19 | |
4130 | *tx19: | |
4131 | // end-sanitize-tx19 | |
4132 | { | |
4133 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4134 | int fs = ((instruction >> 11) & 0x0000001F); |
4135 | int ft = ((instruction >> 16) & 0x0000001F); | |
4136 | int to = ((instruction >> 23) & 0x00000001); | |
f2b30012 AC |
4137 | { |
4138 | if (to) { | |
4139 | if (SizeFGR() == 64) { | |
055ee297 | 4140 | PENDING_FILL ((fs + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[ft]))); |
f2b30012 | 4141 | } else { |
055ee297 | 4142 | PENDING_FILL ((fs + FGRIDX), VL4_8(GPR[ft])); |
f2b30012 AC |
4143 | } |
4144 | } else { | |
055ee297 | 4145 | PENDING_FILL (ft, SIGNEXTEND(FGR[fs],32)); |
f2b30012 AC |
4146 | } |
4147 | } | |
4148 | } | |
4149 | ||
4150 | ||
4151 | 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt | |
4152 | "mov.%s<FMT> f<FD>, f<FS>" | |
4153 | *mipsI: | |
4154 | *mipsII: | |
4155 | *mipsIII: | |
4156 | *mipsIV: | |
90ad43b2 AC |
4157 | // start-sanitize-vr5400 |
4158 | *vr5400: | |
4159 | // end-sanitize-vr5400 | |
f2b30012 AC |
4160 | // start-sanitize-r5900 |
4161 | *r5900: | |
4162 | // end-sanitize-r5900 | |
4163 | *r3900: | |
4164 | // start-sanitize-tx19 | |
4165 | *tx19: | |
4166 | // end-sanitize-tx19 | |
4167 | { | |
4168 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4169 | int destreg = ((instruction >> 6) & 0x0000001F); |
4170 | int fs = ((instruction >> 11) & 0x0000001F); | |
4171 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4172 | { |
4173 | StoreFPR(destreg,format,ValueFPR(fs,format)); | |
4174 | } | |
4175 | } | |
4176 | ||
4177 | ||
4178 | // MOVF | |
4179 | 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf | |
055ee297 | 4180 | "mov%s<TF> r<RD>, r<RS>, <CC>" |
f2b30012 | 4181 | *mipsIV: |
90ad43b2 AC |
4182 | // start-sanitize-vr5400 |
4183 | *vr5400: | |
4184 | // end-sanitize-vr5400 | |
f2b30012 AC |
4185 | // start-sanitize-r5900 |
4186 | *r5900: | |
4187 | // end-sanitize-r5900 | |
4188 | { | |
055ee297 AC |
4189 | if (GETFCC(CC) == TF) |
4190 | GPR[RD] = GPR[RS]; | |
f2b30012 AC |
4191 | } |
4192 | ||
4193 | ||
4194 | // MOVF.fmt | |
4195 | 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt | |
055ee297 | 4196 | "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>" |
f2b30012 | 4197 | *mipsIV: |
90ad43b2 AC |
4198 | // start-sanitize-vr5400 |
4199 | *vr5400: | |
4200 | // end-sanitize-vr5400 | |
f2b30012 AC |
4201 | // start-sanitize-r5900 |
4202 | *r5900: | |
4203 | // end-sanitize-r5900 | |
4204 | { | |
4205 | unsigned32 instruction = instruction_0; | |
055ee297 | 4206 | int format = ((instruction >> 21) & 0x00000007); |
f2b30012 | 4207 | { |
055ee297 AC |
4208 | if (GETFCC(CC) == TF) |
4209 | StoreFPR (FD, format, ValueFPR (FS, format)); | |
f2b30012 | 4210 | else |
055ee297 | 4211 | StoreFPR (FD, format, ValueFPR (FD, format)); |
f2b30012 AC |
4212 | } |
4213 | } | |
4214 | ||
4215 | ||
4216 | 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt | |
4217 | *mipsIV: | |
90ad43b2 AC |
4218 | // start-sanitize-vr5400 |
4219 | *vr5400: | |
4220 | // end-sanitize-vr5400 | |
f2b30012 AC |
4221 | // start-sanitize-r5900 |
4222 | *r5900: | |
4223 | // end-sanitize-r5900 | |
4224 | { | |
4225 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4226 | int destreg = ((instruction >> 6) & 0x0000001F); |
4227 | int fs = ((instruction >> 11) & 0x0000001F); | |
4228 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4229 | { |
4230 | StoreFPR(destreg,format,ValueFPR(fs,format)); | |
4231 | } | |
4232 | } | |
4233 | ||
4234 | ||
4235 | // MOVT see MOVtf | |
4236 | ||
4237 | ||
4238 | // MOVT.fmt see MOVtf.fmt | |
4239 | ||
4240 | ||
4241 | ||
4242 | 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt | |
4243 | "movz.%s<FMT> f<FD>, f<FS>, r<RT>" | |
4244 | *mipsIV: | |
90ad43b2 AC |
4245 | // start-sanitize-vr5400 |
4246 | *vr5400: | |
4247 | // end-sanitize-vr5400 | |
f2b30012 AC |
4248 | // start-sanitize-r5900 |
4249 | *r5900: | |
4250 | // end-sanitize-r5900 | |
4251 | { | |
4252 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4253 | int destreg = ((instruction >> 6) & 0x0000001F); |
4254 | int fs = ((instruction >> 11) & 0x0000001F); | |
4255 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4256 | { |
4257 | StoreFPR(destreg,format,ValueFPR(fs,format)); | |
4258 | } | |
4259 | } | |
4260 | ||
4261 | ||
4262 | // MSUB.fmt | |
4263 | 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D | |
4264 | "msub.d f<FD>, f<FR>, f<FS>, f<FT>" | |
4265 | *mipsIV: | |
90ad43b2 AC |
4266 | // start-sanitize-vr5400 |
4267 | *vr5400: | |
4268 | // end-sanitize-vr5400 | |
f2b30012 AC |
4269 | // start-sanitize-r5900 |
4270 | *r5900: | |
4271 | // end-sanitize-r5900 | |
4272 | { | |
4273 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4274 | int destreg = ((instruction >> 6) & 0x0000001F); |
4275 | int fs = ((instruction >> 11) & 0x0000001F); | |
4276 | int ft = ((instruction >> 16) & 0x0000001F); | |
4277 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 AC |
4278 | { |
4279 | StoreFPR(destreg,fmt_double,(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double)); | |
4280 | } | |
4281 | } | |
4282 | ||
4283 | ||
4284 | // MSUB.fmt | |
055ee297 | 4285 | 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S |
f2b30012 AC |
4286 | "msub.s f<FD>, f<FR>, f<FS>, f<FT>" |
4287 | *mipsIV: | |
90ad43b2 AC |
4288 | // start-sanitize-vr5400 |
4289 | *vr5400: | |
4290 | // end-sanitize-vr5400 | |
f2b30012 AC |
4291 | // start-sanitize-r5900 |
4292 | *r5900: | |
4293 | // end-sanitize-r5900 | |
4294 | { | |
4295 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4296 | int destreg = ((instruction >> 6) & 0x0000001F); |
4297 | int fs = ((instruction >> 11) & 0x0000001F); | |
4298 | int ft = ((instruction >> 16) & 0x0000001F); | |
4299 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 AC |
4300 | { |
4301 | StoreFPR(destreg,fmt_single,(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single)); | |
4302 | } | |
4303 | } | |
4304 | ||
4305 | ||
4306 | // MTC1 see MxC1 | |
4307 | ||
4308 | ||
4309 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt | |
4310 | "mul.%s<FMT> f<FD>, f<FS>, f<FT>" | |
4311 | *mipsI: | |
4312 | *mipsII: | |
4313 | *mipsIII: | |
4314 | *mipsIV: | |
90ad43b2 AC |
4315 | // start-sanitize-vr5400 |
4316 | *vr5400: | |
4317 | // end-sanitize-vr5400 | |
f2b30012 AC |
4318 | // start-sanitize-r5900 |
4319 | *r5900: | |
4320 | // end-sanitize-r5900 | |
4321 | *r3900: | |
4322 | // start-sanitize-tx19 | |
4323 | *tx19: | |
4324 | // end-sanitize-tx19 | |
4325 | { | |
4326 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4327 | int destreg = ((instruction >> 6) & 0x0000001F); |
4328 | int fs = ((instruction >> 11) & 0x0000001F); | |
4329 | int ft = ((instruction >> 16) & 0x0000001F); | |
4330 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4331 | { |
4332 | if ((format != fmt_single) && (format != fmt_double)) | |
4333 | SignalException(ReservedInstruction,instruction); | |
4334 | else | |
4335 | StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format)); | |
4336 | } | |
4337 | } | |
4338 | ||
4339 | ||
4340 | 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt | |
4341 | "neg.%s<FMT> f<FD>, f<FS>" | |
4342 | *mipsI: | |
4343 | *mipsII: | |
4344 | *mipsIII: | |
4345 | *mipsIV: | |
90ad43b2 AC |
4346 | // start-sanitize-vr5400 |
4347 | *vr5400: | |
4348 | // end-sanitize-vr5400 | |
f2b30012 AC |
4349 | // start-sanitize-r5900 |
4350 | *r5900: | |
4351 | // end-sanitize-r5900 | |
4352 | *r3900: | |
4353 | // start-sanitize-tx19 | |
4354 | *tx19: | |
4355 | // end-sanitize-tx19 | |
4356 | { | |
4357 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4358 | int destreg = ((instruction >> 6) & 0x0000001F); |
4359 | int fs = ((instruction >> 11) & 0x0000001F); | |
4360 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4361 | { |
4362 | if ((format != fmt_single) && (format != fmt_double)) | |
4363 | SignalException(ReservedInstruction,instruction); | |
4364 | else | |
4365 | StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format)); | |
4366 | } | |
4367 | } | |
4368 | ||
4369 | ||
4370 | // NMADD.fmt | |
4371 | 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D | |
4372 | "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>" | |
4373 | *mipsIV: | |
90ad43b2 AC |
4374 | // start-sanitize-vr5400 |
4375 | *vr5400: | |
4376 | // end-sanitize-vr5400 | |
f2b30012 AC |
4377 | { |
4378 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4379 | int destreg = ((instruction >> 6) & 0x0000001F); |
4380 | int fs = ((instruction >> 11) & 0x0000001F); | |
4381 | int ft = ((instruction >> 16) & 0x0000001F); | |
4382 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 AC |
4383 | { |
4384 | StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double)); | |
4385 | } | |
4386 | } | |
4387 | ||
4388 | ||
4389 | // NMADD.fmt | |
4390 | 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S | |
4391 | "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>" | |
4392 | *mipsIV: | |
90ad43b2 AC |
4393 | // start-sanitize-vr5400 |
4394 | *vr5400: | |
4395 | // end-sanitize-vr5400 | |
f2b30012 AC |
4396 | { |
4397 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4398 | int destreg = ((instruction >> 6) & 0x0000001F); |
4399 | int fs = ((instruction >> 11) & 0x0000001F); | |
4400 | int ft = ((instruction >> 16) & 0x0000001F); | |
4401 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 AC |
4402 | { |
4403 | StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single)); | |
4404 | } | |
4405 | } | |
4406 | ||
4407 | ||
4408 | // NMSUB.fmt | |
055ee297 | 4409 | 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D |
f2b30012 AC |
4410 | "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>" |
4411 | *mipsIV: | |
90ad43b2 AC |
4412 | // start-sanitize-vr5400 |
4413 | *vr5400: | |
4414 | // end-sanitize-vr5400 | |
f2b30012 AC |
4415 | { |
4416 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4417 | int destreg = ((instruction >> 6) & 0x0000001F); |
4418 | int fs = ((instruction >> 11) & 0x0000001F); | |
4419 | int ft = ((instruction >> 16) & 0x0000001F); | |
4420 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 AC |
4421 | { |
4422 | StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double)); | |
4423 | } | |
4424 | } | |
4425 | ||
4426 | ||
4427 | // NMSUB.fmt | |
055ee297 | 4428 | 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S |
f2b30012 AC |
4429 | "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>" |
4430 | *mipsIV: | |
90ad43b2 AC |
4431 | // start-sanitize-vr5400 |
4432 | *vr5400: | |
4433 | // end-sanitize-vr5400 | |
f2b30012 AC |
4434 | { |
4435 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4436 | int destreg = ((instruction >> 6) & 0x0000001F); |
4437 | int fs = ((instruction >> 11) & 0x0000001F); | |
4438 | int ft = ((instruction >> 16) & 0x0000001F); | |
4439 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 AC |
4440 | { |
4441 | StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single)); | |
4442 | } | |
4443 | } | |
4444 | ||
4445 | ||
4446 | 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX | |
49a6eed5 | 4447 | "prefx <HINT>, r<INDEX>(r<BASE>)" |
f2b30012 | 4448 | *mipsIV: |
90ad43b2 AC |
4449 | // start-sanitize-vr5400 |
4450 | *vr5400: | |
4451 | // end-sanitize-vr5400 | |
f2b30012 AC |
4452 | { |
4453 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4454 | int fs = ((instruction >> 11) & 0x0000001F); |
4455 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
4456 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 4457 | { |
49a76833 AC |
4458 | address_word vaddr = ((unsigned64)op1 + (unsigned64)op2); |
4459 | address_word paddr; | |
f2b30012 AC |
4460 | int uncached; |
4461 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4462 | Prefetch(uncached,paddr,vaddr,isDATA,fs); | |
4463 | } | |
4464 | } | |
4465 | ||
4466 | 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt | |
4467 | *mipsIV: | |
4468 | "recip.%s<FMT> f<FD>, f<FS>" | |
90ad43b2 AC |
4469 | // start-sanitize-vr5400 |
4470 | *vr5400: | |
4471 | // end-sanitize-vr5400 | |
f2b30012 AC |
4472 | { |
4473 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4474 | int destreg = ((instruction >> 6) & 0x0000001F); |
4475 | int fs = ((instruction >> 11) & 0x0000001F); | |
4476 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4477 | { |
4478 | if ((format != fmt_single) && (format != fmt_double)) | |
4479 | SignalException(ReservedInstruction,instruction); | |
4480 | else | |
4481 | StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format)); | |
4482 | } | |
4483 | } | |
4484 | ||
4485 | ||
4486 | 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt | |
49a6eed5 | 4487 | "round.l.%s<FMT> f<FD>, f<FS>" |
f2b30012 AC |
4488 | *mipsIII: |
4489 | *mipsIV: | |
90ad43b2 AC |
4490 | // start-sanitize-vr5400 |
4491 | *vr5400: | |
4492 | // end-sanitize-vr5400 | |
f2b30012 AC |
4493 | // start-sanitize-r5900 |
4494 | *r5900: | |
4495 | // end-sanitize-r5900 | |
4496 | *r3900: | |
4497 | // start-sanitize-tx19 | |
4498 | *tx19: | |
4499 | // end-sanitize-tx19 | |
4500 | { | |
4501 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4502 | int destreg = ((instruction >> 6) & 0x0000001F); |
4503 | int fs = ((instruction >> 11) & 0x0000001F); | |
4504 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4505 | { |
4506 | if ((format != fmt_single) && (format != fmt_double)) | |
4507 | SignalException(ReservedInstruction,instruction); | |
4508 | else | |
4509 | StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long)); | |
4510 | } | |
4511 | } | |
4512 | ||
4513 | ||
4514 | 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt | |
49a6eed5 | 4515 | "round.w.%s<FMT> f<FD>, f<FS>" |
f2b30012 AC |
4516 | *mipsII: |
4517 | *mipsIII: | |
4518 | *mipsIV: | |
90ad43b2 AC |
4519 | // start-sanitize-vr5400 |
4520 | *vr5400: | |
4521 | // end-sanitize-vr5400 | |
f2b30012 AC |
4522 | // start-sanitize-r5900 |
4523 | *r5900: | |
4524 | // end-sanitize-r5900 | |
4525 | *r3900: | |
4526 | // start-sanitize-tx19 | |
4527 | *tx19: | |
4528 | // end-sanitize-tx19 | |
4529 | { | |
4530 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4531 | int destreg = ((instruction >> 6) & 0x0000001F); |
4532 | int fs = ((instruction >> 11) & 0x0000001F); | |
4533 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4534 | { |
4535 | if ((format != fmt_single) && (format != fmt_double)) | |
4536 | SignalException(ReservedInstruction,instruction); | |
4537 | else | |
4538 | StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word)); | |
4539 | } | |
4540 | } | |
4541 | ||
4542 | ||
4543 | 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt | |
4544 | *mipsIV: | |
4545 | "rsqrt.%s<FMT> f<FD>, f<FS>" | |
90ad43b2 AC |
4546 | // start-sanitize-vr5400 |
4547 | *vr5400: | |
4548 | // end-sanitize-vr5400 | |
f2b30012 AC |
4549 | { |
4550 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4551 | int destreg = ((instruction >> 6) & 0x0000001F); |
4552 | int fs = ((instruction >> 11) & 0x0000001F); | |
4553 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4554 | { |
4555 | if ((format != fmt_single) && (format != fmt_double)) | |
4556 | SignalException(ReservedInstruction,instruction); | |
4557 | else | |
085c1cb9 | 4558 | StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format)); |
f2b30012 AC |
4559 | } |
4560 | } | |
4561 | ||
4562 | ||
4563 | // SDC1 | |
4564 | ||
4565 | ||
4566 | 010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1 | |
4567 | *mipsIV: | |
90ad43b2 AC |
4568 | // start-sanitize-vr5400 |
4569 | *vr5400: | |
4570 | // end-sanitize-vr5400 | |
f2b30012 AC |
4571 | // start-sanitize-r5900 |
4572 | *r5900: | |
4573 | // end-sanitize-r5900 | |
4574 | { | |
4575 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4576 | int fs = ((instruction >> 11) & 0x0000001F); |
4577 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
4578 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 4579 | { |
49a76833 AC |
4580 | address_word vaddr = ((unsigned64)op1 + op2); |
4581 | address_word paddr; | |
f2b30012 AC |
4582 | int uncached; |
4583 | if ((vaddr & 7) != 0) | |
055ee297 | 4584 | SignalExceptionAddressStore(); |
f2b30012 AC |
4585 | else |
4586 | { | |
4587 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
4588 | { | |
4589 | unsigned64 memval = 0; | |
4590 | unsigned64 memval1 = 0; | |
4591 | memval = (unsigned64)COP_SD(1,fs); | |
4592 | { | |
4593 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
4594 | } | |
4595 | } | |
4596 | } | |
4597 | } | |
4598 | } | |
4599 | ||
4600 | ||
4601 | 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt | |
4602 | "sqrt.%s<FMT> f<FD>, f<FS>" | |
4603 | *mipsII: | |
4604 | *mipsIII: | |
4605 | *mipsIV: | |
90ad43b2 AC |
4606 | // start-sanitize-vr5400 |
4607 | *vr5400: | |
4608 | // end-sanitize-vr5400 | |
f2b30012 AC |
4609 | // start-sanitize-r5900 |
4610 | *r5900: | |
4611 | // end-sanitize-r5900 | |
4612 | *r3900: | |
4613 | // start-sanitize-tx19 | |
4614 | *tx19: | |
4615 | // end-sanitize-tx19 | |
4616 | { | |
4617 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4618 | int destreg = ((instruction >> 6) & 0x0000001F); |
4619 | int fs = ((instruction >> 11) & 0x0000001F); | |
4620 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4621 | { |
4622 | if ((format != fmt_single) && (format != fmt_double)) | |
4623 | SignalException(ReservedInstruction,instruction); | |
4624 | else | |
4625 | StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format))); | |
4626 | } | |
4627 | } | |
4628 | ||
4629 | ||
4630 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt | |
4631 | "sub.%s<FMT> f<FD>, f<FS>, f<FT>" | |
4632 | *mipsI: | |
4633 | *mipsII: | |
4634 | *mipsIII: | |
4635 | *mipsIV: | |
90ad43b2 AC |
4636 | // start-sanitize-vr5400 |
4637 | *vr5400: | |
4638 | // end-sanitize-vr5400 | |
f2b30012 AC |
4639 | // start-sanitize-r5900 |
4640 | *r5900: | |
4641 | // end-sanitize-r5900 | |
4642 | *r3900: | |
4643 | // start-sanitize-tx19 | |
4644 | *tx19: | |
4645 | // end-sanitize-tx19 | |
4646 | { | |
4647 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4648 | int destreg = ((instruction >> 6) & 0x0000001F); |
4649 | int fs = ((instruction >> 11) & 0x0000001F); | |
4650 | int ft = ((instruction >> 16) & 0x0000001F); | |
4651 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4652 | { |
4653 | if ((format != fmt_single) && (format != fmt_double)) | |
4654 | SignalException(ReservedInstruction,instruction); | |
4655 | else | |
4656 | StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format)); | |
4657 | } | |
4658 | } | |
4659 | ||
4660 | ||
4661 | // SWC1 | |
4662 | ||
4663 | ||
085c1cb9 AC |
4664 | 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1 |
4665 | "swxc1 f<FS>, r<INDEX>(r<BASE>)" | |
f2b30012 | 4666 | *mipsIV: |
90ad43b2 AC |
4667 | // start-sanitize-vr5400 |
4668 | *vr5400: | |
4669 | // end-sanitize-vr5400 | |
f2b30012 AC |
4670 | // start-sanitize-r5900 |
4671 | *r5900: | |
4672 | // end-sanitize-r5900 | |
4673 | { | |
4674 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4675 | int fs = ((instruction >> 11) & 0x0000001F); |
4676 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
4677 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 4678 | { |
49a76833 AC |
4679 | address_word vaddr = ((unsigned64)op1 + op2); |
4680 | address_word paddr; | |
f2b30012 AC |
4681 | int uncached; |
4682 | if ((vaddr & 3) != 0) | |
055ee297 | 4683 | SignalExceptionAddressStore(); |
f2b30012 AC |
4684 | else |
4685 | { | |
4686 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
4687 | { | |
4688 | unsigned64 memval = 0; | |
4689 | unsigned64 memval1 = 0; | |
4690 | unsigned64 mask = 0x7; | |
4691 | unsigned int byte; | |
4692 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
4693 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
4694 | memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte)); | |
4695 | { | |
4696 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
4697 | } | |
4698 | } | |
4699 | } | |
4700 | } | |
4701 | } | |
4702 | ||
4703 | ||
4704 | 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt | |
4705 | "trunc.l.%s<FMT> f<FD>, f<FS>" | |
4706 | *mipsIII: | |
4707 | *mipsIV: | |
90ad43b2 AC |
4708 | // start-sanitize-vr5400 |
4709 | *vr5400: | |
4710 | // end-sanitize-vr5400 | |
f2b30012 AC |
4711 | // start-sanitize-r5900 |
4712 | *r5900: | |
4713 | // end-sanitize-r5900 | |
4714 | *r3900: | |
4715 | // start-sanitize-tx19 | |
4716 | *tx19: | |
4717 | // end-sanitize-tx19 | |
4718 | { | |
4719 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4720 | int destreg = ((instruction >> 6) & 0x0000001F); |
4721 | int fs = ((instruction >> 11) & 0x0000001F); | |
4722 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4723 | { |
4724 | if ((format != fmt_single) && (format != fmt_double)) | |
4725 | SignalException(ReservedInstruction,instruction); | |
4726 | else | |
4727 | StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long)); | |
4728 | } | |
4729 | } | |
4730 | ||
4731 | ||
4732 | 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W | |
4733 | "trunc.w.%s<FMT> f<FD>, f<FS>" | |
4734 | *mipsII: | |
4735 | *mipsIII: | |
4736 | *mipsIV: | |
90ad43b2 AC |
4737 | // start-sanitize-vr5400 |
4738 | *vr5400: | |
4739 | // end-sanitize-vr5400 | |
f2b30012 AC |
4740 | // start-sanitize-r5900 |
4741 | *r5900: | |
4742 | // end-sanitize-r5900 | |
4743 | *r3900: | |
4744 | // start-sanitize-tx19 | |
4745 | *tx19: | |
4746 | // end-sanitize-tx19 | |
4747 | { | |
4748 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4749 | int destreg = ((instruction >> 6) & 0x0000001F); |
4750 | int fs = ((instruction >> 11) & 0x0000001F); | |
4751 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4752 | { |
4753 | if ((format != fmt_single) && (format != fmt_double)) | |
4754 | SignalException(ReservedInstruction,instruction); | |
4755 | else | |
4756 | StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word)); | |
4757 | } | |
4758 | } | |
4759 | ||
4760 | \f | |
4761 | // | |
4762 | // MIPS Architecture: | |
4763 | // | |
4764 | // System Control Instruction Set (COP0) | |
4765 | // | |
4766 | ||
4767 | ||
4768 | 010000,01000,00000,16.OFFSET:COP0:32::BC0F | |
4769 | "bc0f <OFFSET>" | |
4770 | *mipsI: | |
4771 | *mipsII: | |
4772 | *mipsIII: | |
4773 | *mipsIV: | |
90ad43b2 AC |
4774 | // start-sanitize-vr5400 |
4775 | *vr5400: | |
4776 | // end-sanitize-vr5400 | |
f2b30012 AC |
4777 | // start-sanitize-r5900 |
4778 | *r5900: | |
4779 | // end-sanitize-r5900 | |
4780 | ||
4781 | ||
4782 | 010000,01000,00010,16.OFFSET:COP0:32::BC0FL | |
4783 | "bc0fl <OFFSET>" | |
4784 | *mipsI: | |
4785 | *mipsII: | |
4786 | *mipsIII: | |
4787 | *mipsIV: | |
90ad43b2 AC |
4788 | // start-sanitize-vr5400 |
4789 | *vr5400: | |
4790 | // end-sanitize-vr5400 | |
f2b30012 AC |
4791 | // start-sanitize-r5900 |
4792 | *r5900: | |
4793 | // end-sanitize-r5900 | |
4794 | ||
4795 | ||
4796 | 010000,01000,00001,16.OFFSET:COP0:32::BC0T | |
4797 | "bc0t <OFFSET>" | |
4798 | *mipsI: | |
4799 | *mipsII: | |
4800 | *mipsIII: | |
4801 | *mipsIV: | |
4802 | // start-sanitize-r5900 | |
4803 | *r5900: | |
4804 | // end-sanitize-r5900 | |
4805 | ||
4806 | ||
4807 | ||
49a6eed5 | 4808 | 010000,01000,00011,16.OFFSET:COP0:32::BC0TL |
f2b30012 AC |
4809 | "bc0tl <OFFSET>" |
4810 | *mipsI: | |
4811 | *mipsII: | |
4812 | *mipsIII: | |
4813 | *mipsIV: | |
90ad43b2 AC |
4814 | // start-sanitize-vr5400 |
4815 | *vr5400: | |
4816 | // end-sanitize-vr5400 | |
f2b30012 AC |
4817 | // start-sanitize-r5900 |
4818 | *r5900: | |
4819 | // end-sanitize-r5900 | |
4820 | ||
4821 | ||
4822 | 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE | |
4823 | *mipsIII: | |
4824 | *mipsIV: | |
90ad43b2 AC |
4825 | // start-sanitize-vr5400 |
4826 | *vr5400: | |
4827 | // end-sanitize-vr5400 | |
f2b30012 AC |
4828 | // start-sanitize-r5900 |
4829 | *r5900: | |
4830 | // end-sanitize-r5900 | |
4831 | *r3900: | |
4832 | // start-sanitize-tx19 | |
4833 | *tx19: | |
4834 | // end-sanitize-tx19 | |
4835 | { | |
4836 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4837 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
4838 | int hint = ((instruction >> 16) & 0x0000001F); | |
4839 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 4840 | { |
49a76833 AC |
4841 | address_word vaddr = (op1 + offset); |
4842 | address_word paddr; | |
f2b30012 AC |
4843 | int uncached; |
4844 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4845 | CacheOp(hint,vaddr,paddr,instruction); | |
4846 | } | |
4847 | } | |
4848 | ||
4849 | ||
4850 | 010000,10000,000000000000000,111001:COP0:32::DI | |
4851 | "di" | |
4852 | *mipsI: | |
4853 | *mipsII: | |
4854 | *mipsIII: | |
4855 | *mipsIV: | |
90ad43b2 AC |
4856 | // start-sanitize-vr5400 |
4857 | *vr5400: | |
4858 | // end-sanitize-vr5400 | |
f2b30012 AC |
4859 | // start-sanitize-r5900 |
4860 | *r5900: | |
4861 | // end-sanitize-r5900 | |
4862 | ||
4863 | ||
4864 | 010000,10000,000000000000000,111000:COP0:32::EI | |
4865 | "ei" | |
4866 | *mipsI: | |
4867 | *mipsII: | |
4868 | *mipsIII: | |
4869 | *mipsIV: | |
90ad43b2 AC |
4870 | // start-sanitize-vr5400 |
4871 | *vr5400: | |
4872 | // end-sanitize-vr5400 | |
f2b30012 AC |
4873 | // start-sanitize-r5900 |
4874 | *r5900: | |
4875 | // end-sanitize-r5900 | |
4876 | ||
4877 | ||
4878 | 010000,10000,000000000000000,011000:COP0:32::ERET | |
4879 | "eret" | |
4880 | *mipsIII: | |
4881 | *mipsIV: | |
90ad43b2 AC |
4882 | // start-sanitize-vr5400 |
4883 | *vr5400: | |
4884 | // end-sanitize-vr5400 | |
f2b30012 AC |
4885 | // start-sanitize-r5900 |
4886 | *r5900: | |
4887 | // end-sanitize-r5900 | |
4888 | ||
4889 | ||
49a6eed5 AC |
4890 | 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0 |
4891 | "mfc0 r<RT>, r<RD> # <REGX>" | |
f2b30012 AC |
4892 | *mipsI: |
4893 | *mipsII: | |
4894 | *mipsIII: | |
4895 | *mipsIV: | |
90ad43b2 AC |
4896 | // start-sanitize-vr5400 |
4897 | *vr5400: | |
4898 | // end-sanitize-vr5400 | |
f2b30012 AC |
4899 | // start-sanitize-r5900 |
4900 | *r5900: | |
4901 | // end-sanitize-r5900 | |
4902 | ||
4903 | ||
49a6eed5 AC |
4904 | 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0 |
4905 | "mtc0 r<RT>, r<RD> # <REGX>" | |
f2b30012 AC |
4906 | *mipsI: |
4907 | *mipsII: | |
4908 | *mipsIII: | |
4909 | *mipsIV: | |
90ad43b2 AC |
4910 | // start-sanitize-vr5400 |
4911 | *vr5400: | |
4912 | // end-sanitize-vr5400 | |
f2b30012 AC |
4913 | // start-sanitize-r5900 |
4914 | *r5900: | |
4915 | // end-sanitize-r5900 | |
4916 | ||
4917 | ||
4918 | 010000,10000,000000000000000,001000:COP0:32::TLBP | |
4919 | "tlbp" | |
4920 | *mipsI: | |
4921 | *mipsII: | |
4922 | *mipsIII: | |
4923 | *mipsIV: | |
90ad43b2 AC |
4924 | // start-sanitize-vr5400 |
4925 | *vr5400: | |
4926 | // end-sanitize-vr5400 | |
f2b30012 AC |
4927 | // start-sanitize-r5900 |
4928 | *r5900: | |
4929 | // end-sanitize-r5900 | |
4930 | ||
4931 | ||
4932 | 010000,10000,000000000000000,000001:COP0:32::TLBR | |
4933 | "tlbr" | |
4934 | *mipsI: | |
4935 | *mipsII: | |
4936 | *mipsIII: | |
4937 | *mipsIV: | |
90ad43b2 AC |
4938 | // start-sanitize-vr5400 |
4939 | *vr5400: | |
4940 | // end-sanitize-vr5400 | |
f2b30012 AC |
4941 | // start-sanitize-r5900 |
4942 | *r5900: | |
4943 | // end-sanitize-r5900 | |
4944 | ||
4945 | ||
4946 | 010000,10000,000000000000000,000010:COP0:32::TLBWI | |
4947 | "tlbwi" | |
4948 | *mipsI: | |
4949 | *mipsII: | |
4950 | *mipsIII: | |
4951 | *mipsIV: | |
90ad43b2 AC |
4952 | // start-sanitize-vr5400 |
4953 | *vr5400: | |
4954 | // end-sanitize-vr5400 | |
f2b30012 AC |
4955 | // start-sanitize-r5900 |
4956 | *r5900: | |
4957 | // end-sanitize-r5900 | |
4958 | ||
4959 | ||
4960 | 010000,10000,000000000000000,000110:COP0:32::TLBWR | |
4961 | "tlbwr" | |
4962 | *mipsI: | |
4963 | *mipsII: | |
4964 | *mipsIII: | |
4965 | *mipsIV: | |
90ad43b2 AC |
4966 | // start-sanitize-vr5400 |
4967 | *vr5400: | |
4968 | // end-sanitize-vr5400 | |
f2b30012 AC |
4969 | // start-sanitize-r5900 |
4970 | *r5900: | |
4971 | // end-sanitize-r5900 | |
4972 | ||
4973 | \f | |
89d09738 | 4974 | :include:::m16.igen |
16bd5d6e | 4975 | // start-sanitize-vr5400 |
89d09738 | 4976 | :include::vr5400:vr5400.igen |
16bd5d6e | 4977 | // end-sanitize-vr5400 |
f2b30012 | 4978 | // start-sanitize-r5900 |
89d09738 | 4979 | :include::r5900:r5900.igen |
f2b30012 AC |
4980 | // end-sanitize-r5900 |
4981 | \f | |
4982 | // start-sanitize-cygnus-never | |
4983 | ||
49a6eed5 AC |
4984 | // // FIXME FIXME FIXME What is this instruction? |
4985 | // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT> | |
4986 | // *mipsI: | |
4987 | // *mipsII: | |
4988 | // *mipsIII: | |
4989 | // *mipsIV: | |
4990 | // // start-sanitize-r5900 | |
4991 | // *r5900: | |
4992 | // // end-sanitize-r5900 | |
4993 | // *r3900: | |
4994 | // // start-sanitize-tx19 | |
4995 | // *tx19: | |
4996 | // // end-sanitize-tx19 | |
4997 | // { | |
4998 | // unsigned32 instruction = instruction_0; | |
055ee297 AC |
4999 | // signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
5000 | // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
5001 | // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
49a6eed5 AC |
5002 | // { |
5003 | // if (CoProcPresent(3)) | |
5004 | // SignalException(CoProcessorUnusable); | |
5005 | // else | |
5006 | // SignalException(ReservedInstruction,instruction); | |
5007 | // } | |
5008 | // } | |
5009 | ||
5010 | // end-sanitize-cygnus-never | |
5011 | // start-sanitize-cygnus-never | |
5012 | ||
5013 | // // FIXME FIXME FIXME What is this? | |
5014 | // 11100,******,00001:RR:16::SDBBP | |
5015 | // *mips16: | |
5016 | // { | |
5017 | // unsigned32 instruction = instruction_0; | |
5018 | // if (have_extendval) | |
5019 | // SignalException (ReservedInstruction, instruction); | |
5020 | // { | |
5021 | // SignalException(DebugBreakPoint,instruction); | |
5022 | // } | |
5023 | // } | |
f2b30012 AC |
5024 | |
5025 | // end-sanitize-cygnus-never | |
5026 | // start-sanitize-cygnus-never | |
5027 | ||
49a6eed5 AC |
5028 | // // FIXME FIXME FIXME What is this? |
5029 | // 000000,********************,001110:SPECIAL:32::SDBBP | |
5030 | // *r3900: | |
5031 | // { | |
5032 | // unsigned32 instruction = instruction_0; | |
5033 | // { | |
5034 | // SignalException(DebugBreakPoint,instruction); | |
5035 | // } | |
5036 | // } | |
f2b30012 AC |
5037 | |
5038 | // end-sanitize-cygnus-never | |
5039 | // start-sanitize-cygnus-never | |
5040 | ||
49a6eed5 AC |
5041 | // // FIXME FIXME FIXME This apparently belongs to the vr4100 which |
5042 | // // isn't yet reconized by this simulator. | |
5043 | // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16 | |
5044 | // *vr4100: | |
5045 | // { | |
5046 | // unsigned32 instruction = instruction_0; | |
055ee297 AC |
5047 | // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; |
5048 | // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
49a6eed5 AC |
5049 | // { |
5050 | // CHECKHILO("Multiply-Add"); | |
5051 | // { | |
5052 | // unsigned64 temp = (op1 * op2); | |
5053 | // temp += (SET64HI(VL4_8(HI)) | VL4_8(LO)); | |
5054 | // LO = SIGNEXTEND((unsigned64)VL4_8(temp),32); | |
5055 | // HI = SIGNEXTEND((unsigned64)VH4_8(temp),32); | |
5056 | // } | |
5057 | // } | |
5058 | // } | |
f2b30012 AC |
5059 | |
5060 | // end-sanitize-cygnus-never | |
49a6eed5 AC |
5061 | // start-sanitize-cygnus-never |
5062 | ||
5063 | // // FIXME FIXME FIXME This apparently belongs to the vr4100 which | |
5064 | // // isn't yet reconized by this simulator. | |
5065 | // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16 | |
5066 | // *vr4100: | |
5067 | // { | |
5068 | // unsigned32 instruction = instruction_0; | |
055ee297 AC |
5069 | // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; |
5070 | // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
49a6eed5 AC |
5071 | // { |
5072 | // CHECKHILO("Multiply-Add"); | |
5073 | // { | |
5074 | // unsigned64 temp = (op1 * op2); | |
5075 | // LO = LO + temp; | |
5076 | // } | |
5077 | // } | |
5078 | // } | |
5079 | ||
5080 | // start-sanitize-cygnus-never |