projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gold: Add view and view_size parameters to is_call_to_non_split.
[deliverable/binutils-gdb.git] / sim / mips / mips.igen
CommitLineData
c906108c
SS		 1// -*- C -*-
2//
c906108c
SS		 3// <insn> ::=
4// <insn-word> { "+" <insn-word> }
5// ":" <format-name>
6// ":" <filter-flags>
7// ":" <options>
8// ":" <name>
9// <nl>
10// { <insn-model> }
11// { <insn-mnemonic> }
12// <code-block>
13//
14
15
16// IGEN config - mips16
17// :option:16::insn-bit-size:16
18// :option:16::hi-bit-nr:15
19:option:16::insn-specifying-widths:true
20:option:16::gen-delayed-branch:false
21
22// IGEN config - mips32/64..
23// :option:32::insn-bit-size:32
24// :option:32::hi-bit-nr:31
25:option:32::insn-specifying-widths:true
26:option:32::gen-delayed-branch:false
27
28
29// Generate separate simulators for each target
30// :option:::multi-sim:true
31
32
074e9cb8 33// Models known by this simulator are defined below.
c5d00cc7
CD		 34//
35// When placing models in the instruction descriptions, please place
36// them one per line, in the order given here.
074e9cb8
CD		 37
38// MIPS ISAs:
39//
40// Instructions and related functions for these models are included in
41// this file.
c906108c
SS		 42:model:::mipsI:mips3000:
43:model:::mipsII:mips6000:
44:model:::mipsIII:mips4000:
45:model:::mipsIV:mips8000:
603a98e7 46:model:::mipsV:mipsisaV:
1e799e28 47:model:::mips32:mipsisa32:
e70cb6cd 48:model:::mips32r2:mipsisa32r2:
1e799e28 49:model:::mips64:mipsisa64:
e70cb6cd 50:model:::mips64r2:mipsisa64r2:
074e9cb8
CD		 51
52// Vendor ISAs:
53//
54// Standard MIPS ISA instructions used for these models are listed here,
55// as are functions needed by those standard instructions. Instructions
56// which are model-dependent and which are not in the standard MIPS ISAs
57// (or which pre-date or use different encodings than the standard
58// instructions) are (for the most part) in separate .igen files.
59:model:::vr4100:mips4100: // vr.igen
4c54fc26 60:model:::vr4120:mips4120:
c906108c 61:model:::vr5000:mips5000:
4c54fc26
CD		 62:model:::vr5400:mips5400:
63:model:::vr5500:mips5500:
074e9cb8 64:model:::r3900:mips3900: // tx.igen
c906108c 65
074e9cb8
CD		 66// MIPS Application Specific Extensions (ASEs)
67//
68// Instructions for the ASEs are in separate .igen files.
f4f1b9f1 69// ASEs add instructions on to a base ISA.
074e9cb8 70:model:::mips16:mips16: // m16.igen (and m16.dc)
b16d63da 71:model:::mips16e:mips16e: // m16e.igen
e7e81181 72:model:::mips3d:mips3d: // mips3d.igen
f4f1b9f1 73:model:::mdmx:mdmx: // mdmx.igen
40a5538e 74:model:::dsp:dsp: // dsp.igen
8b082fb1 75:model:::dsp2:dsp2: // dsp2.igen
2d2733fc 76:model:::smartmips:smartmips: // smartmips.igen
8e394ffc
AB		 77:model:::micromips32:micromips64: // micromips.igen
78:model:::micromips64:micromips64: // micromips.igen
79:model:::micromipsdsp:micromipsdsp: // micromipsdsp.igen
c906108c 80
7cbea089
CD		 81// Vendor Extensions
82//
83// Instructions specific to these extensions are in separate .igen files.
84// Extensions add instructions on to a base ISA.
85:model:::sb1:sb1: // sb1.igen
86
c906108c
SS		 87
88// Pseudo instructions known by IGEN
89:internal::::illegal:
90{
91 SignalException (ReservedInstruction, 0);
92}
93
94
95// Pseudo instructions known by interp.c
96// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
8e394ffc 97000000,5.*,5.*,5.*,5.OP,111001:SPECIAL:32::RSVD
c906108c
SS		 98"rsvd <OP>"
99{
100 SignalException (ReservedInstruction, instruction_0);
101}
102
103
104
105// Helper:
106//
107// Simulate a 32 bit delayslot instruction
108//
109
110:function:::address_word:delayslot32:address_word target
111{
112 instruction_word delay_insn;
113 sim_events_slip (SD, 1);
114 DSPC = CIA;
115 CIA = CIA + 4; /* NOTE not mips16 */
116 STATE |= simDELAYSLOT;
117 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
d4f3574e 118 ENGINE_ISSUE_PREFIX_HOOK();
c906108c
SS		 119 idecode_issue (CPU_, delay_insn, (CIA));
120 STATE &= ~simDELAYSLOT;
121 return target;
122}
123
124:function:::address_word:nullify_next_insn32:
125{
126 sim_events_slip (SD, 1);
127 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
128 return CIA + 8;
129}
130
09297648
CD		 131
132// Helper:
133//
134// Calculate an effective address given a base and an offset.
135//
136
137:function:::address_word:loadstore_ea:address_word base, address_word offset
138*mipsI:
139*mipsII:
140*mipsIII:
141*mipsIV:
142*mipsV:
1e799e28 143*mips32:
e70cb6cd 144*mips32r2:
09297648
CD		 145*vr4100:
146*vr5000:
147*r3900:
8e394ffc 148*micromips32:
09297648
CD		 149{
150 return base + offset;
151}
152
1e799e28
CD		 153:function:::address_word:loadstore_ea:address_word base, address_word offset
154*mips64:
e70cb6cd 155*mips64r2:
8e394ffc 156*micromips64:
1e799e28
CD		 157{
158#if 0 /* XXX FIXME: enable this only after some additional testing. */
159 /* If in user mode and UX is not set, use 32-bit compatibility effective
160 address computations as defined in the MIPS64 Architecture for
161 Programmers Volume III, Revision 0.95, section 4.9. */
162 if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
163 == (ksu_user << status_KSU_shift))
164 return (address_word)((signed32)base + (signed32)offset);
165#endif
166 return base + offset;
167}
168
09297648 169
402586aa
CD		 170// Helper:
171//
172// Check that a 32-bit register value is properly sign-extended.
173// (See NotWordValue in ISA spec.)
174//
175
176:function:::int:not_word_value:unsigned_word value
177*mipsI:
178*mipsII:
179*mipsIII:
180*mipsIV:
181*mipsV:
182*vr4100:
183*vr5000:
184*r3900:
402586aa 185*mips32:
e70cb6cd 186*mips32r2:
402586aa 187*mips64:
e70cb6cd 188*mips64r2:
8e394ffc
AB		 189*micromips32:
190*micromips64:
402586aa 191{
14fb6c5a
TS		 192#if WITH_TARGET_WORD_BITSIZE == 64
193 return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
194#else
195 return 0;
196#endif
402586aa
CD		 197}
198
402586aa
CD		 199// Helper:
200//
201// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
202// theoretically portable code which invokes non-portable behaviour from
203// running with no indication of the portability issue.
204// (See definition of UNPREDICTABLE in ISA spec.)
205//
206
207:function:::void:unpredictable:
208*mipsI:
209*mipsII:
210*mipsIII:
211*mipsIV:
212*mipsV:
213*vr4100:
214*vr5000:
215*r3900:
216{
217}
218
219:function:::void:unpredictable:
220*mips32:
e70cb6cd 221*mips32r2:
402586aa 222*mips64:
e70cb6cd 223*mips64r2:
8e394ffc
AB		 224*micromips32:
225*micromips64:
402586aa
CD		 226{
227 unpredictable_action (CPU, CIA);
228}
229
230
b3208fb8 231// Helpers:
4a0bd876 232//
c906108c
SS		 233// Check that an access to a HI/LO register meets timing requirements
234//
b3208fb8 235// In all MIPS ISAs,
c906108c 236//
b3208fb8
CD		 237// OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
238// makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
239//
240// The following restrictions exist for MIPS I - MIPS III:
241//
242// MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
243// in between makes MF UNPREDICTABLE. (2)
244//
245// MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
246// in between makes MF UNPREDICTABLE. (3)
247//
248// On the r3900, restriction (2) is not present, and restriction (3) is not
249// present for multiplication.
250//
0e1b7197
RS		 251// Unfortunately, there seems to be some confusion about whether the last
252// two restrictions should apply to "MIPS IV" as well. One edition of
253// the MIPS IV ISA says they do, but references in later ISA documents
254// suggest they don't.
255//
256// In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
257// these restrictions, while others, like the VR5500, don't. To accomodate
258// such differences, the MIPS IV and MIPS V version of these helper functions
259// use auxillary routines to determine whether the restriction applies.
b3208fb8
CD		 260
261// check_mf_cycles:
262//
263// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
264// to check for restrictions (2) and (3) above.
c906108c 265//
c906108c
SS		 266:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
267{
268 if (history->mf.timestamp + 3 > time)
269 {
270 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
271 itable[MY_INDEX].name,
272 new, (long) CIA,
4a0bd876 273 (long) history->mf.cia);
c906108c
SS		 274 return 0;
275 }
276 return 1;
277}
278
b3208fb8
CD		 279
280// check_mt_hilo:
281//
282// Check for restriction (2) above (for ISAs/processors that have it),
283// and record timestamps for restriction (1) above.
284//
c906108c 285:function:::int:check_mt_hilo:hilo_history *history
c5d00cc7
CD		 286*mipsI:
287*mipsII:
288*mipsIII:
c906108c
SS		 289*vr4100:
290*vr5000:
291{
292 signed64 time = sim_events_time (SD);
293 int ok = check_mf_cycles (SD_, history, time, "MT");
294 history->mt.timestamp = time;
295 history->mt.cia = CIA;
296 return ok;
297}
298
0e1b7197
RS		 299:function:::int:check_mt_hilo:hilo_history *history
300*mipsIV:
301*mipsV:
302{
303 signed64 time = sim_events_time (SD);
304 int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
305 || check_mf_cycles (SD_, history, time, "MT"));
306 history->mt.timestamp = time;
307 history->mt.cia = CIA;
308 return ok;
309}
310
c906108c 311:function:::int:check_mt_hilo:hilo_history *history
1e799e28 312*mips32:
e70cb6cd 313*mips32r2:
1e799e28 314*mips64:
e70cb6cd 315*mips64r2:
c906108c 316*r3900:
8e394ffc
AB		 317*micromips32:
318*micromips64:
c906108c
SS		 319{
320 signed64 time = sim_events_time (SD);
321 history->mt.timestamp = time;
322 history->mt.cia = CIA;
323 return 1;
324}
325
326
b3208fb8
CD		 327// check_mf_hilo:
328//
329// Check for restriction (1) above, and record timestamps for
330// restriction (2) and (3) above.
331//
c906108c 332:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
c5d00cc7
CD		 333*mipsI:
334*mipsII:
335*mipsIII:
336*mipsIV:
603a98e7 337*mipsV:
1e799e28 338*mips32:
e70cb6cd 339*mips32r2:
1e799e28 340*mips64:
e70cb6cd 341*mips64r2:
c906108c
SS		 342*vr4100:
343*vr5000:
344*r3900:
8e394ffc
AB		 345*micromips32:
346*micromips64:
c906108c
SS		 347{
348 signed64 time = sim_events_time (SD);
349 int ok = 1;
350 if (peer != NULL
351 && peer->mt.timestamp > history->op.timestamp
352 && history->mt.timestamp < history->op.timestamp
353 && ! (history->mf.timestamp > history->op.timestamp
354 && history->mf.timestamp < peer->mt.timestamp)
355 && ! (peer->mf.timestamp > history->op.timestamp
356 && peer->mf.timestamp < peer->mt.timestamp))
357 {
358 /* The peer has been written to since the last OP yet we have
359 not */
360 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
361 itable[MY_INDEX].name,
362 (long) CIA,
363 (long) history->op.cia,
4a0bd876 364 (long) peer->mt.cia);
c906108c
SS		 365 ok = 0;
366 }
367 history->mf.timestamp = time;
368 history->mf.cia = CIA;
369 return ok;
370}
371
372
373
b3208fb8
CD		 374// check_mult_hilo:
375//
376// Check for restriction (3) above (for ISAs/processors that have it)
377// for MULT ops, and record timestamps for restriction (1) above.
378//
c906108c 379:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
c5d00cc7
CD		 380*mipsI:
381*mipsII:
382*mipsIII:
c906108c
SS		 383*vr4100:
384*vr5000:
385{
386 signed64 time = sim_events_time (SD);
387 int ok = (check_mf_cycles (SD_, hi, time, "OP")
388 && check_mf_cycles (SD_, lo, time, "OP"));
389 hi->op.timestamp = time;
390 lo->op.timestamp = time;
391 hi->op.cia = CIA;
392 lo->op.cia = CIA;
393 return ok;
394}
395
0e1b7197
RS		 396:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
397*mipsIV:
398*mipsV:
399{
400 signed64 time = sim_events_time (SD);
401 int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
402 || (check_mf_cycles (SD_, hi, time, "OP")
403 && check_mf_cycles (SD_, lo, time, "OP")));
404 hi->op.timestamp = time;
405 lo->op.timestamp = time;
406 hi->op.cia = CIA;
407 lo->op.cia = CIA;
408 return ok;
409}
410
c906108c 411:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
1e799e28 412*mips32:
e70cb6cd 413*mips32r2:
1e799e28 414*mips64:
e70cb6cd 415*mips64r2:
c906108c 416*r3900:
8e394ffc
AB		 417*micromips32:
418*micromips64:
c906108c
SS		 419{
420 /* FIXME: could record the fact that a stall occured if we want */
421 signed64 time = sim_events_time (SD);
422 hi->op.timestamp = time;
423 lo->op.timestamp = time;
424 hi->op.cia = CIA;
425 lo->op.cia = CIA;
426 return 1;
427}
428
429
b3208fb8
CD		 430// check_div_hilo:
431//
432// Check for restriction (3) above (for ISAs/processors that have it)
433// for DIV ops, and record timestamps for restriction (1) above.
434//
c906108c 435:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
c5d00cc7
CD		 436*mipsI:
437*mipsII:
438*mipsIII:
c906108c
SS		 439*vr4100:
440*vr5000:
441*r3900:
442{
443 signed64 time = sim_events_time (SD);
444 int ok = (check_mf_cycles (SD_, hi, time, "OP")
445 && check_mf_cycles (SD_, lo, time, "OP"));
446 hi->op.timestamp = time;
447 lo->op.timestamp = time;
448 hi->op.cia = CIA;
449 lo->op.cia = CIA;
450 return ok;
451}
452
0e1b7197
RS		 453:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
454*mipsIV:
455*mipsV:
456{
457 signed64 time = sim_events_time (SD);
458 int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
459 || (check_mf_cycles (SD_, hi, time, "OP")
460 && check_mf_cycles (SD_, lo, time, "OP")));
461 hi->op.timestamp = time;
462 lo->op.timestamp = time;
463 hi->op.cia = CIA;
464 lo->op.cia = CIA;
465 return ok;
466}
467
b3208fb8
CD		 468:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
469*mips32:
e70cb6cd 470*mips32r2:
b3208fb8 471*mips64:
e70cb6cd 472*mips64r2:
8e394ffc
AB		 473*micromips32:
474*micromips64:
b3208fb8
CD		 475{
476 signed64 time = sim_events_time (SD);
477 hi->op.timestamp = time;
478 lo->op.timestamp = time;
479 hi->op.cia = CIA;
480 lo->op.cia = CIA;
481 return 1;
482}
483
c906108c 484
ca971540 485// Helper:
4a0bd876 486//
ca971540 487// Check that the 64-bit instruction can currently be used, and signal
b5040d49 488// a ReservedInstruction exception if not.
ca971540
CD		 489//
490
491:function:::void:check_u64:instruction_word insn
492*mipsIII:
493*mipsIV:
494*mipsV:
495*vr4100:
496*vr5000:
e70cb6cd
CD		 497*vr5400:
498*vr5500:
ca971540 499{
ca971540
CD		 500 // The check should be similar to mips64 for any with PX/UX bit equivalents.
501}
c906108c 502
1e799e28 503:function:::void:check_u64:instruction_word insn
b16d63da 504*mips16e:
1e799e28 505*mips64:
e70cb6cd 506*mips64r2:
8e394ffc
AB		 507*mips32:
508*mips32r2:
509*micromips64:
510*micromips32:
1e799e28
CD		 511{
512#if 0 /* XXX FIXME: enable this only after some additional testing. */
513 if (UserMode && (SR & (status_UX|status_PX)) == 0)
514 SignalException (ReservedInstruction, insn);
515#endif
516}
517
c906108c
SS		 518
519
520//
074e9cb8 521// MIPS Architecture:
c906108c 522//
e70cb6cd 523// CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
c906108c
SS		 524//
525
526
8e394ffc
AB		 527:function:::void:do_add:int rs, int rt, int rd
528{
529 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
530 Unpredictable ();
531 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
532 {
533 ALU32_BEGIN (GPR[rs]);
534 ALU32_ADD (GPR[rt]);
535 ALU32_END (GPR[rd]); /* This checks for overflow. */
536 }
537 TRACE_ALU_RESULT (GPR[rd]);
538}
539
540:function:::void:do_addi:int rs, int rt, unsigned16 immediate
541{
542 if (NotWordValue (GPR[rs]))
543 Unpredictable ();
544 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
545 {
546 ALU32_BEGIN (GPR[rs]);
547 ALU32_ADD (EXTEND16 (immediate));
548 ALU32_END (GPR[rt]); /* This checks for overflow. */
549 }
550 TRACE_ALU_RESULT (GPR[rt]);
551}
552
553:function:::void:do_andi:int rs, int rt, unsigned int immediate
554{
555 TRACE_ALU_INPUT2 (GPR[rs], immediate);
556 GPR[rt] = GPR[rs] & immediate;
557 TRACE_ALU_RESULT (GPR[rt]);
558}
559
560:function:::void:do_dadd:int rd, int rs, int rt
561{
562 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
563 {
564 ALU64_BEGIN (GPR[rs]);
565 ALU64_ADD (GPR[rt]);
566 ALU64_END (GPR[rd]); /* This checks for overflow. */
567 }
568 TRACE_ALU_RESULT (GPR[rd]);
569}
570
571:function:::void:do_daddi:int rt, int rs, int immediate
572{
573 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
574 {
575 ALU64_BEGIN (GPR[rs]);
576 ALU64_ADD (EXTEND16 (immediate));
577 ALU64_END (GPR[rt]); /* This checks for overflow. */
578 }
579 TRACE_ALU_RESULT (GPR[rt]);
580}
581
582:function:::void:do_dsll32:int rd, int rt, int shift
583{
584 int s = 32 + shift;
585 TRACE_ALU_INPUT2 (GPR[rt], s);
586 GPR[rd] = GPR[rt] << s;
587 TRACE_ALU_RESULT (GPR[rd]);
588}
589
590:function:::void:do_dsra32:int rd, int rt, int shift
591{
592 int s = 32 + shift;
593 TRACE_ALU_INPUT2 (GPR[rt], s);
594 GPR[rd] = ((signed64) GPR[rt]) >> s;
595 TRACE_ALU_RESULT (GPR[rd]);
596}
597
598:function:::void:do_dsrl32:int rd, int rt, int shift
599{
600 int s = 32 + shift;
601 TRACE_ALU_INPUT2 (GPR[rt], s);
602 GPR[rd] = (unsigned64) GPR[rt] >> s;
603 TRACE_ALU_RESULT (GPR[rd]);
604}
605
606:function:::void:do_dsub:int rd, int rs, int rt
607{
608 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
609 {
610 ALU64_BEGIN (GPR[rs]);
611 ALU64_SUB (GPR[rt]);
612 ALU64_END (GPR[rd]); /* This checks for overflow. */
613 }
614 TRACE_ALU_RESULT (GPR[rd]);
615}
616
617:function:::void:do_break:address_word instruction_0
618{
619 /* Check for some break instruction which are reserved for use by the
620 simulator. */
621 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
622 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
623 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
624 {
625 sim_engine_halt (SD, CPU, NULL, cia,
626 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
627 }
628 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
629 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
630 {
631 if (STATE & simDELAYSLOT)
632 PC = cia - 4; /* reference the branch instruction */
633 else
634 PC = cia;
635 SignalException (BreakPoint, instruction_0);
636 }
637
638 else
639 {
640 /* If we get this far, we're not an instruction reserved by the sim. Raise
641 the exception. */
642 SignalException (BreakPoint, instruction_0);
643 }
644}
645
646:function:::void:do_break16:address_word instruction_0
647{
648 if (STATE & simDELAYSLOT)
649 PC = cia - 2; /* reference the branch instruction */
650 else
651 PC = cia;
652 SignalException (BreakPoint, instruction_0);
653}
654
655:function:::void:do_clo:int rd, int rs
656{
657 unsigned32 temp = GPR[rs];
658 unsigned32 i, mask;
659 if (NotWordValue (GPR[rs]))
660 Unpredictable ();
661 TRACE_ALU_INPUT1 (GPR[rs]);
662 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
663 {
664 if ((temp & mask) == 0)
665 break;
666 mask >>= 1;
667 }
668 GPR[rd] = EXTEND32 (i);
669 TRACE_ALU_RESULT (GPR[rd]);
670}
671
672:function:::void:do_clz:int rd, int rs
673{
674 unsigned32 temp = GPR[rs];
675 unsigned32 i, mask;
676 if (NotWordValue (GPR[rs]))
677 Unpredictable ();
678 TRACE_ALU_INPUT1 (GPR[rs]);
679 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
680 {
681 if ((temp & mask) != 0)
682 break;
683 mask >>= 1;
684 }
685 GPR[rd] = EXTEND32 (i);
686 TRACE_ALU_RESULT (GPR[rd]);
687}
688
689:function:::void:do_dclo:int rd, int rs
690{
691 unsigned64 temp = GPR[rs];
692 unsigned32 i;
693 unsigned64 mask;
694 TRACE_ALU_INPUT1 (GPR[rs]);
695 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
696 {
697 if ((temp & mask) == 0)
698 break;
699 mask >>= 1;
700 }
701 GPR[rd] = EXTEND32 (i);
702 TRACE_ALU_RESULT (GPR[rd]);
703}
704
705:function:::void:do_dclz:int rd, int rs
706{
707 unsigned64 temp = GPR[rs];
708 unsigned32 i;
709 unsigned64 mask;
710 TRACE_ALU_INPUT1 (GPR[rs]);
711 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
712 {
713 if ((temp & mask) != 0)
714 break;
715 mask >>= 1;
716 }
717 GPR[rd] = EXTEND32 (i);
718 TRACE_ALU_RESULT (GPR[rd]);
719}
720
721:function:::void:do_lb:int rt, int offset, int base
722{
723 GPR[rt] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[base],
724 EXTEND16 (offset)));
725}
726
727:function:::void:do_lh:int rt, int offset, int base
728{
729 GPR[rt] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[base],
730 EXTEND16 (offset)));
731}
732
733:function:::void:do_lwr:int rt, int offset, int base
734{
735 GPR[rt] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[base],
736 EXTEND16 (offset), GPR[rt]));
737}
738
739:function:::void:do_lwl:int rt, int offset, int base
740{
741 GPR[rt] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[base],
742 EXTEND16 (offset), GPR[rt]));
743}
744
745:function:::void:do_lwc:int num, int rt, int offset, int base
746{
747 COP_LW (num, rt, do_load (SD_, AccessLength_WORD, GPR[base],
748 EXTEND16 (offset)));
749}
750
751:function:::void:do_lw:int rt, int offset, int base
752{
753 GPR[rt] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[base],
754 EXTEND16 (offset)));
755}
756
757:function:::void:do_lwu:int rt, int offset, int base, address_word instruction_0
758{
759 check_u64 (SD_, instruction_0);
760 GPR[rt] = do_load (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset));
761}
762
763:function:::void:do_lhu:int rt, int offset, int base
764{
765 GPR[rt] = do_load (SD_, AccessLength_HALFWORD, GPR[base], EXTEND16 (offset));
766}
767
768:function:::void:do_ldc:int num, int rt, int offset, int base
769{
770 COP_LD (num, rt, do_load (SD_, AccessLength_DOUBLEWORD, GPR[base],
771 EXTEND16 (offset)));
772}
773
774:function:::void:do_lbu:int rt, int offset, int base
775{
776 GPR[rt] = do_load (SD_, AccessLength_BYTE, GPR[base], EXTEND16 (offset));
777}
778
779:function:::void:do_ll:int rt, int insn_offset, int basereg
780{
781 address_word base = GPR[basereg];
782 address_word offset = EXTEND16 (insn_offset);
783 {
784 address_word vaddr = loadstore_ea (SD_, base, offset);
26f8bf63 785 address_word paddr = vaddr;
8e394ffc
AB		 786 if ((vaddr & 3) != 0)
787 {
788 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer,
789 sim_core_unaligned_signal);
790 }
791 else
792 {
26f8bf63
MF		 793 unsigned64 memval = 0;
794 unsigned64 memval1 = 0;
795 unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
796 unsigned int shift = 2;
797 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
798 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
799 unsigned int byte;
800 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
801 LoadMemory (&memval, &memval1, AccessLength_WORD, paddr, vaddr,
802 isDATA, isREAL);
803 byte = ((vaddr & mask) ^ (bigend << shift));
804 GPR[rt] = EXTEND32 (memval >> (8 * byte));
805 LLBIT = 1;
8e394ffc
AB		 806 }
807 }
808}
809
810:function:::void:do_lld:int rt, int roffset, int rbase
811{
812 address_word base = GPR[rbase];
813 address_word offset = EXTEND16 (roffset);
814 {
815 address_word vaddr = loadstore_ea (SD_, base, offset);
26f8bf63
MF		 816 address_word paddr = vaddr;
817
8e394ffc
AB		 818 if ((vaddr & 7) != 0)
819 {
820 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer,
821 sim_core_unaligned_signal);
822 }
823 else
824 {
26f8bf63
MF		 825 unsigned64 memval = 0;
826 unsigned64 memval1 = 0;
827 LoadMemory (&memval, &memval1, AccessLength_DOUBLEWORD, paddr, vaddr,
828 isDATA, isREAL);
829 GPR[rt] = memval;
830 LLBIT = 1;
8e394ffc
AB		 831 }
832 }
833}
834
835:function:::void:do_lui:int rt, int immediate
836{
837 TRACE_ALU_INPUT1 (immediate);
838 GPR[rt] = EXTEND32 (immediate << 16);
839 TRACE_ALU_RESULT (GPR[rt]);
840}
841
842:function:::void:do_madd:int rs, int rt
843{
844 signed64 temp;
845 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
846 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
847 Unpredictable ();
848 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
849 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
850 + ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
851 LO = EXTEND32 (temp);
852 HI = EXTEND32 (VH4_8 (temp));
853 TRACE_ALU_RESULT2 (HI, LO);
854}
855
856:function:::void:do_dsp_madd:int ac, int rs, int rt
857{
858 signed64 temp;
859 if (ac == 0)
860 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
861 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
862 Unpredictable ();
863 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
864 temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
865 + ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
866 DSPLO(ac) = EXTEND32 (temp);
867 DSPHI(ac) = EXTEND32 (VH4_8 (temp));
868 if (ac == 0)
869 TRACE_ALU_RESULT2 (HI, LO);
870}
871
872:function:::void:do_maddu:int rs, int rt
873{
874 unsigned64 temp;
875 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
876 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
877 Unpredictable ();
878 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
879 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
880 + ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
881 ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
882 LO = EXTEND32 (temp);
883 HI = EXTEND32 (VH4_8 (temp));
884 TRACE_ALU_RESULT2 (HI, LO);
885}
886
887:function:::void:do_dsp_maddu:int ac, int rs, int rt
888{
889 unsigned64 temp;
890 if (ac == 0)
891 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
892 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
893 Unpredictable ();
894 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
895 temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
896 + ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
897 if (ac == 0)
898 ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
899 DSPLO(ac) = EXTEND32 (temp);
900 DSPHI(ac) = EXTEND32 (VH4_8 (temp));
901 if (ac == 0)
902 TRACE_ALU_RESULT2 (HI, LO);
903}
904
905:function:::void:do_dsp_mfhi:int ac, int rd
906{
907 if (ac == 0)
908 do_mfhi (SD_, rd);
909 else
910 GPR[rd] = DSPHI(ac);
911}
912
913:function:::void:do_dsp_mflo:int ac, int rd
914{
915 if (ac == 0)
916 do_mflo (SD_, rd);
917 else
918 GPR[rd] = DSPLO(ac);
919}
920
921:function:::void:do_movn:int rd, int rs, int rt
922{
923 if (GPR[rt] != 0)
924 {
925 GPR[rd] = GPR[rs];
926 TRACE_ALU_RESULT (GPR[rd]);
927 }
928}
929
930:function:::void:do_movz:int rd, int rs, int rt
931{
932 if (GPR[rt] == 0)
933 {
934 GPR[rd] = GPR[rs];
935 TRACE_ALU_RESULT (GPR[rd]);
936 }
937}
938
939:function:::void:do_msub:int rs, int rt
940{
941 signed64 temp;
942 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
943 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
944 Unpredictable ();
945 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
946 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
947 - ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
948 LO = EXTEND32 (temp);
949 HI = EXTEND32 (VH4_8 (temp));
950 TRACE_ALU_RESULT2 (HI, LO);
951}
952
953:function:::void:do_dsp_msub:int ac, int rs, int rt
954{
955 signed64 temp;
956 if (ac == 0)
957 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
958 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
959 Unpredictable ();
960 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
961 temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
962 - ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
963 DSPLO(ac) = EXTEND32 (temp);
964 DSPHI(ac) = EXTEND32 (VH4_8 (temp));
965 if (ac == 0)
966 TRACE_ALU_RESULT2 (HI, LO);
967}
968
969:function:::void:do_msubu:int rs, int rt
970{
971 unsigned64 temp;
972 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
973 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
974 Unpredictable ();
975 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
976 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
977 - ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
978 LO = EXTEND32 (temp);
979 HI = EXTEND32 (VH4_8 (temp));
980 TRACE_ALU_RESULT2 (HI, LO);
981}
982
983:function:::void:do_dsp_msubu:int ac, int rs, int rt
984{
985 unsigned64 temp;
986 if (ac == 0)
987 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
988 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
989 Unpredictable ();
990 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
991 temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
992 - ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
993 DSPLO(ac) = EXTEND32 (temp);
994 DSPHI(ac) = EXTEND32 (VH4_8 (temp));
995 if (ac == 0)
996 TRACE_ALU_RESULT2 (HI, LO);
997}
998
999:function:::void:do_mthi:int rs
1000{
1001 check_mt_hilo (SD_, HIHISTORY);
1002 HI = GPR[rs];
1003}
1004
1005:function:::void:do_dsp_mthi:int ac, int rs
1006{
1007 if (ac == 0)
1008 check_mt_hilo (SD_, HIHISTORY);
1009 DSPHI(ac) = GPR[rs];
1010}
1011
1012:function:::void:do_mtlo:int rs
1013{
1014 check_mt_hilo (SD_, LOHISTORY);
1015 LO = GPR[rs];
1016}
1017
1018:function:::void:do_dsp_mtlo:int ac, int rs
1019{
1020 if (ac == 0)
1021 check_mt_hilo (SD_, LOHISTORY);
1022 DSPLO(ac) = GPR[rs];
1023}
1024
1025:function:::void:do_mul:int rd, int rs, int rt
1026{
1027 signed64 prod;
1028 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1029 Unpredictable ();
1030 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1031 prod = (((signed64)(signed32) GPR[rs])
1032 * ((signed64)(signed32) GPR[rt]));
1033 GPR[rd] = EXTEND32 (VL4_8 (prod));
1034 TRACE_ALU_RESULT (GPR[rd]);
1035}
1036
1037:function:::void:do_dsp_mult:int ac, int rs, int rt
1038{
1039 signed64 prod;
1040 if (ac == 0)
1041 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1042 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1043 Unpredictable ();
1044 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1045 prod = ((signed64)(signed32) GPR[rs])
1046 * ((signed64)(signed32) GPR[rt]);
1047 DSPLO(ac) = EXTEND32 (VL4_8 (prod));
1048 DSPHI(ac) = EXTEND32 (VH4_8 (prod));
1049 if (ac == 0)
1050 {
1051 ACX = 0; /* SmartMIPS */
1052 TRACE_ALU_RESULT2 (HI, LO);
1053 }
1054}
1055
1056:function:::void:do_dsp_multu:int ac, int rs, int rt
1057{
1058 unsigned64 prod;
1059 if (ac == 0)
1060 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1061 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1062 Unpredictable ();
1063 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1064 prod = ((unsigned64)(unsigned32) GPR[rs])
1065 * ((unsigned64)(unsigned32) GPR[rt]);
1066 DSPLO(ac) = EXTEND32 (VL4_8 (prod));
1067 DSPHI(ac) = EXTEND32 (VH4_8 (prod));
1068 if (ac == 0)
1069 TRACE_ALU_RESULT2 (HI, LO);
1070}
1071
1072:function:::void:do_pref:int hint, int insn_offset, int insn_base
1073{
1074 address_word base = GPR[insn_base];
1075 address_word offset = EXTEND16 (insn_offset);
1076 {
1077 address_word vaddr = loadstore_ea (SD_, base, offset);
26f8bf63
MF		 1078 address_word paddr = vaddr;
1079 /* Prefetch (paddr, vaddr, isDATA, hint); */
8e394ffc
AB		 1080 }
1081}
1082
1083:function:::void:do_sc:int rt, int offsetarg, int basereg, address_word instruction_0
1084{
1085 unsigned32 instruction = instruction_0;
1086 address_word base = GPR[basereg];
1087 address_word offset = EXTEND16 (offsetarg);
1088 {
1089 address_word vaddr = loadstore_ea (SD_, base, offset);
26f8bf63
MF		 1090 address_word paddr = vaddr;
1091
8e394ffc
AB		 1092 if ((vaddr & 3) != 0)
1093 {
1094 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
1095 sim_core_unaligned_signal);
1096 }
1097 else
1098 {
26f8bf63
MF		 1099 unsigned64 memval = 0;
1100 unsigned64 memval1 = 0;
1101 unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1102 address_word reverseendian =
1103 (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
1104 address_word bigendiancpu =
1105 (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
1106 unsigned int byte;
1107 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1108 byte = ((vaddr & mask) ^ bigendiancpu);
1109 memval = ((unsigned64) GPR[rt] << (8 * byte));
1110 if (LLBIT)
1111 StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
1112 isREAL);
1113 GPR[rt] = LLBIT;
8e394ffc
AB		 1114 }
1115 }
1116}
1117
1118:function:::void:do_scd:int rt, int roffset, int rbase
1119{
1120 address_word base = GPR[rbase];
1121 address_word offset = EXTEND16 (roffset);
1122 {
1123 address_word vaddr = loadstore_ea (SD_, base, offset);
26f8bf63
MF		 1124 address_word paddr = vaddr;
1125
8e394ffc
AB		 1126 if ((vaddr & 7) != 0)
1127 {
1128 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer,
1129 sim_core_unaligned_signal);
1130 }
1131 else
1132 {
26f8bf63
MF		 1133 unsigned64 memval = 0;
1134 unsigned64 memval1 = 0;
1135 memval = GPR[rt];
1136 if (LLBIT)
1137 StoreMemory (AccessLength_DOUBLEWORD, memval, memval1, paddr, vaddr,
1138 isREAL);
1139 GPR[rt] = LLBIT;
8e394ffc
AB		 1140 }
1141 }
1142}
1143
1144:function:::void:do_sub:int rs, int rt, int rd
1145{
1146 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1147 Unpredictable ();
1148 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1149 {
1150 ALU32_BEGIN (GPR[rs]);
1151 ALU32_SUB (GPR[rt]);
1152 ALU32_END (GPR[rd]); /* This checks for overflow. */
1153 }
1154 TRACE_ALU_RESULT (GPR[rd]);
1155}
1156
1157:function:::void:do_sw:int rt, int offset, int base
1158{
1159 do_store (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset), GPR[rt]);
1160}
1161
1162:function:::void:do_teq:int rs, int rt, address_word instruction_0
1163{
1164 if ((signed_word) GPR[rs] == (signed_word) GPR[rt])
1165 SignalException (Trap, instruction_0);
1166}
1167
1168:function:::void:do_teqi:int rs, int immediate, address_word instruction_0
1169{
1170 if ((signed_word) GPR[rs] == (signed_word) EXTEND16 (immediate))
1171 SignalException (Trap, instruction_0);
1172}
1173
1174:function:::void:do_tge:int rs, int rt, address_word instruction_0
1175{
1176 if ((signed_word) GPR[rs] >= (signed_word) GPR[rt])
1177 SignalException (Trap, instruction_0);
1178}
1179
1180:function:::void:do_tgei:int rs, int immediate, address_word instruction_0
1181{
1182 if ((signed_word) GPR[rs] >= (signed_word) EXTEND16 (immediate))
1183 SignalException (Trap, instruction_0);
1184}
1185
1186:function:::void:do_tgeiu:int rs, int immediate, address_word instruction_0
1187{
1188 if ((unsigned_word) GPR[rs] >= (unsigned_word) EXTEND16 (immediate))
1189 SignalException (Trap, instruction_0);
1190}
1191
1192:function:::void:do_tgeu:int rs ,int rt, address_word instruction_0
1193{
1194 if ((unsigned_word) GPR[rs] >= (unsigned_word) GPR[rt])
1195 SignalException (Trap, instruction_0);
1196}
1197
1198:function:::void:do_tlt:int rs, int rt, address_word instruction_0
1199{
1200 if ((signed_word) GPR[rs] < (signed_word) GPR[rt])
1201 SignalException (Trap, instruction_0);
1202}
1203
1204:function:::void:do_tlti:int rs, int immediate, address_word instruction_0
1205{
1206 if ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate))
1207 SignalException (Trap, instruction_0);
1208}
1209
1210:function:::void:do_tltiu:int rs, int immediate, address_word instruction_0
1211{
1212 if ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate))
1213 SignalException (Trap, instruction_0);
1214}
1215
1216:function:::void:do_tltu:int rs, int rt, address_word instruction_0
1217{
1218 if ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt])
1219 SignalException (Trap, instruction_0);
1220}
1221
1222:function:::void:do_tne:int rs, int rt, address_word instruction_0
1223{
1224 if ((signed_word) GPR[rs] != (signed_word) GPR[rt])
1225 SignalException (Trap, instruction_0);
1226}
1227
1228:function:::void:do_tnei:int rs, int immediate, address_word instruction_0
1229{
1230 if ((signed_word) GPR[rs] != (signed_word) EXTEND16 (immediate))
1231 SignalException (Trap, instruction_0);
1232}
1233
1234:function:::void:do_abs_fmt:int fmt, int fd, int fs, address_word instruction_0
1235{
1236 check_fpu (SD_);
1237 check_fmt_p (SD_, fmt, instruction_0);
1238 StoreFPR (fd, fmt, AbsoluteValue (ValueFPR (fs, fmt), fmt));
1239}
1240
1241:function:::void:do_add_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
1242{
1243 check_fpu (SD_);
1244 check_fmt_p (SD_, fmt, instruction_0);
1245 StoreFPR (fd, fmt, Add (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
1246}
1247
1248:function:::void:do_alnv_ps:int fd, int fs, int ft, int rs, address_word instruction_0
1249{
1250 unsigned64 fsx;
1251 unsigned64 ftx;
1252 unsigned64 fdx;
1253 check_fpu (SD_);
1254 check_u64 (SD_, instruction_0);
1255 fsx = ValueFPR (fs, fmt_ps);
1256 if ((GPR[rs] & 0x3) != 0)
1257 Unpredictable ();
1258 if ((GPR[rs] & 0x4) == 0)
1259 fdx = fsx;
1260 else
1261 {
1262 ftx = ValueFPR (ft, fmt_ps);
1263 if (BigEndianCPU)
1264 fdx = PackPS (PSLower (fsx), PSUpper (ftx));
1265 else
1266 fdx = PackPS (PSLower (ftx), PSUpper (fsx));
1267 }
1268 StoreFPR (fd, fmt_ps, fdx);
1269}
1270
1271:function:::void:do_c_cond_fmt:int cond, int fmt, int cc, int fs, int ft, address_word instruction_0
1272{
1273 check_fpu (SD_);
1274 check_fmt_p (SD_, fmt, instruction_0);
1275 Compare (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt, cond, cc);
1276 TRACE_ALU_RESULT (ValueFCR (31));
1277}
1278
1279:function:::void:do_ceil_fmt:int type, int fmt, int fd, int fs, address_word instruction_0
1280{
1281 check_fpu (SD_);
1282 check_fmt_p (SD_, fmt, instruction_0);
1283 StoreFPR (fd, type, Convert (FP_RM_TOPINF, ValueFPR (fs, fmt), fmt,
1284 type));
1285}
1286
1287:function:::void:do_cfc1:int rt, int fs
1288{
1289 check_fpu (SD_);
1290 if (fs == 0 || fs == 25 || fs == 26 || fs == 28 || fs == 31)
1291 {
1292 unsigned_word fcr = ValueFCR (fs);
1293 TRACE_ALU_INPUT1 (fcr);
1294 GPR[rt] = fcr;
1295 }
1296 /* else NOP */
1297 TRACE_ALU_RESULT (GPR[rt]);
1298}
1299
1300:function:::void:do_ctc1:int rt, int fs
1301{
1302 check_fpu (SD_);
1303 TRACE_ALU_INPUT1 (GPR[rt]);
1304 if (fs == 25 || fs == 26 || fs == 28 || fs == 31)
1305 StoreFCR (fs, GPR[rt]);
1306 /* else NOP */
1307}
1308
1309:function:::void:do_cvt_d_fmt:int fmt, int fd, int fs, address_word instruction_0
1310{
1311 check_fpu (SD_);
1312 if ((fmt == fmt_double) | 0)
1313 SignalException (ReservedInstruction, instruction_0);
1314 StoreFPR (fd, fmt_double, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
1315 fmt_double));
1316}
1317
1318:function:::void:do_cvt_l_fmt:int fmt, int fd, int fs, address_word instruction_0
1319{
1320 check_fpu (SD_);
1321 if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
1322 SignalException (ReservedInstruction, instruction_0);
1323 StoreFPR (fd, fmt_long, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
1324 fmt_long));
1325}
1326
1327:function:::void:do_cvt_ps_s:int fd, int fs, int ft, address_word instruction_0
1328{
1329 check_fpu (SD_);
1330 check_u64 (SD_, instruction_0);
1331 StoreFPR (fd, fmt_ps, PackPS (ValueFPR (fs, fmt_single),
1332 ValueFPR (ft, fmt_single)));
1333}
1334
1335:function:::void:do_cvt_s_fmt:int fmt, int fd, int fs, address_word instruction_0
1336{
1337 check_fpu (SD_);
1338 if ((fmt == fmt_single) | 0)
1339 SignalException (ReservedInstruction, instruction_0);
1340 StoreFPR (fd, fmt_single, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
1341 fmt_single));
1342}
1343
1344:function:::void:do_cvt_s_pl:int fd, int fs, address_word instruction_0
1345{
1346 check_fpu (SD_);
1347 check_u64 (SD_, instruction_0);
1348 StoreFPR (fd, fmt_single, PSLower (ValueFPR (fs, fmt_ps)));
1349}
1350
1351:function:::void:do_cvt_s_pu:int fd, int fs, address_word instruction_0
1352{
1353 check_fpu (SD_);
1354 check_u64 (SD_, instruction_0);
1355 StoreFPR (fd, fmt_single, PSUpper (ValueFPR (fs, fmt_ps)));
1356}
1357
1358:function:::void:do_cvt_w_fmt:int fmt, int fd, int fs, address_word instruction_0
1359{
1360 check_fpu (SD_);
1361 if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
1362 SignalException (ReservedInstruction, instruction_0);
1363 StoreFPR (fd, fmt_word, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
1364 fmt_word));
1365}
1366
1367:function:::void:do_div_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
1368{
1369 check_fpu (SD_);
1370 StoreFPR (fd, fmt, Divide (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
1371}
1372
1373:function:::void:do_dmfc1b:int rt, int fs
1374*mipsIV:
1375*mipsV:
1376*mips64:
1377*mips64r2:
1378*vr4100:
1379*vr5000:
1380*r3900:
1381*micromips64:
1382{
1383 if (SizeFGR () == 64)
1384 GPR[rt] = FGR[fs];
1385 else if ((fs & 0x1) == 0)
1386 GPR[rt] = SET64HI (FGR[fs+1]) | FGR[fs];
1387 else
1388 GPR[rt] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
1389 TRACE_ALU_RESULT (GPR[rt]);
1390}
1391
1392:function:::void:do_dmtc1b:int rt, int fs
1393{
1394 if (SizeFGR () == 64)
1395 StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]);
1396 else if ((fs & 0x1) == 0)
1397 StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]);
1398 else
1399 Unpredictable ();
1400}
1401
1402:function:::void:do_floor_fmt:int type, int fmt, int fd, int fs
1403{
1404 check_fpu (SD_);
1405 StoreFPR (fd, type, Convert (FP_RM_TOMINF, ValueFPR (fs, fmt), fmt,
1406 type));
1407}
1408
1409:function:::void:do_luxc1_32:int fd, int rindex, int rbase
1410*mips32r2:
1411*micromips32:
1412{
1413 address_word base = GPR[rbase];
1414 address_word index = GPR[rindex];
1415 address_word vaddr = base + index;
1416 check_fpu (SD_);
1417 if (SizeFGR () != 64)
1418 Unpredictable ();
1419 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
1420 if ((vaddr & 0x7) != 0)
1421 index -= (vaddr & 0x7);
1422 COP_LD (1, fd, do_load_double (SD_, base, index));
1423}
1424
1425:function:::void:do_luxc1_64:int fd, int rindex, int rbase
1426{
1427 address_word base = GPR[rbase];
1428 address_word index = GPR[rindex];
1429 address_word vaddr = base + index;
1430 if (SizeFGR () != 64)
1431 Unpredictable ();
1432 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
1433 if ((vaddr & 0x7) != 0)
1434 index -= (vaddr & 0x7);
1435 COP_LD (1, fd, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
1436
1437}
1438
1439:function:::void:do_lwc1:int ft, int offset, int base
1440{
1441 check_fpu (SD_);
1442 COP_LW (1, ft, do_load (SD_, AccessLength_WORD, GPR[base],
1443 EXTEND16 (offset)));
1444}
1445
1446:function:::void:do_lwxc1:int fd, int index, int base, address_word instruction_0
1447{
1448 check_fpu (SD_);
1449 check_u64 (SD_, instruction_0);
1450 COP_LW (1, fd, do_load (SD_, AccessLength_WORD, GPR[base], GPR[index]));
1451}
1452
1453:function:::void:do_madd_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
1454{
1455 check_fpu (SD_);
1456 check_u64 (SD_, instruction_0);
1457 check_fmt_p (SD_, fmt, instruction_0);
1458 StoreFPR (fd, fmt, MultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
1459 ValueFPR (fr, fmt), fmt));
1460}
1461
1462:function:::void:do_mfc1b:int rt, int fs
1463{
1464 check_fpu (SD_);
1465 GPR[rt] = EXTEND32 (FGR[fs]);
1466 TRACE_ALU_RESULT (GPR[rt]);
1467}
1468
1469:function:::void:do_mov_fmt:int fmt, int fd, int fs, address_word instruction_0
1470{
1471 check_fpu (SD_);
1472 check_fmt_p (SD_, fmt, instruction_0);
1473 StoreFPR (fd, fmt, ValueFPR (fs, fmt));
1474}
1475
1476:function:::void:do_movtf:int tf, int rd, int rs, int cc
1477{
1478 check_fpu (SD_);
1479 if (GETFCC(cc) == tf)
1480 GPR[rd] = GPR[rs];
1481}
1482
1483:function:::void:do_movtf_fmt:int tf, int fmt, int fd, int fs, int cc
1484{
1485 check_fpu (SD_);
1486 if (fmt != fmt_ps)
1487 {
1488 if (GETFCC(cc) == tf)
1489 StoreFPR (fd, fmt, ValueFPR (fs, fmt));
1490 else
1491 StoreFPR (fd, fmt, ValueFPR (fd, fmt)); /* set fmt */
1492 }
1493 else
1494 {
1495 unsigned64 fdx;
1496 fdx = PackPS (PSUpper (ValueFPR ((GETFCC (cc+1) == tf) ? fs : fd,
1497 fmt_ps)),
1498 PSLower (ValueFPR ((GETFCC (cc+0) == tf) ? fs : fd,
1499 fmt_ps)));
1500 StoreFPR (fd, fmt_ps, fdx);
1501 }
1502}
1503
1504:function:::void:do_movn_fmt:int fmt, int fd, int fs, int rt
1505{
1506 check_fpu (SD_);
1507 if (GPR[rt] != 0)
1508 StoreFPR (fd, fmt, ValueFPR (fs, fmt));
1509 else
1510 StoreFPR (fd, fmt, ValueFPR (fd, fmt));
1511}
1512
1513:function:::void:do_movz_fmt:int fmt, int fd, int fs, int rt
1514{
1515 check_fpu (SD_);
1516 if (GPR[rt] == 0)
1517 StoreFPR (fd, fmt, ValueFPR (fs, fmt));
1518 else
1519 StoreFPR (fd, fmt, ValueFPR (fd, fmt));
1520}
1521
1522:function:::void:do_msub_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
1523{
1524 check_fpu (SD_);
1525 check_u64 (SD_, instruction_0);
1526 check_fmt_p (SD_, fmt, instruction_0);
1527 StoreFPR (fd, fmt, MultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
1528 ValueFPR (fr, fmt), fmt));
1529}
1530
1531:function:::void:do_mtc1b:int rt, int fs
1532{
1533 check_fpu (SD_);
1534 StoreFPR (fs, fmt_uninterpreted_32, VL4_8 (GPR[rt]));
1535}
1536
1537:function:::void:do_mul_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
1538{
1539 check_fpu (SD_);
1540 check_fmt_p (SD_, fmt, instruction_0);
1541 StoreFPR (fd, fmt, Multiply (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
1542}
1543
1544:function:::void:do_neg_fmt:int fmt, int fd, int fs, address_word instruction_0
1545{
1546 check_fpu (SD_);
1547 check_fmt_p (SD_, fmt, instruction_0);
1548 StoreFPR (fd, fmt, Negate (ValueFPR (fs, fmt), fmt));
1549}
1550
1551:function:::void:do_nmadd_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
1552{
1553 check_fpu (SD_);
1554 check_u64 (SD_, instruction_0);
1555 check_fmt_p (SD_, fmt, instruction_0);
1556 StoreFPR (fd, fmt, NegMultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
1557 ValueFPR (fr, fmt), fmt));
1558}
1559
1560:function:::void:do_nmsub_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
1561{
1562 check_fpu (SD_);
1563 check_u64 (SD_, instruction_0);
1564 check_fmt_p (SD_, fmt, instruction_0);
1565 StoreFPR (fd, fmt, NegMultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
1566 ValueFPR (fr, fmt), fmt));
1567}
1568
1569:function:::void:do_pll_ps:int fd, int fs, int ft, address_word instruction_0
1570{
1571 check_fpu (SD_);
1572 check_u64 (SD_, instruction_0);
1573 StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)),
1574 PSLower (ValueFPR (ft, fmt_ps))));
1575}
1576
1577:function:::void:do_plu_ps:int fd, int fs, int ft, address_word instruction_0
1578{
1579 check_fpu (SD_);
1580 check_u64 (SD_, instruction_0);
1581 StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)),
1582 PSUpper (ValueFPR (ft, fmt_ps))));
1583}
1584
1585:function:::void:do_pul_ps:int fd, int fs, int ft, address_word instruction_0
1586{
1587 check_fpu (SD_);
1588 check_u64 (SD_, instruction_0);
1589 StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)),
1590 PSLower (ValueFPR (ft, fmt_ps))));
1591}
1592
1593:function:::void:do_puu_ps:int fd, int fs, int ft, address_word instruction_0
1594{
1595 check_fpu (SD_);
1596 check_u64 (SD_, instruction_0);
1597 StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)),
1598 PSUpper (ValueFPR (ft, fmt_ps))));
1599}
1600
1601:function:::void:do_recip_fmt:int fmt, int fd, int fs
1602{
1603 check_fpu (SD_);
1604 StoreFPR (fd, fmt, Recip (ValueFPR (fs, fmt), fmt));
1605}
1606
1607:function:::void:do_round_fmt:int type, int fmt, int fd, int fs
1608{
1609 check_fpu (SD_);
1610 StoreFPR (fd, type, Convert (FP_RM_NEAREST, ValueFPR (fs, fmt), fmt,
1611 type));
1612}
1613
1614:function:::void:do_rsqrt_fmt:int fmt, int fd, int fs
1615{
1616 check_fpu (SD_);
1617 StoreFPR (fd, fmt, RSquareRoot (ValueFPR (fs, fmt), fmt));
1618}
1619
1620:function:::void:do_prefx:int hint, int rindex, int rbase
1621{
1622 address_word base = GPR[rbase];
1623 address_word index = GPR[rindex];
1624 {
1625 address_word vaddr = loadstore_ea (SD_, base, index);
26f8bf63
MF		 1626 address_word paddr = vaddr;
1627 /* Prefetch (paddr, vaddr, isDATA, hint); */
8e394ffc
AB		 1628 }
1629}
1630
1631:function:::void:do_sdc1:int ft, int offset, int base
1632*mipsII:
1633*mips32:
1634*mips32r2:
1635*micromips32:
1636{
1637 check_fpu (SD_);
1638 do_store_double (SD_, GPR[base], EXTEND16 (offset), COP_SD (1, ft));
1639}
1640
1641:function:::void:do_suxc1_32:int fs, int rindex, int rbase
1642*mips32r2:
1643*micromips32:
1644{
1645 address_word base = GPR[rbase];
1646 address_word index = GPR[rindex];
1647 address_word vaddr = base + index;
1648 check_fpu (SD_);
1649 if (SizeFGR () != 64)
1650 Unpredictable ();
1651 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
1652 if ((vaddr & 0x7) != 0)
1653 index -= (vaddr & 0x7);
1654 do_store_double (SD_, base, index, COP_SD (1, fs));
1655}
1656
1657:function:::void:do_suxc1_64:int fs, int rindex, int rbase
1658{
1659 address_word base = GPR[rbase];
1660 address_word index = GPR[rindex];
1661 address_word vaddr = base + index;
1662 if (SizeFGR () != 64)
1663 Unpredictable ();
1664 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
1665 if ((vaddr & 0x7) != 0)
1666 index -= (vaddr & 0x7);
1667 do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, fs));
1668}
1669
1670:function:::void:do_sqrt_fmt:int fmt, int fd, int fs
1671{
1672 check_fpu (SD_);
1673 StoreFPR (fd, fmt, (SquareRoot (ValueFPR (fs, fmt), fmt)));
1674}
1675
1676:function:::void:do_sub_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
1677{
1678 check_fpu (SD_);
1679 check_fmt_p (SD_, fmt, instruction_0);
1680 StoreFPR (fd, fmt, Sub (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
1681}
1682
1683:function:::void:do_swc1:int ft, int roffset, int rbase, address_word instruction_0
1684{
1685 address_word base = GPR[rbase];
1686 address_word offset = EXTEND16 (roffset);
1687 check_fpu (SD_);
1688 {
1689 address_word vaddr = loadstore_ea (SD_, base, offset);
26f8bf63
MF		 1690 address_word paddr = vaddr;
1691
8e394ffc
AB		 1692 if ((vaddr & 3) != 0)
1693 {
1694 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr,
1695 write_transfer, sim_core_unaligned_signal);
1696 }
1697 else
1698 {
26f8bf63
MF		 1699 uword64 memval = 0;
1700 uword64 memval1 = 0;
1701 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1702 address_word reverseendian =
1703 (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
1704 address_word bigendiancpu =
1705 (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
1706 unsigned int byte;
1707 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1708 byte = ((vaddr & mask) ^ bigendiancpu);
1709 memval = (((uword64)COP_SW(1, ft)) << (8 * byte));
1710 StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, isREAL);
8e394ffc
AB		 1711 }
1712 }
1713}
1714
1715:function:::void:do_swxc1:int fs, int rindex, int rbase, address_word instruction_0
1716{
1717 address_word base = GPR[rbase];
1718 address_word index = GPR[rindex];
1719 check_fpu (SD_);
1720 check_u64 (SD_, instruction_0);
1721 {
1722 address_word vaddr = loadstore_ea (SD_, base, index);
26f8bf63
MF		 1723 address_word paddr = vaddr;
1724
8e394ffc
AB		 1725 if ((vaddr & 3) != 0)
1726 {
1727 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
1728 sim_core_unaligned_signal);
1729 }
1730 else
1731 {
26f8bf63
MF		 1732 unsigned64 memval = 0;
1733 unsigned64 memval1 = 0;
1734 unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1735 address_word reverseendian =
1736 (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
1737 address_word bigendiancpu =
1738 (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
1739 unsigned int byte;
1740 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1741 byte = ((vaddr & mask) ^ bigendiancpu);
1742 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
1743 StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
1744 isREAL);
8e394ffc
AB		 1745 }
1746 }
1747}
1748
1749:function:::void:do_trunc_fmt:int type, int fmt, int fd, int fs
1750{
1751 check_fpu (SD_);
1752 StoreFPR (fd, type, Convert (FP_RM_TOZERO, ValueFPR (fs, fmt), fmt,
1753 type));
1754}
c906108c
SS		 1755
1756000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
1757"add r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 1758*mipsI:
1759*mipsII:
1760*mipsIII:
1761*mipsIV:
603a98e7 1762*mipsV:
1e799e28 1763*mips32:
e70cb6cd 1764*mips32r2:
1e799e28 1765*mips64:
e70cb6cd 1766*mips64r2:
c906108c
SS		 1767*vr4100:
1768*vr5000:
1769*r3900:
1770{
8e394ffc 1771 do_add (SD_, RS, RT, RD);
c906108c
SS		 1772}
1773
1774
1775
1776001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
20ae0098 1777"addi r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 1778*mipsI:
1779*mipsII:
1780*mipsIII:
1781*mipsIV:
603a98e7 1782*mipsV:
1e799e28 1783*mips32:
e70cb6cd 1784*mips32r2:
1e799e28 1785*mips64:
e70cb6cd 1786*mips64r2:
c906108c
SS		 1787*vr4100:
1788*vr5000:
1789*r3900:
1790{
8e394ffc 1791 do_addi (SD_, RS, RT, IMMEDIATE);
c906108c
SS		 1792}
1793
1794
1795
1796:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
1797{
402586aa
CD		 1798 if (NotWordValue (GPR[rs]))
1799 Unpredictable ();
c906108c
SS		 1800 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1801 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
1802 TRACE_ALU_RESULT (GPR[rt]);
1803}
1804
1805001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
1806"addiu r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 1807*mipsI:
1808*mipsII:
1809*mipsIII:
1810*mipsIV:
603a98e7 1811*mipsV:
1e799e28 1812*mips32:
e70cb6cd 1813*mips32r2:
1e799e28 1814*mips64:
e70cb6cd 1815*mips64r2:
c906108c
SS		 1816*vr4100:
1817*vr5000:
1818*r3900:
1819{
1820 do_addiu (SD_, RS, RT, IMMEDIATE);
1821}
1822
1823
1824
1825:function:::void:do_addu:int rs, int rt, int rd
1826{
402586aa
CD		 1827 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1828 Unpredictable ();
c906108c
SS		 1829 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1830 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
1831 TRACE_ALU_RESULT (GPR[rd]);
1832}
1833
1834000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
1835"addu r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 1836*mipsI:
1837*mipsII:
1838*mipsIII:
1839*mipsIV:
603a98e7 1840*mipsV:
1e799e28 1841*mips32:
e70cb6cd 1842*mips32r2:
1e799e28 1843*mips64:
e70cb6cd 1844*mips64r2:
c906108c
SS		 1845*vr4100:
1846*vr5000:
1847*r3900:
1848{
1849 do_addu (SD_, RS, RT, RD);
1850}
1851
1852
1853
1854:function:::void:do_and:int rs, int rt, int rd
1855{
1856 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1857 GPR[rd] = GPR[rs] & GPR[rt];
1858 TRACE_ALU_RESULT (GPR[rd]);
1859}
1860
1861000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
1862"and r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 1863*mipsI:
1864*mipsII:
1865*mipsIII:
1866*mipsIV:
603a98e7 1867*mipsV:
1e799e28 1868*mips32:
e70cb6cd 1869*mips32r2:
1e799e28 1870*mips64:
e70cb6cd 1871*mips64r2:
c906108c
SS		 1872*vr4100:
1873*vr5000:
1874*r3900:
1875{
1876 do_and (SD_, RS, RT, RD);
1877}
1878
1879
1880
1881001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
82f728db 1882"andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
c5d00cc7
CD		 1883*mipsI:
1884*mipsII:
1885*mipsIII:
1886*mipsIV:
603a98e7 1887*mipsV:
1e799e28 1888*mips32:
e70cb6cd 1889*mips32r2:
1e799e28 1890*mips64:
e70cb6cd 1891*mips64r2:
c906108c
SS		 1892*vr4100:
1893*vr5000:
1894*r3900:
1895{
8e394ffc 1896 do_andi (SD_,RS, RT, IMMEDIATE);
c906108c
SS		 1897}
1898
1899
1900
1901000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
1902"beq r<RS>, r<RT>, <OFFSET>"
c5d00cc7
CD		 1903*mipsI:
1904*mipsII:
1905*mipsIII:
1906*mipsIV:
603a98e7 1907*mipsV:
1e799e28 1908*mips32:
e70cb6cd 1909*mips32r2:
1e799e28 1910*mips64:
e70cb6cd 1911*mips64r2:
c906108c
SS		 1912*vr4100:
1913*vr5000:
1914*r3900:
1915{
1916 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 1917 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
1918 {
c906108c
SS		 1919 DELAY_SLOT (NIA + offset);
1920 }
1921}
1922
1923
1924
1925010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
1926"beql r<RS>, r<RT>, <OFFSET>"
1927*mipsII:
1928*mipsIII:
1929*mipsIV:
603a98e7 1930*mipsV:
1e799e28 1931*mips32:
e70cb6cd 1932*mips32r2:
1e799e28 1933*mips64:
e70cb6cd 1934*mips64r2:
c906108c
SS		 1935*vr4100:
1936*vr5000:
1937*r3900:
1938{
1939 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 1940 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
1941 {
c906108c
SS		 1942 DELAY_SLOT (NIA + offset);
1943 }
1944 else
1945 NULLIFY_NEXT_INSTRUCTION ();
1946}
1947
1948
1949
1950000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
1951"bgez r<RS>, <OFFSET>"
c5d00cc7
CD		 1952*mipsI:
1953*mipsII:
1954*mipsIII:
1955*mipsIV:
603a98e7 1956*mipsV:
1e799e28 1957*mips32:
e70cb6cd 1958*mips32r2:
1e799e28 1959*mips64:
e70cb6cd 1960*mips64r2:
c906108c
SS		 1961*vr4100:
1962*vr5000:
1963*r3900:
1964{
1965 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 1966 if ((signed_word) GPR[RS] >= 0)
1967 {
c906108c
SS		 1968 DELAY_SLOT (NIA + offset);
1969 }
1970}
1971
1972
1973
1974000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
1975"bgezal r<RS>, <OFFSET>"
c5d00cc7
CD		 1976*mipsI:
1977*mipsII:
1978*mipsIII:
1979*mipsIV:
603a98e7 1980*mipsV:
1e799e28 1981*mips32:
e70cb6cd 1982*mips32r2:
1e799e28 1983*mips64:
e70cb6cd 1984*mips64r2:
c906108c
SS		 1985*vr4100:
1986*vr5000:
1987*r3900:
1988{
1989 address_word offset = EXTEND16 (OFFSET) << 2;
402586aa
CD		 1990 if (RS == 31)
1991 Unpredictable ();
c906108c
SS		 1992 RA = (CIA + 8);
1993 if ((signed_word) GPR[RS] >= 0)
1994 {
c906108c
SS		 1995 DELAY_SLOT (NIA + offset);
1996 }
1997}
1998
1999
2000
2001000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
2002"bgezall r<RS>, <OFFSET>"
2003*mipsII:
2004*mipsIII:
2005*mipsIV:
603a98e7 2006*mipsV:
1e799e28 2007*mips32:
e70cb6cd 2008*mips32r2:
1e799e28 2009*mips64:
e70cb6cd 2010*mips64r2:
c906108c
SS		 2011*vr4100:
2012*vr5000:
2013*r3900:
2014{
2015 address_word offset = EXTEND16 (OFFSET) << 2;
402586aa
CD		 2016 if (RS == 31)
2017 Unpredictable ();
c906108c
SS		 2018 RA = (CIA + 8);
2019 /* NOTE: The branch occurs AFTER the next instruction has been
2020 executed */
2021 if ((signed_word) GPR[RS] >= 0)
2022 {
c906108c
SS		 2023 DELAY_SLOT (NIA + offset);
2024 }
2025 else
2026 NULLIFY_NEXT_INSTRUCTION ();
2027}
2028
2029
2030
2031000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
2032"bgezl r<RS>, <OFFSET>"
2033*mipsII:
2034*mipsIII:
2035*mipsIV:
603a98e7 2036*mipsV:
1e799e28 2037*mips32:
e70cb6cd 2038*mips32r2:
1e799e28 2039*mips64:
e70cb6cd 2040*mips64r2:
c906108c
SS		 2041*vr4100:
2042*vr5000:
2043*r3900:
2044{
2045 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 2046 if ((signed_word) GPR[RS] >= 0)
2047 {
c906108c
SS		 2048 DELAY_SLOT (NIA + offset);
2049 }
2050 else
2051 NULLIFY_NEXT_INSTRUCTION ();
2052}
2053
2054
2055
2056000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
2057"bgtz r<RS>, <OFFSET>"
c5d00cc7
CD		 2058*mipsI:
2059*mipsII:
2060*mipsIII:
2061*mipsIV:
603a98e7 2062*mipsV:
1e799e28 2063*mips32:
e70cb6cd 2064*mips32r2:
1e799e28 2065*mips64:
e70cb6cd 2066*mips64r2:
c906108c
SS		 2067*vr4100:
2068*vr5000:
2069*r3900:
2070{
2071 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 2072 if ((signed_word) GPR[RS] > 0)
2073 {
c906108c
SS		 2074 DELAY_SLOT (NIA + offset);
2075 }
2076}
2077
2078
2079
2080010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
2081"bgtzl r<RS>, <OFFSET>"
2082*mipsII:
2083*mipsIII:
2084*mipsIV:
603a98e7 2085*mipsV:
1e799e28 2086*mips32:
e70cb6cd 2087*mips32r2:
1e799e28 2088*mips64:
e70cb6cd 2089*mips64r2:
c906108c
SS		 2090*vr4100:
2091*vr5000:
2092*r3900:
2093{
2094 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 2095 /* NOTE: The branch occurs AFTER the next instruction has been
2096 executed */
2097 if ((signed_word) GPR[RS] > 0)
2098 {
c906108c
SS		 2099 DELAY_SLOT (NIA + offset);
2100 }
2101 else
2102 NULLIFY_NEXT_INSTRUCTION ();
2103}
2104
2105
2106
2107000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
2108"blez r<RS>, <OFFSET>"
c5d00cc7
CD		 2109*mipsI:
2110*mipsII:
2111*mipsIII:
2112*mipsIV:
603a98e7 2113*mipsV:
1e799e28 2114*mips32:
e70cb6cd 2115*mips32r2:
1e799e28 2116*mips64:
e70cb6cd 2117*mips64r2:
c906108c
SS		 2118*vr4100:
2119*vr5000:
2120*r3900:
2121{
2122 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 2123 /* NOTE: The branch occurs AFTER the next instruction has been
2124 executed */
2125 if ((signed_word) GPR[RS] <= 0)
2126 {
c906108c
SS		 2127 DELAY_SLOT (NIA + offset);
2128 }
2129}
2130
2131
2132
2133010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
2134"bgezl r<RS>, <OFFSET>"
2135*mipsII:
2136*mipsIII:
2137*mipsIV:
603a98e7 2138*mipsV:
1e799e28 2139*mips32:
e70cb6cd 2140*mips32r2:
1e799e28 2141*mips64:
e70cb6cd 2142*mips64r2:
c906108c
SS		 2143*vr4100:
2144*vr5000:
2145*r3900:
2146{
2147 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 2148 if ((signed_word) GPR[RS] <= 0)
2149 {
c906108c
SS		 2150 DELAY_SLOT (NIA + offset);
2151 }
2152 else
2153 NULLIFY_NEXT_INSTRUCTION ();
2154}
2155
2156
2157
2158000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
2159"bltz r<RS>, <OFFSET>"
c5d00cc7
CD		 2160*mipsI:
2161*mipsII:
2162*mipsIII:
2163*mipsIV:
603a98e7 2164*mipsV:
1e799e28 2165*mips32:
e70cb6cd 2166*mips32r2:
1e799e28 2167*mips64:
e70cb6cd 2168*mips64r2:
c906108c
SS		 2169*vr4100:
2170*vr5000:
2171*r3900:
2172{
2173 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 2174 if ((signed_word) GPR[RS] < 0)
2175 {
c906108c
SS		 2176 DELAY_SLOT (NIA + offset);
2177 }
2178}
2179
2180
2181
2182000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
2183"bltzal r<RS>, <OFFSET>"
c5d00cc7
CD		 2184*mipsI:
2185*mipsII:
2186*mipsIII:
2187*mipsIV:
603a98e7 2188*mipsV:
1e799e28 2189*mips32:
e70cb6cd 2190*mips32r2:
1e799e28 2191*mips64:
e70cb6cd 2192*mips64r2:
c906108c
SS		 2193*vr4100:
2194*vr5000:
2195*r3900:
2196{
2197 address_word offset = EXTEND16 (OFFSET) << 2;
402586aa
CD		 2198 if (RS == 31)
2199 Unpredictable ();
c906108c
SS		 2200 RA = (CIA + 8);
2201 /* NOTE: The branch occurs AFTER the next instruction has been
2202 executed */
2203 if ((signed_word) GPR[RS] < 0)
2204 {
c906108c
SS		 2205 DELAY_SLOT (NIA + offset);
2206 }
2207}
2208
2209
2210
2211000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
2212"bltzall r<RS>, <OFFSET>"
2213*mipsII:
2214*mipsIII:
2215*mipsIV:
603a98e7 2216*mipsV:
1e799e28 2217*mips32:
e70cb6cd 2218*mips32r2:
1e799e28 2219*mips64:
e70cb6cd 2220*mips64r2:
c906108c
SS		 2221*vr4100:
2222*vr5000:
2223*r3900:
2224{
2225 address_word offset = EXTEND16 (OFFSET) << 2;
402586aa
CD		 2226 if (RS == 31)
2227 Unpredictable ();
c906108c
SS		 2228 RA = (CIA + 8);
2229 if ((signed_word) GPR[RS] < 0)
2230 {
c906108c
SS		 2231 DELAY_SLOT (NIA + offset);
2232 }
2233 else
2234 NULLIFY_NEXT_INSTRUCTION ();
2235}
2236
2237
2238
2239000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
2240"bltzl r<RS>, <OFFSET>"
2241*mipsII:
2242*mipsIII:
2243*mipsIV:
603a98e7 2244*mipsV:
1e799e28 2245*mips32:
e70cb6cd 2246*mips32r2:
1e799e28 2247*mips64:
e70cb6cd 2248*mips64r2:
c906108c
SS		 2249*vr4100:
2250*vr5000:
2251*r3900:
2252{
2253 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 2254 /* NOTE: The branch occurs AFTER the next instruction has been
2255 executed */
2256 if ((signed_word) GPR[RS] < 0)
2257 {
c906108c
SS		 2258 DELAY_SLOT (NIA + offset);
2259 }
2260 else
2261 NULLIFY_NEXT_INSTRUCTION ();
2262}
2263
2264
2265
2266000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
2267"bne r<RS>, r<RT>, <OFFSET>"
c5d00cc7
CD		 2268*mipsI:
2269*mipsII:
2270*mipsIII:
2271*mipsIV:
603a98e7 2272*mipsV:
1e799e28 2273*mips32:
e70cb6cd 2274*mips32r2:
1e799e28 2275*mips64:
e70cb6cd 2276*mips64r2:
c906108c
SS		 2277*vr4100:
2278*vr5000:
2279*r3900:
2280{
2281 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 2282 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2283 {
c906108c
SS		 2284 DELAY_SLOT (NIA + offset);
2285 }
2286}
2287
2288
2289
2290010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
2291"bnel r<RS>, r<RT>, <OFFSET>"
2292*mipsII:
2293*mipsIII:
2294*mipsIV:
603a98e7 2295*mipsV:
1e799e28 2296*mips32:
e70cb6cd 2297*mips32r2:
1e799e28 2298*mips64:
e70cb6cd 2299*mips64r2:
c906108c
SS		 2300*vr4100:
2301*vr5000:
2302*r3900:
2303{
2304 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 2305 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2306 {
c906108c
SS		 2307 DELAY_SLOT (NIA + offset);
2308 }
2309 else
2310 NULLIFY_NEXT_INSTRUCTION ();
2311}
2312
2313
2314
2315000000,20.CODE,001101:SPECIAL:32::BREAK
82f728db 2316"break %#lx<CODE>"
c5d00cc7
CD		 2317*mipsI:
2318*mipsII:
2319*mipsIII:
2320*mipsIV:
603a98e7 2321*mipsV:
1e799e28 2322*mips32:
e70cb6cd 2323*mips32r2:
1e799e28 2324*mips64:
e70cb6cd 2325*mips64r2:
c906108c
SS		 2326*vr4100:
2327*vr5000:
2328*r3900:
2329{
8e394ffc 2330 do_break (SD_, instruction_0);
c906108c
SS		 2331}
2332
2333
2334
1e799e28
CD		 2335011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
2336"clo r<RD>, r<RS>"
2337*mips32:
e70cb6cd 2338*mips32r2:
1e799e28 2339*mips64:
e70cb6cd 2340*mips64r2:
4c54fc26 2341*vr5500:
1e799e28 2342{
1e799e28 2343 if (RT != RD)
c9b9995a 2344 Unpredictable ();
8e394ffc 2345 do_clo (SD_, RD, RS);
1e799e28
CD		 2346}
2347
2348
2349
2350011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
2351"clz r<RD>, r<RS>"
2352*mips32:
e70cb6cd 2353*mips32r2:
1e799e28 2354*mips64:
e70cb6cd 2355*mips64r2:
4c54fc26 2356*vr5500:
1e799e28 2357{
1e799e28 2358 if (RT != RD)
c9b9995a 2359 Unpredictable ();
8e394ffc 2360 do_clz (SD_, RD, RS);
1e799e28
CD		 2361}
2362
2363
2364
c906108c
SS		 2365000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
2366"dadd r<RD>, r<RS>, r<RT>"
2367*mipsIII:
2368*mipsIV:
603a98e7 2369*mipsV:
1e799e28 2370*mips64:
e70cb6cd 2371*mips64r2:
c906108c
SS		 2372*vr4100:
2373*vr5000:
2374{
ca971540 2375 check_u64 (SD_, instruction_0);
8e394ffc 2376 do_dadd (SD_, RD, RS, RT);
c906108c
SS		 2377}
2378
2379
2380
2381011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
2382"daddi r<RT>, r<RS>, <IMMEDIATE>"
2383*mipsIII:
2384*mipsIV:
603a98e7 2385*mipsV:
1e799e28 2386*mips64:
e70cb6cd 2387*mips64r2:
c906108c
SS		 2388*vr4100:
2389*vr5000:
2390{
ca971540 2391 check_u64 (SD_, instruction_0);
8e394ffc 2392 do_daddi (SD_, RT, RS, IMMEDIATE);
c906108c
SS		 2393}
2394
2395
2396
2397:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
2398{
2399 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2400 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
2401 TRACE_ALU_RESULT (GPR[rt]);
2402}
2403
2404011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
20ae0098 2405"daddiu r<RT>, r<RS>, <IMMEDIATE>"
c906108c
SS		 2406*mipsIII:
2407*mipsIV:
603a98e7 2408*mipsV:
1e799e28 2409*mips64:
e70cb6cd 2410*mips64r2:
c906108c
SS		 2411*vr4100:
2412*vr5000:
2413{
ca971540 2414 check_u64 (SD_, instruction_0);
c906108c
SS		 2415 do_daddiu (SD_, RS, RT, IMMEDIATE);
2416}
2417
2418
2419
2420:function:::void:do_daddu:int rs, int rt, int rd
2421{
2422 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2423 GPR[rd] = GPR[rs] + GPR[rt];
2424 TRACE_ALU_RESULT (GPR[rd]);
2425}
2426
2427000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
2428"daddu r<RD>, r<RS>, r<RT>"
2429*mipsIII:
2430*mipsIV:
603a98e7 2431*mipsV:
1e799e28 2432*mips64:
e70cb6cd 2433*mips64r2:
c906108c
SS		 2434*vr4100:
2435*vr5000:
2436{
ca971540 2437 check_u64 (SD_, instruction_0);
c906108c
SS		 2438 do_daddu (SD_, RS, RT, RD);
2439}
2440
2441
2442
1e799e28
CD		 2443011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
2444"dclo r<RD>, r<RS>"
2445*mips64:
e70cb6cd 2446*mips64r2:
4c54fc26 2447*vr5500:
1e799e28 2448{
1e799e28 2449 if (RT != RD)
c9b9995a 2450 Unpredictable ();
8e394ffc
AB		 2451 check_u64 (SD_, instruction_0);
2452 do_dclo (SD_, RD, RS);
1e799e28
CD		 2453}
2454
2455
2456
2457011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
2458"dclz r<RD>, r<RS>"
2459*mips64:
e70cb6cd 2460*mips64r2:
4c54fc26 2461*vr5500:
1e799e28 2462{
1e799e28 2463 if (RT != RD)
c9b9995a 2464 Unpredictable ();
8e394ffc
AB		 2465 check_u64 (SD_, instruction_0);
2466 do_dclz (SD_, RD, RS);
1e799e28
CD		 2467}
2468
2469
2470
c906108c
SS		 2471:function:::void:do_ddiv:int rs, int rt
2472{
2473 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
2474 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2475 {
2476 signed64 n = GPR[rs];
2477 signed64 d = GPR[rt];
2478 signed64 hi;
2479 signed64 lo;
2480 if (d == 0)
2481 {
2482 lo = SIGNED64 (0x8000000000000000);
2483 hi = 0;
2484 }
2485 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
2486 {
2487 lo = SIGNED64 (0x8000000000000000);
2488 hi = 0;
2489 }
2490 else
2491 {
2492 lo = (n / d);
2493 hi = (n % d);
2494 }
2495 HI = hi;
2496 LO = lo;
2497 }
2498 TRACE_ALU_RESULT2 (HI, LO);
2499}
2500
f701dad2 2501000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
c906108c
SS		 2502"ddiv r<RS>, r<RT>"
2503*mipsIII:
2504*mipsIV:
603a98e7 2505*mipsV:
1e799e28 2506*mips64:
e70cb6cd 2507*mips64r2:
c906108c
SS		 2508*vr4100:
2509*vr5000:
2510{
ca971540 2511 check_u64 (SD_, instruction_0);
c906108c
SS		 2512 do_ddiv (SD_, RS, RT);
2513}
2514
2515
2516
2517:function:::void:do_ddivu:int rs, int rt
2518{
2519 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
2520 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2521 {
2522 unsigned64 n = GPR[rs];
2523 unsigned64 d = GPR[rt];
2524 unsigned64 hi;
2525 unsigned64 lo;
2526 if (d == 0)
2527 {
2528 lo = SIGNED64 (0x8000000000000000);
2529 hi = 0;
2530 }
2531 else
2532 {
2533 lo = (n / d);
2534 hi = (n % d);
2535 }
2536 HI = hi;
2537 LO = lo;
2538 }
2539 TRACE_ALU_RESULT2 (HI, LO);
2540}
2541
2542000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
2543"ddivu r<RS>, r<RT>"
2544*mipsIII:
2545*mipsIV:
603a98e7 2546*mipsV:
1e799e28 2547*mips64:
e70cb6cd 2548*mips64r2:
c906108c
SS		 2549*vr4100:
2550*vr5000:
2551{
ca971540 2552 check_u64 (SD_, instruction_0);
c906108c
SS		 2553 do_ddivu (SD_, RS, RT);
2554}
2555
c906108c
SS		 2556:function:::void:do_div:int rs, int rt
2557{
2558 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
2559 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2560 {
2561 signed32 n = GPR[rs];
2562 signed32 d = GPR[rt];
2563 if (d == 0)
2564 {
2565 LO = EXTEND32 (0x80000000);
2566 HI = EXTEND32 (0);
2567 }
2568 else if (n == SIGNED32 (0x80000000) && d == -1)
2569 {
2570 LO = EXTEND32 (0x80000000);
2571 HI = EXTEND32 (0);
2572 }
2573 else
2574 {
2575 LO = EXTEND32 (n / d);
2576 HI = EXTEND32 (n % d);
2577 }
2578 }
2579 TRACE_ALU_RESULT2 (HI, LO);
2580}
2581
f701dad2 2582000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
c906108c 2583"div r<RS>, r<RT>"
c5d00cc7
CD		 2584*mipsI:
2585*mipsII:
2586*mipsIII:
2587*mipsIV:
603a98e7 2588*mipsV:
1e799e28 2589*mips32:
e70cb6cd 2590*mips32r2:
1e799e28 2591*mips64:
e70cb6cd 2592*mips64r2:
c906108c
SS		 2593*vr4100:
2594*vr5000:
2595*r3900:
2596{
2597 do_div (SD_, RS, RT);
2598}
2599
2600
2601
2602:function:::void:do_divu:int rs, int rt
2603{
2604 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
2605 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2606 {
2607 unsigned32 n = GPR[rs];
2608 unsigned32 d = GPR[rt];
2609 if (d == 0)
2610 {
2611 LO = EXTEND32 (0x80000000);
2612 HI = EXTEND32 (0);
2613 }
3e1dca16
CD		 2614 else
2615 {
2616 LO = EXTEND32 (n / d);
2617 HI = EXTEND32 (n % d);
2618 }
c906108c
SS		 2619 }
2620 TRACE_ALU_RESULT2 (HI, LO);
2621}
2622
f701dad2 2623000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
c906108c 2624"divu r<RS>, r<RT>"
c5d00cc7
CD		 2625*mipsI:
2626*mipsII:
2627*mipsIII:
2628*mipsIV:
603a98e7 2629*mipsV:
1e799e28 2630*mips32:
e70cb6cd 2631*mips32r2:
1e799e28 2632*mips64:
e70cb6cd 2633*mips64r2:
c906108c
SS		 2634*vr4100:
2635*vr5000:
2636*r3900:
2637{
2638 do_divu (SD_, RS, RT);
2639}
2640
2641
c906108c
SS		 2642:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
2643{
2644 unsigned64 lo;
2645 unsigned64 hi;
2646 unsigned64 m00;
2647 unsigned64 m01;
2648 unsigned64 m10;
2649 unsigned64 m11;
2650 unsigned64 mid;
2651 int sign;
2652 unsigned64 op1 = GPR[rs];
2653 unsigned64 op2 = GPR[rt];
2654 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2655 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4a0bd876 2656 /* make signed multiply unsigned */
c906108c
SS		 2657 sign = 0;
2658 if (signed_p)
2659 {
9a1d84fb 2660 if ((signed64) op1 < 0)
c906108c
SS		 2661 {
2662 op1 = - op1;
2663 ++sign;
2664 }
9a1d84fb 2665 if ((signed64) op2 < 0)
c906108c
SS		 2666 {
2667 op2 = - op2;
2668 ++sign;
2669 }
2670 }
67f5c7ef 2671 /* multiply out the 4 sub products */
c906108c
SS		 2672 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
2673 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
2674 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
2675 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
2676 /* add the products */
2677 mid = ((unsigned64) VH4_8 (m00)
2678 + (unsigned64) VL4_8 (m10)
2679 + (unsigned64) VL4_8 (m01));
2680 lo = U8_4 (mid, m00);
2681 hi = (m11
2682 + (unsigned64) VH4_8 (mid)
2683 + (unsigned64) VH4_8 (m01)
2684 + (unsigned64) VH4_8 (m10));
2685 /* fix the sign */
2686 if (sign & 1)
2687 {
2688 lo = -lo;
2689 if (lo == 0)
2690 hi = -hi;
2691 else
2692 hi = -hi - 1;
2693 }
2694 /* save the result HI/LO (and a gpr) */
2695 LO = lo;
2696 HI = hi;
2697 if (rd != 0)
2698 GPR[rd] = lo;
2699 TRACE_ALU_RESULT2 (HI, LO);
2700}
2701
2702:function:::void:do_dmult:int rs, int rt, int rd
2703{
2704 do_dmultx (SD_, rs, rt, rd, 1);
2705}
2706
f701dad2 2707000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
c906108c 2708"dmult r<RS>, r<RT>"
c5d00cc7
CD		 2709*mipsIII:
2710*mipsIV:
603a98e7 2711*mipsV:
1e799e28 2712*mips64:
e70cb6cd 2713*mips64r2:
c906108c
SS		 2714*vr4100:
2715{
ca971540 2716 check_u64 (SD_, instruction_0);
c906108c
SS		 2717 do_dmult (SD_, RS, RT, 0);
2718}
2719
f701dad2 2720000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
c906108c
SS		 2721"dmult r<RS>, r<RT>":RD == 0
2722"dmult r<RD>, r<RS>, r<RT>"
2723*vr5000:
2724{
ca971540 2725 check_u64 (SD_, instruction_0);
c906108c
SS		 2726 do_dmult (SD_, RS, RT, RD);
2727}
2728
2729
2730
2731:function:::void:do_dmultu:int rs, int rt, int rd
2732{
2733 do_dmultx (SD_, rs, rt, rd, 0);
2734}
2735
f701dad2 2736000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
c906108c 2737"dmultu r<RS>, r<RT>"
c5d00cc7
CD		 2738*mipsIII:
2739*mipsIV:
603a98e7 2740*mipsV:
1e799e28 2741*mips64:
e70cb6cd 2742*mips64r2:
c906108c
SS		 2743*vr4100:
2744{
ca971540 2745 check_u64 (SD_, instruction_0);
c906108c
SS		 2746 do_dmultu (SD_, RS, RT, 0);
2747}
2748
f701dad2 2749000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
c906108c
SS		 2750"dmultu r<RD>, r<RS>, r<RT>":RD == 0
2751"dmultu r<RS>, r<RT>"
2752*vr5000:
2753{
ca971540 2754 check_u64 (SD_, instruction_0);
c906108c
SS		 2755 do_dmultu (SD_, RS, RT, RD);
2756}
2757
e70cb6cd
CD		 2758
2759:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
2760{
2761 unsigned64 result;
2762
2763 y &= 63;
2764 TRACE_ALU_INPUT2 (x, y);
2765 result = ROTR64 (x, y);
2766 TRACE_ALU_RESULT (result);
2767 return result;
2768}
2769
2770000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
2771"dror r<RD>, r<RT>, <SHIFT>"
2772*mips64r2:
2773*vr5400:
2774*vr5500:
2775{
2776 check_u64 (SD_, instruction_0);
2777 GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
2778}
2779
2780000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
2781"dror32 r<RD>, r<RT>, <SHIFT>"
2782*mips64r2:
2783*vr5400:
2784*vr5500:
2785{
2786 check_u64 (SD_, instruction_0);
2787 GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
2788}
2789
2790000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
2791"drorv r<RD>, r<RT>, r<RS>"
2792*mips64r2:
2793*vr5400:
2794*vr5500:
2795{
2796 check_u64 (SD_, instruction_0);
2797 GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
2798}
2799
2800
c906108c
SS		 2801:function:::void:do_dsll:int rt, int rd, int shift
2802{
fff8d27d 2803 TRACE_ALU_INPUT2 (GPR[rt], shift);
c906108c 2804 GPR[rd] = GPR[rt] << shift;
fff8d27d 2805 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 2806}
2807
f701dad2 2808000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
c906108c
SS		 2809"dsll r<RD>, r<RT>, <SHIFT>"
2810*mipsIII:
2811*mipsIV:
603a98e7 2812*mipsV:
1e799e28 2813*mips64:
e70cb6cd 2814*mips64r2:
c906108c
SS		 2815*vr4100:
2816*vr5000:
2817{
ca971540 2818 check_u64 (SD_, instruction_0);
c906108c
SS		 2819 do_dsll (SD_, RT, RD, SHIFT);
2820}
2821
2822
f701dad2 2823000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
c906108c
SS		 2824"dsll32 r<RD>, r<RT>, <SHIFT>"
2825*mipsIII:
2826*mipsIV:
603a98e7 2827*mipsV:
1e799e28 2828*mips64:
e70cb6cd 2829*mips64r2:
c906108c
SS		 2830*vr4100:
2831*vr5000:
2832{
ca971540 2833 check_u64 (SD_, instruction_0);
8e394ffc 2834 do_dsll32 (SD_, RD, RT, SHIFT);
c906108c
SS		 2835}
2836
3e1dca16
CD		 2837:function:::void:do_dsllv:int rs, int rt, int rd
2838{
2839 int s = MASKED64 (GPR[rs], 5, 0);
2840 TRACE_ALU_INPUT2 (GPR[rt], s);
2841 GPR[rd] = GPR[rt] << s;
2842 TRACE_ALU_RESULT (GPR[rd]);
2843}
2844
f701dad2 2845000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
c906108c
SS		 2846"dsllv r<RD>, r<RT>, r<RS>"
2847*mipsIII:
2848*mipsIV:
603a98e7 2849*mipsV:
1e799e28 2850*mips64:
e70cb6cd 2851*mips64r2:
c906108c
SS		 2852*vr4100:
2853*vr5000:
2854{
ca971540 2855 check_u64 (SD_, instruction_0);
c906108c
SS		 2856 do_dsllv (SD_, RS, RT, RD);
2857}
2858
2859:function:::void:do_dsra:int rt, int rd, int shift
2860{
fff8d27d 2861 TRACE_ALU_INPUT2 (GPR[rt], shift);
c906108c 2862 GPR[rd] = ((signed64) GPR[rt]) >> shift;
fff8d27d 2863 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 2864}
2865
2866
f701dad2 2867000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
c906108c
SS		 2868"dsra r<RD>, r<RT>, <SHIFT>"
2869*mipsIII:
2870*mipsIV:
603a98e7 2871*mipsV:
1e799e28 2872*mips64:
e70cb6cd 2873*mips64r2:
c906108c
SS		 2874*vr4100:
2875*vr5000:
2876{
ca971540 2877 check_u64 (SD_, instruction_0);
c906108c
SS		 2878 do_dsra (SD_, RT, RD, SHIFT);
2879}
2880
2881
f701dad2 2882000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
bb22bd7d 2883"dsra32 r<RD>, r<RT>, <SHIFT>"
c906108c
SS		 2884*mipsIII:
2885*mipsIV:
603a98e7 2886*mipsV:
1e799e28 2887*mips64:
e70cb6cd 2888*mips64r2:
c906108c
SS		 2889*vr4100:
2890*vr5000:
2891{
ca971540 2892 check_u64 (SD_, instruction_0);
8e394ffc 2893 do_dsra32 (SD_, RD, RT, SHIFT);
c906108c
SS		 2894}
2895
2896
2897:function:::void:do_dsrav:int rs, int rt, int rd
2898{
2899 int s = MASKED64 (GPR[rs], 5, 0);
2900 TRACE_ALU_INPUT2 (GPR[rt], s);
2901 GPR[rd] = ((signed64) GPR[rt]) >> s;
2902 TRACE_ALU_RESULT (GPR[rd]);
2903}
2904
f701dad2 2905000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
bb22bd7d 2906"dsrav r<RD>, r<RT>, r<RS>"
c906108c
SS		 2907*mipsIII:
2908*mipsIV:
603a98e7 2909*mipsV:
1e799e28 2910*mips64:
e70cb6cd 2911*mips64r2:
c906108c
SS		 2912*vr4100:
2913*vr5000:
2914{
ca971540 2915 check_u64 (SD_, instruction_0);
c906108c
SS		 2916 do_dsrav (SD_, RS, RT, RD);
2917}
2918
2919:function:::void:do_dsrl:int rt, int rd, int shift
2920{
fff8d27d 2921 TRACE_ALU_INPUT2 (GPR[rt], shift);
c906108c 2922 GPR[rd] = (unsigned64) GPR[rt] >> shift;
fff8d27d 2923 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 2924}
2925
2926
f701dad2 2927000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
c906108c
SS		 2928"dsrl r<RD>, r<RT>, <SHIFT>"
2929*mipsIII:
2930*mipsIV:
603a98e7 2931*mipsV:
1e799e28 2932*mips64:
e70cb6cd 2933*mips64r2:
c906108c
SS		 2934*vr4100:
2935*vr5000:
2936{
ca971540 2937 check_u64 (SD_, instruction_0);
c906108c
SS		 2938 do_dsrl (SD_, RT, RD, SHIFT);
2939}
2940
2941
f701dad2 2942000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
c906108c
SS		 2943"dsrl32 r<RD>, r<RT>, <SHIFT>"
2944*mipsIII:
2945*mipsIV:
603a98e7 2946*mipsV:
1e799e28 2947*mips64:
e70cb6cd 2948*mips64r2:
c906108c
SS		 2949*vr4100:
2950*vr5000:
2951{
ca971540 2952 check_u64 (SD_, instruction_0);
8e394ffc 2953 do_dsrl32 (SD_, RD, RT, SHIFT);
c906108c
SS		 2954}
2955
2956
2957:function:::void:do_dsrlv:int rs, int rt, int rd
2958{
2959 int s = MASKED64 (GPR[rs], 5, 0);
fff8d27d 2960 TRACE_ALU_INPUT2 (GPR[rt], s);
c906108c 2961 GPR[rd] = (unsigned64) GPR[rt] >> s;
fff8d27d 2962 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 2963}
2964
2965
2966
f701dad2 2967000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
20ae0098 2968"dsrlv r<RD>, r<RT>, r<RS>"
c906108c
SS		 2969*mipsIII:
2970*mipsIV:
603a98e7 2971*mipsV:
1e799e28 2972*mips64:
e70cb6cd 2973*mips64r2:
c906108c
SS		 2974*vr4100:
2975*vr5000:
2976{
ca971540 2977 check_u64 (SD_, instruction_0);
c906108c
SS		 2978 do_dsrlv (SD_, RS, RT, RD);
2979}
2980
2981
f701dad2 2982000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
c906108c
SS		 2983"dsub r<RD>, r<RS>, r<RT>"
2984*mipsIII:
2985*mipsIV:
603a98e7 2986*mipsV:
1e799e28 2987*mips64:
e70cb6cd 2988*mips64r2:
c906108c
SS		 2989*vr4100:
2990*vr5000:
2991{
ca971540 2992 check_u64 (SD_, instruction_0);
8e394ffc 2993 do_dsub (SD_, RD, RS, RT);
c906108c
SS		 2994}
2995
2996
2997:function:::void:do_dsubu:int rs, int rt, int rd
2998{
2999 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3000 GPR[rd] = GPR[rs] - GPR[rt];
3001 TRACE_ALU_RESULT (GPR[rd]);
3002}
3003
f701dad2 3004000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
c906108c
SS		 3005"dsubu r<RD>, r<RS>, r<RT>"
3006*mipsIII:
3007*mipsIV:
603a98e7 3008*mipsV:
1e799e28 3009*mips64:
e70cb6cd 3010*mips64r2:
c906108c
SS		 3011*vr4100:
3012*vr5000:
3013{
ca971540 3014 check_u64 (SD_, instruction_0);
c906108c
SS		 3015 do_dsubu (SD_, RS, RT, RD);
3016}
3017
3018
3019000010,26.INSTR_INDEX:NORMAL:32::J
3020"j <INSTR_INDEX>"
c5d00cc7
CD		 3021*mipsI:
3022*mipsII:
3023*mipsIII:
3024*mipsIV:
603a98e7 3025*mipsV:
1e799e28 3026*mips32:
e70cb6cd 3027*mips32r2:
1e799e28 3028*mips64:
e70cb6cd 3029*mips64r2:
c906108c
SS		 3030*vr4100:
3031*vr5000:
3032*r3900:
3033{
3034 /* NOTE: The region used is that of the delay slot NIA and NOT the
3035 current instruction */
3036 address_word region = (NIA & MASK (63, 28));
3037 DELAY_SLOT (region | (INSTR_INDEX << 2));
3038}
3039
3040
3041000011,26.INSTR_INDEX:NORMAL:32::JAL
3042"jal <INSTR_INDEX>"
c5d00cc7
CD		 3043*mipsI:
3044*mipsII:
3045*mipsIII:
3046*mipsIV:
603a98e7 3047*mipsV:
1e799e28 3048*mips32:
e70cb6cd 3049*mips32r2:
1e799e28 3050*mips64:
e70cb6cd 3051*mips64r2:
c906108c
SS		 3052*vr4100:
3053*vr5000:
3054*r3900:
3055{
3056 /* NOTE: The region used is that of the delay slot and NOT the
3057 current instruction */
3058 address_word region = (NIA & MASK (63, 28));
3059 GPR[31] = CIA + 8;
3060 DELAY_SLOT (region | (INSTR_INDEX << 2));
3061}
3062
f701dad2 3063000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
c906108c
SS		 3064"jalr r<RS>":RD == 31
3065"jalr r<RD>, r<RS>"
c5d00cc7
CD		 3066*mipsI:
3067*mipsII:
3068*mipsIII:
3069*mipsIV:
603a98e7 3070*mipsV:
1e799e28 3071*mips32:
e70cb6cd 3072*mips32r2:
1e799e28 3073*mips64:
e70cb6cd 3074*mips64r2:
c906108c
SS		 3075*vr4100:
3076*vr5000:
3077*r3900:
3078{
3079 address_word temp = GPR[RS];
3080 GPR[RD] = CIA + 8;
3081 DELAY_SLOT (temp);
3082}
3083
b1004875
TS		 3084000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB
3085"jalr.hb r<RS>":RD == 31
3086"jalr.hb r<RD>, r<RS>"
3087*mips32r2:
3088*mips64r2:
3089{
3090 address_word temp = GPR[RS];
3091 GPR[RD] = CIA + 8;
3092 DELAY_SLOT (temp);
3093}
c906108c 3094
b1004875 3095000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR
c906108c 3096"jr r<RS>"
c5d00cc7
CD		 3097*mipsI:
3098*mipsII:
3099*mipsIII:
3100*mipsIV:
603a98e7 3101*mipsV:
1e799e28 3102*mips32:
e70cb6cd 3103*mips32r2:
1e799e28 3104*mips64:
e70cb6cd 3105*mips64r2:
c906108c
SS		 3106*vr4100:
3107*vr5000:
3108*r3900:
3109{
3110 DELAY_SLOT (GPR[RS]);
3111}
3112
b1004875
TS		 3113000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB
3114"jr.hb r<RS>"
3115*mips32r2:
3116*mips64r2:
3117{
3118 DELAY_SLOT (GPR[RS]);
3119}
c906108c
SS		 3120
3121:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
3122{
3123 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3124 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
3125 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
3126 unsigned int byte;
3127 address_word paddr;
c906108c
SS		 3128 unsigned64 memval;
3129 address_word vaddr;
3130
26f8bf63 3131 paddr = vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 3132 if ((vaddr & access) != 0)
3133 {
3134 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
3135 }
c906108c 3136 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
26f8bf63 3137 LoadMemory (&memval, NULL, access, paddr, vaddr, isDATA, isREAL);
c906108c
SS		 3138 byte = ((vaddr & mask) ^ bigendiancpu);
3139 return (memval >> (8 * byte));
3140}
3141
1c47a468
CD		 3142:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3143{
3144 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3145 address_word reverseendian = (ReverseEndian ? -1 : 0);
3146 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3147 unsigned int byte;
3148 unsigned int word;
3149 address_word paddr;
1c47a468
CD		 3150 unsigned64 memval;
3151 address_word vaddr;
3152 int nr_lhs_bits;
3153 int nr_rhs_bits;
3154 unsigned_word lhs_mask;
3155 unsigned_word temp;
3156
26f8bf63 3157 paddr = vaddr = loadstore_ea (SD_, base, offset);
1c47a468
CD		 3158 paddr = (paddr ^ (reverseendian & mask));
3159 if (BigEndianMem == 0)
3160 paddr = paddr & ~access;
3161
3162 /* compute where within the word/mem we are */
3163 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3164 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3165 nr_lhs_bits = 8 * byte + 8;
3166 nr_rhs_bits = 8 * access - 8 * byte;
3167 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3168
3169 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3170 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3171 (long) ((unsigned64) paddr >> 32), (long) paddr,
3172 word, byte, nr_lhs_bits, nr_rhs_bits); */
3173
26f8bf63 3174 LoadMemory (&memval, NULL, byte, paddr, vaddr, isDATA, isREAL);
1c47a468
CD		 3175 if (word == 0)
3176 {
3177 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
3178 temp = (memval << nr_rhs_bits);
3179 }
3180 else
3181 {
3182 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
3183 temp = (memval >> nr_lhs_bits);
3184 }
3185 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
3186 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
3187
3188 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
3189 (long) ((unsigned64) memval >> 32), (long) memval,
3190 (long) ((unsigned64) temp >> 32), (long) temp,
3191 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
3192 (long) (rt >> 32), (long) rt); */
3193 return rt;
3194}
3195
3196:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3197{
3198 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3199 address_word reverseendian = (ReverseEndian ? -1 : 0);
3200 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3201 unsigned int byte;
3202 address_word paddr;
1c47a468
CD		 3203 unsigned64 memval;
3204 address_word vaddr;
3205
26f8bf63 3206 paddr = vaddr = loadstore_ea (SD_, base, offset);
1c47a468
CD		 3207 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
3208 paddr = (paddr ^ (reverseendian & mask));
3209 if (BigEndianMem != 0)
3210 paddr = paddr & ~access;
3211 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3212 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
26f8bf63 3213 LoadMemory (&memval, NULL, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1c47a468
CD		 3214 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
3215 (long) paddr, byte, (long) paddr, (long) memval); */
3216 {
3217 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
3218 rt &= ~screen;
3219 rt |= (memval >> (8 * byte)) & screen;
3220 }
3221 return rt;
3222}
3223
c906108c
SS		 3224
3225100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
3226"lb r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3227*mipsI:
3228*mipsII:
3229*mipsIII:
3230*mipsIV:
603a98e7 3231*mipsV:
1e799e28 3232*mips32:
e70cb6cd 3233*mips32r2:
1e799e28 3234*mips64:
e70cb6cd 3235*mips64r2:
c906108c
SS		 3236*vr4100:
3237*vr5000:
3238*r3900:
3239{
8e394ffc 3240 do_lb (SD_,RT,OFFSET,BASE);
c906108c
SS		 3241}
3242
3243
3244100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
3245"lbu r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3246*mipsI:
3247*mipsII:
3248*mipsIII:
3249*mipsIV:
603a98e7 3250*mipsV:
1e799e28 3251*mips32:
e70cb6cd 3252*mips32r2:
1e799e28 3253*mips64:
e70cb6cd 3254*mips64r2:
c906108c
SS		 3255*vr4100:
3256*vr5000:
3257*r3900:
3258{
8e394ffc 3259 do_lbu (SD_, RT,OFFSET,BASE);
c906108c
SS		 3260}
3261
3262
3263110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
3264"ld r<RT>, <OFFSET>(r<BASE>)"
3265*mipsIII:
3266*mipsIV:
603a98e7 3267*mipsV:
1e799e28 3268*mips64:
e70cb6cd 3269*mips64r2:
c906108c
SS		 3270*vr4100:
3271*vr5000:
3272{
ca971540 3273 check_u64 (SD_, instruction_0);
c906108c
SS		 3274 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
3275}
3276
3277
32781101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
3279"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3280*mipsII:
3281*mipsIII:
3282*mipsIV:
603a98e7 3283*mipsV:
1e799e28 3284*mips32:
e70cb6cd 3285*mips32r2:
1e799e28 3286*mips64:
e70cb6cd 3287*mips64r2:
c906108c
SS		 3288*vr4100:
3289*vr5000:
3290*r3900:
3291{
8e394ffc 3292 do_ldc (SD_, ZZ, RT, OFFSET, BASE);
c906108c
SS		 3293}
3294
3295
3296
3297
3298011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
3299"ldl r<RT>, <OFFSET>(r<BASE>)"
3300*mipsIII:
3301*mipsIV:
603a98e7 3302*mipsV:
1e799e28 3303*mips64:
e70cb6cd 3304*mips64r2:
c906108c
SS		 3305*vr4100:
3306*vr5000:
3307{
ca971540 3308 check_u64 (SD_, instruction_0);
c906108c
SS		 3309 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3310}
3311
3312
3313011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
3314"ldr r<RT>, <OFFSET>(r<BASE>)"
3315*mipsIII:
3316*mipsIV:
603a98e7 3317*mipsV:
1e799e28 3318*mips64:
e70cb6cd 3319*mips64r2:
c906108c
SS		 3320*vr4100:
3321*vr5000:
3322{
ca971540 3323 check_u64 (SD_, instruction_0);
c906108c
SS		 3324 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3325}
3326
3327
3328100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
3329"lh r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3330*mipsI:
3331*mipsII:
3332*mipsIII:
3333*mipsIV:
603a98e7 3334*mipsV:
1e799e28 3335*mips32:
e70cb6cd 3336*mips32r2:
1e799e28 3337*mips64:
e70cb6cd 3338*mips64r2:
c906108c
SS		 3339*vr4100:
3340*vr5000:
3341*r3900:
3342{
8e394ffc 3343 do_lh (SD_,RT,OFFSET,BASE);
c906108c
SS		 3344}
3345
3346
3347100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
3348"lhu r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3349*mipsI:
3350*mipsII:
3351*mipsIII:
3352*mipsIV:
603a98e7 3353*mipsV:
1e799e28 3354*mips32:
e70cb6cd 3355*mips32r2:
1e799e28 3356*mips64:
e70cb6cd 3357*mips64r2:
c906108c
SS		 3358*vr4100:
3359*vr5000:
3360*r3900:
3361{
8e394ffc 3362 do_lhu (SD_,RT,OFFSET,BASE);
c906108c
SS		 3363}
3364
3365
3366110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
3367"ll r<RT>, <OFFSET>(r<BASE>)"
3368*mipsII:
3369*mipsIII:
3370*mipsIV:
603a98e7 3371*mipsV:
1e799e28 3372*mips32:
e70cb6cd 3373*mips32r2:
1e799e28 3374*mips64:
e70cb6cd 3375*mips64r2:
c906108c
SS		 3376*vr4100:
3377*vr5000:
3378{
8e394ffc 3379 do_ll (SD_, RT, OFFSET, BASE);
c906108c
SS		 3380}
3381
3382
3383110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
3384"lld r<RT>, <OFFSET>(r<BASE>)"
3385*mipsIII:
3386*mipsIV:
603a98e7 3387*mipsV:
1e799e28 3388*mips64:
e70cb6cd 3389*mips64r2:
c906108c
SS		 3390*vr4100:
3391*vr5000:
3392{
ca971540 3393 check_u64 (SD_, instruction_0);
8e394ffc 3394 do_lld (SD_, RT, OFFSET, BASE);
c906108c
SS		 3395}
3396
3397
3398001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
82f728db 3399"lui r<RT>, %#lx<IMMEDIATE>"
c5d00cc7
CD		 3400*mipsI:
3401*mipsII:
3402*mipsIII:
3403*mipsIV:
603a98e7 3404*mipsV:
1e799e28 3405*mips32:
e70cb6cd 3406*mips32r2:
1e799e28 3407*mips64:
e70cb6cd 3408*mips64r2:
c906108c
SS		 3409*vr4100:
3410*vr5000:
3411*r3900:
3412{
8e394ffc 3413 do_lui (SD_, RT, IMMEDIATE);
c906108c
SS		 3414}
3415
3416
3417100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
3418"lw r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3419*mipsI:
3420*mipsII:
3421*mipsIII:
3422*mipsIV:
603a98e7 3423*mipsV:
1e799e28 3424*mips32:
e70cb6cd 3425*mips32r2:
1e799e28 3426*mips64:
e70cb6cd 3427*mips64r2:
c906108c
SS		 3428*vr4100:
3429*vr5000:
3430*r3900:
3431{
8e394ffc 3432 do_lw (SD_,RT,OFFSET,BASE);
c906108c
SS		 3433}
3434
3435
34361100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
3437"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3438*mipsI:
3439*mipsII:
3440*mipsIII:
3441*mipsIV:
603a98e7 3442*mipsV:
1e799e28 3443*mips32:
e70cb6cd 3444*mips32r2:
1e799e28 3445*mips64:
e70cb6cd 3446*mips64r2:
c906108c
SS		 3447*vr4100:
3448*vr5000:
3449*r3900:
3450{
8e394ffc 3451 do_lwc (SD_, ZZ, RT, OFFSET, BASE);
c906108c
SS		 3452}
3453
3454
c906108c
SS		 3455100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
3456"lwl r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3457*mipsI:
3458*mipsII:
3459*mipsIII:
3460*mipsIV:
603a98e7 3461*mipsV:
1e799e28 3462*mips32:
e70cb6cd 3463*mips32r2:
1e799e28 3464*mips64:
e70cb6cd 3465*mips64r2:
c906108c
SS		 3466*vr4100:
3467*vr5000:
3468*r3900:
3469{
8e394ffc 3470 do_lwl (SD_, RT, OFFSET, BASE);
c906108c
SS		 3471}
3472
3473
c906108c
SS		 3474100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
3475"lwr r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3476*mipsI:
3477*mipsII:
3478*mipsIII:
3479*mipsIV:
603a98e7 3480*mipsV:
1e799e28 3481*mips32:
e70cb6cd 3482*mips32r2:
1e799e28 3483*mips64:
e70cb6cd 3484*mips64r2:
c906108c
SS		 3485*vr4100:
3486*vr5000:
3487*r3900:
3488{
8e394ffc 3489 do_lwr (SD_, RT, OFFSET, BASE);
c906108c
SS		 3490}
3491
3492
bb22bd7d 3493100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
c906108c
SS		 3494"lwu r<RT>, <OFFSET>(r<BASE>)"
3495*mipsIII:
3496*mipsIV:
603a98e7 3497*mipsV:
1e799e28 3498*mips64:
e70cb6cd 3499*mips64r2:
c906108c
SS		 3500*vr4100:
3501*vr5000:
3502{
8e394ffc 3503 do_lwu (SD_, RT, OFFSET, BASE, instruction_0);
c906108c
SS		 3504}
3505
3506
1e799e28
CD		 3507
3508011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
3509"madd r<RS>, r<RT>"
3510*mips32:
3511*mips64:
4c54fc26 3512*vr5500:
1e799e28 3513{
8e394ffc 3514 do_madd (SD_, RS, RT);
1e799e28
CD		 3515}
3516
3517
8b082fb1
TS		 3518011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD
3519"madd r<RS>, r<RT>":AC == 0
3520"madd ac<AC>, r<RS>, r<RT>"
3521*mips32r2:
3522*mips64r2:
3523*dsp2:
3524{
8e394ffc 3525 do_dsp_madd (SD_, AC, RS, RT);
8b082fb1
TS		 3526}
3527
1e799e28
CD		 3528
3529011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
3530"maddu r<RS>, r<RT>"
3531*mips32:
3532*mips64:
4c54fc26 3533*vr5500:
1e799e28 3534{
8e394ffc 3535 do_maddu (SD_, RS, RT);
1e799e28
CD		 3536}
3537
3538
8b082fb1
TS		 3539011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU
3540"maddu r<RS>, r<RT>":AC == 0
3541"maddu ac<AC>, r<RS>, r<RT>"
3542*mips32r2:
3543*mips64r2:
3544*dsp2:
3545{
8e394ffc 3546 do_dsp_maddu (SD_, AC, RS, RT);
8b082fb1
TS		 3547}
3548
3549
c906108c
SS		 3550:function:::void:do_mfhi:int rd
3551{
3552 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
3553 TRACE_ALU_INPUT1 (HI);
3554 GPR[rd] = HI;
3555 TRACE_ALU_RESULT (GPR[rd]);
3556}
3557
3558000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
3559"mfhi r<RD>"
c5d00cc7
CD		 3560*mipsI:
3561*mipsII:
3562*mipsIII:
3563*mipsIV:
603a98e7 3564*mipsV:
c906108c
SS		 3565*vr4100:
3566*vr5000:
3567*r3900:
53f4826b
TS		 3568*mips32:
3569*mips64:
c906108c
SS		 3570{
3571 do_mfhi (SD_, RD);
3572}
3573
3574
8b082fb1
TS		 3575000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI
3576"mfhi r<RD>":AC == 0
3577"mfhi r<RD>, ac<AC>"
3578*mips32r2:
3579*mips64r2:
3580*dsp:
3581{
8e394ffc 3582 do_dsp_mfhi (SD_, AC, RD);
8b082fb1
TS		 3583}
3584
c906108c
SS		 3585
3586:function:::void:do_mflo:int rd
3587{
3588 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
3589 TRACE_ALU_INPUT1 (LO);
3590 GPR[rd] = LO;
3591 TRACE_ALU_RESULT (GPR[rd]);
3592}
3593
3594000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
3595"mflo r<RD>"
c5d00cc7
CD		 3596*mipsI:
3597*mipsII:
3598*mipsIII:
3599*mipsIV:
603a98e7 3600*mipsV:
c906108c
SS		 3601*vr4100:
3602*vr5000:
3603*r3900:
53f4826b
TS		 3604*mips32:
3605*mips64:
c906108c
SS		 3606{
3607 do_mflo (SD_, RD);
3608}
3609
3610
8b082fb1
TS		 3611000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO
3612"mflo r<RD>":AC == 0
3613"mflo r<RD>, ac<AC>"
3614*mips32r2:
3615*mips64r2:
3616*dsp:
3617{
8e394ffc 3618 do_dsp_mflo (SD_, AC, RD);
8b082fb1
TS		 3619}
3620
c906108c 3621
f701dad2 3622000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
c906108c
SS		 3623"movn r<RD>, r<RS>, r<RT>"
3624*mipsIV:
603a98e7 3625*mipsV:
1e799e28 3626*mips32:
e70cb6cd 3627*mips32r2:
1e799e28 3628*mips64:
e70cb6cd 3629*mips64r2:
c906108c
SS		 3630*vr5000:
3631{
8e394ffc 3632 do_movn (SD_, RD, RS, RT);
c906108c
SS		 3633}
3634
3635
3636
f701dad2 3637000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
c906108c
SS		 3638"movz r<RD>, r<RS>, r<RT>"
3639*mipsIV:
603a98e7 3640*mipsV:
1e799e28 3641*mips32:
e70cb6cd 3642*mips32r2:
1e799e28 3643*mips64:
e70cb6cd 3644*mips64r2:
c906108c
SS		 3645*vr5000:
3646{
8e394ffc 3647 do_movz (SD_, RD, RS, RT);
c906108c
SS		 3648}
3649
3650
3651
1e799e28
CD		 3652011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
3653"msub r<RS>, r<RT>"
3654*mips32:
3655*mips64:
4c54fc26 3656*vr5500:
1e799e28 3657{
8e394ffc 3658 do_msub (SD_, RS, RT);
1e799e28
CD		 3659}
3660
3661
8b082fb1
TS		 3662011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB
3663"msub r<RS>, r<RT>":AC == 0
3664"msub ac<AC>, r<RS>, r<RT>"
3665*mips32r2:
3666*mips64r2:
3667*dsp2:
3668{
8e394ffc 3669 do_dsp_msub (SD_, AC, RS, RT);
8b082fb1
TS		 3670}
3671
1e799e28
CD		 3672
3673011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
3674"msubu r<RS>, r<RT>"
3675*mips32:
3676*mips64:
4c54fc26 3677*vr5500:
1e799e28 3678{
8e394ffc 3679 do_msubu (SD_, RS, RT);
1e799e28
CD		 3680}
3681
3682
8b082fb1
TS		 3683011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU
3684"msubu r<RS>, r<RT>":AC == 0
3685"msubu ac<AC>, r<RS>, r<RT>"
3686*mips32r2:
3687*mips64r2:
3688*dsp2:
3689{
8e394ffc 3690 do_dsp_msubu (SD_, AC, RS, RT);
8b082fb1
TS		 3691}
3692
1e799e28 3693
c906108c
SS		 3694000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
3695"mthi r<RS>"
c5d00cc7
CD		 3696*mipsI:
3697*mipsII:
3698*mipsIII:
3699*mipsIV:
603a98e7 3700*mipsV:
c906108c
SS		 3701*vr4100:
3702*vr5000:
3703*r3900:
53f4826b
TS		 3704*mips32:
3705*mips64:
c906108c 3706{
8e394ffc 3707 do_mthi (SD_, RS);
c906108c
SS		 3708}
3709
3710
8b082fb1
TS		 3711000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI
3712"mthi r<RS>":AC == 0
3713"mthi r<RS>, ac<AC>"
3714*mips32r2:
3715*mips64r2:
3716*dsp:
3717{
8e394ffc 3718 do_dsp_mthi (SD_, AC, RS);
8b082fb1
TS		 3719}
3720
c906108c 3721
f701dad2 3722000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
c906108c 3723"mtlo r<RS>"
c5d00cc7
CD		 3724*mipsI:
3725*mipsII:
3726*mipsIII:
3727*mipsIV:
603a98e7 3728*mipsV:
c906108c
SS		 3729*vr4100:
3730*vr5000:
3731*r3900:
53f4826b
TS		 3732*mips32:
3733*mips64:
c906108c 3734{
8e394ffc 3735 do_mtlo (SD_, RS);
c906108c
SS		 3736}
3737
3738
8b082fb1
TS		 3739000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO
3740"mtlo r<RS>":AC == 0
3741"mtlo r<RS>, ac<AC>"
3742*mips32r2:
3743*mips64r2:
3744*dsp:
3745{
8e394ffc 3746 do_dsp_mtlo (SD_, AC, RS);
8b082fb1
TS		 3747}
3748
c906108c 3749
1e799e28
CD		 3750011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
3751"mul r<RD>, r<RS>, r<RT>"
3752*mips32:
e70cb6cd 3753*mips32r2:
1e799e28 3754*mips64:
e70cb6cd 3755*mips64r2:
4c54fc26 3756*vr5500:
1e799e28 3757{
8e394ffc 3758 do_mul (SD_, RD, RS, RT);
1e799e28
CD		 3759}
3760
3761
3762
c906108c
SS		 3763:function:::void:do_mult:int rs, int rt, int rd
3764{
3765 signed64 prod;
3766 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
402586aa
CD		 3767 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3768 Unpredictable ();
c906108c
SS		 3769 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3770 prod = (((signed64)(signed32) GPR[rs])
3771 * ((signed64)(signed32) GPR[rt]));
3772 LO = EXTEND32 (VL4_8 (prod));
3773 HI = EXTEND32 (VH4_8 (prod));
2d2733fc 3774 ACX = 0; /* SmartMIPS */
c906108c
SS		 3775 if (rd != 0)
3776 GPR[rd] = LO;
3777 TRACE_ALU_RESULT2 (HI, LO);
3778}
3779
f701dad2 3780000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
c906108c 3781"mult r<RS>, r<RT>"
c5d00cc7
CD		 3782*mipsI:
3783*mipsII:
3784*mipsIII:
3785*mipsIV:
603a98e7 3786*mipsV:
1e799e28
CD		 3787*mips32:
3788*mips64:
c906108c
SS		 3789*vr4100:
3790{
3791 do_mult (SD_, RS, RT, 0);
3792}
3793
3794
8b082fb1
TS		 3795000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT
3796"mult r<RS>, r<RT>":AC == 0
3797"mult ac<AC>, r<RS>, r<RT>"
3798*mips32r2:
3799*mips64r2:
3800*dsp2:
3801{
8e394ffc 3802 do_dsp_mult (SD_, AC, RS, RT);
8b082fb1
TS		 3803}
3804
3805
f701dad2 3806000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
9846de1b 3807"mult r<RS>, r<RT>":RD == 0
c906108c
SS		 3808"mult r<RD>, r<RS>, r<RT>"
3809*vr5000:
3810*r3900:
3811{
3812 do_mult (SD_, RS, RT, RD);
3813}
3814
3815
3816:function:::void:do_multu:int rs, int rt, int rd
3817{
3818 unsigned64 prod;
3819 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
402586aa
CD		 3820 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3821 Unpredictable ();
c906108c
SS		 3822 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3823 prod = (((unsigned64)(unsigned32) GPR[rs])
3824 * ((unsigned64)(unsigned32) GPR[rt]));
3825 LO = EXTEND32 (VL4_8 (prod));
3826 HI = EXTEND32 (VH4_8 (prod));
3827 if (rd != 0)
3828 GPR[rd] = LO;
3829 TRACE_ALU_RESULT2 (HI, LO);
3830}
3831
f701dad2 3832000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
c906108c 3833"multu r<RS>, r<RT>"
c5d00cc7
CD		 3834*mipsI:
3835*mipsII:
3836*mipsIII:
3837*mipsIV:
603a98e7 3838*mipsV:
1e799e28
CD		 3839*mips32:
3840*mips64:
c906108c
SS		 3841*vr4100:
3842{
cff3e48b 3843 do_multu (SD_, RS, RT, 0);
c906108c
SS		 3844}
3845
8b082fb1
TS		 3846
3847000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU
3848"multu r<RS>, r<RT>":AC == 0
3849"multu r<RS>, r<RT>"
3850*mips32r2:
3851*mips64r2:
3852*dsp2:
3853{
8e394ffc 3854 do_dsp_multu (SD_, AC, RS, RT);
8b082fb1
TS		 3855}
3856
3857
f701dad2 3858000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
9846de1b 3859"multu r<RS>, r<RT>":RD == 0
c906108c
SS		 3860"multu r<RD>, r<RS>, r<RT>"
3861*vr5000:
3862*r3900:
3863{
cff3e48b 3864 do_multu (SD_, RS, RT, RD);
c906108c
SS		 3865}
3866
3867
3868:function:::void:do_nor:int rs, int rt, int rd
3869{
3870 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3871 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
3872 TRACE_ALU_RESULT (GPR[rd]);
3873}
3874
3875000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
3876"nor r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 3877*mipsI:
3878*mipsII:
3879*mipsIII:
3880*mipsIV:
603a98e7 3881*mipsV:
1e799e28 3882*mips32:
e70cb6cd 3883*mips32r2:
1e799e28 3884*mips64:
e70cb6cd 3885*mips64r2:
c906108c
SS		 3886*vr4100:
3887*vr5000:
3888*r3900:
3889{
3890 do_nor (SD_, RS, RT, RD);
3891}
3892
3893
3894:function:::void:do_or:int rs, int rt, int rd
3895{
3896 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3897 GPR[rd] = (GPR[rs] | GPR[rt]);
3898 TRACE_ALU_RESULT (GPR[rd]);
3899}
3900
3901000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
3902"or r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 3903*mipsI:
3904*mipsII:
3905*mipsIII:
3906*mipsIV:
603a98e7 3907*mipsV:
1e799e28 3908*mips32:
e70cb6cd 3909*mips32r2:
1e799e28 3910*mips64:
e70cb6cd 3911*mips64r2:
c906108c
SS		 3912*vr4100:
3913*vr5000:
3914*r3900:
3915{
3916 do_or (SD_, RS, RT, RD);
3917}
3918
3919
3920
3921:function:::void:do_ori:int rs, int rt, unsigned immediate
3922{
3923 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3924 GPR[rt] = (GPR[rs] | immediate);
3925 TRACE_ALU_RESULT (GPR[rt]);
3926}
3927
3928001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
82f728db 3929"ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
c5d00cc7
CD		 3930*mipsI:
3931*mipsII:
3932*mipsIII:
3933*mipsIV:
603a98e7 3934*mipsV:
1e799e28 3935*mips32:
e70cb6cd 3936*mips32r2:
1e799e28 3937*mips64:
e70cb6cd 3938*mips64r2:
c906108c
SS		 3939*vr4100:
3940*vr5000:
3941*r3900:
3942{
3943 do_ori (SD_, RS, RT, IMMEDIATE);
3944}
3945
3946
af5107af
CD		 3947110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
3948"pref <HINT>, <OFFSET>(r<BASE>)"
c906108c 3949*mipsIV:
603a98e7 3950*mipsV:
1e799e28 3951*mips32:
e70cb6cd 3952*mips32r2:
1e799e28 3953*mips64:
e70cb6cd 3954*mips64r2:
c906108c
SS		 3955*vr5000:
3956{
8e394ffc 3957 do_pref (SD_, HINT, OFFSET, BASE);
c906108c
SS		 3958}
3959
1c47a468 3960
e70cb6cd
CD		 3961:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
3962{
3963 unsigned64 result;
3964
3965 y &= 31;
3966 TRACE_ALU_INPUT2 (x, y);
3967 result = EXTEND32 (ROTR32 (x, y));
3968 TRACE_ALU_RESULT (result);
3969 return result;
3970}
3971
3972000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
3973"ror r<RD>, r<RT>, <SHIFT>"
3974*mips32r2:
3975*mips64r2:
2d2733fc 3976*smartmips:
e70cb6cd
CD		 3977*vr5400:
3978*vr5500:
3979{
3980 GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
3981}
3982
3983000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
3984"rorv r<RD>, r<RT>, r<RS>"
3985*mips32r2:
3986*mips64r2:
2d2733fc 3987*smartmips:
e70cb6cd
CD		 3988*vr5400:
3989*vr5500:
3990{
3991 GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
3992}
3993
3994
c906108c
SS		 3995:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
3996{
3997 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3998 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
3999 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
4000 unsigned int byte;
4001 address_word paddr;
c906108c
SS		 4002 unsigned64 memval;
4003 address_word vaddr;
4004
26f8bf63 4005 paddr = vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 4006 if ((vaddr & access) != 0)
4007 {
4008 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
4009 }
c906108c
SS		 4010 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4011 byte = ((vaddr & mask) ^ bigendiancpu);
4012 memval = (word << (8 * byte));
26f8bf63 4013 StoreMemory (access, memval, 0, paddr, vaddr, isREAL);
c906108c
SS		 4014}
4015
1c47a468
CD		 4016:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
4017{
4018 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4019 address_word reverseendian = (ReverseEndian ? -1 : 0);
4020 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
4021 unsigned int byte;
4022 unsigned int word;
4023 address_word paddr;
1c47a468
CD		 4024 unsigned64 memval;
4025 address_word vaddr;
4026 int nr_lhs_bits;
4027 int nr_rhs_bits;
4028
26f8bf63 4029 paddr = vaddr = loadstore_ea (SD_, base, offset);
1c47a468
CD		 4030 paddr = (paddr ^ (reverseendian & mask));
4031 if (BigEndianMem == 0)
4032 paddr = paddr & ~access;
4033
4034 /* compute where within the word/mem we are */
4035 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
4036 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
4037 nr_lhs_bits = 8 * byte + 8;
4038 nr_rhs_bits = 8 * access - 8 * byte;
4039 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
4040 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
4041 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
4042 (long) ((unsigned64) paddr >> 32), (long) paddr,
4043 word, byte, nr_lhs_bits, nr_rhs_bits); */
4044
4045 if (word == 0)
4046 {
4047 memval = (rt >> nr_rhs_bits);
4048 }
4049 else
4050 {
4051 memval = (rt << nr_lhs_bits);
4052 }
4053 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
4054 (long) ((unsigned64) rt >> 32), (long) rt,
4055 (long) ((unsigned64) memval >> 32), (long) memval); */
26f8bf63 4056 StoreMemory (byte, memval, 0, paddr, vaddr, isREAL);
1c47a468
CD		 4057}
4058
4059:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
4060{
4061 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4062 address_word reverseendian = (ReverseEndian ? -1 : 0);
4063 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
4064 unsigned int byte;
4065 address_word paddr;
1c47a468
CD		 4066 unsigned64 memval;
4067 address_word vaddr;
4068
26f8bf63 4069 paddr = vaddr = loadstore_ea (SD_, base, offset);
1c47a468
CD		 4070 paddr = (paddr ^ (reverseendian & mask));
4071 if (BigEndianMem != 0)
4072 paddr &= ~access;
4073 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
4074 memval = (rt << (byte * 8));
26f8bf63 4075 StoreMemory (access - (access & byte), memval, 0, paddr, vaddr, isREAL);
1c47a468
CD		 4076}
4077
c906108c
SS		 4078
4079101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
4080"sb r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 4081*mipsI:
4082*mipsII:
4083*mipsIII:
4084*mipsIV:
603a98e7 4085*mipsV:
1e799e28 4086*mips32:
e70cb6cd 4087*mips32r2:
1e799e28 4088*mips64:
e70cb6cd 4089*mips64r2:
c906108c
SS		 4090*vr4100:
4091*vr5000:
4092*r3900:
4093{
4094 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4095}
4096
4097
4098111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
4099"sc r<RT>, <OFFSET>(r<BASE>)"
4100*mipsII:
4101*mipsIII:
4102*mipsIV:
603a98e7 4103*mipsV:
1e799e28 4104*mips32:
e70cb6cd 4105*mips32r2:
1e799e28 4106*mips64:
e70cb6cd 4107*mips64r2:
8e394ffc
AB		 4108*vr4100:
4109*vr5000:
4110{
4111 do_sc (SD_, RT, OFFSET, BASE, instruction_0);
4112}
4113
4114
4115111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
4116"scd r<RT>, <OFFSET>(r<BASE>)"
4117*mipsIII:
4118*mipsIV:
4119*mipsV:
4120*mips64:
4121*mips64r2:
4122*vr4100:
4123*vr5000:
4124{
4125 check_u64 (SD_, instruction_0);
4126 do_scd (SD_, RT, OFFSET, BASE);
c906108c
SS		 4127}
4128
4129
4130111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
4131"sd r<RT>, <OFFSET>(r<BASE>)"
4132*mipsIII:
4133*mipsIV:
603a98e7 4134*mipsV:
1e799e28 4135*mips64:
e70cb6cd 4136*mips64r2:
c906108c
SS		 4137*vr4100:
4138*vr5000:
4139{
ca971540 4140 check_u64 (SD_, instruction_0);
c906108c
SS		 4141 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4142}
4143
4144
41451111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
4146"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
4147*mipsII:
4148*mipsIII:
4149*mipsIV:
603a98e7 4150*mipsV:
1e799e28 4151*mips32:
e70cb6cd 4152*mips32r2:
1e799e28 4153*mips64:
e70cb6cd 4154*mips64r2:
c906108c
SS		 4155*vr4100:
4156*vr5000:
4157{
4158 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
4159}
4160
4161
4162101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
4163"sdl r<RT>, <OFFSET>(r<BASE>)"
4164*mipsIII:
4165*mipsIV:
603a98e7 4166*mipsV:
1e799e28 4167*mips64:
e70cb6cd 4168*mips64r2:
c906108c
SS		 4169*vr4100:
4170*vr5000:
4171{
ca971540 4172 check_u64 (SD_, instruction_0);
c906108c
SS		 4173 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4174}
4175
4176
4177101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
4178"sdr r<RT>, <OFFSET>(r<BASE>)"
4179*mipsIII:
4180*mipsIV:
603a98e7 4181*mipsV:
1e799e28 4182*mips64:
e70cb6cd 4183*mips64r2:
c906108c
SS		 4184*vr4100:
4185*vr5000:
4186{
ca971540 4187 check_u64 (SD_, instruction_0);
c906108c
SS		 4188 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4189}
4190
4191
e70cb6cd 4192
c906108c
SS		 4193101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
4194"sh r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 4195*mipsI:
4196*mipsII:
4197*mipsIII:
4198*mipsIV:
603a98e7 4199*mipsV:
1e799e28 4200*mips32:
e70cb6cd 4201*mips32r2:
1e799e28 4202*mips64:
e70cb6cd 4203*mips64r2:
c906108c
SS		 4204*vr4100:
4205*vr5000:
4206*r3900:
4207{
4208 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4209}
4210
4211
4212:function:::void:do_sll:int rt, int rd, int shift
4213{
4214 unsigned32 temp = (GPR[rt] << shift);
4215 TRACE_ALU_INPUT2 (GPR[rt], shift);
4216 GPR[rd] = EXTEND32 (temp);
4217 TRACE_ALU_RESULT (GPR[rd]);
4218}
4219
1e799e28 4220000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
20ae0098 4221"nop":RD == 0 && RT == 0 && SHIFT == 0
c906108c 4222"sll r<RD>, r<RT>, <SHIFT>"
c5d00cc7
CD		 4223*mipsI:
4224*mipsII:
4225*mipsIII:
4226*mipsIV:
603a98e7 4227*mipsV:
c906108c
SS		 4228*vr4100:
4229*vr5000:
4230*r3900:
4231{
20ae0098
CD		 4232 /* Skip shift for NOP, so that there won't be lots of extraneous
4233 trace output. */
4234 if (RD != 0 || RT != 0 || SHIFT != 0)
4235 do_sll (SD_, RT, RD, SHIFT);
c906108c
SS		 4236}
4237
1e799e28
CD		 4238000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
4239"nop":RD == 0 && RT == 0 && SHIFT == 0
4240"ssnop":RD == 0 && RT == 0 && SHIFT == 1
4241"sll r<RD>, r<RT>, <SHIFT>"
4242*mips32:
e70cb6cd 4243*mips32r2:
1e799e28 4244*mips64:
e70cb6cd 4245*mips64r2:
1e799e28
CD		 4246{
4247 /* Skip shift for NOP and SSNOP, so that there won't be lots of
4248 extraneous trace output. */
4249 if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
4250 do_sll (SD_, RT, RD, SHIFT);
4251}
4252
c906108c
SS		 4253
4254:function:::void:do_sllv:int rs, int rt, int rd
4255{
4256 int s = MASKED (GPR[rs], 4, 0);
4257 unsigned32 temp = (GPR[rt] << s);
4258 TRACE_ALU_INPUT2 (GPR[rt], s);
4259 GPR[rd] = EXTEND32 (temp);
4260 TRACE_ALU_RESULT (GPR[rd]);
4261}
4262
f701dad2 4263000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
c906108c 4264"sllv r<RD>, r<RT>, r<RS>"
c5d00cc7
CD		 4265*mipsI:
4266*mipsII:
4267*mipsIII:
4268*mipsIV:
603a98e7 4269*mipsV:
1e799e28 4270*mips32:
e70cb6cd 4271*mips32r2:
1e799e28 4272*mips64:
e70cb6cd 4273*mips64r2:
c906108c
SS		 4274*vr4100:
4275*vr5000:
4276*r3900:
4277{
4278 do_sllv (SD_, RS, RT, RD);
4279}
4280
4281
4282:function:::void:do_slt:int rs, int rt, int rd
4283{
4284 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4285 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
4286 TRACE_ALU_RESULT (GPR[rd]);
4287}
4288
f701dad2 4289000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
c906108c 4290"slt r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 4291*mipsI:
4292*mipsII:
4293*mipsIII:
4294*mipsIV:
603a98e7 4295*mipsV:
1e799e28 4296*mips32:
e70cb6cd 4297*mips32r2:
1e799e28 4298*mips64:
e70cb6cd 4299*mips64r2:
c906108c
SS		 4300*vr4100:
4301*vr5000:
4302*r3900:
4303{
4304 do_slt (SD_, RS, RT, RD);
4305}
4306
4307
4308:function:::void:do_slti:int rs, int rt, unsigned16 immediate
4309{
4310 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
4311 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
4312 TRACE_ALU_RESULT (GPR[rt]);
4313}
4314
4315001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
4316"slti r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 4317*mipsI:
4318*mipsII:
4319*mipsIII:
4320*mipsIV:
603a98e7 4321*mipsV:
1e799e28 4322*mips32:
e70cb6cd 4323*mips32r2:
1e799e28 4324*mips64:
e70cb6cd 4325*mips64r2:
c906108c
SS		 4326*vr4100:
4327*vr5000:
4328*r3900:
4329{
4330 do_slti (SD_, RS, RT, IMMEDIATE);
4331}
4332
4333
4334:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
4335{
4336 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
4337 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
4338 TRACE_ALU_RESULT (GPR[rt]);
4339}
4340
4341001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
4342"sltiu r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 4343*mipsI:
4344*mipsII:
4345*mipsIII:
4346*mipsIV:
603a98e7 4347*mipsV:
1e799e28 4348*mips32:
e70cb6cd 4349*mips32r2:
1e799e28 4350*mips64:
e70cb6cd 4351*mips64r2:
c906108c
SS		 4352*vr4100:
4353*vr5000:
4354*r3900:
4355{
4356 do_sltiu (SD_, RS, RT, IMMEDIATE);
4357}
4358
4359
4360
4361:function:::void:do_sltu:int rs, int rt, int rd
4362{
4363 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4364 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
4365 TRACE_ALU_RESULT (GPR[rd]);
4366}
4367
f701dad2 4368000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
c906108c 4369"sltu r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 4370*mipsI:
4371*mipsII:
4372*mipsIII:
4373*mipsIV:
603a98e7 4374*mipsV:
1e799e28 4375*mips32:
e70cb6cd 4376*mips32r2:
1e799e28 4377*mips64:
e70cb6cd 4378*mips64r2:
c906108c
SS		 4379*vr4100:
4380*vr5000:
4381*r3900:
4382{
4383 do_sltu (SD_, RS, RT, RD);
4384}
4385
4386
4387:function:::void:do_sra:int rt, int rd, int shift
4388{
4389 signed32 temp = (signed32) GPR[rt] >> shift;
402586aa
CD		 4390 if (NotWordValue (GPR[rt]))
4391 Unpredictable ();
c906108c
SS		 4392 TRACE_ALU_INPUT2 (GPR[rt], shift);
4393 GPR[rd] = EXTEND32 (temp);
4394 TRACE_ALU_RESULT (GPR[rd]);
4395}
4396
4397000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
4398"sra r<RD>, r<RT>, <SHIFT>"
c5d00cc7
CD		 4399*mipsI:
4400*mipsII:
4401*mipsIII:
4402*mipsIV:
603a98e7 4403*mipsV:
1e799e28 4404*mips32:
e70cb6cd 4405*mips32r2:
1e799e28 4406*mips64:
e70cb6cd 4407*mips64r2:
c906108c
SS		 4408*vr4100:
4409*vr5000:
4410*r3900:
4411{
4412 do_sra (SD_, RT, RD, SHIFT);
4413}
4414
4415
4416
4417:function:::void:do_srav:int rs, int rt, int rd
4418{
4419 int s = MASKED (GPR[rs], 4, 0);
4420 signed32 temp = (signed32) GPR[rt] >> s;
402586aa
CD		 4421 if (NotWordValue (GPR[rt]))
4422 Unpredictable ();
c906108c
SS		 4423 TRACE_ALU_INPUT2 (GPR[rt], s);
4424 GPR[rd] = EXTEND32 (temp);
4425 TRACE_ALU_RESULT (GPR[rd]);
4426}
4427
f701dad2 4428000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
c906108c 4429"srav r<RD>, r<RT>, r<RS>"
c5d00cc7
CD		 4430*mipsI:
4431*mipsII:
4432*mipsIII:
4433*mipsIV:
603a98e7 4434*mipsV:
1e799e28 4435*mips32:
e70cb6cd 4436*mips32r2:
1e799e28 4437*mips64:
e70cb6cd 4438*mips64r2:
c906108c
SS		 4439*vr4100:
4440*vr5000:
4441*r3900:
4442{
4443 do_srav (SD_, RS, RT, RD);
4444}
4445
4446
4447
4448:function:::void:do_srl:int rt, int rd, int shift
4449{
4450 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
402586aa
CD		 4451 if (NotWordValue (GPR[rt]))
4452 Unpredictable ();
c906108c
SS		 4453 TRACE_ALU_INPUT2 (GPR[rt], shift);
4454 GPR[rd] = EXTEND32 (temp);
4455 TRACE_ALU_RESULT (GPR[rd]);
4456}
4457
4458000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
4459"srl r<RD>, r<RT>, <SHIFT>"
c5d00cc7
CD		 4460*mipsI:
4461*mipsII:
4462*mipsIII:
4463*mipsIV:
603a98e7 4464*mipsV:
1e799e28 4465*mips32:
e70cb6cd 4466*mips32r2:
1e799e28 4467*mips64:
e70cb6cd 4468*mips64r2:
c906108c
SS		 4469*vr4100:
4470*vr5000:
4471*r3900:
4472{
4473 do_srl (SD_, RT, RD, SHIFT);
4474}
4475
4476
4477:function:::void:do_srlv:int rs, int rt, int rd
4478{
4479 int s = MASKED (GPR[rs], 4, 0);
4480 unsigned32 temp = (unsigned32) GPR[rt] >> s;
402586aa
CD		 4481 if (NotWordValue (GPR[rt]))
4482 Unpredictable ();
c906108c
SS		 4483 TRACE_ALU_INPUT2 (GPR[rt], s);
4484 GPR[rd] = EXTEND32 (temp);
4485 TRACE_ALU_RESULT (GPR[rd]);
4486}
4487
f701dad2 4488000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
c906108c 4489"srlv r<RD>, r<RT>, r<RS>"
c5d00cc7
CD		 4490*mipsI:
4491*mipsII:
4492*mipsIII:
4493*mipsIV:
603a98e7 4494*mipsV:
1e799e28 4495*mips32:
e70cb6cd 4496*mips32r2:
1e799e28 4497*mips64:
e70cb6cd 4498*mips64r2:
c906108c
SS		 4499*vr4100:
4500*vr5000:
4501*r3900:
4502{
4503 do_srlv (SD_, RS, RT, RD);
4504}
4505
4506
f701dad2 4507000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
c906108c 4508"sub r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 4509*mipsI:
4510*mipsII:
4511*mipsIII:
4512*mipsIV:
603a98e7 4513*mipsV:
1e799e28 4514*mips32:
e70cb6cd 4515*mips32r2:
1e799e28 4516*mips64:
e70cb6cd 4517*mips64r2:
c906108c
SS		 4518*vr4100:
4519*vr5000:
4520*r3900:
4521{
8e394ffc 4522 do_sub (SD_, RD, RS, RT);
c906108c
SS		 4523}
4524
4525
4526:function:::void:do_subu:int rs, int rt, int rd
4527{
402586aa
CD		 4528 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
4529 Unpredictable ();
c906108c
SS		 4530 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4531 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
4532 TRACE_ALU_RESULT (GPR[rd]);
4533}
4534
f701dad2 4535000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
c906108c 4536"subu r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 4537*mipsI:
4538*mipsII:
4539*mipsIII:
4540*mipsIV:
603a98e7 4541*mipsV:
1e799e28 4542*mips32:
e70cb6cd 4543*mips32r2:
1e799e28 4544*mips64:
e70cb6cd 4545*mips64r2:
c906108c
SS		 4546*vr4100:
4547*vr5000:
4548*r3900:
4549{
4550 do_subu (SD_, RS, RT, RD);
4551}
4552
4553
4554101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
4555"sw r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 4556*mipsI:
4557*mipsII:
4558*mipsIII:
4559*mipsIV:
603a98e7 4560*mipsV:
1e799e28 4561*mips32:
e70cb6cd 4562*mips32r2:
1e799e28 4563*mips64:
e70cb6cd 4564*mips64r2:
c906108c
SS		 4565*vr4100:
4566*r3900:
4567*vr5000:
4568{
8e394ffc 4569 do_sw (SD_, RT, OFFSET, BASE);
c906108c
SS		 4570}
4571
4572
45731110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
4574"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 4575*mipsI:
4576*mipsII:
4577*mipsIII:
4578*mipsIV:
603a98e7 4579*mipsV:
1e799e28 4580*mips32:
e70cb6cd 4581*mips32r2:
1e799e28 4582*mips64:
e70cb6cd 4583*mips64r2:
c906108c
SS		 4584*vr4100:
4585*vr5000:
4586*r3900:
4587{
4588 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
4589}
4590
4591
c906108c
SS		 4592101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
4593"swl r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 4594*mipsI:
4595*mipsII:
4596*mipsIII:
4597*mipsIV:
603a98e7 4598*mipsV:
1e799e28 4599*mips32:
e70cb6cd 4600*mips32r2:
1e799e28 4601*mips64:
e70cb6cd 4602*mips64r2:
c906108c
SS		 4603*vr4100:
4604*vr5000:
4605*r3900:
4606{
4607 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4608}
4609
4610
c906108c
SS		 4611101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
4612"swr r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 4613*mipsI:
4614*mipsII:
4615*mipsIII:
4616*mipsIV:
603a98e7 4617*mipsV:
1e799e28 4618*mips32:
e70cb6cd 4619*mips32r2:
1e799e28 4620*mips64:
e70cb6cd 4621*mips64r2:
c906108c
SS		 4622*vr4100:
4623*vr5000:
4624*r3900:
4625{
4626 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4627}
4628
4629
f701dad2 4630000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
c906108c
SS		 4631"sync":STYPE == 0
4632"sync <STYPE>"
4633*mipsII:
4634*mipsIII:
4635*mipsIV:
603a98e7 4636*mipsV:
1e799e28 4637*mips32:
e70cb6cd 4638*mips32r2:
1e799e28 4639*mips64:
e70cb6cd 4640*mips64r2:
c906108c
SS		 4641*vr4100:
4642*vr5000:
4643*r3900:
4644{
4645 SyncOperation (STYPE);
4646}
4647
4648
4649000000,20.CODE,001100:SPECIAL:32::SYSCALL
82f728db 4650"syscall %#lx<CODE>"
c5d00cc7
CD		 4651*mipsI:
4652*mipsII:
4653*mipsIII:
4654*mipsIV:
603a98e7 4655*mipsV:
1e799e28 4656*mips32:
e70cb6cd 4657*mips32r2:
1e799e28 4658*mips64:
e70cb6cd 4659*mips64r2:
c906108c
SS		 4660*vr4100:
4661*vr5000:
4662*r3900:
4663{
86b77b47 4664 SignalException (SystemCall, instruction_0);
c906108c
SS		 4665}
4666
4667
4668000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
4669"teq r<RS>, r<RT>"
4670*mipsII:
4671*mipsIII:
4672*mipsIV:
603a98e7 4673*mipsV:
1e799e28 4674*mips32:
e70cb6cd 4675*mips32r2:
1e799e28 4676*mips64:
e70cb6cd 4677*mips64r2:
c906108c
SS		 4678*vr4100:
4679*vr5000:
4680{
8e394ffc 4681 do_teq (SD_, RS, RT, instruction_0);
c906108c
SS		 4682}
4683
4684
4685000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
4686"teqi r<RS>, <IMMEDIATE>"
4687*mipsII:
4688*mipsIII:
4689*mipsIV:
603a98e7 4690*mipsV:
1e799e28 4691*mips32:
e70cb6cd 4692*mips32r2:
1e799e28 4693*mips64:
e70cb6cd 4694*mips64r2:
c906108c
SS		 4695*vr4100:
4696*vr5000:
4697{
8e394ffc 4698 do_teqi (SD_, RS, IMMEDIATE, instruction_0);
c906108c
SS		 4699}
4700
4701
4702000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
4703"tge r<RS>, r<RT>"
4704*mipsII:
4705*mipsIII:
4706*mipsIV:
603a98e7 4707*mipsV:
1e799e28 4708*mips32:
e70cb6cd 4709*mips32r2:
1e799e28 4710*mips64:
e70cb6cd 4711*mips64r2:
c906108c
SS		 4712*vr4100:
4713*vr5000:
4714{
8e394ffc 4715 do_tge (SD_, RS, RT, instruction_0);
c906108c
SS		 4716}
4717
4718
4719000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
4720"tgei r<RS>, <IMMEDIATE>"
4721*mipsII:
4722*mipsIII:
4723*mipsIV:
603a98e7 4724*mipsV:
1e799e28 4725*mips32:
e70cb6cd 4726*mips32r2:
1e799e28 4727*mips64:
e70cb6cd 4728*mips64r2:
c906108c
SS		 4729*vr4100:
4730*vr5000:
4731{
8e394ffc 4732 do_tgei (SD_, RS, IMMEDIATE, instruction_0);
c906108c
SS		 4733}
4734
4735
4736000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
4737"tgeiu r<RS>, <IMMEDIATE>"
4738*mipsII:
4739*mipsIII:
4740*mipsIV:
603a98e7 4741*mipsV:
1e799e28 4742*mips32:
e70cb6cd 4743*mips32r2:
1e799e28 4744*mips64:
e70cb6cd 4745*mips64r2:
c906108c
SS		 4746*vr4100:
4747*vr5000:
4748{
8e394ffc 4749 do_tgeiu (SD_, RS, IMMEDIATE, instruction_0);
c906108c
SS		 4750}
4751
4752
4753000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
4754"tgeu r<RS>, r<RT>"
4755*mipsII:
4756*mipsIII:
4757*mipsIV:
603a98e7 4758*mipsV:
1e799e28 4759*mips32:
e70cb6cd 4760*mips32r2:
1e799e28 4761*mips64:
e70cb6cd 4762*mips64r2:
c906108c
SS		 4763*vr4100:
4764*vr5000:
4765{
8e394ffc 4766 do_tgeu (SD_, RS, RT, instruction_0);
c906108c
SS		 4767}
4768
4769
4770000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
4771"tlt r<RS>, r<RT>"
4772*mipsII:
4773*mipsIII:
4774*mipsIV:
603a98e7 4775*mipsV:
1e799e28 4776*mips32:
e70cb6cd 4777*mips32r2:
1e799e28 4778*mips64:
e70cb6cd 4779*mips64r2:
c906108c
SS		 4780*vr4100:
4781*vr5000:
4782{
8e394ffc 4783 do_tlt (SD_, RS, RT, instruction_0);
c906108c
SS		 4784}
4785
4786
4787000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
4788"tlti r<RS>, <IMMEDIATE>"
4789*mipsII:
4790*mipsIII:
4791*mipsIV:
603a98e7 4792*mipsV:
1e799e28 4793*mips32:
e70cb6cd 4794*mips32r2:
1e799e28 4795*mips64:
e70cb6cd 4796*mips64r2:
c906108c
SS		 4797*vr4100:
4798*vr5000:
4799{
8e394ffc 4800 do_tlti (SD_, RS, IMMEDIATE, instruction_0);
c906108c
SS		 4801}
4802
4803
4804000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
4805"tltiu r<RS>, <IMMEDIATE>"
4806*mipsII:
4807*mipsIII:
4808*mipsIV:
603a98e7 4809*mipsV:
1e799e28 4810*mips32:
e70cb6cd 4811*mips32r2:
1e799e28 4812*mips64:
e70cb6cd 4813*mips64r2:
c906108c
SS		 4814*vr4100:
4815*vr5000:
4816{
8e394ffc 4817 do_tltiu (SD_, RS, IMMEDIATE, instruction_0);
c906108c
SS		 4818}
4819
4820
4821000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
4822"tltu r<RS>, r<RT>"
4823*mipsII:
4824*mipsIII:
4825*mipsIV:
603a98e7 4826*mipsV:
1e799e28 4827*mips32:
e70cb6cd 4828*mips32r2:
1e799e28 4829*mips64:
e70cb6cd 4830*mips64r2:
c906108c
SS		 4831*vr4100:
4832*vr5000:
4833{
8e394ffc 4834 do_tltu (SD_, RS, RT, instruction_0);
c906108c
SS		 4835}
4836
4837
4838000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
4839"tne r<RS>, r<RT>"
4840*mipsII:
4841*mipsIII:
4842*mipsIV:
603a98e7 4843*mipsV:
1e799e28 4844*mips32:
e70cb6cd 4845*mips32r2:
1e799e28 4846*mips64:
e70cb6cd 4847*mips64r2:
c906108c
SS		 4848*vr4100:
4849*vr5000:
4850{
8e394ffc 4851 do_tne (SD_, RS, RT, instruction_0);
c906108c
SS		 4852}
4853
4854
4855000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
95fd5cee 4856"tnei r<RS>, <IMMEDIATE>"
c906108c
SS		 4857*mipsII:
4858*mipsIII:
4859*mipsIV:
603a98e7 4860*mipsV:
1e799e28 4861*mips32:
e70cb6cd 4862*mips32r2:
1e799e28 4863*mips64:
e70cb6cd 4864*mips64r2:
c906108c
SS		 4865*vr4100:
4866*vr5000:
4867{
8e394ffc 4868 do_tnei (SD_, RS, IMMEDIATE, instruction_0);
c906108c
SS		 4869}
4870
4871
4872:function:::void:do_xor:int rs, int rt, int rd
4873{
4874 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4875 GPR[rd] = GPR[rs] ^ GPR[rt];
4876 TRACE_ALU_RESULT (GPR[rd]);
4877}
4878
f701dad2 4879000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
c906108c 4880"xor r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 4881*mipsI:
4882*mipsII:
4883*mipsIII:
4884*mipsIV:
603a98e7 4885*mipsV:
1e799e28 4886*mips32:
e70cb6cd 4887*mips32r2:
1e799e28 4888*mips64:
e70cb6cd 4889*mips64r2:
c906108c
SS		 4890*vr4100:
4891*vr5000:
4892*r3900:
4893{
4894 do_xor (SD_, RS, RT, RD);
4895}
4896
4897
4898:function:::void:do_xori:int rs, int rt, unsigned16 immediate
4899{
4900 TRACE_ALU_INPUT2 (GPR[rs], immediate);
4901 GPR[rt] = GPR[rs] ^ immediate;
4902 TRACE_ALU_RESULT (GPR[rt]);
4903}
4904
4905001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
82f728db 4906"xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
c5d00cc7
CD		 4907*mipsI:
4908*mipsII:
4909*mipsIII:
4910*mipsIV:
603a98e7 4911*mipsV:
1e799e28 4912*mips32:
e70cb6cd 4913*mips32r2:
1e799e28 4914*mips64:
e70cb6cd 4915*mips64r2:
c906108c
SS		 4916*vr4100:
4917*vr5000:
4918*r3900:
4919{
4920 do_xori (SD_, RS, RT, IMMEDIATE);
4921}
4922
4923\f
4924//
4925// MIPS Architecture:
4926//
4927// FPU Instruction Set (COP1 & COP1X)
4928//
4929
4930
4931:%s::::FMT:int fmt
4932{
4933 switch (fmt)
4934 {
4935 case fmt_single: return "s";
4936 case fmt_double: return "d";
4937 case fmt_word: return "w";
4938 case fmt_long: return "l";
3a2b820e 4939 case fmt_ps: return "ps";
c906108c
SS		 4940 default: return "?";
4941 }
4942}
4943
c906108c
SS		 4944:%s::::TF:int tf
4945{
4946 if (tf)
4947 return "t";
4948 else
4949 return "f";
4950}
4951
4952:%s::::ND:int nd
4953{
4954 if (nd)
4955 return "l";
4956 else
4957 return "";
4958}
4959
4960:%s::::COND:int cond
4961{
4962 switch (cond)
4963 {
4964 case 00: return "f";
4965 case 01: return "un";
4966 case 02: return "eq";
4967 case 03: return "ueq";
4968 case 04: return "olt";
4969 case 05: return "ult";
4970 case 06: return "ole";
4971 case 07: return "ule";
4972 case 010: return "sf";
4973 case 011: return "ngle";
4974 case 012: return "seq";
4975 case 013: return "ngl";
4976 case 014: return "lt";
4977 case 015: return "nge";
4978 case 016: return "le";
4979 case 017: return "ngt";
4980 default: return "?";
4981 }
4982}
4983
8612006b
CD		 4984
4985// Helpers:
4986//
4987// Check that the given FPU format is usable, and signal a
4988// ReservedInstruction exception if not.
4989//
4990
8612006b
CD		 4991// check_fmt_p checks that the format is single, double, or paired single.
4992:function:::void:check_fmt_p:int fmt, instruction_word insn
4993*mipsI:
4994*mipsII:
4995*mipsIII:
4996*mipsIV:
1e799e28 4997*mips32:
8612006b
CD		 4998*vr4100:
4999*vr5000:
5000*r3900:
5001{
5002 /* None of these ISAs support Paired Single, so just fall back to
5003 the single/double check. */
14234056
CD		 5004 if ((fmt != fmt_single) && (fmt != fmt_double))
5005 SignalException (ReservedInstruction, insn);
8612006b
CD		 5006}
5007
60dc88db
RS		 5008:function:::void:check_fmt_p:int fmt, instruction_word insn
5009*mips32r2:
8e394ffc 5010*micromips32:
60dc88db
RS		 5011{
5012 if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps))
5013 SignalException (ReservedInstruction, insn);
5014}
5015
1e799e28
CD		 5016:function:::void:check_fmt_p:int fmt, instruction_word insn
5017*mipsV:
5018*mips64:
e70cb6cd 5019*mips64r2:
8e394ffc 5020*micromips64:
1e799e28 5021{
1e799e28
CD		 5022 if ((fmt != fmt_single) && (fmt != fmt_double)
5023 && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
5024 SignalException (ReservedInstruction, insn);
1e799e28
CD		 5025}
5026
8612006b 5027
ca971540 5028// Helper:
4a0bd876 5029//
ca971540
CD		 5030// Check that the FPU is currently usable, and signal a CoProcessorUnusable
5031// exception if not.
5032//
5033
5034:function:::void:check_fpu:
4a0bd876 5035*mipsI:
ca971540
CD		 5036*mipsII:
5037*mipsIII:
5038*mipsIV:
5039*mipsV:
1e799e28 5040*mips32:
e70cb6cd 5041*mips32r2:
1e799e28 5042*mips64:
e70cb6cd 5043*mips64r2:
ca971540
CD		 5044*vr4100:
5045*vr5000:
5046*r3900:
8e394ffc
AB		 5047*micromips32:
5048*micromips64:
ca971540 5049{
ca971540
CD		 5050 if (! COP_Usable (1))
5051 SignalExceptionCoProcessorUnusable (1);
ca971540
CD		 5052}
5053
c906108c 5054
06e7837e
CD		 5055// Helper:
5056//
5057// Load a double word FP value using 2 32-bit memory cycles a la MIPS II
5058// or MIPS32. do_load cannot be used instead because it returns an
5059// unsigned_word, which is limited to the size of the machine's registers.
5060//
5061
5062:function:::unsigned64:do_load_double:address_word base, address_word offset
5063*mipsII:
5064*mips32:
e70cb6cd 5065*mips32r2:
8e394ffc 5066*micromips32:
06e7837e
CD		 5067{
5068 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
5069 address_word vaddr;
5070 address_word paddr;
06e7837e
CD		 5071 unsigned64 memval;
5072 unsigned64 v;
5073
26f8bf63 5074 paddr = vaddr = loadstore_ea (SD_, base, offset);
06e7837e
CD		 5075 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
5076 {
5077 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
5078 AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
5079 sim_core_unaligned_signal);
5080 }
26f8bf63 5081 LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA, isREAL);
06e7837e 5082 v = (unsigned64)memval;
26f8bf63
MF		 5083 LoadMemory (&memval, NULL, AccessLength_WORD, paddr + 4, vaddr + 4, isDATA,
5084 isREAL);
06e7837e
CD		 5085 return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
5086}
5087
5088
5089// Helper:
5090//
5091// Store a double word FP value using 2 32-bit memory cycles a la MIPS II
5092// or MIPS32. do_load cannot be used instead because it returns an
5093// unsigned_word, which is limited to the size of the machine's registers.
5094//
5095
5096:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
5097*mipsII:
5098*mips32:
e70cb6cd 5099*mips32r2:
8e394ffc 5100*micromips32:
06e7837e
CD		 5101{
5102 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
5103 address_word vaddr;
5104 address_word paddr;
06e7837e
CD		 5105 unsigned64 memval;
5106
26f8bf63 5107 paddr = vaddr = loadstore_ea (SD_, base, offset);
06e7837e
CD		 5108 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
5109 {
5110 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
5111 AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
5112 sim_core_unaligned_signal);
5113 }
06e7837e 5114 memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
26f8bf63 5115 StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr, isREAL);
06e7837e 5116 memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
26f8bf63 5117 StoreMemory (AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4, isREAL);
06e7837e
CD		 5118}
5119
5120
14234056 5121010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
c906108c 5122"abs.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 5123*mipsI:
5124*mipsII:
5125*mipsIII:
5126*mipsIV:
603a98e7 5127*mipsV:
1e799e28 5128*mips32:
e70cb6cd 5129*mips32r2:
1e799e28 5130*mips64:
e70cb6cd 5131*mips64r2:
c906108c
SS		 5132*vr4100:
5133*vr5000:
5134*r3900:
5135{
8e394ffc 5136 do_abs_fmt (SD_, FMT, FD, FS, instruction_0);
c906108c
SS		 5137}
5138
5139
5140
14234056 5141010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
c906108c 5142"add.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 5143*mipsI:
5144*mipsII:
5145*mipsIII:
5146*mipsIV:
603a98e7 5147*mipsV:
1e799e28 5148*mips32:
e70cb6cd 5149*mips32r2:
1e799e28 5150*mips64:
e70cb6cd 5151*mips64r2:
c906108c
SS		 5152*vr4100:
5153*vr5000:
5154*r3900:
5155{
8e394ffc 5156 do_add_fmt (SD_, FMT, FD, FS, FT, instruction_0);
c906108c
SS		 5157}
5158
5159
60dc88db 5160010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:32,f::ALNV.PS
3a2b820e
CD		 5161"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
5162*mipsV:
bfe9c90b 5163*mips32r2:
3a2b820e 5164*mips64:
e70cb6cd 5165*mips64r2:
3a2b820e 5166{
8e394ffc 5167 do_alnv_ps (SD_, FD, FS, FT, RS, instruction_0);
3a2b820e
CD		 5168}
5169
c906108c
SS		 5170
5171// BC1F
5172// BC1FL
5173// BC1T
5174// BC1TL
5175
5176010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
5177"bc1%s<TF>%s<ND> <OFFSET>"
c5d00cc7
CD		 5178*mipsI:
5179*mipsII:
5180*mipsIII:
c906108c 5181{
9b17d183 5182 check_fpu (SD_);
c906108c
SS		 5183 TRACE_BRANCH_INPUT (PREVCOC1());
5184 if (PREVCOC1() == TF)
5185 {
5186 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
5187 TRACE_BRANCH_RESULT (dest);
c906108c
SS		 5188 DELAY_SLOT (dest);
5189 }
5190 else if (ND)
5191 {
5192 TRACE_BRANCH_RESULT (0);
5193 NULLIFY_NEXT_INSTRUCTION ();
5194 }
5195 else
5196 {
5197 TRACE_BRANCH_RESULT (NIA);
5198 }
5199}
5200
5201010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
5202"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
5203"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
5204*mipsIV:
603a98e7 5205*mipsV:
1e799e28 5206*mips32:
e70cb6cd 5207*mips32r2:
1e799e28 5208*mips64:
e70cb6cd 5209*mips64r2:
c906108c 5210#*vr4100:
074e9cb8 5211*vr5000:
c906108c
SS		 5212*r3900:
5213{
9b17d183 5214 check_fpu (SD_);
c906108c
SS		 5215 if (GETFCC(CC) == TF)
5216 {
5217 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
c906108c
SS		 5218 DELAY_SLOT (dest);
5219 }
5220 else if (ND)
5221 {
5222 NULLIFY_NEXT_INSTRUCTION ();
5223 }
5224}
5225
5226
14234056 5227010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
c906108c 5228"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
c5d00cc7
CD		 5229*mipsI:
5230*mipsII:
5231*mipsIII:
c906108c 5232{
8612006b 5233 int fmt = FMT;
9b17d183 5234 check_fpu (SD_);
cfe9ea23
CD		 5235 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
5236 TRACE_ALU_RESULT (ValueFCR (31));
c906108c
SS		 5237}
5238
14234056 5239010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
c906108c
SS		 5240"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
5241"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
5242*mipsIV:
603a98e7 5243*mipsV:
1e799e28 5244*mips32:
e70cb6cd 5245*mips32r2:
1e799e28 5246*mips64:
e70cb6cd 5247*mips64r2:
c906108c
SS		 5248*vr4100:
5249*vr5000:
5250*r3900:
5251{
8e394ffc 5252 do_c_cond_fmt (SD_, COND, FMT, CC, FS, FT, instruction_0);
c906108c
SS		 5253}
5254
5255
60dc88db 5256010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:32,f::CEIL.L.fmt
c906108c
SS		 5257"ceil.l.%s<FMT> f<FD>, f<FS>"
5258*mipsIII:
5259*mipsIV:
603a98e7 5260*mipsV:
bfe9c90b 5261*mips32r2:
1e799e28 5262*mips64:
e70cb6cd 5263*mips64r2:
c906108c
SS		 5264*vr4100:
5265*vr5000:
5266*r3900:
5267{
8e394ffc 5268 do_ceil_fmt (SD_, fmt_long, FMT, FD, FS, instruction_0);
c906108c
SS		 5269}
5270
5271
14234056 5272010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
95fd5cee 5273"ceil.w.%s<FMT> f<FD>, f<FS>"
c906108c
SS		 5274*mipsII:
5275*mipsIII:
5276*mipsIV:
603a98e7 5277*mipsV:
1e799e28 5278*mips32:
e70cb6cd 5279*mips32r2:
1e799e28 5280*mips64:
e70cb6cd 5281*mips64r2:
c906108c
SS		 5282*vr4100:
5283*vr5000:
5284*r3900:
5285{
8e394ffc 5286 do_ceil_fmt (SD_, fmt_word, FMT, FD, FS, instruction_0);
c906108c
SS		 5287}
5288
5289
cfe9ea23
CD		 5290010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
5291"cfc1 r<RT>, f<FS>"
c906108c
SS		 5292*mipsI:
5293*mipsII:
5294*mipsIII:
5295{
9b17d183 5296 check_fpu (SD_);
cfe9ea23
CD		 5297 if (FS == 0)
5298 PENDING_FILL (RT, EXTEND32 (FCR0));
5299 else if (FS == 31)
5300 PENDING_FILL (RT, EXTEND32 (FCR31));
5301 /* else NOP */
5302}
5303
5304010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
5305"cfc1 r<RT>, f<FS>"
5306*mipsIV:
5307*vr4100:
5308*vr5000:
5309*r3900:
5310{
5311 check_fpu (SD_);
5312 if (FS == 0 || FS == 31)
c906108c 5313 {
cfe9ea23
CD		 5314 unsigned_word fcr = ValueFCR (FS);
5315 TRACE_ALU_INPUT1 (fcr);
5316 GPR[RT] = fcr;
c906108c 5317 }
cfe9ea23
CD		 5318 /* else NOP */
5319 TRACE_ALU_RESULT (GPR[RT]);
c906108c 5320}
cfe9ea23
CD		 5321
5322010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
5323"cfc1 r<RT>, f<FS>"
603a98e7 5324*mipsV:
1e799e28 5325*mips32:
e70cb6cd 5326*mips32r2:
1e799e28 5327*mips64:
e70cb6cd 5328*mips64r2:
cfe9ea23 5329{
8e394ffc 5330 do_cfc1 (SD_, RT, FS);
cfe9ea23
CD		 5331}
5332
5333010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
5334"ctc1 r<RT>, f<FS>"
5335*mipsI:
5336*mipsII:
5337*mipsIII:
5338{
5339 check_fpu (SD_);
5340 if (FS == 31)
5341 PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
5342 /* else NOP */
5343}
5344
5345010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
5346"ctc1 r<RT>, f<FS>"
5347*mipsIV:
c906108c
SS		 5348*vr4100:
5349*vr5000:
5350*r3900:
5351{
9b17d183 5352 check_fpu (SD_);
cfe9ea23
CD		 5353 TRACE_ALU_INPUT1 (GPR[RT]);
5354 if (FS == 31)
5355 StoreFCR (FS, GPR[RT]);
5356 /* else NOP */
5357}
5358
5359010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
5360"ctc1 r<RT>, f<FS>"
5361*mipsV:
5362*mips32:
e70cb6cd 5363*mips32r2:
cfe9ea23 5364*mips64:
e70cb6cd 5365*mips64r2:
cfe9ea23 5366{
8e394ffc 5367 do_ctc1 (SD_, RT, FS);
c906108c
SS		 5368}
5369
5370
5371//
5372// FIXME: Does not correctly differentiate between mips*
5373//
14234056 5374010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
c906108c 5375"cvt.d.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 5376*mipsI:
5377*mipsII:
5378*mipsIII:
5379*mipsIV:
603a98e7 5380*mipsV:
1e799e28 5381*mips32:
e70cb6cd 5382*mips32r2:
1e799e28 5383*mips64:
e70cb6cd 5384*mips64r2:
c906108c
SS		 5385*vr4100:
5386*vr5000:
5387*r3900:
5388{
8e394ffc 5389 do_cvt_d_fmt (SD_, FMT, FD, FS, instruction_0);
c906108c
SS		 5390}
5391
5392
60dc88db 5393010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:32,f::CVT.L.fmt
c906108c
SS		 5394"cvt.l.%s<FMT> f<FD>, f<FS>"
5395*mipsIII:
5396*mipsIV:
603a98e7 5397*mipsV:
bfe9c90b 5398*mips32r2:
1e799e28 5399*mips64:
e70cb6cd 5400*mips64r2:
c906108c
SS		 5401*vr4100:
5402*vr5000:
5403*r3900:
5404{
8e394ffc 5405 do_cvt_l_fmt (SD_, FMT, FD, FS, instruction_0);
c906108c
SS		 5406}
5407
5408
60dc88db 5409010001,10,000,5.FT,5.FS,5.FD,100110:COP1:32,f::CVT.PS.S
3a2b820e
CD		 5410"cvt.ps.s f<FD>, f<FS>, f<FT>"
5411*mipsV:
bfe9c90b 5412*mips32r2:
3a2b820e 5413*mips64:
e70cb6cd 5414*mips64r2:
3a2b820e 5415{
8e394ffc 5416 do_cvt_ps_s (SD_, FD, FS, FT, instruction_0);
3a2b820e
CD		 5417}
5418
5419
c906108c
SS		 5420//
5421// FIXME: Does not correctly differentiate between mips*
5422//
14234056 5423010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
c906108c 5424"cvt.s.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 5425*mipsI:
5426*mipsII:
5427*mipsIII:
5428*mipsIV:
603a98e7 5429*mipsV:
1e799e28 5430*mips32:
e70cb6cd 5431*mips32r2:
1e799e28 5432*mips64:
e70cb6cd 5433*mips64r2:
c906108c
SS		 5434*vr4100:
5435*vr5000:
5436*r3900:
5437{
8e394ffc 5438 do_cvt_s_fmt (SD_, FMT, FD, FS, instruction_0);
c906108c
SS		 5439}
5440
5441
60dc88db 5442010001,10,110,00000,5.FS,5.FD,101000:COP1:32,f::CVT.S.PL
3a2b820e
CD		 5443"cvt.s.pl f<FD>, f<FS>"
5444*mipsV:
bfe9c90b 5445*mips32r2:
3a2b820e 5446*mips64:
e70cb6cd 5447*mips64r2:
3a2b820e 5448{
8e394ffc 5449 do_cvt_s_pl (SD_, FD, FS, instruction_0);
3a2b820e
CD		 5450}
5451
5452
60dc88db 5453010001,10,110,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.PU
3a2b820e
CD		 5454"cvt.s.pu f<FD>, f<FS>"
5455*mipsV:
bfe9c90b 5456*mips32r2:
3a2b820e 5457*mips64:
e70cb6cd 5458*mips64r2:
3a2b820e 5459{
8e394ffc 5460 do_cvt_s_pu (SD_, FD, FS, instruction_0);
3a2b820e
CD		 5461}
5462
5463
14234056 5464010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
c906108c 5465"cvt.w.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 5466*mipsI:
5467*mipsII:
5468*mipsIII:
5469*mipsIV:
603a98e7 5470*mipsV:
1e799e28 5471*mips32:
e70cb6cd 5472*mips32r2:
1e799e28 5473*mips64:
e70cb6cd 5474*mips64r2:
c906108c
SS		 5475*vr4100:
5476*vr5000:
5477*r3900:
5478{
8e394ffc 5479 do_cvt_w_fmt (SD_, FMT, FD, FS, instruction_0);
c906108c
SS		 5480}
5481
5482
14234056 5483010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
c906108c 5484"div.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 5485*mipsI:
5486*mipsII:
5487*mipsIII:
5488*mipsIV:
603a98e7 5489*mipsV:
1e799e28 5490*mips32:
e70cb6cd 5491*mips32r2:
1e799e28 5492*mips64:
e70cb6cd 5493*mips64r2:
c906108c
SS		 5494*vr4100:
5495*vr5000:
5496*r3900:
5497{
8e394ffc 5498 do_div_fmt (SD_, FMT, FD, FS, FT, instruction_0);
c906108c
SS		 5499}
5500
5501
cfe9ea23
CD		 5502010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
5503"dmfc1 r<RT>, f<FS>"
c906108c
SS		 5504*mipsIII:
5505{
cfe9ea23 5506 unsigned64 v;
9b17d183 5507 check_fpu (SD_);
ca971540 5508 check_u64 (SD_, instruction_0);
cfe9ea23
CD		 5509 if (SizeFGR () == 64)
5510 v = FGR[FS];
5511 else if ((FS & 0x1) == 0)
5512 v = SET64HI (FGR[FS+1]) | FGR[FS];
c906108c 5513 else
cfe9ea23
CD		 5514 v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
5515 PENDING_FILL (RT, v);
5516 TRACE_ALU_RESULT (v);
c906108c 5517}
cfe9ea23
CD		 5518
5519010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
5520"dmfc1 r<RT>, f<FS>"
c906108c 5521*mipsIV:
603a98e7 5522*mipsV:
1e799e28 5523*mips64:
e70cb6cd 5524*mips64r2:
c906108c
SS		 5525*vr4100:
5526*vr5000:
5527*r3900:
5528{
9b17d183 5529 check_fpu (SD_);
ca971540 5530 check_u64 (SD_, instruction_0);
8e394ffc 5531 do_dmfc1b (SD_, RT, FS);
cfe9ea23
CD		 5532}
5533
5534
5535010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
5536"dmtc1 r<RT>, f<FS>"
5537*mipsIII:
5538{
5539 unsigned64 v;
5540 check_fpu (SD_);
5541 check_u64 (SD_, instruction_0);
5542 if (SizeFGR () == 64)
5543 PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
5544 else if ((FS & 0x1) == 0)
c906108c 5545 {
cfe9ea23
CD		 5546 PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
5547 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
c906108c 5548 }
cfe9ea23
CD		 5549 else
5550 Unpredictable ();
5551 TRACE_FP_RESULT (GPR[RT]);
5552}
5553
5554010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
5555"dmtc1 r<RT>, f<FS>"
5556*mipsIV:
5557*mipsV:
5558*mips64:
e70cb6cd 5559*mips64r2:
cfe9ea23
CD		 5560*vr4100:
5561*vr5000:
5562*r3900:
5563{
5564 check_fpu (SD_);
5565 check_u64 (SD_, instruction_0);
8e394ffc 5566 do_dmtc1b (SD_, RT, FS);
c906108c
SS		 5567}
5568
5569
60dc88db 5570010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:32,f::FLOOR.L.fmt
c906108c
SS		 5571"floor.l.%s<FMT> f<FD>, f<FS>"
5572*mipsIII:
5573*mipsIV:
603a98e7 5574*mipsV:
bfe9c90b 5575*mips32r2:
1e799e28 5576*mips64:
e70cb6cd 5577*mips64r2:
c906108c
SS		 5578*vr4100:
5579*vr5000:
5580*r3900:
5581{
8e394ffc 5582 do_floor_fmt (SD_, fmt_long, FMT, FD, FS);
c906108c
SS		 5583}
5584
5585
14234056 5586010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
c906108c
SS		 5587"floor.w.%s<FMT> f<FD>, f<FS>"
5588*mipsII:
5589*mipsIII:
5590*mipsIV:
603a98e7 5591*mipsV:
1e799e28 5592*mips32:
e70cb6cd 5593*mips32r2:
1e799e28 5594*mips64:
e70cb6cd 5595*mips64r2:
c906108c
SS		 5596*vr4100:
5597*vr5000:
5598*r3900:
5599{
8e394ffc 5600 do_floor_fmt (SD_, fmt_word, FMT, FD, FS);
c906108c
SS		 5601}
5602
5603
06e7837e 5604110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
c906108c
SS		 5605"ldc1 f<FT>, <OFFSET>(r<BASE>)"
5606*mipsII:
06e7837e 5607*mips32:
e70cb6cd 5608*mips32r2:
06e7837e
CD		 5609{
5610 check_fpu (SD_);
5611 COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
5612}
5613
5614
5615110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
5616"ldc1 f<FT>, <OFFSET>(r<BASE>)"
c906108c
SS		 5617*mipsIII:
5618*mipsIV:
603a98e7 5619*mipsV:
1e799e28 5620*mips64:
e70cb6cd 5621*mips64r2:
c906108c
SS		 5622*vr4100:
5623*vr5000:
5624*r3900:
5625{
9b17d183 5626 check_fpu (SD_);
c906108c
SS		 5627 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
5628}
5629
5630
60dc88db
RS		 5631010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:32,f::LDXC1
5632"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
5633*mips32r2:
5634{
5635 check_fpu (SD_);
5636 COP_LD (1, FD, do_load_double (SD_, GPR[BASE], GPR[INDEX]));
5637}
5638
5639
eb5fcf93 5640010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
c906108c
SS		 5641"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
5642*mipsIV:
603a98e7 5643*mipsV:
1e799e28 5644*mips64:
e70cb6cd 5645*mips64r2:
c906108c
SS		 5646*vr5000:
5647{
9b17d183 5648 check_fpu (SD_);
ca971540 5649 check_u64 (SD_, instruction_0);
c906108c
SS		 5650 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
5651}
5652
5653
60dc88db
RS		 5654010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:32,f::LUXC1
5655"luxc1 f<FD>, r<INDEX>(r<BASE>)"
5656*mips32r2:
5657{
8e394ffc 5658 do_luxc1_32 (SD_, FD, INDEX, BASE);
60dc88db
RS		 5659}
5660
5661
d29e330f
CD		 5662010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
5663"luxc1 f<FD>, r<INDEX>(r<BASE>)"
5664*mipsV:
5665*mips64:
e70cb6cd 5666*mips64r2:
d29e330f 5667{
d29e330f
CD		 5668 check_fpu (SD_);
5669 check_u64 (SD_, instruction_0);
8e394ffc 5670 do_luxc1_64 (SD_, FD, INDEX, BASE);
d29e330f
CD		 5671}
5672
c906108c 5673
4a0bd876 5674110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
c906108c 5675"lwc1 f<FT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 5676*mipsI:
5677*mipsII:
5678*mipsIII:
5679*mipsIV:
603a98e7 5680*mipsV:
1e799e28 5681*mips32:
e70cb6cd 5682*mips32r2:
1e799e28 5683*mips64:
e70cb6cd 5684*mips64r2:
c906108c
SS		 5685*vr4100:
5686*vr5000:
5687*r3900:
5688{
8e394ffc 5689 do_lwc1 (SD_, FT, OFFSET, BASE);
c906108c
SS		 5690}
5691
5692
60dc88db 5693010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32,f::LWXC1
c906108c
SS		 5694"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
5695*mipsIV:
603a98e7 5696*mipsV:
bfe9c90b 5697*mips32r2:
1e799e28 5698*mips64:
e70cb6cd 5699*mips64r2:
c906108c
SS		 5700*vr5000:
5701{
8e394ffc 5702 do_lwxc1 (SD_, FD, INDEX, BASE, instruction_0);
c906108c
SS		 5703}
5704
5705
5706
60dc88db 5707010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:32,f::MADD.fmt
f3c08b7e 5708"madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
c906108c 5709*mipsIV:
603a98e7 5710*mipsV:
bfe9c90b 5711*mips32r2:
1e799e28 5712*mips64:
e70cb6cd 5713*mips64r2:
c906108c
SS		 5714*vr5000:
5715{
8e394ffc 5716 do_madd_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
c906108c
SS		 5717}
5718
5719
cfe9ea23
CD		 5720010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
5721"mfc1 r<RT>, f<FS>"
c906108c
SS		 5722*mipsI:
5723*mipsII:
5724*mipsIII:
5725{
cfe9ea23 5726 unsigned64 v;
9b17d183 5727 check_fpu (SD_);
cfe9ea23
CD		 5728 v = EXTEND32 (FGR[FS]);
5729 PENDING_FILL (RT, v);
5730 TRACE_ALU_RESULT (v);
c906108c 5731}
cfe9ea23
CD		 5732
5733010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
5734"mfc1 r<RT>, f<FS>"
c906108c 5735*mipsIV:
603a98e7 5736*mipsV:
1e799e28 5737*mips32:
e70cb6cd 5738*mips32r2:
1e799e28 5739*mips64:
e70cb6cd 5740*mips64r2:
c906108c
SS		 5741*vr4100:
5742*vr5000:
5743*r3900:
cfe9ea23 5744{
8e394ffc 5745 do_mfc1b (SD_, RT, FS);
c906108c
SS		 5746}
5747
5748
14234056 5749010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
c906108c 5750"mov.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 5751*mipsI:
5752*mipsII:
5753*mipsIII:
5754*mipsIV:
603a98e7 5755*mipsV:
1e799e28 5756*mips32:
e70cb6cd 5757*mips32r2:
1e799e28 5758*mips64:
e70cb6cd 5759*mips64r2:
c906108c
SS		 5760*vr4100:
5761*vr5000:
5762*r3900:
5763{
8e394ffc 5764 do_mov_fmt (SD_, FMT, FD, FS, instruction_0);
c906108c
SS		 5765}
5766
5767
5768// MOVF
c2d11a7d 5769// MOVT
eb5fcf93 5770000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
c906108c
SS		 5771"mov%s<TF> r<RD>, r<RS>, <CC>"
5772*mipsIV:
603a98e7 5773*mipsV:
1e799e28 5774*mips32:
e70cb6cd 5775*mips32r2:
1e799e28 5776*mips64:
e70cb6cd 5777*mips64r2:
c906108c
SS		 5778*vr5000:
5779{
8e394ffc 5780 do_movtf (SD_, TF, RD, RS, CC);
c906108c
SS		 5781}
5782
5783
5784// MOVF.fmt
c2d11a7d 5785// MOVT.fmt
14234056 5786010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
c906108c
SS		 5787"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
5788*mipsIV:
603a98e7 5789*mipsV:
1e799e28 5790*mips32:
e70cb6cd 5791*mips32r2:
1e799e28 5792*mips64:
e70cb6cd 5793*mips64r2:
c906108c
SS		 5794*vr5000:
5795{
8e394ffc 5796 do_movtf_fmt (SD_, TF, FMT, FD, FS, CC);
c906108c
SS		 5797}
5798
5799
14234056 5800010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
80ee11fa 5801"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
c906108c 5802*mipsIV:
603a98e7 5803*mipsV:
1e799e28 5804*mips32:
e70cb6cd 5805*mips32r2:
1e799e28 5806*mips64:
e70cb6cd 5807*mips64r2:
c906108c
SS		 5808*vr5000:
5809{
8e394ffc 5810 do_movn_fmt (SD_, FMT, FD, FS, RT);
c906108c
SS		 5811}
5812
5813
5814// MOVT see MOVtf
5815
5816
5817// MOVT.fmt see MOVtf.fmt
5818
5819
5820
14234056 5821010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
c906108c
SS		 5822"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
5823*mipsIV:
603a98e7 5824*mipsV:
1e799e28 5825*mips32:
e70cb6cd 5826*mips32r2:
1e799e28 5827*mips64:
e70cb6cd 5828*mips64r2:
c906108c
SS		 5829*vr5000:
5830{
8e394ffc 5831 do_movz_fmt (SD_, FMT, FD, FS, RT);
c906108c
SS		 5832}
5833
5834
60dc88db 5835010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:32,f::MSUB.fmt
f3c08b7e 5836"msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
c906108c 5837*mipsIV:
603a98e7 5838*mipsV:
bfe9c90b 5839*mips32r2:
1e799e28 5840*mips64:
e70cb6cd 5841*mips64r2:
c906108c
SS		 5842*vr5000:
5843{
8e394ffc 5844 do_msub_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
c906108c
SS		 5845}
5846
5847
cfe9ea23
CD		 5848010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
5849"mtc1 r<RT>, f<FS>"
5850*mipsI:
5851*mipsII:
5852*mipsIII:
5853{
5854 check_fpu (SD_);
5855 if (SizeFGR () == 64)
5856 PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
5857 else
5858 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
5859 TRACE_FP_RESULT (GPR[RT]);
5860}
5861
5862010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
5863"mtc1 r<RT>, f<FS>"
5864*mipsIV:
5865*mipsV:
5866*mips32:
e70cb6cd 5867*mips32r2:
cfe9ea23 5868*mips64:
e70cb6cd 5869*mips64r2:
cfe9ea23
CD		 5870*vr4100:
5871*vr5000:
5872*r3900:
5873{
8e394ffc 5874 do_mtc1b (SD_, RT, FS);
cfe9ea23 5875}
c906108c
SS		 5876
5877
14234056 5878010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
c906108c 5879"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 5880*mipsI:
5881*mipsII:
5882*mipsIII:
5883*mipsIV:
603a98e7 5884*mipsV:
1e799e28 5885*mips32:
e70cb6cd 5886*mips32r2:
1e799e28 5887*mips64:
e70cb6cd 5888*mips64r2:
c906108c
SS		 5889*vr4100:
5890*vr5000:
5891*r3900:
5892{
8e394ffc 5893 do_mul_fmt (SD_, FMT, FD, FS, FT, instruction_0);
c906108c
SS		 5894}
5895
5896
14234056 5897010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
c906108c 5898"neg.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 5899*mipsI:
5900*mipsII:
5901*mipsIII:
5902*mipsIV:
603a98e7 5903*mipsV:
1e799e28 5904*mips32:
e70cb6cd 5905*mips32r2:
1e799e28 5906*mips64:
e70cb6cd 5907*mips64r2:
c906108c
SS		 5908*vr4100:
5909*vr5000:
5910*r3900:
5911{
8e394ffc 5912 do_neg_fmt (SD_, FMT, FD, FS, instruction_0);
c906108c
SS		 5913}
5914
5915
60dc88db 5916010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:32,f::NMADD.fmt
f3c08b7e 5917"nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
c906108c 5918*mipsIV:
603a98e7 5919*mipsV:
bfe9c90b 5920*mips32r2:
1e799e28 5921*mips64:
e70cb6cd 5922*mips64r2:
c906108c
SS		 5923*vr5000:
5924{
8e394ffc 5925 do_nmadd_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
c906108c
SS		 5926}
5927
5928
60dc88db 5929010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:32,f::NMSUB.fmt
f3c08b7e 5930"nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
c906108c 5931*mipsIV:
603a98e7 5932*mipsV:
bfe9c90b 5933*mips32r2:
1e799e28 5934*mips64:
e70cb6cd 5935*mips64r2:
c906108c
SS		 5936*vr5000:
5937{
8e394ffc 5938 do_nmsub_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
c906108c
SS		 5939}
5940
5941
60dc88db 5942010001,10,110,5.FT,5.FS,5.FD,101100:COP1:32,f::PLL.PS
3a2b820e
CD		 5943"pll.ps f<FD>, f<FS>, f<FT>"
5944*mipsV:
bfe9c90b 5945*mips32r2:
3a2b820e 5946*mips64:
e70cb6cd 5947*mips64r2:
3a2b820e 5948{
8e394ffc 5949 do_pll_ps (SD_, FD, FS, FT, instruction_0);
3a2b820e
CD		 5950}
5951
5952
60dc88db 5953010001,10,110,5.FT,5.FS,5.FD,101101:COP1:32,f::PLU.PS
3a2b820e
CD		 5954"plu.ps f<FD>, f<FS>, f<FT>"
5955*mipsV:
bfe9c90b 5956*mips32r2:
3a2b820e 5957*mips64:
e70cb6cd 5958*mips64r2:
3a2b820e 5959{
8e394ffc 5960 do_plu_ps (SD_, FD, FS, FT, instruction_0);
3a2b820e
CD		 5961}
5962
5963
60dc88db 5964010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX
c906108c
SS		 5965"prefx <HINT>, r<INDEX>(r<BASE>)"
5966*mipsIV:
603a98e7 5967*mipsV:
bfe9c90b 5968*mips32r2:
1e799e28 5969*mips64:
e70cb6cd 5970*mips64r2:
c906108c
SS		 5971*vr5000:
5972{
8e394ffc 5973 do_prefx (SD_, HINT, INDEX, BASE);
c906108c
SS		 5974}
5975
3a2b820e 5976
60dc88db 5977010001,10,110,5.FT,5.FS,5.FD,101110:COP1:32,f::PUL.PS
3a2b820e
CD		 5978"pul.ps f<FD>, f<FS>, f<FT>"
5979*mipsV:
bfe9c90b 5980*mips32r2:
3a2b820e 5981*mips64:
e70cb6cd 5982*mips64r2:
3a2b820e 5983{
8e394ffc 5984 do_pul_ps (SD_, FD, FS, FT, instruction_0);
3a2b820e
CD		 5985}
5986
5987
60dc88db 5988010001,10,110,5.FT,5.FS,5.FD,101111:COP1:32,f::PUU.PS
3a2b820e
CD		 5989"puu.ps f<FD>, f<FS>, f<FT>"
5990*mipsV:
bfe9c90b 5991*mips32r2:
3a2b820e 5992*mips64:
e70cb6cd 5993*mips64r2:
3a2b820e 5994{
8e394ffc 5995 do_puu_ps (SD_, FD, FS, FT, instruction_0);
3a2b820e
CD		 5996}
5997
5998
14234056 5999010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
c906108c 6000"recip.%s<FMT> f<FD>, f<FS>"
e514a9d6 6001*mipsIV:
603a98e7 6002*mipsV:
bfe9c90b 6003*mips32r2:
1e799e28 6004*mips64:
e70cb6cd 6005*mips64r2:
c906108c
SS		 6006*vr5000:
6007{
8e394ffc 6008 do_recip_fmt (SD_, FMT, FD, FS);
c906108c
SS		 6009}
6010
6011
60dc88db 6012010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:32,f::ROUND.L.fmt
c906108c
SS		 6013"round.l.%s<FMT> f<FD>, f<FS>"
6014*mipsIII:
6015*mipsIV:
603a98e7 6016*mipsV:
bfe9c90b 6017*mips32r2:
1e799e28 6018*mips64:
e70cb6cd 6019*mips64r2:
c906108c
SS		 6020*vr4100:
6021*vr5000:
6022*r3900:
6023{
8e394ffc 6024 do_round_fmt (SD_, fmt_long, FMT, FD, FS);
c906108c
SS		 6025}
6026
6027
14234056 6028010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
c906108c
SS		 6029"round.w.%s<FMT> f<FD>, f<FS>"
6030*mipsII:
6031*mipsIII:
6032*mipsIV:
603a98e7 6033*mipsV:
1e799e28 6034*mips32:
e70cb6cd 6035*mips32r2:
1e799e28 6036*mips64:
e70cb6cd 6037*mips64r2:
c906108c
SS		 6038*vr4100:
6039*vr5000:
6040*r3900:
6041{
8e394ffc 6042 do_round_fmt (SD_, fmt_word, FMT, FD, FS);
c906108c
SS		 6043}
6044
6045
14234056 6046010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
95fd5cee 6047"rsqrt.%s<FMT> f<FD>, f<FS>"
c906108c 6048*mipsIV:
603a98e7 6049*mipsV:
bfe9c90b 6050*mips32r2:
1e799e28 6051*mips64:
e70cb6cd 6052*mips64r2:
c906108c
SS		 6053*vr5000:
6054{
8e394ffc 6055 do_rsqrt_fmt (SD_, FMT, FD, FS);
c906108c
SS		 6056}
6057
6058
06e7837e 6059111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
c906108c
SS		 6060"sdc1 f<FT>, <OFFSET>(r<BASE>)"
6061*mipsII:
06e7837e 6062*mips32:
e70cb6cd 6063*mips32r2:
06e7837e 6064{
8e394ffc 6065 do_sdc1 (SD_, FT, OFFSET, BASE);
06e7837e
CD		 6066}
6067
6068
6069111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
6070"sdc1 f<FT>, <OFFSET>(r<BASE>)"
c906108c
SS		 6071*mipsIII:
6072*mipsIV:
603a98e7 6073*mipsV:
1e799e28 6074*mips64:
e70cb6cd 6075*mips64r2:
c906108c
SS		 6076*vr4100:
6077*vr5000:
6078*r3900:
6079{
9b17d183 6080 check_fpu (SD_);
c906108c
SS		 6081 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
6082}
6083
6084
60dc88db
RS		 6085010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1
6086"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
6087*mips32r2
6088{
6089 check_fpu (SD_);
6090 do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
6091}
6092
6093
eb5fcf93 6094010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
91a177cf 6095"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
c906108c 6096*mipsIV:
603a98e7 6097*mipsV:
1e799e28 6098*mips64:
e70cb6cd 6099*mips64r2:
c906108c
SS		 6100*vr5000:
6101{
9b17d183 6102 check_fpu (SD_);
ca971540 6103 check_u64 (SD_, instruction_0);
c906108c
SS		 6104 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
6105}
6106
6107
60dc88db
RS		 6108010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:32,f::SUXC1
6109"suxc1 f<FS>, r<INDEX>(r<BASE>)"
6110*mips32r2:
6111{
8e394ffc 6112 do_suxc1_32 (SD_, FS, INDEX, BASE);
60dc88db
RS		 6113}
6114
6115
d29e330f
CD		 6116010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
6117"suxc1 f<FS>, r<INDEX>(r<BASE>)"
6118*mipsV:
6119*mips64:
e70cb6cd 6120*mips64r2:
d29e330f 6121{
d29e330f
CD		 6122 check_fpu (SD_);
6123 check_u64 (SD_, instruction_0);
8e394ffc 6124 do_suxc1_64 (SD_, FS, INDEX, BASE);
d29e330f
CD		 6125}
6126
6127
14234056 6128010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
c906108c
SS		 6129"sqrt.%s<FMT> f<FD>, f<FS>"
6130*mipsII:
6131*mipsIII:
6132*mipsIV:
603a98e7 6133*mipsV:
1e799e28 6134*mips32:
e70cb6cd 6135*mips32r2:
1e799e28 6136*mips64:
e70cb6cd 6137*mips64r2:
c906108c
SS		 6138*vr4100:
6139*vr5000:
6140*r3900:
6141{
8e394ffc 6142 do_sqrt_fmt (SD_, FMT, FD, FS);
c906108c
SS		 6143}
6144
6145
14234056 6146010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
c906108c 6147"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 6148*mipsI:
6149*mipsII:
6150*mipsIII:
6151*mipsIV:
603a98e7 6152*mipsV:
1e799e28 6153*mips32:
e70cb6cd 6154*mips32r2:
1e799e28 6155*mips64:
e70cb6cd 6156*mips64r2:
c906108c
SS		 6157*vr4100:
6158*vr5000:
6159*r3900:
6160{
8e394ffc 6161 do_sub_fmt (SD_, FMT, FD, FS, FT, instruction_0);
c906108c
SS		 6162}
6163
6164
6165
eb5fcf93 6166111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
c906108c 6167"swc1 f<FT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 6168*mipsI:
6169*mipsII:
6170*mipsIII:
6171*mipsIV:
603a98e7 6172*mipsV:
1e799e28 6173*mips32:
e70cb6cd 6174*mips32r2:
1e799e28 6175*mips64:
e70cb6cd 6176*mips64r2:
c906108c
SS		 6177*vr4100:
6178*vr5000:
6179*r3900:
6180{
8e394ffc 6181 do_swc1 (SD_, FT, OFFSET, BASE, instruction_0);
c906108c
SS		 6182}
6183
6184
eb5fcf93 6185010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
c906108c
SS		 6186"swxc1 f<FS>, r<INDEX>(r<BASE>)"
6187*mipsIV:
603a98e7 6188*mipsV:
bfe9c90b 6189*mips32r2:
1e799e28 6190*mips64:
e70cb6cd 6191*mips64r2:
c906108c
SS		 6192*vr5000:
6193{
8e394ffc 6194 do_swxc1 (SD_, FS, INDEX, BASE, instruction_0);
c906108c
SS		 6195}
6196
6197
60dc88db 6198010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:32,f::TRUNC.L.fmt
c906108c
SS		 6199"trunc.l.%s<FMT> f<FD>, f<FS>"
6200*mipsIII:
6201*mipsIV:
603a98e7 6202*mipsV:
bfe9c90b 6203*mips32r2:
1e799e28 6204*mips64:
e70cb6cd 6205*mips64r2:
c906108c
SS		 6206*vr4100:
6207*vr5000:
6208*r3900:
6209{
8e394ffc 6210 do_trunc_fmt (SD_, fmt_long, FMT, FD, FS);
c906108c
SS		 6211}
6212
6213
14234056 6214010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
c906108c
SS		 6215"trunc.w.%s<FMT> f<FD>, f<FS>"
6216*mipsII:
6217*mipsIII:
6218*mipsIV:
603a98e7 6219*mipsV:
1e799e28 6220*mips32:
e70cb6cd 6221*mips32r2:
1e799e28 6222*mips64:
e70cb6cd 6223*mips64r2:
c906108c
SS		 6224*vr4100:
6225*vr5000:
6226*r3900:
6227{
8e394ffc 6228 do_trunc_fmt (SD_, fmt_word, FMT, FD, FS);
c906108c
SS		 6229}
6230
6231\f
6232//
6233// MIPS Architecture:
6234//
6235// System Control Instruction Set (COP0)
6236//
6237
6238
6239010000,01000,00000,16.OFFSET:COP0:32::BC0F
6240"bc0f <OFFSET>"
c5d00cc7
CD		 6241*mipsI:
6242*mipsII:
6243*mipsIII:
6244*mipsIV:
603a98e7 6245*mipsV:
1e799e28 6246*mips32:
e70cb6cd 6247*mips32r2:
1e799e28 6248*mips64:
e70cb6cd 6249*mips64r2:
c906108c
SS		 6250*vr4100:
6251*vr5000:
6252
7a292a7a
SS		 6253010000,01000,00000,16.OFFSET:COP0:32::BC0F
6254"bc0f <OFFSET>"
6255// stub needed for eCos as tx39 hardware bug workaround
6256*r3900:
6257{
6258 /* do nothing */
6259}
6260
c906108c
SS		 6261
6262010000,01000,00010,16.OFFSET:COP0:32::BC0FL
6263"bc0fl <OFFSET>"
c5d00cc7
CD		 6264*mipsI:
6265*mipsII:
6266*mipsIII:
6267*mipsIV:
603a98e7 6268*mipsV:
1e799e28 6269*mips32:
e70cb6cd 6270*mips32r2:
1e799e28 6271*mips64:
e70cb6cd 6272*mips64r2:
c906108c
SS		 6273*vr4100:
6274*vr5000:
6275
6276
6277010000,01000,00001,16.OFFSET:COP0:32::BC0T
6278"bc0t <OFFSET>"
c5d00cc7
CD		 6279*mipsI:
6280*mipsII:
6281*mipsIII:
6282*mipsIV:
603a98e7 6283*mipsV:
1e799e28 6284*mips32:
e70cb6cd 6285*mips32r2:
1e799e28 6286*mips64:
e70cb6cd 6287*mips64r2:
c906108c
SS		 6288*vr4100:
6289
6290
6291010000,01000,00011,16.OFFSET:COP0:32::BC0TL
6292"bc0tl <OFFSET>"
c5d00cc7
CD		 6293*mipsI:
6294*mipsII:
6295*mipsIII:
6296*mipsIV:
603a98e7 6297*mipsV:
1e799e28 6298*mips32:
e70cb6cd 6299*mips32r2:
1e799e28 6300*mips64:
e70cb6cd 6301*mips64r2:
c906108c
SS		 6302*vr4100:
6303*vr5000:
6304
6305
6306101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
0d3e762b 6307"cache <OP>, <OFFSET>(r<BASE>)"
c906108c
SS		 6308*mipsIII:
6309*mipsIV:
603a98e7 6310*mipsV:
1e799e28 6311*mips32:
e70cb6cd 6312*mips32r2:
1e799e28 6313*mips64:
e70cb6cd 6314*mips64r2:
c906108c
SS		 6315*vr4100:
6316*vr5000:
6317*r3900:
6318{
c1e8ada4
CD		 6319 address_word base = GPR[BASE];
6320 address_word offset = EXTEND16 (OFFSET);
c906108c 6321 {
09297648 6322 address_word vaddr = loadstore_ea (SD_, base, offset);
26f8bf63
MF		 6323 address_word paddr = vaddr;
6324 CacheOp(OP, vaddr, paddr, instruction_0);
c906108c
SS		 6325 }
6326}
6327
6328
8e394ffc 6329010000,00001,5.RT,5.RD,00000000,3.SEL:COP0:64::DMFC0
9846de1b 6330"dmfc0 r<RT>, r<RD>"
c5d00cc7
CD		 6331*mipsIII:
6332*mipsIV:
603a98e7 6333*mipsV:
1e799e28 6334*mips64:
e70cb6cd 6335*mips64r2:
9846de1b 6336{
ca971540 6337 check_u64 (SD_, instruction_0);
8e394ffc 6338 DecodeCoproc (instruction_0, 0, cp0_dmfc0, RT, RD, SEL);
9846de1b
JM		 6339}
6340
6341
8e394ffc 6342010000,00101,5.RT,5.RD,00000000,3.SEL:COP0:64::DMTC0
9846de1b 6343"dmtc0 r<RT>, r<RD>"
c5d00cc7
CD		 6344*mipsIII:
6345*mipsIV:
603a98e7 6346*mipsV:
1e799e28 6347*mips64:
e70cb6cd 6348*mips64r2:
9846de1b 6349{
ca971540 6350 check_u64 (SD_, instruction_0);
8e394ffc 6351 DecodeCoproc (instruction_0, 0, cp0_dmtc0, RT, RD, SEL);
9846de1b
JM		 6352}
6353
6354
f701dad2 6355010000,1,0000000000000000000,011000:COP0:32::ERET
c906108c
SS		 6356"eret"
6357*mipsIII:
6358*mipsIV:
603a98e7 6359*mipsV:
1e799e28 6360*mips32:
e70cb6cd 6361*mips32r2:
1e799e28 6362*mips64:
e70cb6cd 6363*mips64r2:
c906108c
SS		 6364*vr4100:
6365*vr5000:
6366{
6367 if (SR & status_ERL)
6368 {
6369 /* Oops, not yet available */
6370 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
6371 NIA = EPC;
6372 SR &= ~status_ERL;
6373 }
6374 else
6375 {
6376 NIA = EPC;
6377 SR &= ~status_EXL;
6378 }
6379}
6380
6381
8e394ffc
AB		 6382010000,00000,5.RT,5.RD,00000000,3.SEL:COP0:32::MFC0
6383"mfc0 r<RT>, r<RD> # <SEL>"
c5d00cc7
CD		 6384*mipsI:
6385*mipsII:
6386*mipsIII:
6387*mipsIV:
603a98e7 6388*mipsV:
1e799e28 6389*mips32:
e70cb6cd 6390*mips32r2:
1e799e28 6391*mips64:
e70cb6cd 6392*mips64r2:
c906108c
SS		 6393*vr4100:
6394*vr5000:
074e9cb8 6395*r3900:
c906108c
SS		 6396{
6397 TRACE_ALU_INPUT0 ();
8e394ffc 6398 DecodeCoproc (instruction_0, 0, cp0_mfc0, RT, RD, SEL);
c906108c
SS		 6399 TRACE_ALU_RESULT (GPR[RT]);
6400}
6401
8e394ffc
AB		 6402010000,00100,5.RT,5.RD,00000000,3.SEL:COP0:32::MTC0
6403"mtc0 r<RT>, r<RD> # <SEL>"
c5d00cc7
CD		 6404*mipsI:
6405*mipsII:
6406*mipsIII:
6407*mipsIV:
603a98e7 6408*mipsV:
1e799e28 6409*mips32:
e70cb6cd 6410*mips32r2:
1e799e28 6411*mips64:
e70cb6cd 6412*mips64r2:
c906108c
SS		 6413*vr4100:
6414*vr5000:
074e9cb8 6415*r3900:
c906108c 6416{
8e394ffc 6417 DecodeCoproc (instruction_0, 0, cp0_mtc0, RT, RD, SEL);
c906108c
SS		 6418}
6419
6420
f701dad2 6421010000,1,0000000000000000000,010000:COP0:32::RFE
c906108c 6422"rfe"
c5d00cc7
CD		 6423*mipsI:
6424*mipsII:
6425*mipsIII:
6426*mipsIV:
603a98e7 6427*mipsV:
c906108c
SS		 6428*vr4100:
6429*vr5000:
074e9cb8 6430*r3900:
c906108c 6431{
8e394ffc 6432 DecodeCoproc (instruction_0, 0, cp0_rfe, 0, 0, 0x10);
c906108c
SS		 6433}
6434
6435
64360100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
6437"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
c5d00cc7
CD		 6438*mipsI:
6439*mipsII:
6440*mipsIII:
6441*mipsIV:
603a98e7 6442*mipsV:
1e799e28 6443*mips32:
e70cb6cd 6444*mips32r2:
1e799e28 6445*mips64:
e70cb6cd 6446*mips64r2:
c906108c
SS		 6447*vr4100:
6448*r3900:
6449{
8e394ffc 6450 DecodeCoproc (instruction_0, 2, 0, 0, 0, 0);
c906108c
SS		 6451}
6452
6453
6454
f701dad2 6455010000,1,0000000000000000000,001000:COP0:32::TLBP
c906108c 6456"tlbp"
c5d00cc7
CD		 6457*mipsI:
6458*mipsII:
6459*mipsIII:
6460*mipsIV:
603a98e7 6461*mipsV:
1e799e28 6462*mips32:
e70cb6cd 6463*mips32r2:
1e799e28 6464*mips64:
e70cb6cd 6465*mips64r2:
c906108c
SS		 6466*vr4100:
6467*vr5000:
6468
6469
f701dad2 6470010000,1,0000000000000000000,000001:COP0:32::TLBR
c906108c 6471"tlbr"
c5d00cc7
CD		 6472*mipsI:
6473*mipsII:
6474*mipsIII:
6475*mipsIV:
603a98e7 6476*mipsV:
1e799e28 6477*mips32:
e70cb6cd 6478*mips32r2:
1e799e28 6479*mips64:
e70cb6cd 6480*mips64r2:
c906108c
SS		 6481*vr4100:
6482*vr5000:
6483
6484
f701dad2 6485010000,1,0000000000000000000,000010:COP0:32::TLBWI
c906108c 6486"tlbwi"
c5d00cc7
CD		 6487*mipsI:
6488*mipsII:
6489*mipsIII:
6490*mipsIV:
603a98e7 6491*mipsV:
1e799e28 6492*mips32:
e70cb6cd 6493*mips32r2:
1e799e28 6494*mips64:
e70cb6cd 6495*mips64r2:
c906108c
SS		 6496*vr4100:
6497*vr5000:
6498
6499
f701dad2 6500010000,1,0000000000000000000,000110:COP0:32::TLBWR
c906108c 6501"tlbwr"
c5d00cc7
CD		 6502*mipsI:
6503*mipsII:
6504*mipsIII:
6505*mipsIV:
603a98e7 6506*mipsV:
1e799e28 6507*mips32:
e70cb6cd 6508*mips32r2:
1e799e28 6509*mips64:
e70cb6cd 6510*mips64r2:
c906108c
SS		 6511*vr4100:
6512*vr5000:
6513
e70cb6cd
CD		 6514
6515:include:::mips3264r2.igen
c906108c 6516:include:::m16.igen
b16d63da 6517:include:::m16e.igen
f4f1b9f1 6518:include:::mdmx.igen
e7e81181 6519:include:::mips3d.igen
7cbea089 6520:include:::sb1.igen
c906108c
SS		 6521:include:::tx.igen
6522:include:::vr.igen
40a5538e 6523:include:::dsp.igen
8b082fb1 6524:include:::dsp2.igen
2d2733fc 6525:include:::smartmips.igen
8e394ffc
AB		 6526:include:::micromips.igen
6527:include:::micromipsdsp.igen
e70cb6cd 6528
GDB Binutils - Deliverables
This page took 1.315792 seconds and 4 git commands to generate.