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c906108c SS |
1 | // -*- C -*- |
2 | // | |
c906108c SS |
3 | // <insn> ::= |
4 | // <insn-word> { "+" <insn-word> } | |
5 | // ":" <format-name> | |
6 | // ":" <filter-flags> | |
7 | // ":" <options> | |
8 | // ":" <name> | |
9 | // <nl> | |
10 | // { <insn-model> } | |
11 | // { <insn-mnemonic> } | |
12 | // <code-block> | |
13 | // | |
14 | ||
15 | ||
16 | // IGEN config - mips16 | |
17 | // :option:16::insn-bit-size:16 | |
18 | // :option:16::hi-bit-nr:15 | |
19 | :option:16::insn-specifying-widths:true | |
20 | :option:16::gen-delayed-branch:false | |
21 | ||
22 | // IGEN config - mips32/64.. | |
23 | // :option:32::insn-bit-size:32 | |
24 | // :option:32::hi-bit-nr:31 | |
25 | :option:32::insn-specifying-widths:true | |
26 | :option:32::gen-delayed-branch:false | |
27 | ||
28 | ||
29 | // Generate separate simulators for each target | |
30 | // :option:::multi-sim:true | |
31 | ||
32 | ||
074e9cb8 | 33 | // Models known by this simulator are defined below. |
c5d00cc7 CD |
34 | // |
35 | // When placing models in the instruction descriptions, please place | |
36 | // them one per line, in the order given here. | |
074e9cb8 CD |
37 | |
38 | // MIPS ISAs: | |
39 | // | |
40 | // Instructions and related functions for these models are included in | |
41 | // this file. | |
c906108c SS |
42 | :model:::mipsI:mips3000: |
43 | :model:::mipsII:mips6000: | |
44 | :model:::mipsIII:mips4000: | |
45 | :model:::mipsIV:mips8000: | |
603a98e7 | 46 | :model:::mipsV:mipsisaV: |
1e799e28 CD |
47 | :model:::mips32:mipsisa32: |
48 | :model:::mips64:mipsisa64: | |
074e9cb8 CD |
49 | |
50 | // Vendor ISAs: | |
51 | // | |
52 | // Standard MIPS ISA instructions used for these models are listed here, | |
53 | // as are functions needed by those standard instructions. Instructions | |
54 | // which are model-dependent and which are not in the standard MIPS ISAs | |
55 | // (or which pre-date or use different encodings than the standard | |
56 | // instructions) are (for the most part) in separate .igen files. | |
57 | :model:::vr4100:mips4100: // vr.igen | |
c906108c | 58 | :model:::vr5000:mips5000: |
074e9cb8 | 59 | :model:::r3900:mips3900: // tx.igen |
c906108c | 60 | |
074e9cb8 CD |
61 | // MIPS Application Specific Extensions (ASEs) |
62 | // | |
63 | // Instructions for the ASEs are in separate .igen files. | |
f4f1b9f1 | 64 | // ASEs add instructions on to a base ISA. |
074e9cb8 | 65 | :model:::mips16:mips16: // m16.igen (and m16.dc) |
f4f1b9f1 | 66 | :model:::mdmx:mdmx: // mdmx.igen |
c906108c SS |
67 | |
68 | ||
69 | // Pseudo instructions known by IGEN | |
70 | :internal::::illegal: | |
71 | { | |
72 | SignalException (ReservedInstruction, 0); | |
73 | } | |
74 | ||
75 | ||
76 | // Pseudo instructions known by interp.c | |
77 | // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK | |
78 | 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD | |
79 | "rsvd <OP>" | |
80 | { | |
81 | SignalException (ReservedInstruction, instruction_0); | |
82 | } | |
83 | ||
84 | ||
85 | ||
86 | // Helper: | |
87 | // | |
88 | // Simulate a 32 bit delayslot instruction | |
89 | // | |
90 | ||
91 | :function:::address_word:delayslot32:address_word target | |
92 | { | |
93 | instruction_word delay_insn; | |
94 | sim_events_slip (SD, 1); | |
95 | DSPC = CIA; | |
96 | CIA = CIA + 4; /* NOTE not mips16 */ | |
97 | STATE |= simDELAYSLOT; | |
98 | delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ | |
d4f3574e | 99 | ENGINE_ISSUE_PREFIX_HOOK(); |
c906108c SS |
100 | idecode_issue (CPU_, delay_insn, (CIA)); |
101 | STATE &= ~simDELAYSLOT; | |
102 | return target; | |
103 | } | |
104 | ||
105 | :function:::address_word:nullify_next_insn32: | |
106 | { | |
107 | sim_events_slip (SD, 1); | |
108 | dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction"); | |
109 | return CIA + 8; | |
110 | } | |
111 | ||
09297648 CD |
112 | |
113 | // Helper: | |
114 | // | |
115 | // Calculate an effective address given a base and an offset. | |
116 | // | |
117 | ||
118 | :function:::address_word:loadstore_ea:address_word base, address_word offset | |
119 | *mipsI: | |
120 | *mipsII: | |
121 | *mipsIII: | |
122 | *mipsIV: | |
123 | *mipsV: | |
1e799e28 | 124 | *mips32: |
09297648 CD |
125 | *vr4100: |
126 | *vr5000: | |
127 | *r3900: | |
128 | { | |
129 | return base + offset; | |
130 | } | |
131 | ||
1e799e28 CD |
132 | :function:::address_word:loadstore_ea:address_word base, address_word offset |
133 | *mips64: | |
134 | { | |
135 | #if 0 /* XXX FIXME: enable this only after some additional testing. */ | |
136 | /* If in user mode and UX is not set, use 32-bit compatibility effective | |
137 | address computations as defined in the MIPS64 Architecture for | |
138 | Programmers Volume III, Revision 0.95, section 4.9. */ | |
139 | if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX)) | |
140 | == (ksu_user << status_KSU_shift)) | |
141 | return (address_word)((signed32)base + (signed32)offset); | |
142 | #endif | |
143 | return base + offset; | |
144 | } | |
145 | ||
09297648 | 146 | |
402586aa CD |
147 | // Helper: |
148 | // | |
149 | // Check that a 32-bit register value is properly sign-extended. | |
150 | // (See NotWordValue in ISA spec.) | |
151 | // | |
152 | ||
153 | :function:::int:not_word_value:unsigned_word value | |
154 | *mipsI: | |
155 | *mipsII: | |
156 | *mipsIII: | |
157 | *mipsIV: | |
158 | *mipsV: | |
159 | *vr4100: | |
160 | *vr5000: | |
161 | *r3900: | |
162 | { | |
163 | /* For historical simulator compatibility (until documentation is | |
164 | found that makes these operations unpredictable on some of these | |
165 | architectures), this check never returns true. */ | |
166 | return 0; | |
167 | } | |
168 | ||
169 | :function:::int:not_word_value:unsigned_word value | |
170 | *mips32: | |
171 | { | |
172 | /* On MIPS32, since registers are 32-bits, there's no check to be done. */ | |
173 | return 0; | |
174 | } | |
175 | ||
176 | :function:::int:not_word_value:unsigned_word value | |
177 | *mips64: | |
178 | { | |
179 | return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0)); | |
180 | } | |
181 | ||
182 | ||
183 | // Helper: | |
184 | // | |
185 | // Handle UNPREDICTABLE operation behaviour. The goal here is to prevent | |
186 | // theoretically portable code which invokes non-portable behaviour from | |
187 | // running with no indication of the portability issue. | |
188 | // (See definition of UNPREDICTABLE in ISA spec.) | |
189 | // | |
190 | ||
191 | :function:::void:unpredictable: | |
192 | *mipsI: | |
193 | *mipsII: | |
194 | *mipsIII: | |
195 | *mipsIV: | |
196 | *mipsV: | |
197 | *vr4100: | |
198 | *vr5000: | |
199 | *r3900: | |
200 | { | |
201 | } | |
202 | ||
203 | :function:::void:unpredictable: | |
204 | *mips32: | |
205 | *mips64: | |
206 | { | |
207 | unpredictable_action (CPU, CIA); | |
208 | } | |
209 | ||
210 | ||
c906108c | 211 | // Helper: |
4a0bd876 | 212 | // |
c906108c SS |
213 | // Check that an access to a HI/LO register meets timing requirements |
214 | // | |
215 | // The following requirements exist: | |
216 | // | |
217 | // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read | |
218 | // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read | |
219 | // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update | |
220 | // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}. | |
221 | // | |
222 | ||
223 | :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new | |
224 | { | |
225 | if (history->mf.timestamp + 3 > time) | |
226 | { | |
227 | sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n", | |
228 | itable[MY_INDEX].name, | |
229 | new, (long) CIA, | |
4a0bd876 | 230 | (long) history->mf.cia); |
c906108c SS |
231 | return 0; |
232 | } | |
233 | return 1; | |
234 | } | |
235 | ||
236 | :function:::int:check_mt_hilo:hilo_history *history | |
c5d00cc7 CD |
237 | *mipsI: |
238 | *mipsII: | |
239 | *mipsIII: | |
240 | *mipsIV: | |
603a98e7 | 241 | *mipsV: |
c906108c SS |
242 | *vr4100: |
243 | *vr5000: | |
244 | { | |
245 | signed64 time = sim_events_time (SD); | |
246 | int ok = check_mf_cycles (SD_, history, time, "MT"); | |
247 | history->mt.timestamp = time; | |
248 | history->mt.cia = CIA; | |
249 | return ok; | |
250 | } | |
251 | ||
252 | :function:::int:check_mt_hilo:hilo_history *history | |
1e799e28 CD |
253 | *mips32: |
254 | *mips64: | |
c906108c SS |
255 | *r3900: |
256 | { | |
257 | signed64 time = sim_events_time (SD); | |
258 | history->mt.timestamp = time; | |
259 | history->mt.cia = CIA; | |
260 | return 1; | |
261 | } | |
262 | ||
263 | ||
264 | :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer | |
c5d00cc7 CD |
265 | *mipsI: |
266 | *mipsII: | |
267 | *mipsIII: | |
268 | *mipsIV: | |
603a98e7 | 269 | *mipsV: |
1e799e28 CD |
270 | *mips32: |
271 | *mips64: | |
c906108c SS |
272 | *vr4100: |
273 | *vr5000: | |
274 | *r3900: | |
275 | { | |
276 | signed64 time = sim_events_time (SD); | |
277 | int ok = 1; | |
278 | if (peer != NULL | |
279 | && peer->mt.timestamp > history->op.timestamp | |
280 | && history->mt.timestamp < history->op.timestamp | |
281 | && ! (history->mf.timestamp > history->op.timestamp | |
282 | && history->mf.timestamp < peer->mt.timestamp) | |
283 | && ! (peer->mf.timestamp > history->op.timestamp | |
284 | && peer->mf.timestamp < peer->mt.timestamp)) | |
285 | { | |
286 | /* The peer has been written to since the last OP yet we have | |
287 | not */ | |
288 | sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n", | |
289 | itable[MY_INDEX].name, | |
290 | (long) CIA, | |
291 | (long) history->op.cia, | |
4a0bd876 | 292 | (long) peer->mt.cia); |
c906108c SS |
293 | ok = 0; |
294 | } | |
295 | history->mf.timestamp = time; | |
296 | history->mf.cia = CIA; | |
297 | return ok; | |
298 | } | |
299 | ||
300 | ||
301 | ||
302 | :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo | |
c5d00cc7 CD |
303 | *mipsI: |
304 | *mipsII: | |
305 | *mipsIII: | |
306 | *mipsIV: | |
603a98e7 | 307 | *mipsV: |
c906108c SS |
308 | *vr4100: |
309 | *vr5000: | |
310 | { | |
311 | signed64 time = sim_events_time (SD); | |
312 | int ok = (check_mf_cycles (SD_, hi, time, "OP") | |
313 | && check_mf_cycles (SD_, lo, time, "OP")); | |
314 | hi->op.timestamp = time; | |
315 | lo->op.timestamp = time; | |
316 | hi->op.cia = CIA; | |
317 | lo->op.cia = CIA; | |
318 | return ok; | |
319 | } | |
320 | ||
321 | // The r3900 mult and multu insns _can_ be exectuted immediatly after | |
322 | // a mf{hi,lo} | |
323 | :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo | |
1e799e28 CD |
324 | *mips32: |
325 | *mips64: | |
c906108c SS |
326 | *r3900: |
327 | { | |
328 | /* FIXME: could record the fact that a stall occured if we want */ | |
329 | signed64 time = sim_events_time (SD); | |
330 | hi->op.timestamp = time; | |
331 | lo->op.timestamp = time; | |
332 | hi->op.cia = CIA; | |
333 | lo->op.cia = CIA; | |
334 | return 1; | |
335 | } | |
336 | ||
337 | ||
338 | :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo | |
c5d00cc7 CD |
339 | *mipsI: |
340 | *mipsII: | |
341 | *mipsIII: | |
342 | *mipsIV: | |
603a98e7 | 343 | *mipsV: |
1e799e28 CD |
344 | *mips32: |
345 | *mips64: | |
c906108c SS |
346 | *vr4100: |
347 | *vr5000: | |
348 | *r3900: | |
349 | { | |
350 | signed64 time = sim_events_time (SD); | |
351 | int ok = (check_mf_cycles (SD_, hi, time, "OP") | |
352 | && check_mf_cycles (SD_, lo, time, "OP")); | |
353 | hi->op.timestamp = time; | |
354 | lo->op.timestamp = time; | |
355 | hi->op.cia = CIA; | |
356 | lo->op.cia = CIA; | |
357 | return ok; | |
358 | } | |
359 | ||
360 | ||
ca971540 | 361 | // Helper: |
4a0bd876 | 362 | // |
ca971540 | 363 | // Check that the 64-bit instruction can currently be used, and signal |
b5040d49 | 364 | // a ReservedInstruction exception if not. |
ca971540 CD |
365 | // |
366 | ||
367 | :function:::void:check_u64:instruction_word insn | |
368 | *mipsIII: | |
369 | *mipsIV: | |
370 | *mipsV: | |
371 | *vr4100: | |
372 | *vr5000: | |
373 | { | |
ca971540 CD |
374 | // The check should be similar to mips64 for any with PX/UX bit equivalents. |
375 | } | |
c906108c | 376 | |
1e799e28 CD |
377 | :function:::void:check_u64:instruction_word insn |
378 | *mips64: | |
379 | { | |
380 | #if 0 /* XXX FIXME: enable this only after some additional testing. */ | |
381 | if (UserMode && (SR & (status_UX|status_PX)) == 0) | |
382 | SignalException (ReservedInstruction, insn); | |
383 | #endif | |
384 | } | |
385 | ||
c906108c SS |
386 | |
387 | ||
388 | // | |
074e9cb8 | 389 | // MIPS Architecture: |
c906108c | 390 | // |
1e799e28 | 391 | // CPU Instruction Set (mipsI - mipsV, mips32, mips64) |
c906108c SS |
392 | // |
393 | ||
394 | ||
395 | ||
396 | 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD | |
397 | "add r<RD>, r<RS>, r<RT>" | |
c5d00cc7 CD |
398 | *mipsI: |
399 | *mipsII: | |
400 | *mipsIII: | |
401 | *mipsIV: | |
603a98e7 | 402 | *mipsV: |
1e799e28 CD |
403 | *mips32: |
404 | *mips64: | |
c906108c SS |
405 | *vr4100: |
406 | *vr5000: | |
407 | *r3900: | |
408 | { | |
402586aa CD |
409 | if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) |
410 | Unpredictable (); | |
c906108c SS |
411 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); |
412 | { | |
413 | ALU32_BEGIN (GPR[RS]); | |
414 | ALU32_ADD (GPR[RT]); | |
9805e229 | 415 | ALU32_END (GPR[RD]); /* This checks for overflow. */ |
c906108c SS |
416 | } |
417 | TRACE_ALU_RESULT (GPR[RD]); | |
418 | } | |
419 | ||
420 | ||
421 | ||
422 | 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI | |
20ae0098 | 423 | "addi r<RT>, r<RS>, <IMMEDIATE>" |
c5d00cc7 CD |
424 | *mipsI: |
425 | *mipsII: | |
426 | *mipsIII: | |
427 | *mipsIV: | |
603a98e7 | 428 | *mipsV: |
1e799e28 CD |
429 | *mips32: |
430 | *mips64: | |
c906108c SS |
431 | *vr4100: |
432 | *vr5000: | |
433 | *r3900: | |
434 | { | |
402586aa CD |
435 | if (NotWordValue (GPR[RS])) |
436 | Unpredictable (); | |
c906108c SS |
437 | TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE)); |
438 | { | |
439 | ALU32_BEGIN (GPR[RS]); | |
440 | ALU32_ADD (EXTEND16 (IMMEDIATE)); | |
9805e229 | 441 | ALU32_END (GPR[RT]); /* This checks for overflow. */ |
c906108c SS |
442 | } |
443 | TRACE_ALU_RESULT (GPR[RT]); | |
444 | } | |
445 | ||
446 | ||
447 | ||
448 | :function:::void:do_addiu:int rs, int rt, unsigned16 immediate | |
449 | { | |
402586aa CD |
450 | if (NotWordValue (GPR[rs])) |
451 | Unpredictable (); | |
c906108c SS |
452 | TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); |
453 | GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate)); | |
454 | TRACE_ALU_RESULT (GPR[rt]); | |
455 | } | |
456 | ||
457 | 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU | |
458 | "addiu r<RT>, r<RS>, <IMMEDIATE>" | |
c5d00cc7 CD |
459 | *mipsI: |
460 | *mipsII: | |
461 | *mipsIII: | |
462 | *mipsIV: | |
603a98e7 | 463 | *mipsV: |
1e799e28 CD |
464 | *mips32: |
465 | *mips64: | |
c906108c SS |
466 | *vr4100: |
467 | *vr5000: | |
468 | *r3900: | |
469 | { | |
470 | do_addiu (SD_, RS, RT, IMMEDIATE); | |
471 | } | |
472 | ||
473 | ||
474 | ||
475 | :function:::void:do_addu:int rs, int rt, int rd | |
476 | { | |
402586aa CD |
477 | if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
478 | Unpredictable (); | |
c906108c SS |
479 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
480 | GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]); | |
481 | TRACE_ALU_RESULT (GPR[rd]); | |
482 | } | |
483 | ||
484 | 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU | |
485 | "addu r<RD>, r<RS>, r<RT>" | |
c5d00cc7 CD |
486 | *mipsI: |
487 | *mipsII: | |
488 | *mipsIII: | |
489 | *mipsIV: | |
603a98e7 | 490 | *mipsV: |
1e799e28 CD |
491 | *mips32: |
492 | *mips64: | |
c906108c SS |
493 | *vr4100: |
494 | *vr5000: | |
495 | *r3900: | |
496 | { | |
497 | do_addu (SD_, RS, RT, RD); | |
498 | } | |
499 | ||
500 | ||
501 | ||
502 | :function:::void:do_and:int rs, int rt, int rd | |
503 | { | |
504 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
505 | GPR[rd] = GPR[rs] & GPR[rt]; | |
506 | TRACE_ALU_RESULT (GPR[rd]); | |
507 | } | |
508 | ||
509 | 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND | |
510 | "and r<RD>, r<RS>, r<RT>" | |
c5d00cc7 CD |
511 | *mipsI: |
512 | *mipsII: | |
513 | *mipsIII: | |
514 | *mipsIV: | |
603a98e7 | 515 | *mipsV: |
1e799e28 CD |
516 | *mips32: |
517 | *mips64: | |
c906108c SS |
518 | *vr4100: |
519 | *vr5000: | |
520 | *r3900: | |
521 | { | |
522 | do_and (SD_, RS, RT, RD); | |
523 | } | |
524 | ||
525 | ||
526 | ||
527 | 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI | |
82f728db | 528 | "andi r<RT>, r<RS>, %#lx<IMMEDIATE>" |
c5d00cc7 CD |
529 | *mipsI: |
530 | *mipsII: | |
531 | *mipsIII: | |
532 | *mipsIV: | |
603a98e7 | 533 | *mipsV: |
1e799e28 CD |
534 | *mips32: |
535 | *mips64: | |
c906108c SS |
536 | *vr4100: |
537 | *vr5000: | |
538 | *r3900: | |
539 | { | |
540 | TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE); | |
541 | GPR[RT] = GPR[RS] & IMMEDIATE; | |
542 | TRACE_ALU_RESULT (GPR[RT]); | |
543 | } | |
544 | ||
545 | ||
546 | ||
547 | 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ | |
548 | "beq r<RS>, r<RT>, <OFFSET>" | |
c5d00cc7 CD |
549 | *mipsI: |
550 | *mipsII: | |
551 | *mipsIII: | |
552 | *mipsIV: | |
603a98e7 | 553 | *mipsV: |
1e799e28 CD |
554 | *mips32: |
555 | *mips64: | |
c906108c SS |
556 | *vr4100: |
557 | *vr5000: | |
558 | *r3900: | |
559 | { | |
560 | address_word offset = EXTEND16 (OFFSET) << 2; | |
561 | check_branch_bug (); | |
562 | if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) | |
563 | { | |
564 | mark_branch_bug (NIA+offset); | |
565 | DELAY_SLOT (NIA + offset); | |
566 | } | |
567 | } | |
568 | ||
569 | ||
570 | ||
571 | 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL | |
572 | "beql r<RS>, r<RT>, <OFFSET>" | |
573 | *mipsII: | |
574 | *mipsIII: | |
575 | *mipsIV: | |
603a98e7 | 576 | *mipsV: |
1e799e28 CD |
577 | *mips32: |
578 | *mips64: | |
c906108c SS |
579 | *vr4100: |
580 | *vr5000: | |
581 | *r3900: | |
582 | { | |
583 | address_word offset = EXTEND16 (OFFSET) << 2; | |
584 | check_branch_bug (); | |
585 | if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) | |
586 | { | |
587 | mark_branch_bug (NIA+offset); | |
588 | DELAY_SLOT (NIA + offset); | |
589 | } | |
590 | else | |
591 | NULLIFY_NEXT_INSTRUCTION (); | |
592 | } | |
593 | ||
594 | ||
595 | ||
596 | 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ | |
597 | "bgez r<RS>, <OFFSET>" | |
c5d00cc7 CD |
598 | *mipsI: |
599 | *mipsII: | |
600 | *mipsIII: | |
601 | *mipsIV: | |
603a98e7 | 602 | *mipsV: |
1e799e28 CD |
603 | *mips32: |
604 | *mips64: | |
c906108c SS |
605 | *vr4100: |
606 | *vr5000: | |
607 | *r3900: | |
608 | { | |
609 | address_word offset = EXTEND16 (OFFSET) << 2; | |
610 | check_branch_bug (); | |
611 | if ((signed_word) GPR[RS] >= 0) | |
612 | { | |
613 | mark_branch_bug (NIA+offset); | |
614 | DELAY_SLOT (NIA + offset); | |
615 | } | |
616 | } | |
617 | ||
618 | ||
619 | ||
620 | 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL | |
621 | "bgezal r<RS>, <OFFSET>" | |
c5d00cc7 CD |
622 | *mipsI: |
623 | *mipsII: | |
624 | *mipsIII: | |
625 | *mipsIV: | |
603a98e7 | 626 | *mipsV: |
1e799e28 CD |
627 | *mips32: |
628 | *mips64: | |
c906108c SS |
629 | *vr4100: |
630 | *vr5000: | |
631 | *r3900: | |
632 | { | |
633 | address_word offset = EXTEND16 (OFFSET) << 2; | |
634 | check_branch_bug (); | |
402586aa CD |
635 | if (RS == 31) |
636 | Unpredictable (); | |
c906108c SS |
637 | RA = (CIA + 8); |
638 | if ((signed_word) GPR[RS] >= 0) | |
639 | { | |
640 | mark_branch_bug (NIA+offset); | |
641 | DELAY_SLOT (NIA + offset); | |
642 | } | |
643 | } | |
644 | ||
645 | ||
646 | ||
647 | 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL | |
648 | "bgezall r<RS>, <OFFSET>" | |
649 | *mipsII: | |
650 | *mipsIII: | |
651 | *mipsIV: | |
603a98e7 | 652 | *mipsV: |
1e799e28 CD |
653 | *mips32: |
654 | *mips64: | |
c906108c SS |
655 | *vr4100: |
656 | *vr5000: | |
657 | *r3900: | |
658 | { | |
659 | address_word offset = EXTEND16 (OFFSET) << 2; | |
660 | check_branch_bug (); | |
402586aa CD |
661 | if (RS == 31) |
662 | Unpredictable (); | |
c906108c SS |
663 | RA = (CIA + 8); |
664 | /* NOTE: The branch occurs AFTER the next instruction has been | |
665 | executed */ | |
666 | if ((signed_word) GPR[RS] >= 0) | |
667 | { | |
668 | mark_branch_bug (NIA+offset); | |
669 | DELAY_SLOT (NIA + offset); | |
670 | } | |
671 | else | |
672 | NULLIFY_NEXT_INSTRUCTION (); | |
673 | } | |
674 | ||
675 | ||
676 | ||
677 | 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL | |
678 | "bgezl r<RS>, <OFFSET>" | |
679 | *mipsII: | |
680 | *mipsIII: | |
681 | *mipsIV: | |
603a98e7 | 682 | *mipsV: |
1e799e28 CD |
683 | *mips32: |
684 | *mips64: | |
c906108c SS |
685 | *vr4100: |
686 | *vr5000: | |
687 | *r3900: | |
688 | { | |
689 | address_word offset = EXTEND16 (OFFSET) << 2; | |
690 | check_branch_bug (); | |
691 | if ((signed_word) GPR[RS] >= 0) | |
692 | { | |
693 | mark_branch_bug (NIA+offset); | |
694 | DELAY_SLOT (NIA + offset); | |
695 | } | |
696 | else | |
697 | NULLIFY_NEXT_INSTRUCTION (); | |
698 | } | |
699 | ||
700 | ||
701 | ||
702 | 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ | |
703 | "bgtz r<RS>, <OFFSET>" | |
c5d00cc7 CD |
704 | *mipsI: |
705 | *mipsII: | |
706 | *mipsIII: | |
707 | *mipsIV: | |
603a98e7 | 708 | *mipsV: |
1e799e28 CD |
709 | *mips32: |
710 | *mips64: | |
c906108c SS |
711 | *vr4100: |
712 | *vr5000: | |
713 | *r3900: | |
714 | { | |
715 | address_word offset = EXTEND16 (OFFSET) << 2; | |
716 | check_branch_bug (); | |
717 | if ((signed_word) GPR[RS] > 0) | |
718 | { | |
719 | mark_branch_bug (NIA+offset); | |
720 | DELAY_SLOT (NIA + offset); | |
721 | } | |
722 | } | |
723 | ||
724 | ||
725 | ||
726 | 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL | |
727 | "bgtzl r<RS>, <OFFSET>" | |
728 | *mipsII: | |
729 | *mipsIII: | |
730 | *mipsIV: | |
603a98e7 | 731 | *mipsV: |
1e799e28 CD |
732 | *mips32: |
733 | *mips64: | |
c906108c SS |
734 | *vr4100: |
735 | *vr5000: | |
736 | *r3900: | |
737 | { | |
738 | address_word offset = EXTEND16 (OFFSET) << 2; | |
739 | check_branch_bug (); | |
740 | /* NOTE: The branch occurs AFTER the next instruction has been | |
741 | executed */ | |
742 | if ((signed_word) GPR[RS] > 0) | |
743 | { | |
744 | mark_branch_bug (NIA+offset); | |
745 | DELAY_SLOT (NIA + offset); | |
746 | } | |
747 | else | |
748 | NULLIFY_NEXT_INSTRUCTION (); | |
749 | } | |
750 | ||
751 | ||
752 | ||
753 | 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ | |
754 | "blez r<RS>, <OFFSET>" | |
c5d00cc7 CD |
755 | *mipsI: |
756 | *mipsII: | |
757 | *mipsIII: | |
758 | *mipsIV: | |
603a98e7 | 759 | *mipsV: |
1e799e28 CD |
760 | *mips32: |
761 | *mips64: | |
c906108c SS |
762 | *vr4100: |
763 | *vr5000: | |
764 | *r3900: | |
765 | { | |
766 | address_word offset = EXTEND16 (OFFSET) << 2; | |
767 | check_branch_bug (); | |
768 | /* NOTE: The branch occurs AFTER the next instruction has been | |
769 | executed */ | |
770 | if ((signed_word) GPR[RS] <= 0) | |
771 | { | |
772 | mark_branch_bug (NIA+offset); | |
773 | DELAY_SLOT (NIA + offset); | |
774 | } | |
775 | } | |
776 | ||
777 | ||
778 | ||
779 | 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL | |
780 | "bgezl r<RS>, <OFFSET>" | |
781 | *mipsII: | |
782 | *mipsIII: | |
783 | *mipsIV: | |
603a98e7 | 784 | *mipsV: |
1e799e28 CD |
785 | *mips32: |
786 | *mips64: | |
c906108c SS |
787 | *vr4100: |
788 | *vr5000: | |
789 | *r3900: | |
790 | { | |
791 | address_word offset = EXTEND16 (OFFSET) << 2; | |
792 | check_branch_bug (); | |
793 | if ((signed_word) GPR[RS] <= 0) | |
794 | { | |
795 | mark_branch_bug (NIA+offset); | |
796 | DELAY_SLOT (NIA + offset); | |
797 | } | |
798 | else | |
799 | NULLIFY_NEXT_INSTRUCTION (); | |
800 | } | |
801 | ||
802 | ||
803 | ||
804 | 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ | |
805 | "bltz r<RS>, <OFFSET>" | |
c5d00cc7 CD |
806 | *mipsI: |
807 | *mipsII: | |
808 | *mipsIII: | |
809 | *mipsIV: | |
603a98e7 | 810 | *mipsV: |
1e799e28 CD |
811 | *mips32: |
812 | *mips64: | |
c906108c SS |
813 | *vr4100: |
814 | *vr5000: | |
815 | *r3900: | |
816 | { | |
817 | address_word offset = EXTEND16 (OFFSET) << 2; | |
818 | check_branch_bug (); | |
819 | if ((signed_word) GPR[RS] < 0) | |
820 | { | |
821 | mark_branch_bug (NIA+offset); | |
822 | DELAY_SLOT (NIA + offset); | |
823 | } | |
824 | } | |
825 | ||
826 | ||
827 | ||
828 | 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL | |
829 | "bltzal r<RS>, <OFFSET>" | |
c5d00cc7 CD |
830 | *mipsI: |
831 | *mipsII: | |
832 | *mipsIII: | |
833 | *mipsIV: | |
603a98e7 | 834 | *mipsV: |
1e799e28 CD |
835 | *mips32: |
836 | *mips64: | |
c906108c SS |
837 | *vr4100: |
838 | *vr5000: | |
839 | *r3900: | |
840 | { | |
841 | address_word offset = EXTEND16 (OFFSET) << 2; | |
842 | check_branch_bug (); | |
402586aa CD |
843 | if (RS == 31) |
844 | Unpredictable (); | |
c906108c SS |
845 | RA = (CIA + 8); |
846 | /* NOTE: The branch occurs AFTER the next instruction has been | |
847 | executed */ | |
848 | if ((signed_word) GPR[RS] < 0) | |
849 | { | |
850 | mark_branch_bug (NIA+offset); | |
851 | DELAY_SLOT (NIA + offset); | |
852 | } | |
853 | } | |
854 | ||
855 | ||
856 | ||
857 | 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL | |
858 | "bltzall r<RS>, <OFFSET>" | |
859 | *mipsII: | |
860 | *mipsIII: | |
861 | *mipsIV: | |
603a98e7 | 862 | *mipsV: |
1e799e28 CD |
863 | *mips32: |
864 | *mips64: | |
c906108c SS |
865 | *vr4100: |
866 | *vr5000: | |
867 | *r3900: | |
868 | { | |
869 | address_word offset = EXTEND16 (OFFSET) << 2; | |
870 | check_branch_bug (); | |
402586aa CD |
871 | if (RS == 31) |
872 | Unpredictable (); | |
c906108c SS |
873 | RA = (CIA + 8); |
874 | if ((signed_word) GPR[RS] < 0) | |
875 | { | |
876 | mark_branch_bug (NIA+offset); | |
877 | DELAY_SLOT (NIA + offset); | |
878 | } | |
879 | else | |
880 | NULLIFY_NEXT_INSTRUCTION (); | |
881 | } | |
882 | ||
883 | ||
884 | ||
885 | 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL | |
886 | "bltzl r<RS>, <OFFSET>" | |
887 | *mipsII: | |
888 | *mipsIII: | |
889 | *mipsIV: | |
603a98e7 | 890 | *mipsV: |
1e799e28 CD |
891 | *mips32: |
892 | *mips64: | |
c906108c SS |
893 | *vr4100: |
894 | *vr5000: | |
895 | *r3900: | |
896 | { | |
897 | address_word offset = EXTEND16 (OFFSET) << 2; | |
898 | check_branch_bug (); | |
899 | /* NOTE: The branch occurs AFTER the next instruction has been | |
900 | executed */ | |
901 | if ((signed_word) GPR[RS] < 0) | |
902 | { | |
903 | mark_branch_bug (NIA+offset); | |
904 | DELAY_SLOT (NIA + offset); | |
905 | } | |
906 | else | |
907 | NULLIFY_NEXT_INSTRUCTION (); | |
908 | } | |
909 | ||
910 | ||
911 | ||
912 | 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE | |
913 | "bne r<RS>, r<RT>, <OFFSET>" | |
c5d00cc7 CD |
914 | *mipsI: |
915 | *mipsII: | |
916 | *mipsIII: | |
917 | *mipsIV: | |
603a98e7 | 918 | *mipsV: |
1e799e28 CD |
919 | *mips32: |
920 | *mips64: | |
c906108c SS |
921 | *vr4100: |
922 | *vr5000: | |
923 | *r3900: | |
924 | { | |
925 | address_word offset = EXTEND16 (OFFSET) << 2; | |
926 | check_branch_bug (); | |
927 | if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) | |
928 | { | |
929 | mark_branch_bug (NIA+offset); | |
930 | DELAY_SLOT (NIA + offset); | |
931 | } | |
932 | } | |
933 | ||
934 | ||
935 | ||
936 | 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL | |
937 | "bnel r<RS>, r<RT>, <OFFSET>" | |
938 | *mipsII: | |
939 | *mipsIII: | |
940 | *mipsIV: | |
603a98e7 | 941 | *mipsV: |
1e799e28 CD |
942 | *mips32: |
943 | *mips64: | |
c906108c SS |
944 | *vr4100: |
945 | *vr5000: | |
946 | *r3900: | |
947 | { | |
948 | address_word offset = EXTEND16 (OFFSET) << 2; | |
949 | check_branch_bug (); | |
950 | if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) | |
951 | { | |
952 | mark_branch_bug (NIA+offset); | |
953 | DELAY_SLOT (NIA + offset); | |
954 | } | |
955 | else | |
956 | NULLIFY_NEXT_INSTRUCTION (); | |
957 | } | |
958 | ||
959 | ||
960 | ||
961 | 000000,20.CODE,001101:SPECIAL:32::BREAK | |
82f728db | 962 | "break %#lx<CODE>" |
c5d00cc7 CD |
963 | *mipsI: |
964 | *mipsII: | |
965 | *mipsIII: | |
966 | *mipsIV: | |
603a98e7 | 967 | *mipsV: |
1e799e28 CD |
968 | *mips32: |
969 | *mips64: | |
c906108c SS |
970 | *vr4100: |
971 | *vr5000: | |
972 | *r3900: | |
973 | { | |
974 | /* Check for some break instruction which are reserved for use by the simulator. */ | |
975 | unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK; | |
976 | if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) || | |
977 | break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) | |
978 | { | |
979 | sim_engine_halt (SD, CPU, NULL, cia, | |
980 | sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); | |
981 | } | |
982 | else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) || | |
983 | break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) | |
984 | { | |
985 | if (STATE & simDELAYSLOT) | |
986 | PC = cia - 4; /* reference the branch instruction */ | |
987 | else | |
988 | PC = cia; | |
86b77b47 | 989 | SignalException (BreakPoint, instruction_0); |
c906108c SS |
990 | } |
991 | ||
992 | else | |
993 | { | |
4a0bd876 | 994 | /* If we get this far, we're not an instruction reserved by the sim. Raise |
c906108c | 995 | the exception. */ |
86b77b47 | 996 | SignalException (BreakPoint, instruction_0); |
c906108c SS |
997 | } |
998 | } | |
999 | ||
1000 | ||
1001 | ||
1e799e28 CD |
1002 | 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO |
1003 | "clo r<RD>, r<RS>" | |
1004 | *mips32: | |
1005 | *mips64: | |
1006 | { | |
1007 | unsigned32 temp = GPR[RS]; | |
1008 | unsigned32 i, mask; | |
1009 | if (RT != RD) | |
c9b9995a | 1010 | Unpredictable (); |
402586aa CD |
1011 | if (NotWordValue (GPR[RS])) |
1012 | Unpredictable (); | |
1e799e28 CD |
1013 | TRACE_ALU_INPUT1 (GPR[RS]); |
1014 | for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i) | |
1015 | { | |
1016 | if ((temp & mask) == 0) | |
1017 | break; | |
1018 | mask >>= 1; | |
1019 | } | |
1020 | GPR[RD] = EXTEND32 (i); | |
1021 | TRACE_ALU_RESULT (GPR[RD]); | |
1022 | } | |
1023 | ||
1024 | ||
1025 | ||
1026 | 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ | |
1027 | "clz r<RD>, r<RS>" | |
1028 | *mips32: | |
1029 | *mips64: | |
1030 | { | |
1031 | unsigned32 temp = GPR[RS]; | |
1032 | unsigned32 i, mask; | |
1033 | if (RT != RD) | |
c9b9995a | 1034 | Unpredictable (); |
402586aa CD |
1035 | if (NotWordValue (GPR[RS])) |
1036 | Unpredictable (); | |
1e799e28 CD |
1037 | TRACE_ALU_INPUT1 (GPR[RS]); |
1038 | for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i) | |
1039 | { | |
1040 | if ((temp & mask) != 0) | |
1041 | break; | |
1042 | mask >>= 1; | |
1043 | } | |
1044 | GPR[RD] = EXTEND32 (i); | |
1045 | TRACE_ALU_RESULT (GPR[RD]); | |
1046 | } | |
1047 | ||
1048 | ||
1049 | ||
c906108c SS |
1050 | 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD |
1051 | "dadd r<RD>, r<RS>, r<RT>" | |
1052 | *mipsIII: | |
1053 | *mipsIV: | |
603a98e7 | 1054 | *mipsV: |
1e799e28 | 1055 | *mips64: |
c906108c SS |
1056 | *vr4100: |
1057 | *vr5000: | |
1058 | { | |
ca971540 | 1059 | check_u64 (SD_, instruction_0); |
c906108c SS |
1060 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); |
1061 | { | |
1062 | ALU64_BEGIN (GPR[RS]); | |
1063 | ALU64_ADD (GPR[RT]); | |
9805e229 | 1064 | ALU64_END (GPR[RD]); /* This checks for overflow. */ |
c906108c SS |
1065 | } |
1066 | TRACE_ALU_RESULT (GPR[RD]); | |
1067 | } | |
1068 | ||
1069 | ||
1070 | ||
1071 | 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI | |
1072 | "daddi r<RT>, r<RS>, <IMMEDIATE>" | |
1073 | *mipsIII: | |
1074 | *mipsIV: | |
603a98e7 | 1075 | *mipsV: |
1e799e28 | 1076 | *mips64: |
c906108c SS |
1077 | *vr4100: |
1078 | *vr5000: | |
1079 | { | |
ca971540 | 1080 | check_u64 (SD_, instruction_0); |
c906108c SS |
1081 | TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE)); |
1082 | { | |
1083 | ALU64_BEGIN (GPR[RS]); | |
1084 | ALU64_ADD (EXTEND16 (IMMEDIATE)); | |
9805e229 | 1085 | ALU64_END (GPR[RT]); /* This checks for overflow. */ |
c906108c SS |
1086 | } |
1087 | TRACE_ALU_RESULT (GPR[RT]); | |
1088 | } | |
1089 | ||
1090 | ||
1091 | ||
1092 | :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate | |
1093 | { | |
1094 | TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); | |
1095 | GPR[rt] = GPR[rs] + EXTEND16 (immediate); | |
1096 | TRACE_ALU_RESULT (GPR[rt]); | |
1097 | } | |
1098 | ||
1099 | 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU | |
20ae0098 | 1100 | "daddiu r<RT>, r<RS>, <IMMEDIATE>" |
c906108c SS |
1101 | *mipsIII: |
1102 | *mipsIV: | |
603a98e7 | 1103 | *mipsV: |
1e799e28 | 1104 | *mips64: |
c906108c SS |
1105 | *vr4100: |
1106 | *vr5000: | |
1107 | { | |
ca971540 | 1108 | check_u64 (SD_, instruction_0); |
c906108c SS |
1109 | do_daddiu (SD_, RS, RT, IMMEDIATE); |
1110 | } | |
1111 | ||
1112 | ||
1113 | ||
1114 | :function:::void:do_daddu:int rs, int rt, int rd | |
1115 | { | |
1116 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
1117 | GPR[rd] = GPR[rs] + GPR[rt]; | |
1118 | TRACE_ALU_RESULT (GPR[rd]); | |
1119 | } | |
1120 | ||
1121 | 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU | |
1122 | "daddu r<RD>, r<RS>, r<RT>" | |
1123 | *mipsIII: | |
1124 | *mipsIV: | |
603a98e7 | 1125 | *mipsV: |
1e799e28 | 1126 | *mips64: |
c906108c SS |
1127 | *vr4100: |
1128 | *vr5000: | |
1129 | { | |
ca971540 | 1130 | check_u64 (SD_, instruction_0); |
c906108c SS |
1131 | do_daddu (SD_, RS, RT, RD); |
1132 | } | |
1133 | ||
1134 | ||
1135 | ||
1e799e28 CD |
1136 | 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO |
1137 | "dclo r<RD>, r<RS>" | |
1138 | *mips64: | |
1139 | { | |
1140 | unsigned64 temp = GPR[RS]; | |
1141 | unsigned32 i; | |
1142 | unsigned64 mask; | |
1143 | check_u64 (SD_, instruction_0); | |
1144 | if (RT != RD) | |
c9b9995a | 1145 | Unpredictable (); |
1e799e28 CD |
1146 | TRACE_ALU_INPUT1 (GPR[RS]); |
1147 | for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i) | |
1148 | { | |
1149 | if ((temp & mask) == 0) | |
1150 | break; | |
1151 | mask >>= 1; | |
1152 | } | |
1153 | GPR[RD] = EXTEND32 (i); | |
1154 | TRACE_ALU_RESULT (GPR[RD]); | |
1155 | } | |
1156 | ||
1157 | ||
1158 | ||
1159 | 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ | |
1160 | "dclz r<RD>, r<RS>" | |
1161 | *mips64: | |
1162 | { | |
1163 | unsigned64 temp = GPR[RS]; | |
1164 | unsigned32 i; | |
1165 | unsigned64 mask; | |
1166 | check_u64 (SD_, instruction_0); | |
1167 | if (RT != RD) | |
c9b9995a | 1168 | Unpredictable (); |
1e799e28 CD |
1169 | TRACE_ALU_INPUT1 (GPR[RS]); |
1170 | for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i) | |
1171 | { | |
1172 | if ((temp & mask) != 0) | |
1173 | break; | |
1174 | mask >>= 1; | |
1175 | } | |
1176 | GPR[RD] = EXTEND32 (i); | |
1177 | TRACE_ALU_RESULT (GPR[RD]); | |
1178 | } | |
1179 | ||
1180 | ||
1181 | ||
c906108c SS |
1182 | :function:::void:do_ddiv:int rs, int rt |
1183 | { | |
1184 | check_div_hilo (SD_, HIHISTORY, LOHISTORY); | |
1185 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
1186 | { | |
1187 | signed64 n = GPR[rs]; | |
1188 | signed64 d = GPR[rt]; | |
1189 | signed64 hi; | |
1190 | signed64 lo; | |
1191 | if (d == 0) | |
1192 | { | |
1193 | lo = SIGNED64 (0x8000000000000000); | |
1194 | hi = 0; | |
1195 | } | |
1196 | else if (d == -1 && n == SIGNED64 (0x8000000000000000)) | |
1197 | { | |
1198 | lo = SIGNED64 (0x8000000000000000); | |
1199 | hi = 0; | |
1200 | } | |
1201 | else | |
1202 | { | |
1203 | lo = (n / d); | |
1204 | hi = (n % d); | |
1205 | } | |
1206 | HI = hi; | |
1207 | LO = lo; | |
1208 | } | |
1209 | TRACE_ALU_RESULT2 (HI, LO); | |
1210 | } | |
1211 | ||
f701dad2 | 1212 | 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV |
c906108c SS |
1213 | "ddiv r<RS>, r<RT>" |
1214 | *mipsIII: | |
1215 | *mipsIV: | |
603a98e7 | 1216 | *mipsV: |
1e799e28 | 1217 | *mips64: |
c906108c SS |
1218 | *vr4100: |
1219 | *vr5000: | |
1220 | { | |
ca971540 | 1221 | check_u64 (SD_, instruction_0); |
c906108c SS |
1222 | do_ddiv (SD_, RS, RT); |
1223 | } | |
1224 | ||
1225 | ||
1226 | ||
1227 | :function:::void:do_ddivu:int rs, int rt | |
1228 | { | |
1229 | check_div_hilo (SD_, HIHISTORY, LOHISTORY); | |
1230 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
1231 | { | |
1232 | unsigned64 n = GPR[rs]; | |
1233 | unsigned64 d = GPR[rt]; | |
1234 | unsigned64 hi; | |
1235 | unsigned64 lo; | |
1236 | if (d == 0) | |
1237 | { | |
1238 | lo = SIGNED64 (0x8000000000000000); | |
1239 | hi = 0; | |
1240 | } | |
1241 | else | |
1242 | { | |
1243 | lo = (n / d); | |
1244 | hi = (n % d); | |
1245 | } | |
1246 | HI = hi; | |
1247 | LO = lo; | |
1248 | } | |
1249 | TRACE_ALU_RESULT2 (HI, LO); | |
1250 | } | |
1251 | ||
1252 | 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU | |
1253 | "ddivu r<RS>, r<RT>" | |
1254 | *mipsIII: | |
1255 | *mipsIV: | |
603a98e7 | 1256 | *mipsV: |
1e799e28 | 1257 | *mips64: |
c906108c SS |
1258 | *vr4100: |
1259 | *vr5000: | |
1260 | { | |
ca971540 | 1261 | check_u64 (SD_, instruction_0); |
c906108c SS |
1262 | do_ddivu (SD_, RS, RT); |
1263 | } | |
1264 | ||
1265 | ||
1266 | ||
1267 | :function:::void:do_div:int rs, int rt | |
1268 | { | |
1269 | check_div_hilo (SD_, HIHISTORY, LOHISTORY); | |
1270 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
1271 | { | |
1272 | signed32 n = GPR[rs]; | |
1273 | signed32 d = GPR[rt]; | |
1274 | if (d == 0) | |
1275 | { | |
1276 | LO = EXTEND32 (0x80000000); | |
1277 | HI = EXTEND32 (0); | |
1278 | } | |
1279 | else if (n == SIGNED32 (0x80000000) && d == -1) | |
1280 | { | |
1281 | LO = EXTEND32 (0x80000000); | |
1282 | HI = EXTEND32 (0); | |
1283 | } | |
1284 | else | |
1285 | { | |
1286 | LO = EXTEND32 (n / d); | |
1287 | HI = EXTEND32 (n % d); | |
1288 | } | |
1289 | } | |
1290 | TRACE_ALU_RESULT2 (HI, LO); | |
1291 | } | |
1292 | ||
f701dad2 | 1293 | 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV |
c906108c | 1294 | "div r<RS>, r<RT>" |
c5d00cc7 CD |
1295 | *mipsI: |
1296 | *mipsII: | |
1297 | *mipsIII: | |
1298 | *mipsIV: | |
603a98e7 | 1299 | *mipsV: |
1e799e28 CD |
1300 | *mips32: |
1301 | *mips64: | |
c906108c SS |
1302 | *vr4100: |
1303 | *vr5000: | |
1304 | *r3900: | |
1305 | { | |
1306 | do_div (SD_, RS, RT); | |
1307 | } | |
1308 | ||
1309 | ||
1310 | ||
1311 | :function:::void:do_divu:int rs, int rt | |
1312 | { | |
1313 | check_div_hilo (SD_, HIHISTORY, LOHISTORY); | |
1314 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
1315 | { | |
1316 | unsigned32 n = GPR[rs]; | |
1317 | unsigned32 d = GPR[rt]; | |
1318 | if (d == 0) | |
1319 | { | |
1320 | LO = EXTEND32 (0x80000000); | |
1321 | HI = EXTEND32 (0); | |
1322 | } | |
3e1dca16 CD |
1323 | else |
1324 | { | |
1325 | LO = EXTEND32 (n / d); | |
1326 | HI = EXTEND32 (n % d); | |
1327 | } | |
c906108c SS |
1328 | } |
1329 | TRACE_ALU_RESULT2 (HI, LO); | |
1330 | } | |
1331 | ||
f701dad2 | 1332 | 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU |
c906108c | 1333 | "divu r<RS>, r<RT>" |
c5d00cc7 CD |
1334 | *mipsI: |
1335 | *mipsII: | |
1336 | *mipsIII: | |
1337 | *mipsIV: | |
603a98e7 | 1338 | *mipsV: |
1e799e28 CD |
1339 | *mips32: |
1340 | *mips64: | |
c906108c SS |
1341 | *vr4100: |
1342 | *vr5000: | |
1343 | *r3900: | |
1344 | { | |
1345 | do_divu (SD_, RS, RT); | |
1346 | } | |
1347 | ||
1348 | ||
1349 | ||
1350 | :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p | |
1351 | { | |
1352 | unsigned64 lo; | |
1353 | unsigned64 hi; | |
1354 | unsigned64 m00; | |
1355 | unsigned64 m01; | |
1356 | unsigned64 m10; | |
1357 | unsigned64 m11; | |
1358 | unsigned64 mid; | |
1359 | int sign; | |
1360 | unsigned64 op1 = GPR[rs]; | |
1361 | unsigned64 op2 = GPR[rt]; | |
1362 | check_mult_hilo (SD_, HIHISTORY, LOHISTORY); | |
1363 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
4a0bd876 | 1364 | /* make signed multiply unsigned */ |
c906108c SS |
1365 | sign = 0; |
1366 | if (signed_p) | |
1367 | { | |
1368 | if (op1 < 0) | |
1369 | { | |
1370 | op1 = - op1; | |
1371 | ++sign; | |
1372 | } | |
1373 | if (op2 < 0) | |
1374 | { | |
1375 | op2 = - op2; | |
1376 | ++sign; | |
1377 | } | |
1378 | } | |
67f5c7ef | 1379 | /* multiply out the 4 sub products */ |
c906108c SS |
1380 | m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2)); |
1381 | m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2)); | |
1382 | m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2)); | |
1383 | m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2)); | |
1384 | /* add the products */ | |
1385 | mid = ((unsigned64) VH4_8 (m00) | |
1386 | + (unsigned64) VL4_8 (m10) | |
1387 | + (unsigned64) VL4_8 (m01)); | |
1388 | lo = U8_4 (mid, m00); | |
1389 | hi = (m11 | |
1390 | + (unsigned64) VH4_8 (mid) | |
1391 | + (unsigned64) VH4_8 (m01) | |
1392 | + (unsigned64) VH4_8 (m10)); | |
1393 | /* fix the sign */ | |
1394 | if (sign & 1) | |
1395 | { | |
1396 | lo = -lo; | |
1397 | if (lo == 0) | |
1398 | hi = -hi; | |
1399 | else | |
1400 | hi = -hi - 1; | |
1401 | } | |
1402 | /* save the result HI/LO (and a gpr) */ | |
1403 | LO = lo; | |
1404 | HI = hi; | |
1405 | if (rd != 0) | |
1406 | GPR[rd] = lo; | |
1407 | TRACE_ALU_RESULT2 (HI, LO); | |
1408 | } | |
1409 | ||
1410 | :function:::void:do_dmult:int rs, int rt, int rd | |
1411 | { | |
1412 | do_dmultx (SD_, rs, rt, rd, 1); | |
1413 | } | |
1414 | ||
f701dad2 | 1415 | 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT |
c906108c | 1416 | "dmult r<RS>, r<RT>" |
c5d00cc7 CD |
1417 | *mipsIII: |
1418 | *mipsIV: | |
603a98e7 | 1419 | *mipsV: |
1e799e28 | 1420 | *mips64: |
c906108c SS |
1421 | *vr4100: |
1422 | { | |
ca971540 | 1423 | check_u64 (SD_, instruction_0); |
c906108c SS |
1424 | do_dmult (SD_, RS, RT, 0); |
1425 | } | |
1426 | ||
f701dad2 | 1427 | 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT |
c906108c SS |
1428 | "dmult r<RS>, r<RT>":RD == 0 |
1429 | "dmult r<RD>, r<RS>, r<RT>" | |
1430 | *vr5000: | |
1431 | { | |
ca971540 | 1432 | check_u64 (SD_, instruction_0); |
c906108c SS |
1433 | do_dmult (SD_, RS, RT, RD); |
1434 | } | |
1435 | ||
1436 | ||
1437 | ||
1438 | :function:::void:do_dmultu:int rs, int rt, int rd | |
1439 | { | |
1440 | do_dmultx (SD_, rs, rt, rd, 0); | |
1441 | } | |
1442 | ||
f701dad2 | 1443 | 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU |
c906108c | 1444 | "dmultu r<RS>, r<RT>" |
c5d00cc7 CD |
1445 | *mipsIII: |
1446 | *mipsIV: | |
603a98e7 | 1447 | *mipsV: |
1e799e28 | 1448 | *mips64: |
c906108c SS |
1449 | *vr4100: |
1450 | { | |
ca971540 | 1451 | check_u64 (SD_, instruction_0); |
c906108c SS |
1452 | do_dmultu (SD_, RS, RT, 0); |
1453 | } | |
1454 | ||
f701dad2 | 1455 | 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU |
c906108c SS |
1456 | "dmultu r<RD>, r<RS>, r<RT>":RD == 0 |
1457 | "dmultu r<RS>, r<RT>" | |
1458 | *vr5000: | |
1459 | { | |
ca971540 | 1460 | check_u64 (SD_, instruction_0); |
c906108c SS |
1461 | do_dmultu (SD_, RS, RT, RD); |
1462 | } | |
1463 | ||
1464 | :function:::void:do_dsll:int rt, int rd, int shift | |
1465 | { | |
fff8d27d | 1466 | TRACE_ALU_INPUT2 (GPR[rt], shift); |
c906108c | 1467 | GPR[rd] = GPR[rt] << shift; |
fff8d27d | 1468 | TRACE_ALU_RESULT (GPR[rd]); |
c906108c SS |
1469 | } |
1470 | ||
f701dad2 | 1471 | 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL |
c906108c SS |
1472 | "dsll r<RD>, r<RT>, <SHIFT>" |
1473 | *mipsIII: | |
1474 | *mipsIV: | |
603a98e7 | 1475 | *mipsV: |
1e799e28 | 1476 | *mips64: |
c906108c SS |
1477 | *vr4100: |
1478 | *vr5000: | |
1479 | { | |
ca971540 | 1480 | check_u64 (SD_, instruction_0); |
c906108c SS |
1481 | do_dsll (SD_, RT, RD, SHIFT); |
1482 | } | |
1483 | ||
1484 | ||
f701dad2 | 1485 | 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32 |
c906108c SS |
1486 | "dsll32 r<RD>, r<RT>, <SHIFT>" |
1487 | *mipsIII: | |
1488 | *mipsIV: | |
603a98e7 | 1489 | *mipsV: |
1e799e28 | 1490 | *mips64: |
c906108c SS |
1491 | *vr4100: |
1492 | *vr5000: | |
1493 | { | |
1494 | int s = 32 + SHIFT; | |
ca971540 | 1495 | check_u64 (SD_, instruction_0); |
fff8d27d | 1496 | TRACE_ALU_INPUT2 (GPR[RT], s); |
c906108c | 1497 | GPR[RD] = GPR[RT] << s; |
fff8d27d | 1498 | TRACE_ALU_RESULT (GPR[RD]); |
c906108c SS |
1499 | } |
1500 | ||
3e1dca16 CD |
1501 | :function:::void:do_dsllv:int rs, int rt, int rd |
1502 | { | |
1503 | int s = MASKED64 (GPR[rs], 5, 0); | |
1504 | TRACE_ALU_INPUT2 (GPR[rt], s); | |
1505 | GPR[rd] = GPR[rt] << s; | |
1506 | TRACE_ALU_RESULT (GPR[rd]); | |
1507 | } | |
1508 | ||
f701dad2 | 1509 | 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV |
c906108c SS |
1510 | "dsllv r<RD>, r<RT>, r<RS>" |
1511 | *mipsIII: | |
1512 | *mipsIV: | |
603a98e7 | 1513 | *mipsV: |
1e799e28 | 1514 | *mips64: |
c906108c SS |
1515 | *vr4100: |
1516 | *vr5000: | |
1517 | { | |
ca971540 | 1518 | check_u64 (SD_, instruction_0); |
c906108c SS |
1519 | do_dsllv (SD_, RS, RT, RD); |
1520 | } | |
1521 | ||
1522 | :function:::void:do_dsra:int rt, int rd, int shift | |
1523 | { | |
fff8d27d | 1524 | TRACE_ALU_INPUT2 (GPR[rt], shift); |
c906108c | 1525 | GPR[rd] = ((signed64) GPR[rt]) >> shift; |
fff8d27d | 1526 | TRACE_ALU_RESULT (GPR[rd]); |
c906108c SS |
1527 | } |
1528 | ||
1529 | ||
f701dad2 | 1530 | 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA |
c906108c SS |
1531 | "dsra r<RD>, r<RT>, <SHIFT>" |
1532 | *mipsIII: | |
1533 | *mipsIV: | |
603a98e7 | 1534 | *mipsV: |
1e799e28 | 1535 | *mips64: |
c906108c SS |
1536 | *vr4100: |
1537 | *vr5000: | |
1538 | { | |
ca971540 | 1539 | check_u64 (SD_, instruction_0); |
c906108c SS |
1540 | do_dsra (SD_, RT, RD, SHIFT); |
1541 | } | |
1542 | ||
1543 | ||
f701dad2 | 1544 | 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32 |
bb22bd7d | 1545 | "dsra32 r<RD>, r<RT>, <SHIFT>" |
c906108c SS |
1546 | *mipsIII: |
1547 | *mipsIV: | |
603a98e7 | 1548 | *mipsV: |
1e799e28 | 1549 | *mips64: |
c906108c SS |
1550 | *vr4100: |
1551 | *vr5000: | |
1552 | { | |
1553 | int s = 32 + SHIFT; | |
ca971540 | 1554 | check_u64 (SD_, instruction_0); |
fff8d27d | 1555 | TRACE_ALU_INPUT2 (GPR[RT], s); |
c906108c | 1556 | GPR[RD] = ((signed64) GPR[RT]) >> s; |
fff8d27d | 1557 | TRACE_ALU_RESULT (GPR[RD]); |
c906108c SS |
1558 | } |
1559 | ||
1560 | ||
1561 | :function:::void:do_dsrav:int rs, int rt, int rd | |
1562 | { | |
1563 | int s = MASKED64 (GPR[rs], 5, 0); | |
1564 | TRACE_ALU_INPUT2 (GPR[rt], s); | |
1565 | GPR[rd] = ((signed64) GPR[rt]) >> s; | |
1566 | TRACE_ALU_RESULT (GPR[rd]); | |
1567 | } | |
1568 | ||
f701dad2 | 1569 | 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV |
bb22bd7d | 1570 | "dsrav r<RD>, r<RT>, r<RS>" |
c906108c SS |
1571 | *mipsIII: |
1572 | *mipsIV: | |
603a98e7 | 1573 | *mipsV: |
1e799e28 | 1574 | *mips64: |
c906108c SS |
1575 | *vr4100: |
1576 | *vr5000: | |
1577 | { | |
ca971540 | 1578 | check_u64 (SD_, instruction_0); |
c906108c SS |
1579 | do_dsrav (SD_, RS, RT, RD); |
1580 | } | |
1581 | ||
1582 | :function:::void:do_dsrl:int rt, int rd, int shift | |
1583 | { | |
fff8d27d | 1584 | TRACE_ALU_INPUT2 (GPR[rt], shift); |
c906108c | 1585 | GPR[rd] = (unsigned64) GPR[rt] >> shift; |
fff8d27d | 1586 | TRACE_ALU_RESULT (GPR[rd]); |
c906108c SS |
1587 | } |
1588 | ||
1589 | ||
f701dad2 | 1590 | 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL |
c906108c SS |
1591 | "dsrl r<RD>, r<RT>, <SHIFT>" |
1592 | *mipsIII: | |
1593 | *mipsIV: | |
603a98e7 | 1594 | *mipsV: |
1e799e28 | 1595 | *mips64: |
c906108c SS |
1596 | *vr4100: |
1597 | *vr5000: | |
1598 | { | |
ca971540 | 1599 | check_u64 (SD_, instruction_0); |
c906108c SS |
1600 | do_dsrl (SD_, RT, RD, SHIFT); |
1601 | } | |
1602 | ||
1603 | ||
f701dad2 | 1604 | 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32 |
c906108c SS |
1605 | "dsrl32 r<RD>, r<RT>, <SHIFT>" |
1606 | *mipsIII: | |
1607 | *mipsIV: | |
603a98e7 | 1608 | *mipsV: |
1e799e28 | 1609 | *mips64: |
c906108c SS |
1610 | *vr4100: |
1611 | *vr5000: | |
1612 | { | |
1613 | int s = 32 + SHIFT; | |
ca971540 | 1614 | check_u64 (SD_, instruction_0); |
fff8d27d | 1615 | TRACE_ALU_INPUT2 (GPR[RT], s); |
c906108c | 1616 | GPR[RD] = (unsigned64) GPR[RT] >> s; |
fff8d27d | 1617 | TRACE_ALU_RESULT (GPR[RD]); |
c906108c SS |
1618 | } |
1619 | ||
1620 | ||
1621 | :function:::void:do_dsrlv:int rs, int rt, int rd | |
1622 | { | |
1623 | int s = MASKED64 (GPR[rs], 5, 0); | |
fff8d27d | 1624 | TRACE_ALU_INPUT2 (GPR[rt], s); |
c906108c | 1625 | GPR[rd] = (unsigned64) GPR[rt] >> s; |
fff8d27d | 1626 | TRACE_ALU_RESULT (GPR[rd]); |
c906108c SS |
1627 | } |
1628 | ||
1629 | ||
1630 | ||
f701dad2 | 1631 | 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV |
20ae0098 | 1632 | "dsrlv r<RD>, r<RT>, r<RS>" |
c906108c SS |
1633 | *mipsIII: |
1634 | *mipsIV: | |
603a98e7 | 1635 | *mipsV: |
1e799e28 | 1636 | *mips64: |
c906108c SS |
1637 | *vr4100: |
1638 | *vr5000: | |
1639 | { | |
ca971540 | 1640 | check_u64 (SD_, instruction_0); |
c906108c SS |
1641 | do_dsrlv (SD_, RS, RT, RD); |
1642 | } | |
1643 | ||
1644 | ||
f701dad2 | 1645 | 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB |
c906108c SS |
1646 | "dsub r<RD>, r<RS>, r<RT>" |
1647 | *mipsIII: | |
1648 | *mipsIV: | |
603a98e7 | 1649 | *mipsV: |
1e799e28 | 1650 | *mips64: |
c906108c SS |
1651 | *vr4100: |
1652 | *vr5000: | |
1653 | { | |
ca971540 | 1654 | check_u64 (SD_, instruction_0); |
c906108c SS |
1655 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); |
1656 | { | |
1657 | ALU64_BEGIN (GPR[RS]); | |
1658 | ALU64_SUB (GPR[RT]); | |
9805e229 | 1659 | ALU64_END (GPR[RD]); /* This checks for overflow. */ |
c906108c SS |
1660 | } |
1661 | TRACE_ALU_RESULT (GPR[RD]); | |
1662 | } | |
1663 | ||
1664 | ||
1665 | :function:::void:do_dsubu:int rs, int rt, int rd | |
1666 | { | |
1667 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
1668 | GPR[rd] = GPR[rs] - GPR[rt]; | |
1669 | TRACE_ALU_RESULT (GPR[rd]); | |
1670 | } | |
1671 | ||
f701dad2 | 1672 | 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU |
c906108c SS |
1673 | "dsubu r<RD>, r<RS>, r<RT>" |
1674 | *mipsIII: | |
1675 | *mipsIV: | |
603a98e7 | 1676 | *mipsV: |
1e799e28 | 1677 | *mips64: |
c906108c SS |
1678 | *vr4100: |
1679 | *vr5000: | |
1680 | { | |
ca971540 | 1681 | check_u64 (SD_, instruction_0); |
c906108c SS |
1682 | do_dsubu (SD_, RS, RT, RD); |
1683 | } | |
1684 | ||
1685 | ||
1686 | 000010,26.INSTR_INDEX:NORMAL:32::J | |
1687 | "j <INSTR_INDEX>" | |
c5d00cc7 CD |
1688 | *mipsI: |
1689 | *mipsII: | |
1690 | *mipsIII: | |
1691 | *mipsIV: | |
603a98e7 | 1692 | *mipsV: |
1e799e28 CD |
1693 | *mips32: |
1694 | *mips64: | |
c906108c SS |
1695 | *vr4100: |
1696 | *vr5000: | |
1697 | *r3900: | |
1698 | { | |
1699 | /* NOTE: The region used is that of the delay slot NIA and NOT the | |
1700 | current instruction */ | |
1701 | address_word region = (NIA & MASK (63, 28)); | |
1702 | DELAY_SLOT (region | (INSTR_INDEX << 2)); | |
1703 | } | |
1704 | ||
1705 | ||
1706 | 000011,26.INSTR_INDEX:NORMAL:32::JAL | |
1707 | "jal <INSTR_INDEX>" | |
c5d00cc7 CD |
1708 | *mipsI: |
1709 | *mipsII: | |
1710 | *mipsIII: | |
1711 | *mipsIV: | |
603a98e7 | 1712 | *mipsV: |
1e799e28 CD |
1713 | *mips32: |
1714 | *mips64: | |
c906108c SS |
1715 | *vr4100: |
1716 | *vr5000: | |
1717 | *r3900: | |
1718 | { | |
1719 | /* NOTE: The region used is that of the delay slot and NOT the | |
1720 | current instruction */ | |
1721 | address_word region = (NIA & MASK (63, 28)); | |
1722 | GPR[31] = CIA + 8; | |
1723 | DELAY_SLOT (region | (INSTR_INDEX << 2)); | |
1724 | } | |
1725 | ||
f701dad2 | 1726 | 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR |
c906108c SS |
1727 | "jalr r<RS>":RD == 31 |
1728 | "jalr r<RD>, r<RS>" | |
c5d00cc7 CD |
1729 | *mipsI: |
1730 | *mipsII: | |
1731 | *mipsIII: | |
1732 | *mipsIV: | |
603a98e7 | 1733 | *mipsV: |
1e799e28 CD |
1734 | *mips32: |
1735 | *mips64: | |
c906108c SS |
1736 | *vr4100: |
1737 | *vr5000: | |
1738 | *r3900: | |
1739 | { | |
1740 | address_word temp = GPR[RS]; | |
1741 | GPR[RD] = CIA + 8; | |
1742 | DELAY_SLOT (temp); | |
1743 | } | |
1744 | ||
1745 | ||
f701dad2 | 1746 | 000000,5.RS,000000000000000,001000:SPECIAL:32::JR |
c906108c | 1747 | "jr r<RS>" |
c5d00cc7 CD |
1748 | *mipsI: |
1749 | *mipsII: | |
1750 | *mipsIII: | |
1751 | *mipsIV: | |
603a98e7 | 1752 | *mipsV: |
1e799e28 CD |
1753 | *mips32: |
1754 | *mips64: | |
c906108c SS |
1755 | *vr4100: |
1756 | *vr5000: | |
1757 | *r3900: | |
1758 | { | |
1759 | DELAY_SLOT (GPR[RS]); | |
1760 | } | |
1761 | ||
1762 | ||
1763 | :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset | |
1764 | { | |
1765 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); | |
1766 | address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); | |
1767 | address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); | |
1768 | unsigned int byte; | |
1769 | address_word paddr; | |
1770 | int uncached; | |
1771 | unsigned64 memval; | |
1772 | address_word vaddr; | |
1773 | ||
09297648 | 1774 | vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
1775 | if ((vaddr & access) != 0) |
1776 | { | |
1777 | SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal); | |
1778 | } | |
1779 | AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); | |
1780 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); | |
1781 | LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL); | |
1782 | byte = ((vaddr & mask) ^ bigendiancpu); | |
1783 | return (memval >> (8 * byte)); | |
1784 | } | |
1785 | ||
1c47a468 CD |
1786 | :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt |
1787 | { | |
1788 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); | |
1789 | address_word reverseendian = (ReverseEndian ? -1 : 0); | |
1790 | address_word bigendiancpu = (BigEndianCPU ? -1 : 0); | |
1791 | unsigned int byte; | |
1792 | unsigned int word; | |
1793 | address_word paddr; | |
1794 | int uncached; | |
1795 | unsigned64 memval; | |
1796 | address_word vaddr; | |
1797 | int nr_lhs_bits; | |
1798 | int nr_rhs_bits; | |
1799 | unsigned_word lhs_mask; | |
1800 | unsigned_word temp; | |
1801 | ||
09297648 | 1802 | vaddr = loadstore_ea (SD_, base, offset); |
1c47a468 CD |
1803 | AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); |
1804 | paddr = (paddr ^ (reverseendian & mask)); | |
1805 | if (BigEndianMem == 0) | |
1806 | paddr = paddr & ~access; | |
1807 | ||
1808 | /* compute where within the word/mem we are */ | |
1809 | byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */ | |
1810 | word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */ | |
1811 | nr_lhs_bits = 8 * byte + 8; | |
1812 | nr_rhs_bits = 8 * access - 8 * byte; | |
1813 | /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ | |
1814 | ||
1815 | /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", | |
1816 | (long) ((unsigned64) vaddr >> 32), (long) vaddr, | |
1817 | (long) ((unsigned64) paddr >> 32), (long) paddr, | |
1818 | word, byte, nr_lhs_bits, nr_rhs_bits); */ | |
1819 | ||
1820 | LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL); | |
1821 | if (word == 0) | |
1822 | { | |
1823 | /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */ | |
1824 | temp = (memval << nr_rhs_bits); | |
1825 | } | |
1826 | else | |
1827 | { | |
1828 | /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */ | |
1829 | temp = (memval >> nr_lhs_bits); | |
1830 | } | |
1831 | lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits); | |
1832 | rt = (rt & ~lhs_mask) | (temp & lhs_mask); | |
1833 | ||
1834 | /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n", | |
1835 | (long) ((unsigned64) memval >> 32), (long) memval, | |
1836 | (long) ((unsigned64) temp >> 32), (long) temp, | |
1837 | (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask, | |
1838 | (long) (rt >> 32), (long) rt); */ | |
1839 | return rt; | |
1840 | } | |
1841 | ||
1842 | :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt | |
1843 | { | |
1844 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); | |
1845 | address_word reverseendian = (ReverseEndian ? -1 : 0); | |
1846 | address_word bigendiancpu = (BigEndianCPU ? -1 : 0); | |
1847 | unsigned int byte; | |
1848 | address_word paddr; | |
1849 | int uncached; | |
1850 | unsigned64 memval; | |
1851 | address_word vaddr; | |
1852 | ||
09297648 | 1853 | vaddr = loadstore_ea (SD_, base, offset); |
1c47a468 CD |
1854 | AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); |
1855 | /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */ | |
1856 | paddr = (paddr ^ (reverseendian & mask)); | |
1857 | if (BigEndianMem != 0) | |
1858 | paddr = paddr & ~access; | |
1859 | byte = ((vaddr & mask) ^ (bigendiancpu & mask)); | |
1860 | /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */ | |
1861 | LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL); | |
1862 | /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n", | |
1863 | (long) paddr, byte, (long) paddr, (long) memval); */ | |
1864 | { | |
1865 | unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0); | |
1866 | rt &= ~screen; | |
1867 | rt |= (memval >> (8 * byte)) & screen; | |
1868 | } | |
1869 | return rt; | |
1870 | } | |
1871 | ||
c906108c SS |
1872 | |
1873 | 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB | |
1874 | "lb r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
1875 | *mipsI: |
1876 | *mipsII: | |
1877 | *mipsIII: | |
1878 | *mipsIV: | |
603a98e7 | 1879 | *mipsV: |
1e799e28 CD |
1880 | *mips32: |
1881 | *mips64: | |
c906108c SS |
1882 | *vr4100: |
1883 | *vr5000: | |
1884 | *r3900: | |
1885 | { | |
1886 | GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET))); | |
1887 | } | |
1888 | ||
1889 | ||
1890 | 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU | |
1891 | "lbu r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
1892 | *mipsI: |
1893 | *mipsII: | |
1894 | *mipsIII: | |
1895 | *mipsIV: | |
603a98e7 | 1896 | *mipsV: |
1e799e28 CD |
1897 | *mips32: |
1898 | *mips64: | |
c906108c SS |
1899 | *vr4100: |
1900 | *vr5000: | |
1901 | *r3900: | |
1902 | { | |
1903 | GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)); | |
1904 | } | |
1905 | ||
1906 | ||
1907 | 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD | |
1908 | "ld r<RT>, <OFFSET>(r<BASE>)" | |
1909 | *mipsIII: | |
1910 | *mipsIV: | |
603a98e7 | 1911 | *mipsV: |
1e799e28 | 1912 | *mips64: |
c906108c SS |
1913 | *vr4100: |
1914 | *vr5000: | |
1915 | { | |
ca971540 | 1916 | check_u64 (SD_, instruction_0); |
c906108c SS |
1917 | GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); |
1918 | } | |
1919 | ||
1920 | ||
1921 | 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz | |
1922 | "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)" | |
1923 | *mipsII: | |
1924 | *mipsIII: | |
1925 | *mipsIV: | |
603a98e7 | 1926 | *mipsV: |
1e799e28 CD |
1927 | *mips32: |
1928 | *mips64: | |
c906108c SS |
1929 | *vr4100: |
1930 | *vr5000: | |
1931 | *r3900: | |
1932 | { | |
1933 | COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); | |
1934 | } | |
1935 | ||
1936 | ||
1937 | ||
1938 | ||
1939 | 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL | |
1940 | "ldl r<RT>, <OFFSET>(r<BASE>)" | |
1941 | *mipsIII: | |
1942 | *mipsIV: | |
603a98e7 | 1943 | *mipsV: |
1e799e28 | 1944 | *mips64: |
c906108c SS |
1945 | *vr4100: |
1946 | *vr5000: | |
1947 | { | |
ca971540 | 1948 | check_u64 (SD_, instruction_0); |
c906108c SS |
1949 | GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
1950 | } | |
1951 | ||
1952 | ||
1953 | 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR | |
1954 | "ldr r<RT>, <OFFSET>(r<BASE>)" | |
1955 | *mipsIII: | |
1956 | *mipsIV: | |
603a98e7 | 1957 | *mipsV: |
1e799e28 | 1958 | *mips64: |
c906108c SS |
1959 | *vr4100: |
1960 | *vr5000: | |
1961 | { | |
ca971540 | 1962 | check_u64 (SD_, instruction_0); |
c906108c SS |
1963 | GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
1964 | } | |
1965 | ||
1966 | ||
1967 | 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH | |
1968 | "lh r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
1969 | *mipsI: |
1970 | *mipsII: | |
1971 | *mipsIII: | |
1972 | *mipsIV: | |
603a98e7 | 1973 | *mipsV: |
1e799e28 CD |
1974 | *mips32: |
1975 | *mips64: | |
c906108c SS |
1976 | *vr4100: |
1977 | *vr5000: | |
1978 | *r3900: | |
1979 | { | |
1980 | GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET))); | |
1981 | } | |
1982 | ||
1983 | ||
1984 | 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU | |
1985 | "lhu r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
1986 | *mipsI: |
1987 | *mipsII: | |
1988 | *mipsIII: | |
1989 | *mipsIV: | |
603a98e7 | 1990 | *mipsV: |
1e799e28 CD |
1991 | *mips32: |
1992 | *mips64: | |
c906108c SS |
1993 | *vr4100: |
1994 | *vr5000: | |
1995 | *r3900: | |
1996 | { | |
1997 | GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)); | |
1998 | } | |
1999 | ||
2000 | ||
2001 | 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL | |
2002 | "ll r<RT>, <OFFSET>(r<BASE>)" | |
2003 | *mipsII: | |
2004 | *mipsIII: | |
2005 | *mipsIV: | |
603a98e7 | 2006 | *mipsV: |
1e799e28 CD |
2007 | *mips32: |
2008 | *mips64: | |
c906108c SS |
2009 | *vr4100: |
2010 | *vr5000: | |
2011 | { | |
c1e8ada4 CD |
2012 | address_word base = GPR[BASE]; |
2013 | address_word offset = EXTEND16 (OFFSET); | |
c906108c | 2014 | { |
09297648 | 2015 | address_word vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
2016 | address_word paddr; |
2017 | int uncached; | |
2018 | if ((vaddr & 3) != 0) | |
2019 | { | |
2020 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal); | |
2021 | } | |
2022 | else | |
2023 | { | |
2024 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
2025 | { | |
2026 | unsigned64 memval = 0; | |
2027 | unsigned64 memval1 = 0; | |
2028 | unsigned64 mask = 0x7; | |
2029 | unsigned int shift = 2; | |
2030 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
2031 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
2032 | unsigned int byte; | |
2033 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
2034 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
2035 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
043b7057 | 2036 | GPR[RT] = EXTEND32 (memval >> (8 * byte)); |
c906108c SS |
2037 | LLBIT = 1; |
2038 | } | |
2039 | } | |
2040 | } | |
2041 | } | |
2042 | ||
2043 | ||
2044 | 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD | |
2045 | "lld r<RT>, <OFFSET>(r<BASE>)" | |
2046 | *mipsIII: | |
2047 | *mipsIV: | |
603a98e7 | 2048 | *mipsV: |
1e799e28 | 2049 | *mips64: |
c906108c SS |
2050 | *vr4100: |
2051 | *vr5000: | |
2052 | { | |
c1e8ada4 CD |
2053 | address_word base = GPR[BASE]; |
2054 | address_word offset = EXTEND16 (OFFSET); | |
ca971540 | 2055 | check_u64 (SD_, instruction_0); |
c906108c | 2056 | { |
09297648 | 2057 | address_word vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
2058 | address_word paddr; |
2059 | int uncached; | |
2060 | if ((vaddr & 7) != 0) | |
2061 | { | |
2062 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal); | |
2063 | } | |
2064 | else | |
2065 | { | |
2066 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
2067 | { | |
2068 | unsigned64 memval = 0; | |
2069 | unsigned64 memval1 = 0; | |
2070 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); | |
c1e8ada4 | 2071 | GPR[RT] = memval; |
c906108c SS |
2072 | LLBIT = 1; |
2073 | } | |
2074 | } | |
2075 | } | |
2076 | } | |
2077 | ||
2078 | ||
2079 | 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI | |
82f728db | 2080 | "lui r<RT>, %#lx<IMMEDIATE>" |
c5d00cc7 CD |
2081 | *mipsI: |
2082 | *mipsII: | |
2083 | *mipsIII: | |
2084 | *mipsIV: | |
603a98e7 | 2085 | *mipsV: |
1e799e28 CD |
2086 | *mips32: |
2087 | *mips64: | |
c906108c SS |
2088 | *vr4100: |
2089 | *vr5000: | |
2090 | *r3900: | |
2091 | { | |
2092 | TRACE_ALU_INPUT1 (IMMEDIATE); | |
2093 | GPR[RT] = EXTEND32 (IMMEDIATE << 16); | |
2094 | TRACE_ALU_RESULT (GPR[RT]); | |
2095 | } | |
2096 | ||
2097 | ||
2098 | 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW | |
2099 | "lw r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
2100 | *mipsI: |
2101 | *mipsII: | |
2102 | *mipsIII: | |
2103 | *mipsIV: | |
603a98e7 | 2104 | *mipsV: |
1e799e28 CD |
2105 | *mips32: |
2106 | *mips64: | |
c906108c SS |
2107 | *vr4100: |
2108 | *vr5000: | |
2109 | *r3900: | |
2110 | { | |
2111 | GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); | |
2112 | } | |
2113 | ||
2114 | ||
2115 | 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz | |
2116 | "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
2117 | *mipsI: |
2118 | *mipsII: | |
2119 | *mipsIII: | |
2120 | *mipsIV: | |
603a98e7 | 2121 | *mipsV: |
1e799e28 CD |
2122 | *mips32: |
2123 | *mips64: | |
c906108c SS |
2124 | *vr4100: |
2125 | *vr5000: | |
2126 | *r3900: | |
2127 | { | |
2128 | COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); | |
2129 | } | |
2130 | ||
2131 | ||
c906108c SS |
2132 | 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL |
2133 | "lwl r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
2134 | *mipsI: |
2135 | *mipsII: | |
2136 | *mipsIII: | |
2137 | *mipsIV: | |
603a98e7 | 2138 | *mipsV: |
1e799e28 CD |
2139 | *mips32: |
2140 | *mips64: | |
c906108c SS |
2141 | *vr4100: |
2142 | *vr5000: | |
2143 | *r3900: | |
2144 | { | |
7a292a7a | 2145 | GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); |
c906108c SS |
2146 | } |
2147 | ||
2148 | ||
c906108c SS |
2149 | 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR |
2150 | "lwr r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
2151 | *mipsI: |
2152 | *mipsII: | |
2153 | *mipsIII: | |
2154 | *mipsIV: | |
603a98e7 | 2155 | *mipsV: |
1e799e28 CD |
2156 | *mips32: |
2157 | *mips64: | |
c906108c SS |
2158 | *vr4100: |
2159 | *vr5000: | |
2160 | *r3900: | |
2161 | { | |
2162 | GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); | |
2163 | } | |
2164 | ||
2165 | ||
bb22bd7d | 2166 | 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU |
c906108c SS |
2167 | "lwu r<RT>, <OFFSET>(r<BASE>)" |
2168 | *mipsIII: | |
2169 | *mipsIV: | |
603a98e7 | 2170 | *mipsV: |
1e799e28 | 2171 | *mips64: |
c906108c SS |
2172 | *vr4100: |
2173 | *vr5000: | |
2174 | { | |
ca971540 | 2175 | check_u64 (SD_, instruction_0); |
c906108c SS |
2176 | GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)); |
2177 | } | |
2178 | ||
2179 | ||
1e799e28 CD |
2180 | |
2181 | 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD | |
2182 | "madd r<RS>, r<RT>" | |
2183 | *mips32: | |
2184 | *mips64: | |
2185 | { | |
2186 | signed64 temp; | |
2187 | check_mult_hilo (SD_, HIHISTORY, LOHISTORY); | |
402586aa CD |
2188 | if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) |
2189 | Unpredictable (); | |
1e799e28 CD |
2190 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); |
2191 | temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) | |
2192 | + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS]))); | |
2193 | LO = EXTEND32 (temp); | |
2194 | HI = EXTEND32 (VH4_8 (temp)); | |
2195 | TRACE_ALU_RESULT2 (HI, LO); | |
2196 | } | |
2197 | ||
2198 | ||
2199 | ||
2200 | 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU | |
2201 | "maddu r<RS>, r<RT>" | |
2202 | *mips32: | |
2203 | *mips64: | |
2204 | { | |
2205 | unsigned64 temp; | |
2206 | check_mult_hilo (SD_, HIHISTORY, LOHISTORY); | |
402586aa CD |
2207 | if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) |
2208 | Unpredictable (); | |
1e799e28 CD |
2209 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); |
2210 | temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) | |
2211 | + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT]))); | |
2212 | LO = EXTEND32 (temp); | |
2213 | HI = EXTEND32 (VH4_8 (temp)); | |
2214 | TRACE_ALU_RESULT2 (HI, LO); | |
2215 | } | |
2216 | ||
2217 | ||
c906108c SS |
2218 | :function:::void:do_mfhi:int rd |
2219 | { | |
2220 | check_mf_hilo (SD_, HIHISTORY, LOHISTORY); | |
2221 | TRACE_ALU_INPUT1 (HI); | |
2222 | GPR[rd] = HI; | |
2223 | TRACE_ALU_RESULT (GPR[rd]); | |
2224 | } | |
2225 | ||
2226 | 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI | |
2227 | "mfhi r<RD>" | |
c5d00cc7 CD |
2228 | *mipsI: |
2229 | *mipsII: | |
2230 | *mipsIII: | |
2231 | *mipsIV: | |
603a98e7 | 2232 | *mipsV: |
1e799e28 CD |
2233 | *mips32: |
2234 | *mips64: | |
c906108c SS |
2235 | *vr4100: |
2236 | *vr5000: | |
2237 | *r3900: | |
2238 | { | |
2239 | do_mfhi (SD_, RD); | |
2240 | } | |
2241 | ||
2242 | ||
2243 | ||
2244 | :function:::void:do_mflo:int rd | |
2245 | { | |
2246 | check_mf_hilo (SD_, LOHISTORY, HIHISTORY); | |
2247 | TRACE_ALU_INPUT1 (LO); | |
2248 | GPR[rd] = LO; | |
2249 | TRACE_ALU_RESULT (GPR[rd]); | |
2250 | } | |
2251 | ||
2252 | 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO | |
2253 | "mflo r<RD>" | |
c5d00cc7 CD |
2254 | *mipsI: |
2255 | *mipsII: | |
2256 | *mipsIII: | |
2257 | *mipsIV: | |
603a98e7 | 2258 | *mipsV: |
1e799e28 CD |
2259 | *mips32: |
2260 | *mips64: | |
c906108c SS |
2261 | *vr4100: |
2262 | *vr5000: | |
2263 | *r3900: | |
2264 | { | |
2265 | do_mflo (SD_, RD); | |
2266 | } | |
2267 | ||
2268 | ||
2269 | ||
f701dad2 | 2270 | 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN |
c906108c SS |
2271 | "movn r<RD>, r<RS>, r<RT>" |
2272 | *mipsIV: | |
603a98e7 | 2273 | *mipsV: |
1e799e28 CD |
2274 | *mips32: |
2275 | *mips64: | |
c906108c SS |
2276 | *vr5000: |
2277 | { | |
2278 | if (GPR[RT] != 0) | |
2279 | GPR[RD] = GPR[RS]; | |
2280 | } | |
2281 | ||
2282 | ||
2283 | ||
f701dad2 | 2284 | 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ |
c906108c SS |
2285 | "movz r<RD>, r<RS>, r<RT>" |
2286 | *mipsIV: | |
603a98e7 | 2287 | *mipsV: |
1e799e28 CD |
2288 | *mips32: |
2289 | *mips64: | |
c906108c SS |
2290 | *vr5000: |
2291 | { | |
2292 | if (GPR[RT] == 0) | |
2293 | GPR[RD] = GPR[RS]; | |
2294 | } | |
2295 | ||
2296 | ||
2297 | ||
1e799e28 CD |
2298 | 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB |
2299 | "msub r<RS>, r<RT>" | |
2300 | *mips32: | |
2301 | *mips64: | |
2302 | { | |
2303 | signed64 temp; | |
2304 | check_mult_hilo (SD_, HIHISTORY, LOHISTORY); | |
402586aa CD |
2305 | if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) |
2306 | Unpredictable (); | |
1e799e28 CD |
2307 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); |
2308 | temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) | |
2309 | - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS]))); | |
2310 | LO = EXTEND32 (temp); | |
2311 | HI = EXTEND32 (VH4_8 (temp)); | |
2312 | TRACE_ALU_RESULT2 (HI, LO); | |
2313 | } | |
2314 | ||
2315 | ||
2316 | ||
2317 | 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU | |
2318 | "msubu r<RS>, r<RT>" | |
2319 | *mips32: | |
2320 | *mips64: | |
2321 | { | |
2322 | unsigned64 temp; | |
2323 | check_mult_hilo (SD_, HIHISTORY, LOHISTORY); | |
402586aa CD |
2324 | if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) |
2325 | Unpredictable (); | |
1e799e28 CD |
2326 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); |
2327 | temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) | |
2328 | - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT]))); | |
2329 | LO = EXTEND32 (temp); | |
2330 | HI = EXTEND32 (VH4_8 (temp)); | |
2331 | TRACE_ALU_RESULT2 (HI, LO); | |
2332 | } | |
2333 | ||
2334 | ||
2335 | ||
c906108c SS |
2336 | 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI |
2337 | "mthi r<RS>" | |
c5d00cc7 CD |
2338 | *mipsI: |
2339 | *mipsII: | |
2340 | *mipsIII: | |
2341 | *mipsIV: | |
603a98e7 | 2342 | *mipsV: |
1e799e28 CD |
2343 | *mips32: |
2344 | *mips64: | |
c906108c SS |
2345 | *vr4100: |
2346 | *vr5000: | |
2347 | *r3900: | |
2348 | { | |
2349 | check_mt_hilo (SD_, HIHISTORY); | |
2350 | HI = GPR[RS]; | |
2351 | } | |
2352 | ||
2353 | ||
2354 | ||
f701dad2 | 2355 | 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO |
c906108c | 2356 | "mtlo r<RS>" |
c5d00cc7 CD |
2357 | *mipsI: |
2358 | *mipsII: | |
2359 | *mipsIII: | |
2360 | *mipsIV: | |
603a98e7 | 2361 | *mipsV: |
1e799e28 CD |
2362 | *mips32: |
2363 | *mips64: | |
c906108c SS |
2364 | *vr4100: |
2365 | *vr5000: | |
2366 | *r3900: | |
2367 | { | |
2368 | check_mt_hilo (SD_, LOHISTORY); | |
2369 | LO = GPR[RS]; | |
2370 | } | |
2371 | ||
2372 | ||
2373 | ||
1e799e28 CD |
2374 | 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL |
2375 | "mul r<RD>, r<RS>, r<RT>" | |
2376 | *mips32: | |
2377 | *mips64: | |
2378 | { | |
2379 | signed64 prod; | |
402586aa CD |
2380 | if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) |
2381 | Unpredictable (); | |
1e799e28 CD |
2382 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); |
2383 | prod = (((signed64)(signed32) GPR[RS]) | |
2384 | * ((signed64)(signed32) GPR[RT])); | |
2385 | GPR[RD] = EXTEND32 (VL4_8 (prod)); | |
2386 | TRACE_ALU_RESULT (GPR[RD]); | |
2387 | } | |
2388 | ||
2389 | ||
2390 | ||
c906108c SS |
2391 | :function:::void:do_mult:int rs, int rt, int rd |
2392 | { | |
2393 | signed64 prod; | |
2394 | check_mult_hilo (SD_, HIHISTORY, LOHISTORY); | |
402586aa CD |
2395 | if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
2396 | Unpredictable (); | |
c906108c SS |
2397 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
2398 | prod = (((signed64)(signed32) GPR[rs]) | |
2399 | * ((signed64)(signed32) GPR[rt])); | |
2400 | LO = EXTEND32 (VL4_8 (prod)); | |
2401 | HI = EXTEND32 (VH4_8 (prod)); | |
2402 | if (rd != 0) | |
2403 | GPR[rd] = LO; | |
2404 | TRACE_ALU_RESULT2 (HI, LO); | |
2405 | } | |
2406 | ||
f701dad2 | 2407 | 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT |
c906108c | 2408 | "mult r<RS>, r<RT>" |
c5d00cc7 CD |
2409 | *mipsI: |
2410 | *mipsII: | |
2411 | *mipsIII: | |
2412 | *mipsIV: | |
603a98e7 | 2413 | *mipsV: |
1e799e28 CD |
2414 | *mips32: |
2415 | *mips64: | |
c906108c SS |
2416 | *vr4100: |
2417 | { | |
2418 | do_mult (SD_, RS, RT, 0); | |
2419 | } | |
2420 | ||
2421 | ||
f701dad2 | 2422 | 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT |
9846de1b | 2423 | "mult r<RS>, r<RT>":RD == 0 |
c906108c SS |
2424 | "mult r<RD>, r<RS>, r<RT>" |
2425 | *vr5000: | |
2426 | *r3900: | |
2427 | { | |
2428 | do_mult (SD_, RS, RT, RD); | |
2429 | } | |
2430 | ||
2431 | ||
2432 | :function:::void:do_multu:int rs, int rt, int rd | |
2433 | { | |
2434 | unsigned64 prod; | |
2435 | check_mult_hilo (SD_, HIHISTORY, LOHISTORY); | |
402586aa CD |
2436 | if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
2437 | Unpredictable (); | |
c906108c SS |
2438 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
2439 | prod = (((unsigned64)(unsigned32) GPR[rs]) | |
2440 | * ((unsigned64)(unsigned32) GPR[rt])); | |
2441 | LO = EXTEND32 (VL4_8 (prod)); | |
2442 | HI = EXTEND32 (VH4_8 (prod)); | |
2443 | if (rd != 0) | |
2444 | GPR[rd] = LO; | |
2445 | TRACE_ALU_RESULT2 (HI, LO); | |
2446 | } | |
2447 | ||
f701dad2 | 2448 | 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU |
c906108c | 2449 | "multu r<RS>, r<RT>" |
c5d00cc7 CD |
2450 | *mipsI: |
2451 | *mipsII: | |
2452 | *mipsIII: | |
2453 | *mipsIV: | |
603a98e7 | 2454 | *mipsV: |
1e799e28 CD |
2455 | *mips32: |
2456 | *mips64: | |
c906108c SS |
2457 | *vr4100: |
2458 | { | |
cff3e48b | 2459 | do_multu (SD_, RS, RT, 0); |
c906108c SS |
2460 | } |
2461 | ||
f701dad2 | 2462 | 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU |
9846de1b | 2463 | "multu r<RS>, r<RT>":RD == 0 |
c906108c SS |
2464 | "multu r<RD>, r<RS>, r<RT>" |
2465 | *vr5000: | |
2466 | *r3900: | |
2467 | { | |
cff3e48b | 2468 | do_multu (SD_, RS, RT, RD); |
c906108c SS |
2469 | } |
2470 | ||
2471 | ||
2472 | :function:::void:do_nor:int rs, int rt, int rd | |
2473 | { | |
2474 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
2475 | GPR[rd] = ~ (GPR[rs] | GPR[rt]); | |
2476 | TRACE_ALU_RESULT (GPR[rd]); | |
2477 | } | |
2478 | ||
2479 | 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR | |
2480 | "nor r<RD>, r<RS>, r<RT>" | |
c5d00cc7 CD |
2481 | *mipsI: |
2482 | *mipsII: | |
2483 | *mipsIII: | |
2484 | *mipsIV: | |
603a98e7 | 2485 | *mipsV: |
1e799e28 CD |
2486 | *mips32: |
2487 | *mips64: | |
c906108c SS |
2488 | *vr4100: |
2489 | *vr5000: | |
2490 | *r3900: | |
2491 | { | |
2492 | do_nor (SD_, RS, RT, RD); | |
2493 | } | |
2494 | ||
2495 | ||
2496 | :function:::void:do_or:int rs, int rt, int rd | |
2497 | { | |
2498 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
2499 | GPR[rd] = (GPR[rs] | GPR[rt]); | |
2500 | TRACE_ALU_RESULT (GPR[rd]); | |
2501 | } | |
2502 | ||
2503 | 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR | |
2504 | "or r<RD>, r<RS>, r<RT>" | |
c5d00cc7 CD |
2505 | *mipsI: |
2506 | *mipsII: | |
2507 | *mipsIII: | |
2508 | *mipsIV: | |
603a98e7 | 2509 | *mipsV: |
1e799e28 CD |
2510 | *mips32: |
2511 | *mips64: | |
c906108c SS |
2512 | *vr4100: |
2513 | *vr5000: | |
2514 | *r3900: | |
2515 | { | |
2516 | do_or (SD_, RS, RT, RD); | |
2517 | } | |
2518 | ||
2519 | ||
2520 | ||
2521 | :function:::void:do_ori:int rs, int rt, unsigned immediate | |
2522 | { | |
2523 | TRACE_ALU_INPUT2 (GPR[rs], immediate); | |
2524 | GPR[rt] = (GPR[rs] | immediate); | |
2525 | TRACE_ALU_RESULT (GPR[rt]); | |
2526 | } | |
2527 | ||
2528 | 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI | |
82f728db | 2529 | "ori r<RT>, r<RS>, %#lx<IMMEDIATE>" |
c5d00cc7 CD |
2530 | *mipsI: |
2531 | *mipsII: | |
2532 | *mipsIII: | |
2533 | *mipsIV: | |
603a98e7 | 2534 | *mipsV: |
1e799e28 CD |
2535 | *mips32: |
2536 | *mips64: | |
c906108c SS |
2537 | *vr4100: |
2538 | *vr5000: | |
2539 | *r3900: | |
2540 | { | |
2541 | do_ori (SD_, RS, RT, IMMEDIATE); | |
2542 | } | |
2543 | ||
2544 | ||
af5107af CD |
2545 | 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF |
2546 | "pref <HINT>, <OFFSET>(r<BASE>)" | |
c906108c | 2547 | *mipsIV: |
603a98e7 | 2548 | *mipsV: |
1e799e28 CD |
2549 | *mips32: |
2550 | *mips64: | |
c906108c SS |
2551 | *vr5000: |
2552 | { | |
c1e8ada4 CD |
2553 | address_word base = GPR[BASE]; |
2554 | address_word offset = EXTEND16 (OFFSET); | |
c906108c | 2555 | { |
09297648 | 2556 | address_word vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
2557 | address_word paddr; |
2558 | int uncached; | |
2559 | { | |
2560 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
c1e8ada4 | 2561 | Prefetch(uncached,paddr,vaddr,isDATA,HINT); |
c906108c SS |
2562 | } |
2563 | } | |
2564 | } | |
2565 | ||
1c47a468 | 2566 | |
c906108c SS |
2567 | :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word |
2568 | { | |
2569 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); | |
2570 | address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); | |
2571 | address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); | |
2572 | unsigned int byte; | |
2573 | address_word paddr; | |
2574 | int uncached; | |
2575 | unsigned64 memval; | |
2576 | address_word vaddr; | |
2577 | ||
09297648 | 2578 | vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
2579 | if ((vaddr & access) != 0) |
2580 | { | |
2581 | SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal); | |
2582 | } | |
2583 | AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); | |
2584 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); | |
2585 | byte = ((vaddr & mask) ^ bigendiancpu); | |
2586 | memval = (word << (8 * byte)); | |
2587 | StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL); | |
2588 | } | |
2589 | ||
1c47a468 CD |
2590 | :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt |
2591 | { | |
2592 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); | |
2593 | address_word reverseendian = (ReverseEndian ? -1 : 0); | |
2594 | address_word bigendiancpu = (BigEndianCPU ? -1 : 0); | |
2595 | unsigned int byte; | |
2596 | unsigned int word; | |
2597 | address_word paddr; | |
2598 | int uncached; | |
2599 | unsigned64 memval; | |
2600 | address_word vaddr; | |
2601 | int nr_lhs_bits; | |
2602 | int nr_rhs_bits; | |
2603 | ||
09297648 | 2604 | vaddr = loadstore_ea (SD_, base, offset); |
1c47a468 CD |
2605 | AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); |
2606 | paddr = (paddr ^ (reverseendian & mask)); | |
2607 | if (BigEndianMem == 0) | |
2608 | paddr = paddr & ~access; | |
2609 | ||
2610 | /* compute where within the word/mem we are */ | |
2611 | byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */ | |
2612 | word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */ | |
2613 | nr_lhs_bits = 8 * byte + 8; | |
2614 | nr_rhs_bits = 8 * access - 8 * byte; | |
2615 | /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ | |
2616 | /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", | |
2617 | (long) ((unsigned64) vaddr >> 32), (long) vaddr, | |
2618 | (long) ((unsigned64) paddr >> 32), (long) paddr, | |
2619 | word, byte, nr_lhs_bits, nr_rhs_bits); */ | |
2620 | ||
2621 | if (word == 0) | |
2622 | { | |
2623 | memval = (rt >> nr_rhs_bits); | |
2624 | } | |
2625 | else | |
2626 | { | |
2627 | memval = (rt << nr_lhs_bits); | |
2628 | } | |
2629 | /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n", | |
2630 | (long) ((unsigned64) rt >> 32), (long) rt, | |
2631 | (long) ((unsigned64) memval >> 32), (long) memval); */ | |
2632 | StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL); | |
2633 | } | |
2634 | ||
2635 | :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt | |
2636 | { | |
2637 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); | |
2638 | address_word reverseendian = (ReverseEndian ? -1 : 0); | |
2639 | address_word bigendiancpu = (BigEndianCPU ? -1 : 0); | |
2640 | unsigned int byte; | |
2641 | address_word paddr; | |
2642 | int uncached; | |
2643 | unsigned64 memval; | |
2644 | address_word vaddr; | |
2645 | ||
09297648 | 2646 | vaddr = loadstore_ea (SD_, base, offset); |
1c47a468 CD |
2647 | AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); |
2648 | paddr = (paddr ^ (reverseendian & mask)); | |
2649 | if (BigEndianMem != 0) | |
2650 | paddr &= ~access; | |
2651 | byte = ((vaddr & mask) ^ (bigendiancpu & mask)); | |
2652 | memval = (rt << (byte * 8)); | |
2653 | StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL); | |
2654 | } | |
2655 | ||
c906108c SS |
2656 | |
2657 | 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB | |
2658 | "sb r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
2659 | *mipsI: |
2660 | *mipsII: | |
2661 | *mipsIII: | |
2662 | *mipsIV: | |
603a98e7 | 2663 | *mipsV: |
1e799e28 CD |
2664 | *mips32: |
2665 | *mips64: | |
c906108c SS |
2666 | *vr4100: |
2667 | *vr5000: | |
2668 | *r3900: | |
2669 | { | |
2670 | do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); | |
2671 | } | |
2672 | ||
2673 | ||
2674 | 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC | |
2675 | "sc r<RT>, <OFFSET>(r<BASE>)" | |
2676 | *mipsII: | |
2677 | *mipsIII: | |
2678 | *mipsIV: | |
603a98e7 | 2679 | *mipsV: |
1e799e28 CD |
2680 | *mips32: |
2681 | *mips64: | |
c906108c SS |
2682 | *vr4100: |
2683 | *vr5000: | |
2684 | { | |
2685 | unsigned32 instruction = instruction_0; | |
c1e8ada4 CD |
2686 | address_word base = GPR[BASE]; |
2687 | address_word offset = EXTEND16 (OFFSET); | |
c906108c | 2688 | { |
09297648 | 2689 | address_word vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
2690 | address_word paddr; |
2691 | int uncached; | |
2692 | if ((vaddr & 3) != 0) | |
2693 | { | |
2694 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal); | |
2695 | } | |
2696 | else | |
2697 | { | |
2698 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2699 | { | |
2700 | unsigned64 memval = 0; | |
2701 | unsigned64 memval1 = 0; | |
2702 | unsigned64 mask = 0x7; | |
2703 | unsigned int byte; | |
2704 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
2705 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
c1e8ada4 | 2706 | memval = ((unsigned64) GPR[RT] << (8 * byte)); |
c906108c SS |
2707 | if (LLBIT) |
2708 | { | |
2709 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
2710 | } | |
c1e8ada4 | 2711 | GPR[RT] = LLBIT; |
c906108c SS |
2712 | } |
2713 | } | |
2714 | } | |
2715 | } | |
2716 | ||
2717 | ||
2718 | 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD | |
2719 | "scd r<RT>, <OFFSET>(r<BASE>)" | |
2720 | *mipsIII: | |
2721 | *mipsIV: | |
603a98e7 | 2722 | *mipsV: |
1e799e28 | 2723 | *mips64: |
c906108c SS |
2724 | *vr4100: |
2725 | *vr5000: | |
2726 | { | |
c1e8ada4 CD |
2727 | address_word base = GPR[BASE]; |
2728 | address_word offset = EXTEND16 (OFFSET); | |
ca971540 | 2729 | check_u64 (SD_, instruction_0); |
c906108c | 2730 | { |
09297648 | 2731 | address_word vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
2732 | address_word paddr; |
2733 | int uncached; | |
2734 | if ((vaddr & 7) != 0) | |
2735 | { | |
2736 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal); | |
2737 | } | |
2738 | else | |
2739 | { | |
2740 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2741 | { | |
2742 | unsigned64 memval = 0; | |
2743 | unsigned64 memval1 = 0; | |
c1e8ada4 | 2744 | memval = GPR[RT]; |
c906108c SS |
2745 | if (LLBIT) |
2746 | { | |
2747 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
2748 | } | |
c1e8ada4 | 2749 | GPR[RT] = LLBIT; |
c906108c SS |
2750 | } |
2751 | } | |
2752 | } | |
2753 | } | |
2754 | ||
2755 | ||
2756 | 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD | |
2757 | "sd r<RT>, <OFFSET>(r<BASE>)" | |
2758 | *mipsIII: | |
2759 | *mipsIV: | |
603a98e7 | 2760 | *mipsV: |
1e799e28 | 2761 | *mips64: |
c906108c SS |
2762 | *vr4100: |
2763 | *vr5000: | |
2764 | { | |
ca971540 | 2765 | check_u64 (SD_, instruction_0); |
c906108c SS |
2766 | do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
2767 | } | |
2768 | ||
2769 | ||
2770 | 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz | |
2771 | "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)" | |
2772 | *mipsII: | |
2773 | *mipsIII: | |
2774 | *mipsIV: | |
603a98e7 | 2775 | *mipsV: |
1e799e28 CD |
2776 | *mips32: |
2777 | *mips64: | |
c906108c SS |
2778 | *vr4100: |
2779 | *vr5000: | |
2780 | { | |
2781 | do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT)); | |
2782 | } | |
2783 | ||
2784 | ||
2785 | 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL | |
2786 | "sdl r<RT>, <OFFSET>(r<BASE>)" | |
2787 | *mipsIII: | |
2788 | *mipsIV: | |
603a98e7 | 2789 | *mipsV: |
1e799e28 | 2790 | *mips64: |
c906108c SS |
2791 | *vr4100: |
2792 | *vr5000: | |
2793 | { | |
ca971540 | 2794 | check_u64 (SD_, instruction_0); |
c906108c SS |
2795 | do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
2796 | } | |
2797 | ||
2798 | ||
2799 | 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR | |
2800 | "sdr r<RT>, <OFFSET>(r<BASE>)" | |
2801 | *mipsIII: | |
2802 | *mipsIV: | |
603a98e7 | 2803 | *mipsV: |
1e799e28 | 2804 | *mips64: |
c906108c SS |
2805 | *vr4100: |
2806 | *vr5000: | |
2807 | { | |
ca971540 | 2808 | check_u64 (SD_, instruction_0); |
c906108c SS |
2809 | do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
2810 | } | |
2811 | ||
2812 | ||
2813 | 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH | |
2814 | "sh r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
2815 | *mipsI: |
2816 | *mipsII: | |
2817 | *mipsIII: | |
2818 | *mipsIV: | |
603a98e7 | 2819 | *mipsV: |
1e799e28 CD |
2820 | *mips32: |
2821 | *mips64: | |
c906108c SS |
2822 | *vr4100: |
2823 | *vr5000: | |
2824 | *r3900: | |
2825 | { | |
2826 | do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); | |
2827 | } | |
2828 | ||
2829 | ||
2830 | :function:::void:do_sll:int rt, int rd, int shift | |
2831 | { | |
2832 | unsigned32 temp = (GPR[rt] << shift); | |
2833 | TRACE_ALU_INPUT2 (GPR[rt], shift); | |
2834 | GPR[rd] = EXTEND32 (temp); | |
2835 | TRACE_ALU_RESULT (GPR[rd]); | |
2836 | } | |
2837 | ||
1e799e28 | 2838 | 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa |
20ae0098 | 2839 | "nop":RD == 0 && RT == 0 && SHIFT == 0 |
c906108c | 2840 | "sll r<RD>, r<RT>, <SHIFT>" |
c5d00cc7 CD |
2841 | *mipsI: |
2842 | *mipsII: | |
2843 | *mipsIII: | |
2844 | *mipsIV: | |
603a98e7 | 2845 | *mipsV: |
c906108c SS |
2846 | *vr4100: |
2847 | *vr5000: | |
2848 | *r3900: | |
2849 | { | |
20ae0098 CD |
2850 | /* Skip shift for NOP, so that there won't be lots of extraneous |
2851 | trace output. */ | |
2852 | if (RD != 0 || RT != 0 || SHIFT != 0) | |
2853 | do_sll (SD_, RT, RD, SHIFT); | |
c906108c SS |
2854 | } |
2855 | ||
1e799e28 CD |
2856 | 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb |
2857 | "nop":RD == 0 && RT == 0 && SHIFT == 0 | |
2858 | "ssnop":RD == 0 && RT == 0 && SHIFT == 1 | |
2859 | "sll r<RD>, r<RT>, <SHIFT>" | |
2860 | *mips32: | |
2861 | *mips64: | |
2862 | { | |
2863 | /* Skip shift for NOP and SSNOP, so that there won't be lots of | |
2864 | extraneous trace output. */ | |
2865 | if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1)) | |
2866 | do_sll (SD_, RT, RD, SHIFT); | |
2867 | } | |
2868 | ||
c906108c SS |
2869 | |
2870 | :function:::void:do_sllv:int rs, int rt, int rd | |
2871 | { | |
2872 | int s = MASKED (GPR[rs], 4, 0); | |
2873 | unsigned32 temp = (GPR[rt] << s); | |
2874 | TRACE_ALU_INPUT2 (GPR[rt], s); | |
2875 | GPR[rd] = EXTEND32 (temp); | |
2876 | TRACE_ALU_RESULT (GPR[rd]); | |
2877 | } | |
2878 | ||
f701dad2 | 2879 | 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV |
c906108c | 2880 | "sllv r<RD>, r<RT>, r<RS>" |
c5d00cc7 CD |
2881 | *mipsI: |
2882 | *mipsII: | |
2883 | *mipsIII: | |
2884 | *mipsIV: | |
603a98e7 | 2885 | *mipsV: |
1e799e28 CD |
2886 | *mips32: |
2887 | *mips64: | |
c906108c SS |
2888 | *vr4100: |
2889 | *vr5000: | |
2890 | *r3900: | |
2891 | { | |
2892 | do_sllv (SD_, RS, RT, RD); | |
2893 | } | |
2894 | ||
2895 | ||
2896 | :function:::void:do_slt:int rs, int rt, int rd | |
2897 | { | |
2898 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
2899 | GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]); | |
2900 | TRACE_ALU_RESULT (GPR[rd]); | |
2901 | } | |
2902 | ||
f701dad2 | 2903 | 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT |
c906108c | 2904 | "slt r<RD>, r<RS>, r<RT>" |
c5d00cc7 CD |
2905 | *mipsI: |
2906 | *mipsII: | |
2907 | *mipsIII: | |
2908 | *mipsIV: | |
603a98e7 | 2909 | *mipsV: |
1e799e28 CD |
2910 | *mips32: |
2911 | *mips64: | |
c906108c SS |
2912 | *vr4100: |
2913 | *vr5000: | |
2914 | *r3900: | |
2915 | { | |
2916 | do_slt (SD_, RS, RT, RD); | |
2917 | } | |
2918 | ||
2919 | ||
2920 | :function:::void:do_slti:int rs, int rt, unsigned16 immediate | |
2921 | { | |
2922 | TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); | |
2923 | GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate)); | |
2924 | TRACE_ALU_RESULT (GPR[rt]); | |
2925 | } | |
2926 | ||
2927 | 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI | |
2928 | "slti r<RT>, r<RS>, <IMMEDIATE>" | |
c5d00cc7 CD |
2929 | *mipsI: |
2930 | *mipsII: | |
2931 | *mipsIII: | |
2932 | *mipsIV: | |
603a98e7 | 2933 | *mipsV: |
1e799e28 CD |
2934 | *mips32: |
2935 | *mips64: | |
c906108c SS |
2936 | *vr4100: |
2937 | *vr5000: | |
2938 | *r3900: | |
2939 | { | |
2940 | do_slti (SD_, RS, RT, IMMEDIATE); | |
2941 | } | |
2942 | ||
2943 | ||
2944 | :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate | |
2945 | { | |
2946 | TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); | |
2947 | GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate)); | |
2948 | TRACE_ALU_RESULT (GPR[rt]); | |
2949 | } | |
2950 | ||
2951 | 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU | |
2952 | "sltiu r<RT>, r<RS>, <IMMEDIATE>" | |
c5d00cc7 CD |
2953 | *mipsI: |
2954 | *mipsII: | |
2955 | *mipsIII: | |
2956 | *mipsIV: | |
603a98e7 | 2957 | *mipsV: |
1e799e28 CD |
2958 | *mips32: |
2959 | *mips64: | |
c906108c SS |
2960 | *vr4100: |
2961 | *vr5000: | |
2962 | *r3900: | |
2963 | { | |
2964 | do_sltiu (SD_, RS, RT, IMMEDIATE); | |
2965 | } | |
2966 | ||
2967 | ||
2968 | ||
2969 | :function:::void:do_sltu:int rs, int rt, int rd | |
2970 | { | |
2971 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
2972 | GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]); | |
2973 | TRACE_ALU_RESULT (GPR[rd]); | |
2974 | } | |
2975 | ||
f701dad2 | 2976 | 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU |
c906108c | 2977 | "sltu r<RD>, r<RS>, r<RT>" |
c5d00cc7 CD |
2978 | *mipsI: |
2979 | *mipsII: | |
2980 | *mipsIII: | |
2981 | *mipsIV: | |
603a98e7 | 2982 | *mipsV: |
1e799e28 CD |
2983 | *mips32: |
2984 | *mips64: | |
c906108c SS |
2985 | *vr4100: |
2986 | *vr5000: | |
2987 | *r3900: | |
2988 | { | |
2989 | do_sltu (SD_, RS, RT, RD); | |
2990 | } | |
2991 | ||
2992 | ||
2993 | :function:::void:do_sra:int rt, int rd, int shift | |
2994 | { | |
2995 | signed32 temp = (signed32) GPR[rt] >> shift; | |
402586aa CD |
2996 | if (NotWordValue (GPR[rt])) |
2997 | Unpredictable (); | |
c906108c SS |
2998 | TRACE_ALU_INPUT2 (GPR[rt], shift); |
2999 | GPR[rd] = EXTEND32 (temp); | |
3000 | TRACE_ALU_RESULT (GPR[rd]); | |
3001 | } | |
3002 | ||
3003 | 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA | |
3004 | "sra r<RD>, r<RT>, <SHIFT>" | |
c5d00cc7 CD |
3005 | *mipsI: |
3006 | *mipsII: | |
3007 | *mipsIII: | |
3008 | *mipsIV: | |
603a98e7 | 3009 | *mipsV: |
1e799e28 CD |
3010 | *mips32: |
3011 | *mips64: | |
c906108c SS |
3012 | *vr4100: |
3013 | *vr5000: | |
3014 | *r3900: | |
3015 | { | |
3016 | do_sra (SD_, RT, RD, SHIFT); | |
3017 | } | |
3018 | ||
3019 | ||
3020 | ||
3021 | :function:::void:do_srav:int rs, int rt, int rd | |
3022 | { | |
3023 | int s = MASKED (GPR[rs], 4, 0); | |
3024 | signed32 temp = (signed32) GPR[rt] >> s; | |
402586aa CD |
3025 | if (NotWordValue (GPR[rt])) |
3026 | Unpredictable (); | |
c906108c SS |
3027 | TRACE_ALU_INPUT2 (GPR[rt], s); |
3028 | GPR[rd] = EXTEND32 (temp); | |
3029 | TRACE_ALU_RESULT (GPR[rd]); | |
3030 | } | |
3031 | ||
f701dad2 | 3032 | 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV |
c906108c | 3033 | "srav r<RD>, r<RT>, r<RS>" |
c5d00cc7 CD |
3034 | *mipsI: |
3035 | *mipsII: | |
3036 | *mipsIII: | |
3037 | *mipsIV: | |
603a98e7 | 3038 | *mipsV: |
1e799e28 CD |
3039 | *mips32: |
3040 | *mips64: | |
c906108c SS |
3041 | *vr4100: |
3042 | *vr5000: | |
3043 | *r3900: | |
3044 | { | |
3045 | do_srav (SD_, RS, RT, RD); | |
3046 | } | |
3047 | ||
3048 | ||
3049 | ||
3050 | :function:::void:do_srl:int rt, int rd, int shift | |
3051 | { | |
3052 | unsigned32 temp = (unsigned32) GPR[rt] >> shift; | |
402586aa CD |
3053 | if (NotWordValue (GPR[rt])) |
3054 | Unpredictable (); | |
c906108c SS |
3055 | TRACE_ALU_INPUT2 (GPR[rt], shift); |
3056 | GPR[rd] = EXTEND32 (temp); | |
3057 | TRACE_ALU_RESULT (GPR[rd]); | |
3058 | } | |
3059 | ||
3060 | 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL | |
3061 | "srl r<RD>, r<RT>, <SHIFT>" | |
c5d00cc7 CD |
3062 | *mipsI: |
3063 | *mipsII: | |
3064 | *mipsIII: | |
3065 | *mipsIV: | |
603a98e7 | 3066 | *mipsV: |
1e799e28 CD |
3067 | *mips32: |
3068 | *mips64: | |
c906108c SS |
3069 | *vr4100: |
3070 | *vr5000: | |
3071 | *r3900: | |
3072 | { | |
3073 | do_srl (SD_, RT, RD, SHIFT); | |
3074 | } | |
3075 | ||
3076 | ||
3077 | :function:::void:do_srlv:int rs, int rt, int rd | |
3078 | { | |
3079 | int s = MASKED (GPR[rs], 4, 0); | |
3080 | unsigned32 temp = (unsigned32) GPR[rt] >> s; | |
402586aa CD |
3081 | if (NotWordValue (GPR[rt])) |
3082 | Unpredictable (); | |
c906108c SS |
3083 | TRACE_ALU_INPUT2 (GPR[rt], s); |
3084 | GPR[rd] = EXTEND32 (temp); | |
3085 | TRACE_ALU_RESULT (GPR[rd]); | |
3086 | } | |
3087 | ||
f701dad2 | 3088 | 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV |
c906108c | 3089 | "srlv r<RD>, r<RT>, r<RS>" |
c5d00cc7 CD |
3090 | *mipsI: |
3091 | *mipsII: | |
3092 | *mipsIII: | |
3093 | *mipsIV: | |
603a98e7 | 3094 | *mipsV: |
1e799e28 CD |
3095 | *mips32: |
3096 | *mips64: | |
c906108c SS |
3097 | *vr4100: |
3098 | *vr5000: | |
3099 | *r3900: | |
3100 | { | |
3101 | do_srlv (SD_, RS, RT, RD); | |
3102 | } | |
3103 | ||
3104 | ||
f701dad2 | 3105 | 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB |
c906108c | 3106 | "sub r<RD>, r<RS>, r<RT>" |
c5d00cc7 CD |
3107 | *mipsI: |
3108 | *mipsII: | |
3109 | *mipsIII: | |
3110 | *mipsIV: | |
603a98e7 | 3111 | *mipsV: |
1e799e28 CD |
3112 | *mips32: |
3113 | *mips64: | |
c906108c SS |
3114 | *vr4100: |
3115 | *vr5000: | |
3116 | *r3900: | |
3117 | { | |
402586aa CD |
3118 | if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) |
3119 | Unpredictable (); | |
c906108c SS |
3120 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); |
3121 | { | |
3122 | ALU32_BEGIN (GPR[RS]); | |
3123 | ALU32_SUB (GPR[RT]); | |
9805e229 | 3124 | ALU32_END (GPR[RD]); /* This checks for overflow. */ |
c906108c SS |
3125 | } |
3126 | TRACE_ALU_RESULT (GPR[RD]); | |
3127 | } | |
3128 | ||
3129 | ||
3130 | :function:::void:do_subu:int rs, int rt, int rd | |
3131 | { | |
402586aa CD |
3132 | if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) |
3133 | Unpredictable (); | |
c906108c SS |
3134 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); |
3135 | GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]); | |
3136 | TRACE_ALU_RESULT (GPR[rd]); | |
3137 | } | |
3138 | ||
f701dad2 | 3139 | 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU |
c906108c | 3140 | "subu r<RD>, r<RS>, r<RT>" |
c5d00cc7 CD |
3141 | *mipsI: |
3142 | *mipsII: | |
3143 | *mipsIII: | |
3144 | *mipsIV: | |
603a98e7 | 3145 | *mipsV: |
1e799e28 CD |
3146 | *mips32: |
3147 | *mips64: | |
c906108c SS |
3148 | *vr4100: |
3149 | *vr5000: | |
3150 | *r3900: | |
3151 | { | |
3152 | do_subu (SD_, RS, RT, RD); | |
3153 | } | |
3154 | ||
3155 | ||
3156 | 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW | |
3157 | "sw r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
3158 | *mipsI: |
3159 | *mipsII: | |
3160 | *mipsIII: | |
3161 | *mipsIV: | |
603a98e7 | 3162 | *mipsV: |
1e799e28 CD |
3163 | *mips32: |
3164 | *mips64: | |
c906108c SS |
3165 | *vr4100: |
3166 | *r3900: | |
3167 | *vr5000: | |
3168 | { | |
3169 | do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); | |
3170 | } | |
3171 | ||
3172 | ||
3173 | 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz | |
3174 | "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
3175 | *mipsI: |
3176 | *mipsII: | |
3177 | *mipsIII: | |
3178 | *mipsIV: | |
603a98e7 | 3179 | *mipsV: |
1e799e28 CD |
3180 | *mips32: |
3181 | *mips64: | |
c906108c SS |
3182 | *vr4100: |
3183 | *vr5000: | |
3184 | *r3900: | |
3185 | { | |
3186 | do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT)); | |
3187 | } | |
3188 | ||
3189 | ||
c906108c SS |
3190 | 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL |
3191 | "swl r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
3192 | *mipsI: |
3193 | *mipsII: | |
3194 | *mipsIII: | |
3195 | *mipsIV: | |
603a98e7 | 3196 | *mipsV: |
1e799e28 CD |
3197 | *mips32: |
3198 | *mips64: | |
c906108c SS |
3199 | *vr4100: |
3200 | *vr5000: | |
3201 | *r3900: | |
3202 | { | |
3203 | do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); | |
3204 | } | |
3205 | ||
3206 | ||
c906108c SS |
3207 | 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR |
3208 | "swr r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
3209 | *mipsI: |
3210 | *mipsII: | |
3211 | *mipsIII: | |
3212 | *mipsIV: | |
603a98e7 | 3213 | *mipsV: |
1e799e28 CD |
3214 | *mips32: |
3215 | *mips64: | |
c906108c SS |
3216 | *vr4100: |
3217 | *vr5000: | |
3218 | *r3900: | |
3219 | { | |
3220 | do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); | |
3221 | } | |
3222 | ||
3223 | ||
f701dad2 | 3224 | 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC |
c906108c SS |
3225 | "sync":STYPE == 0 |
3226 | "sync <STYPE>" | |
3227 | *mipsII: | |
3228 | *mipsIII: | |
3229 | *mipsIV: | |
603a98e7 | 3230 | *mipsV: |
1e799e28 CD |
3231 | *mips32: |
3232 | *mips64: | |
c906108c SS |
3233 | *vr4100: |
3234 | *vr5000: | |
3235 | *r3900: | |
3236 | { | |
3237 | SyncOperation (STYPE); | |
3238 | } | |
3239 | ||
3240 | ||
3241 | 000000,20.CODE,001100:SPECIAL:32::SYSCALL | |
82f728db | 3242 | "syscall %#lx<CODE>" |
c5d00cc7 CD |
3243 | *mipsI: |
3244 | *mipsII: | |
3245 | *mipsIII: | |
3246 | *mipsIV: | |
603a98e7 | 3247 | *mipsV: |
1e799e28 CD |
3248 | *mips32: |
3249 | *mips64: | |
c906108c SS |
3250 | *vr4100: |
3251 | *vr5000: | |
3252 | *r3900: | |
3253 | { | |
86b77b47 | 3254 | SignalException (SystemCall, instruction_0); |
c906108c SS |
3255 | } |
3256 | ||
3257 | ||
3258 | 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ | |
3259 | "teq r<RS>, r<RT>" | |
3260 | *mipsII: | |
3261 | *mipsIII: | |
3262 | *mipsIV: | |
603a98e7 | 3263 | *mipsV: |
1e799e28 CD |
3264 | *mips32: |
3265 | *mips64: | |
c906108c SS |
3266 | *vr4100: |
3267 | *vr5000: | |
3268 | { | |
3269 | if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) | |
86b77b47 | 3270 | SignalException (Trap, instruction_0); |
c906108c SS |
3271 | } |
3272 | ||
3273 | ||
3274 | 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI | |
3275 | "teqi r<RS>, <IMMEDIATE>" | |
3276 | *mipsII: | |
3277 | *mipsIII: | |
3278 | *mipsIV: | |
603a98e7 | 3279 | *mipsV: |
1e799e28 CD |
3280 | *mips32: |
3281 | *mips64: | |
c906108c SS |
3282 | *vr4100: |
3283 | *vr5000: | |
3284 | { | |
3285 | if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE)) | |
86b77b47 | 3286 | SignalException (Trap, instruction_0); |
c906108c SS |
3287 | } |
3288 | ||
3289 | ||
3290 | 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE | |
3291 | "tge r<RS>, r<RT>" | |
3292 | *mipsII: | |
3293 | *mipsIII: | |
3294 | *mipsIV: | |
603a98e7 | 3295 | *mipsV: |
1e799e28 CD |
3296 | *mips32: |
3297 | *mips64: | |
c906108c SS |
3298 | *vr4100: |
3299 | *vr5000: | |
3300 | { | |
3301 | if ((signed_word) GPR[RS] >= (signed_word) GPR[RT]) | |
86b77b47 | 3302 | SignalException (Trap, instruction_0); |
c906108c SS |
3303 | } |
3304 | ||
3305 | ||
3306 | 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI | |
3307 | "tgei r<RS>, <IMMEDIATE>" | |
3308 | *mipsII: | |
3309 | *mipsIII: | |
3310 | *mipsIV: | |
603a98e7 | 3311 | *mipsV: |
1e799e28 CD |
3312 | *mips32: |
3313 | *mips64: | |
c906108c SS |
3314 | *vr4100: |
3315 | *vr5000: | |
3316 | { | |
3317 | if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE)) | |
86b77b47 | 3318 | SignalException (Trap, instruction_0); |
c906108c SS |
3319 | } |
3320 | ||
3321 | ||
3322 | 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU | |
3323 | "tgeiu r<RS>, <IMMEDIATE>" | |
3324 | *mipsII: | |
3325 | *mipsIII: | |
3326 | *mipsIV: | |
603a98e7 | 3327 | *mipsV: |
1e799e28 CD |
3328 | *mips32: |
3329 | *mips64: | |
c906108c SS |
3330 | *vr4100: |
3331 | *vr5000: | |
3332 | { | |
3333 | if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE)) | |
86b77b47 | 3334 | SignalException (Trap, instruction_0); |
c906108c SS |
3335 | } |
3336 | ||
3337 | ||
3338 | 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU | |
3339 | "tgeu r<RS>, r<RT>" | |
3340 | *mipsII: | |
3341 | *mipsIII: | |
3342 | *mipsIV: | |
603a98e7 | 3343 | *mipsV: |
1e799e28 CD |
3344 | *mips32: |
3345 | *mips64: | |
c906108c SS |
3346 | *vr4100: |
3347 | *vr5000: | |
3348 | { | |
3349 | if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT]) | |
86b77b47 | 3350 | SignalException (Trap, instruction_0); |
c906108c SS |
3351 | } |
3352 | ||
3353 | ||
3354 | 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT | |
3355 | "tlt r<RS>, r<RT>" | |
3356 | *mipsII: | |
3357 | *mipsIII: | |
3358 | *mipsIV: | |
603a98e7 | 3359 | *mipsV: |
1e799e28 CD |
3360 | *mips32: |
3361 | *mips64: | |
c906108c SS |
3362 | *vr4100: |
3363 | *vr5000: | |
3364 | { | |
3365 | if ((signed_word) GPR[RS] < (signed_word) GPR[RT]) | |
86b77b47 | 3366 | SignalException (Trap, instruction_0); |
c906108c SS |
3367 | } |
3368 | ||
3369 | ||
3370 | 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI | |
3371 | "tlti r<RS>, <IMMEDIATE>" | |
3372 | *mipsII: | |
3373 | *mipsIII: | |
3374 | *mipsIV: | |
603a98e7 | 3375 | *mipsV: |
1e799e28 CD |
3376 | *mips32: |
3377 | *mips64: | |
c906108c SS |
3378 | *vr4100: |
3379 | *vr5000: | |
3380 | { | |
3381 | if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE)) | |
86b77b47 | 3382 | SignalException (Trap, instruction_0); |
c906108c SS |
3383 | } |
3384 | ||
3385 | ||
3386 | 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU | |
3387 | "tltiu r<RS>, <IMMEDIATE>" | |
3388 | *mipsII: | |
3389 | *mipsIII: | |
3390 | *mipsIV: | |
603a98e7 | 3391 | *mipsV: |
1e799e28 CD |
3392 | *mips32: |
3393 | *mips64: | |
c906108c SS |
3394 | *vr4100: |
3395 | *vr5000: | |
3396 | { | |
3397 | if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE)) | |
86b77b47 | 3398 | SignalException (Trap, instruction_0); |
c906108c SS |
3399 | } |
3400 | ||
3401 | ||
3402 | 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU | |
3403 | "tltu r<RS>, r<RT>" | |
3404 | *mipsII: | |
3405 | *mipsIII: | |
3406 | *mipsIV: | |
603a98e7 | 3407 | *mipsV: |
1e799e28 CD |
3408 | *mips32: |
3409 | *mips64: | |
c906108c SS |
3410 | *vr4100: |
3411 | *vr5000: | |
3412 | { | |
3413 | if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]) | |
86b77b47 | 3414 | SignalException (Trap, instruction_0); |
c906108c SS |
3415 | } |
3416 | ||
3417 | ||
3418 | 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE | |
3419 | "tne r<RS>, r<RT>" | |
3420 | *mipsII: | |
3421 | *mipsIII: | |
3422 | *mipsIV: | |
603a98e7 | 3423 | *mipsV: |
1e799e28 CD |
3424 | *mips32: |
3425 | *mips64: | |
c906108c SS |
3426 | *vr4100: |
3427 | *vr5000: | |
3428 | { | |
3429 | if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) | |
86b77b47 | 3430 | SignalException (Trap, instruction_0); |
c906108c SS |
3431 | } |
3432 | ||
3433 | ||
3434 | 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI | |
3435 | "tne r<RS>, <IMMEDIATE>" | |
3436 | *mipsII: | |
3437 | *mipsIII: | |
3438 | *mipsIV: | |
603a98e7 | 3439 | *mipsV: |
1e799e28 CD |
3440 | *mips32: |
3441 | *mips64: | |
c906108c SS |
3442 | *vr4100: |
3443 | *vr5000: | |
3444 | { | |
3445 | if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE)) | |
86b77b47 | 3446 | SignalException (Trap, instruction_0); |
c906108c SS |
3447 | } |
3448 | ||
3449 | ||
3450 | :function:::void:do_xor:int rs, int rt, int rd | |
3451 | { | |
3452 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
3453 | GPR[rd] = GPR[rs] ^ GPR[rt]; | |
3454 | TRACE_ALU_RESULT (GPR[rd]); | |
3455 | } | |
3456 | ||
f701dad2 | 3457 | 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR |
c906108c | 3458 | "xor r<RD>, r<RS>, r<RT>" |
c5d00cc7 CD |
3459 | *mipsI: |
3460 | *mipsII: | |
3461 | *mipsIII: | |
3462 | *mipsIV: | |
603a98e7 | 3463 | *mipsV: |
1e799e28 CD |
3464 | *mips32: |
3465 | *mips64: | |
c906108c SS |
3466 | *vr4100: |
3467 | *vr5000: | |
3468 | *r3900: | |
3469 | { | |
3470 | do_xor (SD_, RS, RT, RD); | |
3471 | } | |
3472 | ||
3473 | ||
3474 | :function:::void:do_xori:int rs, int rt, unsigned16 immediate | |
3475 | { | |
3476 | TRACE_ALU_INPUT2 (GPR[rs], immediate); | |
3477 | GPR[rt] = GPR[rs] ^ immediate; | |
3478 | TRACE_ALU_RESULT (GPR[rt]); | |
3479 | } | |
3480 | ||
3481 | 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI | |
82f728db | 3482 | "xori r<RT>, r<RS>, %#lx<IMMEDIATE>" |
c5d00cc7 CD |
3483 | *mipsI: |
3484 | *mipsII: | |
3485 | *mipsIII: | |
3486 | *mipsIV: | |
603a98e7 | 3487 | *mipsV: |
1e799e28 CD |
3488 | *mips32: |
3489 | *mips64: | |
c906108c SS |
3490 | *vr4100: |
3491 | *vr5000: | |
3492 | *r3900: | |
3493 | { | |
3494 | do_xori (SD_, RS, RT, IMMEDIATE); | |
3495 | } | |
3496 | ||
3497 | \f | |
3498 | // | |
3499 | // MIPS Architecture: | |
3500 | // | |
3501 | // FPU Instruction Set (COP1 & COP1X) | |
3502 | // | |
3503 | ||
3504 | ||
3505 | :%s::::FMT:int fmt | |
3506 | { | |
3507 | switch (fmt) | |
3508 | { | |
3509 | case fmt_single: return "s"; | |
3510 | case fmt_double: return "d"; | |
3511 | case fmt_word: return "w"; | |
3512 | case fmt_long: return "l"; | |
3513 | default: return "?"; | |
3514 | } | |
3515 | } | |
3516 | ||
3517 | :%s::::X:int x | |
3518 | { | |
3519 | switch (x) | |
3520 | { | |
3521 | case 0: return "f"; | |
3522 | case 1: return "t"; | |
3523 | default: return "?"; | |
3524 | } | |
3525 | } | |
3526 | ||
3527 | :%s::::TF:int tf | |
3528 | { | |
3529 | if (tf) | |
3530 | return "t"; | |
3531 | else | |
3532 | return "f"; | |
3533 | } | |
3534 | ||
3535 | :%s::::ND:int nd | |
3536 | { | |
3537 | if (nd) | |
3538 | return "l"; | |
3539 | else | |
3540 | return ""; | |
3541 | } | |
3542 | ||
3543 | :%s::::COND:int cond | |
3544 | { | |
3545 | switch (cond) | |
3546 | { | |
3547 | case 00: return "f"; | |
3548 | case 01: return "un"; | |
3549 | case 02: return "eq"; | |
3550 | case 03: return "ueq"; | |
3551 | case 04: return "olt"; | |
3552 | case 05: return "ult"; | |
3553 | case 06: return "ole"; | |
3554 | case 07: return "ule"; | |
3555 | case 010: return "sf"; | |
3556 | case 011: return "ngle"; | |
3557 | case 012: return "seq"; | |
3558 | case 013: return "ngl"; | |
3559 | case 014: return "lt"; | |
3560 | case 015: return "nge"; | |
3561 | case 016: return "le"; | |
3562 | case 017: return "ngt"; | |
3563 | default: return "?"; | |
3564 | } | |
3565 | } | |
3566 | ||
8612006b CD |
3567 | |
3568 | // Helpers: | |
3569 | // | |
3570 | // Check that the given FPU format is usable, and signal a | |
3571 | // ReservedInstruction exception if not. | |
3572 | // | |
3573 | ||
3574 | // check_fmt checks that the format is single or double. | |
3575 | :function:::void:check_fmt:int fmt, instruction_word insn | |
3576 | *mipsI: | |
3577 | *mipsII: | |
3578 | *mipsIII: | |
3579 | *mipsIV: | |
3580 | *mipsV: | |
1e799e28 CD |
3581 | *mips32: |
3582 | *mips64: | |
8612006b CD |
3583 | *vr4100: |
3584 | *vr5000: | |
3585 | *r3900: | |
3586 | { | |
3587 | if ((fmt != fmt_single) && (fmt != fmt_double)) | |
3588 | SignalException (ReservedInstruction, insn); | |
3589 | } | |
3590 | ||
3591 | // check_fmt_p checks that the format is single, double, or paired single. | |
3592 | :function:::void:check_fmt_p:int fmt, instruction_word insn | |
3593 | *mipsI: | |
3594 | *mipsII: | |
3595 | *mipsIII: | |
3596 | *mipsIV: | |
1e799e28 | 3597 | *mips32: |
8612006b CD |
3598 | *vr4100: |
3599 | *vr5000: | |
3600 | *r3900: | |
3601 | { | |
3602 | /* None of these ISAs support Paired Single, so just fall back to | |
3603 | the single/double check. */ | |
8612006b CD |
3604 | check_fmt (SD_, fmt, insn); |
3605 | } | |
3606 | ||
1e799e28 CD |
3607 | :function:::void:check_fmt_p:int fmt, instruction_word insn |
3608 | *mipsV: | |
3609 | *mips64: | |
3610 | { | |
3611 | #if 0 /* XXX FIXME: FP code doesn't yet support paired single ops. */ | |
3612 | if ((fmt != fmt_single) && (fmt != fmt_double) | |
3613 | && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0))) | |
3614 | SignalException (ReservedInstruction, insn); | |
3615 | #else | |
3616 | check_fmt (SD_, fmt, insn); | |
3617 | #endif | |
3618 | } | |
3619 | ||
8612006b | 3620 | |
ca971540 | 3621 | // Helper: |
4a0bd876 | 3622 | // |
ca971540 CD |
3623 | // Check that the FPU is currently usable, and signal a CoProcessorUnusable |
3624 | // exception if not. | |
3625 | // | |
3626 | ||
3627 | :function:::void:check_fpu: | |
4a0bd876 | 3628 | *mipsI: |
ca971540 CD |
3629 | *mipsII: |
3630 | *mipsIII: | |
3631 | *mipsIV: | |
3632 | *mipsV: | |
1e799e28 CD |
3633 | *mips32: |
3634 | *mips64: | |
ca971540 CD |
3635 | *vr4100: |
3636 | *vr5000: | |
3637 | *r3900: | |
3638 | { | |
ca971540 CD |
3639 | if (! COP_Usable (1)) |
3640 | SignalExceptionCoProcessorUnusable (1); | |
ca971540 CD |
3641 | } |
3642 | ||
c906108c SS |
3643 | |
3644 | 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt | |
3645 | "abs.%s<FMT> f<FD>, f<FS>" | |
c5d00cc7 CD |
3646 | *mipsI: |
3647 | *mipsII: | |
3648 | *mipsIII: | |
3649 | *mipsIV: | |
603a98e7 | 3650 | *mipsV: |
1e799e28 CD |
3651 | *mips32: |
3652 | *mips64: | |
c906108c SS |
3653 | *vr4100: |
3654 | *vr5000: | |
3655 | *r3900: | |
3656 | { | |
c1e8ada4 | 3657 | int fmt = FMT; |
9b17d183 | 3658 | check_fpu (SD_); |
8612006b CD |
3659 | check_fmt_p (SD_, fmt, instruction_0); |
3660 | StoreFPR(FD,fmt,AbsoluteValue(ValueFPR(FS,fmt),fmt)); | |
c906108c SS |
3661 | } |
3662 | ||
3663 | ||
3664 | ||
3665 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt | |
3666 | "add.%s<FMT> f<FD>, f<FS>, f<FT>" | |
c5d00cc7 CD |
3667 | *mipsI: |
3668 | *mipsII: | |
3669 | *mipsIII: | |
3670 | *mipsIV: | |
603a98e7 | 3671 | *mipsV: |
1e799e28 CD |
3672 | *mips32: |
3673 | *mips64: | |
c906108c SS |
3674 | *vr4100: |
3675 | *vr5000: | |
3676 | *r3900: | |
3677 | { | |
c1e8ada4 | 3678 | int fmt = FMT; |
9b17d183 | 3679 | check_fpu (SD_); |
8612006b CD |
3680 | check_fmt_p (SD_, fmt, instruction_0); |
3681 | StoreFPR(FD,fmt,Add(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt)); | |
c906108c SS |
3682 | } |
3683 | ||
3684 | ||
3685 | ||
3686 | // BC1F | |
3687 | // BC1FL | |
3688 | // BC1T | |
3689 | // BC1TL | |
3690 | ||
3691 | 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a | |
3692 | "bc1%s<TF>%s<ND> <OFFSET>" | |
c5d00cc7 CD |
3693 | *mipsI: |
3694 | *mipsII: | |
3695 | *mipsIII: | |
c906108c | 3696 | { |
9b17d183 | 3697 | check_fpu (SD_); |
c906108c SS |
3698 | check_branch_bug (); |
3699 | TRACE_BRANCH_INPUT (PREVCOC1()); | |
3700 | if (PREVCOC1() == TF) | |
3701 | { | |
3702 | address_word dest = NIA + (EXTEND16 (OFFSET) << 2); | |
3703 | TRACE_BRANCH_RESULT (dest); | |
3704 | mark_branch_bug (dest); | |
3705 | DELAY_SLOT (dest); | |
3706 | } | |
3707 | else if (ND) | |
3708 | { | |
3709 | TRACE_BRANCH_RESULT (0); | |
3710 | NULLIFY_NEXT_INSTRUCTION (); | |
3711 | } | |
3712 | else | |
3713 | { | |
3714 | TRACE_BRANCH_RESULT (NIA); | |
3715 | } | |
3716 | } | |
3717 | ||
3718 | 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b | |
3719 | "bc1%s<TF>%s<ND> <OFFSET>":CC == 0 | |
3720 | "bc1%s<TF>%s<ND> <CC>, <OFFSET>" | |
3721 | *mipsIV: | |
603a98e7 | 3722 | *mipsV: |
1e799e28 CD |
3723 | *mips32: |
3724 | *mips64: | |
c906108c | 3725 | #*vr4100: |
074e9cb8 | 3726 | *vr5000: |
c906108c SS |
3727 | *r3900: |
3728 | { | |
9b17d183 | 3729 | check_fpu (SD_); |
c906108c SS |
3730 | check_branch_bug (); |
3731 | if (GETFCC(CC) == TF) | |
3732 | { | |
3733 | address_word dest = NIA + (EXTEND16 (OFFSET) << 2); | |
3734 | mark_branch_bug (dest); | |
3735 | DELAY_SLOT (dest); | |
3736 | } | |
3737 | else if (ND) | |
3738 | { | |
3739 | NULLIFY_NEXT_INSTRUCTION (); | |
3740 | } | |
3741 | } | |
3742 | ||
3743 | ||
3744 | ||
3745 | ||
3746 | ||
3747 | ||
3748 | // C.EQ.S | |
3749 | // C.EQ.D | |
3750 | // ... | |
3751 | ||
3752 | :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn | |
3753 | { | |
8612006b CD |
3754 | int less; |
3755 | int equal; | |
3756 | int unordered; | |
3757 | int condition; | |
3758 | unsigned64 ofs = ValueFPR (fs, fmt); | |
3759 | unsigned64 oft = ValueFPR (ft, fmt); | |
3760 | if (NaN (ofs, fmt) || NaN (oft, fmt)) | |
c906108c | 3761 | { |
8612006b | 3762 | if (FCSR & FP_ENABLE (IO)) |
c906108c | 3763 | { |
8612006b CD |
3764 | FCSR |= FP_CAUSE (IO); |
3765 | SignalExceptionFPE (); | |
c906108c | 3766 | } |
8612006b CD |
3767 | less = 0; |
3768 | equal = 0; | |
3769 | unordered = 1; | |
3770 | } | |
3771 | else | |
3772 | { | |
3773 | less = Less (ofs, oft, fmt); | |
3774 | equal = Equal (ofs, oft, fmt); | |
3775 | unordered = 0; | |
c906108c | 3776 | } |
8612006b CD |
3777 | condition = (((cond & (1 << 2)) && less) |
3778 | || ((cond & (1 << 1)) && equal) | |
3779 | || ((cond & (1 << 0)) && unordered)); | |
3780 | SETFCC (cc, condition); | |
c906108c SS |
3781 | } |
3782 | ||
eb5fcf93 | 3783 | 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta |
c906108c | 3784 | "c.%s<COND>.%s<FMT> f<FS>, f<FT>" |
c5d00cc7 CD |
3785 | *mipsI: |
3786 | *mipsII: | |
3787 | *mipsIII: | |
c906108c | 3788 | { |
8612006b | 3789 | int fmt = FMT; |
9b17d183 | 3790 | check_fpu (SD_); |
8612006b CD |
3791 | check_fmt_p (SD_, fmt, instruction_0); |
3792 | do_c_cond_fmt (SD_, fmt, FT, FS, 0, COND, instruction_0); | |
c906108c SS |
3793 | } |
3794 | ||
eb5fcf93 | 3795 | 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb |
c906108c SS |
3796 | "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0 |
3797 | "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>" | |
3798 | *mipsIV: | |
603a98e7 | 3799 | *mipsV: |
1e799e28 CD |
3800 | *mips32: |
3801 | *mips64: | |
c906108c SS |
3802 | *vr4100: |
3803 | *vr5000: | |
3804 | *r3900: | |
3805 | { | |
8612006b | 3806 | int fmt = FMT; |
9b17d183 | 3807 | check_fpu (SD_); |
8612006b CD |
3808 | check_fmt_p (SD_, fmt, instruction_0); |
3809 | do_c_cond_fmt (SD_, fmt, FT, FS, CC, COND, instruction_0); | |
c906108c SS |
3810 | } |
3811 | ||
3812 | ||
eb5fcf93 | 3813 | 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt |
c906108c SS |
3814 | "ceil.l.%s<FMT> f<FD>, f<FS>" |
3815 | *mipsIII: | |
3816 | *mipsIV: | |
603a98e7 | 3817 | *mipsV: |
1e799e28 | 3818 | *mips64: |
c906108c SS |
3819 | *vr4100: |
3820 | *vr5000: | |
3821 | *r3900: | |
3822 | { | |
c1e8ada4 | 3823 | int fmt = FMT; |
9b17d183 | 3824 | check_fpu (SD_); |
8612006b CD |
3825 | check_fmt (SD_, fmt, instruction_0); |
3826 | StoreFPR(FD,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_long)); | |
c906108c SS |
3827 | } |
3828 | ||
3829 | ||
eb5fcf93 | 3830 | 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W |
c906108c SS |
3831 | *mipsII: |
3832 | *mipsIII: | |
3833 | *mipsIV: | |
603a98e7 | 3834 | *mipsV: |
1e799e28 CD |
3835 | *mips32: |
3836 | *mips64: | |
c906108c SS |
3837 | *vr4100: |
3838 | *vr5000: | |
3839 | *r3900: | |
3840 | { | |
c1e8ada4 | 3841 | int fmt = FMT; |
9b17d183 | 3842 | check_fpu (SD_); |
8612006b CD |
3843 | check_fmt (SD_, fmt, instruction_0); |
3844 | StoreFPR(FD,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_word)); | |
c906108c SS |
3845 | } |
3846 | ||
3847 | ||
3848 | // CFC1 | |
3849 | // CTC1 | |
eb5fcf93 | 3850 | 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32,f::CxC1 |
c906108c SS |
3851 | "c%s<X>c1 r<RT>, f<FS>" |
3852 | *mipsI: | |
3853 | *mipsII: | |
3854 | *mipsIII: | |
3855 | { | |
9b17d183 | 3856 | check_fpu (SD_); |
c906108c SS |
3857 | if (X) |
3858 | { | |
3859 | if (FS == 0) | |
c0efbca4 | 3860 | PENDING_FILL(FCR0IDX,VL4_8(GPR[RT])); |
c906108c | 3861 | else if (FS == 31) |
c0efbca4 | 3862 | PENDING_FILL(FCR31IDX,VL4_8(GPR[RT])); |
c906108c | 3863 | /* else NOP */ |
c0efbca4 | 3864 | PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23); |
c906108c SS |
3865 | } |
3866 | else | |
3867 | { /* control from */ | |
3868 | if (FS == 0) | |
043b7057 | 3869 | PENDING_FILL(RT, EXTEND32 (FCR0)); |
c906108c | 3870 | else if (FS == 31) |
043b7057 | 3871 | PENDING_FILL(RT, EXTEND32 (FCR31)); |
c906108c SS |
3872 | /* else NOP */ |
3873 | } | |
3874 | } | |
eb5fcf93 | 3875 | 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32,f::CxC1 |
c906108c SS |
3876 | "c%s<X>c1 r<RT>, f<FS>" |
3877 | *mipsIV: | |
603a98e7 | 3878 | *mipsV: |
1e799e28 CD |
3879 | *mips32: |
3880 | *mips64: | |
c906108c SS |
3881 | *vr4100: |
3882 | *vr5000: | |
3883 | *r3900: | |
3884 | { | |
9b17d183 | 3885 | check_fpu (SD_); |
c906108c SS |
3886 | if (X) |
3887 | { | |
3888 | /* control to */ | |
3889 | TRACE_ALU_INPUT1 (GPR[RT]); | |
3890 | if (FS == 0) | |
3891 | { | |
3892 | FCR0 = VL4_8(GPR[RT]); | |
3893 | TRACE_ALU_RESULT (FCR0); | |
3894 | } | |
3895 | else if (FS == 31) | |
3896 | { | |
3897 | FCR31 = VL4_8(GPR[RT]); | |
3898 | SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0)); | |
3899 | TRACE_ALU_RESULT (FCR31); | |
3900 | } | |
3901 | else | |
3902 | { | |
3903 | TRACE_ALU_RESULT0 (); | |
3904 | } | |
3905 | /* else NOP */ | |
3906 | } | |
3907 | else | |
3908 | { /* control from */ | |
3909 | if (FS == 0) | |
3910 | { | |
3911 | TRACE_ALU_INPUT1 (FCR0); | |
043b7057 | 3912 | GPR[RT] = EXTEND32 (FCR0); |
c906108c SS |
3913 | } |
3914 | else if (FS == 31) | |
3915 | { | |
3916 | TRACE_ALU_INPUT1 (FCR31); | |
043b7057 | 3917 | GPR[RT] = EXTEND32 (FCR31); |
c906108c SS |
3918 | } |
3919 | TRACE_ALU_RESULT (GPR[RT]); | |
3920 | /* else NOP */ | |
3921 | } | |
3922 | } | |
3923 | ||
3924 | ||
3925 | // | |
3926 | // FIXME: Does not correctly differentiate between mips* | |
3927 | // | |
eb5fcf93 | 3928 | 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt |
c906108c | 3929 | "cvt.d.%s<FMT> f<FD>, f<FS>" |
c5d00cc7 CD |
3930 | *mipsI: |
3931 | *mipsII: | |
3932 | *mipsIII: | |
3933 | *mipsIV: | |
603a98e7 | 3934 | *mipsV: |
1e799e28 CD |
3935 | *mips32: |
3936 | *mips64: | |
c906108c SS |
3937 | *vr4100: |
3938 | *vr5000: | |
3939 | *r3900: | |
3940 | { | |
c1e8ada4 | 3941 | int fmt = FMT; |
9b17d183 | 3942 | check_fpu (SD_); |
c906108c | 3943 | { |
c1e8ada4 | 3944 | if ((fmt == fmt_double) | 0) |
86b77b47 | 3945 | SignalException (ReservedInstruction, instruction_0); |
c906108c | 3946 | else |
c1e8ada4 | 3947 | StoreFPR(FD,fmt_double,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_double)); |
c906108c SS |
3948 | } |
3949 | } | |
3950 | ||
3951 | ||
eb5fcf93 | 3952 | 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt |
c906108c SS |
3953 | "cvt.l.%s<FMT> f<FD>, f<FS>" |
3954 | *mipsIII: | |
3955 | *mipsIV: | |
603a98e7 | 3956 | *mipsV: |
1e799e28 | 3957 | *mips64: |
c906108c SS |
3958 | *vr4100: |
3959 | *vr5000: | |
3960 | *r3900: | |
3961 | { | |
c1e8ada4 | 3962 | int fmt = FMT; |
9b17d183 | 3963 | check_fpu (SD_); |
c906108c | 3964 | { |
c1e8ada4 | 3965 | if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word))) |
86b77b47 | 3966 | SignalException (ReservedInstruction, instruction_0); |
c906108c | 3967 | else |
c1e8ada4 | 3968 | StoreFPR(FD,fmt_long,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_long)); |
c906108c SS |
3969 | } |
3970 | } | |
3971 | ||
3972 | ||
3973 | // | |
3974 | // FIXME: Does not correctly differentiate between mips* | |
3975 | // | |
eb5fcf93 | 3976 | 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt |
c906108c | 3977 | "cvt.s.%s<FMT> f<FD>, f<FS>" |
c5d00cc7 CD |
3978 | *mipsI: |
3979 | *mipsII: | |
3980 | *mipsIII: | |
3981 | *mipsIV: | |
603a98e7 | 3982 | *mipsV: |
1e799e28 CD |
3983 | *mips32: |
3984 | *mips64: | |
c906108c SS |
3985 | *vr4100: |
3986 | *vr5000: | |
3987 | *r3900: | |
3988 | { | |
c1e8ada4 | 3989 | int fmt = FMT; |
9b17d183 | 3990 | check_fpu (SD_); |
c906108c | 3991 | { |
c1e8ada4 | 3992 | if ((fmt == fmt_single) | 0) |
86b77b47 | 3993 | SignalException (ReservedInstruction, instruction_0); |
c906108c | 3994 | else |
c1e8ada4 | 3995 | StoreFPR(FD,fmt_single,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_single)); |
c906108c SS |
3996 | } |
3997 | } | |
3998 | ||
3999 | ||
eb5fcf93 | 4000 | 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt |
c906108c | 4001 | "cvt.w.%s<FMT> f<FD>, f<FS>" |
c5d00cc7 CD |
4002 | *mipsI: |
4003 | *mipsII: | |
4004 | *mipsIII: | |
4005 | *mipsIV: | |
603a98e7 | 4006 | *mipsV: |
1e799e28 CD |
4007 | *mips32: |
4008 | *mips64: | |
c906108c SS |
4009 | *vr4100: |
4010 | *vr5000: | |
4011 | *r3900: | |
4012 | { | |
c1e8ada4 | 4013 | int fmt = FMT; |
9b17d183 | 4014 | check_fpu (SD_); |
c906108c | 4015 | { |
c1e8ada4 | 4016 | if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word))) |
86b77b47 | 4017 | SignalException (ReservedInstruction, instruction_0); |
c906108c | 4018 | else |
c1e8ada4 | 4019 | StoreFPR(FD,fmt_word,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_word)); |
c906108c SS |
4020 | } |
4021 | } | |
4022 | ||
4023 | ||
eb5fcf93 | 4024 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt |
c906108c | 4025 | "div.%s<FMT> f<FD>, f<FS>, f<FT>" |
c5d00cc7 CD |
4026 | *mipsI: |
4027 | *mipsII: | |
4028 | *mipsIII: | |
4029 | *mipsIV: | |
603a98e7 | 4030 | *mipsV: |
1e799e28 CD |
4031 | *mips32: |
4032 | *mips64: | |
c906108c SS |
4033 | *vr4100: |
4034 | *vr5000: | |
4035 | *r3900: | |
4036 | { | |
c1e8ada4 | 4037 | int fmt = FMT; |
9b17d183 | 4038 | check_fpu (SD_); |
8612006b CD |
4039 | check_fmt (SD_, fmt, instruction_0); |
4040 | StoreFPR(FD,fmt,Divide(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt)); | |
c906108c SS |
4041 | } |
4042 | ||
4043 | ||
4044 | // DMFC1 | |
4045 | // DMTC1 | |
eb5fcf93 | 4046 | 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64,f::DMxC1 |
c906108c SS |
4047 | "dm%s<X>c1 r<RT>, f<FS>" |
4048 | *mipsIII: | |
4049 | { | |
9b17d183 | 4050 | check_fpu (SD_); |
ca971540 | 4051 | check_u64 (SD_, instruction_0); |
c906108c SS |
4052 | if (X) |
4053 | { | |
4054 | if (SizeFGR() == 64) | |
4055 | PENDING_FILL((FS + FGRIDX),GPR[RT]); | |
4056 | else if ((FS & 0x1) == 0) | |
4057 | { | |
4058 | PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT])); | |
4059 | PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT])); | |
4060 | } | |
4061 | } | |
4062 | else | |
4063 | { | |
4064 | if (SizeFGR() == 64) | |
4065 | PENDING_FILL(RT,FGR[FS]); | |
4066 | else if ((FS & 0x1) == 0) | |
4067 | PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS])); | |
4068 | else | |
a3027dd7 FCE |
4069 | { |
4070 | if (STATE_VERBOSE_P(SD)) | |
4a0bd876 | 4071 | sim_io_eprintf (SD, |
673388c0 AC |
4072 | "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n", |
4073 | (long) CIA); | |
a3027dd7 FCE |
4074 | PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0); |
4075 | } | |
c906108c SS |
4076 | } |
4077 | } | |
eb5fcf93 | 4078 | 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64,f::DMxC1 |
c906108c SS |
4079 | "dm%s<X>c1 r<RT>, f<FS>" |
4080 | *mipsIV: | |
603a98e7 | 4081 | *mipsV: |
1e799e28 | 4082 | *mips64: |
c906108c SS |
4083 | *vr4100: |
4084 | *vr5000: | |
4085 | *r3900: | |
4086 | { | |
9b17d183 | 4087 | check_fpu (SD_); |
ca971540 | 4088 | check_u64 (SD_, instruction_0); |
c906108c SS |
4089 | if (X) |
4090 | { | |
4091 | if (SizeFGR() == 64) | |
4092 | StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]); | |
4093 | else if ((FS & 0x1) == 0) | |
4094 | StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]); | |
4095 | } | |
4096 | else | |
4097 | { | |
4098 | if (SizeFGR() == 64) | |
4099 | GPR[RT] = FGR[FS]; | |
4100 | else if ((FS & 0x1) == 0) | |
4101 | GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS]; | |
4102 | else | |
a3027dd7 FCE |
4103 | { |
4104 | if (STATE_VERBOSE_P(SD)) | |
4a0bd876 | 4105 | sim_io_eprintf (SD, |
dd37a34b AC |
4106 | "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n", |
4107 | (long) CIA); | |
a3027dd7 FCE |
4108 | GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; |
4109 | } | |
c906108c SS |
4110 | } |
4111 | } | |
4112 | ||
4113 | ||
eb5fcf93 | 4114 | 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt |
c906108c SS |
4115 | "floor.l.%s<FMT> f<FD>, f<FS>" |
4116 | *mipsIII: | |
4117 | *mipsIV: | |
603a98e7 | 4118 | *mipsV: |
1e799e28 | 4119 | *mips64: |
c906108c SS |
4120 | *vr4100: |
4121 | *vr5000: | |
4122 | *r3900: | |
4123 | { | |
c1e8ada4 | 4124 | int fmt = FMT; |
9b17d183 | 4125 | check_fpu (SD_); |
8612006b CD |
4126 | check_fmt (SD_, fmt, instruction_0); |
4127 | StoreFPR(FD,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_long)); | |
c906108c SS |
4128 | } |
4129 | ||
4130 | ||
eb5fcf93 | 4131 | 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt |
c906108c SS |
4132 | "floor.w.%s<FMT> f<FD>, f<FS>" |
4133 | *mipsII: | |
4134 | *mipsIII: | |
4135 | *mipsIV: | |
603a98e7 | 4136 | *mipsV: |
1e799e28 CD |
4137 | *mips32: |
4138 | *mips64: | |
c906108c SS |
4139 | *vr4100: |
4140 | *vr5000: | |
4141 | *r3900: | |
4142 | { | |
c1e8ada4 | 4143 | int fmt = FMT; |
9b17d183 | 4144 | check_fpu (SD_); |
8612006b CD |
4145 | check_fmt (SD_, fmt, instruction_0); |
4146 | StoreFPR(FD,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_word)); | |
c906108c SS |
4147 | } |
4148 | ||
4149 | ||
387f484a | 4150 | 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1 |
c906108c SS |
4151 | "ldc1 f<FT>, <OFFSET>(r<BASE>)" |
4152 | *mipsII: | |
4153 | *mipsIII: | |
4154 | *mipsIV: | |
603a98e7 | 4155 | *mipsV: |
1e799e28 CD |
4156 | *mips32: |
4157 | *mips64: | |
c906108c SS |
4158 | *vr4100: |
4159 | *vr5000: | |
4160 | *r3900: | |
4161 | { | |
9b17d183 | 4162 | check_fpu (SD_); |
c906108c SS |
4163 | COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); |
4164 | } | |
4165 | ||
4166 | ||
eb5fcf93 | 4167 | 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1 |
c906108c SS |
4168 | "ldxc1 f<FD>, r<INDEX>(r<BASE>)" |
4169 | *mipsIV: | |
603a98e7 | 4170 | *mipsV: |
1e799e28 | 4171 | *mips64: |
c906108c SS |
4172 | *vr5000: |
4173 | { | |
9b17d183 | 4174 | check_fpu (SD_); |
ca971540 | 4175 | check_u64 (SD_, instruction_0); |
c906108c SS |
4176 | COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX])); |
4177 | } | |
4178 | ||
4179 | ||
4180 | ||
4a0bd876 | 4181 | 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1 |
c906108c | 4182 | "lwc1 f<FT>, <OFFSET>(r<BASE>)" |
c5d00cc7 CD |
4183 | *mipsI: |
4184 | *mipsII: | |
4185 | *mipsIII: | |
4186 | *mipsIV: | |
603a98e7 | 4187 | *mipsV: |
1e799e28 CD |
4188 | *mips32: |
4189 | *mips64: | |
c906108c SS |
4190 | *vr4100: |
4191 | *vr5000: | |
4192 | *r3900: | |
4193 | { | |
9b17d183 | 4194 | check_fpu (SD_); |
c906108c SS |
4195 | COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); |
4196 | } | |
4197 | ||
4198 | ||
eb5fcf93 | 4199 | 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1 |
c906108c SS |
4200 | "lwxc1 f<FD>, r<INDEX>(r<BASE>)" |
4201 | *mipsIV: | |
603a98e7 | 4202 | *mipsV: |
1e799e28 | 4203 | *mips64: |
c906108c SS |
4204 | *vr5000: |
4205 | { | |
9b17d183 | 4206 | check_fpu (SD_); |
ca971540 | 4207 | check_u64 (SD_, instruction_0); |
c906108c SS |
4208 | COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX])); |
4209 | } | |
4210 | ||
4211 | ||
4212 | ||
4213 | // | |
4214 | // FIXME: Not correct for mips* | |
4215 | // | |
4216 | 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D | |
4217 | "madd.d f<FD>, f<FR>, f<FS>, f<FT>" | |
4218 | *mipsIV: | |
603a98e7 | 4219 | *mipsV: |
1e799e28 | 4220 | *mips64: |
c906108c SS |
4221 | *vr5000: |
4222 | { | |
9b17d183 | 4223 | check_fpu (SD_); |
c906108c | 4224 | { |
c1e8ada4 | 4225 | StoreFPR(FD,fmt_double,Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double)); |
c906108c SS |
4226 | } |
4227 | } | |
4228 | ||
4229 | ||
4230 | 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S | |
4231 | "madd.s f<FD>, f<FR>, f<FS>, f<FT>" | |
4232 | *mipsIV: | |
603a98e7 | 4233 | *mipsV: |
1e799e28 | 4234 | *mips64: |
c906108c SS |
4235 | *vr5000: |
4236 | { | |
9b17d183 | 4237 | check_fpu (SD_); |
c906108c | 4238 | { |
c1e8ada4 | 4239 | StoreFPR(FD,fmt_single,Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single)); |
c906108c SS |
4240 | } |
4241 | } | |
4242 | ||
4243 | ||
4244 | // MFC1 | |
4245 | // MTC1 | |
eb5fcf93 | 4246 | 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32,f::MxC1 |
c906108c SS |
4247 | "m%s<X>c1 r<RT>, f<FS>" |
4248 | *mipsI: | |
4249 | *mipsII: | |
4250 | *mipsIII: | |
4251 | { | |
9b17d183 | 4252 | check_fpu (SD_); |
c906108c SS |
4253 | if (X) |
4254 | { /*MTC1*/ | |
4255 | if (SizeFGR() == 64) | |
a3027dd7 FCE |
4256 | { |
4257 | if (STATE_VERBOSE_P(SD)) | |
4a0bd876 | 4258 | sim_io_eprintf (SD, |
673388c0 AC |
4259 | "Warning: PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n", |
4260 | (long) CIA); | |
a3027dd7 FCE |
4261 | PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT]))); |
4262 | } | |
c906108c SS |
4263 | else |
4264 | PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT])); | |
4265 | } | |
4266 | else /*MFC1*/ | |
043b7057 | 4267 | PENDING_FILL (RT, EXTEND32 (FGR[FS])); |
c906108c | 4268 | } |
eb5fcf93 | 4269 | 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1 |
c906108c SS |
4270 | "m%s<X>c1 r<RT>, f<FS>" |
4271 | *mipsIV: | |
603a98e7 | 4272 | *mipsV: |
1e799e28 CD |
4273 | *mips32: |
4274 | *mips64: | |
c906108c SS |
4275 | *vr4100: |
4276 | *vr5000: | |
4277 | *r3900: | |
4278 | { | |
4279 | int fs = FS; | |
9b17d183 | 4280 | check_fpu (SD_); |
c906108c SS |
4281 | if (X) |
4282 | /*MTC1*/ | |
4283 | StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT])); | |
4284 | else /*MFC1*/ | |
043b7057 | 4285 | GPR[RT] = EXTEND32 (FGR[FS]); |
c906108c SS |
4286 | } |
4287 | ||
4288 | ||
eb5fcf93 | 4289 | 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt |
c906108c | 4290 | "mov.%s<FMT> f<FD>, f<FS>" |
c5d00cc7 CD |
4291 | *mipsI: |
4292 | *mipsII: | |
4293 | *mipsIII: | |
4294 | *mipsIV: | |
603a98e7 | 4295 | *mipsV: |
1e799e28 CD |
4296 | *mips32: |
4297 | *mips64: | |
c906108c SS |
4298 | *vr4100: |
4299 | *vr5000: | |
4300 | *r3900: | |
4301 | { | |
c1e8ada4 | 4302 | int fmt = FMT; |
9b17d183 | 4303 | check_fpu (SD_); |
8612006b | 4304 | check_fmt_p (SD_, fmt, instruction_0); |
c1e8ada4 | 4305 | StoreFPR(FD,fmt,ValueFPR(FS,fmt)); |
c906108c SS |
4306 | } |
4307 | ||
4308 | ||
4309 | // MOVF | |
c2d11a7d | 4310 | // MOVT |
eb5fcf93 | 4311 | 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf |
c906108c SS |
4312 | "mov%s<TF> r<RD>, r<RS>, <CC>" |
4313 | *mipsIV: | |
603a98e7 | 4314 | *mipsV: |
1e799e28 CD |
4315 | *mips32: |
4316 | *mips64: | |
c906108c SS |
4317 | *vr5000: |
4318 | { | |
9b17d183 | 4319 | check_fpu (SD_); |
c906108c SS |
4320 | if (GETFCC(CC) == TF) |
4321 | GPR[RD] = GPR[RS]; | |
4322 | } | |
4323 | ||
4324 | ||
4325 | // MOVF.fmt | |
c2d11a7d | 4326 | // MOVT.fmt |
eb5fcf93 | 4327 | 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt |
c906108c SS |
4328 | "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>" |
4329 | *mipsIV: | |
603a98e7 | 4330 | *mipsV: |
1e799e28 CD |
4331 | *mips32: |
4332 | *mips64: | |
c906108c SS |
4333 | *vr5000: |
4334 | { | |
c1e8ada4 | 4335 | int fmt = FMT; |
9b17d183 | 4336 | check_fpu (SD_); |
c906108c SS |
4337 | { |
4338 | if (GETFCC(CC) == TF) | |
c1e8ada4 | 4339 | StoreFPR (FD, fmt, ValueFPR (FS, fmt)); |
c906108c | 4340 | else |
c1e8ada4 | 4341 | StoreFPR (FD, fmt, ValueFPR (FD, fmt)); |
c906108c SS |
4342 | } |
4343 | } | |
4344 | ||
4345 | ||
eb5fcf93 | 4346 | 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt |
80ee11fa | 4347 | "movn.%s<FMT> f<FD>, f<FS>, r<RT>" |
c906108c | 4348 | *mipsIV: |
603a98e7 | 4349 | *mipsV: |
1e799e28 CD |
4350 | *mips32: |
4351 | *mips64: | |
c906108c SS |
4352 | *vr5000: |
4353 | { | |
9b17d183 | 4354 | check_fpu (SD_); |
80ee11fa AC |
4355 | if (GPR[RT] != 0) |
4356 | StoreFPR (FD, FMT, ValueFPR (FS, FMT)); | |
4357 | else | |
4358 | StoreFPR (FD, FMT, ValueFPR (FD, FMT)); | |
c906108c SS |
4359 | } |
4360 | ||
4361 | ||
4362 | // MOVT see MOVtf | |
4363 | ||
4364 | ||
4365 | // MOVT.fmt see MOVtf.fmt | |
4366 | ||
4367 | ||
4368 | ||
eb5fcf93 | 4369 | 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt |
c906108c SS |
4370 | "movz.%s<FMT> f<FD>, f<FS>, r<RT>" |
4371 | *mipsIV: | |
603a98e7 | 4372 | *mipsV: |
1e799e28 CD |
4373 | *mips32: |
4374 | *mips64: | |
c906108c SS |
4375 | *vr5000: |
4376 | { | |
9b17d183 | 4377 | check_fpu (SD_); |
80ee11fa AC |
4378 | if (GPR[RT] == 0) |
4379 | StoreFPR (FD, FMT, ValueFPR (FS, FMT)); | |
4380 | else | |
4381 | StoreFPR (FD, FMT, ValueFPR (FD, FMT)); | |
c906108c SS |
4382 | } |
4383 | ||
4384 | ||
4385 | // MSUB.fmt | |
eb5fcf93 | 4386 | 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32,f::MSUB.D |
c906108c SS |
4387 | "msub.d f<FD>, f<FR>, f<FS>, f<FT>" |
4388 | *mipsIV: | |
603a98e7 | 4389 | *mipsV: |
1e799e28 | 4390 | *mips64: |
c906108c SS |
4391 | *vr5000: |
4392 | { | |
9b17d183 | 4393 | check_fpu (SD_); |
c1e8ada4 | 4394 | StoreFPR(FD,fmt_double,Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double)); |
c906108c SS |
4395 | } |
4396 | ||
4397 | ||
4398 | // MSUB.fmt | |
eb5fcf93 | 4399 | 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32,f::MSUB.S |
c906108c SS |
4400 | "msub.s f<FD>, f<FR>, f<FS>, f<FT>" |
4401 | *mipsIV: | |
603a98e7 | 4402 | *mipsV: |
1e799e28 | 4403 | *mips64: |
c906108c SS |
4404 | *vr5000: |
4405 | { | |
9b17d183 | 4406 | check_fpu (SD_); |
c1e8ada4 | 4407 | StoreFPR(FD,fmt_single,Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single)); |
c906108c SS |
4408 | } |
4409 | ||
4410 | ||
4411 | // MTC1 see MxC1 | |
4412 | ||
4413 | ||
eb5fcf93 | 4414 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt |
c906108c | 4415 | "mul.%s<FMT> f<FD>, f<FS>, f<FT>" |
c5d00cc7 CD |
4416 | *mipsI: |
4417 | *mipsII: | |
4418 | *mipsIII: | |
4419 | *mipsIV: | |
603a98e7 | 4420 | *mipsV: |
1e799e28 CD |
4421 | *mips32: |
4422 | *mips64: | |
c906108c SS |
4423 | *vr4100: |
4424 | *vr5000: | |
4425 | *r3900: | |
4426 | { | |
c1e8ada4 | 4427 | int fmt = FMT; |
9b17d183 | 4428 | check_fpu (SD_); |
8612006b CD |
4429 | check_fmt_p (SD_, fmt, instruction_0); |
4430 | StoreFPR(FD,fmt,Multiply(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt)); | |
c906108c SS |
4431 | } |
4432 | ||
4433 | ||
eb5fcf93 | 4434 | 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt |
c906108c | 4435 | "neg.%s<FMT> f<FD>, f<FS>" |
c5d00cc7 CD |
4436 | *mipsI: |
4437 | *mipsII: | |
4438 | *mipsIII: | |
4439 | *mipsIV: | |
603a98e7 | 4440 | *mipsV: |
1e799e28 CD |
4441 | *mips32: |
4442 | *mips64: | |
c906108c SS |
4443 | *vr4100: |
4444 | *vr5000: | |
4445 | *r3900: | |
4446 | { | |
c1e8ada4 | 4447 | int fmt = FMT; |
9b17d183 | 4448 | check_fpu (SD_); |
8612006b CD |
4449 | check_fmt_p (SD_, fmt, instruction_0); |
4450 | StoreFPR(FD,fmt,Negate(ValueFPR(FS,fmt),fmt)); | |
c906108c SS |
4451 | } |
4452 | ||
4453 | ||
4454 | // NMADD.fmt | |
eb5fcf93 | 4455 | 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32,f::NMADD.D |
c906108c SS |
4456 | "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>" |
4457 | *mipsIV: | |
603a98e7 | 4458 | *mipsV: |
1e799e28 | 4459 | *mips64: |
c906108c SS |
4460 | *vr5000: |
4461 | { | |
9b17d183 | 4462 | check_fpu (SD_); |
c1e8ada4 | 4463 | StoreFPR(FD,fmt_double,Negate(Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double)); |
c906108c SS |
4464 | } |
4465 | ||
4466 | ||
4467 | // NMADD.fmt | |
eb5fcf93 | 4468 | 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32,f::NMADD.S |
c906108c SS |
4469 | "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>" |
4470 | *mipsIV: | |
603a98e7 | 4471 | *mipsV: |
1e799e28 | 4472 | *mips64: |
c906108c SS |
4473 | *vr5000: |
4474 | { | |
9b17d183 | 4475 | check_fpu (SD_); |
c1e8ada4 | 4476 | StoreFPR(FD,fmt_single,Negate(Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single)); |
c906108c SS |
4477 | } |
4478 | ||
4479 | ||
4480 | // NMSUB.fmt | |
eb5fcf93 | 4481 | 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32,f::NMSUB.D |
c906108c SS |
4482 | "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>" |
4483 | *mipsIV: | |
603a98e7 | 4484 | *mipsV: |
1e799e28 | 4485 | *mips64: |
c906108c SS |
4486 | *vr5000: |
4487 | { | |
9b17d183 | 4488 | check_fpu (SD_); |
c1e8ada4 | 4489 | StoreFPR(FD,fmt_double,Negate(Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double)); |
c906108c SS |
4490 | } |
4491 | ||
4492 | ||
4493 | // NMSUB.fmt | |
eb5fcf93 | 4494 | 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32,f::NMSUB.S |
c906108c SS |
4495 | "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>" |
4496 | *mipsIV: | |
603a98e7 | 4497 | *mipsV: |
1e799e28 | 4498 | *mips64: |
c906108c SS |
4499 | *vr5000: |
4500 | { | |
9b17d183 | 4501 | check_fpu (SD_); |
c1e8ada4 | 4502 | StoreFPR(FD,fmt_single,Negate(Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single)); |
c906108c SS |
4503 | } |
4504 | ||
4505 | ||
3d81f391 | 4506 | 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX |
c906108c SS |
4507 | "prefx <HINT>, r<INDEX>(r<BASE>)" |
4508 | *mipsIV: | |
603a98e7 | 4509 | *mipsV: |
1e799e28 | 4510 | *mips64: |
c906108c SS |
4511 | *vr5000: |
4512 | { | |
c1e8ada4 CD |
4513 | address_word base = GPR[BASE]; |
4514 | address_word index = GPR[INDEX]; | |
c906108c | 4515 | { |
09297648 | 4516 | address_word vaddr = loadstore_ea (SD_, base, index); |
c906108c SS |
4517 | address_word paddr; |
4518 | int uncached; | |
4519 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
c1e8ada4 | 4520 | Prefetch(uncached,paddr,vaddr,isDATA,HINT); |
c906108c SS |
4521 | } |
4522 | } | |
4523 | ||
eb5fcf93 | 4524 | 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt |
c906108c | 4525 | "recip.%s<FMT> f<FD>, f<FS>" |
e514a9d6 | 4526 | *mipsIV: |
603a98e7 | 4527 | *mipsV: |
1e799e28 | 4528 | *mips64: |
c906108c SS |
4529 | *vr5000: |
4530 | { | |
c1e8ada4 | 4531 | int fmt = FMT; |
9b17d183 | 4532 | check_fpu (SD_); |
8612006b CD |
4533 | check_fmt (SD_, fmt, instruction_0); |
4534 | StoreFPR(FD,fmt,Recip(ValueFPR(FS,fmt),fmt)); | |
c906108c SS |
4535 | } |
4536 | ||
4537 | ||
eb5fcf93 | 4538 | 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt |
c906108c SS |
4539 | "round.l.%s<FMT> f<FD>, f<FS>" |
4540 | *mipsIII: | |
4541 | *mipsIV: | |
603a98e7 | 4542 | *mipsV: |
1e799e28 | 4543 | *mips64: |
c906108c SS |
4544 | *vr4100: |
4545 | *vr5000: | |
4546 | *r3900: | |
4547 | { | |
c1e8ada4 | 4548 | int fmt = FMT; |
9b17d183 | 4549 | check_fpu (SD_); |
8612006b CD |
4550 | check_fmt (SD_, fmt, instruction_0); |
4551 | StoreFPR(FD,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_long)); | |
c906108c SS |
4552 | } |
4553 | ||
4554 | ||
eb5fcf93 | 4555 | 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt |
c906108c SS |
4556 | "round.w.%s<FMT> f<FD>, f<FS>" |
4557 | *mipsII: | |
4558 | *mipsIII: | |
4559 | *mipsIV: | |
603a98e7 | 4560 | *mipsV: |
1e799e28 CD |
4561 | *mips32: |
4562 | *mips64: | |
c906108c SS |
4563 | *vr4100: |
4564 | *vr5000: | |
4565 | *r3900: | |
4566 | { | |
c1e8ada4 | 4567 | int fmt = FMT; |
9b17d183 | 4568 | check_fpu (SD_); |
8612006b CD |
4569 | check_fmt (SD_, fmt, instruction_0); |
4570 | StoreFPR(FD,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_word)); | |
c906108c SS |
4571 | } |
4572 | ||
4573 | ||
eb5fcf93 | 4574 | 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt |
c906108c | 4575 | *mipsIV: |
603a98e7 | 4576 | *mipsV: |
1e799e28 | 4577 | *mips64: |
c906108c SS |
4578 | "rsqrt.%s<FMT> f<FD>, f<FS>" |
4579 | *vr5000: | |
4580 | { | |
c1e8ada4 | 4581 | int fmt = FMT; |
9b17d183 | 4582 | check_fpu (SD_); |
8612006b CD |
4583 | check_fmt (SD_, fmt, instruction_0); |
4584 | StoreFPR(FD,fmt,Recip(SquareRoot(ValueFPR(FS,fmt),fmt),fmt)); | |
c906108c SS |
4585 | } |
4586 | ||
4587 | ||
387f484a | 4588 | 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1 |
c906108c SS |
4589 | "sdc1 f<FT>, <OFFSET>(r<BASE>)" |
4590 | *mipsII: | |
4591 | *mipsIII: | |
4592 | *mipsIV: | |
603a98e7 | 4593 | *mipsV: |
1e799e28 CD |
4594 | *mips32: |
4595 | *mips64: | |
c906108c SS |
4596 | *vr4100: |
4597 | *vr5000: | |
4598 | *r3900: | |
4599 | { | |
9b17d183 | 4600 | check_fpu (SD_); |
c906108c SS |
4601 | do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT)); |
4602 | } | |
4603 | ||
4604 | ||
eb5fcf93 | 4605 | 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1 |
91a177cf | 4606 | "sdxc1 f<FS>, r<INDEX>(r<BASE>)" |
c906108c | 4607 | *mipsIV: |
603a98e7 | 4608 | *mipsV: |
1e799e28 | 4609 | *mips64: |
c906108c SS |
4610 | *vr5000: |
4611 | { | |
9b17d183 | 4612 | check_fpu (SD_); |
ca971540 | 4613 | check_u64 (SD_, instruction_0); |
c906108c SS |
4614 | do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS)); |
4615 | } | |
4616 | ||
4617 | ||
eb5fcf93 | 4618 | 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt |
c906108c SS |
4619 | "sqrt.%s<FMT> f<FD>, f<FS>" |
4620 | *mipsII: | |
4621 | *mipsIII: | |
4622 | *mipsIV: | |
603a98e7 | 4623 | *mipsV: |
1e799e28 CD |
4624 | *mips32: |
4625 | *mips64: | |
c906108c SS |
4626 | *vr4100: |
4627 | *vr5000: | |
4628 | *r3900: | |
4629 | { | |
c1e8ada4 | 4630 | int fmt = FMT; |
9b17d183 | 4631 | check_fpu (SD_); |
8612006b CD |
4632 | check_fmt (SD_, fmt, instruction_0); |
4633 | StoreFPR(FD,fmt,(SquareRoot(ValueFPR(FS,fmt),fmt))); | |
c906108c SS |
4634 | } |
4635 | ||
4636 | ||
eb5fcf93 | 4637 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt |
c906108c | 4638 | "sub.%s<FMT> f<FD>, f<FS>, f<FT>" |
c5d00cc7 CD |
4639 | *mipsI: |
4640 | *mipsII: | |
4641 | *mipsIII: | |
4642 | *mipsIV: | |
603a98e7 | 4643 | *mipsV: |
1e799e28 CD |
4644 | *mips32: |
4645 | *mips64: | |
c906108c SS |
4646 | *vr4100: |
4647 | *vr5000: | |
4648 | *r3900: | |
4649 | { | |
c1e8ada4 | 4650 | int fmt = FMT; |
9b17d183 | 4651 | check_fpu (SD_); |
8612006b CD |
4652 | check_fmt_p (SD_, fmt, instruction_0); |
4653 | StoreFPR(FD,fmt,Sub(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt)); | |
c906108c SS |
4654 | } |
4655 | ||
4656 | ||
4657 | ||
eb5fcf93 | 4658 | 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1 |
c906108c | 4659 | "swc1 f<FT>, <OFFSET>(r<BASE>)" |
c5d00cc7 CD |
4660 | *mipsI: |
4661 | *mipsII: | |
4662 | *mipsIII: | |
4663 | *mipsIV: | |
603a98e7 | 4664 | *mipsV: |
1e799e28 CD |
4665 | *mips32: |
4666 | *mips64: | |
c906108c SS |
4667 | *vr4100: |
4668 | *vr5000: | |
4669 | *r3900: | |
4670 | { | |
09297648 CD |
4671 | address_word base = GPR[BASE]; |
4672 | address_word offset = EXTEND16 (OFFSET); | |
9b17d183 | 4673 | check_fpu (SD_); |
c906108c | 4674 | { |
09297648 | 4675 | address_word vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
4676 | address_word paddr; |
4677 | int uncached; | |
4678 | if ((vaddr & 3) != 0) | |
4679 | { | |
4680 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal); | |
4681 | } | |
4682 | else | |
4683 | { | |
4684 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
4685 | { | |
4686 | uword64 memval = 0; | |
4687 | uword64 memval1 = 0; | |
4688 | uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); | |
4689 | address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0); | |
4690 | address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0); | |
4691 | unsigned int byte; | |
4692 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); | |
4693 | byte = ((vaddr & mask) ^ bigendiancpu); | |
c1e8ada4 | 4694 | memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte)); |
c906108c SS |
4695 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); |
4696 | } | |
4697 | } | |
4698 | } | |
4699 | } | |
4700 | ||
4701 | ||
eb5fcf93 | 4702 | 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1 |
c906108c SS |
4703 | "swxc1 f<FS>, r<INDEX>(r<BASE>)" |
4704 | *mipsIV: | |
603a98e7 | 4705 | *mipsV: |
1e799e28 | 4706 | *mips64: |
c906108c SS |
4707 | *vr5000: |
4708 | { | |
c1e8ada4 CD |
4709 | |
4710 | address_word base = GPR[BASE]; | |
4711 | address_word index = GPR[INDEX]; | |
9b17d183 | 4712 | check_fpu (SD_); |
ca971540 | 4713 | check_u64 (SD_, instruction_0); |
c906108c | 4714 | { |
09297648 | 4715 | address_word vaddr = loadstore_ea (SD_, base, index); |
c906108c SS |
4716 | address_word paddr; |
4717 | int uncached; | |
4718 | if ((vaddr & 3) != 0) | |
4719 | { | |
4720 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal); | |
4721 | } | |
4722 | else | |
4723 | { | |
4724 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
4725 | { | |
4726 | unsigned64 memval = 0; | |
4727 | unsigned64 memval1 = 0; | |
4728 | unsigned64 mask = 0x7; | |
4729 | unsigned int byte; | |
4730 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
4731 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
c1e8ada4 | 4732 | memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte)); |
c906108c SS |
4733 | { |
4734 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
4735 | } | |
4736 | } | |
4737 | } | |
4738 | } | |
4739 | } | |
4740 | ||
4741 | ||
eb5fcf93 | 4742 | 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt |
c906108c SS |
4743 | "trunc.l.%s<FMT> f<FD>, f<FS>" |
4744 | *mipsIII: | |
4745 | *mipsIV: | |
603a98e7 | 4746 | *mipsV: |
1e799e28 | 4747 | *mips64: |
c906108c SS |
4748 | *vr4100: |
4749 | *vr5000: | |
4750 | *r3900: | |
4751 | { | |
c1e8ada4 | 4752 | int fmt = FMT; |
9b17d183 | 4753 | check_fpu (SD_); |
8612006b CD |
4754 | check_fmt (SD_, fmt, instruction_0); |
4755 | StoreFPR(FD,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_long)); | |
c906108c SS |
4756 | } |
4757 | ||
4758 | ||
eb5fcf93 | 4759 | 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W |
c906108c SS |
4760 | "trunc.w.%s<FMT> f<FD>, f<FS>" |
4761 | *mipsII: | |
4762 | *mipsIII: | |
4763 | *mipsIV: | |
603a98e7 | 4764 | *mipsV: |
1e799e28 CD |
4765 | *mips32: |
4766 | *mips64: | |
c906108c SS |
4767 | *vr4100: |
4768 | *vr5000: | |
4769 | *r3900: | |
4770 | { | |
c1e8ada4 | 4771 | int fmt = FMT; |
9b17d183 | 4772 | check_fpu (SD_); |
8612006b CD |
4773 | check_fmt (SD_, fmt, instruction_0); |
4774 | StoreFPR(FD,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_word)); | |
c906108c SS |
4775 | } |
4776 | ||
4777 | \f | |
4778 | // | |
4779 | // MIPS Architecture: | |
4780 | // | |
4781 | // System Control Instruction Set (COP0) | |
4782 | // | |
4783 | ||
4784 | ||
4785 | 010000,01000,00000,16.OFFSET:COP0:32::BC0F | |
4786 | "bc0f <OFFSET>" | |
c5d00cc7 CD |
4787 | *mipsI: |
4788 | *mipsII: | |
4789 | *mipsIII: | |
4790 | *mipsIV: | |
603a98e7 | 4791 | *mipsV: |
1e799e28 CD |
4792 | *mips32: |
4793 | *mips64: | |
c906108c SS |
4794 | *vr4100: |
4795 | *vr5000: | |
4796 | ||
7a292a7a SS |
4797 | 010000,01000,00000,16.OFFSET:COP0:32::BC0F |
4798 | "bc0f <OFFSET>" | |
4799 | // stub needed for eCos as tx39 hardware bug workaround | |
4800 | *r3900: | |
4801 | { | |
4802 | /* do nothing */ | |
4803 | } | |
4804 | ||
c906108c SS |
4805 | |
4806 | 010000,01000,00010,16.OFFSET:COP0:32::BC0FL | |
4807 | "bc0fl <OFFSET>" | |
c5d00cc7 CD |
4808 | *mipsI: |
4809 | *mipsII: | |
4810 | *mipsIII: | |
4811 | *mipsIV: | |
603a98e7 | 4812 | *mipsV: |
1e799e28 CD |
4813 | *mips32: |
4814 | *mips64: | |
c906108c SS |
4815 | *vr4100: |
4816 | *vr5000: | |
4817 | ||
4818 | ||
4819 | 010000,01000,00001,16.OFFSET:COP0:32::BC0T | |
4820 | "bc0t <OFFSET>" | |
c5d00cc7 CD |
4821 | *mipsI: |
4822 | *mipsII: | |
4823 | *mipsIII: | |
4824 | *mipsIV: | |
603a98e7 | 4825 | *mipsV: |
1e799e28 CD |
4826 | *mips32: |
4827 | *mips64: | |
c906108c SS |
4828 | *vr4100: |
4829 | ||
4830 | ||
4831 | 010000,01000,00011,16.OFFSET:COP0:32::BC0TL | |
4832 | "bc0tl <OFFSET>" | |
c5d00cc7 CD |
4833 | *mipsI: |
4834 | *mipsII: | |
4835 | *mipsIII: | |
4836 | *mipsIV: | |
603a98e7 | 4837 | *mipsV: |
1e799e28 CD |
4838 | *mips32: |
4839 | *mips64: | |
c906108c SS |
4840 | *vr4100: |
4841 | *vr5000: | |
4842 | ||
4843 | ||
4844 | 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE | |
0d3e762b | 4845 | "cache <OP>, <OFFSET>(r<BASE>)" |
c906108c SS |
4846 | *mipsIII: |
4847 | *mipsIV: | |
603a98e7 | 4848 | *mipsV: |
1e799e28 CD |
4849 | *mips32: |
4850 | *mips64: | |
c906108c SS |
4851 | *vr4100: |
4852 | *vr5000: | |
4853 | *r3900: | |
4854 | { | |
c1e8ada4 CD |
4855 | address_word base = GPR[BASE]; |
4856 | address_word offset = EXTEND16 (OFFSET); | |
c906108c | 4857 | { |
09297648 | 4858 | address_word vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
4859 | address_word paddr; |
4860 | int uncached; | |
4861 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
c1e8ada4 | 4862 | CacheOp(OP,vaddr,paddr,instruction_0); |
c906108c SS |
4863 | } |
4864 | } | |
4865 | ||
4866 | ||
f701dad2 | 4867 | 010000,1,0000000000000000000,111001:COP0:32::DI |
c906108c | 4868 | "di" |
c5d00cc7 CD |
4869 | *mipsI: |
4870 | *mipsII: | |
4871 | *mipsIII: | |
4872 | *mipsIV: | |
603a98e7 | 4873 | *mipsV: |
c906108c SS |
4874 | *vr4100: |
4875 | *vr5000: | |
4876 | ||
4877 | ||
f701dad2 | 4878 | 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0 |
9846de1b | 4879 | "dmfc0 r<RT>, r<RD>" |
c5d00cc7 CD |
4880 | *mipsIII: |
4881 | *mipsIV: | |
603a98e7 | 4882 | *mipsV: |
1e799e28 | 4883 | *mips64: |
9846de1b | 4884 | { |
ca971540 | 4885 | check_u64 (SD_, instruction_0); |
9846de1b JM |
4886 | DecodeCoproc (instruction_0); |
4887 | } | |
4888 | ||
4889 | ||
f701dad2 | 4890 | 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0 |
9846de1b | 4891 | "dmtc0 r<RT>, r<RD>" |
c5d00cc7 CD |
4892 | *mipsIII: |
4893 | *mipsIV: | |
603a98e7 | 4894 | *mipsV: |
1e799e28 | 4895 | *mips64: |
9846de1b | 4896 | { |
ca971540 | 4897 | check_u64 (SD_, instruction_0); |
9846de1b JM |
4898 | DecodeCoproc (instruction_0); |
4899 | } | |
4900 | ||
4901 | ||
f701dad2 | 4902 | 010000,1,0000000000000000000,111000:COP0:32::EI |
c906108c | 4903 | "ei" |
c5d00cc7 CD |
4904 | *mipsI: |
4905 | *mipsII: | |
4906 | *mipsIII: | |
4907 | *mipsIV: | |
603a98e7 | 4908 | *mipsV: |
1e799e28 | 4909 | *mips64: |
c906108c SS |
4910 | *vr4100: |
4911 | *vr5000: | |
4912 | ||
4913 | ||
f701dad2 | 4914 | 010000,1,0000000000000000000,011000:COP0:32::ERET |
c906108c SS |
4915 | "eret" |
4916 | *mipsIII: | |
4917 | *mipsIV: | |
603a98e7 | 4918 | *mipsV: |
1e799e28 CD |
4919 | *mips32: |
4920 | *mips64: | |
c906108c SS |
4921 | *vr4100: |
4922 | *vr5000: | |
4923 | { | |
4924 | if (SR & status_ERL) | |
4925 | { | |
4926 | /* Oops, not yet available */ | |
4927 | sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported"); | |
4928 | NIA = EPC; | |
4929 | SR &= ~status_ERL; | |
4930 | } | |
4931 | else | |
4932 | { | |
4933 | NIA = EPC; | |
4934 | SR &= ~status_EXL; | |
4935 | } | |
4936 | } | |
4937 | ||
4938 | ||
4939 | 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0 | |
4940 | "mfc0 r<RT>, r<RD> # <REGX>" | |
c5d00cc7 CD |
4941 | *mipsI: |
4942 | *mipsII: | |
4943 | *mipsIII: | |
4944 | *mipsIV: | |
603a98e7 | 4945 | *mipsV: |
1e799e28 CD |
4946 | *mips32: |
4947 | *mips64: | |
c906108c SS |
4948 | *vr4100: |
4949 | *vr5000: | |
074e9cb8 | 4950 | *r3900: |
c906108c SS |
4951 | { |
4952 | TRACE_ALU_INPUT0 (); | |
4953 | DecodeCoproc (instruction_0); | |
4954 | TRACE_ALU_RESULT (GPR[RT]); | |
4955 | } | |
4956 | ||
4957 | 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0 | |
4958 | "mtc0 r<RT>, r<RD> # <REGX>" | |
c5d00cc7 CD |
4959 | *mipsI: |
4960 | *mipsII: | |
4961 | *mipsIII: | |
4962 | *mipsIV: | |
603a98e7 | 4963 | *mipsV: |
1e799e28 CD |
4964 | *mips32: |
4965 | *mips64: | |
c906108c SS |
4966 | *vr4100: |
4967 | *vr5000: | |
074e9cb8 | 4968 | *r3900: |
c906108c SS |
4969 | { |
4970 | DecodeCoproc (instruction_0); | |
4971 | } | |
4972 | ||
4973 | ||
f701dad2 | 4974 | 010000,1,0000000000000000000,010000:COP0:32::RFE |
c906108c | 4975 | "rfe" |
c5d00cc7 CD |
4976 | *mipsI: |
4977 | *mipsII: | |
4978 | *mipsIII: | |
4979 | *mipsIV: | |
603a98e7 | 4980 | *mipsV: |
c906108c SS |
4981 | *vr4100: |
4982 | *vr5000: | |
074e9cb8 | 4983 | *r3900: |
c906108c SS |
4984 | { |
4985 | DecodeCoproc (instruction_0); | |
4986 | } | |
4987 | ||
4988 | ||
4989 | 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz | |
4990 | "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>" | |
c5d00cc7 CD |
4991 | *mipsI: |
4992 | *mipsII: | |
4993 | *mipsIII: | |
4994 | *mipsIV: | |
603a98e7 | 4995 | *mipsV: |
1e799e28 CD |
4996 | *mips32: |
4997 | *mips64: | |
c906108c SS |
4998 | *vr4100: |
4999 | *r3900: | |
5000 | { | |
5001 | DecodeCoproc (instruction_0); | |
5002 | } | |
5003 | ||
5004 | ||
5005 | ||
f701dad2 | 5006 | 010000,1,0000000000000000000,001000:COP0:32::TLBP |
c906108c | 5007 | "tlbp" |
c5d00cc7 CD |
5008 | *mipsI: |
5009 | *mipsII: | |
5010 | *mipsIII: | |
5011 | *mipsIV: | |
603a98e7 | 5012 | *mipsV: |
1e799e28 CD |
5013 | *mips32: |
5014 | *mips64: | |
c906108c SS |
5015 | *vr4100: |
5016 | *vr5000: | |
5017 | ||
5018 | ||
f701dad2 | 5019 | 010000,1,0000000000000000000,000001:COP0:32::TLBR |
c906108c | 5020 | "tlbr" |
c5d00cc7 CD |
5021 | *mipsI: |
5022 | *mipsII: | |
5023 | *mipsIII: | |
5024 | *mipsIV: | |
603a98e7 | 5025 | *mipsV: |
1e799e28 CD |
5026 | *mips32: |
5027 | *mips64: | |
c906108c SS |
5028 | *vr4100: |
5029 | *vr5000: | |
5030 | ||
5031 | ||
f701dad2 | 5032 | 010000,1,0000000000000000000,000010:COP0:32::TLBWI |
c906108c | 5033 | "tlbwi" |
c5d00cc7 CD |
5034 | *mipsI: |
5035 | *mipsII: | |
5036 | *mipsIII: | |
5037 | *mipsIV: | |
603a98e7 | 5038 | *mipsV: |
1e799e28 CD |
5039 | *mips32: |
5040 | *mips64: | |
c906108c SS |
5041 | *vr4100: |
5042 | *vr5000: | |
5043 | ||
5044 | ||
f701dad2 | 5045 | 010000,1,0000000000000000000,000110:COP0:32::TLBWR |
c906108c | 5046 | "tlbwr" |
c5d00cc7 CD |
5047 | *mipsI: |
5048 | *mipsII: | |
5049 | *mipsIII: | |
5050 | *mipsIV: | |
603a98e7 | 5051 | *mipsV: |
1e799e28 CD |
5052 | *mips32: |
5053 | *mips64: | |
c906108c SS |
5054 | *vr4100: |
5055 | *vr5000: | |
5056 | ||
5057 | \f | |
5058 | :include:::m16.igen | |
f4f1b9f1 | 5059 | :include:::mdmx.igen |
c906108c SS |
5060 | :include:::tx.igen |
5061 | :include:::vr.igen | |
5062 | \f |