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Fixed reloc generation to match latest opcoide list from cgen.
[deliverable/binutils-gdb.git] / sim / mips / mips.igen
CommitLineData
ca6f76d1
AC		 1// -*- C -*-
2//
f2b30012
AC		 3// <insn> ::=
4// <insn-word> { "+" <insn-word> }
5// ":" <format-name>
6// ":" <filter-flags>
7// ":" <options>
8// ":" <name>
9// <nl>
10// { <insn-model> }
11// { <insn-mnemonic> }
12// <code-block>
13//
14
15
16// IGEN config - mips16
a48e8c8d
AC		 17// :option:16::insn-bit-size:16
18// :option:16::hi-bit-nr:15
89d09738
AC		 19:option:16::insn-specifying-widths:true
20:option:16::gen-delayed-branch:false
f2b30012 21
90ad43b2 22// IGEN config - mips32/64..
a48e8c8d
AC		 23// :option:32::insn-bit-size:32
24// :option:32::hi-bit-nr:31
89d09738
AC		 25:option:32::insn-specifying-widths:true
26:option:32::gen-delayed-branch:false
f2b30012
AC		 27
28
49a6eed5 29// Generate separate simulators for each target
89d09738 30// :option:::multi-sim:true
49a6eed5 31
f2b30012
AC		 32
33// Models known by this simulator
15232df4
FCE		 34:model:::mipsI:mips3000:
35:model:::mipsII:mips6000:
36:model:::mipsIII:mips4000:
37:model:::mipsIV:mips8000:
89d09738 38:model:::mips16:mips16:
f2b30012 39// start-sanitize-r5900
a48e8c8d 40:model:::r5900:mips5900:
f2b30012 41// end-sanitize-r5900
a48e8c8d 42:model:::r3900:mips3900:
f2b30012 43// start-sanitize-tx19
89d09738 44:model:::tx19:tx19:
f2b30012 45// end-sanitize-tx19
15232df4
FCE		 46// start-sanitize-vr4320
47:model:::vr4320:mips4320:
48// end-sanitize-vr4320
90ad43b2 49// start-sanitize-vr5400
a48e8c8d 50:model:::vr5400:mips5400:
23850e92 51:model:::mdmx:mdmx:
90ad43b2 52// end-sanitize-vr5400
a48e8c8d 53:model:::vr5000:mips5000:
f2b30012
AC		 54
55
56
57// Pseudo instructions known by IGEN
89d09738 58:internal::::illegal:
f2b30012 59{
030843d7 60 SignalException (ReservedInstruction, 0);
f2b30012
AC		 61}
62
63
030843d7
AC		 64// Pseudo instructions known by interp.c
65// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
66000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
67"rsvd <OP>"
68{
69 SignalException (ReservedInstruction, instruction_0);
70}
71
f2b30012
AC		 72
73
f3bdd368
AC		 74// Helper:
75//
76// Simulate a 32 bit delayslot instruction
77//
78
79:function:::address_word:delayslot32:address_word target
80{
81 instruction_word delay_insn;
82 sim_events_slip (SD, 1);
83 DSPC = CIA;
84 CIA = CIA + 4; /* NOTE not mips16 */
85 STATE |= simDELAYSLOT;
86 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
87 idecode_issue (CPU_, delay_insn, (CIA));
88 STATE &= ~simDELAYSLOT;
89 return target;
90}
91
92:function:::address_word:nullify_next_insn32:
93{
94 sim_events_slip (SD, 1);
95 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
96 return CIA + 8;
97}
98
99
100
421cbaae
AC		 101// Helper:
102//
103// Check that an access to a HI/LO register meets timing requirements
104//
105// The following requirements exist:
106//
107// - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
108// - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
109// - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
110// corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
111//
112
113:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
114{
115 if (history->mf.timestamp + 3 > time)
116 {
117 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
118 itable[MY_INDEX].name,
119 new, (long) CIA,
120 (long) history->mf.cia);
121 return 0;
122 }
123 return 1;
124}
125
126:function:::int:check_mt_hilo:hilo_history *history
3fa454e9
FCE		 127*mipsI,mipsII,mipsIII,mipsIV:
128*vr5000:
129// start-sanitize-vr4320
130*vr4320:
131// end-sanitize-vr4320
132// start-sanitize-vr5400
133*vr5400:
134// end-sanitize-vr5400
421cbaae
AC		 135{
136 signed64 time = sim_events_time (SD);
137 int ok = check_mf_cycles (SD_, history, time, "MT");
138 history->mt.timestamp = time;
139 history->mt.cia = CIA;
140 return ok;
141}
142
3fa454e9
FCE		 143:function:::int:check_mt_hilo:hilo_history *history
144*r3900:
145// start-sanitize-tx19
146*tx19:
147// end-sanitize-tx19
0e797366
AC		 148// start-sanitize-r5900
149*r5900:
150// end-sanitize-r5900
3fa454e9
FCE		 151{
152 signed64 time = sim_events_time (SD);
153 history->mt.timestamp = time;
154 history->mt.cia = CIA;
155 return 1;
156}
157
0e797366 158
421cbaae 159:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
0e797366
AC		 160*mipsI,mipsII,mipsIII,mipsIV:
161*vr5000:
162// start-sanitize-vr4320
163*vr4320:
164// end-sanitize-vr4320
165// start-sanitize-vr5400
166*vr5400:
167// end-sanitize-vr5400
168*r3900:
169// start-sanitize-tx19
170*tx19:
171// end-sanitize-tx19
421cbaae
AC		 172{
173 signed64 time = sim_events_time (SD);
174 int ok = 1;
175 if (peer != NULL
176 && peer->mt.timestamp > history->op.timestamp
aaa2c908
GRK		 177 && history->mt.timestamp < history->op.timestamp
178 && ! (history->mf.timestamp > history->op.timestamp
179 && history->mf.timestamp < peer->mt.timestamp)
180 && ! (peer->mf.timestamp > history->op.timestamp
181 && peer->mf.timestamp < peer->mt.timestamp))
421cbaae
AC		 182 {
183 /* The peer has been written to since the last OP yet we have
184 not */
185 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
186 itable[MY_INDEX].name,
187 (long) CIA,
188 (long) history->op.cia,
189 (long) peer->mt.cia);
190 ok = 0;
191 }
192 history->mf.timestamp = time;
193 history->mf.cia = CIA;
194 return ok;
195}
196
0e797366
AC		 197// start-sanitize-r5900
198// The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
199:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
200// end-sanitize-r5900
201// start-sanitize-r5900
202*r5900:
203// end-sanitize-r5900
204// start-sanitize-r5900
205{
206 /* FIXME: could record the fact that a stall occured if we want */
207 signed64 time = sim_events_time (SD);
208 history->mf.timestamp = time;
209 history->mf.cia = CIA;
210 return 1;
211}
212// end-sanitize-r5900
213
214
94dda41a
GRK		 215:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
216*mipsI,mipsII,mipsIII,mipsIV:
217*vr5000:
218// start-sanitize-vr4320
219*vr4320:
220// end-sanitize-vr4320
221// start-sanitize-vr5400
222*vr5400:
223// end-sanitize-vr5400
94dda41a
GRK		 224{
225 signed64 time = sim_events_time (SD);
226 int ok = (check_mf_cycles (SD_, hi, time, "OP")
227 && check_mf_cycles (SD_, lo, time, "OP"));
228 hi->op.timestamp = time;
229 lo->op.timestamp = time;
230 hi->op.cia = CIA;
231 lo->op.cia = CIA;
232 return ok;
233}
234
94dda41a
GRK		 235// The r3900 mult and multu insns _can_ be exectuted immediatly after
236// a mf{hi,lo}
237:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
238*r3900:
239// start-sanitize-tx19
240*tx19:
241// end-sanitize-tx19
0e797366
AC		 242// start-sanitize-r5900
243*r5900:
244// end-sanitize-r5900
94dda41a 245{
0e797366 246 /* FIXME: could record the fact that a stall occured if we want */
94dda41a
GRK		 247 signed64 time = sim_events_time (SD);
248 hi->op.timestamp = time;
249 lo->op.timestamp = time;
250 hi->op.cia = CIA;
251 lo->op.cia = CIA;
252 return 1;
253}
254
0e797366 255
94dda41a 256:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
421cbaae
AC		 257*mipsI,mipsII,mipsIII,mipsIV:
258*vr5000:
259// start-sanitize-vr4320
260*vr4320:
261// end-sanitize-vr4320
262// start-sanitize-vr5400
263*vr5400:
264// end-sanitize-vr5400
265*r3900:
266// start-sanitize-tx19
267*tx19:
268// end-sanitize-tx19
421cbaae
AC		 269{
270 signed64 time = sim_events_time (SD);
271 int ok = (check_mf_cycles (SD_, hi, time, "OP")
272 && check_mf_cycles (SD_, lo, time, "OP"));
273 hi->op.timestamp = time;
274 lo->op.timestamp = time;
275 hi->op.cia = CIA;
276 lo->op.cia = CIA;
277 return ok;
278}
279
280
0e797366
AC		 281// start-sanitize-r5900
282// The r5900 div et.al insns _can_ be exectuted immediatly after
283// a mf{hi,lo}
284:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
285// end-sanitize-r5900
286// start-sanitize-r5900
287*r5900:
288// end-sanitize-r5900
289// start-sanitize-r5900
290{
291 /* FIXME: could record the fact that a stall occured if we want */
292 signed64 time = sim_events_time (SD);
293 hi->op.timestamp = time;
294 lo->op.timestamp = time;
295 hi->op.cia = CIA;
296 lo->op.cia = CIA;
297 return 1;
298}
299// end-sanitize-r5900
300
301
421cbaae 302
f2b30012 303//
7ce8b917 304// Mips Architecture:
f2b30012
AC		 305//
306// CPU Instruction Set (mipsI - mipsIV)
307//
308
309
c0a4c3ba 310
f2b30012
AC		 311000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
312"add r<RD>, r<RS>, r<RT>"
23850e92
JL		 313*mipsI,mipsII,mipsIII,mipsIV:
314*vr5000:
15232df4
FCE		 315// start-sanitize-vr4320
316*vr4320:
317// end-sanitize-vr4320
90ad43b2
AC		 318// start-sanitize-vr5400
319*vr5400:
320// end-sanitize-vr5400
f2b30012
AC		 321// start-sanitize-r5900
322*r5900:
323// end-sanitize-r5900
324*r3900:
325// start-sanitize-tx19
326*tx19:
327// end-sanitize-tx19
328{
26feb3a8
AC		 329 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
330 {
331 ALU32_BEGIN (GPR[RS]);
332 ALU32_ADD (GPR[RT]);
333 ALU32_END (GPR[RD]);
334 }
335 TRACE_ALU_RESULT (GPR[RD]);
f2b30012
AC		 336}
337
338
c0a4c3ba 339
f2b30012
AC		 340001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
341"addi r<RT>, r<RS>, IMMEDIATE"
23850e92
JL		 342*mipsI,mipsII,mipsIII,mipsIV:
343*vr5000:
15232df4
FCE		 344// start-sanitize-vr4320
345*vr4320:
346// end-sanitize-vr4320
90ad43b2
AC		 347// start-sanitize-vr5400
348*vr5400:
349// end-sanitize-vr5400
f2b30012
AC		 350// start-sanitize-r5900
351*r5900:
352// end-sanitize-r5900
353*r3900:
354// start-sanitize-tx19
355*tx19:
356// end-sanitize-tx19
357{
26feb3a8
AC		 358 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
359 {
360 ALU32_BEGIN (GPR[RS]);
361 ALU32_ADD (EXTEND16 (IMMEDIATE));
362 ALU32_END (GPR[RT]);
363 }
364 TRACE_ALU_RESULT (GPR[RT]);
f2b30012
AC		 365}
366
367
c0a4c3ba
AC		 368
369:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
370{
f3bdd368
AC		 371 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
372 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
373 TRACE_ALU_RESULT (GPR[rt]);
c0a4c3ba
AC		 374}
375
f2b30012 376001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
f3bdd368 377"addiu r<RT>, r<RS>, <IMMEDIATE>"
23850e92
JL		 378*mipsI,mipsII,mipsIII,mipsIV:
379*vr5000:
15232df4
FCE		 380// start-sanitize-vr4320
381*vr4320:
382// end-sanitize-vr4320
90ad43b2
AC		 383// start-sanitize-vr5400
384*vr5400:
385// end-sanitize-vr5400
f2b30012
AC		 386// start-sanitize-r5900
387*r5900:
388// end-sanitize-r5900
389*r3900:
390// start-sanitize-tx19
391*tx19:
392// end-sanitize-tx19
393{
c0a4c3ba 394 do_addiu (SD_, RS, RT, IMMEDIATE);
f2b30012
AC		 395}
396
397
c0a4c3ba
AC		 398
399:function:::void:do_addu:int rs, int rt, int rd
400{
f3bdd368
AC		 401 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
402 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
403 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 404}
405
f2b30012 406000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
ebcfd86a 407"addu r<RD>, r<RS>, r<RT>"
23850e92
JL		 408*mipsI,mipsII,mipsIII,mipsIV:
409*vr5000:
15232df4
FCE		 410// start-sanitize-vr4320
411*vr4320:
412// end-sanitize-vr4320
90ad43b2
AC		 413// start-sanitize-vr5400
414*vr5400:
415// end-sanitize-vr5400
f2b30012
AC		 416// start-sanitize-r5900
417*r5900:
418// end-sanitize-r5900
419*r3900:
420// start-sanitize-tx19
421*tx19:
422// end-sanitize-tx19
423{
c0a4c3ba 424 do_addu (SD_, RS, RT, RD);
f2b30012
AC		 425}
426
427
c0a4c3ba
AC		 428
429:function:::void:do_and:int rs, int rt, int rd
430{
f3bdd368 431 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 432 GPR[rd] = GPR[rs] & GPR[rt];
f3bdd368 433 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 434}
435
f2b30012
AC		 436000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
437"and r<RD>, r<RS>, r<RT>"
23850e92
JL		 438*mipsI,mipsII,mipsIII,mipsIV:
439*vr5000:
15232df4
FCE		 440// start-sanitize-vr4320
441*vr4320:
442// end-sanitize-vr4320
90ad43b2
AC		 443// start-sanitize-vr5400
444*vr5400:
445// end-sanitize-vr5400
f2b30012
AC		 446// start-sanitize-r5900
447*r5900:
448// end-sanitize-r5900
449*r3900:
450// start-sanitize-tx19
451*tx19:
452// end-sanitize-tx19
453{
c0a4c3ba 454 do_and (SD_, RS, RT, RD);
f2b30012
AC		 455}
456
457
c0a4c3ba 458
f2b30012 459001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
23850e92
JL		 460"and r<RT>, r<RS>, <IMMEDIATE>"
461*mipsI,mipsII,mipsIII,mipsIV:
462*vr5000:
15232df4
FCE		 463// start-sanitize-vr4320
464*vr4320:
465// end-sanitize-vr4320
90ad43b2
AC		 466// start-sanitize-vr5400
467*vr5400:
468// end-sanitize-vr5400
f2b30012
AC		 469// start-sanitize-r5900
470*r5900:
471// end-sanitize-r5900
472*r3900:
473// start-sanitize-tx19
474*tx19:
475// end-sanitize-tx19
476{
97f4d183 477 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
055ee297 478 GPR[RT] = GPR[RS] & IMMEDIATE;
97f4d183 479 TRACE_ALU_RESULT (GPR[RT]);
f2b30012
AC		 480}
481
482
c0a4c3ba 483
f2b30012 484000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
7ce8b917 485"beq r<RS>, r<RT>, <OFFSET>"
23850e92
JL		 486*mipsI,mipsII,mipsIII,mipsIV:
487*vr5000:
15232df4
FCE		 488// start-sanitize-vr4320
489*vr4320:
490// end-sanitize-vr4320
90ad43b2
AC		 491// start-sanitize-vr5400
492*vr5400:
493// end-sanitize-vr5400
f2b30012
AC		 494// start-sanitize-r5900
495*r5900:
496// end-sanitize-r5900
497*r3900:
498// start-sanitize-tx19
499*tx19:
500// end-sanitize-tx19
501{
055ee297 502 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 503 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
504 DELAY_SLOT (NIA + offset);
f2b30012
AC		 505}
506
507
c0a4c3ba 508
f2b30012
AC		 509010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
510"beql r<RS>, r<RT>, <OFFSET>"
511*mipsII:
512*mipsIII:
513*mipsIV:
23850e92 514*vr5000:
15232df4
FCE		 515// start-sanitize-vr4320
516*vr4320:
517// end-sanitize-vr4320
90ad43b2
AC		 518// start-sanitize-vr5400
519*vr5400:
520// end-sanitize-vr5400
f2b30012
AC		 521// start-sanitize-r5900
522*r5900:
523// end-sanitize-r5900
524*r3900:
525// start-sanitize-tx19
526*tx19:
527// end-sanitize-tx19
528{
055ee297 529 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 530 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
531 DELAY_SLOT (NIA + offset);
055ee297 532 else
49a76833 533 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 534}
535
536
c0a4c3ba 537
f2b30012
AC		 538000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
539"bgez r<RS>, <OFFSET>"
23850e92
JL		 540*mipsI,mipsII,mipsIII,mipsIV:
541*vr5000:
15232df4
FCE		 542// start-sanitize-vr4320
543*vr4320:
544// end-sanitize-vr4320
90ad43b2
AC		 545// start-sanitize-vr5400
546*vr5400:
547// end-sanitize-vr5400
f2b30012
AC		 548// start-sanitize-r5900
549*r5900:
550// end-sanitize-r5900
551*r3900:
552// start-sanitize-tx19
553*tx19:
554// end-sanitize-tx19
555{
055ee297 556 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 557 if ((signed_word) GPR[RS] >= 0)
558 DELAY_SLOT (NIA + offset);
f2b30012
AC		 559}
560
561
c0a4c3ba 562
f2b30012
AC		 563000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
564"bgezal r<RS>, <OFFSET>"
23850e92
JL		 565*mipsI,mipsII,mipsIII,mipsIV:
566*vr5000:
15232df4
FCE		 567// start-sanitize-vr4320
568*vr4320:
569// end-sanitize-vr4320
90ad43b2
AC		 570// start-sanitize-vr5400
571*vr5400:
572// end-sanitize-vr5400
f2b30012
AC		 573// start-sanitize-r5900
574*r5900:
575// end-sanitize-r5900
576*r3900:
577// start-sanitize-tx19
578*tx19:
579// end-sanitize-tx19
580{
055ee297
AC		 581 address_word offset = EXTEND16 (OFFSET) << 2;
582 RA = (CIA + 8);
030843d7
AC		 583 if ((signed_word) GPR[RS] >= 0)
584 DELAY_SLOT (NIA + offset);
f2b30012
AC		 585}
586
587
c0a4c3ba 588
f2b30012
AC		 589000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
590"bgezall r<RS>, <OFFSET>"
591*mipsII:
592*mipsIII:
593*mipsIV:
23850e92 594*vr5000:
15232df4
FCE		 595// start-sanitize-vr4320
596*vr4320:
597// end-sanitize-vr4320
90ad43b2
AC		 598// start-sanitize-vr5400
599*vr5400:
600// end-sanitize-vr5400
f2b30012
AC		 601// start-sanitize-r5900
602*r5900:
603// end-sanitize-r5900
604*r3900:
605// start-sanitize-tx19
606*tx19:
607// end-sanitize-tx19
608{
055ee297
AC		 609 address_word offset = EXTEND16 (OFFSET) << 2;
610 RA = (CIA + 8);
f2b30012
AC		 611 /* NOTE: The branch occurs AFTER the next instruction has been
612 executed */
030843d7
AC		 613 if ((signed_word) GPR[RS] >= 0)
614 DELAY_SLOT (NIA + offset);
f2b30012 615 else
49a76833 616 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 617}
618
619
c0a4c3ba 620
f2b30012
AC		 621000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
622"bgezl r<RS>, <OFFSET>"
623*mipsII:
624*mipsIII:
625*mipsIV:
23850e92 626*vr5000:
15232df4
FCE		 627// start-sanitize-vr4320
628*vr4320:
629// end-sanitize-vr4320
90ad43b2
AC		 630// start-sanitize-vr5400
631*vr5400:
632// end-sanitize-vr5400
f2b30012
AC		 633// start-sanitize-r5900
634*r5900:
635// end-sanitize-r5900
636*r3900:
637// start-sanitize-tx19
638*tx19:
639// end-sanitize-tx19
640{
055ee297 641 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 642 if ((signed_word) GPR[RS] >= 0)
643 DELAY_SLOT (NIA + offset);
f2b30012 644 else
49a76833 645 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 646}
647
648
c0a4c3ba 649
f2b30012
AC		 650000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
651"bgtz r<RS>, <OFFSET>"
23850e92
JL		 652*mipsI,mipsII,mipsIII,mipsIV:
653*vr5000:
15232df4
FCE		 654// start-sanitize-vr4320
655*vr4320:
656// end-sanitize-vr4320
90ad43b2
AC		 657// start-sanitize-vr5400
658*vr5400:
659// end-sanitize-vr5400
f2b30012
AC		 660// start-sanitize-r5900
661*r5900:
662// end-sanitize-r5900
663*r3900:
664// start-sanitize-tx19
665*tx19:
666// end-sanitize-tx19
667{
055ee297 668 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 669 if ((signed_word) GPR[RS] > 0)
670 DELAY_SLOT (NIA + offset);
f2b30012
AC		 671}
672
673
c0a4c3ba 674
f2b30012
AC		 675010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
676"bgtzl r<RS>, <OFFSET>"
677*mipsII:
678*mipsIII:
679*mipsIV:
23850e92 680*vr5000:
15232df4
FCE		 681// start-sanitize-vr4320
682*vr4320:
683// end-sanitize-vr4320
90ad43b2
AC		 684// start-sanitize-vr5400
685*vr5400:
686// end-sanitize-vr5400
f2b30012
AC		 687// start-sanitize-r5900
688*r5900:
689// end-sanitize-r5900
690*r3900:
691// start-sanitize-tx19
692*tx19:
693// end-sanitize-tx19
694{
055ee297 695 address_word offset = EXTEND16 (OFFSET) << 2;
f2b30012
AC		 696 /* NOTE: The branch occurs AFTER the next instruction has been
697 executed */
030843d7
AC		 698 if ((signed_word) GPR[RS] > 0)
699 DELAY_SLOT (NIA + offset);
f2b30012 700 else
49a76833 701 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 702}
703
704
c0a4c3ba 705
f2b30012
AC		 706000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
707"blez r<RS>, <OFFSET>"
23850e92
JL		 708*mipsI,mipsII,mipsIII,mipsIV:
709*vr5000:
15232df4
FCE		 710// start-sanitize-vr4320
711*vr4320:
712// end-sanitize-vr4320
90ad43b2
AC		 713// start-sanitize-vr5400
714*vr5400:
715// end-sanitize-vr5400
f2b30012
AC		 716// start-sanitize-r5900
717*r5900:
718// end-sanitize-r5900
719*r3900:
720// start-sanitize-tx19
721*tx19:
722// end-sanitize-tx19
723{
055ee297 724 address_word offset = EXTEND16 (OFFSET) << 2;
f2b30012
AC		 725 /* NOTE: The branch occurs AFTER the next instruction has been
726 executed */
030843d7
AC		 727 if ((signed_word) GPR[RS] <= 0)
728 DELAY_SLOT (NIA + offset);
f2b30012
AC		 729}
730
731
c0a4c3ba 732
f2b30012
AC		 733010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
734"bgezl r<RS>, <OFFSET>"
735*mipsII:
736*mipsIII:
737*mipsIV:
23850e92 738*vr5000:
15232df4
FCE		 739// start-sanitize-vr4320
740*vr4320:
741// end-sanitize-vr4320
90ad43b2
AC		 742// start-sanitize-vr5400
743*vr5400:
744// end-sanitize-vr5400
f2b30012
AC		 745// start-sanitize-r5900
746*r5900:
747// end-sanitize-r5900
748*r3900:
749// start-sanitize-tx19
750*tx19:
751// end-sanitize-tx19
752{
055ee297 753 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 754 if ((signed_word) GPR[RS] <= 0)
755 DELAY_SLOT (NIA + offset);
f2b30012 756 else
49a76833 757 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 758}
759
760
c0a4c3ba 761
f2b30012
AC		 762000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
763"bltz r<RS>, <OFFSET>"
23850e92
JL		 764*mipsI,mipsII,mipsIII,mipsIV:
765*vr5000:
15232df4
FCE		 766// start-sanitize-vr4320
767*vr4320:
768// end-sanitize-vr4320
90ad43b2
AC		 769// start-sanitize-vr5400
770*vr5400:
771// end-sanitize-vr5400
f2b30012
AC		 772// start-sanitize-r5900
773*r5900:
774// end-sanitize-r5900
775*r3900:
776// start-sanitize-tx19
777*tx19:
778// end-sanitize-tx19
779{
055ee297 780 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 781 if ((signed_word) GPR[RS] < 0)
782 DELAY_SLOT (NIA + offset);
f2b30012
AC		 783}
784
785
c0a4c3ba 786
f2b30012
AC		 787000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
788"bltzal r<RS>, <OFFSET>"
23850e92
JL		 789*mipsI,mipsII,mipsIII,mipsIV:
790*vr5000:
15232df4
FCE		 791// start-sanitize-vr4320
792*vr4320:
793// end-sanitize-vr4320
90ad43b2
AC		 794// start-sanitize-vr5400
795*vr5400:
796// end-sanitize-vr5400
f2b30012
AC		 797// start-sanitize-r5900
798*r5900:
799// end-sanitize-r5900
800*r3900:
801// start-sanitize-tx19
802*tx19:
803// end-sanitize-tx19
804{
055ee297
AC		 805 address_word offset = EXTEND16 (OFFSET) << 2;
806 RA = (CIA + 8);
f2b30012
AC		 807 /* NOTE: The branch occurs AFTER the next instruction has been
808 executed */
030843d7
AC		 809 if ((signed_word) GPR[RS] < 0)
810 DELAY_SLOT (NIA + offset);
f2b30012
AC		 811}
812
813
c0a4c3ba 814
f2b30012
AC		 815000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
816"bltzall r<RS>, <OFFSET>"
817*mipsII:
818*mipsIII:
819*mipsIV:
23850e92 820*vr5000:
15232df4
FCE		 821// start-sanitize-vr4320
822*vr4320:
823// end-sanitize-vr4320
90ad43b2
AC		 824// start-sanitize-vr5400
825*vr5400:
826// end-sanitize-vr5400
f2b30012
AC		 827// start-sanitize-r5900
828*r5900:
829// end-sanitize-r5900
830*r3900:
831// start-sanitize-tx19
832*tx19:
833// end-sanitize-tx19
834{
055ee297
AC		 835 address_word offset = EXTEND16 (OFFSET) << 2;
836 RA = (CIA + 8);
030843d7
AC		 837 if ((signed_word) GPR[RS] < 0)
838 DELAY_SLOT (NIA + offset);
f2b30012 839 else
49a76833 840 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 841}
842
843
c0a4c3ba 844
f2b30012
AC		 845000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
846"bltzl r<RS>, <OFFSET>"
847*mipsII:
848*mipsIII:
849*mipsIV:
23850e92 850*vr5000:
15232df4
FCE		 851// start-sanitize-vr4320
852*vr4320:
853// end-sanitize-vr4320
90ad43b2
AC		 854// start-sanitize-vr5400
855*vr5400:
856// end-sanitize-vr5400
f2b30012
AC		 857// start-sanitize-r5900
858*r5900:
859// end-sanitize-r5900
860*r3900:
861// start-sanitize-tx19
862*tx19:
863// end-sanitize-tx19
864{
055ee297 865 address_word offset = EXTEND16 (OFFSET) << 2;
f2b30012
AC		 866 /* NOTE: The branch occurs AFTER the next instruction has been
867 executed */
030843d7
AC		 868 if ((signed_word) GPR[RS] < 0)
869 DELAY_SLOT (NIA + offset);
f2b30012 870 else
49a76833 871 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 872}
873
874
c0a4c3ba 875
f2b30012
AC		 876000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
877"bne r<RS>, r<RT>, <OFFSET>"
23850e92
JL		 878*mipsI,mipsII,mipsIII,mipsIV:
879*vr5000:
15232df4
FCE		 880// start-sanitize-vr4320
881*vr4320:
882// end-sanitize-vr4320
90ad43b2
AC		 883// start-sanitize-vr5400
884*vr5400:
885// end-sanitize-vr5400
f2b30012
AC		 886// start-sanitize-r5900
887*r5900:
888// end-sanitize-r5900
889*r3900:
890// start-sanitize-tx19
891*tx19:
892// end-sanitize-tx19
893{
055ee297 894 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 895 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
896 DELAY_SLOT (NIA + offset);
f2b30012
AC		 897}
898
899
c0a4c3ba 900
f2b30012
AC		 901010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
902"bnel r<RS>, r<RT>, <OFFSET>"
903*mipsII:
904*mipsIII:
905*mipsIV:
23850e92 906*vr5000:
15232df4
FCE		 907// start-sanitize-vr4320
908*vr4320:
909// end-sanitize-vr4320
90ad43b2
AC		 910// start-sanitize-vr5400
911*vr5400:
912// end-sanitize-vr5400
f2b30012
AC		 913// start-sanitize-r5900
914*r5900:
915// end-sanitize-r5900
916*r3900:
917// start-sanitize-tx19
918*tx19:
919// end-sanitize-tx19
920{
085c1cb9 921 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 922 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
923 DELAY_SLOT (NIA + offset);
f2b30012 924 else
49a76833 925 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 926}
927
928
c0a4c3ba 929
49a6eed5 930000000,20.CODE,001101:SPECIAL:32::BREAK
f2b30012 931"break"
23850e92
JL		 932*mipsI,mipsII,mipsIII,mipsIV:
933*vr5000:
15232df4
FCE		 934// start-sanitize-vr4320
935*vr4320:
936// end-sanitize-vr4320
90ad43b2
AC		 937// start-sanitize-vr5400
938*vr5400:
939// end-sanitize-vr5400
f2b30012
AC		 940// start-sanitize-r5900
941*r5900:
942// end-sanitize-r5900
943*r3900:
944// start-sanitize-tx19
945*tx19:
946// end-sanitize-tx19
947{
895a7dc2
IC		 948 /* Check for some break instruction which are reserved for use by the simulator. */
949 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
950 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
951 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
952 {
953 sim_engine_halt (SD, CPU, NULL, cia,
954 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
955 }
956 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
957 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
958 {
959 if (STATE & simDELAYSLOT)
960 PC = cia - 4; /* reference the branch instruction */
961 else
962 PC = cia;
963 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
964 }
965// start-sanitize-sky
966 else if (break_code == (HALT_INSTRUCTION_PASS & HALT_INSTRUCTION_MASK))
967 {
968 sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
969 }
970 else if (break_code == (HALT_INSTRUCTION_FAIL & HALT_INSTRUCTION_MASK))
971 {
972 sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 15);
973 }
974// end-sanitize-sky
975
976 /* If we get this far, we're not an instruction reserved by the sim. Raise
977 the exception. */
055ee297 978 SignalException(BreakPoint, instruction_0);
f2b30012
AC		 979}
980
981
c0a4c3ba 982
f2b30012
AC		 983
984
c0a4c3ba 985
f2b30012
AC		 986000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
987"dadd r<RD>, r<RS>, r<RT>"
988*mipsIII:
989*mipsIV:
23850e92 990*vr5000:
15232df4
FCE		 991// start-sanitize-vr4320
992*vr4320:
993// end-sanitize-vr4320
90ad43b2
AC		 994// start-sanitize-vr5400
995*vr5400:
996// end-sanitize-vr5400
f2b30012
AC		 997// start-sanitize-r5900
998*r5900:
999// end-sanitize-r5900
f2b30012
AC		 1000// start-sanitize-tx19
1001*tx19:
1002// end-sanitize-tx19
1003{
ca6f76d1 1004 /* this check's for overflow */
26feb3a8
AC		 1005 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1006 {
1007 ALU64_BEGIN (GPR[RS]);
1008 ALU64_ADD (GPR[RT]);
1009 ALU64_END (GPR[RD]);
1010 }
1011 TRACE_ALU_RESULT (GPR[RD]);
f2b30012
AC		 1012}
1013
1014
c0a4c3ba 1015
f2b30012
AC		 1016011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1017"daddi r<RT>, r<RS>, <IMMEDIATE>"
1018*mipsIII:
1019*mipsIV:
23850e92 1020*vr5000:
15232df4
FCE		 1021// start-sanitize-vr4320
1022*vr4320:
1023// end-sanitize-vr4320
90ad43b2
AC		 1024// start-sanitize-vr5400
1025*vr5400:
1026// end-sanitize-vr5400
f2b30012
AC		 1027// start-sanitize-r5900
1028*r5900:
1029// end-sanitize-r5900
f2b30012
AC		 1030// start-sanitize-tx19
1031*tx19:
1032// end-sanitize-tx19
1033{
26feb3a8
AC		 1034 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1035 {
1036 ALU64_BEGIN (GPR[RS]);
1037 ALU64_ADD (EXTEND16 (IMMEDIATE));
1038 ALU64_END (GPR[RT]);
1039 }
1040 TRACE_ALU_RESULT (GPR[RT]);
f2b30012
AC		 1041}
1042
1043
c0a4c3ba
AC		 1044
1045:function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
1046{
f3bdd368 1047 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
c0a4c3ba 1048 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
f3bdd368 1049 TRACE_ALU_RESULT (GPR[rt]);
c0a4c3ba
AC		 1050}
1051
f2b30012
AC		 1052011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1053"daddu r<RT>, r<RS>, <IMMEDIATE>"
1054*mipsIII:
1055*mipsIV:
23850e92 1056*vr5000:
15232df4
FCE		 1057// start-sanitize-vr4320
1058*vr4320:
1059// end-sanitize-vr4320
90ad43b2
AC		 1060// start-sanitize-vr5400
1061*vr5400:
1062// end-sanitize-vr5400
f2b30012
AC		 1063// start-sanitize-r5900
1064*r5900:
1065// end-sanitize-r5900
f2b30012
AC		 1066// start-sanitize-tx19
1067*tx19:
1068// end-sanitize-tx19
1069{
c0a4c3ba 1070 do_daddiu (SD_, RS, RT, IMMEDIATE);
f2b30012
AC		 1071}
1072
1073
c0a4c3ba
AC		 1074
1075:function:::void:do_daddu:int rs, int rt, int rd
1076{
f3bdd368 1077 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 1078 GPR[rd] = GPR[rs] + GPR[rt];
f3bdd368 1079 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 1080}
1081
f2b30012
AC		 1082000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1083"daddu r<RD>, r<RS>, r<RT>"
1084*mipsIII:
1085*mipsIV:
23850e92 1086*vr5000:
15232df4
FCE		 1087// start-sanitize-vr4320
1088*vr4320:
1089// end-sanitize-vr4320
90ad43b2
AC		 1090// start-sanitize-vr5400
1091*vr5400:
1092// end-sanitize-vr5400
f2b30012
AC		 1093// start-sanitize-r5900
1094*r5900:
1095// end-sanitize-r5900
f2b30012
AC		 1096// start-sanitize-tx19
1097*tx19:
1098// end-sanitize-tx19
1099{
c0a4c3ba 1100 do_daddu (SD_, RS, RT, RD);
f2b30012
AC		 1101}
1102
1103
c0a4c3ba
AC		 1104
1105:function:64::void:do_ddiv:int rs, int rt
f2b30012 1106{
94dda41a 1107 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 1108 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
f2b30012 1109 {
c0a4c3ba
AC		 1110 signed64 n = GPR[rs];
1111 signed64 d = GPR[rt];
f2b30012
AC		 1112 if (d == 0)
1113 {
1114 LO = SIGNED64 (0x8000000000000000);
1115 HI = 0;
1116 }
1117 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1118 {
1119 LO = SIGNED64 (0x8000000000000000);
1120 HI = 0;
1121 }
1122 else
1123 {
1124 LO = (n / d);
1125 HI = (n % d);
1126 }
1127 }
f3bdd368 1128 TRACE_ALU_RESULT2 (HI, LO);
f2b30012
AC		 1129}
1130
c0a4c3ba
AC		 1131000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1132"ddiv r<RS>, r<RT>"
f2b30012
AC		 1133*mipsIII:
1134*mipsIV:
23850e92 1135*vr5000:
15232df4
FCE		 1136// start-sanitize-vr4320
1137*vr4320:
1138// end-sanitize-vr4320
90ad43b2
AC		 1139// start-sanitize-vr5400
1140*vr5400:
1141// end-sanitize-vr5400
c0a4c3ba
AC		 1142// start-sanitize-r5900
1143*r5900:
1144// end-sanitize-r5900
f2b30012
AC		 1145// start-sanitize-tx19
1146*tx19:
1147// end-sanitize-tx19
c0a4c3ba
AC		 1148{
1149 do_ddiv (SD_, RS, RT);
1150}
1151
1152
1153
1154:function:64::void:do_ddivu:int rs, int rt
f2b30012 1155{
94dda41a 1156 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 1157 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
f2b30012 1158 {
c0a4c3ba
AC		 1159 unsigned64 n = GPR[rs];
1160 unsigned64 d = GPR[rt];
f2b30012
AC		 1161 if (d == 0)
1162 {
1163 LO = SIGNED64 (0x8000000000000000);
1164 HI = 0;
1165 }
1166 else
1167 {
1168 LO = (n / d);
1169 HI = (n % d);
1170 }
1171 }
f3bdd368 1172 TRACE_ALU_RESULT2 (HI, LO);
f2b30012
AC		 1173}
1174
c0a4c3ba
AC		 1175000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1176"ddivu r<RS>, r<RT>"
1177*mipsIII:
1178*mipsIV:
23850e92 1179*vr5000:
15232df4
FCE		 1180// start-sanitize-vr4320
1181*vr4320:
1182// end-sanitize-vr4320
90ad43b2
AC		 1183// start-sanitize-vr5400
1184*vr5400:
1185// end-sanitize-vr5400
f2b30012
AC		 1186// start-sanitize-tx19
1187*tx19:
1188// end-sanitize-tx19
c0a4c3ba
AC		 1189{
1190 do_ddivu (SD_, RS, RT);
1191}
1192
1193
1194
1195:function:::void:do_div:int rs, int rt
f2b30012 1196{
94dda41a 1197 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 1198 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
f2b30012 1199 {
c0a4c3ba
AC		 1200 signed32 n = GPR[rs];
1201 signed32 d = GPR[rt];
f2b30012
AC		 1202 if (d == 0)
1203 {
1204 LO = EXTEND32 (0x80000000);
1205 HI = EXTEND32 (0);
1206 }
ca6f76d1 1207 else if (n == SIGNED32 (0x80000000) && d == -1)
f2b30012
AC		 1208 {
1209 LO = EXTEND32 (0x80000000);
1210 HI = EXTEND32 (0);
1211 }
1212 else
1213 {
1214 LO = EXTEND32 (n / d);
1215 HI = EXTEND32 (n % d);
1216 }
1217 }
f3bdd368 1218 TRACE_ALU_RESULT2 (HI, LO);
f2b30012
AC		 1219}
1220
c0a4c3ba
AC		 1221000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1222"div r<RS>, r<RT>"
23850e92
JL		 1223*mipsI,mipsII,mipsIII,mipsIV:
1224*vr5000:
15232df4
FCE		 1225// start-sanitize-vr4320
1226*vr4320:
1227// end-sanitize-vr4320
90ad43b2
AC		 1228// start-sanitize-vr5400
1229*vr5400:
1230// end-sanitize-vr5400
f2b30012
AC		 1231// start-sanitize-r5900
1232*r5900:
1233// end-sanitize-r5900
1234*r3900:
1235// start-sanitize-tx19
1236*tx19:
1237// end-sanitize-tx19
c0a4c3ba
AC		 1238{
1239 do_div (SD_, RS, RT);
1240}
1241
1242
1243
1244:function:::void:do_divu:int rs, int rt
f2b30012 1245{
94dda41a 1246 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 1247 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
f2b30012 1248 {
c0a4c3ba
AC		 1249 unsigned32 n = GPR[rs];
1250 unsigned32 d = GPR[rt];
f2b30012
AC		 1251 if (d == 0)
1252 {
1253 LO = EXTEND32 (0x80000000);
1254 HI = EXTEND32 (0);
1255 }
1256 else
1257 {
1258 LO = EXTEND32 (n / d);
1259 HI = EXTEND32 (n % d);
1260 }
1261 }
f3bdd368 1262 TRACE_ALU_RESULT2 (HI, LO);
f2b30012
AC		 1263}
1264
c0a4c3ba
AC		 1265000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1266"divu r<RS>, r<RT>"
1267*mipsI,mipsII,mipsIII,mipsIV:
1268*vr5000:
1269// start-sanitize-vr4320
1270*vr4320:
1271// end-sanitize-vr4320
1272// start-sanitize-vr5400
1273*vr5400:
1274// end-sanitize-vr5400
1275// start-sanitize-r5900
1276*r5900:
1277// end-sanitize-r5900
1278*r3900:
1279// start-sanitize-tx19
1280*tx19:
1281// end-sanitize-tx19
1282{
1283 do_divu (SD_, RS, RT);
1284}
1285
f2b30012 1286
c0a4c3ba
AC		 1287
1288:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
23850e92
JL		 1289{
1290 unsigned64 lo;
1291 unsigned64 hi;
1292 unsigned64 m00;
1293 unsigned64 m01;
1294 unsigned64 m10;
1295 unsigned64 m11;
1296 unsigned64 mid;
1297 int sign;
1298 unsigned64 op1 = GPR[rs];
1299 unsigned64 op2 = GPR[rt];
94dda41a 1300 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 1301 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
23850e92
JL		 1302 /* make signed multiply unsigned */
1303 sign = 0;
1304 if (signed_p)
1305 {
1306 if (op1 < 0)
1307 {
1308 op1 = - op1;
1309 ++sign;
1310 }
1311 if (op2 < 0)
1312 {
1313 op2 = - op2;
1314 ++sign;
1315 }
1316 }
1317 /* multuply out the 4 sub products */
1318 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1319 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1320 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1321 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1322 /* add the products */
1323 mid = ((unsigned64) VH4_8 (m00)
1324 + (unsigned64) VL4_8 (m10)
1325 + (unsigned64) VL4_8 (m01));
1326 lo = U8_4 (mid, m00);
1327 hi = (m11
1328 + (unsigned64) VH4_8 (mid)
1329 + (unsigned64) VH4_8 (m01)
1330 + (unsigned64) VH4_8 (m10));
1331 /* fix the sign */
1332 if (sign & 1)
1333 {
1334 lo = -lo;
1335 if (lo == 0)
1336 hi = -hi;
1337 else
1338 hi = -hi - 1;
1339 }
1340 /* save the result HI/LO (and a gpr) */
1341 LO = lo;
1342 HI = hi;
1343 if (rd != 0)
1344 GPR[rd] = lo;
f3bdd368 1345 TRACE_ALU_RESULT2 (HI, LO);
23850e92
JL		 1346}
1347
c0a4c3ba
AC		 1348:function:::void:do_dmult:int rs, int rt, int rd
1349{
1350 do_dmultx (SD_, rs, rt, rd, 1);
1351}
23850e92 1352
f2b30012
AC		 1353000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1354"dmult r<RS>, r<RT>"
23850e92 1355*mipsIII,mipsIV:
f2b30012
AC		 1356// start-sanitize-tx19
1357*tx19:
1358// end-sanitize-tx19
15232df4
FCE		 1359// start-sanitize-vr4320
1360*vr4320:
1361// end-sanitize-vr4320
f2b30012 1362{
c0a4c3ba 1363 do_dmult (SD_, RS, RT, 0);
f2b30012
AC		 1364}
1365
23850e92
JL		 1366000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1367"dmult r<RS>, r<RT>":RD == 0
1368"dmult r<RD>, r<RS>, r<RT>"
1369*vr5000:
90ad43b2
AC		 1370// start-sanitize-vr5400
1371*vr5400:
1372// end-sanitize-vr5400
23850e92 1373{
c0a4c3ba 1374 do_dmult (SD_, RS, RT, RD);
23850e92
JL		 1375}
1376
1377
1378
c0a4c3ba
AC		 1379:function:::void:do_dmultu:int rs, int rt, int rd
1380{
1381 do_dmultx (SD_, rs, rt, rd, 0);
1382}
1383
23850e92
JL		 1384000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1385"dmultu r<RS>, r<RT>"
1386*mipsIII,mipsIV:
f2b30012
AC		 1387// start-sanitize-tx19
1388*tx19:
1389// end-sanitize-tx19
15232df4
FCE		 1390// start-sanitize-vr4320
1391*vr4320:
1392// end-sanitize-vr4320
f2b30012 1393{
c0a4c3ba 1394 do_dmultu (SD_, RS, RT, 0);
23850e92
JL		 1395}
1396
1397000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1398"dmultu r<RD>, r<RS>, r<RT>":RD == 0
1399"dmultu r<RS>, r<RT>"
1400*vr5000:
1401// start-sanitize-vr5400
1402*vr5400:
1403// end-sanitize-vr5400
1404{
c0a4c3ba 1405 do_dmultu (SD_, RS, RT, RD);
f2b30012
AC		 1406}
1407
1408
23850e92 1409
055ee297 141000000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
01b9cd49 1411"dsll r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1412*mipsIII:
1413*mipsIV:
23850e92 1414*vr5000:
15232df4
FCE		 1415// start-sanitize-vr4320
1416*vr4320:
1417// end-sanitize-vr4320
90ad43b2
AC		 1418// start-sanitize-vr5400
1419*vr5400:
1420// end-sanitize-vr5400
f2b30012
AC		 1421// start-sanitize-r5900
1422*r5900:
1423// end-sanitize-r5900
f2b30012
AC		 1424// start-sanitize-tx19
1425*tx19:
1426// end-sanitize-tx19
1427{
01b9cd49 1428 int s = SHIFT;
055ee297 1429 GPR[RD] = GPR[RT] << s;
f2b30012
AC		 1430}
1431
1432
055ee297 143300000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
01b9cd49 1434"dsll32 r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1435*mipsIII:
1436*mipsIV:
23850e92 1437*vr5000:
15232df4
FCE		 1438// start-sanitize-vr4320
1439*vr4320:
1440// end-sanitize-vr4320
90ad43b2
AC		 1441// start-sanitize-vr5400
1442*vr5400:
1443// end-sanitize-vr5400
f2b30012
AC		 1444// start-sanitize-r5900
1445*r5900:
1446// end-sanitize-r5900
f2b30012
AC		 1447// start-sanitize-tx19
1448*tx19:
1449// end-sanitize-tx19
1450{
01b9cd49 1451 int s = 32 + SHIFT;
055ee297 1452 GPR[RD] = GPR[RT] << s;
f2b30012
AC		 1453}
1454
1455
c0a4c3ba 1456
f2b30012
AC		 1457000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1458"dsllv r<RD>, r<RT>, r<RS>"
1459*mipsIII:
1460*mipsIV:
23850e92 1461*vr5000:
15232df4
FCE		 1462// start-sanitize-vr4320
1463*vr4320:
1464// end-sanitize-vr4320
90ad43b2
AC		 1465// start-sanitize-vr5400
1466*vr5400:
1467// end-sanitize-vr5400
f2b30012
AC		 1468// start-sanitize-r5900
1469*r5900:
1470// end-sanitize-r5900
f2b30012
AC		 1471// start-sanitize-tx19
1472*tx19:
1473// end-sanitize-tx19
1474{
055ee297
AC		 1475 int s = MASKED64 (GPR[RS], 5, 0);
1476 GPR[RD] = GPR[RT] << s;
f2b30012
AC		 1477}
1478
1479
c0a4c3ba 1480
055ee297 148100000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
01b9cd49 1482"dsra r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1483*mipsIII:
1484*mipsIV:
23850e92 1485*vr5000:
15232df4
FCE		 1486// start-sanitize-vr4320
1487*vr4320:
1488// end-sanitize-vr4320
90ad43b2
AC		 1489// start-sanitize-vr5400
1490*vr5400:
1491// end-sanitize-vr5400
f2b30012
AC		 1492// start-sanitize-r5900
1493*r5900:
1494// end-sanitize-r5900
f2b30012
AC		 1495// start-sanitize-tx19
1496*tx19:
1497// end-sanitize-tx19
1498{
01b9cd49 1499 int s = SHIFT;
055ee297 1500 GPR[RD] = ((signed64) GPR[RT]) >> s;
f2b30012
AC		 1501}
1502
1503
055ee297 150400000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
01b9cd49 1505"dsra32 r<RT>, r<RD>, <SHIFT>"
f2b30012
AC		 1506*mipsIII:
1507*mipsIV:
23850e92 1508*vr5000:
15232df4
FCE		 1509// start-sanitize-vr4320
1510*vr4320:
1511// end-sanitize-vr4320
90ad43b2
AC		 1512// start-sanitize-vr5400
1513*vr5400:
1514// end-sanitize-vr5400
f2b30012
AC		 1515// start-sanitize-r5900
1516*r5900:
1517// end-sanitize-r5900
f2b30012
AC		 1518// start-sanitize-tx19
1519*tx19:
1520// end-sanitize-tx19
1521{
01b9cd49 1522 int s = 32 + SHIFT;
055ee297 1523 GPR[RD] = ((signed64) GPR[RT]) >> s;
f2b30012
AC		 1524}
1525
1526
74025eee 1527:function:::void:do_dsrav:int rs, int rt, int rd
c0a4c3ba
AC		 1528{
1529 int s = MASKED64 (GPR[rs], 5, 0);
f3bdd368 1530 TRACE_ALU_INPUT2 (GPR[rt], s);
c0a4c3ba 1531 GPR[rd] = ((signed64) GPR[rt]) >> s;
f3bdd368 1532 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 1533}
1534
f2b30012
AC		 1535000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1536"dsra32 r<RT>, r<RD>, r<RS>"
1537*mipsIII:
1538*mipsIV:
23850e92 1539*vr5000:
15232df4
FCE		 1540// start-sanitize-vr4320
1541*vr4320:
1542// end-sanitize-vr4320
90ad43b2
AC		 1543// start-sanitize-vr5400
1544*vr5400:
1545// end-sanitize-vr5400
f2b30012
AC		 1546// start-sanitize-r5900
1547*r5900:
1548// end-sanitize-r5900
f2b30012
AC		 1549// start-sanitize-tx19
1550*tx19:
1551// end-sanitize-tx19
1552{
74025eee 1553 do_dsrav (SD_, RS, RT, RD);
f2b30012
AC		 1554}
1555
1556
055ee297 155700000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
74025eee 1558"dsrl r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1559*mipsIII:
1560*mipsIV:
23850e92 1561*vr5000:
15232df4
FCE		 1562// start-sanitize-vr4320
1563*vr4320:
1564// end-sanitize-vr4320
90ad43b2
AC		 1565// start-sanitize-vr5400
1566*vr5400:
1567// end-sanitize-vr5400
f2b30012
AC		 1568// start-sanitize-r5900
1569*r5900:
1570// end-sanitize-r5900
f2b30012
AC		 1571// start-sanitize-tx19
1572*tx19:
1573// end-sanitize-tx19
1574{
01b9cd49 1575 int s = SHIFT;
055ee297 1576 GPR[RD] = (unsigned64) GPR[RT] >> s;
f2b30012
AC		 1577}
1578
1579
055ee297 158000000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
01b9cd49 1581"dsrl32 r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1582*mipsIII:
1583*mipsIV:
23850e92 1584*vr5000:
15232df4
FCE		 1585// start-sanitize-vr4320
1586*vr4320:
1587// end-sanitize-vr4320
90ad43b2
AC		 1588// start-sanitize-vr5400
1589*vr5400:
1590// end-sanitize-vr5400
f2b30012
AC		 1591// start-sanitize-r5900
1592*r5900:
1593// end-sanitize-r5900
f2b30012
AC		 1594// start-sanitize-tx19
1595*tx19:
1596// end-sanitize-tx19
1597{
01b9cd49 1598 int s = 32 + SHIFT;
055ee297 1599 GPR[RD] = (unsigned64) GPR[RT] >> s;
f2b30012
AC		 1600}
1601
1602
1603000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1604"dsrl32 r<RD>, r<RT>, r<RS>"
1605*mipsIII:
1606*mipsIV:
23850e92 1607*vr5000:
15232df4
FCE		 1608// start-sanitize-vr4320
1609*vr4320:
1610// end-sanitize-vr4320
90ad43b2
AC		 1611// start-sanitize-vr5400
1612*vr5400:
1613// end-sanitize-vr5400
f2b30012
AC		 1614// start-sanitize-r5900
1615*r5900:
1616// end-sanitize-r5900
f2b30012
AC		 1617// start-sanitize-tx19
1618*tx19:
1619// end-sanitize-tx19
1620{
055ee297
AC		 1621 int s = MASKED64 (GPR[RS], 5, 0);
1622 GPR[RD] = (unsigned64) GPR[RT] >> s;
f2b30012
AC		 1623}
1624
1625
1626000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1627"dsub r<RD>, r<RS>, r<RT>"
1628*mipsIII:
1629*mipsIV:
23850e92 1630*vr5000:
15232df4
FCE		 1631// start-sanitize-vr4320
1632*vr4320:
1633// end-sanitize-vr4320
90ad43b2
AC		 1634// start-sanitize-vr5400
1635*vr5400:
1636// end-sanitize-vr5400
f2b30012
AC		 1637// start-sanitize-r5900
1638*r5900:
1639// end-sanitize-r5900
f2b30012
AC		 1640// start-sanitize-tx19
1641*tx19:
1642// end-sanitize-tx19
1643{
26feb3a8
AC		 1644 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1645 {
1646 ALU64_BEGIN (GPR[RS]);
1647 ALU64_SUB (GPR[RT]);
1648 ALU64_END (GPR[RD]);
1649 }
1650 TRACE_ALU_RESULT (GPR[RD]);
f2b30012
AC		 1651}
1652
1653
c0a4c3ba
AC		 1654:function:::void:do_dsubu:int rs, int rt, int rd
1655{
f3bdd368 1656 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 1657 GPR[rd] = GPR[rs] - GPR[rt];
f3bdd368 1658 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 1659}
1660
f2b30012
AC		 1661000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1662"dsubu r<RD>, r<RS>, r<RT>"
1663*mipsIII:
1664*mipsIV:
23850e92 1665*vr5000:
15232df4
FCE		 1666// start-sanitize-vr4320
1667*vr4320:
1668// end-sanitize-vr4320
90ad43b2
AC		 1669// start-sanitize-vr5400
1670*vr5400:
1671// end-sanitize-vr5400
f2b30012
AC		 1672// start-sanitize-r5900
1673*r5900:
1674// end-sanitize-r5900
f2b30012
AC		 1675// start-sanitize-tx19
1676*tx19:
1677// end-sanitize-tx19
1678{
c0a4c3ba 1679 do_dsubu (SD_, RS, RT, RD);
f2b30012
AC		 1680}
1681
1682
1683000010,26.INSTR_INDEX:NORMAL:32::J
1684"j <INSTR_INDEX>"
23850e92
JL		 1685*mipsI,mipsII,mipsIII,mipsIV:
1686*vr5000:
15232df4
FCE		 1687// start-sanitize-vr4320
1688*vr4320:
1689// end-sanitize-vr4320
90ad43b2
AC		 1690// start-sanitize-vr5400
1691*vr5400:
1692// end-sanitize-vr5400
f2b30012
AC		 1693// start-sanitize-r5900
1694*r5900:
1695// end-sanitize-r5900
1696*r3900:
1697// start-sanitize-tx19
1698*tx19:
1699// end-sanitize-tx19
1700{
49a76833 1701 /* NOTE: The region used is that of the delay slot NIA and NOT the
f2b30012 1702 current instruction */
49a76833
AC		 1703 address_word region = (NIA & MASK (63, 28));
1704 DELAY_SLOT (region | (INSTR_INDEX << 2));
f2b30012
AC		 1705}
1706
1707
1708000011,26.INSTR_INDEX:NORMAL:32::JAL
1709"jal <INSTR_INDEX>"
23850e92
JL		 1710*mipsI,mipsII,mipsIII,mipsIV:
1711*vr5000:
15232df4
FCE		 1712// start-sanitize-vr4320
1713*vr4320:
1714// end-sanitize-vr4320
90ad43b2
AC		 1715// start-sanitize-vr5400
1716*vr5400:
1717// end-sanitize-vr5400
f2b30012
AC		 1718// start-sanitize-r5900
1719*r5900:
1720// end-sanitize-r5900
1721*r3900:
1722// start-sanitize-tx19
1723*tx19:
1724// end-sanitize-tx19
1725{
1726 /* NOTE: The region used is that of the delay slot and NOT the
1727 current instruction */
49a76833 1728 address_word region = (NIA & MASK (63, 28));
055ee297 1729 GPR[31] = CIA + 8;
49a76833 1730 DELAY_SLOT (region | (INSTR_INDEX << 2));
f2b30012
AC		 1731}
1732
1733
1734000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1735"jalr r<RS>":RD == 31
1736"jalr r<RD>, r<RS>"
23850e92
JL		 1737*mipsI,mipsII,mipsIII,mipsIV:
1738*vr5000:
15232df4
FCE		 1739// start-sanitize-vr4320
1740*vr4320:
1741// end-sanitize-vr4320
90ad43b2
AC		 1742// start-sanitize-vr5400
1743*vr5400:
1744// end-sanitize-vr5400
f2b30012
AC		 1745// start-sanitize-r5900
1746*r5900:
1747// end-sanitize-r5900
1748*r3900:
1749// start-sanitize-tx19
1750*tx19:
1751// end-sanitize-tx19
1752{
055ee297
AC		 1753 address_word temp = GPR[RS];
1754 GPR[RD] = CIA + 8;
49a76833 1755 DELAY_SLOT (temp);
f2b30012
AC		 1756}
1757
1758
1759000000,5.RS,000000000000000001000:SPECIAL:32::JR
1760"jr r<RS>"
23850e92
JL		 1761*mipsI,mipsII,mipsIII,mipsIV:
1762*vr5000:
15232df4
FCE		 1763// start-sanitize-vr4320
1764*vr4320:
1765// end-sanitize-vr4320
90ad43b2
AC		 1766// start-sanitize-vr5400
1767*vr5400:
1768// end-sanitize-vr5400
f2b30012
AC		 1769// start-sanitize-r5900
1770*r5900:
1771// end-sanitize-r5900
1772*r3900:
1773// start-sanitize-tx19
1774*tx19:
1775// end-sanitize-tx19
1776{
49a76833 1777 DELAY_SLOT (GPR[RS]);
f2b30012
AC		 1778}
1779
1780
ebcfd86a 1781:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
a48e8c8d 1782{
ebcfd86a
FCE		 1783 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1784 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1785 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1786 unsigned int byte;
a48e8c8d
AC		 1787 address_word paddr;
1788 int uncached;
ebcfd86a
FCE		 1789 unsigned64 memval;
1790 address_word vaddr;
1791
1792 vaddr = base + offset;
1793 if ((vaddr & access) != 0)
1794 SignalExceptionAddressLoad ();
1795 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1796 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1797 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1798 byte = ((vaddr & mask) ^ bigendiancpu);
1799 return (memval >> (8 * byte));
a48e8c8d
AC		 1800}
1801
ebcfd86a 1802
f2b30012
AC		 1803100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1804"lb r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 1805*mipsI,mipsII,mipsIII,mipsIV:
1806*vr5000:
15232df4
FCE		 1807// start-sanitize-vr4320
1808*vr4320:
1809// end-sanitize-vr4320
90ad43b2
AC		 1810// start-sanitize-vr5400
1811*vr5400:
1812// end-sanitize-vr5400
f2b30012
AC		 1813// start-sanitize-r5900
1814*r5900:
1815// end-sanitize-r5900
1816*r3900:
1817// start-sanitize-tx19
1818*tx19:
1819// end-sanitize-tx19
1820{
ebcfd86a 1821 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
f2b30012
AC		 1822}
1823
1824
1825100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1826"lbu r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 1827*mipsI,mipsII,mipsIII,mipsIV:
1828*vr5000:
15232df4
FCE		 1829// start-sanitize-vr4320
1830*vr4320:
1831// end-sanitize-vr4320
90ad43b2
AC		 1832// start-sanitize-vr5400
1833*vr5400:
1834// end-sanitize-vr5400
f2b30012
AC		 1835// start-sanitize-r5900
1836*r5900:
1837// end-sanitize-r5900
1838*r3900:
1839// start-sanitize-tx19
1840*tx19:
1841// end-sanitize-tx19
1842{
ebcfd86a 1843 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
f2b30012
AC		 1844}
1845
1846
1847110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1848"ld r<RT>, <OFFSET>(r<BASE>)"
1849*mipsIII:
1850*mipsIV:
23850e92 1851*vr5000:
15232df4
FCE		 1852// start-sanitize-vr4320
1853*vr4320:
1854// end-sanitize-vr4320
90ad43b2
AC		 1855// start-sanitize-vr5400
1856*vr5400:
1857// end-sanitize-vr5400
f2b30012
AC		 1858// start-sanitize-r5900
1859*r5900:
1860// end-sanitize-r5900
f2b30012
AC		 1861// start-sanitize-tx19
1862*tx19:
1863// end-sanitize-tx19
1864{
ebcfd86a 1865 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
f2b30012
AC		 1866}
1867
1868
49a6eed5 18691101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
f2b30012
AC		 1870"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1871*mipsII:
1872*mipsIII:
1873*mipsIV:
23850e92 1874*vr5000:
15232df4
FCE		 1875// start-sanitize-vr4320
1876*vr4320:
1877// end-sanitize-vr4320
90ad43b2
AC		 1878// start-sanitize-vr5400
1879*vr5400:
1880// end-sanitize-vr5400
f2b30012
AC		 1881*r3900:
1882// start-sanitize-tx19
1883*tx19:
1884// end-sanitize-tx19
1885{
ebcfd86a 1886 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
f2b30012
AC		 1887}
1888
1889
15232df4
FCE		 1890
1891
f2b30012
AC		 1892011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1893"ldl r<RT>, <OFFSET>(r<BASE>)"
1894*mipsIII:
1895*mipsIV:
23850e92 1896*vr5000:
15232df4
FCE		 1897// start-sanitize-vr4320
1898*vr4320:
1899// end-sanitize-vr4320
90ad43b2
AC		 1900// start-sanitize-vr5400
1901*vr5400:
1902// end-sanitize-vr5400
f2b30012
AC		 1903// start-sanitize-r5900
1904*r5900:
1905// end-sanitize-r5900
f2b30012
AC		 1906// start-sanitize-tx19
1907*tx19:
1908// end-sanitize-tx19
1909{
ebcfd86a 1910 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 1911}
1912
1913
1914011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1915"ldr r<RT>, <OFFSET>(r<BASE>)"
1916*mipsIII:
1917*mipsIV:
23850e92 1918*vr5000:
15232df4
FCE		 1919// start-sanitize-vr4320
1920*vr4320:
1921// end-sanitize-vr4320
90ad43b2
AC		 1922// start-sanitize-vr5400
1923*vr5400:
1924// end-sanitize-vr5400
f2b30012
AC		 1925// start-sanitize-r5900
1926*r5900:
1927// end-sanitize-r5900
f2b30012
AC		 1928// start-sanitize-tx19
1929*tx19:
1930// end-sanitize-tx19
1931{
ebcfd86a 1932 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 1933}
1934
1935
1936100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1937"lh r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 1938*mipsI,mipsII,mipsIII,mipsIV:
1939*vr5000:
15232df4
FCE		 1940// start-sanitize-vr4320
1941*vr4320:
1942// end-sanitize-vr4320
90ad43b2
AC		 1943// start-sanitize-vr5400
1944*vr5400:
1945// end-sanitize-vr5400
f2b30012
AC		 1946// start-sanitize-r5900
1947*r5900:
1948// end-sanitize-r5900
1949*r3900:
1950// start-sanitize-tx19
1951*tx19:
1952// end-sanitize-tx19
1953{
ebcfd86a 1954 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
f2b30012
AC		 1955}
1956
1957
1958100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1959"lhu r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 1960*mipsI,mipsII,mipsIII,mipsIV:
1961*vr5000:
15232df4
FCE		 1962// start-sanitize-vr4320
1963*vr4320:
1964// end-sanitize-vr4320
90ad43b2
AC		 1965// start-sanitize-vr5400
1966*vr5400:
1967// end-sanitize-vr5400
f2b30012
AC		 1968// start-sanitize-r5900
1969*r5900:
1970// end-sanitize-r5900
1971*r3900:
1972// start-sanitize-tx19
1973*tx19:
1974// end-sanitize-tx19
1975{
ebcfd86a 1976 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
f2b30012
AC		 1977}
1978
1979
1980110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1981"ll r<RT>, <OFFSET>(r<BASE>)"
1982*mipsII:
1983*mipsIII:
1984*mipsIV:
23850e92 1985*vr5000:
15232df4
FCE		 1986// start-sanitize-vr4320
1987*vr4320:
1988// end-sanitize-vr4320
90ad43b2
AC		 1989// start-sanitize-vr5400
1990*vr5400:
1991// end-sanitize-vr5400
f2b30012
AC		 1992// start-sanitize-r5900
1993*r5900:
1994// end-sanitize-r5900
f2b30012
AC		 1995// start-sanitize-tx19
1996*tx19:
1997// end-sanitize-tx19
1998{
1999 unsigned32 instruction = instruction_0;
055ee297
AC		 2000 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2001 int destreg = ((instruction >> 16) & 0x0000001F);
2002 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2003 {
49a76833
AC		 2004 address_word vaddr = ((unsigned64)op1 + offset);
2005 address_word paddr;
f2b30012
AC		 2006 int uncached;
2007 if ((vaddr & 3) != 0)
055ee297 2008 SignalExceptionAddressLoad();
f2b30012
AC		 2009 else
2010 {
2011 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2012 {
2013 unsigned64 memval = 0;
2014 unsigned64 memval1 = 0;
2015 unsigned64 mask = 0x7;
2016 unsigned int shift = 2;
055ee297
AC		 2017 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2018 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2019 unsigned int byte;
f2b30012
AC		 2020 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2021 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2022 byte = ((vaddr & mask) ^ (bigend << shift));
2023 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2024 LLBIT = 1;
2025 }
2026 }
2027 }
2028}
2029
2030
2031110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2032"lld r<RT>, <OFFSET>(r<BASE>)"
2033*mipsIII:
2034*mipsIV:
23850e92 2035*vr5000:
15232df4
FCE		 2036// start-sanitize-vr4320
2037*vr4320:
2038// end-sanitize-vr4320
90ad43b2
AC		 2039// start-sanitize-vr5400
2040*vr5400:
2041// end-sanitize-vr5400
f2b30012
AC		 2042// start-sanitize-r5900
2043*r5900:
2044// end-sanitize-r5900
f2b30012
AC		 2045// start-sanitize-tx19
2046*tx19:
2047// end-sanitize-tx19
2048{
2049 unsigned32 instruction = instruction_0;
055ee297
AC		 2050 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2051 int destreg = ((instruction >> 16) & 0x0000001F);
2052 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2053 {
49a76833
AC		 2054 address_word vaddr = ((unsigned64)op1 + offset);
2055 address_word paddr;
f2b30012
AC		 2056 int uncached;
2057 if ((vaddr & 7) != 0)
055ee297 2058 SignalExceptionAddressLoad();
f2b30012
AC		 2059 else
2060 {
2061 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2062 {
2063 unsigned64 memval = 0;
2064 unsigned64 memval1 = 0;
f2b30012
AC		 2065 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2066 GPR[destreg] = memval;
2067 LLBIT = 1;
2068 }
2069 }
2070 }
2071}
2072
2073
2074001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2075"lui r<RT>, <IMMEDIATE>"
23850e92
JL		 2076*mipsI,mipsII,mipsIII,mipsIV:
2077*vr5000:
15232df4
FCE		 2078// start-sanitize-vr4320
2079*vr4320:
2080// end-sanitize-vr4320
90ad43b2
AC		 2081// start-sanitize-vr5400
2082*vr5400:
2083// end-sanitize-vr5400
f2b30012
AC		 2084// start-sanitize-r5900
2085*r5900:
2086// end-sanitize-r5900
2087*r3900:
2088// start-sanitize-tx19
2089*tx19:
2090// end-sanitize-tx19
2091{
97f4d183 2092 TRACE_ALU_INPUT1 (IMMEDIATE);
055ee297 2093 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
97f4d183 2094 TRACE_ALU_RESULT (GPR[RT]);
f2b30012
AC		 2095}
2096
2097
2098100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2099"lw r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 2100*mipsI,mipsII,mipsIII,mipsIV:
2101*vr5000:
15232df4
FCE		 2102// start-sanitize-vr4320
2103*vr4320:
2104// end-sanitize-vr4320
90ad43b2
AC		 2105// start-sanitize-vr5400
2106*vr5400:
2107// end-sanitize-vr5400
f2b30012
AC		 2108// start-sanitize-r5900
2109*r5900:
2110// end-sanitize-r5900
2111*r3900:
2112// start-sanitize-tx19
2113*tx19:
2114// end-sanitize-tx19
2115{
ebcfd86a 2116 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
f2b30012
AC		 2117}
2118
2119
49a6eed5 21201100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
f2b30012 2121"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 2122*mipsI,mipsII,mipsIII,mipsIV:
2123*vr5000:
15232df4
FCE		 2124// start-sanitize-vr4320
2125*vr4320:
2126// end-sanitize-vr4320
90ad43b2
AC		 2127// start-sanitize-vr5400
2128*vr5400:
2129// end-sanitize-vr5400
f2b30012
AC		 2130// start-sanitize-r5900
2131*r5900:
2132// end-sanitize-r5900
2133*r3900:
2134// start-sanitize-tx19
2135*tx19:
2136// end-sanitize-tx19
2137{
ebcfd86a
FCE		 2138 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2139}
2140
2141
2142:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2143{
2144 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2145 address_word reverseendian = (ReverseEndian ? -1 : 0);
2146 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2147 unsigned int byte;
0e797366 2148 unsigned int word;
ebcfd86a
FCE		 2149 address_word paddr;
2150 int uncached;
2151 unsigned64 memval;
2152 address_word vaddr;
0e797366
AC		 2153 int nr_lhs_bits;
2154 int nr_rhs_bits;
2155 unsigned_word lhs_mask;
2156 unsigned_word temp;
ebcfd86a
FCE		 2157
2158 vaddr = base + offset;
2159 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2160 paddr = (paddr ^ (reverseendian & mask));
2161 if (BigEndianMem == 0)
2162 paddr = paddr & ~access;
0e797366
AC		 2163
2164 /* compute where within the word/mem we are */
2165 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2166 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2167 nr_lhs_bits = 8 * byte + 8;
2168 nr_rhs_bits = 8 * access - 8 * byte;
2169 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2170
2171 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2172 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2173 (long) ((unsigned64) paddr >> 32), (long) paddr,
2174 word, byte, nr_lhs_bits, nr_rhs_bits); */
2175
2176 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2177 if (word == 0)
ebcfd86a 2178 {
0e797366
AC		 2179 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2180 temp = (memval << nr_rhs_bits);
ebcfd86a
FCE		 2181 }
2182 else
2183 {
0e797366
AC		 2184 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2185 temp = (memval >> nr_lhs_bits);
ebcfd86a 2186 }
0e797366
AC		 2187 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2188 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2189
2190 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2191 (long) ((unsigned64) memval >> 32), (long) memval,
2192 (long) ((unsigned64) temp >> 32), (long) temp,
2193 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2194 (long) (rt >> 32), (long) rt); */
ebcfd86a 2195 return rt;
f2b30012
AC		 2196}
2197
2198
2199100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2200"lwl r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 2201*mipsI,mipsII,mipsIII,mipsIV:
2202*vr5000:
15232df4
FCE		 2203// start-sanitize-vr4320
2204*vr4320:
2205// end-sanitize-vr4320
90ad43b2
AC		 2206// start-sanitize-vr5400
2207*vr5400:
2208// end-sanitize-vr5400
f2b30012
AC		 2209// start-sanitize-r5900
2210*r5900:
2211// end-sanitize-r5900
2212*r3900:
2213// start-sanitize-tx19
2214*tx19:
2215// end-sanitize-tx19
2216{
ebcfd86a
FCE		 2217 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2218}
2219
2220
2221:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2222{
2223 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2224 address_word reverseendian = (ReverseEndian ? -1 : 0);
2225 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2226 unsigned int byte;
2227 address_word paddr;
2228 int uncached;
2229 unsigned64 memval;
2230 address_word vaddr;
2231
2232 vaddr = base + offset;
2233 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2234 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2235 paddr = (paddr ^ (reverseendian & mask));
2236 if (BigEndianMem != 0)
2237 paddr = paddr & ~access;
2238 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2239 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
2240 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2241 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2242 (long) paddr, byte, (long) paddr, (long) memval); */
f2b30012 2243 {
ebcfd86a
FCE		 2244 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2245 rt &= ~screen;
2246 rt |= (memval >> (8 * byte)) & screen;
f2b30012 2247 }
ebcfd86a 2248 return rt;
f2b30012
AC		 2249}
2250
2251
2252100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2253"lwr r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 2254*mipsI,mipsII,mipsIII,mipsIV:
2255*vr5000:
15232df4
FCE		 2256// start-sanitize-vr4320
2257*vr4320:
2258// end-sanitize-vr4320
90ad43b2
AC		 2259// start-sanitize-vr5400
2260*vr5400:
2261// end-sanitize-vr5400
f2b30012
AC		 2262// start-sanitize-r5900
2263*r5900:
2264// end-sanitize-r5900
2265*r3900:
2266// start-sanitize-tx19
2267*tx19:
2268// end-sanitize-tx19
2269{
ebcfd86a 2270 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
f2b30012
AC		 2271}
2272
2273
2274100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2275"lwu r<RT>, <OFFSET>(r<BASE>)"
2276*mipsIII:
2277*mipsIV:
23850e92 2278*vr5000:
15232df4
FCE		 2279// start-sanitize-vr4320
2280*vr4320:
2281// end-sanitize-vr4320
90ad43b2
AC		 2282// start-sanitize-vr5400
2283*vr5400:
2284// end-sanitize-vr5400
f2b30012
AC		 2285// start-sanitize-r5900
2286*r5900:
2287// end-sanitize-r5900
f2b30012
AC		 2288// start-sanitize-tx19
2289*tx19:
2290// end-sanitize-tx19
2291{
ebcfd86a 2292 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
f2b30012
AC		 2293}
2294
2295
c0a4c3ba
AC		 2296:function:::void:do_mfhi:int rd
2297{
421cbaae 2298 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 2299 TRACE_ALU_INPUT1 (HI);
c0a4c3ba 2300 GPR[rd] = HI;
f3bdd368 2301 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 2302}
2303
f2b30012
AC		 2304000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2305"mfhi r<RD>"
23850e92
JL		 2306*mipsI,mipsII,mipsIII,mipsIV:
2307*vr5000:
15232df4
FCE		 2308// start-sanitize-vr4320
2309*vr4320:
2310// end-sanitize-vr4320
90ad43b2
AC		 2311// start-sanitize-vr5400
2312*vr5400:
2313// end-sanitize-vr5400
f2b30012
AC		 2314// start-sanitize-r5900
2315*r5900:
2316// end-sanitize-r5900
2317*r3900:
2318// start-sanitize-tx19
2319*tx19:
2320// end-sanitize-tx19
2321{
c0a4c3ba
AC		 2322 do_mfhi (SD_, RD);
2323}
2324
2325
2326
2327:function:::void:do_mflo:int rd
2328{
421cbaae 2329 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
f3bdd368 2330 TRACE_ALU_INPUT1 (LO);
c0a4c3ba 2331 GPR[rd] = LO;
f3bdd368 2332 TRACE_ALU_RESULT (GPR[rd]);
f2b30012
AC		 2333}
2334
f2b30012
AC		 2335000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2336"mflo r<RD>"
23850e92
JL		 2337*mipsI,mipsII,mipsIII,mipsIV:
2338*vr5000:
15232df4
FCE		 2339// start-sanitize-vr4320
2340*vr4320:
2341// end-sanitize-vr4320
90ad43b2
AC		 2342// start-sanitize-vr5400
2343*vr5400:
2344// end-sanitize-vr5400
f2b30012
AC		 2345// start-sanitize-r5900
2346*r5900:
2347// end-sanitize-r5900
2348*r3900:
2349// start-sanitize-tx19
2350*tx19:
2351// end-sanitize-tx19
2352{
c0a4c3ba 2353 do_mflo (SD_, RD);
f2b30012
AC		 2354}
2355
2356
c0a4c3ba 2357
f2b30012
AC		 2358000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2359"movn r<RD>, r<RS>, r<RT>"
2360*mipsIV:
23850e92 2361*vr5000:
15232df4
FCE		 2362// start-sanitize-vr4320
2363*vr4320:
2364// end-sanitize-vr4320
90ad43b2
AC		 2365// start-sanitize-vr5400
2366*vr5400:
2367// end-sanitize-vr5400
f2b30012
AC		 2368// start-sanitize-r5900
2369*r5900:
2370// end-sanitize-r5900
2371{
055ee297
AC		 2372 if (GPR[RT] != 0)
2373 GPR[RD] = GPR[RS];
f2b30012
AC		 2374}
2375
2376
c0a4c3ba 2377
f2b30012
AC		 2378000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2379"movz r<RD>, r<RS>, r<RT>"
2380*mipsIV:
23850e92 2381*vr5000:
15232df4
FCE		 2382// start-sanitize-vr4320
2383*vr4320:
2384// end-sanitize-vr4320
90ad43b2
AC		 2385// start-sanitize-vr5400
2386*vr5400:
2387// end-sanitize-vr5400
f2b30012
AC		 2388// start-sanitize-r5900
2389*r5900:
2390// end-sanitize-r5900
2391{
055ee297
AC		 2392 if (GPR[RT] == 0)
2393 GPR[RD] = GPR[RS];
f2b30012
AC		 2394}
2395
2396
c0a4c3ba 2397
f2b30012
AC		 2398000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2399"mthi r<RS>"
23850e92
JL		 2400*mipsI,mipsII,mipsIII,mipsIV:
2401*vr5000:
15232df4
FCE		 2402// start-sanitize-vr4320
2403*vr4320:
2404// end-sanitize-vr4320
90ad43b2
AC		 2405// start-sanitize-vr5400
2406*vr5400:
2407// end-sanitize-vr5400
f2b30012
AC		 2408// start-sanitize-r5900
2409*r5900:
2410// end-sanitize-r5900
2411*r3900:
2412// start-sanitize-tx19
2413*tx19:
2414// end-sanitize-tx19
2415{
421cbaae 2416 check_mt_hilo (SD_, HIHISTORY);
055ee297 2417 HI = GPR[RS];
f2b30012
AC		 2418}
2419
2420
c0a4c3ba 2421
f2b30012
AC		 2422000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2423"mtlo r<RS>"
23850e92
JL		 2424*mipsI,mipsII,mipsIII,mipsIV:
2425*vr5000:
15232df4
FCE		 2426// start-sanitize-vr4320
2427*vr4320:
2428// end-sanitize-vr4320
90ad43b2
AC		 2429// start-sanitize-vr5400
2430*vr5400:
2431// end-sanitize-vr5400
f2b30012
AC		 2432// start-sanitize-r5900
2433*r5900:
2434// end-sanitize-r5900
2435*r3900:
2436// start-sanitize-tx19
2437*tx19:
2438// end-sanitize-tx19
2439{
421cbaae 2440 check_mt_hilo (SD_, LOHISTORY);
055ee297 2441 LO = GPR[RS];
f2b30012
AC		 2442}
2443
2444
c0a4c3ba
AC		 2445
2446:function:::void:do_mult:int rs, int rt, int rd
2447{
2448 signed64 prod;
94dda41a 2449 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 2450 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba
AC		 2451 prod = (((signed64)(signed32) GPR[rs])
2452 * ((signed64)(signed32) GPR[rt]));
2453 LO = EXTEND32 (VL4_8 (prod));
2454 HI = EXTEND32 (VH4_8 (prod));
2455 if (rd != 0)
2456 GPR[rd] = LO;
f3bdd368 2457 TRACE_ALU_RESULT2 (HI, LO);
c0a4c3ba
AC		 2458}
2459
030843d7 2460000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
f2b30012 2461"mult r<RS>, r<RT>"
23850e92 2462*mipsI,mipsII,mipsIII,mipsIV:
15232df4
FCE		 2463// start-sanitize-vr4320
2464*vr4320:
2465// end-sanitize-vr4320
030843d7 2466{
c0a4c3ba 2467 do_mult (SD_, RS, RT, 0);
030843d7 2468}
15232df4
FCE		 2469
2470
030843d7
AC		 2471000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2472"mult r<RD>, r<RS>, r<RT>"
23850e92 2473*vr5000:
90ad43b2
AC		 2474// start-sanitize-vr5400
2475*vr5400:
2476// end-sanitize-vr5400
f2b30012
AC		 2477// start-sanitize-r5900
2478*r5900:
2479// end-sanitize-r5900
2480*r3900:
2481// start-sanitize-tx19
2482*tx19:
2483// end-sanitize-tx19
2484{
c0a4c3ba
AC		 2485 do_mult (SD_, RS, RT, RD);
2486}
2487
2488
2489:function:::void:do_multu:int rs, int rt, int rd
2490{
2491 unsigned64 prod;
94dda41a 2492 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 2493 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba
AC		 2494 prod = (((unsigned64)(unsigned32) GPR[rs])
2495 * ((unsigned64)(unsigned32) GPR[rt]));
f2b30012
AC		 2496 LO = EXTEND32 (VL4_8 (prod));
2497 HI = EXTEND32 (VH4_8 (prod));
c0a4c3ba
AC		 2498 if (rd != 0)
2499 GPR[rd] = LO;
f3bdd368 2500 TRACE_ALU_RESULT2 (HI, LO);
f2b30012
AC		 2501}
2502
030843d7 2503000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
f2b30012 2504"multu r<RS>, r<RT>"
23850e92 2505*mipsI,mipsII,mipsIII,mipsIV:
15232df4
FCE		 2506// start-sanitize-vr4320
2507*vr4320:
2508// end-sanitize-vr4320
030843d7 2509{
c0a4c3ba 2510 do_multu (SD_, RS, RT, 0);
030843d7 2511}
c0a4c3ba 2512
030843d7
AC		 2513000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2514"multu r<RD>, r<RS>, r<RT>"
23850e92 2515*vr5000:
90ad43b2
AC		 2516// start-sanitize-vr5400
2517*vr5400:
2518// end-sanitize-vr5400
f2b30012
AC		 2519// start-sanitize-r5900
2520*r5900:
2521// end-sanitize-r5900
2522*r3900:
2523// start-sanitize-tx19
2524*tx19:
2525// end-sanitize-tx19
2526{
c0a4c3ba 2527 do_multu (SD_, RS, RT, 0);
f2b30012
AC		 2528}
2529
2530
c0a4c3ba
AC		 2531:function:::void:do_nor:int rs, int rt, int rd
2532{
f3bdd368 2533 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 2534 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
f3bdd368 2535 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 2536}
2537
f2b30012
AC		 2538000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2539"nor r<RD>, r<RS>, r<RT>"
23850e92
JL		 2540*mipsI,mipsII,mipsIII,mipsIV:
2541*vr5000:
15232df4
FCE		 2542// start-sanitize-vr4320
2543*vr4320:
2544// end-sanitize-vr4320
90ad43b2
AC		 2545// start-sanitize-vr5400
2546*vr5400:
2547// end-sanitize-vr5400
f2b30012
AC		 2548// start-sanitize-r5900
2549*r5900:
2550// end-sanitize-r5900
2551*r3900:
2552// start-sanitize-tx19
2553*tx19:
2554// end-sanitize-tx19
2555{
c0a4c3ba 2556 do_nor (SD_, RS, RT, RD);
f2b30012
AC		 2557}
2558
2559
c0a4c3ba
AC		 2560:function:::void:do_or:int rs, int rt, int rd
2561{
f3bdd368 2562 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 2563 GPR[rd] = (GPR[rs] | GPR[rt]);
f3bdd368 2564 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 2565}
2566
f2b30012
AC		 2567000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2568"or r<RD>, r<RS>, r<RT>"
23850e92
JL		 2569*mipsI,mipsII,mipsIII,mipsIV:
2570*vr5000:
15232df4
FCE		 2571// start-sanitize-vr4320
2572*vr4320:
2573// end-sanitize-vr4320
90ad43b2
AC		 2574// start-sanitize-vr5400
2575*vr5400:
2576// end-sanitize-vr5400
f2b30012
AC		 2577// start-sanitize-r5900
2578*r5900:
2579// end-sanitize-r5900
2580*r3900:
2581// start-sanitize-tx19
2582*tx19:
2583// end-sanitize-tx19
2584{
c0a4c3ba 2585 do_or (SD_, RS, RT, RD);
f2b30012
AC		 2586}
2587
2588
f3bdd368
AC		 2589
2590:function:::void:do_ori:int rs, int rt, unsigned immediate
2591{
2592 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2593 GPR[rt] = (GPR[rs] | immediate);
2594 TRACE_ALU_RESULT (GPR[rt]);
2595}
2596
f2b30012 2597001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
055ee297 2598"ori r<RT>, r<RS>, <IMMEDIATE>"
23850e92
JL		 2599*mipsI,mipsII,mipsIII,mipsIV:
2600*vr5000:
15232df4
FCE		 2601// start-sanitize-vr4320
2602*vr4320:
2603// end-sanitize-vr4320
90ad43b2
AC		 2604// start-sanitize-vr5400
2605*vr5400:
2606// end-sanitize-vr5400
f2b30012
AC		 2607// start-sanitize-r5900
2608*r5900:
2609// end-sanitize-r5900
2610*r3900:
2611// start-sanitize-tx19
2612*tx19:
2613// end-sanitize-tx19
2614{
f3bdd368 2615 do_ori (SD_, RS, RT, IMMEDIATE);
f2b30012
AC		 2616}
2617
2618
2619110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2620*mipsIV:
23850e92 2621*vr5000:
15232df4
FCE		 2622// start-sanitize-vr4320
2623*vr4320:
2624// end-sanitize-vr4320
90ad43b2
AC		 2625// start-sanitize-vr5400
2626*vr5400:
2627// end-sanitize-vr5400
f2b30012
AC		 2628// start-sanitize-r5900
2629*r5900:
2630// end-sanitize-r5900
2631{
2632 unsigned32 instruction = instruction_0;
055ee297
AC		 2633 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2634 int hint = ((instruction >> 16) & 0x0000001F);
2635 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2636 {
49a76833
AC		 2637 address_word vaddr = ((unsigned64)op1 + offset);
2638 address_word paddr;
f2b30012
AC		 2639 int uncached;
2640 {
2641 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2642 Prefetch(uncached,paddr,vaddr,isDATA,hint);
2643 }
2644 }
2645}
2646
ebcfd86a
FCE		 2647:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2648{
2649 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2650 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2651 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2652 unsigned int byte;
2653 address_word paddr;
2654 int uncached;
2655 unsigned64 memval;
2656 address_word vaddr;
2657
2658 vaddr = base + offset;
2659 if ((vaddr & access) != 0)
2660 SignalExceptionAddressStore ();
2661 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2662 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2663 byte = ((vaddr & mask) ^ bigendiancpu);
2664 memval = (word << (8 * byte));
2665 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2666}
2667
2668
f2b30012
AC		 2669101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2670"sb r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 2671*mipsI,mipsII,mipsIII,mipsIV:
2672*vr5000:
15232df4
FCE		 2673// start-sanitize-vr4320
2674*vr4320:
2675// end-sanitize-vr4320
90ad43b2
AC		 2676// start-sanitize-vr5400
2677*vr5400:
2678// end-sanitize-vr5400
f2b30012
AC		 2679// start-sanitize-r5900
2680*r5900:
2681// end-sanitize-r5900
2682*r3900:
2683// start-sanitize-tx19
2684*tx19:
2685// end-sanitize-tx19
2686{
ebcfd86a 2687 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 2688}
2689
2690
2691111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2692"sc r<RT>, <OFFSET>(r<BASE>)"
2693*mipsII:
2694*mipsIII:
2695*mipsIV:
23850e92 2696*vr5000:
15232df4
FCE		 2697// start-sanitize-vr4320
2698*vr4320:
2699// end-sanitize-vr4320
90ad43b2
AC		 2700// start-sanitize-vr5400
2701*vr5400:
2702// end-sanitize-vr5400
f2b30012
AC		 2703// start-sanitize-r5900
2704*r5900:
2705// end-sanitize-r5900
f2b30012
AC		 2706// start-sanitize-tx19
2707*tx19:
2708// end-sanitize-tx19
2709{
2710 unsigned32 instruction = instruction_0;
055ee297
AC		 2711 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2712 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2713 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2714 {
49a76833
AC		 2715 address_word vaddr = ((unsigned64)op1 + offset);
2716 address_word paddr;
f2b30012
AC		 2717 int uncached;
2718 if ((vaddr & 3) != 0)
055ee297 2719 SignalExceptionAddressStore();
f2b30012
AC		 2720 else
2721 {
2722 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2723 {
2724 unsigned64 memval = 0;
2725 unsigned64 memval1 = 0;
2726 unsigned64 mask = 0x7;
2727 unsigned int byte;
2728 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2729 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2730 memval = ((unsigned64) op2 << (8 * byte));
2731 if (LLBIT)
2732 {
2733 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2734 }
2735 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2736 }
2737 }
2738 }
2739}
2740
2741
2742111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2743"scd r<RT>, <OFFSET>(r<BASE>)"
2744*mipsIII:
2745*mipsIV:
23850e92 2746*vr5000:
15232df4
FCE		 2747// start-sanitize-vr4320
2748*vr4320:
2749// end-sanitize-vr4320
90ad43b2
AC		 2750// start-sanitize-vr5400
2751*vr5400:
2752// end-sanitize-vr5400
f2b30012
AC		 2753// start-sanitize-r5900
2754*r5900:
2755// end-sanitize-r5900
f2b30012
AC		 2756// start-sanitize-tx19
2757*tx19:
2758// end-sanitize-tx19
2759{
2760 unsigned32 instruction = instruction_0;
055ee297
AC		 2761 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2762 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2763 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2764 {
49a76833
AC		 2765 address_word vaddr = ((unsigned64)op1 + offset);
2766 address_word paddr;
f2b30012
AC		 2767 int uncached;
2768 if ((vaddr & 7) != 0)
055ee297 2769 SignalExceptionAddressStore();
f2b30012
AC		 2770 else
2771 {
2772 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2773 {
2774 unsigned64 memval = 0;
2775 unsigned64 memval1 = 0;
2776 memval = op2;
2777 if (LLBIT)
2778 {
2779 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2780 }
2781 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2782 }
2783 }
2784 }
2785}
2786
2787
2788111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2789"sd r<RT>, <OFFSET>(r<BASE>)"
2790*mipsIII:
2791*mipsIV:
23850e92 2792*vr5000:
15232df4
FCE		 2793// start-sanitize-vr4320
2794*vr4320:
2795// end-sanitize-vr4320
90ad43b2
AC		 2796// start-sanitize-vr5400
2797*vr5400:
2798// end-sanitize-vr5400
f2b30012
AC		 2799// start-sanitize-r5900
2800*r5900:
2801// end-sanitize-r5900
f2b30012
AC		 2802// start-sanitize-tx19
2803*tx19:
2804// end-sanitize-tx19
ebcfd86a
FCE		 2805{
2806 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
15232df4 2807}
15232df4
FCE		 2808
2809
ebcfd86a
FCE		 28101111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2811"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2812*mipsII:
2813*mipsIII:
2814*mipsIV:
2815*vr5000:
2816// start-sanitize-vr4320
2817*vr4320:
2818// end-sanitize-vr4320
2819// start-sanitize-vr5400
2820*vr5400:
2821// end-sanitize-vr5400
ebcfd86a
FCE		 2822// start-sanitize-tx19
2823*tx19:
2824// end-sanitize-tx19
2825{
2826 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2827}
2828
15232df4 2829
f2b30012
AC		 2830101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2831"sdl r<RT>, <OFFSET>(r<BASE>)"
2832*mipsIII:
2833*mipsIV:
23850e92 2834*vr5000:
15232df4
FCE		 2835// start-sanitize-vr4320
2836*vr4320:
2837// end-sanitize-vr4320
90ad43b2
AC		 2838// start-sanitize-vr5400
2839*vr5400:
2840// end-sanitize-vr5400
f2b30012
AC		 2841// start-sanitize-r5900
2842*r5900:
2843// end-sanitize-r5900
f2b30012
AC		 2844// start-sanitize-tx19
2845*tx19:
2846// end-sanitize-tx19
2847{
ebcfd86a 2848 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 2849}
2850
2851
2852101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2853"sdr r<RT>, <OFFSET>(r<BASE>)"
2854*mipsIII:
2855*mipsIV:
23850e92 2856*vr5000:
15232df4
FCE		 2857// start-sanitize-vr4320
2858*vr4320:
2859// end-sanitize-vr4320
90ad43b2
AC		 2860// start-sanitize-vr5400
2861*vr5400:
2862// end-sanitize-vr5400
f2b30012
AC		 2863// start-sanitize-r5900
2864*r5900:
2865// end-sanitize-r5900
f2b30012
AC		 2866// start-sanitize-tx19
2867*tx19:
2868// end-sanitize-tx19
2869{
ebcfd86a 2870 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 2871}
2872
2873
2874101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2875"sh r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 2876*mipsI,mipsII,mipsIII,mipsIV:
2877*vr5000:
15232df4
FCE		 2878// start-sanitize-vr4320
2879*vr4320:
2880// end-sanitize-vr4320
90ad43b2
AC		 2881// start-sanitize-vr5400
2882*vr5400:
2883// end-sanitize-vr5400
f2b30012
AC		 2884// start-sanitize-r5900
2885*r5900:
2886// end-sanitize-r5900
2887*r3900:
2888// start-sanitize-tx19
2889*tx19:
2890// end-sanitize-tx19
2891{
ebcfd86a 2892 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 2893}
2894
2895
c0a4c3ba
AC		 2896:function:::void:do_sll:int rt, int rd, int shift
2897{
2898 unsigned32 temp = (GPR[rt] << shift);
f3bdd368 2899 TRACE_ALU_INPUT2 (GPR[rt], shift);
c0a4c3ba 2900 GPR[rd] = EXTEND32 (temp);
f3bdd368 2901 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 2902}
2903
055ee297
AC		 290400000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2905"sll r<RD>, r<RT>, <SHIFT>"
23850e92
JL		 2906*mipsI,mipsII,mipsIII,mipsIV:
2907*vr5000:
15232df4
FCE		 2908// start-sanitize-vr4320
2909*vr4320:
2910// end-sanitize-vr4320
90ad43b2
AC		 2911// start-sanitize-vr5400
2912*vr5400:
2913// end-sanitize-vr5400
f2b30012
AC		 2914// start-sanitize-r5900
2915*r5900:
2916// end-sanitize-r5900
2917*r3900:
2918// start-sanitize-tx19
2919*tx19:
2920// end-sanitize-tx19
2921{
c0a4c3ba 2922 do_sll (SD_, RT, RD, SHIFT);
f2b30012
AC		 2923}
2924
2925
c0a4c3ba
AC		 2926:function:::void:do_sllv:int rs, int rt, int rd
2927{
2928 int s = MASKED (GPR[rs], 4, 0);
2929 unsigned32 temp = (GPR[rt] << s);
f3bdd368 2930 TRACE_ALU_INPUT2 (GPR[rt], s);
c0a4c3ba 2931 GPR[rd] = EXTEND32 (temp);
f3bdd368 2932 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 2933}
2934
055ee297 2935000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
f2b30012 2936"sllv r<RD>, r<RT>, r<RS>"
23850e92
JL		 2937*mipsI,mipsII,mipsIII,mipsIV:
2938*vr5000:
15232df4
FCE		 2939// start-sanitize-vr4320
2940*vr4320:
2941// end-sanitize-vr4320
90ad43b2
AC		 2942// start-sanitize-vr5400
2943*vr5400:
2944// end-sanitize-vr5400
f2b30012
AC		 2945// start-sanitize-r5900
2946*r5900:
2947// end-sanitize-r5900
2948*r3900:
2949// start-sanitize-tx19
2950*tx19:
2951// end-sanitize-tx19
2952{
c0a4c3ba 2953 do_sllv (SD_, RS, RT, RD);
f2b30012
AC		 2954}
2955
2956
c0a4c3ba
AC		 2957:function:::void:do_slt:int rs, int rt, int rd
2958{
f3bdd368 2959 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 2960 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
f3bdd368 2961 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 2962}
2963
f2b30012
AC		 2964000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2965"slt r<RD>, r<RS>, r<RT>"
23850e92
JL		 2966*mipsI,mipsII,mipsIII,mipsIV:
2967*vr5000:
15232df4
FCE		 2968// start-sanitize-vr4320
2969*vr4320:
2970// end-sanitize-vr4320
90ad43b2
AC		 2971// start-sanitize-vr5400
2972*vr5400:
2973// end-sanitize-vr5400
f2b30012
AC		 2974// start-sanitize-r5900
2975*r5900:
2976// end-sanitize-r5900
2977*r3900:
2978// start-sanitize-tx19
2979*tx19:
2980// end-sanitize-tx19
2981{
c0a4c3ba 2982 do_slt (SD_, RS, RT, RD);
f2b30012
AC		 2983}
2984
2985
c0a4c3ba
AC		 2986:function:::void:do_slti:int rs, int rt, unsigned16 immediate
2987{
f3bdd368 2988 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
c0a4c3ba 2989 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
f3bdd368 2990 TRACE_ALU_RESULT (GPR[rt]);
c0a4c3ba
AC		 2991}
2992
f2b30012 2993001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
055ee297 2994"slti r<RT>, r<RS>, <IMMEDIATE>"
23850e92
JL		 2995*mipsI,mipsII,mipsIII,mipsIV:
2996*vr5000:
15232df4
FCE		 2997// start-sanitize-vr4320
2998*vr4320:
2999// end-sanitize-vr4320
90ad43b2
AC		 3000// start-sanitize-vr5400
3001*vr5400:
3002// end-sanitize-vr5400
f2b30012
AC		 3003// start-sanitize-r5900
3004*r5900:
3005// end-sanitize-r5900
3006*r3900:
3007// start-sanitize-tx19
3008*tx19:
3009// end-sanitize-tx19
3010{
c0a4c3ba 3011 do_slti (SD_, RS, RT, IMMEDIATE);
f2b30012
AC		 3012}
3013
3014
c0a4c3ba
AC		 3015:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3016{
f3bdd368 3017 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
c0a4c3ba 3018 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
f3bdd368 3019 TRACE_ALU_RESULT (GPR[rt]);
c0a4c3ba
AC		 3020}
3021
f2b30012 3022001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
055ee297 3023"sltiu r<RT>, r<RS>, <IMMEDIATE>"
23850e92
JL		 3024*mipsI,mipsII,mipsIII,mipsIV:
3025*vr5000:
15232df4
FCE		 3026// start-sanitize-vr4320
3027*vr4320:
3028// end-sanitize-vr4320
90ad43b2
AC		 3029// start-sanitize-vr5400
3030*vr5400:
3031// end-sanitize-vr5400
f2b30012
AC		 3032// start-sanitize-r5900
3033*r5900:
3034// end-sanitize-r5900
3035*r3900:
3036// start-sanitize-tx19
3037*tx19:
3038// end-sanitize-tx19
3039{
c0a4c3ba
AC		 3040 do_sltiu (SD_, RS, RT, IMMEDIATE);
3041}
3042
3043
3044
3045:function:::void:do_sltu:int rs, int rt, int rd
3046{
f3bdd368 3047 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 3048 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
f3bdd368 3049 TRACE_ALU_RESULT (GPR[rd]);
f2b30012
AC		 3050}
3051
3052000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3053"sltu r<RD>, r<RS>, r<RT>"
23850e92
JL		 3054*mipsI,mipsII,mipsIII,mipsIV:
3055*vr5000:
15232df4
FCE		 3056// start-sanitize-vr4320
3057*vr4320:
3058// end-sanitize-vr4320
90ad43b2
AC		 3059// start-sanitize-vr5400
3060*vr5400:
3061// end-sanitize-vr5400
f2b30012
AC		 3062// start-sanitize-r5900
3063*r5900:
3064// end-sanitize-r5900
3065*r3900:
3066// start-sanitize-tx19
3067*tx19:
3068// end-sanitize-tx19
3069{
f3bdd368 3070 do_sltu (SD_, RS, RT, RD);
f2b30012
AC		 3071}
3072
3073
c0a4c3ba
AC		 3074:function:::void:do_sra:int rt, int rd, int shift
3075{
3076 signed32 temp = (signed32) GPR[rt] >> shift;
f3bdd368 3077 TRACE_ALU_INPUT2 (GPR[rt], shift);
c0a4c3ba 3078 GPR[rd] = EXTEND32 (temp);
f3bdd368 3079 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 3080}
3081
055ee297
AC		 3082000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3083"sra r<RD>, r<RT>, <SHIFT>"
23850e92
JL		 3084*mipsI,mipsII,mipsIII,mipsIV:
3085*vr5000:
15232df4
FCE		 3086// start-sanitize-vr4320
3087*vr4320:
3088// end-sanitize-vr4320
90ad43b2
AC		 3089// start-sanitize-vr5400
3090*vr5400:
3091// end-sanitize-vr5400
f2b30012
AC		 3092// start-sanitize-r5900
3093*r5900:
3094// end-sanitize-r5900
3095*r3900:
3096// start-sanitize-tx19
3097*tx19:
3098// end-sanitize-tx19
3099{
c0a4c3ba 3100 do_sra (SD_, RT, RD, SHIFT);
f2b30012
AC		 3101}
3102
3103
74025eee
AC		 3104
3105:function:::void:do_srav:int rs, int rt, int rd
3106{
3107 int s = MASKED (GPR[rs], 4, 0);
3108 signed32 temp = (signed32) GPR[rt] >> s;
3109 TRACE_ALU_INPUT2 (GPR[rt], s);
3110 GPR[rd] = EXTEND32 (temp);
3111 TRACE_ALU_RESULT (GPR[rd]);
3112}
3113
f2b30012
AC		 3114000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3115"srav r<RD>, r<RT>, r<RS>"
23850e92
JL		 3116*mipsI,mipsII,mipsIII,mipsIV:
3117*vr5000:
15232df4
FCE		 3118// start-sanitize-vr4320
3119*vr4320:
3120// end-sanitize-vr4320
90ad43b2
AC		 3121// start-sanitize-vr5400
3122*vr5400:
3123// end-sanitize-vr5400
f2b30012
AC		 3124// start-sanitize-r5900
3125*r5900:
3126// end-sanitize-r5900
3127*r3900:
3128// start-sanitize-tx19
3129*tx19:
3130// end-sanitize-tx19
3131{
74025eee 3132 do_srav (SD_, RS, RT, RD);
f2b30012
AC		 3133}
3134
3135
74025eee 3136
c0a4c3ba
AC		 3137:function:::void:do_srl:int rt, int rd, int shift
3138{
3139 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
f3bdd368 3140 TRACE_ALU_INPUT2 (GPR[rt], shift);
c0a4c3ba 3141 GPR[rd] = EXTEND32 (temp);
f3bdd368 3142 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 3143}
3144
055ee297
AC		 3145000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3146"srl r<RD>, r<RT>, <SHIFT>"
23850e92
JL		 3147*mipsI,mipsII,mipsIII,mipsIV:
3148*vr5000:
15232df4
FCE		 3149// start-sanitize-vr4320
3150*vr4320:
3151// end-sanitize-vr4320
90ad43b2
AC		 3152// start-sanitize-vr5400
3153*vr5400:
3154// end-sanitize-vr5400
f2b30012
AC		 3155// start-sanitize-r5900
3156*r5900:
3157// end-sanitize-r5900
3158*r3900:
3159// start-sanitize-tx19
3160*tx19:
3161// end-sanitize-tx19
3162{
c0a4c3ba 3163 do_srl (SD_, RT, RD, SHIFT);
f2b30012
AC		 3164}
3165
3166
c0a4c3ba
AC		 3167:function:::void:do_srlv:int rs, int rt, int rd
3168{
3169 int s = MASKED (GPR[rs], 4, 0);
3170 unsigned32 temp = (unsigned32) GPR[rt] >> s;
f3bdd368 3171 TRACE_ALU_INPUT2 (GPR[rt], s);
c0a4c3ba 3172 GPR[rd] = EXTEND32 (temp);
f3bdd368 3173 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 3174}
3175
f2b30012
AC		 3176000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3177"srlv r<RD>, r<RT>, r<RS>"
23850e92
JL		 3178*mipsI,mipsII,mipsIII,mipsIV:
3179*vr5000:
15232df4
FCE		 3180// start-sanitize-vr4320
3181*vr4320:
3182// end-sanitize-vr4320
90ad43b2
AC		 3183// start-sanitize-vr5400
3184*vr5400:
3185// end-sanitize-vr5400
f2b30012
AC		 3186// start-sanitize-r5900
3187*r5900:
3188// end-sanitize-r5900
3189*r3900:
3190// start-sanitize-tx19
3191*tx19:
3192// end-sanitize-tx19
3193{
c0a4c3ba 3194 do_srlv (SD_, RS, RT, RD);
f2b30012
AC		 3195}
3196
3197
3198000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3199"sub r<RD>, r<RS>, r<RT>"
23850e92
JL		 3200*mipsI,mipsII,mipsIII,mipsIV:
3201*vr5000:
15232df4
FCE		 3202// start-sanitize-vr4320
3203*vr4320:
3204// end-sanitize-vr4320
90ad43b2
AC		 3205// start-sanitize-vr5400
3206*vr5400:
3207// end-sanitize-vr5400
f2b30012
AC		 3208// start-sanitize-r5900
3209*r5900:
3210// end-sanitize-r5900
3211*r3900:
3212// start-sanitize-tx19
3213*tx19:
3214// end-sanitize-tx19
3215{
26feb3a8
AC		 3216 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3217 {
3218 ALU32_BEGIN (GPR[RS]);
3219 ALU32_SUB (GPR[RT]);
3220 ALU32_END (GPR[RD]);
3221 }
3222 TRACE_ALU_RESULT (GPR[RD]);
f2b30012
AC		 3223}
3224
3225
c0a4c3ba
AC		 3226:function:::void:do_subu:int rs, int rt, int rd
3227{
f3bdd368
AC		 3228 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3229 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3230 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 3231}
3232
f2b30012
AC		 3233000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3234"subu r<RD>, r<RS>, r<RT>"
23850e92
JL		 3235*mipsI,mipsII,mipsIII,mipsIV:
3236*vr5000:
15232df4
FCE		 3237// start-sanitize-vr4320
3238*vr4320:
3239// end-sanitize-vr4320
90ad43b2
AC		 3240// start-sanitize-vr5400
3241*vr5400:
3242// end-sanitize-vr5400
f2b30012
AC		 3243// start-sanitize-r5900
3244*r5900:
3245// end-sanitize-r5900
3246*r3900:
3247// start-sanitize-tx19
3248*tx19:
3249// end-sanitize-tx19
3250{
c0a4c3ba 3251 do_subu (SD_, RS, RT, RD);
f2b30012
AC		 3252}
3253
3254
3255101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3256"sw r<RT>, <OFFSET>(r<BASE>)"
23850e92 3257*mipsI,mipsII,mipsIII,mipsIV:
ebcfd86a
FCE		 3258// start-sanitize-tx19
3259*tx19:
3260// end-sanitize-tx19
3261*r3900:
15232df4
FCE		 3262// start-sanitize-vr4320
3263*vr4320:
3264// end-sanitize-vr4320
ebcfd86a 3265*vr5000:
90ad43b2
AC		 3266// start-sanitize-vr5400
3267*vr5400:
3268// end-sanitize-vr5400
f2b30012
AC		 3269// start-sanitize-r5900
3270*r5900:
3271// end-sanitize-r5900
f2b30012 3272{
ebcfd86a 3273 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 3274}
3275
3276
085c1cb9 32771110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
f2b30012 3278"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 3279*mipsI,mipsII,mipsIII,mipsIV:
3280*vr5000:
15232df4
FCE		 3281// start-sanitize-vr4320
3282*vr4320:
3283// end-sanitize-vr4320
90ad43b2
AC		 3284// start-sanitize-vr5400
3285*vr5400:
3286// end-sanitize-vr5400
f2b30012
AC		 3287*r3900:
3288// start-sanitize-tx19
3289*tx19:
3290// end-sanitize-tx19
3291{
ebcfd86a
FCE		 3292 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3293}
3294
3295
3296
3297:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3298{
3299 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3300 address_word reverseendian = (ReverseEndian ? -1 : 0);
3301 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3302 unsigned int byte;
0e797366 3303 unsigned int word;
ebcfd86a
FCE		 3304 address_word paddr;
3305 int uncached;
3306 unsigned64 memval;
3307 address_word vaddr;
0e797366
AC		 3308 int nr_lhs_bits;
3309 int nr_rhs_bits;
ebcfd86a
FCE		 3310
3311 vaddr = base + offset;
3312 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3313 paddr = (paddr ^ (reverseendian & mask));
3314 if (BigEndianMem == 0)
3315 paddr = paddr & ~access;
0e797366
AC		 3316
3317 /* compute where within the word/mem we are */
3318 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3319 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3320 nr_lhs_bits = 8 * byte + 8;
3321 nr_rhs_bits = 8 * access - 8 * byte;
3322 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3323 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3324 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3325 (long) ((unsigned64) paddr >> 32), (long) paddr,
3326 word, byte, nr_lhs_bits, nr_rhs_bits); */
3327
3328 if (word == 0)
3329 {
3330 memval = (rt >> nr_rhs_bits);
3331 }
ebcfd86a 3332 else
0e797366
AC		 3333 {
3334 memval = (rt << nr_lhs_bits);
3335 }
3336 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3337 (long) ((unsigned64) rt >> 32), (long) rt,
3338 (long) ((unsigned64) memval >> 32), (long) memval); */
3339 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
f2b30012
AC		 3340}
3341
3342
3343101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3344"swl r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 3345*mipsI,mipsII,mipsIII,mipsIV:
3346*vr5000:
15232df4
FCE		 3347// start-sanitize-vr4320
3348*vr4320:
3349// end-sanitize-vr4320
90ad43b2
AC		 3350// start-sanitize-vr5400
3351*vr5400:
3352// end-sanitize-vr5400
f2b30012
AC		 3353// start-sanitize-r5900
3354*r5900:
3355// end-sanitize-r5900
3356*r3900:
3357// start-sanitize-tx19
3358*tx19:
3359// end-sanitize-tx19
3360{
ebcfd86a 3361 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 3362}
3363
3364
ebcfd86a
FCE		 3365:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3366{
3367 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3368 address_word reverseendian = (ReverseEndian ? -1 : 0);
3369 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3370 unsigned int byte;
3371 address_word paddr;
3372 int uncached;
3373 unsigned64 memval;
3374 address_word vaddr;
3375
3376 vaddr = base + offset;
3377 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3378 paddr = (paddr ^ (reverseendian & mask));
3379 if (BigEndianMem != 0)
3380 paddr &= ~access;
3381 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3382 memval = (rt << (byte * 8));
3383 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3384}
3385
f2b30012
AC		 3386101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3387"swr r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 3388*mipsI,mipsII,mipsIII,mipsIV:
3389*vr5000:
15232df4
FCE		 3390// start-sanitize-vr4320
3391*vr4320:
3392// end-sanitize-vr4320
90ad43b2
AC		 3393// start-sanitize-vr5400
3394*vr5400:
3395// end-sanitize-vr5400
f2b30012
AC		 3396// start-sanitize-r5900
3397*r5900:
3398// end-sanitize-r5900
3399*r3900:
3400// start-sanitize-tx19
3401*tx19:
3402// end-sanitize-tx19
3403{
ebcfd86a 3404 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 3405}
3406
3407
3408000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3409"sync":STYPE == 0
3410"sync <STYPE>"
3411*mipsII:
3412*mipsIII:
3413*mipsIV:
23850e92 3414*vr5000:
15232df4
FCE		 3415// start-sanitize-vr4320
3416*vr4320:
3417// end-sanitize-vr4320
90ad43b2
AC		 3418// start-sanitize-vr5400
3419*vr5400:
3420// end-sanitize-vr5400
f2b30012
AC		 3421// start-sanitize-r5900
3422*r5900:
3423// end-sanitize-r5900
3424*r3900:
3425// start-sanitize-tx19
3426*tx19:
3427// end-sanitize-tx19
3428{
085c1cb9 3429 SyncOperation (STYPE);
f2b30012
AC		 3430}
3431
3432
3433000000,20.CODE,001100:SPECIAL:32::SYSCALL
3434"syscall <CODE>"
23850e92
JL		 3435*mipsI,mipsII,mipsIII,mipsIV:
3436*vr5000:
15232df4
FCE		 3437// start-sanitize-vr4320
3438*vr4320:
3439// end-sanitize-vr4320
90ad43b2
AC		 3440// start-sanitize-vr5400
3441*vr5400:
3442// end-sanitize-vr5400
f2b30012
AC		 3443// start-sanitize-r5900
3444*r5900:
3445// end-sanitize-r5900
3446*r3900:
3447// start-sanitize-tx19
3448*tx19:
3449// end-sanitize-tx19
3450{
055ee297 3451 SignalException(SystemCall, instruction_0);
f2b30012
AC		 3452}
3453
3454
3455000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3456"teq r<RS>, r<RT>"
3457*mipsII:
3458*mipsIII:
3459*mipsIV:
23850e92 3460*vr5000:
15232df4
FCE		 3461// start-sanitize-vr4320
3462*vr4320:
3463// end-sanitize-vr4320
90ad43b2
AC		 3464// start-sanitize-vr5400
3465*vr5400:
3466// end-sanitize-vr5400
f2b30012
AC		 3467// start-sanitize-r5900
3468*r5900:
3469// end-sanitize-r5900
f2b30012
AC		 3470// start-sanitize-tx19
3471*tx19:
3472// end-sanitize-tx19
3473{
a94c5493 3474 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
055ee297 3475 SignalException(Trap, instruction_0);
f2b30012
AC		 3476}
3477
3478
3479000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3480"teqi r<RS>, <IMMEDIATE>"
3481*mipsII:
3482*mipsIII:
3483*mipsIV:
23850e92 3484*vr5000:
15232df4
FCE		 3485// start-sanitize-vr4320
3486*vr4320:
3487// end-sanitize-vr4320
90ad43b2
AC		 3488// start-sanitize-vr5400
3489*vr5400:
3490// end-sanitize-vr5400
f2b30012
AC		 3491// start-sanitize-r5900
3492*r5900:
3493// end-sanitize-r5900
f2b30012
AC		 3494// start-sanitize-tx19
3495*tx19:
3496// end-sanitize-tx19
3497{
a94c5493 3498 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
055ee297 3499 SignalException(Trap, instruction_0);
f2b30012
AC		 3500}
3501
3502
3503000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3504"tge r<RS>, r<RT>"
3505*mipsII:
3506*mipsIII:
3507*mipsIV:
23850e92 3508*vr5000:
15232df4
FCE		 3509// start-sanitize-vr4320
3510*vr4320:
3511// end-sanitize-vr4320
90ad43b2
AC		 3512// start-sanitize-vr5400
3513*vr5400:
3514// end-sanitize-vr5400
f2b30012
AC		 3515// start-sanitize-r5900
3516*r5900:
3517// end-sanitize-r5900
f2b30012
AC		 3518// start-sanitize-tx19
3519*tx19:
3520// end-sanitize-tx19
3521{
a94c5493 3522 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
055ee297 3523 SignalException(Trap, instruction_0);
f2b30012
AC		 3524}
3525
3526
3527000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3528"tgei r<RS>, <IMMEDIATE>"
3529*mipsII:
3530*mipsIII:
3531*mipsIV:
23850e92 3532*vr5000:
15232df4
FCE		 3533// start-sanitize-vr4320
3534*vr4320:
3535// end-sanitize-vr4320
90ad43b2
AC		 3536// start-sanitize-vr5400
3537*vr5400:
3538// end-sanitize-vr5400
f2b30012
AC		 3539// start-sanitize-r5900
3540*r5900:
3541// end-sanitize-r5900
f2b30012
AC		 3542// start-sanitize-tx19
3543*tx19:
3544// end-sanitize-tx19
3545{
a94c5493 3546 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
055ee297 3547 SignalException(Trap, instruction_0);
f2b30012
AC		 3548}
3549
3550
3551000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3552"tgeiu r<RS>, <IMMEDIATE>"
3553*mipsII:
3554*mipsIII:
3555*mipsIV:
23850e92 3556*vr5000:
15232df4
FCE		 3557// start-sanitize-vr4320
3558*vr4320:
3559// end-sanitize-vr4320
90ad43b2
AC		 3560// start-sanitize-vr5400
3561*vr5400:
3562// end-sanitize-vr5400
f2b30012
AC		 3563// start-sanitize-r5900
3564*r5900:
3565// end-sanitize-r5900
f2b30012
AC		 3566// start-sanitize-tx19
3567*tx19:
3568// end-sanitize-tx19
3569{
055ee297
AC		 3570 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3571 SignalException(Trap, instruction_0);
f2b30012
AC		 3572}
3573
3574
3575000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3576"tgeu r<RS>, r<RT>"
3577*mipsII:
3578*mipsIII:
3579*mipsIV:
23850e92 3580*vr5000:
15232df4
FCE		 3581// start-sanitize-vr4320
3582*vr4320:
3583// end-sanitize-vr4320
90ad43b2
AC		 3584// start-sanitize-vr5400
3585*vr5400:
3586// end-sanitize-vr5400
f2b30012
AC		 3587// start-sanitize-r5900
3588*r5900:
3589// end-sanitize-r5900
f2b30012
AC		 3590// start-sanitize-tx19
3591*tx19:
3592// end-sanitize-tx19
3593{
055ee297
AC		 3594 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3595 SignalException(Trap, instruction_0);
f2b30012
AC		 3596}
3597
3598
3599000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3600"tlt r<RS>, r<RT>"
3601*mipsII:
3602*mipsIII:
3603*mipsIV:
23850e92 3604*vr5000:
15232df4
FCE		 3605// start-sanitize-vr4320
3606*vr4320:
3607// end-sanitize-vr4320
90ad43b2
AC		 3608// start-sanitize-vr5400
3609*vr5400:
3610// end-sanitize-vr5400
f2b30012
AC		 3611// start-sanitize-r5900
3612*r5900:
3613// end-sanitize-r5900
f2b30012
AC		 3614// start-sanitize-tx19
3615*tx19:
3616// end-sanitize-tx19
3617{
a94c5493 3618 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
055ee297 3619 SignalException(Trap, instruction_0);
f2b30012
AC		 3620}
3621
3622
3623000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3624"tlti r<RS>, <IMMEDIATE>"
3625*mipsII:
3626*mipsIII:
3627*mipsIV:
23850e92 3628*vr5000:
15232df4
FCE		 3629// start-sanitize-vr4320
3630*vr4320:
3631// end-sanitize-vr4320
90ad43b2
AC		 3632// start-sanitize-vr5400
3633*vr5400:
3634// end-sanitize-vr5400
f2b30012
AC		 3635// start-sanitize-r5900
3636*r5900:
3637// end-sanitize-r5900
f2b30012
AC		 3638// start-sanitize-tx19
3639*tx19:
3640// end-sanitize-tx19
3641{
a94c5493 3642 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
055ee297 3643 SignalException(Trap, instruction_0);
f2b30012
AC		 3644}
3645
3646
3647000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3648"tltiu r<RS>, <IMMEDIATE>"
3649*mipsII:
3650*mipsIII:
3651*mipsIV:
23850e92 3652*vr5000:
15232df4
FCE		 3653// start-sanitize-vr4320
3654*vr4320:
3655// end-sanitize-vr4320
90ad43b2
AC		 3656// start-sanitize-vr5400
3657*vr5400:
3658// end-sanitize-vr5400
f2b30012
AC		 3659// start-sanitize-r5900
3660*r5900:
3661// end-sanitize-r5900
f2b30012
AC		 3662// start-sanitize-tx19
3663*tx19:
3664// end-sanitize-tx19
3665{
055ee297
AC		 3666 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3667 SignalException(Trap, instruction_0);
f2b30012
AC		 3668}
3669
3670
3671000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3672"tltu r<RS>, r<RT>"
3673*mipsII:
3674*mipsIII:
3675*mipsIV:
23850e92 3676*vr5000:
15232df4
FCE		 3677// start-sanitize-vr4320
3678*vr4320:
3679// end-sanitize-vr4320
90ad43b2
AC		 3680// start-sanitize-vr5400
3681*vr5400:
3682// end-sanitize-vr5400
f2b30012
AC		 3683// start-sanitize-r5900
3684*r5900:
3685// end-sanitize-r5900
f2b30012
AC		 3686// start-sanitize-tx19
3687*tx19:
3688// end-sanitize-tx19
3689{
055ee297
AC		 3690 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3691 SignalException(Trap, instruction_0);
f2b30012
AC		 3692}
3693
3694
3695000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3696"tne r<RS>, r<RT>"
3697*mipsII:
3698*mipsIII:
3699*mipsIV:
23850e92 3700*vr5000:
15232df4
FCE		 3701// start-sanitize-vr4320
3702*vr4320:
3703// end-sanitize-vr4320
90ad43b2
AC		 3704// start-sanitize-vr5400
3705*vr5400:
3706// end-sanitize-vr5400
f2b30012
AC		 3707// start-sanitize-r5900
3708*r5900:
3709// end-sanitize-r5900
f2b30012
AC		 3710// start-sanitize-tx19
3711*tx19:
3712// end-sanitize-tx19
3713{
a94c5493 3714 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
055ee297 3715 SignalException(Trap, instruction_0);
f2b30012
AC		 3716}
3717
3718
3719000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3720"tne r<RS>, <IMMEDIATE>"
3721*mipsII:
3722*mipsIII:
3723*mipsIV:
23850e92 3724*vr5000:
15232df4
FCE		 3725// start-sanitize-vr4320
3726*vr4320:
3727// end-sanitize-vr4320
90ad43b2
AC		 3728// start-sanitize-vr5400
3729*vr5400:
3730// end-sanitize-vr5400
f2b30012
AC		 3731// start-sanitize-r5900
3732*r5900:
3733// end-sanitize-r5900
f2b30012
AC		 3734// start-sanitize-tx19
3735*tx19:
3736// end-sanitize-tx19
3737{
a94c5493 3738 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
055ee297 3739 SignalException(Trap, instruction_0);
f2b30012
AC		 3740}
3741
3742
c0a4c3ba
AC		 3743:function:::void:do_xor:int rs, int rt, int rd
3744{
f3bdd368 3745 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 3746 GPR[rd] = GPR[rs] ^ GPR[rt];
f3bdd368 3747 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 3748}
3749
f2b30012
AC		 3750000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3751"xor r<RD>, r<RS>, r<RT>"
23850e92
JL		 3752*mipsI,mipsII,mipsIII,mipsIV:
3753*vr5000:
15232df4
FCE		 3754// start-sanitize-vr4320
3755*vr4320:
3756// end-sanitize-vr4320
90ad43b2
AC		 3757// start-sanitize-vr5400
3758*vr5400:
3759// end-sanitize-vr5400
f2b30012
AC		 3760// start-sanitize-r5900
3761*r5900:
3762// end-sanitize-r5900
3763*r3900:
3764// start-sanitize-tx19
3765*tx19:
3766// end-sanitize-tx19
3767{
c0a4c3ba 3768 do_xor (SD_, RS, RT, RD);
f2b30012
AC		 3769}
3770
3771
c0a4c3ba
AC		 3772:function:::void:do_xori:int rs, int rt, unsigned16 immediate
3773{
f3bdd368 3774 TRACE_ALU_INPUT2 (GPR[rs], immediate);
c0a4c3ba 3775 GPR[rt] = GPR[rs] ^ immediate;
f3bdd368 3776 TRACE_ALU_RESULT (GPR[rt]);
c0a4c3ba
AC		 3777}
3778
f2b30012 3779001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
055ee297 3780"xori r<RT>, r<RS>, <IMMEDIATE>"
23850e92
JL		 3781*mipsI,mipsII,mipsIII,mipsIV:
3782*vr5000:
15232df4
FCE		 3783// start-sanitize-vr4320
3784*vr4320:
3785// end-sanitize-vr4320
90ad43b2
AC		 3786// start-sanitize-vr5400
3787*vr5400:
3788// end-sanitize-vr5400
f2b30012
AC		 3789// start-sanitize-r5900
3790*r5900:
3791// end-sanitize-r5900
3792*r3900:
3793// start-sanitize-tx19
3794*tx19:
3795// end-sanitize-tx19
3796{
c0a4c3ba 3797 do_xori (SD_, RS, RT, IMMEDIATE);
f2b30012
AC		 3798}
3799
3800\f
3801//
3802// MIPS Architecture:
3803//
3804// FPU Instruction Set (COP1 & COP1X)
3805//
3806
3807
89d09738 3808:%s::::FMT:int fmt
055ee297
AC		 3809{
3810 switch (fmt)
3811 {
3812 case fmt_single: return "s";
3813 case fmt_double: return "d";
3814 case fmt_word: return "w";
3815 case fmt_long: return "l";
3816 default: return "?";
3817 }
3818}
3819
030843d7
AC		 3820:%s::::X:int x
3821{
3822 switch (x)
3823 {
3824 case 0: return "f";
3825 case 1: return "t";
3826 default: return "?";
3827 }
3828}
3829
89d09738 3830:%s::::TF:int tf
055ee297
AC		 3831{
3832 if (tf)
3833 return "t";
3834 else
3835 return "f";
3836}
3837
89d09738 3838:%s::::ND:int nd
055ee297
AC		 3839{
3840 if (nd)
3841 return "l";
3842 else
3843 return "";
3844}
3845
89d09738 3846:%s::::COND:int cond
055ee297
AC		 3847{
3848 switch (cond)
3849 {
3850 case 00: return "f";
3851 case 01: return "un";
3852 case 02: return "eq";
3853 case 03: return "ueq";
3854 case 04: return "olt";
3855 case 05: return "ult";
3856 case 06: return "ole";
3857 case 07: return "ule";
3858 case 010: return "sf";
3859 case 011: return "ngle";
3860 case 012: return "seq";
3861 case 013: return "ngl";
3862 case 014: return "lt";
3863 case 015: return "nge";
3864 case 016: return "le";
3865 case 017: return "ngt";
3866 default: return "?";
3867 }
3868}
3869
3870
f2b30012
AC		 3871010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3872"abs.%s<FMT> f<FD>, f<FS>"
23850e92
JL		 3873*mipsI,mipsII,mipsIII,mipsIV:
3874*vr5000:
15232df4
FCE		 3875// start-sanitize-vr4320
3876*vr4320:
3877// end-sanitize-vr4320
90ad43b2
AC		 3878// start-sanitize-vr5400
3879*vr5400:
3880// end-sanitize-vr5400
f2b30012
AC		 3881*r3900:
3882// start-sanitize-tx19
3883*tx19:
3884// end-sanitize-tx19
3885{
3886 unsigned32 instruction = instruction_0;
055ee297
AC		 3887 int destreg = ((instruction >> 6) & 0x0000001F);
3888 int fs = ((instruction >> 11) & 0x0000001F);
3889 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3890 {
3891 if ((format != fmt_single) && (format != fmt_double))
3892 SignalException(ReservedInstruction,instruction);
3893 else
3894 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3895 }
3896}
3897
3898
055ee297 3899
a48e8c8d 3900010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
f2b30012 3901"add.%s<FMT> f<FD>, f<FS>, f<FT>"
23850e92
JL		 3902*mipsI,mipsII,mipsIII,mipsIV:
3903*vr5000:
15232df4
FCE		 3904// start-sanitize-vr4320
3905*vr4320:
3906// end-sanitize-vr4320
90ad43b2
AC		 3907// start-sanitize-vr5400
3908*vr5400:
3909// end-sanitize-vr5400
f2b30012
AC		 3910*r3900:
3911// start-sanitize-tx19
3912*tx19:
3913// end-sanitize-tx19
3914{
3915 unsigned32 instruction = instruction_0;
055ee297
AC		 3916 int destreg = ((instruction >> 6) & 0x0000001F);
3917 int fs = ((instruction >> 11) & 0x0000001F);
3918 int ft = ((instruction >> 16) & 0x0000001F);
3919 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3920 {
3921 if ((format != fmt_single) && (format != fmt_double))
055ee297 3922 SignalException(ReservedInstruction, instruction);
f2b30012
AC		 3923 else
3924 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3925 }
3926}
3927
3928
23850e92 3929
f2b30012
AC		 3930// BC1F
3931// BC1FL
3932// BC1T
3933// BC1TL
23850e92
JL		 3934
3935010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3936"bc1%s<TF>%s<ND> <OFFSET>"
3937*mipsI,mipsII,mipsIII:
3938// start-sanitize-r5900
3939*r5900:
3940// end-sanitize-r5900
3941{
a48e8c8d 3942 TRACE_BRANCH_INPUT (PREVCOC1());
23850e92
JL		 3943 if (PREVCOC1() == TF)
3944 {
a48e8c8d
AC		 3945 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3946 TRACE_BRANCH_RESULT (dest);
3947 DELAY_SLOT (dest);
23850e92
JL		 3948 }
3949 else if (ND)
3950 {
a48e8c8d 3951 TRACE_BRANCH_RESULT (0);
23850e92
JL		 3952 NULLIFY_NEXT_INSTRUCTION ();
3953 }
a48e8c8d
AC		 3954 else
3955 {
3956 TRACE_BRANCH_RESULT (NIA);
3957 }
23850e92
JL		 3958}
3959
055ee297
AC		 3960010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3961"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3962"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
f2b30012 3963*mipsIV:
23850e92 3964*vr5000:
15232df4
FCE		 3965// start-sanitize-vr4320
3966*vr4320:
3967// end-sanitize-vr4320
90ad43b2
AC		 3968// start-sanitize-vr5400
3969*vr5400:
3970// end-sanitize-vr5400
f2b30012
AC		 3971*r3900:
3972// start-sanitize-tx19
3973*tx19:
3974// end-sanitize-tx19
3975{
23850e92
JL		 3976 if (GETFCC(CC) == TF)
3977 {
3978 DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3979 }
3980 else if (ND)
3981 {
3982 NULLIFY_NEXT_INSTRUCTION ();
f2b30012 3983 }
f2b30012
AC		 3984}
3985
3986
23850e92 3987
702968c5
FCE		 3988
3989
3990
23850e92
JL		 3991// C.EQ.S
3992// C.EQ.D
3993// ...
3994
3995:function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3996{
3997 if ((fmt != fmt_single) && (fmt != fmt_double))
3998 SignalException (ReservedInstruction, insn);
3999 else
4000 {
4001 int less;
4002 int equal;
4003 int unordered;
4004 int condition;
4005 unsigned64 ofs = ValueFPR (fs, fmt);
4006 unsigned64 oft = ValueFPR (ft, fmt);
4007 if (NaN (ofs, fmt) || NaN (oft, fmt))
4008 {
4009 if (FCSR & FP_ENABLE (IO))
4010 {
4011 FCSR |= FP_CAUSE (IO);
4012 SignalExceptionFPE ();
4013 }
4014 less = 0;
4015 equal = 0;
4016 unordered = 1;
4017 }
4018 else
4019 {
4020 less = Less (ofs, oft, fmt);
4021 equal = Equal (ofs, oft, fmt);
4022 unordered = 0;
4023 }
4024 condition = (((cond & (1 << 2)) && less)
4025 || ((cond & (1 << 1)) && equal)
4026 || ((cond & (1 << 0)) && unordered));
4027 SETFCC (cc, condition);
4028 }
4029}
4030
4031010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
4032*mipsI,mipsII,mipsIII:
4033"c.%s<COND>.%s<FMT> f<FS>, f<FT>":
4034{
4035 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4036}
4037
f2b30012
AC		 4038010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
4039"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4040"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
f2b30012 4041*mipsIV:
23850e92 4042*vr5000:
15232df4
FCE		 4043// start-sanitize-vr4320
4044*vr4320:
4045// end-sanitize-vr4320
90ad43b2
AC		 4046// start-sanitize-vr5400
4047*vr5400:
4048// end-sanitize-vr5400
f2b30012
AC		 4049*r3900:
4050// start-sanitize-tx19
4051*tx19:
4052// end-sanitize-tx19
4053{
23850e92 4054 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
f2b30012
AC		 4055}
4056
4057
4058010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4059"ceil.l.%s<FMT> f<FD>, f<FS>"
4060*mipsIII:
4061*mipsIV:
23850e92 4062*vr5000:
15232df4
FCE		 4063// start-sanitize-vr4320
4064*vr4320:
4065// end-sanitize-vr4320
90ad43b2
AC		 4066// start-sanitize-vr5400
4067*vr5400:
4068// end-sanitize-vr5400
f2b30012
AC		 4069// start-sanitize-r5900
4070*r5900:
4071// end-sanitize-r5900
4072*r3900:
4073// start-sanitize-tx19
4074*tx19:
4075// end-sanitize-tx19
4076{
4077 unsigned32 instruction = instruction_0;
055ee297
AC		 4078 int destreg = ((instruction >> 6) & 0x0000001F);
4079 int fs = ((instruction >> 11) & 0x0000001F);
4080 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4081 {
4082 if ((format != fmt_single) && (format != fmt_double))
4083 SignalException(ReservedInstruction,instruction);
4084 else
4085 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4086 }
4087}
4088
4089
4090010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4091*mipsII:
4092*mipsIII:
4093*mipsIV:
23850e92 4094*vr5000:
15232df4
FCE		 4095// start-sanitize-vr4320
4096*vr4320:
4097// end-sanitize-vr4320
90ad43b2
AC		 4098// start-sanitize-vr5400
4099*vr5400:
4100// end-sanitize-vr5400
f2b30012
AC		 4101// start-sanitize-r5900
4102*r5900:
4103// end-sanitize-r5900
4104*r3900:
4105// start-sanitize-tx19
4106*tx19:
4107// end-sanitize-tx19
4108{
4109 unsigned32 instruction = instruction_0;
055ee297
AC		 4110 int destreg = ((instruction >> 6) & 0x0000001F);
4111 int fs = ((instruction >> 11) & 0x0000001F);
4112 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4113 {
4114 if ((format != fmt_single) && (format != fmt_double))
4115 SignalException(ReservedInstruction,instruction);
4116 else
4117 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4118 }
4119}
4120
4121
4122// CFC1
4123// CTC1
030843d7
AC		 4124010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4125"c%s<X>c1 r<RT>, f<FS>"
f2b30012
AC		 4126*mipsI:
4127*mipsII:
4128*mipsIII:
030843d7
AC		 4129{
4130 if (X)
4131 {
4132 if (FS == 0)
4133 PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4134 else if (FS == 31)
4135 PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4136 /* else NOP */
4137 PENDING_FILL(COCIDX,0); /* special case */
4138 }
4139 else
4140 { /* control from */
4141 if (FS == 0)
4142 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4143 else if (FS == 31)
4144 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4145 /* else NOP */
4146 }
4147}
4148010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4149"c%s<X>c1 r<RT>, f<FS>"
f2b30012 4150*mipsIV:
23850e92 4151*vr5000:
15232df4
FCE		 4152// start-sanitize-vr4320
4153*vr4320:
4154// end-sanitize-vr4320
90ad43b2
AC		 4155// start-sanitize-vr5400
4156*vr5400:
4157// end-sanitize-vr5400
f2b30012
AC		 4158*r3900:
4159// start-sanitize-tx19
4160*tx19:
4161// end-sanitize-tx19
4162{
030843d7
AC		 4163 if (X)
4164 {
f89c0689
AC		 4165 /* control to */
4166 TRACE_ALU_INPUT1 (GPR[RT]);
030843d7 4167 if (FS == 0)
f89c0689
AC		 4168 {
4169 FCR0 = VL4_8(GPR[RT]);
4170 TRACE_ALU_RESULT (FCR0);
4171 }
030843d7 4172 else if (FS == 31)
f89c0689
AC		 4173 {
4174 FCR31 = VL4_8(GPR[RT]);
4175 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4176 TRACE_ALU_RESULT (FCR31);
4177 }
4178 else
4179 {
4180 TRACE_ALU_RESULT0 ();
4181 }
030843d7 4182 /* else NOP */
030843d7
AC		 4183 }
4184 else
4185 { /* control from */
4186 if (FS == 0)
f89c0689
AC		 4187 {
4188 TRACE_ALU_INPUT1 (FCR0);
4189 GPR[RT] = SIGNEXTEND (FCR0, 32);
4190 }
030843d7 4191 else if (FS == 31)
f89c0689
AC		 4192 {
4193 TRACE_ALU_INPUT1 (FCR31);
4194 GPR[RT] = SIGNEXTEND (FCR31, 32);
4195 }
4196 TRACE_ALU_RESULT (GPR[RT]);
030843d7 4197 /* else NOP */
f2b30012 4198 }
f2b30012
AC		 4199}
4200
4201
4202//
4203// FIXME: Does not correctly differentiate between mips*
4204//
4205010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4206"cvt.d.%s<FMT> f<FD>, f<FS>"
23850e92
JL		 4207*mipsI,mipsII,mipsIII,mipsIV:
4208*vr5000:
15232df4
FCE		 4209// start-sanitize-vr4320
4210*vr4320:
4211// end-sanitize-vr4320
90ad43b2
AC		 4212// start-sanitize-vr5400
4213*vr5400:
4214// end-sanitize-vr5400
f2b30012
AC		 4215*r3900:
4216// start-sanitize-tx19
4217*tx19:
4218// end-sanitize-tx19
4219{
4220 unsigned32 instruction = instruction_0;
055ee297
AC		 4221 int destreg = ((instruction >> 6) & 0x0000001F);
4222 int fs = ((instruction >> 11) & 0x0000001F);
4223 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4224 {
4225 if ((format == fmt_double) | 0)
4226 SignalException(ReservedInstruction,instruction);
4227 else
4228 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4229 }
4230}
4231
4232
4233010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4234"cvt.l.%s<FMT> f<FD>, f<FS>"
4235*mipsIII:
4236*mipsIV:
23850e92 4237*vr5000:
15232df4
FCE		 4238// start-sanitize-vr4320
4239*vr4320:
4240// end-sanitize-vr4320
90ad43b2
AC		 4241// start-sanitize-vr5400
4242*vr5400:
4243// end-sanitize-vr5400
f2b30012
AC		 4244*r3900:
4245// start-sanitize-tx19
4246*tx19:
4247// end-sanitize-tx19
4248{
4249 unsigned32 instruction = instruction_0;
055ee297
AC		 4250 int destreg = ((instruction >> 6) & 0x0000001F);
4251 int fs = ((instruction >> 11) & 0x0000001F);
4252 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4253 {
4254 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4255 SignalException(ReservedInstruction,instruction);
4256 else
4257 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4258 }
4259}
4260
4261
4262//
4263// FIXME: Does not correctly differentiate between mips*
4264//
4265010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4266"cvt.s.%s<FMT> f<FD>, f<FS>"
23850e92
JL		 4267*mipsI,mipsII,mipsIII,mipsIV:
4268*vr5000:
15232df4
FCE		 4269// start-sanitize-vr4320
4270*vr4320:
4271// end-sanitize-vr4320
90ad43b2
AC		 4272// start-sanitize-vr5400
4273*vr5400:
4274// end-sanitize-vr5400
f2b30012
AC		 4275*r3900:
4276// start-sanitize-tx19
4277*tx19:
4278// end-sanitize-tx19
4279{
4280 unsigned32 instruction = instruction_0;
055ee297
AC		 4281 int destreg = ((instruction >> 6) & 0x0000001F);
4282 int fs = ((instruction >> 11) & 0x0000001F);
4283 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4284 {
4285 if ((format == fmt_single) | 0)
4286 SignalException(ReservedInstruction,instruction);
4287 else
4288 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4289 }
4290}
4291
4292
4293010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4294"cvt.w.%s<FMT> f<FD>, f<FS>"
23850e92
JL		 4295*mipsI,mipsII,mipsIII,mipsIV:
4296*vr5000:
15232df4
FCE		 4297// start-sanitize-vr4320
4298*vr4320:
4299// end-sanitize-vr4320
90ad43b2
AC		 4300// start-sanitize-vr5400
4301*vr5400:
4302// end-sanitize-vr5400
f2b30012
AC		 4303*r3900:
4304// start-sanitize-tx19
4305*tx19:
4306// end-sanitize-tx19
4307{
4308 unsigned32 instruction = instruction_0;
055ee297
AC		 4309 int destreg = ((instruction >> 6) & 0x0000001F);
4310 int fs = ((instruction >> 11) & 0x0000001F);
4311 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4312 {
4313 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4314 SignalException(ReservedInstruction,instruction);
4315 else
4316 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4317 }
4318}
4319
4320
4321010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4322"div.%s<FMT> f<FD>, f<FS>, f<FT>"
23850e92
JL		 4323*mipsI,mipsII,mipsIII,mipsIV:
4324*vr5000:
15232df4
FCE		 4325// start-sanitize-vr4320
4326*vr4320:
4327// end-sanitize-vr4320
90ad43b2
AC		 4328// start-sanitize-vr5400
4329*vr5400:
4330// end-sanitize-vr5400
f2b30012
AC		 4331*r3900:
4332// start-sanitize-tx19
4333*tx19:
4334// end-sanitize-tx19
4335{
4336 unsigned32 instruction = instruction_0;
055ee297
AC		 4337 int destreg = ((instruction >> 6) & 0x0000001F);
4338 int fs = ((instruction >> 11) & 0x0000001F);
4339 int ft = ((instruction >> 16) & 0x0000001F);
4340 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4341 {
4342 if ((format != fmt_single) && (format != fmt_double))
4343 SignalException(ReservedInstruction,instruction);
4344 else
4345 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4346 }
4347}
4348
4349
4350// DMFC1
4351// DMTC1
030843d7
AC		 4352010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4353"dm%s<X>c1 r<RT>, f<FS>"
f2b30012 4354*mipsIII:
030843d7
AC		 4355{
4356 if (X)
4357 {
4358 if (SizeFGR() == 64)
4359 PENDING_FILL((FS + FGRIDX),GPR[RT]);
4360 else if ((FS & 0x1) == 0)
4361 {
4362 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4363 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4364 }
4365 }
4366 else
4367 {
4368 if (SizeFGR() == 64)
4369 PENDING_FILL(RT,FGR[FS]);
4370 else if ((FS & 0x1) == 0)
4371 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4372 else
4373 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4374 }
4375}
4376010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4377"dm%s<X>c1 r<RT>, f<FS>"
f2b30012 4378*mipsIV:
23850e92 4379*vr5000:
15232df4
FCE		 4380// start-sanitize-vr4320
4381*vr4320:
4382// end-sanitize-vr4320
90ad43b2
AC		 4383// start-sanitize-vr5400
4384*vr5400:
4385// end-sanitize-vr5400
f2b30012
AC		 4386// start-sanitize-r5900
4387*r5900:
4388// end-sanitize-r5900
4389*r3900:
4390// start-sanitize-tx19
4391*tx19:
4392// end-sanitize-tx19
4393{
030843d7
AC		 4394 if (X)
4395 {
4396 if (SizeFGR() == 64)
23850e92 4397 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
030843d7 4398 else if ((FS & 0x1) == 0)
23850e92 4399 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
f2b30012 4400 }
030843d7
AC		 4401 else
4402 {
4403 if (SizeFGR() == 64)
4404 GPR[RT] = FGR[FS];
4405 else if ((FS & 0x1) == 0)
4406 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4407 else
4408 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4409 }
f2b30012
AC		 4410}
4411
4412
4413010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4414"floor.l.%s<FMT> f<FD>, f<FS>"
4415*mipsIII:
4416*mipsIV:
23850e92 4417*vr5000:
15232df4
FCE		 4418// start-sanitize-vr4320
4419*vr4320:
4420// end-sanitize-vr4320
90ad43b2
AC		 4421// start-sanitize-vr5400
4422*vr5400:
4423// end-sanitize-vr5400
f2b30012
AC		 4424// start-sanitize-r5900
4425*r5900:
4426// end-sanitize-r5900
4427*r3900:
4428// start-sanitize-tx19
4429*tx19:
4430// end-sanitize-tx19
4431{
4432 unsigned32 instruction = instruction_0;
055ee297
AC		 4433 int destreg = ((instruction >> 6) & 0x0000001F);
4434 int fs = ((instruction >> 11) & 0x0000001F);
4435 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4436 {
4437 if ((format != fmt_single) && (format != fmt_double))
4438 SignalException(ReservedInstruction,instruction);
4439 else
4440 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4441 }
4442}
4443
4444
4445010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4446"floor.w.%s<FMT> f<FD>, f<FS>"
4447*mipsII:
4448*mipsIII:
4449*mipsIV:
23850e92 4450*vr5000:
15232df4
FCE		 4451// start-sanitize-vr4320
4452*vr4320:
4453// end-sanitize-vr4320
90ad43b2
AC		 4454// start-sanitize-vr5400
4455*vr5400:
4456// end-sanitize-vr5400
f2b30012
AC		 4457// start-sanitize-r5900
4458*r5900:
4459// end-sanitize-r5900
4460*r3900:
4461// start-sanitize-tx19
4462*tx19:
4463// end-sanitize-tx19
4464{
4465 unsigned32 instruction = instruction_0;
055ee297
AC		 4466 int destreg = ((instruction >> 6) & 0x0000001F);
4467 int fs = ((instruction >> 11) & 0x0000001F);
4468 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4469 {
4470 if ((format != fmt_single) && (format != fmt_double))
4471 SignalException(ReservedInstruction,instruction);
4472 else
4473 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4474 }
4475}
4476
4477
030843d7 4478110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
a94c5493 4479"ldc1 f<FT>, <OFFSET>(r<BASE>)"
030843d7
AC		 4480*mipsII:
4481*mipsIII:
4482*mipsIV:
23850e92 4483*vr5000:
15232df4
FCE		 4484// start-sanitize-vr4320
4485*vr4320:
4486// end-sanitize-vr4320
030843d7
AC		 4487// start-sanitize-vr5400
4488*vr5400:
4489// end-sanitize-vr5400
4490*r3900:
4491// start-sanitize-tx19
4492*tx19:
4493// end-sanitize-tx19
4494{
ebcfd86a 4495 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
030843d7 4496}
f2b30012
AC		 4497
4498
4499010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4500"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4501*mipsIV:
23850e92 4502*vr5000:
15232df4
FCE		 4503// start-sanitize-vr4320
4504*vr4320:
4505// end-sanitize-vr4320
90ad43b2
AC		 4506// start-sanitize-vr5400
4507*vr5400:
4508// end-sanitize-vr5400
f2b30012 4509{
ebcfd86a 4510 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
f2b30012
AC		 4511}
4512
4513
f2b30012 4514
030843d7 4515110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
23850e92
JL		 4516"lwc1 f<FT>, <OFFSET>(r<BASE>)"
4517*mipsI,mipsII,mipsIII,mipsIV:
4518*vr5000:
15232df4
FCE		 4519// start-sanitize-vr4320
4520*vr4320:
4521// end-sanitize-vr4320
90ad43b2
AC		 4522// start-sanitize-vr5400
4523*vr5400:
4524// end-sanitize-vr5400
f2b30012
AC		 4525// start-sanitize-r5900
4526*r5900:
4527// end-sanitize-r5900
030843d7
AC		 4528*r3900:
4529// start-sanitize-tx19
4530*tx19:
4531// end-sanitize-tx19
4532{
ebcfd86a 4533 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
030843d7
AC		 4534}
4535
4536
4537010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4538"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4539*mipsIV:
23850e92 4540*vr5000:
15232df4
FCE		 4541// start-sanitize-vr4320
4542*vr4320:
4543// end-sanitize-vr4320
030843d7
AC		 4544// start-sanitize-vr5400
4545*vr5400:
4546// end-sanitize-vr5400
f2b30012 4547{
ebcfd86a 4548 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
f2b30012
AC		 4549}
4550
4551
4552
4553//
4554// FIXME: Not correct for mips*
4555//
a48e8c8d 4556010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
f2b30012
AC		 4557"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4558*mipsIV:
23850e92 4559*vr5000:
15232df4
FCE		 4560// start-sanitize-vr4320
4561*vr4320:
4562// end-sanitize-vr4320
90ad43b2
AC		 4563// start-sanitize-vr5400
4564*vr5400:
4565// end-sanitize-vr5400
f2b30012
AC		 4566{
4567 unsigned32 instruction = instruction_0;
055ee297
AC		 4568 int destreg = ((instruction >> 6) & 0x0000001F);
4569 int fs = ((instruction >> 11) & 0x0000001F);
4570 int ft = ((instruction >> 16) & 0x0000001F);
4571 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4572 {
4573 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4574 }
4575}
4576
4577
a48e8c8d 4578010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
f2b30012
AC		 4579"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4580*mipsIV:
23850e92 4581*vr5000:
15232df4
FCE		 4582// start-sanitize-vr4320
4583*vr4320:
4584// end-sanitize-vr4320
90ad43b2
AC		 4585// start-sanitize-vr5400
4586*vr5400:
4587// end-sanitize-vr5400
f2b30012
AC		 4588{
4589 unsigned32 instruction = instruction_0;
055ee297
AC		 4590 int destreg = ((instruction >> 6) & 0x0000001F);
4591 int fs = ((instruction >> 11) & 0x0000001F);
4592 int ft = ((instruction >> 16) & 0x0000001F);
4593 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4594 {
4595 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4596 }
4597}
4598
4599
4600// MFC1
030843d7 4601// MTC1
f2b30012 4602010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
030843d7 4603"m%s<X>c1 r<RT>, f<FS>"
f2b30012
AC		 4604*mipsI:
4605*mipsII:
4606*mipsIII:
030843d7
AC		 4607{
4608 if (X)
4609 { /*MTC1*/
4610 if (SizeFGR() == 64)
4611 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4612 else
4613 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4614 }
4615 else /*MFC1*/
4616 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4617}
4618010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4619"m%s<X>c1 r<RT>, f<FS>"
f2b30012 4620*mipsIV:
23850e92 4621*vr5000:
15232df4
FCE		 4622// start-sanitize-vr4320
4623*vr4320:
4624// end-sanitize-vr4320
90ad43b2
AC		 4625// start-sanitize-vr5400
4626*vr5400:
4627// end-sanitize-vr5400
f2b30012
AC		 4628*r3900:
4629// start-sanitize-tx19
4630*tx19:
4631// end-sanitize-tx19
4632{
030843d7 4633 if (X)
23850e92
JL		 4634 /*MTC1*/
4635 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
030843d7
AC		 4636 else /*MFC1*/
4637 GPR[RT] = SIGNEXTEND(FGR[FS],32);
f2b30012
AC		 4638}
4639
4640
4641010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4642"mov.%s<FMT> f<FD>, f<FS>"
23850e92
JL		 4643*mipsI,mipsII,mipsIII,mipsIV:
4644*vr5000:
15232df4
FCE		 4645// start-sanitize-vr4320
4646*vr4320:
4647// end-sanitize-vr4320
90ad43b2
AC		 4648// start-sanitize-vr5400
4649*vr5400:
4650// end-sanitize-vr5400
f2b30012
AC		 4651*r3900:
4652// start-sanitize-tx19
4653*tx19:
4654// end-sanitize-tx19
4655{
4656 unsigned32 instruction = instruction_0;
055ee297
AC		 4657 int destreg = ((instruction >> 6) & 0x0000001F);
4658 int fs = ((instruction >> 11) & 0x0000001F);
4659 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4660 {
4661 StoreFPR(destreg,format,ValueFPR(fs,format));
4662 }
4663}
4664
4665
4666// MOVF
4667000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
055ee297 4668"mov%s<TF> r<RD>, r<RS>, <CC>"
f2b30012 4669*mipsIV:
23850e92 4670*vr5000:
15232df4
FCE		 4671// start-sanitize-vr4320
4672*vr4320:
4673// end-sanitize-vr4320
90ad43b2
AC		 4674// start-sanitize-vr5400
4675*vr5400:
4676// end-sanitize-vr5400
f2b30012
AC		 4677// start-sanitize-r5900
4678*r5900:
4679// end-sanitize-r5900
4680{
055ee297
AC		 4681 if (GETFCC(CC) == TF)
4682 GPR[RD] = GPR[RS];
f2b30012
AC		 4683}
4684
4685
4686// MOVF.fmt
4687010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
055ee297 4688"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
f2b30012 4689*mipsIV:
23850e92 4690*vr5000:
15232df4
FCE		 4691// start-sanitize-vr4320
4692*vr4320:
4693// end-sanitize-vr4320
90ad43b2
AC		 4694// start-sanitize-vr5400
4695*vr5400:
4696// end-sanitize-vr5400
f2b30012
AC		 4697// start-sanitize-r5900
4698*r5900:
4699// end-sanitize-r5900
4700{
4701 unsigned32 instruction = instruction_0;
055ee297 4702 int format = ((instruction >> 21) & 0x00000007);
f2b30012 4703 {
055ee297
AC		 4704 if (GETFCC(CC) == TF)
4705 StoreFPR (FD, format, ValueFPR (FS, format));
f2b30012 4706 else
055ee297 4707 StoreFPR (FD, format, ValueFPR (FD, format));
f2b30012
AC		 4708 }
4709}
4710
4711
4712010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4713*mipsIV:
23850e92 4714*vr5000:
15232df4
FCE		 4715// start-sanitize-vr4320
4716*vr4320:
4717// end-sanitize-vr4320
90ad43b2
AC		 4718// start-sanitize-vr5400
4719*vr5400:
4720// end-sanitize-vr5400
f2b30012
AC		 4721// start-sanitize-r5900
4722*r5900:
4723// end-sanitize-r5900
4724{
4725 unsigned32 instruction = instruction_0;
055ee297
AC		 4726 int destreg = ((instruction >> 6) & 0x0000001F);
4727 int fs = ((instruction >> 11) & 0x0000001F);
4728 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4729 {
4730 StoreFPR(destreg,format,ValueFPR(fs,format));
4731 }
4732}
4733
4734
4735// MOVT see MOVtf
4736
4737
4738// MOVT.fmt see MOVtf.fmt
4739
4740
4741
4742010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4743"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4744*mipsIV:
23850e92 4745*vr5000:
15232df4
FCE		 4746// start-sanitize-vr4320
4747*vr4320:
4748// end-sanitize-vr4320
90ad43b2
AC		 4749// start-sanitize-vr5400
4750*vr5400:
4751// end-sanitize-vr5400
f2b30012
AC		 4752// start-sanitize-r5900
4753*r5900:
4754// end-sanitize-r5900
4755{
4756 unsigned32 instruction = instruction_0;
055ee297
AC		 4757 int destreg = ((instruction >> 6) & 0x0000001F);
4758 int fs = ((instruction >> 11) & 0x0000001F);
4759 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4760 {
4761 StoreFPR(destreg,format,ValueFPR(fs,format));
4762 }
4763}
4764
4765
4766// MSUB.fmt
4767010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4768"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4769*mipsIV:
23850e92 4770*vr5000:
15232df4
FCE		 4771// start-sanitize-vr4320
4772*vr4320:
4773// end-sanitize-vr4320
90ad43b2
AC		 4774// start-sanitize-vr5400
4775*vr5400:
4776// end-sanitize-vr5400
f2b30012
AC		 4777// start-sanitize-r5900
4778*r5900:
4779// end-sanitize-r5900
4780{
4781 unsigned32 instruction = instruction_0;
055ee297
AC		 4782 int destreg = ((instruction >> 6) & 0x0000001F);
4783 int fs = ((instruction >> 11) & 0x0000001F);
4784 int ft = ((instruction >> 16) & 0x0000001F);
4785 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012 4786 {
23850e92 4787 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
f2b30012
AC		 4788 }
4789}
4790
4791
4792// MSUB.fmt
055ee297 4793010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
f2b30012
AC		 4794"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4795*mipsIV:
23850e92 4796*vr5000:
15232df4
FCE		 4797// start-sanitize-vr4320
4798*vr4320:
4799// end-sanitize-vr4320
90ad43b2
AC		 4800// start-sanitize-vr5400
4801*vr5400:
4802// end-sanitize-vr5400
f2b30012
AC		 4803// start-sanitize-r5900
4804*r5900:
4805// end-sanitize-r5900
4806{
4807 unsigned32 instruction = instruction_0;
055ee297
AC		 4808 int destreg = ((instruction >> 6) & 0x0000001F);
4809 int fs = ((instruction >> 11) & 0x0000001F);
4810 int ft = ((instruction >> 16) & 0x0000001F);
4811 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012 4812 {
23850e92 4813 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
f2b30012
AC		 4814 }
4815}
4816
4817
4818// MTC1 see MxC1
4819
4820
4821010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4822"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
23850e92
JL		 4823*mipsI,mipsII,mipsIII,mipsIV:
4824*vr5000:
15232df4
FCE		 4825// start-sanitize-vr4320
4826*vr4320:
4827// end-sanitize-vr4320
90ad43b2
AC		 4828// start-sanitize-vr5400
4829*vr5400:
4830// end-sanitize-vr5400
f2b30012
AC		 4831*r3900:
4832// start-sanitize-tx19
4833*tx19:
4834// end-sanitize-tx19
4835{
4836 unsigned32 instruction = instruction_0;
055ee297
AC		 4837 int destreg = ((instruction >> 6) & 0x0000001F);
4838 int fs = ((instruction >> 11) & 0x0000001F);
4839 int ft = ((instruction >> 16) & 0x0000001F);
4840 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4841 {
4842 if ((format != fmt_single) && (format != fmt_double))
4843 SignalException(ReservedInstruction,instruction);
4844 else
4845 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4846 }
4847}
4848
4849
4850010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4851"neg.%s<FMT> f<FD>, f<FS>"
23850e92
JL		 4852*mipsI,mipsII,mipsIII,mipsIV:
4853*vr5000:
15232df4
FCE		 4854// start-sanitize-vr4320
4855*vr4320:
4856// end-sanitize-vr4320
90ad43b2
AC		 4857// start-sanitize-vr5400
4858*vr5400:
4859// end-sanitize-vr5400
f2b30012
AC		 4860*r3900:
4861// start-sanitize-tx19
4862*tx19:
4863// end-sanitize-tx19
4864{
4865 unsigned32 instruction = instruction_0;
055ee297
AC		 4866 int destreg = ((instruction >> 6) & 0x0000001F);
4867 int fs = ((instruction >> 11) & 0x0000001F);
4868 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4869 {
4870 if ((format != fmt_single) && (format != fmt_double))
4871 SignalException(ReservedInstruction,instruction);
4872 else
4873 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4874 }
4875}
4876
4877
4878// NMADD.fmt
4879010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4880"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4881*mipsIV:
23850e92 4882*vr5000:
15232df4
FCE		 4883// start-sanitize-vr4320
4884*vr4320:
4885// end-sanitize-vr4320
90ad43b2
AC		 4886// start-sanitize-vr5400
4887*vr5400:
4888// end-sanitize-vr5400
f2b30012
AC		 4889{
4890 unsigned32 instruction = instruction_0;
055ee297
AC		 4891 int destreg = ((instruction >> 6) & 0x0000001F);
4892 int fs = ((instruction >> 11) & 0x0000001F);
4893 int ft = ((instruction >> 16) & 0x0000001F);
4894 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4895 {
4896 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4897 }
4898}
4899
4900
4901// NMADD.fmt
4902010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4903"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4904*mipsIV:
23850e92 4905*vr5000:
15232df4
FCE		 4906// start-sanitize-vr4320
4907*vr4320:
4908// end-sanitize-vr4320
90ad43b2
AC		 4909// start-sanitize-vr5400
4910*vr5400:
4911// end-sanitize-vr5400
f2b30012
AC		 4912{
4913 unsigned32 instruction = instruction_0;
055ee297
AC		 4914 int destreg = ((instruction >> 6) & 0x0000001F);
4915 int fs = ((instruction >> 11) & 0x0000001F);
4916 int ft = ((instruction >> 16) & 0x0000001F);
4917 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4918 {
4919 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4920 }
4921}
4922
4923
4924// NMSUB.fmt
055ee297 4925010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
f2b30012
AC		 4926"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4927*mipsIV:
23850e92 4928*vr5000:
15232df4
FCE		 4929// start-sanitize-vr4320
4930*vr4320:
4931// end-sanitize-vr4320
90ad43b2
AC		 4932// start-sanitize-vr5400
4933*vr5400:
4934// end-sanitize-vr5400
f2b30012
AC		 4935{
4936 unsigned32 instruction = instruction_0;
055ee297
AC		 4937 int destreg = ((instruction >> 6) & 0x0000001F);
4938 int fs = ((instruction >> 11) & 0x0000001F);
4939 int ft = ((instruction >> 16) & 0x0000001F);
4940 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4941 {
4942 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4943 }
4944}
4945
4946
4947// NMSUB.fmt
055ee297 4948010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
f2b30012
AC		 4949"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4950*mipsIV:
23850e92 4951*vr5000:
15232df4
FCE		 4952// start-sanitize-vr4320
4953*vr4320:
4954// end-sanitize-vr4320
90ad43b2
AC		 4955// start-sanitize-vr5400
4956*vr5400:
4957// end-sanitize-vr5400
f2b30012
AC		 4958{
4959 unsigned32 instruction = instruction_0;
055ee297
AC		 4960 int destreg = ((instruction >> 6) & 0x0000001F);
4961 int fs = ((instruction >> 11) & 0x0000001F);
4962 int ft = ((instruction >> 16) & 0x0000001F);
4963 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4964 {
4965 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4966 }
4967}
4968
4969
4970010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
49a6eed5 4971"prefx <HINT>, r<INDEX>(r<BASE>)"
f2b30012 4972*mipsIV:
23850e92 4973*vr5000:
15232df4
FCE		 4974// start-sanitize-vr4320
4975*vr4320:
4976// end-sanitize-vr4320
90ad43b2
AC		 4977// start-sanitize-vr5400
4978*vr5400:
4979// end-sanitize-vr5400
f2b30012
AC		 4980{
4981 unsigned32 instruction = instruction_0;
055ee297
AC		 4982 int fs = ((instruction >> 11) & 0x0000001F);
4983 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4984 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 4985 {
49a76833
AC		 4986 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4987 address_word paddr;
f2b30012
AC		 4988 int uncached;
4989 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4990 Prefetch(uncached,paddr,vaddr,isDATA,fs);
4991 }
4992}
4993
4994010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4995*mipsIV:
4996"recip.%s<FMT> f<FD>, f<FS>"
23850e92 4997*vr5000:
15232df4
FCE		 4998// start-sanitize-vr4320
4999*vr4320:
5000// end-sanitize-vr4320
90ad43b2
AC		 5001// start-sanitize-vr5400
5002*vr5400:
5003// end-sanitize-vr5400
f2b30012
AC		 5004{
5005 unsigned32 instruction = instruction_0;
055ee297
AC		 5006 int destreg = ((instruction >> 6) & 0x0000001F);
5007 int fs = ((instruction >> 11) & 0x0000001F);
5008 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5009 {
5010 if ((format != fmt_single) && (format != fmt_double))
5011 SignalException(ReservedInstruction,instruction);
5012 else
5013 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5014 }
5015}
5016
5017
5018010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
49a6eed5 5019"round.l.%s<FMT> f<FD>, f<FS>"
f2b30012
AC		 5020*mipsIII:
5021*mipsIV:
23850e92 5022*vr5000:
15232df4
FCE		 5023// start-sanitize-vr4320
5024*vr4320:
5025// end-sanitize-vr4320
90ad43b2
AC		 5026// start-sanitize-vr5400
5027*vr5400:
5028// end-sanitize-vr5400
f2b30012
AC		 5029// start-sanitize-r5900
5030*r5900:
5031// end-sanitize-r5900
5032*r3900:
5033// start-sanitize-tx19
5034*tx19:
5035// end-sanitize-tx19
5036{
5037 unsigned32 instruction = instruction_0;
055ee297
AC		 5038 int destreg = ((instruction >> 6) & 0x0000001F);
5039 int fs = ((instruction >> 11) & 0x0000001F);
5040 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5041 {
5042 if ((format != fmt_single) && (format != fmt_double))
5043 SignalException(ReservedInstruction,instruction);
5044 else
5045 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5046 }
5047}
5048
5049
5050010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
49a6eed5 5051"round.w.%s<FMT> f<FD>, f<FS>"
f2b30012
AC		 5052*mipsII:
5053*mipsIII:
5054*mipsIV:
23850e92 5055*vr5000:
15232df4
FCE		 5056// start-sanitize-vr4320
5057*vr4320:
5058// end-sanitize-vr4320
90ad43b2
AC		 5059// start-sanitize-vr5400
5060*vr5400:
5061// end-sanitize-vr5400
f2b30012
AC		 5062// start-sanitize-r5900
5063*r5900:
5064// end-sanitize-r5900
5065*r3900:
5066// start-sanitize-tx19
5067*tx19:
5068// end-sanitize-tx19
5069{
5070 unsigned32 instruction = instruction_0;
055ee297
AC		 5071 int destreg = ((instruction >> 6) & 0x0000001F);
5072 int fs = ((instruction >> 11) & 0x0000001F);
5073 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5074 {
5075 if ((format != fmt_single) && (format != fmt_double))
5076 SignalException(ReservedInstruction,instruction);
5077 else
5078 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5079 }
5080}
5081
5082
5083010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5084*mipsIV:
5085"rsqrt.%s<FMT> f<FD>, f<FS>"
23850e92 5086*vr5000:
15232df4
FCE		 5087// start-sanitize-vr4320
5088*vr4320:
5089// end-sanitize-vr4320
90ad43b2
AC		 5090// start-sanitize-vr5400
5091*vr5400:
5092// end-sanitize-vr5400
f2b30012
AC		 5093{
5094 unsigned32 instruction = instruction_0;
055ee297
AC		 5095 int destreg = ((instruction >> 6) & 0x0000001F);
5096 int fs = ((instruction >> 11) & 0x0000001F);
5097 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5098 {
5099 if ((format != fmt_single) && (format != fmt_double))
5100 SignalException(ReservedInstruction,instruction);
5101 else
085c1cb9 5102 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
f2b30012
AC		 5103 }
5104}
5105
5106
030843d7
AC		 5107111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5108"sdc1 f<FT>, <OFFSET>(r<BASE>)"
5109*mipsII:
5110*mipsIII:
5111*mipsIV:
23850e92 5112*vr5000:
15232df4
FCE		 5113// start-sanitize-vr4320
5114*vr4320:
5115// end-sanitize-vr4320
030843d7
AC		 5116// start-sanitize-vr5400
5117*vr5400:
5118// end-sanitize-vr5400
5119*r3900:
5120// start-sanitize-tx19
5121*tx19:
5122// end-sanitize-tx19
5123{
ebcfd86a 5124 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
030843d7 5125}
f2b30012
AC		 5126
5127
ebcfd86a
FCE		 5128010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
5129"ldxc1 f<FS>, r<INDEX>(r<BASE>)"
f2b30012 5130*mipsIV:
23850e92 5131*vr5000:
15232df4
FCE		 5132// start-sanitize-vr4320
5133*vr4320:
5134// end-sanitize-vr4320
90ad43b2
AC		 5135// start-sanitize-vr5400
5136*vr5400:
5137// end-sanitize-vr5400
f2b30012 5138{
ebcfd86a 5139 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
f2b30012
AC		 5140}
5141
5142
5143010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5144"sqrt.%s<FMT> f<FD>, f<FS>"
5145*mipsII:
5146*mipsIII:
5147*mipsIV:
23850e92 5148*vr5000:
15232df4
FCE		 5149// start-sanitize-vr4320
5150*vr4320:
5151// end-sanitize-vr4320
90ad43b2
AC		 5152// start-sanitize-vr5400
5153*vr5400:
5154// end-sanitize-vr5400
f2b30012
AC		 5155*r3900:
5156// start-sanitize-tx19
5157*tx19:
5158// end-sanitize-tx19
5159{
5160 unsigned32 instruction = instruction_0;
055ee297
AC		 5161 int destreg = ((instruction >> 6) & 0x0000001F);
5162 int fs = ((instruction >> 11) & 0x0000001F);
5163 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5164 {
5165 if ((format != fmt_single) && (format != fmt_double))
5166 SignalException(ReservedInstruction,instruction);
5167 else
5168 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5169 }
5170}
5171
5172
5173010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5174"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
23850e92
JL		 5175*mipsI,mipsII,mipsIII,mipsIV:
5176*vr5000:
15232df4
FCE		 5177// start-sanitize-vr4320
5178*vr4320:
5179// end-sanitize-vr4320
90ad43b2
AC		 5180// start-sanitize-vr5400
5181*vr5400:
5182// end-sanitize-vr5400
f2b30012
AC		 5183*r3900:
5184// start-sanitize-tx19
5185*tx19:
5186// end-sanitize-tx19
5187{
5188 unsigned32 instruction = instruction_0;
055ee297
AC		 5189 int destreg = ((instruction >> 6) & 0x0000001F);
5190 int fs = ((instruction >> 11) & 0x0000001F);
5191 int ft = ((instruction >> 16) & 0x0000001F);
5192 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5193 {
5194 if ((format != fmt_single) && (format != fmt_double))
5195 SignalException(ReservedInstruction,instruction);
5196 else
5197 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5198 }
5199}
5200
5201
f2b30012 5202
030843d7
AC		 5203111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5204"swc1 f<FT>, <OFFSET>(r<BASE>)"
23850e92
JL		 5205*mipsI,mipsII,mipsIII,mipsIV:
5206*vr5000:
15232df4
FCE		 5207// start-sanitize-vr4320
5208*vr4320:
5209// end-sanitize-vr4320
90ad43b2
AC		 5210// start-sanitize-vr5400
5211*vr5400:
5212// end-sanitize-vr5400
f2b30012
AC		 5213// start-sanitize-r5900
5214*r5900:
5215// end-sanitize-r5900
030843d7
AC		 5216*r3900:
5217// start-sanitize-tx19
5218*tx19:
5219// end-sanitize-tx19
5220{
5221 unsigned32 instruction = instruction_0;
5222 signed_word offset = EXTEND16 (OFFSET);
5223 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5224 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5225 {
5226 address_word vaddr = ((uword64)op1 + offset);
5227 address_word paddr;
5228 int uncached;
5229 if ((vaddr & 3) != 0)
5230 SignalExceptionAddressStore();
5231 else
5232 {
5233 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5234 {
5235 uword64 memval = 0;
5236 uword64 memval1 = 0;
2b5d87df
GRK		 5237 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5238 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5239 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
030843d7 5240 unsigned int byte;
2b5d87df
GRK		 5241 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5242 byte = ((vaddr & mask) ^ bigendiancpu);
030843d7 5243 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
2b5d87df 5244 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
030843d7
AC		 5245 }
5246 }
5247 }
5248}
5249
5250
5251010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5252"swxc1 f<FS>, r<INDEX>(r<BASE>)"
5253*mipsIV:
23850e92 5254*vr5000:
15232df4
FCE		 5255// start-sanitize-vr4320
5256*vr4320:
5257// end-sanitize-vr4320
030843d7
AC		 5258// start-sanitize-vr5400
5259*vr5400:
5260// end-sanitize-vr5400
f2b30012
AC		 5261{
5262 unsigned32 instruction = instruction_0;
055ee297
AC		 5263 int fs = ((instruction >> 11) & 0x0000001F);
5264 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5265 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 5266 {
49a76833
AC		 5267 address_word vaddr = ((unsigned64)op1 + op2);
5268 address_word paddr;
f2b30012
AC		 5269 int uncached;
5270 if ((vaddr & 3) != 0)
055ee297 5271 SignalExceptionAddressStore();
f2b30012
AC		 5272 else
5273 {
5274 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5275 {
5276 unsigned64 memval = 0;
5277 unsigned64 memval1 = 0;
5278 unsigned64 mask = 0x7;
5279 unsigned int byte;
5280 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5281 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5282 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5283 {
5284 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5285 }
5286 }
5287 }
5288 }
5289}
5290
5291
5292010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5293"trunc.l.%s<FMT> f<FD>, f<FS>"
5294*mipsIII:
5295*mipsIV:
23850e92 5296*vr5000:
15232df4
FCE		 5297// start-sanitize-vr4320
5298*vr4320:
5299// end-sanitize-vr4320
90ad43b2
AC		 5300// start-sanitize-vr5400
5301*vr5400:
5302// end-sanitize-vr5400
f2b30012
AC		 5303// start-sanitize-r5900
5304*r5900:
5305// end-sanitize-r5900
5306*r3900:
5307// start-sanitize-tx19
5308*tx19:
5309// end-sanitize-tx19
5310{
5311 unsigned32 instruction = instruction_0;
055ee297
AC		 5312 int destreg = ((instruction >> 6) & 0x0000001F);
5313 int fs = ((instruction >> 11) & 0x0000001F);
5314 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5315 {
5316 if ((format != fmt_single) && (format != fmt_double))
5317 SignalException(ReservedInstruction,instruction);
5318 else
5319 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5320 }
5321}
5322
5323
5324010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5325"trunc.w.%s<FMT> f<FD>, f<FS>"
5326*mipsII:
5327*mipsIII:
5328*mipsIV:
23850e92 5329*vr5000:
15232df4
FCE		 5330// start-sanitize-vr4320
5331*vr4320:
5332// end-sanitize-vr4320
90ad43b2
AC		 5333// start-sanitize-vr5400
5334*vr5400:
5335// end-sanitize-vr5400
f2b30012
AC		 5336// start-sanitize-r5900
5337*r5900:
5338// end-sanitize-r5900
5339*r3900:
5340// start-sanitize-tx19
5341*tx19:
5342// end-sanitize-tx19
5343{
5344 unsigned32 instruction = instruction_0;
055ee297
AC		 5345 int destreg = ((instruction >> 6) & 0x0000001F);
5346 int fs = ((instruction >> 11) & 0x0000001F);
5347 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5348 {
5349 if ((format != fmt_single) && (format != fmt_double))
5350 SignalException(ReservedInstruction,instruction);
5351 else
5352 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5353 }
5354}
5355
5356\f
5357//
5358// MIPS Architecture:
5359//
5360// System Control Instruction Set (COP0)
5361//
5362
5363
5364010000,01000,00000,16.OFFSET:COP0:32::BC0F
5365"bc0f <OFFSET>"
23850e92
JL		 5366*mipsI,mipsII,mipsIII,mipsIV:
5367*vr5000:
15232df4
FCE		 5368// start-sanitize-vr4320
5369*vr4320:
5370// end-sanitize-vr4320
90ad43b2
AC		 5371// start-sanitize-vr5400
5372*vr5400:
5373// end-sanitize-vr5400
f2b30012
AC		 5374
5375
5376010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5377"bc0fl <OFFSET>"
23850e92
JL		 5378*mipsI,mipsII,mipsIII,mipsIV:
5379*vr5000:
15232df4
FCE		 5380// start-sanitize-vr4320
5381*vr4320:
5382// end-sanitize-vr4320
90ad43b2
AC		 5383// start-sanitize-vr5400
5384*vr5400:
5385// end-sanitize-vr5400
f2b30012
AC		 5386
5387
5388010000,01000,00001,16.OFFSET:COP0:32::BC0T
5389"bc0t <OFFSET>"
23850e92 5390*mipsI,mipsII,mipsIII,mipsIV:
f2b30012
AC		 5391
5392
5393
49a6eed5 5394010000,01000,00011,16.OFFSET:COP0:32::BC0TL
f2b30012 5395"bc0tl <OFFSET>"
23850e92
JL		 5396*mipsI,mipsII,mipsIII,mipsIV:
5397*vr5000:
15232df4
FCE		 5398// start-sanitize-vr4320
5399*vr4320:
5400// end-sanitize-vr4320
90ad43b2
AC		 5401// start-sanitize-vr5400
5402*vr5400:
5403// end-sanitize-vr5400
f2b30012
AC		 5404
5405
5406101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5407*mipsIII:
5408*mipsIV:
23850e92 5409*vr5000:
15232df4
FCE		 5410// start-sanitize-vr4320
5411*vr4320:
5412// end-sanitize-vr4320
90ad43b2
AC		 5413// start-sanitize-vr5400
5414*vr5400:
5415// end-sanitize-vr5400
f2b30012
AC		 5416*r3900:
5417// start-sanitize-tx19
5418*tx19:
5419// end-sanitize-tx19
5420{
5421 unsigned32 instruction = instruction_0;
055ee297
AC		 5422 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5423 int hint = ((instruction >> 16) & 0x0000001F);
5424 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 5425 {
49a76833
AC		 5426 address_word vaddr = (op1 + offset);
5427 address_word paddr;
f2b30012
AC		 5428 int uncached;
5429 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5430 CacheOp(hint,vaddr,paddr,instruction);
5431 }
5432}
5433
5434
5435010000,10000,000000000000000,111001:COP0:32::DI
5436"di"
23850e92
JL		 5437*mipsI,mipsII,mipsIII,mipsIV:
5438*vr5000:
15232df4
FCE		 5439// start-sanitize-vr4320
5440*vr4320:
5441// end-sanitize-vr4320
90ad43b2
AC		 5442// start-sanitize-vr5400
5443*vr5400:
5444// end-sanitize-vr5400
f2b30012
AC		 5445
5446
5447010000,10000,000000000000000,111000:COP0:32::EI
5448"ei"
23850e92
JL		 5449*mipsI,mipsII,mipsIII,mipsIV:
5450*vr5000:
15232df4
FCE		 5451// start-sanitize-vr4320
5452*vr4320:
5453// end-sanitize-vr4320
90ad43b2
AC		 5454// start-sanitize-vr5400
5455*vr5400:
5456// end-sanitize-vr5400
f2b30012
AC		 5457
5458
5459010000,10000,000000000000000,011000:COP0:32::ERET
5460"eret"
5461*mipsIII:
5462*mipsIV:
23850e92 5463*vr5000:
15232df4
FCE		 5464// start-sanitize-vr4320
5465*vr4320:
5466// end-sanitize-vr4320
90ad43b2
AC		 5467// start-sanitize-vr5400
5468*vr5400:
5469// end-sanitize-vr5400
f2b30012
AC		 5470// start-sanitize-r5900
5471*r5900:
5472// end-sanitize-r5900
97f4d183
AC		 5473{
5474 if (SR & status_ERL)
5475 {
5476 /* Oops, not yet available */
5477 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5478 NIA = EPC;
5479 SR &= ~status_ERL;
5480 }
5481 else
5482 {
5483 NIA = EPC;
5484 SR &= ~status_EXL;
5485 }
5486}
f2b30012
AC		 5487
5488
49a6eed5
AC		 5489010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5490"mfc0 r<RT>, r<RD> # <REGX>"
23850e92 5491*mipsI,mipsII,mipsIII,mipsIV:
3fa454e9 5492*r3900:
23850e92 5493*vr5000:
15232df4
FCE		 5494// start-sanitize-vr4320
5495*vr4320:
5496// end-sanitize-vr4320
90ad43b2
AC		 5497// start-sanitize-vr5400
5498*vr5400:
5499// end-sanitize-vr5400
f2b30012
AC		 5500// start-sanitize-r5900
5501*r5900:
5502// end-sanitize-r5900
030843d7 5503{
97f4d183 5504 TRACE_ALU_INPUT0 ();
030843d7 5505 DecodeCoproc (instruction_0);
97f4d183 5506 TRACE_ALU_RESULT (GPR[RT]);
030843d7 5507}
f2b30012 5508
49a6eed5
AC		 5509010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5510"mtc0 r<RT>, r<RD> # <REGX>"
23850e92 5511*mipsI,mipsII,mipsIII,mipsIV:
f3bdd368
AC		 5512// start-sanitize-tx19
5513*tx19:
5514// end-sanitize-tx19
ebcfd86a 5515*r3900:
15232df4
FCE		 5516// start-sanitize-vr4320
5517*vr4320:
5518// end-sanitize-vr4320
ebcfd86a 5519*vr5000:
90ad43b2
AC		 5520// start-sanitize-vr5400
5521*vr5400:
5522// end-sanitize-vr5400
f2b30012 5523// start-sanitize-r5900
3fa454e9
FCE		 5524*r5900:
5525// end-sanitize-r5900
5526{
5527 DecodeCoproc (instruction_0);
5528}
5529
5530
5531010000,10000,000000000000000,010000:COP0:32::RFE
5532"rfe"
5533*mipsI,mipsII,mipsIII,mipsIV:
5534// start-sanitize-tx19
5535*tx19:
5536// end-sanitize-tx19
5537*r3900:
5538// start-sanitize-vr4320
5539*vr4320:
5540// end-sanitize-vr4320
5541*vr5000:
5542// start-sanitize-vr5400
5543*vr5400:
5544// end-sanitize-vr5400
5545// start-sanitize-r5900
f2b30012
AC		 5546*r5900:
5547// end-sanitize-r5900
030843d7
AC		 5548{
5549 DecodeCoproc (instruction_0);
5550}
f2b30012
AC		 5551
5552
702968c5
FCE		 55530100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5554"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5555*mipsI,mipsII,mipsIII,mipsIV:
5556// start-sanitize-r5900
5557*r5900:
5558// end-sanitize-r5900
5559*r3900:
5560// start-sanitize-tx19
5561*tx19:
5562// end-sanitize-tx19
5563{
5564 DecodeCoproc (instruction_0);
5565}
5566
5567
5568
f2b30012
AC		 5569010000,10000,000000000000000,001000:COP0:32::TLBP
5570"tlbp"
23850e92
JL		 5571*mipsI,mipsII,mipsIII,mipsIV:
5572*vr5000:
15232df4
FCE		 5573// start-sanitize-vr4320
5574*vr4320:
5575// end-sanitize-vr4320
90ad43b2
AC		 5576// start-sanitize-vr5400
5577*vr5400:
5578// end-sanitize-vr5400
f2b30012
AC		 5579
5580
5581010000,10000,000000000000000,000001:COP0:32::TLBR
5582"tlbr"
23850e92
JL		 5583*mipsI,mipsII,mipsIII,mipsIV:
5584*vr5000:
15232df4
FCE		 5585// start-sanitize-vr4320
5586*vr4320:
5587// end-sanitize-vr4320
90ad43b2
AC		 5588// start-sanitize-vr5400
5589*vr5400:
5590// end-sanitize-vr5400
f2b30012
AC		 5591
5592
5593010000,10000,000000000000000,000010:COP0:32::TLBWI
5594"tlbwi"
23850e92
JL		 5595*mipsI,mipsII,mipsIII,mipsIV:
5596*vr5000:
15232df4
FCE		 5597// start-sanitize-vr4320
5598*vr4320:
5599// end-sanitize-vr4320
90ad43b2
AC		 5600// start-sanitize-vr5400
5601*vr5400:
5602// end-sanitize-vr5400
f2b30012
AC		 5603
5604
5605010000,10000,000000000000000,000110:COP0:32::TLBWR
5606"tlbwr"
23850e92
JL		 5607*mipsI,mipsII,mipsIII,mipsIV:
5608*vr5000:
15232df4
FCE		 5609// start-sanitize-vr4320
5610*vr4320:
5611// end-sanitize-vr4320
90ad43b2
AC		 5612// start-sanitize-vr5400
5613*vr5400:
5614// end-sanitize-vr5400
f2b30012
AC		 5615
5616\f
f3bdd368 5617:include:::m16.igen
15232df4
FCE		 5618// start-sanitize-vr4320
5619:include::vr4320:vr4320.igen
5620// end-sanitize-vr4320
16bd5d6e 5621// start-sanitize-vr5400
89d09738 5622:include::vr5400:vr5400.igen
a48e8c8d 5623:include:64,f::mdmx.igen
16bd5d6e 5624// end-sanitize-vr5400
f2b30012 5625// start-sanitize-r5900
89d09738 5626:include::r5900:r5900.igen
f2b30012 5627// end-sanitize-r5900
ebcfd86a 5628:include:::tx.igen
f2b30012
AC		 5629\f
5630// start-sanitize-cygnus-never
5631
49a6eed5
AC		 5632// // FIXME FIXME FIXME What is this instruction?
5633// 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5634// *mipsI:
5635// *mipsII:
5636// *mipsIII:
5637// *mipsIV:
5638// // start-sanitize-r5900
5639// *r5900:
5640// // end-sanitize-r5900
5641// *r3900:
5642// // start-sanitize-tx19
5643// *tx19:
5644// // end-sanitize-tx19
5645// {
5646// unsigned32 instruction = instruction_0;
055ee297
AC		 5647// signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5648// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5649// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
49a6eed5
AC		 5650// {
5651// if (CoProcPresent(3))
5652// SignalException(CoProcessorUnusable);
5653// else
5654// SignalException(ReservedInstruction,instruction);
5655// }
5656// }
5657
5658// end-sanitize-cygnus-never
5659// start-sanitize-cygnus-never
5660
5661// // FIXME FIXME FIXME What is this?
5662// 11100,******,00001:RR:16::SDBBP
5663// *mips16:
5664// {
5665// unsigned32 instruction = instruction_0;
5666// if (have_extendval)
5667// SignalException (ReservedInstruction, instruction);
5668// {
5669// SignalException(DebugBreakPoint,instruction);
5670// }
5671// }
f2b30012
AC		 5672
5673// end-sanitize-cygnus-never
5674// start-sanitize-cygnus-never
5675
49a6eed5
AC		 5676// // FIXME FIXME FIXME What is this?
5677// 000000,********************,001110:SPECIAL:32::SDBBP
5678// *r3900:
5679// {
5680// unsigned32 instruction = instruction_0;
5681// {
5682// SignalException(DebugBreakPoint,instruction);
5683// }
5684// }
f2b30012
AC		 5685
5686// end-sanitize-cygnus-never
5687// start-sanitize-cygnus-never
5688
49a6eed5
AC		 5689// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5690// // isn't yet reconized by this simulator.
5691// 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5692// *vr4100:
5693// {
5694// unsigned32 instruction = instruction_0;
055ee297
AC		 5695// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5696// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
49a6eed5
AC		 5697// {
5698// CHECKHILO("Multiply-Add");
5699// {
5700// unsigned64 temp = (op1 * op2);
5701// temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5702// LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5703// HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5704// }
5705// }
5706// }
f2b30012
AC		 5707
5708// end-sanitize-cygnus-never
49a6eed5
AC		 5709// start-sanitize-cygnus-never
5710
5711// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5712// // isn't yet reconized by this simulator.
5713// 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5714// *vr4100:
5715// {
5716// unsigned32 instruction = instruction_0;
055ee297
AC		 5717// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5718// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
49a6eed5
AC		 5719// {
5720// CHECKHILO("Multiply-Add");
5721// {
5722// unsigned64 temp = (op1 * op2);
5723// LO = LO + temp;
5724// }
5725// }
5726// }
5727
a48e8c8d 5728// end-sanitize-cygnus-never
GDB Binutils - Deliverables
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