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* ldcref.c (check_reloc_refs): Compare section for local syms.
[deliverable/binutils-gdb.git] / sim / mips / mips.igen
CommitLineData
c906108c
SS		 1// -*- C -*-
2//
c906108c
SS		 3// <insn> ::=
4// <insn-word> { "+" <insn-word> }
5// ":" <format-name>
6// ":" <filter-flags>
7// ":" <options>
8// ":" <name>
9// <nl>
10// { <insn-model> }
11// { <insn-mnemonic> }
12// <code-block>
13//
14
15
16// IGEN config - mips16
17// :option:16::insn-bit-size:16
18// :option:16::hi-bit-nr:15
19:option:16::insn-specifying-widths:true
20:option:16::gen-delayed-branch:false
21
22// IGEN config - mips32/64..
23// :option:32::insn-bit-size:32
24// :option:32::hi-bit-nr:31
25:option:32::insn-specifying-widths:true
26:option:32::gen-delayed-branch:false
27
28
29// Generate separate simulators for each target
30// :option:::multi-sim:true
31
32
074e9cb8 33// Models known by this simulator are defined below.
c5d00cc7
CD		 34//
35// When placing models in the instruction descriptions, please place
36// them one per line, in the order given here.
074e9cb8
CD		 37
38// MIPS ISAs:
39//
40// Instructions and related functions for these models are included in
41// this file.
c906108c
SS		 42:model:::mipsI:mips3000:
43:model:::mipsII:mips6000:
44:model:::mipsIII:mips4000:
45:model:::mipsIV:mips8000:
603a98e7 46:model:::mipsV:mipsisaV:
1e799e28 47:model:::mips32:mipsisa32:
e70cb6cd 48:model:::mips32r2:mipsisa32r2:
1e799e28 49:model:::mips64:mipsisa64:
e70cb6cd 50:model:::mips64r2:mipsisa64r2:
074e9cb8
CD		 51
52// Vendor ISAs:
53//
54// Standard MIPS ISA instructions used for these models are listed here,
55// as are functions needed by those standard instructions. Instructions
56// which are model-dependent and which are not in the standard MIPS ISAs
57// (or which pre-date or use different encodings than the standard
58// instructions) are (for the most part) in separate .igen files.
59:model:::vr4100:mips4100: // vr.igen
4c54fc26 60:model:::vr4120:mips4120:
c906108c 61:model:::vr5000:mips5000:
4c54fc26
CD		 62:model:::vr5400:mips5400:
63:model:::vr5500:mips5500:
074e9cb8 64:model:::r3900:mips3900: // tx.igen
c906108c 65
074e9cb8
CD		 66// MIPS Application Specific Extensions (ASEs)
67//
68// Instructions for the ASEs are in separate .igen files.
f4f1b9f1 69// ASEs add instructions on to a base ISA.
074e9cb8 70:model:::mips16:mips16: // m16.igen (and m16.dc)
b16d63da 71:model:::mips16e:mips16e: // m16e.igen
e7e81181 72:model:::mips3d:mips3d: // mips3d.igen
f4f1b9f1 73:model:::mdmx:mdmx: // mdmx.igen
40a5538e 74:model:::dsp:dsp: // dsp.igen
2d2733fc 75:model:::smartmips:smartmips: // smartmips.igen
c906108c 76
7cbea089
CD		 77// Vendor Extensions
78//
79// Instructions specific to these extensions are in separate .igen files.
80// Extensions add instructions on to a base ISA.
81:model:::sb1:sb1: // sb1.igen
82
c906108c
SS		 83
84// Pseudo instructions known by IGEN
85:internal::::illegal:
86{
87 SignalException (ReservedInstruction, 0);
88}
89
90
91// Pseudo instructions known by interp.c
92// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
93000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
94"rsvd <OP>"
95{
96 SignalException (ReservedInstruction, instruction_0);
97}
98
99
100
101// Helper:
102//
103// Simulate a 32 bit delayslot instruction
104//
105
106:function:::address_word:delayslot32:address_word target
107{
108 instruction_word delay_insn;
109 sim_events_slip (SD, 1);
110 DSPC = CIA;
111 CIA = CIA + 4; /* NOTE not mips16 */
112 STATE |= simDELAYSLOT;
113 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
d4f3574e 114 ENGINE_ISSUE_PREFIX_HOOK();
c906108c
SS		 115 idecode_issue (CPU_, delay_insn, (CIA));
116 STATE &= ~simDELAYSLOT;
117 return target;
118}
119
120:function:::address_word:nullify_next_insn32:
121{
122 sim_events_slip (SD, 1);
123 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
124 return CIA + 8;
125}
126
09297648
CD		 127
128// Helper:
129//
130// Calculate an effective address given a base and an offset.
131//
132
133:function:::address_word:loadstore_ea:address_word base, address_word offset
134*mipsI:
135*mipsII:
136*mipsIII:
137*mipsIV:
138*mipsV:
1e799e28 139*mips32:
e70cb6cd 140*mips32r2:
09297648
CD		 141*vr4100:
142*vr5000:
143*r3900:
144{
145 return base + offset;
146}
147
1e799e28
CD		 148:function:::address_word:loadstore_ea:address_word base, address_word offset
149*mips64:
e70cb6cd 150*mips64r2:
1e799e28
CD		 151{
152#if 0 /* XXX FIXME: enable this only after some additional testing. */
153 /* If in user mode and UX is not set, use 32-bit compatibility effective
154 address computations as defined in the MIPS64 Architecture for
155 Programmers Volume III, Revision 0.95, section 4.9. */
156 if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
157 == (ksu_user << status_KSU_shift))
158 return (address_word)((signed32)base + (signed32)offset);
159#endif
160 return base + offset;
161}
162
09297648 163
402586aa
CD		 164// Helper:
165//
166// Check that a 32-bit register value is properly sign-extended.
167// (See NotWordValue in ISA spec.)
168//
169
170:function:::int:not_word_value:unsigned_word value
171*mipsI:
172*mipsII:
173*mipsIII:
174*mipsIV:
175*mipsV:
176*vr4100:
177*vr5000:
178*r3900:
179{
180 /* For historical simulator compatibility (until documentation is
181 found that makes these operations unpredictable on some of these
182 architectures), this check never returns true. */
183 return 0;
184}
185
186:function:::int:not_word_value:unsigned_word value
187*mips32:
e70cb6cd 188*mips32r2:
402586aa
CD		 189{
190 /* On MIPS32, since registers are 32-bits, there's no check to be done. */
191 return 0;
192}
193
194:function:::int:not_word_value:unsigned_word value
195*mips64:
e70cb6cd 196*mips64r2:
402586aa
CD		 197{
198 return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
199}
200
201
202// Helper:
203//
204// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
205// theoretically portable code which invokes non-portable behaviour from
206// running with no indication of the portability issue.
207// (See definition of UNPREDICTABLE in ISA spec.)
208//
209
210:function:::void:unpredictable:
211*mipsI:
212*mipsII:
213*mipsIII:
214*mipsIV:
215*mipsV:
216*vr4100:
217*vr5000:
218*r3900:
219{
220}
221
222:function:::void:unpredictable:
223*mips32:
e70cb6cd 224*mips32r2:
402586aa 225*mips64:
e70cb6cd 226*mips64r2:
402586aa
CD		 227{
228 unpredictable_action (CPU, CIA);
229}
230
231
b3208fb8 232// Helpers:
4a0bd876 233//
c906108c
SS		 234// Check that an access to a HI/LO register meets timing requirements
235//
b3208fb8 236// In all MIPS ISAs,
c906108c 237//
b3208fb8
CD		 238// OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
239// makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
240//
241// The following restrictions exist for MIPS I - MIPS III:
242//
243// MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
244// in between makes MF UNPREDICTABLE. (2)
245//
246// MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
247// in between makes MF UNPREDICTABLE. (3)
248//
249// On the r3900, restriction (2) is not present, and restriction (3) is not
250// present for multiplication.
251//
0e1b7197
RS		 252// Unfortunately, there seems to be some confusion about whether the last
253// two restrictions should apply to "MIPS IV" as well. One edition of
254// the MIPS IV ISA says they do, but references in later ISA documents
255// suggest they don't.
256//
257// In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
258// these restrictions, while others, like the VR5500, don't. To accomodate
259// such differences, the MIPS IV and MIPS V version of these helper functions
260// use auxillary routines to determine whether the restriction applies.
b3208fb8
CD		 261
262// check_mf_cycles:
263//
264// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
265// to check for restrictions (2) and (3) above.
c906108c 266//
c906108c
SS		 267:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
268{
269 if (history->mf.timestamp + 3 > time)
270 {
271 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
272 itable[MY_INDEX].name,
273 new, (long) CIA,
4a0bd876 274 (long) history->mf.cia);
c906108c
SS		 275 return 0;
276 }
277 return 1;
278}
279
b3208fb8
CD		 280
281// check_mt_hilo:
282//
283// Check for restriction (2) above (for ISAs/processors that have it),
284// and record timestamps for restriction (1) above.
285//
c906108c 286:function:::int:check_mt_hilo:hilo_history *history
c5d00cc7
CD		 287*mipsI:
288*mipsII:
289*mipsIII:
c906108c
SS		 290*vr4100:
291*vr5000:
292{
293 signed64 time = sim_events_time (SD);
294 int ok = check_mf_cycles (SD_, history, time, "MT");
295 history->mt.timestamp = time;
296 history->mt.cia = CIA;
297 return ok;
298}
299
0e1b7197
RS		 300:function:::int:check_mt_hilo:hilo_history *history
301*mipsIV:
302*mipsV:
303{
304 signed64 time = sim_events_time (SD);
305 int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
306 || check_mf_cycles (SD_, history, time, "MT"));
307 history->mt.timestamp = time;
308 history->mt.cia = CIA;
309 return ok;
310}
311
c906108c 312:function:::int:check_mt_hilo:hilo_history *history
1e799e28 313*mips32:
e70cb6cd 314*mips32r2:
1e799e28 315*mips64:
e70cb6cd 316*mips64r2:
c906108c
SS		 317*r3900:
318{
319 signed64 time = sim_events_time (SD);
320 history->mt.timestamp = time;
321 history->mt.cia = CIA;
322 return 1;
323}
324
325
b3208fb8
CD		 326// check_mf_hilo:
327//
328// Check for restriction (1) above, and record timestamps for
329// restriction (2) and (3) above.
330//
c906108c 331:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
c5d00cc7
CD		 332*mipsI:
333*mipsII:
334*mipsIII:
335*mipsIV:
603a98e7 336*mipsV:
1e799e28 337*mips32:
e70cb6cd 338*mips32r2:
1e799e28 339*mips64:
e70cb6cd 340*mips64r2:
c906108c
SS		 341*vr4100:
342*vr5000:
343*r3900:
344{
345 signed64 time = sim_events_time (SD);
346 int ok = 1;
347 if (peer != NULL
348 && peer->mt.timestamp > history->op.timestamp
349 && history->mt.timestamp < history->op.timestamp
350 && ! (history->mf.timestamp > history->op.timestamp
351 && history->mf.timestamp < peer->mt.timestamp)
352 && ! (peer->mf.timestamp > history->op.timestamp
353 && peer->mf.timestamp < peer->mt.timestamp))
354 {
355 /* The peer has been written to since the last OP yet we have
356 not */
357 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
358 itable[MY_INDEX].name,
359 (long) CIA,
360 (long) history->op.cia,
4a0bd876 361 (long) peer->mt.cia);
c906108c
SS		 362 ok = 0;
363 }
364 history->mf.timestamp = time;
365 history->mf.cia = CIA;
366 return ok;
367}
368
369
370
b3208fb8
CD		 371// check_mult_hilo:
372//
373// Check for restriction (3) above (for ISAs/processors that have it)
374// for MULT ops, and record timestamps for restriction (1) above.
375//
c906108c 376:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
c5d00cc7
CD		 377*mipsI:
378*mipsII:
379*mipsIII:
c906108c
SS		 380*vr4100:
381*vr5000:
382{
383 signed64 time = sim_events_time (SD);
384 int ok = (check_mf_cycles (SD_, hi, time, "OP")
385 && check_mf_cycles (SD_, lo, time, "OP"));
386 hi->op.timestamp = time;
387 lo->op.timestamp = time;
388 hi->op.cia = CIA;
389 lo->op.cia = CIA;
390 return ok;
391}
392
0e1b7197
RS		 393:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
394*mipsIV:
395*mipsV:
396{
397 signed64 time = sim_events_time (SD);
398 int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
399 || (check_mf_cycles (SD_, hi, time, "OP")
400 && check_mf_cycles (SD_, lo, time, "OP")));
401 hi->op.timestamp = time;
402 lo->op.timestamp = time;
403 hi->op.cia = CIA;
404 lo->op.cia = CIA;
405 return ok;
406}
407
c906108c 408:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
1e799e28 409*mips32:
e70cb6cd 410*mips32r2:
1e799e28 411*mips64:
e70cb6cd 412*mips64r2:
c906108c
SS		 413*r3900:
414{
415 /* FIXME: could record the fact that a stall occured if we want */
416 signed64 time = sim_events_time (SD);
417 hi->op.timestamp = time;
418 lo->op.timestamp = time;
419 hi->op.cia = CIA;
420 lo->op.cia = CIA;
421 return 1;
422}
423
424
b3208fb8
CD		 425// check_div_hilo:
426//
427// Check for restriction (3) above (for ISAs/processors that have it)
428// for DIV ops, and record timestamps for restriction (1) above.
429//
c906108c 430:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
c5d00cc7
CD		 431*mipsI:
432*mipsII:
433*mipsIII:
c906108c
SS		 434*vr4100:
435*vr5000:
436*r3900:
437{
438 signed64 time = sim_events_time (SD);
439 int ok = (check_mf_cycles (SD_, hi, time, "OP")
440 && check_mf_cycles (SD_, lo, time, "OP"));
441 hi->op.timestamp = time;
442 lo->op.timestamp = time;
443 hi->op.cia = CIA;
444 lo->op.cia = CIA;
445 return ok;
446}
447
0e1b7197
RS		 448:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
449*mipsIV:
450*mipsV:
451{
452 signed64 time = sim_events_time (SD);
453 int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
454 || (check_mf_cycles (SD_, hi, time, "OP")
455 && check_mf_cycles (SD_, lo, time, "OP")));
456 hi->op.timestamp = time;
457 lo->op.timestamp = time;
458 hi->op.cia = CIA;
459 lo->op.cia = CIA;
460 return ok;
461}
462
b3208fb8
CD		 463:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
464*mips32:
e70cb6cd 465*mips32r2:
b3208fb8 466*mips64:
e70cb6cd 467*mips64r2:
b3208fb8
CD		 468{
469 signed64 time = sim_events_time (SD);
470 hi->op.timestamp = time;
471 lo->op.timestamp = time;
472 hi->op.cia = CIA;
473 lo->op.cia = CIA;
474 return 1;
475}
476
c906108c 477
ca971540 478// Helper:
4a0bd876 479//
ca971540 480// Check that the 64-bit instruction can currently be used, and signal
b5040d49 481// a ReservedInstruction exception if not.
ca971540
CD		 482//
483
484:function:::void:check_u64:instruction_word insn
485*mipsIII:
486*mipsIV:
487*mipsV:
488*vr4100:
489*vr5000:
e70cb6cd
CD		 490*vr5400:
491*vr5500:
ca971540 492{
ca971540
CD		 493 // The check should be similar to mips64 for any with PX/UX bit equivalents.
494}
c906108c 495
1e799e28 496:function:::void:check_u64:instruction_word insn
b16d63da 497*mips16e:
1e799e28 498*mips64:
e70cb6cd 499*mips64r2:
1e799e28
CD		 500{
501#if 0 /* XXX FIXME: enable this only after some additional testing. */
502 if (UserMode && (SR & (status_UX|status_PX)) == 0)
503 SignalException (ReservedInstruction, insn);
504#endif
505}
506
c906108c
SS		 507
508
509//
074e9cb8 510// MIPS Architecture:
c906108c 511//
e70cb6cd 512// CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
c906108c
SS		 513//
514
515
516
517000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
518"add r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 519*mipsI:
520*mipsII:
521*mipsIII:
522*mipsIV:
603a98e7 523*mipsV:
1e799e28 524*mips32:
e70cb6cd 525*mips32r2:
1e799e28 526*mips64:
e70cb6cd 527*mips64r2:
c906108c
SS		 528*vr4100:
529*vr5000:
530*r3900:
531{
402586aa
CD		 532 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
533 Unpredictable ();
c906108c
SS		 534 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
535 {
536 ALU32_BEGIN (GPR[RS]);
537 ALU32_ADD (GPR[RT]);
9805e229 538 ALU32_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 539 }
540 TRACE_ALU_RESULT (GPR[RD]);
541}
542
543
544
545001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
20ae0098 546"addi r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 547*mipsI:
548*mipsII:
549*mipsIII:
550*mipsIV:
603a98e7 551*mipsV:
1e799e28 552*mips32:
e70cb6cd 553*mips32r2:
1e799e28 554*mips64:
e70cb6cd 555*mips64r2:
c906108c
SS		 556*vr4100:
557*vr5000:
558*r3900:
559{
402586aa
CD		 560 if (NotWordValue (GPR[RS]))
561 Unpredictable ();
c906108c
SS		 562 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
563 {
564 ALU32_BEGIN (GPR[RS]);
565 ALU32_ADD (EXTEND16 (IMMEDIATE));
9805e229 566 ALU32_END (GPR[RT]); /* This checks for overflow. */
c906108c
SS		 567 }
568 TRACE_ALU_RESULT (GPR[RT]);
569}
570
571
572
573:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
574{
402586aa
CD		 575 if (NotWordValue (GPR[rs]))
576 Unpredictable ();
c906108c
SS		 577 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
578 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
579 TRACE_ALU_RESULT (GPR[rt]);
580}
581
582001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
583"addiu r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 584*mipsI:
585*mipsII:
586*mipsIII:
587*mipsIV:
603a98e7 588*mipsV:
1e799e28 589*mips32:
e70cb6cd 590*mips32r2:
1e799e28 591*mips64:
e70cb6cd 592*mips64r2:
c906108c
SS		 593*vr4100:
594*vr5000:
595*r3900:
596{
597 do_addiu (SD_, RS, RT, IMMEDIATE);
598}
599
600
601
602:function:::void:do_addu:int rs, int rt, int rd
603{
402586aa
CD		 604 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
605 Unpredictable ();
c906108c
SS		 606 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
607 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
608 TRACE_ALU_RESULT (GPR[rd]);
609}
610
611000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
612"addu r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 613*mipsI:
614*mipsII:
615*mipsIII:
616*mipsIV:
603a98e7 617*mipsV:
1e799e28 618*mips32:
e70cb6cd 619*mips32r2:
1e799e28 620*mips64:
e70cb6cd 621*mips64r2:
c906108c
SS		 622*vr4100:
623*vr5000:
624*r3900:
625{
626 do_addu (SD_, RS, RT, RD);
627}
628
629
630
631:function:::void:do_and:int rs, int rt, int rd
632{
633 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
634 GPR[rd] = GPR[rs] & GPR[rt];
635 TRACE_ALU_RESULT (GPR[rd]);
636}
637
638000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
639"and r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 640*mipsI:
641*mipsII:
642*mipsIII:
643*mipsIV:
603a98e7 644*mipsV:
1e799e28 645*mips32:
e70cb6cd 646*mips32r2:
1e799e28 647*mips64:
e70cb6cd 648*mips64r2:
c906108c
SS		 649*vr4100:
650*vr5000:
651*r3900:
652{
653 do_and (SD_, RS, RT, RD);
654}
655
656
657
658001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
82f728db 659"andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
c5d00cc7
CD		 660*mipsI:
661*mipsII:
662*mipsIII:
663*mipsIV:
603a98e7 664*mipsV:
1e799e28 665*mips32:
e70cb6cd 666*mips32r2:
1e799e28 667*mips64:
e70cb6cd 668*mips64r2:
c906108c
SS		 669*vr4100:
670*vr5000:
671*r3900:
672{
673 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
674 GPR[RT] = GPR[RS] & IMMEDIATE;
675 TRACE_ALU_RESULT (GPR[RT]);
676}
677
678
679
680000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
681"beq r<RS>, r<RT>, <OFFSET>"
c5d00cc7
CD		 682*mipsI:
683*mipsII:
684*mipsIII:
685*mipsIV:
603a98e7 686*mipsV:
1e799e28 687*mips32:
e70cb6cd 688*mips32r2:
1e799e28 689*mips64:
e70cb6cd 690*mips64r2:
c906108c
SS		 691*vr4100:
692*vr5000:
693*r3900:
694{
695 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 696 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
697 {
c906108c
SS		 698 DELAY_SLOT (NIA + offset);
699 }
700}
701
702
703
704010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
705"beql r<RS>, r<RT>, <OFFSET>"
706*mipsII:
707*mipsIII:
708*mipsIV:
603a98e7 709*mipsV:
1e799e28 710*mips32:
e70cb6cd 711*mips32r2:
1e799e28 712*mips64:
e70cb6cd 713*mips64r2:
c906108c
SS		 714*vr4100:
715*vr5000:
716*r3900:
717{
718 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 719 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
720 {
c906108c
SS		 721 DELAY_SLOT (NIA + offset);
722 }
723 else
724 NULLIFY_NEXT_INSTRUCTION ();
725}
726
727
728
729000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
730"bgez r<RS>, <OFFSET>"
c5d00cc7
CD		 731*mipsI:
732*mipsII:
733*mipsIII:
734*mipsIV:
603a98e7 735*mipsV:
1e799e28 736*mips32:
e70cb6cd 737*mips32r2:
1e799e28 738*mips64:
e70cb6cd 739*mips64r2:
c906108c
SS		 740*vr4100:
741*vr5000:
742*r3900:
743{
744 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 745 if ((signed_word) GPR[RS] >= 0)
746 {
c906108c
SS		 747 DELAY_SLOT (NIA + offset);
748 }
749}
750
751
752
753000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
754"bgezal r<RS>, <OFFSET>"
c5d00cc7
CD		 755*mipsI:
756*mipsII:
757*mipsIII:
758*mipsIV:
603a98e7 759*mipsV:
1e799e28 760*mips32:
e70cb6cd 761*mips32r2:
1e799e28 762*mips64:
e70cb6cd 763*mips64r2:
c906108c
SS		 764*vr4100:
765*vr5000:
766*r3900:
767{
768 address_word offset = EXTEND16 (OFFSET) << 2;
402586aa
CD		 769 if (RS == 31)
770 Unpredictable ();
c906108c
SS		 771 RA = (CIA + 8);
772 if ((signed_word) GPR[RS] >= 0)
773 {
c906108c
SS		 774 DELAY_SLOT (NIA + offset);
775 }
776}
777
778
779
780000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
781"bgezall r<RS>, <OFFSET>"
782*mipsII:
783*mipsIII:
784*mipsIV:
603a98e7 785*mipsV:
1e799e28 786*mips32:
e70cb6cd 787*mips32r2:
1e799e28 788*mips64:
e70cb6cd 789*mips64r2:
c906108c
SS		 790*vr4100:
791*vr5000:
792*r3900:
793{
794 address_word offset = EXTEND16 (OFFSET) << 2;
402586aa
CD		 795 if (RS == 31)
796 Unpredictable ();
c906108c
SS		 797 RA = (CIA + 8);
798 /* NOTE: The branch occurs AFTER the next instruction has been
799 executed */
800 if ((signed_word) GPR[RS] >= 0)
801 {
c906108c
SS		 802 DELAY_SLOT (NIA + offset);
803 }
804 else
805 NULLIFY_NEXT_INSTRUCTION ();
806}
807
808
809
810000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
811"bgezl r<RS>, <OFFSET>"
812*mipsII:
813*mipsIII:
814*mipsIV:
603a98e7 815*mipsV:
1e799e28 816*mips32:
e70cb6cd 817*mips32r2:
1e799e28 818*mips64:
e70cb6cd 819*mips64r2:
c906108c
SS		 820*vr4100:
821*vr5000:
822*r3900:
823{
824 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 825 if ((signed_word) GPR[RS] >= 0)
826 {
c906108c
SS		 827 DELAY_SLOT (NIA + offset);
828 }
829 else
830 NULLIFY_NEXT_INSTRUCTION ();
831}
832
833
834
835000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
836"bgtz r<RS>, <OFFSET>"
c5d00cc7
CD		 837*mipsI:
838*mipsII:
839*mipsIII:
840*mipsIV:
603a98e7 841*mipsV:
1e799e28 842*mips32:
e70cb6cd 843*mips32r2:
1e799e28 844*mips64:
e70cb6cd 845*mips64r2:
c906108c
SS		 846*vr4100:
847*vr5000:
848*r3900:
849{
850 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 851 if ((signed_word) GPR[RS] > 0)
852 {
c906108c
SS		 853 DELAY_SLOT (NIA + offset);
854 }
855}
856
857
858
859010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
860"bgtzl r<RS>, <OFFSET>"
861*mipsII:
862*mipsIII:
863*mipsIV:
603a98e7 864*mipsV:
1e799e28 865*mips32:
e70cb6cd 866*mips32r2:
1e799e28 867*mips64:
e70cb6cd 868*mips64r2:
c906108c
SS		 869*vr4100:
870*vr5000:
871*r3900:
872{
873 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 874 /* NOTE: The branch occurs AFTER the next instruction has been
875 executed */
876 if ((signed_word) GPR[RS] > 0)
877 {
c906108c
SS		 878 DELAY_SLOT (NIA + offset);
879 }
880 else
881 NULLIFY_NEXT_INSTRUCTION ();
882}
883
884
885
886000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
887"blez r<RS>, <OFFSET>"
c5d00cc7
CD		 888*mipsI:
889*mipsII:
890*mipsIII:
891*mipsIV:
603a98e7 892*mipsV:
1e799e28 893*mips32:
e70cb6cd 894*mips32r2:
1e799e28 895*mips64:
e70cb6cd 896*mips64r2:
c906108c
SS		 897*vr4100:
898*vr5000:
899*r3900:
900{
901 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 902 /* NOTE: The branch occurs AFTER the next instruction has been
903 executed */
904 if ((signed_word) GPR[RS] <= 0)
905 {
c906108c
SS		 906 DELAY_SLOT (NIA + offset);
907 }
908}
909
910
911
912010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
913"bgezl r<RS>, <OFFSET>"
914*mipsII:
915*mipsIII:
916*mipsIV:
603a98e7 917*mipsV:
1e799e28 918*mips32:
e70cb6cd 919*mips32r2:
1e799e28 920*mips64:
e70cb6cd 921*mips64r2:
c906108c
SS		 922*vr4100:
923*vr5000:
924*r3900:
925{
926 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 927 if ((signed_word) GPR[RS] <= 0)
928 {
c906108c
SS		 929 DELAY_SLOT (NIA + offset);
930 }
931 else
932 NULLIFY_NEXT_INSTRUCTION ();
933}
934
935
936
937000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
938"bltz r<RS>, <OFFSET>"
c5d00cc7
CD		 939*mipsI:
940*mipsII:
941*mipsIII:
942*mipsIV:
603a98e7 943*mipsV:
1e799e28 944*mips32:
e70cb6cd 945*mips32r2:
1e799e28 946*mips64:
e70cb6cd 947*mips64r2:
c906108c
SS		 948*vr4100:
949*vr5000:
950*r3900:
951{
952 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 953 if ((signed_word) GPR[RS] < 0)
954 {
c906108c
SS		 955 DELAY_SLOT (NIA + offset);
956 }
957}
958
959
960
961000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
962"bltzal r<RS>, <OFFSET>"
c5d00cc7
CD		 963*mipsI:
964*mipsII:
965*mipsIII:
966*mipsIV:
603a98e7 967*mipsV:
1e799e28 968*mips32:
e70cb6cd 969*mips32r2:
1e799e28 970*mips64:
e70cb6cd 971*mips64r2:
c906108c
SS		 972*vr4100:
973*vr5000:
974*r3900:
975{
976 address_word offset = EXTEND16 (OFFSET) << 2;
402586aa
CD		 977 if (RS == 31)
978 Unpredictable ();
c906108c
SS		 979 RA = (CIA + 8);
980 /* NOTE: The branch occurs AFTER the next instruction has been
981 executed */
982 if ((signed_word) GPR[RS] < 0)
983 {
c906108c
SS		 984 DELAY_SLOT (NIA + offset);
985 }
986}
987
988
989
990000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
991"bltzall r<RS>, <OFFSET>"
992*mipsII:
993*mipsIII:
994*mipsIV:
603a98e7 995*mipsV:
1e799e28 996*mips32:
e70cb6cd 997*mips32r2:
1e799e28 998*mips64:
e70cb6cd 999*mips64r2:
c906108c
SS		 1000*vr4100:
1001*vr5000:
1002*r3900:
1003{
1004 address_word offset = EXTEND16 (OFFSET) << 2;
402586aa
CD		 1005 if (RS == 31)
1006 Unpredictable ();
c906108c
SS		 1007 RA = (CIA + 8);
1008 if ((signed_word) GPR[RS] < 0)
1009 {
c906108c
SS		 1010 DELAY_SLOT (NIA + offset);
1011 }
1012 else
1013 NULLIFY_NEXT_INSTRUCTION ();
1014}
1015
1016
1017
1018000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
1019"bltzl r<RS>, <OFFSET>"
1020*mipsII:
1021*mipsIII:
1022*mipsIV:
603a98e7 1023*mipsV:
1e799e28 1024*mips32:
e70cb6cd 1025*mips32r2:
1e799e28 1026*mips64:
e70cb6cd 1027*mips64r2:
c906108c
SS		 1028*vr4100:
1029*vr5000:
1030*r3900:
1031{
1032 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 1033 /* NOTE: The branch occurs AFTER the next instruction has been
1034 executed */
1035 if ((signed_word) GPR[RS] < 0)
1036 {
c906108c
SS		 1037 DELAY_SLOT (NIA + offset);
1038 }
1039 else
1040 NULLIFY_NEXT_INSTRUCTION ();
1041}
1042
1043
1044
1045000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
1046"bne r<RS>, r<RT>, <OFFSET>"
c5d00cc7
CD		 1047*mipsI:
1048*mipsII:
1049*mipsIII:
1050*mipsIV:
603a98e7 1051*mipsV:
1e799e28 1052*mips32:
e70cb6cd 1053*mips32r2:
1e799e28 1054*mips64:
e70cb6cd 1055*mips64r2:
c906108c
SS		 1056*vr4100:
1057*vr5000:
1058*r3900:
1059{
1060 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 1061 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1062 {
c906108c
SS		 1063 DELAY_SLOT (NIA + offset);
1064 }
1065}
1066
1067
1068
1069010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1070"bnel r<RS>, r<RT>, <OFFSET>"
1071*mipsII:
1072*mipsIII:
1073*mipsIV:
603a98e7 1074*mipsV:
1e799e28 1075*mips32:
e70cb6cd 1076*mips32r2:
1e799e28 1077*mips64:
e70cb6cd 1078*mips64r2:
c906108c
SS		 1079*vr4100:
1080*vr5000:
1081*r3900:
1082{
1083 address_word offset = EXTEND16 (OFFSET) << 2;
c906108c
SS		 1084 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1085 {
c906108c
SS		 1086 DELAY_SLOT (NIA + offset);
1087 }
1088 else
1089 NULLIFY_NEXT_INSTRUCTION ();
1090}
1091
1092
1093
1094000000,20.CODE,001101:SPECIAL:32::BREAK
82f728db 1095"break %#lx<CODE>"
c5d00cc7
CD		 1096*mipsI:
1097*mipsII:
1098*mipsIII:
1099*mipsIV:
603a98e7 1100*mipsV:
1e799e28 1101*mips32:
e70cb6cd 1102*mips32r2:
1e799e28 1103*mips64:
e70cb6cd 1104*mips64r2:
c906108c
SS		 1105*vr4100:
1106*vr5000:
1107*r3900:
1108{
1109 /* Check for some break instruction which are reserved for use by the simulator. */
1110 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1111 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1112 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1113 {
1114 sim_engine_halt (SD, CPU, NULL, cia,
1115 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1116 }
1117 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1118 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1119 {
1120 if (STATE & simDELAYSLOT)
1121 PC = cia - 4; /* reference the branch instruction */
1122 else
1123 PC = cia;
86b77b47 1124 SignalException (BreakPoint, instruction_0);
c906108c
SS		 1125 }
1126
1127 else
1128 {
4a0bd876 1129 /* If we get this far, we're not an instruction reserved by the sim. Raise
c906108c 1130 the exception. */
86b77b47 1131 SignalException (BreakPoint, instruction_0);
c906108c
SS		 1132 }
1133}
1134
1135
1136
1e799e28
CD		 1137011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1138"clo r<RD>, r<RS>"
1139*mips32:
e70cb6cd 1140*mips32r2:
1e799e28 1141*mips64:
e70cb6cd 1142*mips64r2:
4c54fc26 1143*vr5500:
1e799e28
CD		 1144{
1145 unsigned32 temp = GPR[RS];
1146 unsigned32 i, mask;
1147 if (RT != RD)
c9b9995a 1148 Unpredictable ();
402586aa
CD		 1149 if (NotWordValue (GPR[RS]))
1150 Unpredictable ();
1e799e28
CD		 1151 TRACE_ALU_INPUT1 (GPR[RS]);
1152 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1153 {
1154 if ((temp & mask) == 0)
1155 break;
1156 mask >>= 1;
1157 }
1158 GPR[RD] = EXTEND32 (i);
1159 TRACE_ALU_RESULT (GPR[RD]);
1160}
1161
1162
1163
1164011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1165"clz r<RD>, r<RS>"
1166*mips32:
e70cb6cd 1167*mips32r2:
1e799e28 1168*mips64:
e70cb6cd 1169*mips64r2:
4c54fc26 1170*vr5500:
1e799e28
CD		 1171{
1172 unsigned32 temp = GPR[RS];
1173 unsigned32 i, mask;
1174 if (RT != RD)
c9b9995a 1175 Unpredictable ();
402586aa
CD		 1176 if (NotWordValue (GPR[RS]))
1177 Unpredictable ();
1e799e28
CD		 1178 TRACE_ALU_INPUT1 (GPR[RS]);
1179 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1180 {
1181 if ((temp & mask) != 0)
1182 break;
1183 mask >>= 1;
1184 }
1185 GPR[RD] = EXTEND32 (i);
1186 TRACE_ALU_RESULT (GPR[RD]);
1187}
1188
1189
1190
c906108c
SS		 1191000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1192"dadd r<RD>, r<RS>, r<RT>"
1193*mipsIII:
1194*mipsIV:
603a98e7 1195*mipsV:
1e799e28 1196*mips64:
e70cb6cd 1197*mips64r2:
c906108c
SS		 1198*vr4100:
1199*vr5000:
1200{
ca971540 1201 check_u64 (SD_, instruction_0);
c906108c
SS		 1202 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1203 {
1204 ALU64_BEGIN (GPR[RS]);
1205 ALU64_ADD (GPR[RT]);
9805e229 1206 ALU64_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 1207 }
1208 TRACE_ALU_RESULT (GPR[RD]);
1209}
1210
1211
1212
1213011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1214"daddi r<RT>, r<RS>, <IMMEDIATE>"
1215*mipsIII:
1216*mipsIV:
603a98e7 1217*mipsV:
1e799e28 1218*mips64:
e70cb6cd 1219*mips64r2:
c906108c
SS		 1220*vr4100:
1221*vr5000:
1222{
ca971540 1223 check_u64 (SD_, instruction_0);
c906108c
SS		 1224 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1225 {
1226 ALU64_BEGIN (GPR[RS]);
1227 ALU64_ADD (EXTEND16 (IMMEDIATE));
9805e229 1228 ALU64_END (GPR[RT]); /* This checks for overflow. */
c906108c
SS		 1229 }
1230 TRACE_ALU_RESULT (GPR[RT]);
1231}
1232
1233
1234
1235:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1236{
1237 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1238 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1239 TRACE_ALU_RESULT (GPR[rt]);
1240}
1241
1242011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
20ae0098 1243"daddiu r<RT>, r<RS>, <IMMEDIATE>"
c906108c
SS		 1244*mipsIII:
1245*mipsIV:
603a98e7 1246*mipsV:
1e799e28 1247*mips64:
e70cb6cd 1248*mips64r2:
c906108c
SS		 1249*vr4100:
1250*vr5000:
1251{
ca971540 1252 check_u64 (SD_, instruction_0);
c906108c
SS		 1253 do_daddiu (SD_, RS, RT, IMMEDIATE);
1254}
1255
1256
1257
1258:function:::void:do_daddu:int rs, int rt, int rd
1259{
1260 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1261 GPR[rd] = GPR[rs] + GPR[rt];
1262 TRACE_ALU_RESULT (GPR[rd]);
1263}
1264
1265000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1266"daddu r<RD>, r<RS>, r<RT>"
1267*mipsIII:
1268*mipsIV:
603a98e7 1269*mipsV:
1e799e28 1270*mips64:
e70cb6cd 1271*mips64r2:
c906108c
SS		 1272*vr4100:
1273*vr5000:
1274{
ca971540 1275 check_u64 (SD_, instruction_0);
c906108c
SS		 1276 do_daddu (SD_, RS, RT, RD);
1277}
1278
1279
1280
1e799e28
CD		 1281011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1282"dclo r<RD>, r<RS>"
1283*mips64:
e70cb6cd 1284*mips64r2:
4c54fc26 1285*vr5500:
1e799e28
CD		 1286{
1287 unsigned64 temp = GPR[RS];
1288 unsigned32 i;
1289 unsigned64 mask;
1290 check_u64 (SD_, instruction_0);
1291 if (RT != RD)
c9b9995a 1292 Unpredictable ();
1e799e28
CD		 1293 TRACE_ALU_INPUT1 (GPR[RS]);
1294 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1295 {
1296 if ((temp & mask) == 0)
1297 break;
1298 mask >>= 1;
1299 }
1300 GPR[RD] = EXTEND32 (i);
1301 TRACE_ALU_RESULT (GPR[RD]);
1302}
1303
1304
1305
1306011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1307"dclz r<RD>, r<RS>"
1308*mips64:
e70cb6cd 1309*mips64r2:
4c54fc26 1310*vr5500:
1e799e28
CD		 1311{
1312 unsigned64 temp = GPR[RS];
1313 unsigned32 i;
1314 unsigned64 mask;
1315 check_u64 (SD_, instruction_0);
1316 if (RT != RD)
c9b9995a 1317 Unpredictable ();
1e799e28
CD		 1318 TRACE_ALU_INPUT1 (GPR[RS]);
1319 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1320 {
1321 if ((temp & mask) != 0)
1322 break;
1323 mask >>= 1;
1324 }
1325 GPR[RD] = EXTEND32 (i);
1326 TRACE_ALU_RESULT (GPR[RD]);
1327}
1328
1329
1330
c906108c
SS		 1331:function:::void:do_ddiv:int rs, int rt
1332{
1333 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1334 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1335 {
1336 signed64 n = GPR[rs];
1337 signed64 d = GPR[rt];
1338 signed64 hi;
1339 signed64 lo;
1340 if (d == 0)
1341 {
1342 lo = SIGNED64 (0x8000000000000000);
1343 hi = 0;
1344 }
1345 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1346 {
1347 lo = SIGNED64 (0x8000000000000000);
1348 hi = 0;
1349 }
1350 else
1351 {
1352 lo = (n / d);
1353 hi = (n % d);
1354 }
1355 HI = hi;
1356 LO = lo;
1357 }
1358 TRACE_ALU_RESULT2 (HI, LO);
1359}
1360
f701dad2 1361000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
c906108c
SS		 1362"ddiv r<RS>, r<RT>"
1363*mipsIII:
1364*mipsIV:
603a98e7 1365*mipsV:
1e799e28 1366*mips64:
e70cb6cd 1367*mips64r2:
c906108c
SS		 1368*vr4100:
1369*vr5000:
1370{
ca971540 1371 check_u64 (SD_, instruction_0);
c906108c
SS		 1372 do_ddiv (SD_, RS, RT);
1373}
1374
1375
1376
1377:function:::void:do_ddivu:int rs, int rt
1378{
1379 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1380 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1381 {
1382 unsigned64 n = GPR[rs];
1383 unsigned64 d = GPR[rt];
1384 unsigned64 hi;
1385 unsigned64 lo;
1386 if (d == 0)
1387 {
1388 lo = SIGNED64 (0x8000000000000000);
1389 hi = 0;
1390 }
1391 else
1392 {
1393 lo = (n / d);
1394 hi = (n % d);
1395 }
1396 HI = hi;
1397 LO = lo;
1398 }
1399 TRACE_ALU_RESULT2 (HI, LO);
1400}
1401
1402000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1403"ddivu r<RS>, r<RT>"
1404*mipsIII:
1405*mipsIV:
603a98e7 1406*mipsV:
1e799e28 1407*mips64:
e70cb6cd 1408*mips64r2:
c906108c
SS		 1409*vr4100:
1410*vr5000:
1411{
ca971540 1412 check_u64 (SD_, instruction_0);
c906108c
SS		 1413 do_ddivu (SD_, RS, RT);
1414}
1415
c906108c
SS		 1416:function:::void:do_div:int rs, int rt
1417{
1418 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1419 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1420 {
1421 signed32 n = GPR[rs];
1422 signed32 d = GPR[rt];
1423 if (d == 0)
1424 {
1425 LO = EXTEND32 (0x80000000);
1426 HI = EXTEND32 (0);
1427 }
1428 else if (n == SIGNED32 (0x80000000) && d == -1)
1429 {
1430 LO = EXTEND32 (0x80000000);
1431 HI = EXTEND32 (0);
1432 }
1433 else
1434 {
1435 LO = EXTEND32 (n / d);
1436 HI = EXTEND32 (n % d);
1437 }
1438 }
1439 TRACE_ALU_RESULT2 (HI, LO);
1440}
1441
f701dad2 1442000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
c906108c 1443"div r<RS>, r<RT>"
c5d00cc7
CD		 1444*mipsI:
1445*mipsII:
1446*mipsIII:
1447*mipsIV:
603a98e7 1448*mipsV:
1e799e28 1449*mips32:
e70cb6cd 1450*mips32r2:
1e799e28 1451*mips64:
e70cb6cd 1452*mips64r2:
c906108c
SS		 1453*vr4100:
1454*vr5000:
1455*r3900:
1456{
1457 do_div (SD_, RS, RT);
1458}
1459
1460
1461
1462:function:::void:do_divu:int rs, int rt
1463{
1464 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1465 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1466 {
1467 unsigned32 n = GPR[rs];
1468 unsigned32 d = GPR[rt];
1469 if (d == 0)
1470 {
1471 LO = EXTEND32 (0x80000000);
1472 HI = EXTEND32 (0);
1473 }
3e1dca16
CD		 1474 else
1475 {
1476 LO = EXTEND32 (n / d);
1477 HI = EXTEND32 (n % d);
1478 }
c906108c
SS		 1479 }
1480 TRACE_ALU_RESULT2 (HI, LO);
1481}
1482
f701dad2 1483000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
c906108c 1484"divu r<RS>, r<RT>"
c5d00cc7
CD		 1485*mipsI:
1486*mipsII:
1487*mipsIII:
1488*mipsIV:
603a98e7 1489*mipsV:
1e799e28 1490*mips32:
e70cb6cd 1491*mips32r2:
1e799e28 1492*mips64:
e70cb6cd 1493*mips64r2:
c906108c
SS		 1494*vr4100:
1495*vr5000:
1496*r3900:
1497{
1498 do_divu (SD_, RS, RT);
1499}
1500
1501
c906108c
SS		 1502:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1503{
1504 unsigned64 lo;
1505 unsigned64 hi;
1506 unsigned64 m00;
1507 unsigned64 m01;
1508 unsigned64 m10;
1509 unsigned64 m11;
1510 unsigned64 mid;
1511 int sign;
1512 unsigned64 op1 = GPR[rs];
1513 unsigned64 op2 = GPR[rt];
1514 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1515 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4a0bd876 1516 /* make signed multiply unsigned */
c906108c
SS		 1517 sign = 0;
1518 if (signed_p)
1519 {
9a1d84fb 1520 if ((signed64) op1 < 0)
c906108c
SS		 1521 {
1522 op1 = - op1;
1523 ++sign;
1524 }
9a1d84fb 1525 if ((signed64) op2 < 0)
c906108c
SS		 1526 {
1527 op2 = - op2;
1528 ++sign;
1529 }
1530 }
67f5c7ef 1531 /* multiply out the 4 sub products */
c906108c
SS		 1532 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1533 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1534 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1535 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1536 /* add the products */
1537 mid = ((unsigned64) VH4_8 (m00)
1538 + (unsigned64) VL4_8 (m10)
1539 + (unsigned64) VL4_8 (m01));
1540 lo = U8_4 (mid, m00);
1541 hi = (m11
1542 + (unsigned64) VH4_8 (mid)
1543 + (unsigned64) VH4_8 (m01)
1544 + (unsigned64) VH4_8 (m10));
1545 /* fix the sign */
1546 if (sign & 1)
1547 {
1548 lo = -lo;
1549 if (lo == 0)
1550 hi = -hi;
1551 else
1552 hi = -hi - 1;
1553 }
1554 /* save the result HI/LO (and a gpr) */
1555 LO = lo;
1556 HI = hi;
1557 if (rd != 0)
1558 GPR[rd] = lo;
1559 TRACE_ALU_RESULT2 (HI, LO);
1560}
1561
1562:function:::void:do_dmult:int rs, int rt, int rd
1563{
1564 do_dmultx (SD_, rs, rt, rd, 1);
1565}
1566
f701dad2 1567000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
c906108c 1568"dmult r<RS>, r<RT>"
c5d00cc7
CD		 1569*mipsIII:
1570*mipsIV:
603a98e7 1571*mipsV:
1e799e28 1572*mips64:
e70cb6cd 1573*mips64r2:
c906108c
SS		 1574*vr4100:
1575{
ca971540 1576 check_u64 (SD_, instruction_0);
c906108c
SS		 1577 do_dmult (SD_, RS, RT, 0);
1578}
1579
f701dad2 1580000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
c906108c
SS		 1581"dmult r<RS>, r<RT>":RD == 0
1582"dmult r<RD>, r<RS>, r<RT>"
1583*vr5000:
1584{
ca971540 1585 check_u64 (SD_, instruction_0);
c906108c
SS		 1586 do_dmult (SD_, RS, RT, RD);
1587}
1588
1589
1590
1591:function:::void:do_dmultu:int rs, int rt, int rd
1592{
1593 do_dmultx (SD_, rs, rt, rd, 0);
1594}
1595
f701dad2 1596000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
c906108c 1597"dmultu r<RS>, r<RT>"
c5d00cc7
CD		 1598*mipsIII:
1599*mipsIV:
603a98e7 1600*mipsV:
1e799e28 1601*mips64:
e70cb6cd 1602*mips64r2:
c906108c
SS		 1603*vr4100:
1604{
ca971540 1605 check_u64 (SD_, instruction_0);
c906108c
SS		 1606 do_dmultu (SD_, RS, RT, 0);
1607}
1608
f701dad2 1609000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
c906108c
SS		 1610"dmultu r<RD>, r<RS>, r<RT>":RD == 0
1611"dmultu r<RS>, r<RT>"
1612*vr5000:
1613{
ca971540 1614 check_u64 (SD_, instruction_0);
c906108c
SS		 1615 do_dmultu (SD_, RS, RT, RD);
1616}
1617
e70cb6cd
CD		 1618
1619:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
1620{
1621 unsigned64 result;
1622
1623 y &= 63;
1624 TRACE_ALU_INPUT2 (x, y);
1625 result = ROTR64 (x, y);
1626 TRACE_ALU_RESULT (result);
1627 return result;
1628}
1629
1630000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
1631"dror r<RD>, r<RT>, <SHIFT>"
1632*mips64r2:
1633*vr5400:
1634*vr5500:
1635{
1636 check_u64 (SD_, instruction_0);
1637 GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
1638}
1639
1640000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
1641"dror32 r<RD>, r<RT>, <SHIFT>"
1642*mips64r2:
1643*vr5400:
1644*vr5500:
1645{
1646 check_u64 (SD_, instruction_0);
1647 GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
1648}
1649
1650000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
1651"drorv r<RD>, r<RT>, r<RS>"
1652*mips64r2:
1653*vr5400:
1654*vr5500:
1655{
1656 check_u64 (SD_, instruction_0);
1657 GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
1658}
1659
1660
c906108c
SS		 1661:function:::void:do_dsll:int rt, int rd, int shift
1662{
fff8d27d 1663 TRACE_ALU_INPUT2 (GPR[rt], shift);
c906108c 1664 GPR[rd] = GPR[rt] << shift;
fff8d27d 1665 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 1666}
1667
f701dad2 1668000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
c906108c
SS		 1669"dsll r<RD>, r<RT>, <SHIFT>"
1670*mipsIII:
1671*mipsIV:
603a98e7 1672*mipsV:
1e799e28 1673*mips64:
e70cb6cd 1674*mips64r2:
c906108c
SS		 1675*vr4100:
1676*vr5000:
1677{
ca971540 1678 check_u64 (SD_, instruction_0);
c906108c
SS		 1679 do_dsll (SD_, RT, RD, SHIFT);
1680}
1681
1682
f701dad2 1683000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
c906108c
SS		 1684"dsll32 r<RD>, r<RT>, <SHIFT>"
1685*mipsIII:
1686*mipsIV:
603a98e7 1687*mipsV:
1e799e28 1688*mips64:
e70cb6cd 1689*mips64r2:
c906108c
SS		 1690*vr4100:
1691*vr5000:
1692{
1693 int s = 32 + SHIFT;
ca971540 1694 check_u64 (SD_, instruction_0);
fff8d27d 1695 TRACE_ALU_INPUT2 (GPR[RT], s);
c906108c 1696 GPR[RD] = GPR[RT] << s;
fff8d27d 1697 TRACE_ALU_RESULT (GPR[RD]);
c906108c
SS		 1698}
1699
3e1dca16
CD		 1700:function:::void:do_dsllv:int rs, int rt, int rd
1701{
1702 int s = MASKED64 (GPR[rs], 5, 0);
1703 TRACE_ALU_INPUT2 (GPR[rt], s);
1704 GPR[rd] = GPR[rt] << s;
1705 TRACE_ALU_RESULT (GPR[rd]);
1706}
1707
f701dad2 1708000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
c906108c
SS		 1709"dsllv r<RD>, r<RT>, r<RS>"
1710*mipsIII:
1711*mipsIV:
603a98e7 1712*mipsV:
1e799e28 1713*mips64:
e70cb6cd 1714*mips64r2:
c906108c
SS		 1715*vr4100:
1716*vr5000:
1717{
ca971540 1718 check_u64 (SD_, instruction_0);
c906108c
SS		 1719 do_dsllv (SD_, RS, RT, RD);
1720}
1721
1722:function:::void:do_dsra:int rt, int rd, int shift
1723{
fff8d27d 1724 TRACE_ALU_INPUT2 (GPR[rt], shift);
c906108c 1725 GPR[rd] = ((signed64) GPR[rt]) >> shift;
fff8d27d 1726 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 1727}
1728
1729
f701dad2 1730000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
c906108c
SS		 1731"dsra r<RD>, r<RT>, <SHIFT>"
1732*mipsIII:
1733*mipsIV:
603a98e7 1734*mipsV:
1e799e28 1735*mips64:
e70cb6cd 1736*mips64r2:
c906108c
SS		 1737*vr4100:
1738*vr5000:
1739{
ca971540 1740 check_u64 (SD_, instruction_0);
c906108c
SS		 1741 do_dsra (SD_, RT, RD, SHIFT);
1742}
1743
1744
f701dad2 1745000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
bb22bd7d 1746"dsra32 r<RD>, r<RT>, <SHIFT>"
c906108c
SS		 1747*mipsIII:
1748*mipsIV:
603a98e7 1749*mipsV:
1e799e28 1750*mips64:
e70cb6cd 1751*mips64r2:
c906108c
SS		 1752*vr4100:
1753*vr5000:
1754{
1755 int s = 32 + SHIFT;
ca971540 1756 check_u64 (SD_, instruction_0);
fff8d27d 1757 TRACE_ALU_INPUT2 (GPR[RT], s);
c906108c 1758 GPR[RD] = ((signed64) GPR[RT]) >> s;
fff8d27d 1759 TRACE_ALU_RESULT (GPR[RD]);
c906108c
SS		 1760}
1761
1762
1763:function:::void:do_dsrav:int rs, int rt, int rd
1764{
1765 int s = MASKED64 (GPR[rs], 5, 0);
1766 TRACE_ALU_INPUT2 (GPR[rt], s);
1767 GPR[rd] = ((signed64) GPR[rt]) >> s;
1768 TRACE_ALU_RESULT (GPR[rd]);
1769}
1770
f701dad2 1771000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
bb22bd7d 1772"dsrav r<RD>, r<RT>, r<RS>"
c906108c
SS		 1773*mipsIII:
1774*mipsIV:
603a98e7 1775*mipsV:
1e799e28 1776*mips64:
e70cb6cd 1777*mips64r2:
c906108c
SS		 1778*vr4100:
1779*vr5000:
1780{
ca971540 1781 check_u64 (SD_, instruction_0);
c906108c
SS		 1782 do_dsrav (SD_, RS, RT, RD);
1783}
1784
1785:function:::void:do_dsrl:int rt, int rd, int shift
1786{
fff8d27d 1787 TRACE_ALU_INPUT2 (GPR[rt], shift);
c906108c 1788 GPR[rd] = (unsigned64) GPR[rt] >> shift;
fff8d27d 1789 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 1790}
1791
1792
f701dad2 1793000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
c906108c
SS		 1794"dsrl r<RD>, r<RT>, <SHIFT>"
1795*mipsIII:
1796*mipsIV:
603a98e7 1797*mipsV:
1e799e28 1798*mips64:
e70cb6cd 1799*mips64r2:
c906108c
SS		 1800*vr4100:
1801*vr5000:
1802{
ca971540 1803 check_u64 (SD_, instruction_0);
c906108c
SS		 1804 do_dsrl (SD_, RT, RD, SHIFT);
1805}
1806
1807
f701dad2 1808000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
c906108c
SS		 1809"dsrl32 r<RD>, r<RT>, <SHIFT>"
1810*mipsIII:
1811*mipsIV:
603a98e7 1812*mipsV:
1e799e28 1813*mips64:
e70cb6cd 1814*mips64r2:
c906108c
SS		 1815*vr4100:
1816*vr5000:
1817{
1818 int s = 32 + SHIFT;
ca971540 1819 check_u64 (SD_, instruction_0);
fff8d27d 1820 TRACE_ALU_INPUT2 (GPR[RT], s);
c906108c 1821 GPR[RD] = (unsigned64) GPR[RT] >> s;
fff8d27d 1822 TRACE_ALU_RESULT (GPR[RD]);
c906108c
SS		 1823}
1824
1825
1826:function:::void:do_dsrlv:int rs, int rt, int rd
1827{
1828 int s = MASKED64 (GPR[rs], 5, 0);
fff8d27d 1829 TRACE_ALU_INPUT2 (GPR[rt], s);
c906108c 1830 GPR[rd] = (unsigned64) GPR[rt] >> s;
fff8d27d 1831 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 1832}
1833
1834
1835
f701dad2 1836000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
20ae0098 1837"dsrlv r<RD>, r<RT>, r<RS>"
c906108c
SS		 1838*mipsIII:
1839*mipsIV:
603a98e7 1840*mipsV:
1e799e28 1841*mips64:
e70cb6cd 1842*mips64r2:
c906108c
SS		 1843*vr4100:
1844*vr5000:
1845{
ca971540 1846 check_u64 (SD_, instruction_0);
c906108c
SS		 1847 do_dsrlv (SD_, RS, RT, RD);
1848}
1849
1850
f701dad2 1851000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
c906108c
SS		 1852"dsub r<RD>, r<RS>, r<RT>"
1853*mipsIII:
1854*mipsIV:
603a98e7 1855*mipsV:
1e799e28 1856*mips64:
e70cb6cd 1857*mips64r2:
c906108c
SS		 1858*vr4100:
1859*vr5000:
1860{
ca971540 1861 check_u64 (SD_, instruction_0);
c906108c
SS		 1862 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1863 {
1864 ALU64_BEGIN (GPR[RS]);
1865 ALU64_SUB (GPR[RT]);
9805e229 1866 ALU64_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 1867 }
1868 TRACE_ALU_RESULT (GPR[RD]);
1869}
1870
1871
1872:function:::void:do_dsubu:int rs, int rt, int rd
1873{
1874 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1875 GPR[rd] = GPR[rs] - GPR[rt];
1876 TRACE_ALU_RESULT (GPR[rd]);
1877}
1878
f701dad2 1879000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
c906108c
SS		 1880"dsubu r<RD>, r<RS>, r<RT>"
1881*mipsIII:
1882*mipsIV:
603a98e7 1883*mipsV:
1e799e28 1884*mips64:
e70cb6cd 1885*mips64r2:
c906108c
SS		 1886*vr4100:
1887*vr5000:
1888{
ca971540 1889 check_u64 (SD_, instruction_0);
c906108c
SS		 1890 do_dsubu (SD_, RS, RT, RD);
1891}
1892
1893
1894000010,26.INSTR_INDEX:NORMAL:32::J
1895"j <INSTR_INDEX>"
c5d00cc7
CD		 1896*mipsI:
1897*mipsII:
1898*mipsIII:
1899*mipsIV:
603a98e7 1900*mipsV:
1e799e28 1901*mips32:
e70cb6cd 1902*mips32r2:
1e799e28 1903*mips64:
e70cb6cd 1904*mips64r2:
c906108c
SS		 1905*vr4100:
1906*vr5000:
1907*r3900:
1908{
1909 /* NOTE: The region used is that of the delay slot NIA and NOT the
1910 current instruction */
1911 address_word region = (NIA & MASK (63, 28));
1912 DELAY_SLOT (region | (INSTR_INDEX << 2));
1913}
1914
1915
1916000011,26.INSTR_INDEX:NORMAL:32::JAL
1917"jal <INSTR_INDEX>"
c5d00cc7
CD		 1918*mipsI:
1919*mipsII:
1920*mipsIII:
1921*mipsIV:
603a98e7 1922*mipsV:
1e799e28 1923*mips32:
e70cb6cd 1924*mips32r2:
1e799e28 1925*mips64:
e70cb6cd 1926*mips64r2:
c906108c
SS		 1927*vr4100:
1928*vr5000:
1929*r3900:
1930{
1931 /* NOTE: The region used is that of the delay slot and NOT the
1932 current instruction */
1933 address_word region = (NIA & MASK (63, 28));
1934 GPR[31] = CIA + 8;
1935 DELAY_SLOT (region | (INSTR_INDEX << 2));
1936}
1937
f701dad2 1938000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
c906108c
SS		 1939"jalr r<RS>":RD == 31
1940"jalr r<RD>, r<RS>"
c5d00cc7
CD		 1941*mipsI:
1942*mipsII:
1943*mipsIII:
1944*mipsIV:
603a98e7 1945*mipsV:
1e799e28 1946*mips32:
e70cb6cd 1947*mips32r2:
1e799e28 1948*mips64:
e70cb6cd 1949*mips64r2:
c906108c
SS		 1950*vr4100:
1951*vr5000:
1952*r3900:
1953{
1954 address_word temp = GPR[RS];
1955 GPR[RD] = CIA + 8;
1956 DELAY_SLOT (temp);
1957}
1958
1959
f701dad2 1960000000,5.RS,000000000000000,001000:SPECIAL:32::JR
c906108c 1961"jr r<RS>"
c5d00cc7
CD		 1962*mipsI:
1963*mipsII:
1964*mipsIII:
1965*mipsIV:
603a98e7 1966*mipsV:
1e799e28 1967*mips32:
e70cb6cd 1968*mips32r2:
1e799e28 1969*mips64:
e70cb6cd 1970*mips64r2:
c906108c
SS		 1971*vr4100:
1972*vr5000:
1973*r3900:
1974{
1975 DELAY_SLOT (GPR[RS]);
1976}
1977
1978
1979:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1980{
1981 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1982 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1983 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1984 unsigned int byte;
1985 address_word paddr;
1986 int uncached;
1987 unsigned64 memval;
1988 address_word vaddr;
1989
09297648 1990 vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 1991 if ((vaddr & access) != 0)
1992 {
1993 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1994 }
1995 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1996 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1997 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1998 byte = ((vaddr & mask) ^ bigendiancpu);
1999 return (memval >> (8 * byte));
2000}
2001
1c47a468
CD		 2002:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2003{
2004 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2005 address_word reverseendian = (ReverseEndian ? -1 : 0);
2006 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2007 unsigned int byte;
2008 unsigned int word;
2009 address_word paddr;
2010 int uncached;
2011 unsigned64 memval;
2012 address_word vaddr;
2013 int nr_lhs_bits;
2014 int nr_rhs_bits;
2015 unsigned_word lhs_mask;
2016 unsigned_word temp;
2017
09297648 2018 vaddr = loadstore_ea (SD_, base, offset);
1c47a468
CD		 2019 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2020 paddr = (paddr ^ (reverseendian & mask));
2021 if (BigEndianMem == 0)
2022 paddr = paddr & ~access;
2023
2024 /* compute where within the word/mem we are */
2025 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2026 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2027 nr_lhs_bits = 8 * byte + 8;
2028 nr_rhs_bits = 8 * access - 8 * byte;
2029 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2030
2031 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2032 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2033 (long) ((unsigned64) paddr >> 32), (long) paddr,
2034 word, byte, nr_lhs_bits, nr_rhs_bits); */
2035
2036 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2037 if (word == 0)
2038 {
2039 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2040 temp = (memval << nr_rhs_bits);
2041 }
2042 else
2043 {
2044 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2045 temp = (memval >> nr_lhs_bits);
2046 }
2047 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2048 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2049
2050 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2051 (long) ((unsigned64) memval >> 32), (long) memval,
2052 (long) ((unsigned64) temp >> 32), (long) temp,
2053 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2054 (long) (rt >> 32), (long) rt); */
2055 return rt;
2056}
2057
2058:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2059{
2060 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2061 address_word reverseendian = (ReverseEndian ? -1 : 0);
2062 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2063 unsigned int byte;
2064 address_word paddr;
2065 int uncached;
2066 unsigned64 memval;
2067 address_word vaddr;
2068
09297648 2069 vaddr = loadstore_ea (SD_, base, offset);
1c47a468
CD		 2070 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2071 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2072 paddr = (paddr ^ (reverseendian & mask));
2073 if (BigEndianMem != 0)
2074 paddr = paddr & ~access;
2075 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2076 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
2077 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2078 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2079 (long) paddr, byte, (long) paddr, (long) memval); */
2080 {
2081 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2082 rt &= ~screen;
2083 rt |= (memval >> (8 * byte)) & screen;
2084 }
2085 return rt;
2086}
2087
c906108c
SS		 2088
2089100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
2090"lb r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2091*mipsI:
2092*mipsII:
2093*mipsIII:
2094*mipsIV:
603a98e7 2095*mipsV:
1e799e28 2096*mips32:
e70cb6cd 2097*mips32r2:
1e799e28 2098*mips64:
e70cb6cd 2099*mips64r2:
c906108c
SS		 2100*vr4100:
2101*vr5000:
2102*r3900:
2103{
2104 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
2105}
2106
2107
2108100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2109"lbu r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2110*mipsI:
2111*mipsII:
2112*mipsIII:
2113*mipsIV:
603a98e7 2114*mipsV:
1e799e28 2115*mips32:
e70cb6cd 2116*mips32r2:
1e799e28 2117*mips64:
e70cb6cd 2118*mips64r2:
c906108c
SS		 2119*vr4100:
2120*vr5000:
2121*r3900:
2122{
2123 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
2124}
2125
2126
2127110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2128"ld r<RT>, <OFFSET>(r<BASE>)"
2129*mipsIII:
2130*mipsIV:
603a98e7 2131*mipsV:
1e799e28 2132*mips64:
e70cb6cd 2133*mips64r2:
c906108c
SS		 2134*vr4100:
2135*vr5000:
2136{
ca971540 2137 check_u64 (SD_, instruction_0);
c906108c
SS		 2138 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2139}
2140
2141
21421101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
2143"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2144*mipsII:
2145*mipsIII:
2146*mipsIV:
603a98e7 2147*mipsV:
1e799e28 2148*mips32:
e70cb6cd 2149*mips32r2:
1e799e28 2150*mips64:
e70cb6cd 2151*mips64r2:
c906108c
SS		 2152*vr4100:
2153*vr5000:
2154*r3900:
2155{
2156 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2157}
2158
2159
2160
2161
2162011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2163"ldl r<RT>, <OFFSET>(r<BASE>)"
2164*mipsIII:
2165*mipsIV:
603a98e7 2166*mipsV:
1e799e28 2167*mips64:
e70cb6cd 2168*mips64r2:
c906108c
SS		 2169*vr4100:
2170*vr5000:
2171{
ca971540 2172 check_u64 (SD_, instruction_0);
c906108c
SS		 2173 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2174}
2175
2176
2177011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2178"ldr r<RT>, <OFFSET>(r<BASE>)"
2179*mipsIII:
2180*mipsIV:
603a98e7 2181*mipsV:
1e799e28 2182*mips64:
e70cb6cd 2183*mips64r2:
c906108c
SS		 2184*vr4100:
2185*vr5000:
2186{
ca971540 2187 check_u64 (SD_, instruction_0);
c906108c
SS		 2188 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2189}
2190
2191
2192100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2193"lh r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2194*mipsI:
2195*mipsII:
2196*mipsIII:
2197*mipsIV:
603a98e7 2198*mipsV:
1e799e28 2199*mips32:
e70cb6cd 2200*mips32r2:
1e799e28 2201*mips64:
e70cb6cd 2202*mips64r2:
c906108c
SS		 2203*vr4100:
2204*vr5000:
2205*r3900:
2206{
2207 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2208}
2209
2210
2211100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2212"lhu r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2213*mipsI:
2214*mipsII:
2215*mipsIII:
2216*mipsIV:
603a98e7 2217*mipsV:
1e799e28 2218*mips32:
e70cb6cd 2219*mips32r2:
1e799e28 2220*mips64:
e70cb6cd 2221*mips64r2:
c906108c
SS		 2222*vr4100:
2223*vr5000:
2224*r3900:
2225{
2226 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2227}
2228
2229
2230110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2231"ll r<RT>, <OFFSET>(r<BASE>)"
2232*mipsII:
2233*mipsIII:
2234*mipsIV:
603a98e7 2235*mipsV:
1e799e28 2236*mips32:
e70cb6cd 2237*mips32r2:
1e799e28 2238*mips64:
e70cb6cd 2239*mips64r2:
c906108c
SS		 2240*vr4100:
2241*vr5000:
2242{
c1e8ada4
CD		 2243 address_word base = GPR[BASE];
2244 address_word offset = EXTEND16 (OFFSET);
c906108c 2245 {
09297648 2246 address_word vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 2247 address_word paddr;
2248 int uncached;
2249 if ((vaddr & 3) != 0)
2250 {
2251 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2252 }
2253 else
2254 {
2255 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2256 {
2257 unsigned64 memval = 0;
2258 unsigned64 memval1 = 0;
2259 unsigned64 mask = 0x7;
2260 unsigned int shift = 2;
2261 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2262 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2263 unsigned int byte;
2264 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2265 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2266 byte = ((vaddr & mask) ^ (bigend << shift));
043b7057 2267 GPR[RT] = EXTEND32 (memval >> (8 * byte));
c906108c
SS		 2268 LLBIT = 1;
2269 }
2270 }
2271 }
2272}
2273
2274
2275110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2276"lld r<RT>, <OFFSET>(r<BASE>)"
2277*mipsIII:
2278*mipsIV:
603a98e7 2279*mipsV:
1e799e28 2280*mips64:
e70cb6cd 2281*mips64r2:
c906108c
SS		 2282*vr4100:
2283*vr5000:
2284{
c1e8ada4
CD		 2285 address_word base = GPR[BASE];
2286 address_word offset = EXTEND16 (OFFSET);
ca971540 2287 check_u64 (SD_, instruction_0);
c906108c 2288 {
09297648 2289 address_word vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 2290 address_word paddr;
2291 int uncached;
2292 if ((vaddr & 7) != 0)
2293 {
2294 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2295 }
2296 else
2297 {
2298 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2299 {
2300 unsigned64 memval = 0;
2301 unsigned64 memval1 = 0;
2302 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
c1e8ada4 2303 GPR[RT] = memval;
c906108c
SS		 2304 LLBIT = 1;
2305 }
2306 }
2307 }
2308}
2309
2310
2311001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
82f728db 2312"lui r<RT>, %#lx<IMMEDIATE>"
c5d00cc7
CD		 2313*mipsI:
2314*mipsII:
2315*mipsIII:
2316*mipsIV:
603a98e7 2317*mipsV:
1e799e28 2318*mips32:
e70cb6cd 2319*mips32r2:
1e799e28 2320*mips64:
e70cb6cd 2321*mips64r2:
c906108c
SS		 2322*vr4100:
2323*vr5000:
2324*r3900:
2325{
2326 TRACE_ALU_INPUT1 (IMMEDIATE);
2327 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2328 TRACE_ALU_RESULT (GPR[RT]);
2329}
2330
2331
2332100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2333"lw r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2334*mipsI:
2335*mipsII:
2336*mipsIII:
2337*mipsIV:
603a98e7 2338*mipsV:
1e799e28 2339*mips32:
e70cb6cd 2340*mips32r2:
1e799e28 2341*mips64:
e70cb6cd 2342*mips64r2:
c906108c
SS		 2343*vr4100:
2344*vr5000:
2345*r3900:
2346{
2347 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2348}
2349
2350
23511100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2352"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2353*mipsI:
2354*mipsII:
2355*mipsIII:
2356*mipsIV:
603a98e7 2357*mipsV:
1e799e28 2358*mips32:
e70cb6cd 2359*mips32r2:
1e799e28 2360*mips64:
e70cb6cd 2361*mips64r2:
c906108c
SS		 2362*vr4100:
2363*vr5000:
2364*r3900:
2365{
2366 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2367}
2368
2369
c906108c
SS		 2370100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2371"lwl r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2372*mipsI:
2373*mipsII:
2374*mipsIII:
2375*mipsIV:
603a98e7 2376*mipsV:
1e799e28 2377*mips32:
e70cb6cd 2378*mips32r2:
1e799e28 2379*mips64:
e70cb6cd 2380*mips64r2:
c906108c
SS		 2381*vr4100:
2382*vr5000:
2383*r3900:
2384{
7a292a7a 2385 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
c906108c
SS		 2386}
2387
2388
c906108c
SS		 2389100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2390"lwr r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2391*mipsI:
2392*mipsII:
2393*mipsIII:
2394*mipsIV:
603a98e7 2395*mipsV:
1e799e28 2396*mips32:
e70cb6cd 2397*mips32r2:
1e799e28 2398*mips64:
e70cb6cd 2399*mips64r2:
c906108c
SS		 2400*vr4100:
2401*vr5000:
2402*r3900:
2403{
2404 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2405}
2406
2407
bb22bd7d 2408100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
c906108c
SS		 2409"lwu r<RT>, <OFFSET>(r<BASE>)"
2410*mipsIII:
2411*mipsIV:
603a98e7 2412*mipsV:
1e799e28 2413*mips64:
e70cb6cd 2414*mips64r2:
c906108c
SS		 2415*vr4100:
2416*vr5000:
2417{
ca971540 2418 check_u64 (SD_, instruction_0);
c906108c
SS		 2419 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2420}
2421
2422
1e799e28
CD		 2423
2424011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2425"madd r<RS>, r<RT>"
2426*mips32:
e70cb6cd 2427*mips32r2:
1e799e28 2428*mips64:
e70cb6cd 2429*mips64r2:
4c54fc26 2430*vr5500:
1e799e28
CD		 2431{
2432 signed64 temp;
2433 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
402586aa
CD		 2434 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2435 Unpredictable ();
1e799e28
CD		 2436 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2437 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2438 + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2439 LO = EXTEND32 (temp);
2440 HI = EXTEND32 (VH4_8 (temp));
2441 TRACE_ALU_RESULT2 (HI, LO);
2442}
2443
2444
2445
2446011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2447"maddu r<RS>, r<RT>"
2448*mips32:
e70cb6cd 2449*mips32r2:
1e799e28 2450*mips64:
e70cb6cd 2451*mips64r2:
4c54fc26 2452*vr5500:
1e799e28
CD		 2453{
2454 unsigned64 temp;
2455 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
402586aa
CD		 2456 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2457 Unpredictable ();
1e799e28
CD		 2458 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2459 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2460 + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2d2733fc 2461 ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
1e799e28
CD		 2462 LO = EXTEND32 (temp);
2463 HI = EXTEND32 (VH4_8 (temp));
2464 TRACE_ALU_RESULT2 (HI, LO);
2465}
2466
2467
c906108c
SS		 2468:function:::void:do_mfhi:int rd
2469{
2470 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2471 TRACE_ALU_INPUT1 (HI);
2472 GPR[rd] = HI;
2473 TRACE_ALU_RESULT (GPR[rd]);
2474}
2475
2476000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2477"mfhi r<RD>"
c5d00cc7
CD		 2478*mipsI:
2479*mipsII:
2480*mipsIII:
2481*mipsIV:
603a98e7 2482*mipsV:
c906108c
SS		 2483*vr4100:
2484*vr5000:
2485*r3900:
2486{
2487 do_mfhi (SD_, RD);
2488}
2489
2490
2491
2492:function:::void:do_mflo:int rd
2493{
2494 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2495 TRACE_ALU_INPUT1 (LO);
2496 GPR[rd] = LO;
2497 TRACE_ALU_RESULT (GPR[rd]);
2498}
2499
2500000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2501"mflo r<RD>"
c5d00cc7
CD		 2502*mipsI:
2503*mipsII:
2504*mipsIII:
2505*mipsIV:
603a98e7 2506*mipsV:
c906108c
SS		 2507*vr4100:
2508*vr5000:
2509*r3900:
2510{
2511 do_mflo (SD_, RD);
2512}
2513
2514
2515
f701dad2 2516000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
c906108c
SS		 2517"movn r<RD>, r<RS>, r<RT>"
2518*mipsIV:
603a98e7 2519*mipsV:
1e799e28 2520*mips32:
e70cb6cd 2521*mips32r2:
1e799e28 2522*mips64:
e70cb6cd 2523*mips64r2:
c906108c
SS		 2524*vr5000:
2525{
2526 if (GPR[RT] != 0)
95fd5cee
CD		 2527 {
2528 GPR[RD] = GPR[RS];
2529 TRACE_ALU_RESULT (GPR[RD]);
2530 }
c906108c
SS		 2531}
2532
2533
2534
f701dad2 2535000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
c906108c
SS		 2536"movz r<RD>, r<RS>, r<RT>"
2537*mipsIV:
603a98e7 2538*mipsV:
1e799e28 2539*mips32:
e70cb6cd 2540*mips32r2:
1e799e28 2541*mips64:
e70cb6cd 2542*mips64r2:
c906108c
SS		 2543*vr5000:
2544{
2545 if (GPR[RT] == 0)
95fd5cee
CD		 2546 {
2547 GPR[RD] = GPR[RS];
2548 TRACE_ALU_RESULT (GPR[RD]);
2549 }
c906108c
SS		 2550}
2551
2552
2553
1e799e28
CD		 2554011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2555"msub r<RS>, r<RT>"
2556*mips32:
e70cb6cd 2557*mips32r2:
1e799e28 2558*mips64:
e70cb6cd 2559*mips64r2:
4c54fc26 2560*vr5500:
1e799e28
CD		 2561{
2562 signed64 temp;
2563 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
402586aa
CD		 2564 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2565 Unpredictable ();
1e799e28
CD		 2566 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2567 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2568 - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2569 LO = EXTEND32 (temp);
2570 HI = EXTEND32 (VH4_8 (temp));
2571 TRACE_ALU_RESULT2 (HI, LO);
2572}
2573
2574
2575
2576011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2577"msubu r<RS>, r<RT>"
2578*mips32:
e70cb6cd 2579*mips32r2:
1e799e28 2580*mips64:
e70cb6cd 2581*mips64r2:
4c54fc26 2582*vr5500:
1e799e28
CD		 2583{
2584 unsigned64 temp;
2585 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
402586aa
CD		 2586 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2587 Unpredictable ();
1e799e28
CD		 2588 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2589 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2590 - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2591 LO = EXTEND32 (temp);
2592 HI = EXTEND32 (VH4_8 (temp));
2593 TRACE_ALU_RESULT2 (HI, LO);
2594}
2595
2596
2597
c906108c
SS		 2598000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2599"mthi r<RS>"
c5d00cc7
CD		 2600*mipsI:
2601*mipsII:
2602*mipsIII:
2603*mipsIV:
603a98e7 2604*mipsV:
c906108c
SS		 2605*vr4100:
2606*vr5000:
2607*r3900:
2608{
2609 check_mt_hilo (SD_, HIHISTORY);
2610 HI = GPR[RS];
2611}
2612
2613
2614
f701dad2 2615000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
c906108c 2616"mtlo r<RS>"
c5d00cc7
CD		 2617*mipsI:
2618*mipsII:
2619*mipsIII:
2620*mipsIV:
603a98e7 2621*mipsV:
c906108c
SS		 2622*vr4100:
2623*vr5000:
2624*r3900:
2625{
2626 check_mt_hilo (SD_, LOHISTORY);
2627 LO = GPR[RS];
2628}
2629
2630
2631
1e799e28
CD		 2632011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2633"mul r<RD>, r<RS>, r<RT>"
2634*mips32:
e70cb6cd 2635*mips32r2:
1e799e28 2636*mips64:
e70cb6cd 2637*mips64r2:
4c54fc26 2638*vr5500:
1e799e28
CD		 2639{
2640 signed64 prod;
402586aa
CD		 2641 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2642 Unpredictable ();
1e799e28
CD		 2643 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2644 prod = (((signed64)(signed32) GPR[RS])
2645 * ((signed64)(signed32) GPR[RT]));
2646 GPR[RD] = EXTEND32 (VL4_8 (prod));
2647 TRACE_ALU_RESULT (GPR[RD]);
2648}
2649
2650
2651
c906108c
SS		 2652:function:::void:do_mult:int rs, int rt, int rd
2653{
2654 signed64 prod;
2655 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
402586aa
CD		 2656 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2657 Unpredictable ();
c906108c
SS		 2658 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2659 prod = (((signed64)(signed32) GPR[rs])
2660 * ((signed64)(signed32) GPR[rt]));
2661 LO = EXTEND32 (VL4_8 (prod));
2662 HI = EXTEND32 (VH4_8 (prod));
2d2733fc 2663 ACX = 0; /* SmartMIPS */
c906108c
SS		 2664 if (rd != 0)
2665 GPR[rd] = LO;
2666 TRACE_ALU_RESULT2 (HI, LO);
2667}
2668
f701dad2 2669000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
c906108c 2670"mult r<RS>, r<RT>"
c5d00cc7
CD		 2671*mipsI:
2672*mipsII:
2673*mipsIII:
2674*mipsIV:
603a98e7 2675*mipsV:
1e799e28 2676*mips32:
e70cb6cd 2677*mips32r2:
1e799e28 2678*mips64:
e70cb6cd 2679*mips64r2:
c906108c
SS		 2680*vr4100:
2681{
2682 do_mult (SD_, RS, RT, 0);
2683}
2684
2685
f701dad2 2686000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
9846de1b 2687"mult r<RS>, r<RT>":RD == 0
c906108c
SS		 2688"mult r<RD>, r<RS>, r<RT>"
2689*vr5000:
2690*r3900:
2691{
2692 do_mult (SD_, RS, RT, RD);
2693}
2694
2695
2696:function:::void:do_multu:int rs, int rt, int rd
2697{
2698 unsigned64 prod;
2699 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
402586aa
CD		 2700 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2701 Unpredictable ();
c906108c
SS		 2702 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2703 prod = (((unsigned64)(unsigned32) GPR[rs])
2704 * ((unsigned64)(unsigned32) GPR[rt]));
2705 LO = EXTEND32 (VL4_8 (prod));
2706 HI = EXTEND32 (VH4_8 (prod));
2707 if (rd != 0)
2708 GPR[rd] = LO;
2709 TRACE_ALU_RESULT2 (HI, LO);
2710}
2711
f701dad2 2712000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
c906108c 2713"multu r<RS>, r<RT>"
c5d00cc7
CD		 2714*mipsI:
2715*mipsII:
2716*mipsIII:
2717*mipsIV:
603a98e7 2718*mipsV:
1e799e28 2719*mips32:
e70cb6cd 2720*mips32r2:
1e799e28 2721*mips64:
e70cb6cd 2722*mips64r2:
c906108c
SS		 2723*vr4100:
2724{
cff3e48b 2725 do_multu (SD_, RS, RT, 0);
c906108c
SS		 2726}
2727
f701dad2 2728000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
9846de1b 2729"multu r<RS>, r<RT>":RD == 0
c906108c
SS		 2730"multu r<RD>, r<RS>, r<RT>"
2731*vr5000:
2732*r3900:
2733{
cff3e48b 2734 do_multu (SD_, RS, RT, RD);
c906108c
SS		 2735}
2736
2737
2738:function:::void:do_nor:int rs, int rt, int rd
2739{
2740 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2741 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2742 TRACE_ALU_RESULT (GPR[rd]);
2743}
2744
2745000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2746"nor r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 2747*mipsI:
2748*mipsII:
2749*mipsIII:
2750*mipsIV:
603a98e7 2751*mipsV:
1e799e28 2752*mips32:
e70cb6cd 2753*mips32r2:
1e799e28 2754*mips64:
e70cb6cd 2755*mips64r2:
c906108c
SS		 2756*vr4100:
2757*vr5000:
2758*r3900:
2759{
2760 do_nor (SD_, RS, RT, RD);
2761}
2762
2763
2764:function:::void:do_or:int rs, int rt, int rd
2765{
2766 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2767 GPR[rd] = (GPR[rs] | GPR[rt]);
2768 TRACE_ALU_RESULT (GPR[rd]);
2769}
2770
2771000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2772"or r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 2773*mipsI:
2774*mipsII:
2775*mipsIII:
2776*mipsIV:
603a98e7 2777*mipsV:
1e799e28 2778*mips32:
e70cb6cd 2779*mips32r2:
1e799e28 2780*mips64:
e70cb6cd 2781*mips64r2:
c906108c
SS		 2782*vr4100:
2783*vr5000:
2784*r3900:
2785{
2786 do_or (SD_, RS, RT, RD);
2787}
2788
2789
2790
2791:function:::void:do_ori:int rs, int rt, unsigned immediate
2792{
2793 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2794 GPR[rt] = (GPR[rs] | immediate);
2795 TRACE_ALU_RESULT (GPR[rt]);
2796}
2797
2798001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
82f728db 2799"ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
c5d00cc7
CD		 2800*mipsI:
2801*mipsII:
2802*mipsIII:
2803*mipsIV:
603a98e7 2804*mipsV:
1e799e28 2805*mips32:
e70cb6cd 2806*mips32r2:
1e799e28 2807*mips64:
e70cb6cd 2808*mips64r2:
c906108c
SS		 2809*vr4100:
2810*vr5000:
2811*r3900:
2812{
2813 do_ori (SD_, RS, RT, IMMEDIATE);
2814}
2815
2816
af5107af
CD		 2817110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2818"pref <HINT>, <OFFSET>(r<BASE>)"
c906108c 2819*mipsIV:
603a98e7 2820*mipsV:
1e799e28 2821*mips32:
e70cb6cd 2822*mips32r2:
1e799e28 2823*mips64:
e70cb6cd 2824*mips64r2:
c906108c
SS		 2825*vr5000:
2826{
c1e8ada4
CD		 2827 address_word base = GPR[BASE];
2828 address_word offset = EXTEND16 (OFFSET);
c906108c 2829 {
09297648 2830 address_word vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 2831 address_word paddr;
2832 int uncached;
2833 {
2834 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
c1e8ada4 2835 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
c906108c
SS		 2836 }
2837 }
2838}
2839
1c47a468 2840
e70cb6cd
CD		 2841:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
2842{
2843 unsigned64 result;
2844
2845 y &= 31;
2846 TRACE_ALU_INPUT2 (x, y);
2847 result = EXTEND32 (ROTR32 (x, y));
2848 TRACE_ALU_RESULT (result);
2849 return result;
2850}
2851
2852000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
2853"ror r<RD>, r<RT>, <SHIFT>"
2854*mips32r2:
2855*mips64r2:
2d2733fc 2856*smartmips:
e70cb6cd
CD		 2857*vr5400:
2858*vr5500:
2859{
2860 GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
2861}
2862
2863000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
2864"rorv r<RD>, r<RT>, r<RS>"
2865*mips32r2:
2866*mips64r2:
2d2733fc 2867*smartmips:
e70cb6cd
CD		 2868*vr5400:
2869*vr5500:
2870{
2871 GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
2872}
2873
2874
c906108c
SS		 2875:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2876{
2877 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2878 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2879 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2880 unsigned int byte;
2881 address_word paddr;
2882 int uncached;
2883 unsigned64 memval;
2884 address_word vaddr;
2885
09297648 2886 vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 2887 if ((vaddr & access) != 0)
2888 {
2889 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2890 }
2891 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2892 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2893 byte = ((vaddr & mask) ^ bigendiancpu);
2894 memval = (word << (8 * byte));
2895 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2896}
2897
1c47a468
CD		 2898:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2899{
2900 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2901 address_word reverseendian = (ReverseEndian ? -1 : 0);
2902 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2903 unsigned int byte;
2904 unsigned int word;
2905 address_word paddr;
2906 int uncached;
2907 unsigned64 memval;
2908 address_word vaddr;
2909 int nr_lhs_bits;
2910 int nr_rhs_bits;
2911
09297648 2912 vaddr = loadstore_ea (SD_, base, offset);
1c47a468
CD		 2913 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2914 paddr = (paddr ^ (reverseendian & mask));
2915 if (BigEndianMem == 0)
2916 paddr = paddr & ~access;
2917
2918 /* compute where within the word/mem we are */
2919 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2920 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2921 nr_lhs_bits = 8 * byte + 8;
2922 nr_rhs_bits = 8 * access - 8 * byte;
2923 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2924 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2925 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2926 (long) ((unsigned64) paddr >> 32), (long) paddr,
2927 word, byte, nr_lhs_bits, nr_rhs_bits); */
2928
2929 if (word == 0)
2930 {
2931 memval = (rt >> nr_rhs_bits);
2932 }
2933 else
2934 {
2935 memval = (rt << nr_lhs_bits);
2936 }
2937 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2938 (long) ((unsigned64) rt >> 32), (long) rt,
2939 (long) ((unsigned64) memval >> 32), (long) memval); */
2940 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2941}
2942
2943:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2944{
2945 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2946 address_word reverseendian = (ReverseEndian ? -1 : 0);
2947 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2948 unsigned int byte;
2949 address_word paddr;
2950 int uncached;
2951 unsigned64 memval;
2952 address_word vaddr;
2953
09297648 2954 vaddr = loadstore_ea (SD_, base, offset);
1c47a468
CD		 2955 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2956 paddr = (paddr ^ (reverseendian & mask));
2957 if (BigEndianMem != 0)
2958 paddr &= ~access;
2959 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2960 memval = (rt << (byte * 8));
2961 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2962}
2963
c906108c
SS		 2964
2965101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2966"sb r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2967*mipsI:
2968*mipsII:
2969*mipsIII:
2970*mipsIV:
603a98e7 2971*mipsV:
1e799e28 2972*mips32:
e70cb6cd 2973*mips32r2:
1e799e28 2974*mips64:
e70cb6cd 2975*mips64r2:
c906108c
SS		 2976*vr4100:
2977*vr5000:
2978*r3900:
2979{
2980 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2981}
2982
2983
2984111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2985"sc r<RT>, <OFFSET>(r<BASE>)"
2986*mipsII:
2987*mipsIII:
2988*mipsIV:
603a98e7 2989*mipsV:
1e799e28 2990*mips32:
e70cb6cd 2991*mips32r2:
1e799e28 2992*mips64:
e70cb6cd 2993*mips64r2:
c906108c
SS		 2994*vr4100:
2995*vr5000:
2996{
2997 unsigned32 instruction = instruction_0;
c1e8ada4
CD		 2998 address_word base = GPR[BASE];
2999 address_word offset = EXTEND16 (OFFSET);
c906108c 3000 {
09297648 3001 address_word vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 3002 address_word paddr;
3003 int uncached;
3004 if ((vaddr & 3) != 0)
3005 {
3006 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
3007 }
3008 else
3009 {
3010 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3011 {
3012 unsigned64 memval = 0;
3013 unsigned64 memval1 = 0;
3014 unsigned64 mask = 0x7;
3015 unsigned int byte;
3016 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3017 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
c1e8ada4 3018 memval = ((unsigned64) GPR[RT] << (8 * byte));
c906108c
SS		 3019 if (LLBIT)
3020 {
3021 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3022 }
c1e8ada4 3023 GPR[RT] = LLBIT;
c906108c
SS		 3024 }
3025 }
3026 }
3027}
3028
3029
3030111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
3031"scd r<RT>, <OFFSET>(r<BASE>)"
3032*mipsIII:
3033*mipsIV:
603a98e7 3034*mipsV:
1e799e28 3035*mips64:
e70cb6cd 3036*mips64r2:
c906108c
SS		 3037*vr4100:
3038*vr5000:
3039{
c1e8ada4
CD		 3040 address_word base = GPR[BASE];
3041 address_word offset = EXTEND16 (OFFSET);
ca971540 3042 check_u64 (SD_, instruction_0);
c906108c 3043 {
09297648 3044 address_word vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 3045 address_word paddr;
3046 int uncached;
3047 if ((vaddr & 7) != 0)
3048 {
3049 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
3050 }
3051 else
3052 {
3053 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3054 {
3055 unsigned64 memval = 0;
3056 unsigned64 memval1 = 0;
c1e8ada4 3057 memval = GPR[RT];
c906108c
SS		 3058 if (LLBIT)
3059 {
3060 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
3061 }
c1e8ada4 3062 GPR[RT] = LLBIT;
c906108c
SS		 3063 }
3064 }
3065 }
3066}
3067
3068
3069111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
3070"sd r<RT>, <OFFSET>(r<BASE>)"
3071*mipsIII:
3072*mipsIV:
603a98e7 3073*mipsV:
1e799e28 3074*mips64:
e70cb6cd 3075*mips64r2:
c906108c
SS		 3076*vr4100:
3077*vr5000:
3078{
ca971540 3079 check_u64 (SD_, instruction_0);
c906108c
SS		 3080 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3081}
3082
3083
30841111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3085"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3086*mipsII:
3087*mipsIII:
3088*mipsIV:
603a98e7 3089*mipsV:
1e799e28 3090*mips32:
e70cb6cd 3091*mips32r2:
1e799e28 3092*mips64:
e70cb6cd 3093*mips64r2:
c906108c
SS		 3094*vr4100:
3095*vr5000:
3096{
3097 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3098}
3099
3100
3101101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3102"sdl r<RT>, <OFFSET>(r<BASE>)"
3103*mipsIII:
3104*mipsIV:
603a98e7 3105*mipsV:
1e799e28 3106*mips64:
e70cb6cd 3107*mips64r2:
c906108c
SS		 3108*vr4100:
3109*vr5000:
3110{
ca971540 3111 check_u64 (SD_, instruction_0);
c906108c
SS		 3112 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3113}
3114
3115
3116101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3117"sdr r<RT>, <OFFSET>(r<BASE>)"
3118*mipsIII:
3119*mipsIV:
603a98e7 3120*mipsV:
1e799e28 3121*mips64:
e70cb6cd 3122*mips64r2:
c906108c
SS		 3123*vr4100:
3124*vr5000:
3125{
ca971540 3126 check_u64 (SD_, instruction_0);
c906108c
SS		 3127 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3128}
3129
3130
e70cb6cd 3131
c906108c
SS		 3132101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3133"sh r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3134*mipsI:
3135*mipsII:
3136*mipsIII:
3137*mipsIV:
603a98e7 3138*mipsV:
1e799e28 3139*mips32:
e70cb6cd 3140*mips32r2:
1e799e28 3141*mips64:
e70cb6cd 3142*mips64r2:
c906108c
SS		 3143*vr4100:
3144*vr5000:
3145*r3900:
3146{
3147 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3148}
3149
3150
3151:function:::void:do_sll:int rt, int rd, int shift
3152{
3153 unsigned32 temp = (GPR[rt] << shift);
3154 TRACE_ALU_INPUT2 (GPR[rt], shift);
3155 GPR[rd] = EXTEND32 (temp);
3156 TRACE_ALU_RESULT (GPR[rd]);
3157}
3158
1e799e28 3159000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
20ae0098 3160"nop":RD == 0 && RT == 0 && SHIFT == 0
c906108c 3161"sll r<RD>, r<RT>, <SHIFT>"
c5d00cc7
CD		 3162*mipsI:
3163*mipsII:
3164*mipsIII:
3165*mipsIV:
603a98e7 3166*mipsV:
c906108c
SS		 3167*vr4100:
3168*vr5000:
3169*r3900:
3170{
20ae0098
CD		 3171 /* Skip shift for NOP, so that there won't be lots of extraneous
3172 trace output. */
3173 if (RD != 0 || RT != 0 || SHIFT != 0)
3174 do_sll (SD_, RT, RD, SHIFT);
c906108c
SS		 3175}
3176
1e799e28
CD		 3177000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
3178"nop":RD == 0 && RT == 0 && SHIFT == 0
3179"ssnop":RD == 0 && RT == 0 && SHIFT == 1
3180"sll r<RD>, r<RT>, <SHIFT>"
3181*mips32:
e70cb6cd 3182*mips32r2:
1e799e28 3183*mips64:
e70cb6cd 3184*mips64r2:
1e799e28
CD		 3185{
3186 /* Skip shift for NOP and SSNOP, so that there won't be lots of
3187 extraneous trace output. */
3188 if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
3189 do_sll (SD_, RT, RD, SHIFT);
3190}
3191
c906108c
SS		 3192
3193:function:::void:do_sllv:int rs, int rt, int rd
3194{
3195 int s = MASKED (GPR[rs], 4, 0);
3196 unsigned32 temp = (GPR[rt] << s);
3197 TRACE_ALU_INPUT2 (GPR[rt], s);
3198 GPR[rd] = EXTEND32 (temp);
3199 TRACE_ALU_RESULT (GPR[rd]);
3200}
3201
f701dad2 3202000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
c906108c 3203"sllv r<RD>, r<RT>, r<RS>"
c5d00cc7
CD		 3204*mipsI:
3205*mipsII:
3206*mipsIII:
3207*mipsIV:
603a98e7 3208*mipsV:
1e799e28 3209*mips32:
e70cb6cd 3210*mips32r2:
1e799e28 3211*mips64:
e70cb6cd 3212*mips64r2:
c906108c
SS		 3213*vr4100:
3214*vr5000:
3215*r3900:
3216{
3217 do_sllv (SD_, RS, RT, RD);
3218}
3219
3220
3221:function:::void:do_slt:int rs, int rt, int rd
3222{
3223 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3224 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3225 TRACE_ALU_RESULT (GPR[rd]);
3226}
3227
f701dad2 3228000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
c906108c 3229"slt r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 3230*mipsI:
3231*mipsII:
3232*mipsIII:
3233*mipsIV:
603a98e7 3234*mipsV:
1e799e28 3235*mips32:
e70cb6cd 3236*mips32r2:
1e799e28 3237*mips64:
e70cb6cd 3238*mips64r2:
c906108c
SS		 3239*vr4100:
3240*vr5000:
3241*r3900:
3242{
3243 do_slt (SD_, RS, RT, RD);
3244}
3245
3246
3247:function:::void:do_slti:int rs, int rt, unsigned16 immediate
3248{
3249 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3250 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3251 TRACE_ALU_RESULT (GPR[rt]);
3252}
3253
3254001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3255"slti r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 3256*mipsI:
3257*mipsII:
3258*mipsIII:
3259*mipsIV:
603a98e7 3260*mipsV:
1e799e28 3261*mips32:
e70cb6cd 3262*mips32r2:
1e799e28 3263*mips64:
e70cb6cd 3264*mips64r2:
c906108c
SS		 3265*vr4100:
3266*vr5000:
3267*r3900:
3268{
3269 do_slti (SD_, RS, RT, IMMEDIATE);
3270}
3271
3272
3273:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3274{
3275 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3276 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3277 TRACE_ALU_RESULT (GPR[rt]);
3278}
3279
3280001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3281"sltiu r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 3282*mipsI:
3283*mipsII:
3284*mipsIII:
3285*mipsIV:
603a98e7 3286*mipsV:
1e799e28 3287*mips32:
e70cb6cd 3288*mips32r2:
1e799e28 3289*mips64:
e70cb6cd 3290*mips64r2:
c906108c
SS		 3291*vr4100:
3292*vr5000:
3293*r3900:
3294{
3295 do_sltiu (SD_, RS, RT, IMMEDIATE);
3296}
3297
3298
3299
3300:function:::void:do_sltu:int rs, int rt, int rd
3301{
3302 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3303 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3304 TRACE_ALU_RESULT (GPR[rd]);
3305}
3306
f701dad2 3307000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
c906108c 3308"sltu r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 3309*mipsI:
3310*mipsII:
3311*mipsIII:
3312*mipsIV:
603a98e7 3313*mipsV:
1e799e28 3314*mips32:
e70cb6cd 3315*mips32r2:
1e799e28 3316*mips64:
e70cb6cd 3317*mips64r2:
c906108c
SS		 3318*vr4100:
3319*vr5000:
3320*r3900:
3321{
3322 do_sltu (SD_, RS, RT, RD);
3323}
3324
3325
3326:function:::void:do_sra:int rt, int rd, int shift
3327{
3328 signed32 temp = (signed32) GPR[rt] >> shift;
402586aa
CD		 3329 if (NotWordValue (GPR[rt]))
3330 Unpredictable ();
c906108c
SS		 3331 TRACE_ALU_INPUT2 (GPR[rt], shift);
3332 GPR[rd] = EXTEND32 (temp);
3333 TRACE_ALU_RESULT (GPR[rd]);
3334}
3335
3336000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3337"sra r<RD>, r<RT>, <SHIFT>"
c5d00cc7
CD		 3338*mipsI:
3339*mipsII:
3340*mipsIII:
3341*mipsIV:
603a98e7 3342*mipsV:
1e799e28 3343*mips32:
e70cb6cd 3344*mips32r2:
1e799e28 3345*mips64:
e70cb6cd 3346*mips64r2:
c906108c
SS		 3347*vr4100:
3348*vr5000:
3349*r3900:
3350{
3351 do_sra (SD_, RT, RD, SHIFT);
3352}
3353
3354
3355
3356:function:::void:do_srav:int rs, int rt, int rd
3357{
3358 int s = MASKED (GPR[rs], 4, 0);
3359 signed32 temp = (signed32) GPR[rt] >> s;
402586aa
CD		 3360 if (NotWordValue (GPR[rt]))
3361 Unpredictable ();
c906108c
SS		 3362 TRACE_ALU_INPUT2 (GPR[rt], s);
3363 GPR[rd] = EXTEND32 (temp);
3364 TRACE_ALU_RESULT (GPR[rd]);
3365}
3366
f701dad2 3367000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
c906108c 3368"srav r<RD>, r<RT>, r<RS>"
c5d00cc7
CD		 3369*mipsI:
3370*mipsII:
3371*mipsIII:
3372*mipsIV:
603a98e7 3373*mipsV:
1e799e28 3374*mips32:
e70cb6cd 3375*mips32r2:
1e799e28 3376*mips64:
e70cb6cd 3377*mips64r2:
c906108c
SS		 3378*vr4100:
3379*vr5000:
3380*r3900:
3381{
3382 do_srav (SD_, RS, RT, RD);
3383}
3384
3385
3386
3387:function:::void:do_srl:int rt, int rd, int shift
3388{
3389 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
402586aa
CD		 3390 if (NotWordValue (GPR[rt]))
3391 Unpredictable ();
c906108c
SS		 3392 TRACE_ALU_INPUT2 (GPR[rt], shift);
3393 GPR[rd] = EXTEND32 (temp);
3394 TRACE_ALU_RESULT (GPR[rd]);
3395}
3396
3397000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3398"srl r<RD>, r<RT>, <SHIFT>"
c5d00cc7
CD		 3399*mipsI:
3400*mipsII:
3401*mipsIII:
3402*mipsIV:
603a98e7 3403*mipsV:
1e799e28 3404*mips32:
e70cb6cd 3405*mips32r2:
1e799e28 3406*mips64:
e70cb6cd 3407*mips64r2:
c906108c
SS		 3408*vr4100:
3409*vr5000:
3410*r3900:
3411{
3412 do_srl (SD_, RT, RD, SHIFT);
3413}
3414
3415
3416:function:::void:do_srlv:int rs, int rt, int rd
3417{
3418 int s = MASKED (GPR[rs], 4, 0);
3419 unsigned32 temp = (unsigned32) GPR[rt] >> s;
402586aa
CD		 3420 if (NotWordValue (GPR[rt]))
3421 Unpredictable ();
c906108c
SS		 3422 TRACE_ALU_INPUT2 (GPR[rt], s);
3423 GPR[rd] = EXTEND32 (temp);
3424 TRACE_ALU_RESULT (GPR[rd]);
3425}
3426
f701dad2 3427000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
c906108c 3428"srlv r<RD>, r<RT>, r<RS>"
c5d00cc7
CD		 3429*mipsI:
3430*mipsII:
3431*mipsIII:
3432*mipsIV:
603a98e7 3433*mipsV:
1e799e28 3434*mips32:
e70cb6cd 3435*mips32r2:
1e799e28 3436*mips64:
e70cb6cd 3437*mips64r2:
c906108c
SS		 3438*vr4100:
3439*vr5000:
3440*r3900:
3441{
3442 do_srlv (SD_, RS, RT, RD);
3443}
3444
3445
f701dad2 3446000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
c906108c 3447"sub r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 3448*mipsI:
3449*mipsII:
3450*mipsIII:
3451*mipsIV:
603a98e7 3452*mipsV:
1e799e28 3453*mips32:
e70cb6cd 3454*mips32r2:
1e799e28 3455*mips64:
e70cb6cd 3456*mips64r2:
c906108c
SS		 3457*vr4100:
3458*vr5000:
3459*r3900:
3460{
402586aa
CD		 3461 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3462 Unpredictable ();
c906108c
SS		 3463 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3464 {
3465 ALU32_BEGIN (GPR[RS]);
3466 ALU32_SUB (GPR[RT]);
9805e229 3467 ALU32_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 3468 }
3469 TRACE_ALU_RESULT (GPR[RD]);
3470}
3471
3472
3473:function:::void:do_subu:int rs, int rt, int rd
3474{
402586aa
CD		 3475 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3476 Unpredictable ();
c906108c
SS		 3477 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3478 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3479 TRACE_ALU_RESULT (GPR[rd]);
3480}
3481
f701dad2 3482000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
c906108c 3483"subu r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 3484*mipsI:
3485*mipsII:
3486*mipsIII:
3487*mipsIV:
603a98e7 3488*mipsV:
1e799e28 3489*mips32:
e70cb6cd 3490*mips32r2:
1e799e28 3491*mips64:
e70cb6cd 3492*mips64r2:
c906108c
SS		 3493*vr4100:
3494*vr5000:
3495*r3900:
3496{
3497 do_subu (SD_, RS, RT, RD);
3498}
3499
3500
3501101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3502"sw r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3503*mipsI:
3504*mipsII:
3505*mipsIII:
3506*mipsIV:
603a98e7 3507*mipsV:
1e799e28 3508*mips32:
e70cb6cd 3509*mips32r2:
1e799e28 3510*mips64:
e70cb6cd 3511*mips64r2:
c906108c
SS		 3512*vr4100:
3513*r3900:
3514*vr5000:
3515{
3516 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3517}
3518
3519
35201110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3521"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3522*mipsI:
3523*mipsII:
3524*mipsIII:
3525*mipsIV:
603a98e7 3526*mipsV:
1e799e28 3527*mips32:
e70cb6cd 3528*mips32r2:
1e799e28 3529*mips64:
e70cb6cd 3530*mips64r2:
c906108c
SS		 3531*vr4100:
3532*vr5000:
3533*r3900:
3534{
3535 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3536}
3537
3538
c906108c
SS		 3539101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3540"swl r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3541*mipsI:
3542*mipsII:
3543*mipsIII:
3544*mipsIV:
603a98e7 3545*mipsV:
1e799e28 3546*mips32:
e70cb6cd 3547*mips32r2:
1e799e28 3548*mips64:
e70cb6cd 3549*mips64r2:
c906108c
SS		 3550*vr4100:
3551*vr5000:
3552*r3900:
3553{
3554 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3555}
3556
3557
c906108c
SS		 3558101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3559"swr r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3560*mipsI:
3561*mipsII:
3562*mipsIII:
3563*mipsIV:
603a98e7 3564*mipsV:
1e799e28 3565*mips32:
e70cb6cd 3566*mips32r2:
1e799e28 3567*mips64:
e70cb6cd 3568*mips64r2:
c906108c
SS		 3569*vr4100:
3570*vr5000:
3571*r3900:
3572{
3573 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3574}
3575
3576
f701dad2 3577000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
c906108c
SS		 3578"sync":STYPE == 0
3579"sync <STYPE>"
3580*mipsII:
3581*mipsIII:
3582*mipsIV:
603a98e7 3583*mipsV:
1e799e28 3584*mips32:
e70cb6cd 3585*mips32r2:
1e799e28 3586*mips64:
e70cb6cd 3587*mips64r2:
c906108c
SS		 3588*vr4100:
3589*vr5000:
3590*r3900:
3591{
3592 SyncOperation (STYPE);
3593}
3594
3595
3596000000,20.CODE,001100:SPECIAL:32::SYSCALL
82f728db 3597"syscall %#lx<CODE>"
c5d00cc7
CD		 3598*mipsI:
3599*mipsII:
3600*mipsIII:
3601*mipsIV:
603a98e7 3602*mipsV:
1e799e28 3603*mips32:
e70cb6cd 3604*mips32r2:
1e799e28 3605*mips64:
e70cb6cd 3606*mips64r2:
c906108c
SS		 3607*vr4100:
3608*vr5000:
3609*r3900:
3610{
86b77b47 3611 SignalException (SystemCall, instruction_0);
c906108c
SS		 3612}
3613
3614
3615000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3616"teq r<RS>, r<RT>"
3617*mipsII:
3618*mipsIII:
3619*mipsIV:
603a98e7 3620*mipsV:
1e799e28 3621*mips32:
e70cb6cd 3622*mips32r2:
1e799e28 3623*mips64:
e70cb6cd 3624*mips64r2:
c906108c
SS		 3625*vr4100:
3626*vr5000:
3627{
3628 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
86b77b47 3629 SignalException (Trap, instruction_0);
c906108c
SS		 3630}
3631
3632
3633000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3634"teqi r<RS>, <IMMEDIATE>"
3635*mipsII:
3636*mipsIII:
3637*mipsIV:
603a98e7 3638*mipsV:
1e799e28 3639*mips32:
e70cb6cd 3640*mips32r2:
1e799e28 3641*mips64:
e70cb6cd 3642*mips64r2:
c906108c
SS		 3643*vr4100:
3644*vr5000:
3645{
3646 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
86b77b47 3647 SignalException (Trap, instruction_0);
c906108c
SS		 3648}
3649
3650
3651000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3652"tge r<RS>, r<RT>"
3653*mipsII:
3654*mipsIII:
3655*mipsIV:
603a98e7 3656*mipsV:
1e799e28 3657*mips32:
e70cb6cd 3658*mips32r2:
1e799e28 3659*mips64:
e70cb6cd 3660*mips64r2:
c906108c
SS		 3661*vr4100:
3662*vr5000:
3663{
3664 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
86b77b47 3665 SignalException (Trap, instruction_0);
c906108c
SS		 3666}
3667
3668
3669000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3670"tgei r<RS>, <IMMEDIATE>"
3671*mipsII:
3672*mipsIII:
3673*mipsIV:
603a98e7 3674*mipsV:
1e799e28 3675*mips32:
e70cb6cd 3676*mips32r2:
1e799e28 3677*mips64:
e70cb6cd 3678*mips64r2:
c906108c
SS		 3679*vr4100:
3680*vr5000:
3681{
3682 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
86b77b47 3683 SignalException (Trap, instruction_0);
c906108c
SS		 3684}
3685
3686
3687000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3688"tgeiu r<RS>, <IMMEDIATE>"
3689*mipsII:
3690*mipsIII:
3691*mipsIV:
603a98e7 3692*mipsV:
1e799e28 3693*mips32:
e70cb6cd 3694*mips32r2:
1e799e28 3695*mips64:
e70cb6cd 3696*mips64r2:
c906108c
SS		 3697*vr4100:
3698*vr5000:
3699{
3700 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
86b77b47 3701 SignalException (Trap, instruction_0);
c906108c
SS		 3702}
3703
3704
3705000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3706"tgeu r<RS>, r<RT>"
3707*mipsII:
3708*mipsIII:
3709*mipsIV:
603a98e7 3710*mipsV:
1e799e28 3711*mips32:
e70cb6cd 3712*mips32r2:
1e799e28 3713*mips64:
e70cb6cd 3714*mips64r2:
c906108c
SS		 3715*vr4100:
3716*vr5000:
3717{
3718 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
86b77b47 3719 SignalException (Trap, instruction_0);
c906108c
SS		 3720}
3721
3722
3723000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3724"tlt r<RS>, r<RT>"
3725*mipsII:
3726*mipsIII:
3727*mipsIV:
603a98e7 3728*mipsV:
1e799e28 3729*mips32:
e70cb6cd 3730*mips32r2:
1e799e28 3731*mips64:
e70cb6cd 3732*mips64r2:
c906108c
SS		 3733*vr4100:
3734*vr5000:
3735{
3736 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
86b77b47 3737 SignalException (Trap, instruction_0);
c906108c
SS		 3738}
3739
3740
3741000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3742"tlti r<RS>, <IMMEDIATE>"
3743*mipsII:
3744*mipsIII:
3745*mipsIV:
603a98e7 3746*mipsV:
1e799e28 3747*mips32:
e70cb6cd 3748*mips32r2:
1e799e28 3749*mips64:
e70cb6cd 3750*mips64r2:
c906108c
SS		 3751*vr4100:
3752*vr5000:
3753{
3754 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
86b77b47 3755 SignalException (Trap, instruction_0);
c906108c
SS		 3756}
3757
3758
3759000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3760"tltiu r<RS>, <IMMEDIATE>"
3761*mipsII:
3762*mipsIII:
3763*mipsIV:
603a98e7 3764*mipsV:
1e799e28 3765*mips32:
e70cb6cd 3766*mips32r2:
1e799e28 3767*mips64:
e70cb6cd 3768*mips64r2:
c906108c
SS		 3769*vr4100:
3770*vr5000:
3771{
3772 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
86b77b47 3773 SignalException (Trap, instruction_0);
c906108c
SS		 3774}
3775
3776
3777000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3778"tltu r<RS>, r<RT>"
3779*mipsII:
3780*mipsIII:
3781*mipsIV:
603a98e7 3782*mipsV:
1e799e28 3783*mips32:
e70cb6cd 3784*mips32r2:
1e799e28 3785*mips64:
e70cb6cd 3786*mips64r2:
c906108c
SS		 3787*vr4100:
3788*vr5000:
3789{
3790 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
86b77b47 3791 SignalException (Trap, instruction_0);
c906108c
SS		 3792}
3793
3794
3795000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3796"tne r<RS>, r<RT>"
3797*mipsII:
3798*mipsIII:
3799*mipsIV:
603a98e7 3800*mipsV:
1e799e28 3801*mips32:
e70cb6cd 3802*mips32r2:
1e799e28 3803*mips64:
e70cb6cd 3804*mips64r2:
c906108c
SS		 3805*vr4100:
3806*vr5000:
3807{
3808 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
86b77b47 3809 SignalException (Trap, instruction_0);
c906108c
SS		 3810}
3811
3812
3813000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
95fd5cee 3814"tnei r<RS>, <IMMEDIATE>"
c906108c
SS		 3815*mipsII:
3816*mipsIII:
3817*mipsIV:
603a98e7 3818*mipsV:
1e799e28 3819*mips32:
e70cb6cd 3820*mips32r2:
1e799e28 3821*mips64:
e70cb6cd 3822*mips64r2:
c906108c
SS		 3823*vr4100:
3824*vr5000:
3825{
3826 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
86b77b47 3827 SignalException (Trap, instruction_0);
c906108c
SS		 3828}
3829
3830
3831:function:::void:do_xor:int rs, int rt, int rd
3832{
3833 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3834 GPR[rd] = GPR[rs] ^ GPR[rt];
3835 TRACE_ALU_RESULT (GPR[rd]);
3836}
3837
f701dad2 3838000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
c906108c 3839"xor r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 3840*mipsI:
3841*mipsII:
3842*mipsIII:
3843*mipsIV:
603a98e7 3844*mipsV:
1e799e28 3845*mips32:
e70cb6cd 3846*mips32r2:
1e799e28 3847*mips64:
e70cb6cd 3848*mips64r2:
c906108c
SS		 3849*vr4100:
3850*vr5000:
3851*r3900:
3852{
3853 do_xor (SD_, RS, RT, RD);
3854}
3855
3856
3857:function:::void:do_xori:int rs, int rt, unsigned16 immediate
3858{
3859 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3860 GPR[rt] = GPR[rs] ^ immediate;
3861 TRACE_ALU_RESULT (GPR[rt]);
3862}
3863
3864001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
82f728db 3865"xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
c5d00cc7
CD		 3866*mipsI:
3867*mipsII:
3868*mipsIII:
3869*mipsIV:
603a98e7 3870*mipsV:
1e799e28 3871*mips32:
e70cb6cd 3872*mips32r2:
1e799e28 3873*mips64:
e70cb6cd 3874*mips64r2:
c906108c
SS		 3875*vr4100:
3876*vr5000:
3877*r3900:
3878{
3879 do_xori (SD_, RS, RT, IMMEDIATE);
3880}
3881
3882\f
3883//
3884// MIPS Architecture:
3885//
3886// FPU Instruction Set (COP1 & COP1X)
3887//
3888
3889
3890:%s::::FMT:int fmt
3891{
3892 switch (fmt)
3893 {
3894 case fmt_single: return "s";
3895 case fmt_double: return "d";
3896 case fmt_word: return "w";
3897 case fmt_long: return "l";
3a2b820e 3898 case fmt_ps: return "ps";
c906108c
SS		 3899 default: return "?";
3900 }
3901}
3902
c906108c
SS		 3903:%s::::TF:int tf
3904{
3905 if (tf)
3906 return "t";
3907 else
3908 return "f";
3909}
3910
3911:%s::::ND:int nd
3912{
3913 if (nd)
3914 return "l";
3915 else
3916 return "";
3917}
3918
3919:%s::::COND:int cond
3920{
3921 switch (cond)
3922 {
3923 case 00: return "f";
3924 case 01: return "un";
3925 case 02: return "eq";
3926 case 03: return "ueq";
3927 case 04: return "olt";
3928 case 05: return "ult";
3929 case 06: return "ole";
3930 case 07: return "ule";
3931 case 010: return "sf";
3932 case 011: return "ngle";
3933 case 012: return "seq";
3934 case 013: return "ngl";
3935 case 014: return "lt";
3936 case 015: return "nge";
3937 case 016: return "le";
3938 case 017: return "ngt";
3939 default: return "?";
3940 }
3941}
3942
8612006b
CD		 3943
3944// Helpers:
3945//
3946// Check that the given FPU format is usable, and signal a
3947// ReservedInstruction exception if not.
3948//
3949
8612006b
CD		 3950// check_fmt_p checks that the format is single, double, or paired single.
3951:function:::void:check_fmt_p:int fmt, instruction_word insn
3952*mipsI:
3953*mipsII:
3954*mipsIII:
3955*mipsIV:
1e799e28 3956*mips32:
e70cb6cd 3957*mips32r2:
8612006b
CD		 3958*vr4100:
3959*vr5000:
3960*r3900:
3961{
3962 /* None of these ISAs support Paired Single, so just fall back to
3963 the single/double check. */
14234056
CD		 3964 if ((fmt != fmt_single) && (fmt != fmt_double))
3965 SignalException (ReservedInstruction, insn);
8612006b
CD		 3966}
3967
1e799e28
CD		 3968:function:::void:check_fmt_p:int fmt, instruction_word insn
3969*mipsV:
3970*mips64:
e70cb6cd 3971*mips64r2:
1e799e28 3972{
1e799e28
CD		 3973 if ((fmt != fmt_single) && (fmt != fmt_double)
3974 && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3975 SignalException (ReservedInstruction, insn);
1e799e28
CD		 3976}
3977
8612006b 3978
ca971540 3979// Helper:
4a0bd876 3980//
ca971540
CD		 3981// Check that the FPU is currently usable, and signal a CoProcessorUnusable
3982// exception if not.
3983//
3984
3985:function:::void:check_fpu:
4a0bd876 3986*mipsI:
ca971540
CD		 3987*mipsII:
3988*mipsIII:
3989*mipsIV:
3990*mipsV:
1e799e28 3991*mips32:
e70cb6cd 3992*mips32r2:
1e799e28 3993*mips64:
e70cb6cd 3994*mips64r2:
ca971540
CD		 3995*vr4100:
3996*vr5000:
3997*r3900:
3998{
ca971540
CD		 3999 if (! COP_Usable (1))
4000 SignalExceptionCoProcessorUnusable (1);
ca971540
CD		 4001}
4002
c906108c 4003
06e7837e
CD		 4004// Helper:
4005//
4006// Load a double word FP value using 2 32-bit memory cycles a la MIPS II
4007// or MIPS32. do_load cannot be used instead because it returns an
4008// unsigned_word, which is limited to the size of the machine's registers.
4009//
4010
4011:function:::unsigned64:do_load_double:address_word base, address_word offset
4012*mipsII:
4013*mips32:
e70cb6cd 4014*mips32r2:
06e7837e
CD		 4015{
4016 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4017 address_word vaddr;
4018 address_word paddr;
4019 int uncached;
4020 unsigned64 memval;
4021 unsigned64 v;
4022
4023 vaddr = loadstore_ea (SD_, base, offset);
4024 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4025 {
4026 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
4027 AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
4028 sim_core_unaligned_signal);
4029 }
4030 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
4031 isREAL);
4032 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
4033 isDATA, isREAL);
4034 v = (unsigned64)memval;
4035 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
4036 isDATA, isREAL);
4037 return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
4038}
4039
4040
4041// Helper:
4042//
4043// Store a double word FP value using 2 32-bit memory cycles a la MIPS II
4044// or MIPS32. do_load cannot be used instead because it returns an
4045// unsigned_word, which is limited to the size of the machine's registers.
4046//
4047
4048:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
4049*mipsII:
4050*mips32:
e70cb6cd 4051*mips32r2:
06e7837e
CD		 4052{
4053 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4054 address_word vaddr;
4055 address_word paddr;
4056 int uncached;
4057 unsigned64 memval;
4058
4059 vaddr = loadstore_ea (SD_, base, offset);
4060 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4061 {
4062 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
4063 AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
4064 sim_core_unaligned_signal);
4065 }
4066 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
4067 isREAL);
4068 memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
4069 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
4070 isREAL);
4071 memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
4072 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
4073 isREAL);
4074}
4075
4076
14234056 4077010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
c906108c 4078"abs.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 4079*mipsI:
4080*mipsII:
4081*mipsIII:
4082*mipsIV:
603a98e7 4083*mipsV:
1e799e28 4084*mips32:
e70cb6cd 4085*mips32r2:
1e799e28 4086*mips64:
e70cb6cd 4087*mips64r2:
c906108c
SS		 4088*vr4100:
4089*vr5000:
4090*r3900:
4091{
c1e8ada4 4092 int fmt = FMT;
9b17d183 4093 check_fpu (SD_);
8612006b 4094 check_fmt_p (SD_, fmt, instruction_0);
d18ea9c2 4095 StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
c906108c
SS		 4096}
4097
4098
4099
14234056 4100010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
c906108c 4101"add.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 4102*mipsI:
4103*mipsII:
4104*mipsIII:
4105*mipsIV:
603a98e7 4106*mipsV:
1e799e28 4107*mips32:
e70cb6cd 4108*mips32r2:
1e799e28 4109*mips64:
e70cb6cd 4110*mips64r2:
c906108c
SS		 4111*vr4100:
4112*vr5000:
4113*r3900:
4114{
c1e8ada4 4115 int fmt = FMT;
9b17d183 4116 check_fpu (SD_);
8612006b 4117 check_fmt_p (SD_, fmt, instruction_0);
d18ea9c2 4118 StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
c906108c
SS		 4119}
4120
4121
3a2b820e
CD		 4122010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
4123"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
4124*mipsV:
4125*mips64:
e70cb6cd 4126*mips64r2:
3a2b820e
CD		 4127{
4128 unsigned64 fs;
4129 unsigned64 ft;
4130 unsigned64 fd;
4131 check_fpu (SD_);
4132 check_u64 (SD_, instruction_0);
4133 fs = ValueFPR (FS, fmt_ps);
4134 if ((GPR[RS] & 0x3) != 0)
4135 Unpredictable ();
4136 if ((GPR[RS] & 0x4) == 0)
4137 fd = fs;
4138 else
4139 {
4140 ft = ValueFPR (FT, fmt_ps);
4141 if (BigEndianCPU)
4142 fd = PackPS (PSLower (fs), PSUpper (ft));
4143 else
4144 fd = PackPS (PSLower (ft), PSUpper (fs));
4145 }
4146 StoreFPR (FD, fmt_ps, fd);
4147}
4148
c906108c
SS		 4149
4150// BC1F
4151// BC1FL
4152// BC1T
4153// BC1TL
4154
4155010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
4156"bc1%s<TF>%s<ND> <OFFSET>"
c5d00cc7
CD		 4157*mipsI:
4158*mipsII:
4159*mipsIII:
c906108c 4160{
9b17d183 4161 check_fpu (SD_);
c906108c
SS		 4162 TRACE_BRANCH_INPUT (PREVCOC1());
4163 if (PREVCOC1() == TF)
4164 {
4165 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4166 TRACE_BRANCH_RESULT (dest);
c906108c
SS		 4167 DELAY_SLOT (dest);
4168 }
4169 else if (ND)
4170 {
4171 TRACE_BRANCH_RESULT (0);
4172 NULLIFY_NEXT_INSTRUCTION ();
4173 }
4174 else
4175 {
4176 TRACE_BRANCH_RESULT (NIA);
4177 }
4178}
4179
4180010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
4181"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4182"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4183*mipsIV:
603a98e7 4184*mipsV:
1e799e28 4185*mips32:
e70cb6cd 4186*mips32r2:
1e799e28 4187*mips64:
e70cb6cd 4188*mips64r2:
c906108c 4189#*vr4100:
074e9cb8 4190*vr5000:
c906108c
SS		 4191*r3900:
4192{
9b17d183 4193 check_fpu (SD_);
c906108c
SS		 4194 if (GETFCC(CC) == TF)
4195 {
4196 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
c906108c
SS		 4197 DELAY_SLOT (dest);
4198 }
4199 else if (ND)
4200 {
4201 NULLIFY_NEXT_INSTRUCTION ();
4202 }
4203}
4204
4205
14234056 4206010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
c906108c 4207"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
c5d00cc7
CD		 4208*mipsI:
4209*mipsII:
4210*mipsIII:
c906108c 4211{
8612006b 4212 int fmt = FMT;
9b17d183 4213 check_fpu (SD_);
cfe9ea23
CD		 4214 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
4215 TRACE_ALU_RESULT (ValueFCR (31));
c906108c
SS		 4216}
4217
14234056 4218010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
c906108c
SS		 4219"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4220"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4221*mipsIV:
603a98e7 4222*mipsV:
1e799e28 4223*mips32:
e70cb6cd 4224*mips32r2:
1e799e28 4225*mips64:
e70cb6cd 4226*mips64r2:
c906108c
SS		 4227*vr4100:
4228*vr5000:
4229*r3900:
4230{
8612006b 4231 int fmt = FMT;
9b17d183 4232 check_fpu (SD_);
8612006b 4233 check_fmt_p (SD_, fmt, instruction_0);
cfe9ea23
CD		 4234 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
4235 TRACE_ALU_RESULT (ValueFCR (31));
c906108c
SS		 4236}
4237
4238
14234056 4239010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
c906108c
SS		 4240"ceil.l.%s<FMT> f<FD>, f<FS>"
4241*mipsIII:
4242*mipsIV:
603a98e7 4243*mipsV:
1e799e28 4244*mips64:
e70cb6cd 4245*mips64r2:
c906108c
SS		 4246*vr4100:
4247*vr5000:
4248*r3900:
4249{
c1e8ada4 4250 int fmt = FMT;
9b17d183 4251 check_fpu (SD_);
d18ea9c2
CD		 4252 StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4253 fmt_long));
c906108c
SS		 4254}
4255
4256
14234056 4257010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
95fd5cee 4258"ceil.w.%s<FMT> f<FD>, f<FS>"
c906108c
SS		 4259*mipsII:
4260*mipsIII:
4261*mipsIV:
603a98e7 4262*mipsV:
1e799e28 4263*mips32:
e70cb6cd 4264*mips32r2:
1e799e28 4265*mips64:
e70cb6cd 4266*mips64r2:
c906108c
SS		 4267*vr4100:
4268*vr5000:
4269*r3900:
4270{
c1e8ada4 4271 int fmt = FMT;
9b17d183 4272 check_fpu (SD_);
d18ea9c2
CD		 4273 StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4274 fmt_word));
c906108c
SS		 4275}
4276
4277
cfe9ea23
CD		 4278010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
4279"cfc1 r<RT>, f<FS>"
c906108c
SS		 4280*mipsI:
4281*mipsII:
4282*mipsIII:
4283{
9b17d183 4284 check_fpu (SD_);
cfe9ea23
CD		 4285 if (FS == 0)
4286 PENDING_FILL (RT, EXTEND32 (FCR0));
4287 else if (FS == 31)
4288 PENDING_FILL (RT, EXTEND32 (FCR31));
4289 /* else NOP */
4290}
4291
4292010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
4293"cfc1 r<RT>, f<FS>"
4294*mipsIV:
4295*vr4100:
4296*vr5000:
4297*r3900:
4298{
4299 check_fpu (SD_);
4300 if (FS == 0 || FS == 31)
c906108c 4301 {
cfe9ea23
CD		 4302 unsigned_word fcr = ValueFCR (FS);
4303 TRACE_ALU_INPUT1 (fcr);
4304 GPR[RT] = fcr;
c906108c 4305 }
cfe9ea23
CD		 4306 /* else NOP */
4307 TRACE_ALU_RESULT (GPR[RT]);
c906108c 4308}
cfe9ea23
CD		 4309
4310010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
4311"cfc1 r<RT>, f<FS>"
603a98e7 4312*mipsV:
1e799e28 4313*mips32:
e70cb6cd 4314*mips32r2:
1e799e28 4315*mips64:
e70cb6cd 4316*mips64r2:
cfe9ea23
CD		 4317{
4318 check_fpu (SD_);
4319 if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
4320 {
4321 unsigned_word fcr = ValueFCR (FS);
4322 TRACE_ALU_INPUT1 (fcr);
4323 GPR[RT] = fcr;
4324 }
4325 /* else NOP */
4326 TRACE_ALU_RESULT (GPR[RT]);
4327}
4328
4329010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
4330"ctc1 r<RT>, f<FS>"
4331*mipsI:
4332*mipsII:
4333*mipsIII:
4334{
4335 check_fpu (SD_);
4336 if (FS == 31)
4337 PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
4338 /* else NOP */
4339}
4340
4341010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
4342"ctc1 r<RT>, f<FS>"
4343*mipsIV:
c906108c
SS		 4344*vr4100:
4345*vr5000:
4346*r3900:
4347{
9b17d183 4348 check_fpu (SD_);
cfe9ea23
CD		 4349 TRACE_ALU_INPUT1 (GPR[RT]);
4350 if (FS == 31)
4351 StoreFCR (FS, GPR[RT]);
4352 /* else NOP */
4353}
4354
4355010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
4356"ctc1 r<RT>, f<FS>"
4357*mipsV:
4358*mips32:
e70cb6cd 4359*mips32r2:
cfe9ea23 4360*mips64:
e70cb6cd 4361*mips64r2:
cfe9ea23
CD		 4362{
4363 check_fpu (SD_);
4364 TRACE_ALU_INPUT1 (GPR[RT]);
4365 if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
4366 StoreFCR (FS, GPR[RT]);
4367 /* else NOP */
c906108c
SS		 4368}
4369
4370
4371//
4372// FIXME: Does not correctly differentiate between mips*
4373//
14234056 4374010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
c906108c 4375"cvt.d.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 4376*mipsI:
4377*mipsII:
4378*mipsIII:
4379*mipsIV:
603a98e7 4380*mipsV:
1e799e28 4381*mips32:
e70cb6cd 4382*mips32r2:
1e799e28 4383*mips64:
e70cb6cd 4384*mips64r2:
c906108c
SS		 4385*vr4100:
4386*vr5000:
4387*r3900:
4388{
c1e8ada4 4389 int fmt = FMT;
9b17d183 4390 check_fpu (SD_);
d18ea9c2
CD		 4391 if ((fmt == fmt_double) | 0)
4392 SignalException (ReservedInstruction, instruction_0);
4393 StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4394 fmt_double));
c906108c
SS		 4395}
4396
4397
14234056 4398010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
c906108c
SS		 4399"cvt.l.%s<FMT> f<FD>, f<FS>"
4400*mipsIII:
4401*mipsIV:
603a98e7 4402*mipsV:
1e799e28 4403*mips64:
e70cb6cd 4404*mips64r2:
c906108c
SS		 4405*vr4100:
4406*vr5000:
4407*r3900:
4408{
c1e8ada4 4409 int fmt = FMT;
9b17d183 4410 check_fpu (SD_);
d18ea9c2
CD		 4411 if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
4412 SignalException (ReservedInstruction, instruction_0);
4413 StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4414 fmt_long));
c906108c
SS		 4415}
4416
4417
3a2b820e
CD		 4418010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
4419"cvt.ps.s f<FD>, f<FS>, f<FT>"
4420*mipsV:
4421*mips64:
e70cb6cd 4422*mips64r2:
3a2b820e
CD		 4423{
4424 check_fpu (SD_);
4425 check_u64 (SD_, instruction_0);
4426 StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
4427 ValueFPR (FT, fmt_single)));
4428}
4429
4430
c906108c
SS		 4431//
4432// FIXME: Does not correctly differentiate between mips*
4433//
14234056 4434010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
c906108c 4435"cvt.s.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 4436*mipsI:
4437*mipsII:
4438*mipsIII:
4439*mipsIV:
603a98e7 4440*mipsV:
1e799e28 4441*mips32:
e70cb6cd 4442*mips32r2:
1e799e28 4443*mips64:
e70cb6cd 4444*mips64r2:
c906108c
SS		 4445*vr4100:
4446*vr5000:
4447*r3900:
4448{
c1e8ada4 4449 int fmt = FMT;
9b17d183 4450 check_fpu (SD_);
d18ea9c2
CD		 4451 if ((fmt == fmt_single) | 0)
4452 SignalException (ReservedInstruction, instruction_0);
4453 StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4454 fmt_single));
c906108c
SS		 4455}
4456
4457
3a2b820e
CD		 4458010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4459"cvt.s.pl f<FD>, f<FS>"
4460*mipsV:
4461*mips64:
e70cb6cd 4462*mips64r2:
3a2b820e
CD		 4463{
4464 check_fpu (SD_);
4465 check_u64 (SD_, instruction_0);
4466 StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4467}
4468
4469
4470010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4471"cvt.s.pu f<FD>, f<FS>"
4472*mipsV:
4473*mips64:
e70cb6cd 4474*mips64r2:
3a2b820e
CD		 4475{
4476 check_fpu (SD_);
4477 check_u64 (SD_, instruction_0);
4478 StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4479}
4480
4481
14234056 4482010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
c906108c 4483"cvt.w.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 4484*mipsI:
4485*mipsII:
4486*mipsIII:
4487*mipsIV:
603a98e7 4488*mipsV:
1e799e28 4489*mips32:
e70cb6cd 4490*mips32r2:
1e799e28 4491*mips64:
e70cb6cd 4492*mips64r2:
c906108c
SS		 4493*vr4100:
4494*vr5000:
4495*r3900:
4496{
c1e8ada4 4497 int fmt = FMT;
9b17d183 4498 check_fpu (SD_);
d18ea9c2
CD		 4499 if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4500 SignalException (ReservedInstruction, instruction_0);
4501 StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4502 fmt_word));
c906108c
SS		 4503}
4504
4505
14234056 4506010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
c906108c 4507"div.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 4508*mipsI:
4509*mipsII:
4510*mipsIII:
4511*mipsIV:
603a98e7 4512*mipsV:
1e799e28 4513*mips32:
e70cb6cd 4514*mips32r2:
1e799e28 4515*mips64:
e70cb6cd 4516*mips64r2:
c906108c
SS		 4517*vr4100:
4518*vr5000:
4519*r3900:
4520{
c1e8ada4 4521 int fmt = FMT;
9b17d183 4522 check_fpu (SD_);
d18ea9c2 4523 StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
c906108c
SS		 4524}
4525
4526
cfe9ea23
CD		 4527010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4528"dmfc1 r<RT>, f<FS>"
c906108c
SS		 4529*mipsIII:
4530{
cfe9ea23 4531 unsigned64 v;
9b17d183 4532 check_fpu (SD_);
ca971540 4533 check_u64 (SD_, instruction_0);
cfe9ea23
CD		 4534 if (SizeFGR () == 64)
4535 v = FGR[FS];
4536 else if ((FS & 0x1) == 0)
4537 v = SET64HI (FGR[FS+1]) | FGR[FS];
c906108c 4538 else
cfe9ea23
CD		 4539 v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4540 PENDING_FILL (RT, v);
4541 TRACE_ALU_RESULT (v);
c906108c 4542}
cfe9ea23
CD		 4543
4544010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4545"dmfc1 r<RT>, f<FS>"
c906108c 4546*mipsIV:
603a98e7 4547*mipsV:
1e799e28 4548*mips64:
e70cb6cd 4549*mips64r2:
c906108c
SS		 4550*vr4100:
4551*vr5000:
4552*r3900:
4553{
9b17d183 4554 check_fpu (SD_);
ca971540 4555 check_u64 (SD_, instruction_0);
cfe9ea23
CD		 4556 if (SizeFGR () == 64)
4557 GPR[RT] = FGR[FS];
4558 else if ((FS & 0x1) == 0)
4559 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
c906108c 4560 else
cfe9ea23
CD		 4561 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4562 TRACE_ALU_RESULT (GPR[RT]);
4563}
4564
4565
4566010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4567"dmtc1 r<RT>, f<FS>"
4568*mipsIII:
4569{
4570 unsigned64 v;
4571 check_fpu (SD_);
4572 check_u64 (SD_, instruction_0);
4573 if (SizeFGR () == 64)
4574 PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4575 else if ((FS & 0x1) == 0)
c906108c 4576 {
cfe9ea23
CD		 4577 PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4578 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
c906108c 4579 }
cfe9ea23
CD		 4580 else
4581 Unpredictable ();
4582 TRACE_FP_RESULT (GPR[RT]);
4583}
4584
4585010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4586"dmtc1 r<RT>, f<FS>"
4587*mipsIV:
4588*mipsV:
4589*mips64:
e70cb6cd 4590*mips64r2:
cfe9ea23
CD		 4591*vr4100:
4592*vr5000:
4593*r3900:
4594{
4595 check_fpu (SD_);
4596 check_u64 (SD_, instruction_0);
4597 if (SizeFGR () == 64)
4598 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4599 else if ((FS & 0x1) == 0)
4600 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4601 else
4602 Unpredictable ();
c906108c
SS		 4603}
4604
4605
14234056 4606010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
c906108c
SS		 4607"floor.l.%s<FMT> f<FD>, f<FS>"
4608*mipsIII:
4609*mipsIV:
603a98e7 4610*mipsV:
1e799e28 4611*mips64:
e70cb6cd 4612*mips64r2:
c906108c
SS		 4613*vr4100:
4614*vr5000:
4615*r3900:
4616{
c1e8ada4 4617 int fmt = FMT;
9b17d183 4618 check_fpu (SD_);
d18ea9c2
CD		 4619 StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4620 fmt_long));
c906108c
SS		 4621}
4622
4623
14234056 4624010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
c906108c
SS		 4625"floor.w.%s<FMT> f<FD>, f<FS>"
4626*mipsII:
4627*mipsIII:
4628*mipsIV:
603a98e7 4629*mipsV:
1e799e28 4630*mips32:
e70cb6cd 4631*mips32r2:
1e799e28 4632*mips64:
e70cb6cd 4633*mips64r2:
c906108c
SS		 4634*vr4100:
4635*vr5000:
4636*r3900:
4637{
c1e8ada4 4638 int fmt = FMT;
9b17d183 4639 check_fpu (SD_);
d18ea9c2
CD		 4640 StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4641 fmt_word));
c906108c
SS		 4642}
4643
4644
06e7837e 4645110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
c906108c
SS		 4646"ldc1 f<FT>, <OFFSET>(r<BASE>)"
4647*mipsII:
06e7837e 4648*mips32:
e70cb6cd 4649*mips32r2:
06e7837e
CD		 4650{
4651 check_fpu (SD_);
4652 COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
4653}
4654
4655
4656110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
4657"ldc1 f<FT>, <OFFSET>(r<BASE>)"
c906108c
SS		 4658*mipsIII:
4659*mipsIV:
603a98e7 4660*mipsV:
1e799e28 4661*mips64:
e70cb6cd 4662*mips64r2:
c906108c
SS		 4663*vr4100:
4664*vr5000:
4665*r3900:
4666{
9b17d183 4667 check_fpu (SD_);
c906108c
SS		 4668 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4669}
4670
4671
eb5fcf93 4672010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
c906108c
SS		 4673"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4674*mipsIV:
603a98e7 4675*mipsV:
1e799e28 4676*mips64:
e70cb6cd 4677*mips64r2:
c906108c
SS		 4678*vr5000:
4679{
9b17d183 4680 check_fpu (SD_);
ca971540 4681 check_u64 (SD_, instruction_0);
c906108c
SS		 4682 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4683}
4684
4685
d29e330f
CD		 4686010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
4687"luxc1 f<FD>, r<INDEX>(r<BASE>)"
4688*mipsV:
4689*mips64:
e70cb6cd 4690*mips64r2:
d29e330f
CD		 4691{
4692 address_word base = GPR[BASE];
4693 address_word index = GPR[INDEX];
4694 address_word vaddr = base + index;
4695 check_fpu (SD_);
4696 check_u64 (SD_, instruction_0);
4697 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
4698 if ((vaddr & 0x7) != 0)
4699 index -= (vaddr & 0x7);
4700 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
4701}
4702
c906108c 4703
4a0bd876 4704110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
c906108c 4705"lwc1 f<FT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 4706*mipsI:
4707*mipsII:
4708*mipsIII:
4709*mipsIV:
603a98e7 4710*mipsV:
1e799e28 4711*mips32:
e70cb6cd 4712*mips32r2:
1e799e28 4713*mips64:
e70cb6cd 4714*mips64r2:
c906108c
SS		 4715*vr4100:
4716*vr5000:
4717*r3900:
4718{
9b17d183 4719 check_fpu (SD_);
c906108c
SS		 4720 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4721}
4722
4723
eb5fcf93 4724010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
c906108c
SS		 4725"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4726*mipsIV:
603a98e7 4727*mipsV:
1e799e28 4728*mips64:
e70cb6cd 4729*mips64r2:
c906108c
SS		 4730*vr5000:
4731{
9b17d183 4732 check_fpu (SD_);
ca971540 4733 check_u64 (SD_, instruction_0);
c906108c
SS		 4734 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4735}
4736
4737
4738
14234056 4739010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:64,f::MADD.fmt
f3c08b7e 4740"madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
c906108c 4741*mipsIV:
603a98e7 4742*mipsV:
1e799e28 4743*mips64:
e70cb6cd 4744*mips64r2:
c906108c
SS		 4745*vr5000:
4746{
f3c08b7e 4747 int fmt = FMT;
9b17d183 4748 check_fpu (SD_);
f3c08b7e
CD		 4749 check_u64 (SD_, instruction_0);
4750 check_fmt_p (SD_, fmt, instruction_0);
4751 StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4752 ValueFPR (FR, fmt), fmt));
c906108c
SS		 4753}
4754
4755
cfe9ea23
CD		 4756010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4757"mfc1 r<RT>, f<FS>"
c906108c
SS		 4758*mipsI:
4759*mipsII:
4760*mipsIII:
4761{
cfe9ea23 4762 unsigned64 v;
9b17d183 4763 check_fpu (SD_);
cfe9ea23
CD		 4764 v = EXTEND32 (FGR[FS]);
4765 PENDING_FILL (RT, v);
4766 TRACE_ALU_RESULT (v);
c906108c 4767}
cfe9ea23
CD		 4768
4769010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4770"mfc1 r<RT>, f<FS>"
c906108c 4771*mipsIV:
603a98e7 4772*mipsV:
1e799e28 4773*mips32:
e70cb6cd 4774*mips32r2:
1e799e28 4775*mips64:
e70cb6cd 4776*mips64r2:
c906108c
SS		 4777*vr4100:
4778*vr5000:
4779*r3900:
cfe9ea23 4780{
9b17d183 4781 check_fpu (SD_);
cfe9ea23
CD		 4782 GPR[RT] = EXTEND32 (FGR[FS]);
4783 TRACE_ALU_RESULT (GPR[RT]);
c906108c
SS		 4784}
4785
4786
14234056 4787010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
c906108c 4788"mov.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 4789*mipsI:
4790*mipsII:
4791*mipsIII:
4792*mipsIV:
603a98e7 4793*mipsV:
1e799e28 4794*mips32:
e70cb6cd 4795*mips32r2:
1e799e28 4796*mips64:
e70cb6cd 4797*mips64r2:
c906108c
SS		 4798*vr4100:
4799*vr5000:
4800*r3900:
4801{
c1e8ada4 4802 int fmt = FMT;
9b17d183 4803 check_fpu (SD_);
8612006b 4804 check_fmt_p (SD_, fmt, instruction_0);
d18ea9c2 4805 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
c906108c
SS		 4806}
4807
4808
4809// MOVF
c2d11a7d 4810// MOVT
eb5fcf93 4811000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
c906108c
SS		 4812"mov%s<TF> r<RD>, r<RS>, <CC>"
4813*mipsIV:
603a98e7 4814*mipsV:
1e799e28 4815*mips32:
e70cb6cd 4816*mips32r2:
1e799e28 4817*mips64:
e70cb6cd 4818*mips64r2:
c906108c
SS		 4819*vr5000:
4820{
9b17d183 4821 check_fpu (SD_);
c906108c
SS		 4822 if (GETFCC(CC) == TF)
4823 GPR[RD] = GPR[RS];
4824}
4825
4826
4827// MOVF.fmt
c2d11a7d 4828// MOVT.fmt
14234056 4829010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
c906108c
SS		 4830"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4831*mipsIV:
603a98e7 4832*mipsV:
1e799e28 4833*mips32:
e70cb6cd 4834*mips32r2:
1e799e28 4835*mips64:
e70cb6cd 4836*mips64r2:
c906108c
SS		 4837*vr5000:
4838{
c1e8ada4 4839 int fmt = FMT;
9b17d183 4840 check_fpu (SD_);
3a2b820e
CD		 4841 if (fmt != fmt_ps)
4842 {
4843 if (GETFCC(CC) == TF)
4844 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4845 else
4846 StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */
4847 }
4848 else
4849 {
4850 unsigned64 fd;
4851 fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
4852 fmt_ps)),
4853 PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
4854 fmt_ps)));
4855 StoreFPR (FD, fmt_ps, fd);
4856 }
c906108c
SS		 4857}
4858
4859
14234056 4860010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
80ee11fa 4861"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
c906108c 4862*mipsIV:
603a98e7 4863*mipsV:
1e799e28 4864*mips32:
e70cb6cd 4865*mips32r2:
1e799e28 4866*mips64:
e70cb6cd 4867*mips64r2:
c906108c
SS		 4868*vr5000:
4869{
9b17d183 4870 check_fpu (SD_);
80ee11fa
AC		 4871 if (GPR[RT] != 0)
4872 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4873 else
4874 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
c906108c
SS		 4875}
4876
4877
4878// MOVT see MOVtf
4879
4880
4881// MOVT.fmt see MOVtf.fmt
4882
4883
4884
14234056 4885010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
c906108c
SS		 4886"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4887*mipsIV:
603a98e7 4888*mipsV:
1e799e28 4889*mips32:
e70cb6cd 4890*mips32r2:
1e799e28 4891*mips64:
e70cb6cd 4892*mips64r2:
c906108c
SS		 4893*vr5000:
4894{
9b17d183 4895 check_fpu (SD_);
80ee11fa
AC		 4896 if (GPR[RT] == 0)
4897 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4898 else
4899 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
c906108c
SS		 4900}
4901
4902
14234056 4903010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:64,f::MSUB.fmt
f3c08b7e 4904"msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
c906108c 4905*mipsIV:
603a98e7 4906*mipsV:
1e799e28 4907*mips64:
e70cb6cd 4908*mips64r2:
c906108c
SS		 4909*vr5000:
4910{
f3c08b7e 4911 int fmt = FMT;
9b17d183 4912 check_fpu (SD_);
f3c08b7e
CD		 4913 check_u64 (SD_, instruction_0);
4914 check_fmt_p (SD_, fmt, instruction_0);
4915 StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4916 ValueFPR (FR, fmt), fmt));
c906108c
SS		 4917}
4918
4919
cfe9ea23
CD		 4920010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4921"mtc1 r<RT>, f<FS>"
4922*mipsI:
4923*mipsII:
4924*mipsIII:
4925{
4926 check_fpu (SD_);
4927 if (SizeFGR () == 64)
4928 PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4929 else
4930 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4931 TRACE_FP_RESULT (GPR[RT]);
4932}
4933
4934010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4935"mtc1 r<RT>, f<FS>"
4936*mipsIV:
4937*mipsV:
4938*mips32:
e70cb6cd 4939*mips32r2:
cfe9ea23 4940*mips64:
e70cb6cd 4941*mips64r2:
cfe9ea23
CD		 4942*vr4100:
4943*vr5000:
4944*r3900:
4945{
4946 check_fpu (SD_);
4947 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4948}
c906108c
SS		 4949
4950
14234056 4951010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
c906108c 4952"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 4953*mipsI:
4954*mipsII:
4955*mipsIII:
4956*mipsIV:
603a98e7 4957*mipsV:
1e799e28 4958*mips32:
e70cb6cd 4959*mips32r2:
1e799e28 4960*mips64:
e70cb6cd 4961*mips64r2:
c906108c
SS		 4962*vr4100:
4963*vr5000:
4964*r3900:
4965{
c1e8ada4 4966 int fmt = FMT;
9b17d183 4967 check_fpu (SD_);
8612006b 4968 check_fmt_p (SD_, fmt, instruction_0);
d18ea9c2 4969 StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
c906108c
SS		 4970}
4971
4972
14234056 4973010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
c906108c 4974"neg.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 4975*mipsI:
4976*mipsII:
4977*mipsIII:
4978*mipsIV:
603a98e7 4979*mipsV:
1e799e28 4980*mips32:
e70cb6cd 4981*mips32r2:
1e799e28 4982*mips64:
e70cb6cd 4983*mips64r2:
c906108c
SS		 4984*vr4100:
4985*vr5000:
4986*r3900:
4987{
c1e8ada4 4988 int fmt = FMT;
9b17d183 4989 check_fpu (SD_);
8612006b 4990 check_fmt_p (SD_, fmt, instruction_0);
d18ea9c2 4991 StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
c906108c
SS		 4992}
4993
4994
14234056 4995010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:64,f::NMADD.fmt
f3c08b7e 4996"nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
c906108c 4997*mipsIV:
603a98e7 4998*mipsV:
1e799e28 4999*mips64:
e70cb6cd 5000*mips64r2:
c906108c
SS		 5001*vr5000:
5002{
f3c08b7e 5003 int fmt = FMT;
9b17d183 5004 check_fpu (SD_);
f3c08b7e
CD		 5005 check_u64 (SD_, instruction_0);
5006 check_fmt_p (SD_, fmt, instruction_0);
5007 StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5008 ValueFPR (FR, fmt), fmt));
c906108c
SS		 5009}
5010
5011
14234056 5012010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:64,f::NMSUB.fmt
f3c08b7e 5013"nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
c906108c 5014*mipsIV:
603a98e7 5015*mipsV:
1e799e28 5016*mips64:
e70cb6cd 5017*mips64r2:
c906108c
SS		 5018*vr5000:
5019{
f3c08b7e 5020 int fmt = FMT;
9b17d183 5021 check_fpu (SD_);
f3c08b7e
CD		 5022 check_u64 (SD_, instruction_0);
5023 check_fmt_p (SD_, fmt, instruction_0);
5024 StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5025 ValueFPR (FR, fmt), fmt));
c906108c
SS		 5026}
5027
5028
3a2b820e
CD		 5029010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
5030"pll.ps f<FD>, f<FS>, f<FT>"
5031*mipsV:
5032*mips64:
e70cb6cd 5033*mips64r2:
3a2b820e
CD		 5034{
5035 check_fpu (SD_);
5036 check_u64 (SD_, instruction_0);
5037 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5038 PSLower (ValueFPR (FT, fmt_ps))));
5039}
5040
5041
5042010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
5043"plu.ps f<FD>, f<FS>, f<FT>"
5044*mipsV:
5045*mips64:
e70cb6cd 5046*mips64r2:
3a2b820e
CD		 5047{
5048 check_fpu (SD_);
5049 check_u64 (SD_, instruction_0);
5050 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5051 PSUpper (ValueFPR (FT, fmt_ps))));
5052}
5053
5054
3d81f391 5055010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
c906108c
SS		 5056"prefx <HINT>, r<INDEX>(r<BASE>)"
5057*mipsIV:
603a98e7 5058*mipsV:
1e799e28 5059*mips64:
e70cb6cd 5060*mips64r2:
c906108c
SS		 5061*vr5000:
5062{
c1e8ada4
CD		 5063 address_word base = GPR[BASE];
5064 address_word index = GPR[INDEX];
c906108c 5065 {
09297648 5066 address_word vaddr = loadstore_ea (SD_, base, index);
c906108c
SS		 5067 address_word paddr;
5068 int uncached;
5069 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
c1e8ada4 5070 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
c906108c
SS		 5071 }
5072}
5073
3a2b820e
CD		 5074
5075010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
5076"pul.ps f<FD>, f<FS>, f<FT>"
5077*mipsV:
5078*mips64:
e70cb6cd 5079*mips64r2:
3a2b820e
CD		 5080{
5081 check_fpu (SD_);
5082 check_u64 (SD_, instruction_0);
5083 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5084 PSLower (ValueFPR (FT, fmt_ps))));
5085}
5086
5087
5088010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
5089"puu.ps f<FD>, f<FS>, f<FT>"
5090*mipsV:
5091*mips64:
e70cb6cd 5092*mips64r2:
3a2b820e
CD		 5093{
5094 check_fpu (SD_);
5095 check_u64 (SD_, instruction_0);
5096 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5097 PSUpper (ValueFPR (FT, fmt_ps))));
5098}
5099
5100
14234056 5101010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
c906108c 5102"recip.%s<FMT> f<FD>, f<FS>"
e514a9d6 5103*mipsIV:
603a98e7 5104*mipsV:
1e799e28 5105*mips64:
e70cb6cd 5106*mips64r2:
c906108c
SS		 5107*vr5000:
5108{
c1e8ada4 5109 int fmt = FMT;
9b17d183 5110 check_fpu (SD_);
d18ea9c2 5111 StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
c906108c
SS		 5112}
5113
5114
14234056 5115010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
c906108c
SS		 5116"round.l.%s<FMT> f<FD>, f<FS>"
5117*mipsIII:
5118*mipsIV:
603a98e7 5119*mipsV:
1e799e28 5120*mips64:
e70cb6cd 5121*mips64r2:
c906108c
SS		 5122*vr4100:
5123*vr5000:
5124*r3900:
5125{
c1e8ada4 5126 int fmt = FMT;
9b17d183 5127 check_fpu (SD_);
d18ea9c2
CD		 5128 StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5129 fmt_long));
c906108c
SS		 5130}
5131
5132
14234056 5133010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
c906108c
SS		 5134"round.w.%s<FMT> f<FD>, f<FS>"
5135*mipsII:
5136*mipsIII:
5137*mipsIV:
603a98e7 5138*mipsV:
1e799e28 5139*mips32:
e70cb6cd 5140*mips32r2:
1e799e28 5141*mips64:
e70cb6cd 5142*mips64r2:
c906108c
SS		 5143*vr4100:
5144*vr5000:
5145*r3900:
5146{
c1e8ada4 5147 int fmt = FMT;
9b17d183 5148 check_fpu (SD_);
d18ea9c2
CD		 5149 StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5150 fmt_word));
c906108c
SS		 5151}
5152
5153
14234056 5154010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
95fd5cee 5155"rsqrt.%s<FMT> f<FD>, f<FS>"
c906108c 5156*mipsIV:
603a98e7 5157*mipsV:
1e799e28 5158*mips64:
e70cb6cd 5159*mips64r2:
c906108c
SS		 5160*vr5000:
5161{
c1e8ada4 5162 int fmt = FMT;
9b17d183 5163 check_fpu (SD_);
f3c08b7e 5164 StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
c906108c
SS		 5165}
5166
5167
06e7837e 5168111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
c906108c
SS		 5169"sdc1 f<FT>, <OFFSET>(r<BASE>)"
5170*mipsII:
06e7837e 5171*mips32:
e70cb6cd 5172*mips32r2:
06e7837e
CD		 5173{
5174 check_fpu (SD_);
5175 do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5176}
5177
5178
5179111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
5180"sdc1 f<FT>, <OFFSET>(r<BASE>)"
c906108c
SS		 5181*mipsIII:
5182*mipsIV:
603a98e7 5183*mipsV:
1e799e28 5184*mips64:
e70cb6cd 5185*mips64r2:
c906108c
SS		 5186*vr4100:
5187*vr5000:
5188*r3900:
5189{
9b17d183 5190 check_fpu (SD_);
c906108c
SS		 5191 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5192}
5193
5194
eb5fcf93 5195010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
91a177cf 5196"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
c906108c 5197*mipsIV:
603a98e7 5198*mipsV:
1e799e28 5199*mips64:
e70cb6cd 5200*mips64r2:
c906108c
SS		 5201*vr5000:
5202{
9b17d183 5203 check_fpu (SD_);
ca971540 5204 check_u64 (SD_, instruction_0);
c906108c
SS		 5205 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5206}
5207
5208
d29e330f
CD		 5209010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
5210"suxc1 f<FS>, r<INDEX>(r<BASE>)"
5211*mipsV:
5212*mips64:
e70cb6cd 5213*mips64r2:
d29e330f
CD		 5214{
5215 unsigned64 v;
5216 address_word base = GPR[BASE];
5217 address_word index = GPR[INDEX];
5218 address_word vaddr = base + index;
5219 check_fpu (SD_);
5220 check_u64 (SD_, instruction_0);
5221 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
5222 if ((vaddr & 0x7) != 0)
5223 index -= (vaddr & 0x7);
5224 do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
5225}
5226
5227
14234056 5228010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
c906108c
SS		 5229"sqrt.%s<FMT> f<FD>, f<FS>"
5230*mipsII:
5231*mipsIII:
5232*mipsIV:
603a98e7 5233*mipsV:
1e799e28 5234*mips32:
e70cb6cd 5235*mips32r2:
1e799e28 5236*mips64:
e70cb6cd 5237*mips64r2:
c906108c
SS		 5238*vr4100:
5239*vr5000:
5240*r3900:
5241{
c1e8ada4 5242 int fmt = FMT;
9b17d183 5243 check_fpu (SD_);
d18ea9c2 5244 StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
c906108c
SS		 5245}
5246
5247
14234056 5248010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
c906108c 5249"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 5250*mipsI:
5251*mipsII:
5252*mipsIII:
5253*mipsIV:
603a98e7 5254*mipsV:
1e799e28 5255*mips32:
e70cb6cd 5256*mips32r2:
1e799e28 5257*mips64:
e70cb6cd 5258*mips64r2:
c906108c
SS		 5259*vr4100:
5260*vr5000:
5261*r3900:
5262{
c1e8ada4 5263 int fmt = FMT;
9b17d183 5264 check_fpu (SD_);
8612006b 5265 check_fmt_p (SD_, fmt, instruction_0);
d18ea9c2 5266 StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
c906108c
SS		 5267}
5268
5269
5270
eb5fcf93 5271111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
c906108c 5272"swc1 f<FT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 5273*mipsI:
5274*mipsII:
5275*mipsIII:
5276*mipsIV:
603a98e7 5277*mipsV:
1e799e28 5278*mips32:
e70cb6cd 5279*mips32r2:
1e799e28 5280*mips64:
e70cb6cd 5281*mips64r2:
c906108c
SS		 5282*vr4100:
5283*vr5000:
5284*r3900:
5285{
09297648
CD		 5286 address_word base = GPR[BASE];
5287 address_word offset = EXTEND16 (OFFSET);
9b17d183 5288 check_fpu (SD_);
c906108c 5289 {
09297648 5290 address_word vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 5291 address_word paddr;
5292 int uncached;
5293 if ((vaddr & 3) != 0)
5294 {
5295 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
5296 }
5297 else
5298 {
5299 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5300 {
5301 uword64 memval = 0;
5302 uword64 memval1 = 0;
5303 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5304 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5305 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5306 unsigned int byte;
5307 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5308 byte = ((vaddr & mask) ^ bigendiancpu);
c1e8ada4 5309 memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
c906108c
SS		 5310 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5311 }
5312 }
5313 }
5314}
5315
5316
eb5fcf93 5317010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
c906108c
SS		 5318"swxc1 f<FS>, r<INDEX>(r<BASE>)"
5319*mipsIV:
603a98e7 5320*mipsV:
1e799e28 5321*mips64:
e70cb6cd 5322*mips64r2:
c906108c
SS		 5323*vr5000:
5324{
c1e8ada4
CD		 5325
5326 address_word base = GPR[BASE];
5327 address_word index = GPR[INDEX];
9b17d183 5328 check_fpu (SD_);
ca971540 5329 check_u64 (SD_, instruction_0);
c906108c 5330 {
09297648 5331 address_word vaddr = loadstore_ea (SD_, base, index);
c906108c
SS		 5332 address_word paddr;
5333 int uncached;
5334 if ((vaddr & 3) != 0)
5335 {
5336 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
5337 }
5338 else
5339 {
5340 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5341 {
5342 unsigned64 memval = 0;
5343 unsigned64 memval1 = 0;
5344 unsigned64 mask = 0x7;
5345 unsigned int byte;
5346 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5347 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
c1e8ada4 5348 memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
c906108c
SS		 5349 {
5350 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5351 }
5352 }
5353 }
5354 }
5355}
5356
5357
14234056 5358010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
c906108c
SS		 5359"trunc.l.%s<FMT> f<FD>, f<FS>"
5360*mipsIII:
5361*mipsIV:
603a98e7 5362*mipsV:
1e799e28 5363*mips64:
e70cb6cd 5364*mips64r2:
c906108c
SS		 5365*vr4100:
5366*vr5000:
5367*r3900:
5368{
c1e8ada4 5369 int fmt = FMT;
9b17d183 5370 check_fpu (SD_);
d18ea9c2
CD		 5371 StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5372 fmt_long));
c906108c
SS		 5373}
5374
5375
14234056 5376010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
c906108c
SS		 5377"trunc.w.%s<FMT> f<FD>, f<FS>"
5378*mipsII:
5379*mipsIII:
5380*mipsIV:
603a98e7 5381*mipsV:
1e799e28 5382*mips32:
e70cb6cd 5383*mips32r2:
1e799e28 5384*mips64:
e70cb6cd 5385*mips64r2:
c906108c
SS		 5386*vr4100:
5387*vr5000:
5388*r3900:
5389{
c1e8ada4 5390 int fmt = FMT;
9b17d183 5391 check_fpu (SD_);
d18ea9c2
CD		 5392 StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5393 fmt_word));
c906108c
SS		 5394}
5395
5396\f
5397//
5398// MIPS Architecture:
5399//
5400// System Control Instruction Set (COP0)
5401//
5402
5403
5404010000,01000,00000,16.OFFSET:COP0:32::BC0F
5405"bc0f <OFFSET>"
c5d00cc7
CD		 5406*mipsI:
5407*mipsII:
5408*mipsIII:
5409*mipsIV:
603a98e7 5410*mipsV:
1e799e28 5411*mips32:
e70cb6cd 5412*mips32r2:
1e799e28 5413*mips64:
e70cb6cd 5414*mips64r2:
c906108c
SS		 5415*vr4100:
5416*vr5000:
5417
7a292a7a
SS		 5418010000,01000,00000,16.OFFSET:COP0:32::BC0F
5419"bc0f <OFFSET>"
5420// stub needed for eCos as tx39 hardware bug workaround
5421*r3900:
5422{
5423 /* do nothing */
5424}
5425
c906108c
SS		 5426
5427010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5428"bc0fl <OFFSET>"
c5d00cc7
CD		 5429*mipsI:
5430*mipsII:
5431*mipsIII:
5432*mipsIV:
603a98e7 5433*mipsV:
1e799e28 5434*mips32:
e70cb6cd 5435*mips32r2:
1e799e28 5436*mips64:
e70cb6cd 5437*mips64r2:
c906108c
SS		 5438*vr4100:
5439*vr5000:
5440
5441
5442010000,01000,00001,16.OFFSET:COP0:32::BC0T
5443"bc0t <OFFSET>"
c5d00cc7
CD		 5444*mipsI:
5445*mipsII:
5446*mipsIII:
5447*mipsIV:
603a98e7 5448*mipsV:
1e799e28 5449*mips32:
e70cb6cd 5450*mips32r2:
1e799e28 5451*mips64:
e70cb6cd 5452*mips64r2:
c906108c
SS		 5453*vr4100:
5454
5455
5456010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5457"bc0tl <OFFSET>"
c5d00cc7
CD		 5458*mipsI:
5459*mipsII:
5460*mipsIII:
5461*mipsIV:
603a98e7 5462*mipsV:
1e799e28 5463*mips32:
e70cb6cd 5464*mips32r2:
1e799e28 5465*mips64:
e70cb6cd 5466*mips64r2:
c906108c
SS		 5467*vr4100:
5468*vr5000:
5469
5470
5471101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
0d3e762b 5472"cache <OP>, <OFFSET>(r<BASE>)"
c906108c
SS		 5473*mipsIII:
5474*mipsIV:
603a98e7 5475*mipsV:
1e799e28 5476*mips32:
e70cb6cd 5477*mips32r2:
1e799e28 5478*mips64:
e70cb6cd 5479*mips64r2:
c906108c
SS		 5480*vr4100:
5481*vr5000:
5482*r3900:
5483{
c1e8ada4
CD		 5484 address_word base = GPR[BASE];
5485 address_word offset = EXTEND16 (OFFSET);
c906108c 5486 {
09297648 5487 address_word vaddr = loadstore_ea (SD_, base, offset);
c906108c
SS		 5488 address_word paddr;
5489 int uncached;
5490 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
c1e8ada4 5491 CacheOp(OP,vaddr,paddr,instruction_0);
c906108c
SS		 5492 }
5493}
5494
5495
f701dad2 5496010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
9846de1b 5497"dmfc0 r<RT>, r<RD>"
c5d00cc7
CD		 5498*mipsIII:
5499*mipsIV:
603a98e7 5500*mipsV:
1e799e28 5501*mips64:
e70cb6cd 5502*mips64r2:
9846de1b 5503{
ca971540 5504 check_u64 (SD_, instruction_0);
9846de1b
JM		 5505 DecodeCoproc (instruction_0);
5506}
5507
5508
f701dad2 5509010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
9846de1b 5510"dmtc0 r<RT>, r<RD>"
c5d00cc7
CD		 5511*mipsIII:
5512*mipsIV:
603a98e7 5513*mipsV:
1e799e28 5514*mips64:
e70cb6cd 5515*mips64r2:
9846de1b 5516{
ca971540 5517 check_u64 (SD_, instruction_0);
9846de1b
JM		 5518 DecodeCoproc (instruction_0);
5519}
5520
5521
f701dad2 5522010000,1,0000000000000000000,011000:COP0:32::ERET
c906108c
SS		 5523"eret"
5524*mipsIII:
5525*mipsIV:
603a98e7 5526*mipsV:
1e799e28 5527*mips32:
e70cb6cd 5528*mips32r2:
1e799e28 5529*mips64:
e70cb6cd 5530*mips64r2:
c906108c
SS		 5531*vr4100:
5532*vr5000:
5533{
5534 if (SR & status_ERL)
5535 {
5536 /* Oops, not yet available */
5537 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5538 NIA = EPC;
5539 SR &= ~status_ERL;
5540 }
5541 else
5542 {
5543 NIA = EPC;
5544 SR &= ~status_EXL;
5545 }
5546}
5547
5548
5549010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5550"mfc0 r<RT>, r<RD> # <REGX>"
c5d00cc7
CD		 5551*mipsI:
5552*mipsII:
5553*mipsIII:
5554*mipsIV:
603a98e7 5555*mipsV:
1e799e28 5556*mips32:
e70cb6cd 5557*mips32r2:
1e799e28 5558*mips64:
e70cb6cd 5559*mips64r2:
c906108c
SS		 5560*vr4100:
5561*vr5000:
074e9cb8 5562*r3900:
c906108c
SS		 5563{
5564 TRACE_ALU_INPUT0 ();
5565 DecodeCoproc (instruction_0);
5566 TRACE_ALU_RESULT (GPR[RT]);
5567}
5568
5569010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5570"mtc0 r<RT>, r<RD> # <REGX>"
c5d00cc7
CD		 5571*mipsI:
5572*mipsII:
5573*mipsIII:
5574*mipsIV:
603a98e7 5575*mipsV:
1e799e28 5576*mips32:
e70cb6cd 5577*mips32r2:
1e799e28 5578*mips64:
e70cb6cd 5579*mips64r2:
c906108c
SS		 5580*vr4100:
5581*vr5000:
074e9cb8 5582*r3900:
c906108c
SS		 5583{
5584 DecodeCoproc (instruction_0);
5585}
5586
5587
f701dad2 5588010000,1,0000000000000000000,010000:COP0:32::RFE
c906108c 5589"rfe"
c5d00cc7
CD		 5590*mipsI:
5591*mipsII:
5592*mipsIII:
5593*mipsIV:
603a98e7 5594*mipsV:
c906108c
SS		 5595*vr4100:
5596*vr5000:
074e9cb8 5597*r3900:
c906108c
SS		 5598{
5599 DecodeCoproc (instruction_0);
5600}
5601
5602
56030100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5604"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
c5d00cc7
CD		 5605*mipsI:
5606*mipsII:
5607*mipsIII:
5608*mipsIV:
603a98e7 5609*mipsV:
1e799e28 5610*mips32:
e70cb6cd 5611*mips32r2:
1e799e28 5612*mips64:
e70cb6cd 5613*mips64r2:
c906108c
SS		 5614*vr4100:
5615*r3900:
5616{
5617 DecodeCoproc (instruction_0);
5618}
5619
5620
5621
f701dad2 5622010000,1,0000000000000000000,001000:COP0:32::TLBP
c906108c 5623"tlbp"
c5d00cc7
CD		 5624*mipsI:
5625*mipsII:
5626*mipsIII:
5627*mipsIV:
603a98e7 5628*mipsV:
1e799e28 5629*mips32:
e70cb6cd 5630*mips32r2:
1e799e28 5631*mips64:
e70cb6cd 5632*mips64r2:
c906108c
SS		 5633*vr4100:
5634*vr5000:
5635
5636
f701dad2 5637010000,1,0000000000000000000,000001:COP0:32::TLBR
c906108c 5638"tlbr"
c5d00cc7
CD		 5639*mipsI:
5640*mipsII:
5641*mipsIII:
5642*mipsIV:
603a98e7 5643*mipsV:
1e799e28 5644*mips32:
e70cb6cd 5645*mips32r2:
1e799e28 5646*mips64:
e70cb6cd 5647*mips64r2:
c906108c
SS		 5648*vr4100:
5649*vr5000:
5650
5651
f701dad2 5652010000,1,0000000000000000000,000010:COP0:32::TLBWI
c906108c 5653"tlbwi"
c5d00cc7
CD		 5654*mipsI:
5655*mipsII:
5656*mipsIII:
5657*mipsIV:
603a98e7 5658*mipsV:
1e799e28 5659*mips32:
e70cb6cd 5660*mips32r2:
1e799e28 5661*mips64:
e70cb6cd 5662*mips64r2:
c906108c
SS		 5663*vr4100:
5664*vr5000:
5665
5666
f701dad2 5667010000,1,0000000000000000000,000110:COP0:32::TLBWR
c906108c 5668"tlbwr"
c5d00cc7
CD		 5669*mipsI:
5670*mipsII:
5671*mipsIII:
5672*mipsIV:
603a98e7 5673*mipsV:
1e799e28 5674*mips32:
e70cb6cd 5675*mips32r2:
1e799e28 5676*mips64:
e70cb6cd 5677*mips64r2:
c906108c
SS		 5678*vr4100:
5679*vr5000:
5680
e70cb6cd
CD		 5681
5682:include:::mips3264r2.igen
c906108c 5683:include:::m16.igen
b16d63da 5684:include:::m16e.igen
f4f1b9f1 5685:include:::mdmx.igen
e7e81181 5686:include:::mips3d.igen
7cbea089 5687:include:::sb1.igen
c906108c
SS		 5688:include:::tx.igen
5689:include:::vr.igen
40a5538e 5690:include:::dsp.igen
2d2733fc 5691:include:::smartmips.igen
e70cb6cd 5692
GDB Binutils - Deliverables
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