Commit | Line | Data |
---|---|---|
f2b30012 AC |
1 | // <insn> ::= |
2 | // <insn-word> { "+" <insn-word> } | |
3 | // ":" <format-name> | |
4 | // ":" <filter-flags> | |
5 | // ":" <options> | |
6 | // ":" <name> | |
7 | // <nl> | |
8 | // { <insn-model> } | |
9 | // { <insn-mnemonic> } | |
10 | // <code-block> | |
11 | // | |
12 | ||
13 | ||
14 | // IGEN config - mips16 | |
15 | :option:16:insn-bit-size:16 | |
16 | :option:16:hi-bit-nr:15 | |
17 | :option:16:insn-specifying-widths:true | |
18 | ||
19 | // IGEN config - mipsI.. | |
20 | :option:32:insn-bit-size:32 | |
21 | :option:32:hi-bit-nr:31 | |
22 | :option:32:insn-specifying-widths:true | |
23 | ||
24 | ||
49a6eed5 AC |
25 | // Generate separate simulators for each target |
26 | :option::multi-sim:true | |
27 | ||
f2b30012 AC |
28 | |
29 | // Models known by this simulator | |
30 | :model::mipsI:mipsI: | |
31 | :model::mipsII:mipsII: | |
32 | :model::mipsIII:mipsIII: | |
33 | :model::mipsIV:mipsIV: | |
34 | :model::mips16:mips16: | |
35 | // start-sanitize-r5900 | |
36 | :model::r5900:r5900: | |
37 | // end-sanitize-r5900 | |
38 | :model::r3900:r3900: | |
39 | // start-sanitize-tx19 | |
40 | :model::tx19:tx19: | |
41 | // end-sanitize-tx19 | |
42 | ||
43 | ||
44 | ||
45 | // Pseudo instructions known by IGEN | |
46 | :internal:::illegal | |
47 | { | |
48 | sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n", | |
49 | (unsigned long) cia); | |
50 | sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL); | |
51 | } | |
52 | ||
53 | ||
54 | ||
55 | ||
56 | // | |
57 | // MIPS Architecture: | |
58 | // | |
59 | // CPU Instruction Set (mipsI - mipsIV) | |
60 | // | |
61 | ||
62 | ||
63 | 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD | |
64 | "add r<RD>, r<RS>, r<RT>" | |
65 | *mipsI: | |
66 | *mipsII: | |
67 | *mipsIII: | |
68 | *mipsIV: | |
69 | // start-sanitize-r5900 | |
70 | *r5900: | |
71 | // end-sanitize-r5900 | |
72 | *r3900: | |
73 | // start-sanitize-tx19 | |
74 | *tx19: | |
75 | // end-sanitize-tx19 | |
76 | { | |
77 | ALU32_BEGIN (GPR (RS)); | |
78 | ALU32_ADD (GPR (RT)); | |
79 | ALU32_END (GPR (RD)); | |
80 | } | |
81 | ||
82 | ||
83 | 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI | |
84 | "addi r<RT>, r<RS>, IMMEDIATE" | |
85 | *mipsI: | |
86 | *mipsII: | |
87 | *mipsIII: | |
88 | *mipsIV: | |
89 | // start-sanitize-r5900 | |
90 | *r5900: | |
91 | // end-sanitize-r5900 | |
92 | *r3900: | |
93 | // start-sanitize-tx19 | |
94 | *tx19: | |
95 | // end-sanitize-tx19 | |
96 | { | |
97 | ALU32_BEGIN (GPR (RS)); | |
98 | ALU32_ADD (EXTEND16 (IMMEDIATE)); | |
99 | ALU32_END (GPR (RT)); | |
100 | } | |
101 | ||
102 | ||
103 | 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU | |
104 | "add r<RT>, r<RS>, IMMEDIATE" | |
105 | *mipsI: | |
106 | *mipsII: | |
107 | *mipsIII: | |
108 | *mipsIV: | |
109 | // start-sanitize-r5900 | |
110 | *r5900: | |
111 | // end-sanitize-r5900 | |
112 | *r3900: | |
113 | // start-sanitize-tx19 | |
114 | *tx19: | |
115 | // end-sanitize-tx19 | |
116 | { | |
117 | signed32 temp = GPR (RS) + EXTEND16 (IMMEDIATE); | |
118 | GPR (RT) = EXTEND32 (temp); | |
119 | } | |
120 | ||
121 | ||
122 | 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU | |
123 | *mipsI: | |
124 | *mipsII: | |
125 | *mipsIII: | |
126 | *mipsIV: | |
127 | // start-sanitize-r5900 | |
128 | *r5900: | |
129 | // end-sanitize-r5900 | |
130 | *r3900: | |
131 | // start-sanitize-tx19 | |
132 | *tx19: | |
133 | // end-sanitize-tx19 | |
134 | { | |
135 | signed32 temp = GPR (RS) + GPR (RT); | |
136 | GPR (RD) = EXTEND32 (temp); | |
137 | } | |
138 | ||
139 | ||
140 | 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND | |
141 | "and r<RD>, r<RS>, r<RT>" | |
142 | *mipsI: | |
143 | *mipsII: | |
144 | *mipsIII: | |
145 | *mipsIV: | |
146 | // start-sanitize-r5900 | |
147 | *r5900: | |
148 | // end-sanitize-r5900 | |
149 | *r3900: | |
150 | // start-sanitize-tx19 | |
151 | *tx19: | |
152 | // end-sanitize-tx19 | |
153 | { | |
154 | GPR (RD) = GPR (RS) & GPR (RT); | |
155 | } | |
156 | ||
157 | ||
158 | 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI | |
159 | "and r<RT>, r<RS>, IMMEDIATE" | |
160 | *mipsI: | |
161 | *mipsII: | |
162 | *mipsIII: | |
163 | // start-sanitize-r5900 | |
164 | *r5900: | |
165 | // end-sanitize-r5900 | |
166 | *r3900: | |
167 | // start-sanitize-tx19 | |
168 | *tx19: | |
169 | // end-sanitize-tx19 | |
170 | { | |
171 | GPR (RT) = GPR (RS) & IMMEDIATE; | |
172 | } | |
173 | ||
174 | ||
175 | 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ | |
176 | "beq r<RS>, r<RT>, OFFSET" | |
177 | *mipsI: | |
178 | *mipsII: | |
179 | *mipsIII: | |
180 | *mipsIV: | |
181 | // start-sanitize-r5900 | |
182 | *r5900: | |
183 | // end-sanitize-r5900 | |
184 | *r3900: | |
185 | // start-sanitize-tx19 | |
186 | *tx19: | |
187 | // end-sanitize-tx19 | |
188 | { | |
189 | /* NOTE: The branch occurs AFTER the next instruction has been | |
190 | executed */ | |
191 | if (GPR (RS) == GPR (RT)) | |
192 | { | |
193 | DSPC = (PC + offset); | |
194 | DELAYSLOT (); | |
195 | } | |
196 | } | |
197 | ||
198 | ||
199 | 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL | |
200 | "beql r<RS>, r<RT>, <OFFSET>" | |
201 | *mipsII: | |
202 | *mipsIII: | |
203 | *mipsIV: | |
204 | // start-sanitize-r5900 | |
205 | *r5900: | |
206 | // end-sanitize-r5900 | |
207 | *r3900: | |
208 | // start-sanitize-tx19 | |
209 | *tx19: | |
210 | // end-sanitize-tx19 | |
211 | { | |
212 | /* NOTE: The branch occurs AFTER the next instruction has been | |
213 | executed */ | |
214 | if (GPR (RS) == GPR (RT)) | |
215 | { | |
216 | DSPC = (PC + offset); | |
217 | DELAYSLOT (); | |
218 | } | |
219 | else | |
220 | NULLIFY(); | |
221 | } | |
222 | ||
223 | ||
224 | 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ | |
225 | "bgez r<RS>, <OFFSET>" | |
226 | *mipsI: | |
227 | *mipsII: | |
228 | *mipsIII: | |
229 | *mipsIV: | |
230 | // start-sanitize-r5900 | |
231 | *r5900: | |
232 | // end-sanitize-r5900 | |
233 | *r3900: | |
234 | // start-sanitize-tx19 | |
235 | *tx19: | |
236 | // end-sanitize-tx19 | |
237 | { | |
238 | /* NOTE: The branch occurs AFTER the next instruction has been | |
239 | executed */ | |
240 | if (GPR (RS) >= 0) | |
241 | { | |
242 | DSPC = (PC + offset); | |
243 | DELAYSLOT (); | |
244 | } | |
245 | } | |
246 | ||
247 | ||
248 | 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL | |
249 | "bgezal r<RS>, <OFFSET>" | |
250 | *mipsI: | |
251 | *mipsII: | |
252 | *mipsIII: | |
253 | *mipsIV: | |
254 | // start-sanitize-r5900 | |
255 | *r5900: | |
256 | // end-sanitize-r5900 | |
257 | *r3900: | |
258 | // start-sanitize-tx19 | |
259 | *tx19: | |
260 | // end-sanitize-tx19 | |
261 | { | |
262 | LR = (CIA + 8); | |
263 | /* NOTE: The branch occurs AFTER the next instruction has been | |
264 | executed */ | |
265 | if (GPR (RS) >= 0) | |
266 | { | |
267 | DSPC = (PC + offset); | |
268 | DELAYSLOT(); | |
269 | } | |
270 | } | |
271 | ||
272 | ||
273 | 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL | |
274 | "bgezall r<RS>, <OFFSET>" | |
275 | *mipsII: | |
276 | *mipsIII: | |
277 | *mipsIV: | |
278 | // start-sanitize-r5900 | |
279 | *r5900: | |
280 | // end-sanitize-r5900 | |
281 | *r3900: | |
282 | // start-sanitize-tx19 | |
283 | *tx19: | |
284 | // end-sanitize-tx19 | |
285 | { | |
286 | LR = (CIA + 8); | |
287 | /* NOTE: The branch occurs AFTER the next instruction has been | |
288 | executed */ | |
289 | if (GPR (RS) >= 0) | |
290 | { | |
291 | DSPC = (PC + offset); | |
292 | DELAYSLOT (); | |
293 | } | |
294 | else | |
295 | NULLIFY (); | |
296 | } | |
297 | ||
298 | ||
299 | 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL | |
300 | "bgezl r<RS>, <OFFSET>" | |
301 | *mipsII: | |
302 | *mipsIII: | |
303 | *mipsIV: | |
304 | // start-sanitize-r5900 | |
305 | *r5900: | |
306 | // end-sanitize-r5900 | |
307 | *r3900: | |
308 | // start-sanitize-tx19 | |
309 | *tx19: | |
310 | // end-sanitize-tx19 | |
311 | { | |
312 | /* NOTE: The branch occurs AFTER the next instruction has been | |
313 | executed */ | |
314 | if (GPR (RS) >= 0) | |
315 | { | |
316 | DSPC = (PC + offset); | |
317 | DELAYSLOT(); | |
318 | } | |
319 | else | |
320 | NULLIFY (); | |
321 | } | |
322 | ||
323 | ||
324 | 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ | |
325 | "bgtz r<RS>, <OFFSET>" | |
326 | *mipsI: | |
327 | *mipsII: | |
328 | *mipsIII: | |
329 | *mipsIV: | |
330 | // start-sanitize-r5900 | |
331 | *r5900: | |
332 | // end-sanitize-r5900 | |
333 | *r3900: | |
334 | // start-sanitize-tx19 | |
335 | *tx19: | |
336 | // end-sanitize-tx19 | |
337 | { | |
338 | /* NOTE: The branch occurs AFTER the next instruction has been | |
339 | executed */ | |
340 | if (GPR (RS) > 0) | |
341 | { | |
342 | DSPC = (PC + offset); | |
343 | DELAYSLOT (); | |
344 | } | |
345 | } | |
346 | ||
347 | ||
348 | 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL | |
349 | "bgtzl r<RS>, <OFFSET>" | |
350 | *mipsII: | |
351 | *mipsIII: | |
352 | *mipsIV: | |
353 | // start-sanitize-r5900 | |
354 | *r5900: | |
355 | // end-sanitize-r5900 | |
356 | *r3900: | |
357 | // start-sanitize-tx19 | |
358 | *tx19: | |
359 | // end-sanitize-tx19 | |
360 | { | |
361 | /* NOTE: The branch occurs AFTER the next instruction has been | |
362 | executed */ | |
363 | if (GPR (RS) > 0) | |
364 | { | |
365 | DSPC = (PC + offset); | |
366 | DELAYSLOT (); | |
367 | } | |
368 | else | |
369 | NULLIFY (); | |
370 | } | |
371 | ||
372 | ||
373 | 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ | |
374 | "blez r<RS>, <OFFSET>" | |
375 | *mipsI: | |
376 | *mipsII: | |
377 | *mipsIII: | |
378 | *mipsIV: | |
379 | // start-sanitize-r5900 | |
380 | *r5900: | |
381 | // end-sanitize-r5900 | |
382 | *r3900: | |
383 | // start-sanitize-tx19 | |
384 | *tx19: | |
385 | // end-sanitize-tx19 | |
386 | { | |
387 | /* NOTE: The branch occurs AFTER the next instruction has been | |
388 | executed */ | |
389 | if (GPR (RS) <= 0) | |
390 | { | |
391 | DSPC = (PC + offset); | |
392 | DELAYSLOT (); | |
393 | } | |
394 | } | |
395 | ||
396 | ||
397 | 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL | |
398 | "bgezl r<RS>, <OFFSET>" | |
399 | *mipsII: | |
400 | *mipsIII: | |
401 | *mipsIV: | |
402 | // start-sanitize-r5900 | |
403 | *r5900: | |
404 | // end-sanitize-r5900 | |
405 | *r3900: | |
406 | // start-sanitize-tx19 | |
407 | *tx19: | |
408 | // end-sanitize-tx19 | |
409 | { | |
410 | /* NOTE: The branch occurs AFTER the next instruction has been | |
411 | executed */ | |
412 | if (GPR (RS) <= 0) | |
413 | { | |
414 | DSPC = (PC + offset); | |
415 | DELAYSLOT (); | |
416 | } | |
417 | else | |
418 | NULLIFY (); | |
419 | } | |
420 | ||
421 | ||
422 | 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ | |
423 | "bltz r<RS>, <OFFSET>" | |
424 | *mipsI: | |
425 | *mipsII: | |
426 | *mipsIII: | |
427 | *mipsIV: | |
428 | // start-sanitize-r5900 | |
429 | *r5900: | |
430 | // end-sanitize-r5900 | |
431 | *r3900: | |
432 | // start-sanitize-tx19 | |
433 | *tx19: | |
434 | // end-sanitize-tx19 | |
435 | { | |
436 | /* NOTE: The branch occurs AFTER the next instruction has been | |
437 | executed */ | |
438 | if (GPR (RS) < 0) | |
439 | { | |
440 | DSPC = (PC + offset); | |
441 | DELAYSLOT (); | |
442 | } | |
443 | } | |
444 | ||
445 | ||
446 | 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL | |
447 | "bltzal r<RS>, <OFFSET>" | |
448 | *mipsI: | |
449 | *mipsII: | |
450 | *mipsIII: | |
451 | *mipsIV: | |
452 | // start-sanitize-r5900 | |
453 | *r5900: | |
454 | // end-sanitize-r5900 | |
455 | *r3900: | |
456 | // start-sanitize-tx19 | |
457 | *tx19: | |
458 | // end-sanitize-tx19 | |
459 | { | |
460 | LR = (CIA + 8); | |
461 | /* NOTE: The branch occurs AFTER the next instruction has been | |
462 | executed */ | |
463 | if (GPR (RS) < 0) | |
464 | { | |
465 | DSPC = (PC + offset); | |
466 | DELAYSLOT (); | |
467 | } | |
468 | } | |
469 | ||
470 | ||
471 | 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL | |
472 | "bltzall r<RS>, <OFFSET>" | |
473 | *mipsII: | |
474 | *mipsIII: | |
475 | *mipsIV: | |
476 | // start-sanitize-r5900 | |
477 | *r5900: | |
478 | // end-sanitize-r5900 | |
479 | *r3900: | |
480 | // start-sanitize-tx19 | |
481 | *tx19: | |
482 | // end-sanitize-tx19 | |
483 | { | |
484 | LR = (CIA + 8); | |
485 | /* NOTE: The branch occurs AFTER the next instruction has been | |
486 | executed */ | |
487 | if (GPR (RS) < 0) | |
488 | { | |
489 | DSPC = (PC + offset); | |
490 | DELAYSLOT (); | |
491 | } | |
492 | else | |
493 | NULLIFY (); | |
494 | } | |
495 | ||
496 | ||
497 | 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL | |
498 | "bltzl r<RS>, <OFFSET>" | |
499 | *mipsII: | |
500 | *mipsIII: | |
501 | *mipsIV: | |
502 | // start-sanitize-r5900 | |
503 | *r5900: | |
504 | // end-sanitize-r5900 | |
505 | *r3900: | |
506 | // start-sanitize-tx19 | |
507 | *tx19: | |
508 | // end-sanitize-tx19 | |
509 | { | |
510 | /* NOTE: The branch occurs AFTER the next instruction has been | |
511 | executed */ | |
512 | if (GPR (RS) < 0) | |
513 | { | |
514 | DSPC = (PC + offset); | |
515 | DELAYSLOT (); | |
516 | } | |
517 | else | |
518 | NULLIFY (); | |
519 | } | |
520 | ||
521 | ||
522 | 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE | |
523 | "bne r<RS>, r<RT>, <OFFSET>" | |
524 | *mipsI: | |
525 | *mipsII: | |
526 | *mipsIII: | |
527 | *mipsIV: | |
528 | // start-sanitize-r5900 | |
529 | *r5900: | |
530 | // end-sanitize-r5900 | |
531 | *r3900: | |
532 | // start-sanitize-tx19 | |
533 | *tx19: | |
534 | // end-sanitize-tx19 | |
535 | { | |
536 | /* NOTE: The branch occurs AFTER the next instruction has been | |
537 | executed */ | |
538 | if (GPR (RS) != GPR (RT)) | |
539 | { | |
540 | DSPC = (PC + offset); | |
541 | DELAYSLOT (); | |
542 | } | |
543 | } | |
544 | ||
545 | ||
546 | 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL | |
547 | "bnel r<RS>, r<RT>, <OFFSET>" | |
548 | *mipsII: | |
549 | *mipsIII: | |
550 | *mipsIV: | |
551 | // start-sanitize-r5900 | |
552 | *r5900: | |
553 | // end-sanitize-r5900 | |
554 | *r3900: | |
555 | // start-sanitize-tx19 | |
556 | *tx19: | |
557 | // end-sanitize-tx19 | |
558 | { | |
559 | /* NOTE: The branch occurs AFTER the next instruction has been | |
560 | executed */ | |
561 | if (GPR (RS) != GPR (RT)) | |
562 | { | |
563 | DSPC = (PC + offset); | |
564 | DELAYSLOT (); | |
565 | } | |
566 | else | |
567 | NULLIFY (); | |
568 | } | |
569 | ||
570 | ||
49a6eed5 | 571 | 000000,20.CODE,001101:SPECIAL:32::BREAK |
f2b30012 AC |
572 | "break" |
573 | *mipsI: | |
574 | *mipsII: | |
575 | *mipsIII: | |
576 | *mipsIV: | |
577 | // start-sanitize-r5900 | |
578 | *r5900: | |
579 | // end-sanitize-r5900 | |
580 | *r3900: | |
581 | // start-sanitize-tx19 | |
582 | *tx19: | |
583 | // end-sanitize-tx19 | |
584 | { | |
585 | SignalException (BreakPoint, instruction_0); | |
586 | } | |
587 | ||
588 | ||
49a6eed5 | 589 | 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz |
f2b30012 AC |
590 | "cop<ZZ> <COP_FUN>" |
591 | *mipsI: | |
592 | *mipsII: | |
593 | *mipsIII: | |
594 | *mipsIV: | |
595 | // start-sanitize-r5900 | |
596 | *r5900: | |
597 | // end-sanitize-r5900 | |
598 | *r3900: | |
599 | // start-sanitize-tx19 | |
600 | *tx19: | |
601 | // end-sanitize-tx19 | |
602 | { | |
603 | decode_coproc (SD_, ZZ, COP_FUN); | |
604 | } | |
605 | ||
606 | ||
607 | 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD | |
608 | "dadd r<RD>, r<RS>, r<RT>" | |
609 | *mipsIII: | |
610 | *mipsIV: | |
611 | // start-sanitize-r5900 | |
612 | *r5900: | |
613 | // end-sanitize-r5900 | |
614 | *r3900: | |
615 | // start-sanitize-tx19 | |
616 | *tx19: | |
617 | // end-sanitize-tx19 | |
618 | { | |
619 | ALU64_START (GPR (RS)); | |
620 | ALU64_ADD (GPR (RT)); | |
621 | ALU64_RESULT (GPR (RT)); | |
622 | } | |
623 | ||
624 | ||
625 | 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI | |
626 | "daddi r<RT>, r<RS>, <IMMEDIATE>" | |
627 | *mipsIII: | |
628 | *mipsIV: | |
629 | // start-sanitize-r5900 | |
630 | *r5900: | |
631 | // end-sanitize-r5900 | |
632 | *r3900: | |
633 | // start-sanitize-tx19 | |
634 | *tx19: | |
635 | // end-sanitize-tx19 | |
636 | { | |
637 | ALU64_START (GPR (RS)); | |
638 | ALU64_ADD (EXTEND16 (IMMEDIATE)); | |
639 | ALU64_RESULT (GPR (RT)); | |
640 | } | |
641 | ||
642 | ||
643 | 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU | |
644 | "daddu r<RT>, r<RS>, <IMMEDIATE>" | |
645 | *mipsIII: | |
646 | *mipsIV: | |
647 | // start-sanitize-r5900 | |
648 | *r5900: | |
649 | // end-sanitize-r5900 | |
650 | *r3900: | |
651 | // start-sanitize-tx19 | |
652 | *tx19: | |
653 | // end-sanitize-tx19 | |
654 | { | |
655 | GPR (RT) = GPR (RS) + EXTEND16 (immediate); | |
656 | } | |
657 | ||
658 | ||
659 | 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU | |
660 | "daddu r<RD>, r<RS>, r<RT>" | |
661 | *mipsIII: | |
662 | *mipsIV: | |
663 | // start-sanitize-r5900 | |
664 | *r5900: | |
665 | // end-sanitize-r5900 | |
666 | *r3900: | |
667 | // start-sanitize-tx19 | |
668 | *tx19: | |
669 | // end-sanitize-tx19 | |
670 | { | |
671 | GPR (RD) = GPR (RS) + GPR (RT); | |
672 | } | |
673 | ||
674 | ||
675 | 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV | |
676 | "ddiv r<RS>, r<RT>" | |
677 | *mipsIII: | |
678 | *mipsIV: | |
679 | // start-sanitize-r5900 | |
680 | *r5900: | |
681 | // end-sanitize-r5900 | |
682 | *r3900: | |
683 | // start-sanitize-tx19 | |
684 | *tx19: | |
685 | // end-sanitize-tx19 | |
686 | { | |
687 | CHECKHILO ("Division"); | |
688 | { | |
689 | signed64 n = GPR (RS); | |
690 | signed64 d = GPR (RT); | |
691 | if (d == 0) | |
692 | { | |
693 | LO = SIGNED64 (0x8000000000000000); | |
694 | HI = 0; | |
695 | } | |
696 | else if (d == -1 && n == SIGNED64 (0x8000000000000000)) | |
697 | { | |
698 | LO = SIGNED64 (0x8000000000000000); | |
699 | HI = 0; | |
700 | } | |
701 | else | |
702 | { | |
703 | LO = (n / d); | |
704 | HI = (n % d); | |
705 | } | |
706 | } | |
707 | } | |
708 | ||
709 | ||
710 | ||
711 | 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU | |
712 | "ddivu r<RS>, r<RT>" | |
713 | *mipsIII: | |
714 | *mipsIV: | |
715 | *r3900: | |
716 | // start-sanitize-tx19 | |
717 | *tx19: | |
718 | // end-sanitize-tx19 | |
719 | { | |
720 | CHECKHILO ("Division"); | |
721 | { | |
722 | unsigned64 n = GPR (RS); | |
723 | unsigned64 d = GPR (RT); | |
724 | if (d == 0) | |
725 | { | |
726 | LO = SIGNED64 (0x8000000000000000); | |
727 | HI = 0; | |
728 | } | |
729 | else | |
730 | { | |
731 | LO = (n / d); | |
732 | HI = (n % d); | |
733 | } | |
734 | } | |
735 | } | |
736 | ||
737 | ||
738 | 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV | |
739 | "div r<RS>, r<RT>" | |
740 | *mipsI: | |
741 | *mipsII: | |
742 | *mipsIII: | |
743 | *mipsIV: | |
744 | // start-sanitize-r5900 | |
745 | *r5900: | |
746 | // end-sanitize-r5900 | |
747 | *r3900: | |
748 | // start-sanitize-tx19 | |
749 | *tx19: | |
750 | // end-sanitize-tx19 | |
751 | { | |
752 | CHECKHILO("Division"); | |
753 | { | |
754 | signed32 n = GPR (RS); | |
755 | signed32 d = GPR (RT); | |
756 | if (d == 0) | |
757 | { | |
758 | LO = EXTEND32 (0x80000000); | |
759 | HI = EXTEND32 (0); | |
760 | } | |
761 | else if (d == -1 && q == 0x80000000) | |
762 | { | |
763 | LO = EXTEND32 (0x80000000); | |
764 | HI = EXTEND32 (0); | |
765 | } | |
766 | else | |
767 | { | |
768 | LO = EXTEND32 (n / d); | |
769 | HI = EXTEND32 (n % d); | |
770 | } | |
771 | } | |
772 | } | |
773 | ||
774 | ||
775 | 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU | |
776 | "divu r<RS>, r<RT>" | |
777 | *mipsI: | |
778 | *mipsII: | |
779 | *mipsIII: | |
780 | *mipsIV: | |
781 | // start-sanitize-r5900 | |
782 | *r5900: | |
783 | // end-sanitize-r5900 | |
784 | *r3900: | |
785 | // start-sanitize-tx19 | |
786 | *tx19: | |
787 | // end-sanitize-tx19 | |
788 | { | |
789 | CHECKHILO ("Division"); | |
790 | { | |
791 | unsigned32 n = GPR (RS); | |
792 | unsigned32 d = GPR (RT); | |
793 | if (d == 0) | |
794 | { | |
795 | LO = EXTEND32 (0x80000000); | |
796 | HI = EXTEND32 (0); | |
797 | } | |
798 | else | |
799 | { | |
800 | LO = EXTEND32 (n / d); | |
801 | HI = EXTEND32 (n % d); | |
802 | } | |
803 | } | |
804 | } | |
805 | ||
806 | ||
807 | 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT | |
808 | "dmult r<RS>, r<RT>" | |
809 | *mipsIII: | |
810 | *mipsIV: | |
811 | *r3900: | |
812 | // start-sanitize-tx19 | |
813 | *tx19: | |
814 | // end-sanitize-tx19 | |
815 | { | |
816 | CHECKHILO ("Multiplication"); | |
817 | { | |
818 | signed64 op1 = GPR (RS); | |
819 | signed64 op2 = GPR (RT); | |
820 | unsigned64 lo; | |
821 | unsigned64 hi; | |
822 | unsigned64 m00; | |
823 | unsigned64 m01; | |
824 | unsigned64 m10; | |
825 | unsigned64 m11; | |
826 | unsigned64 mid; | |
827 | unsigned64 temp; | |
828 | int sign = 0; | |
829 | /* make it unsigned */ | |
830 | if (op1 < 0) | |
831 | { | |
832 | op1 = - op1; | |
833 | ++sign; | |
834 | } | |
835 | if (op2 < 0) | |
836 | { | |
837 | op2 = - op2; | |
838 | ++sign; | |
839 | } | |
840 | /* multuply out the 4 sub products */ | |
841 | m00 = (VL4_8 (op1) * VL4_8 (op2)); | |
842 | m10 = (VH4_8 (op1) * VL4_8 (op2)); | |
843 | m01 = (VL4_8 (op1) * VH4_8 (op2)); | |
844 | m11 = (VH4_8 (op1) * VH4_8 (op2)); | |
845 | /* add the products */ | |
846 | mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01); | |
847 | lo = U8_4 (mid, m00); | |
848 | hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10); | |
849 | /* save the result */ | |
850 | if (sign & 1) | |
851 | { | |
852 | LO = -lo; | |
853 | if (lo == 0) | |
854 | HI = -hi; | |
855 | else | |
856 | HI = -hi - 1; | |
857 | } | |
858 | else | |
859 | { | |
860 | LO = lo; | |
861 | HI = hi; | |
862 | } | |
863 | } | |
864 | } | |
865 | ||
866 | ||
867 | 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU | |
868 | "dmultu r<RS>, r<RT>" | |
869 | *mipsIII: | |
870 | *mipsIV: | |
871 | *r3900: | |
872 | // start-sanitize-tx19 | |
873 | *tx19: | |
874 | // end-sanitize-tx19 | |
875 | { | |
876 | CHECKHILO ("Multiplication"); | |
877 | { | |
878 | signed64 op1 = GPR (RS); | |
879 | signed64 op2 = GPR (RT); | |
880 | unsigned64 lo; | |
881 | unsigned64 hi; | |
882 | unsigned64 m00; | |
883 | unsigned64 m01; | |
884 | unsigned64 m10; | |
885 | unsigned64 m11; | |
886 | unsigned64 mid; | |
887 | unsigned64 temp; | |
888 | /* multuply out the 4 sub products */ | |
889 | m00 = (VL4_8 (op1) * VL4_8 (op2)); | |
890 | m10 = (VH4_8 (op1) * VL4_8 (op2)); | |
891 | m01 = (VL4_8 (op1) * VH4_8 (op2)); | |
892 | m11 = (VH4_8 (op1) * VH4_8 (op2)); | |
893 | /* add the products */ | |
894 | mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01); | |
895 | lo = U8_4 (mid, m00); | |
896 | hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10); | |
897 | /* save the result */ | |
898 | LO = lo; | |
899 | HI = hi; | |
900 | } | |
901 | } | |
902 | ||
903 | ||
904 | 00000000000,5.RT,5.RD,5.SA,111000:SPECIAL:64::DSLL | |
905 | "dsll r<RD>, r<RT>, <SA>" | |
906 | *mipsIII: | |
907 | *mipsIV: | |
908 | // start-sanitize-r5900 | |
909 | *r5900: | |
910 | // end-sanitize-r5900 | |
911 | *r3900: | |
912 | // start-sanitize-tx19 | |
913 | *tx19: | |
914 | // end-sanitize-tx19 | |
915 | { | |
916 | s = SA; | |
917 | GPR (RD) = GPR (RT) << s; | |
918 | } | |
919 | ||
920 | ||
921 | 00000000000,5.RT,5.RD,5.SA,111100:SPECIAL:64::DSLL32 | |
922 | "dsll32 r<RD>, r<RT>, <SA>" | |
923 | *mipsIII: | |
924 | *mipsIV: | |
925 | // start-sanitize-r5900 | |
926 | *r5900: | |
927 | // end-sanitize-r5900 | |
928 | *r3900: | |
929 | // start-sanitize-tx19 | |
930 | *tx19: | |
931 | // end-sanitize-tx19 | |
932 | { | |
933 | s = 32 + SA; | |
934 | GPR (RD) = GPR (RT) << s; | |
935 | } | |
936 | ||
937 | ||
938 | 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV | |
939 | "dsllv r<RD>, r<RT>, r<RS>" | |
940 | *mipsIII: | |
941 | *mipsIV: | |
942 | // start-sanitize-r5900 | |
943 | *r5900: | |
944 | // end-sanitize-r5900 | |
945 | *r3900: | |
946 | // start-sanitize-tx19 | |
947 | *tx19: | |
948 | // end-sanitize-tx19 | |
949 | { | |
950 | s = MASKED64 (GPR (RS), 5, 0); | |
951 | GPR (RD) = GPR (RT) << s; | |
952 | } | |
953 | ||
954 | ||
955 | 00000000000,5.RT,5.RD,5.SA,111011:SPECIAL:64::DSRA | |
956 | "dsra r<RD>, r<RT>, <SA>" | |
957 | *mipsIII: | |
958 | *mipsIV: | |
959 | // start-sanitize-r5900 | |
960 | *r5900: | |
961 | // end-sanitize-r5900 | |
962 | *r3900: | |
963 | // start-sanitize-tx19 | |
964 | *tx19: | |
965 | // end-sanitize-tx19 | |
966 | { | |
967 | s = SA; | |
968 | GPR (RD) = ((signed64) GPR (RT)) >> s; | |
969 | } | |
970 | ||
971 | ||
972 | 00000000000,5.RT,5.RD,5.SA,111111:SPECIAL:64::DSRA32 | |
973 | "dsra32 r<RT>, r<RD>, <SA>" | |
974 | *mipsIII: | |
975 | *mipsIV: | |
976 | // start-sanitize-r5900 | |
977 | *r5900: | |
978 | // end-sanitize-r5900 | |
979 | *r3900: | |
980 | // start-sanitize-tx19 | |
981 | *tx19: | |
982 | // end-sanitize-tx19 | |
983 | { | |
984 | s = 32 + SA; | |
985 | GPR (RD) = ((signed64) GPR (RT)) >> s; | |
986 | } | |
987 | ||
988 | ||
989 | 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV | |
990 | "dsra32 r<RT>, r<RD>, r<RS>" | |
991 | *mipsIII: | |
992 | *mipsIV: | |
993 | // start-sanitize-r5900 | |
994 | *r5900: | |
995 | // end-sanitize-r5900 | |
996 | *r3900: | |
997 | // start-sanitize-tx19 | |
998 | *tx19: | |
999 | // end-sanitize-tx19 | |
1000 | { | |
1001 | int s = MASKED64 (GPR (RS), 5, 0); | |
1002 | GPR (RD) = ((signed64) GPR (RT)) >> s; | |
1003 | } | |
1004 | ||
1005 | ||
1006 | 00000000000,5.RT,5.RD,5.SA,111010:SPECIAL:64::DSRL | |
1007 | "dsrav r<RD>, r<RT>, <SA>" | |
1008 | *mipsIII: | |
1009 | *mipsIV: | |
1010 | // start-sanitize-r5900 | |
1011 | *r5900: | |
1012 | // end-sanitize-r5900 | |
1013 | *r3900: | |
1014 | // start-sanitize-tx19 | |
1015 | *tx19: | |
1016 | // end-sanitize-tx19 | |
1017 | { | |
1018 | int s = SA; | |
1019 | GPR (RD) = (unsigned64) GPR (RT) >> s; | |
1020 | } | |
1021 | ||
1022 | ||
1023 | 00000000000,5.RT,5.RD,5.SA,111110:SPECIAL:64::DSRL32 | |
1024 | "dsrl32 r<RD>, r<RT>, <SA>" | |
1025 | *mipsIII: | |
1026 | *mipsIV: | |
1027 | // start-sanitize-r5900 | |
1028 | *r5900: | |
1029 | // end-sanitize-r5900 | |
1030 | *r3900: | |
1031 | // start-sanitize-tx19 | |
1032 | *tx19: | |
1033 | // end-sanitize-tx19 | |
1034 | { | |
1035 | int s = 32 + SA; | |
1036 | GPR (RD) = (unsigned64) GPR (RT) >> s; | |
1037 | } | |
1038 | ||
1039 | ||
1040 | 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV | |
1041 | "dsrl32 r<RD>, r<RT>, r<RS>" | |
1042 | *mipsIII: | |
1043 | *mipsIV: | |
1044 | // start-sanitize-r5900 | |
1045 | *r5900: | |
1046 | // end-sanitize-r5900 | |
1047 | *r3900: | |
1048 | // start-sanitize-tx19 | |
1049 | *tx19: | |
1050 | // end-sanitize-tx19 | |
1051 | { | |
1052 | int s = MASKED64 (GPR (RS), 5, 0); | |
1053 | GPR (RD) = (unsigned64) GPR (RT) >> s; | |
1054 | } | |
1055 | ||
1056 | ||
1057 | 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB | |
1058 | "dsub r<RD>, r<RS>, r<RT>" | |
1059 | *mipsIII: | |
1060 | *mipsIV: | |
1061 | // start-sanitize-r5900 | |
1062 | *r5900: | |
1063 | // end-sanitize-r5900 | |
1064 | *r3900: | |
1065 | // start-sanitize-tx19 | |
1066 | *tx19: | |
1067 | // end-sanitize-tx19 | |
1068 | { | |
1069 | ALU64_BEGIN (GPR (RS)); | |
1070 | ALU64_SUB (GPR (RT)); | |
1071 | ALU64_END (GPR (RD)); | |
1072 | } | |
1073 | ||
1074 | ||
1075 | 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU | |
1076 | "dsubu r<RD>, r<RS>, r<RT>" | |
1077 | *mipsIII: | |
1078 | *mipsIV: | |
1079 | // start-sanitize-r5900 | |
1080 | *r5900: | |
1081 | // end-sanitize-r5900 | |
1082 | *r3900: | |
1083 | // start-sanitize-tx19 | |
1084 | *tx19: | |
1085 | // end-sanitize-tx19 | |
1086 | { | |
1087 | GPR (RD) = GPR (RS) - GPR (RT); | |
1088 | } | |
1089 | ||
1090 | ||
1091 | 000010,26.INSTR_INDEX:NORMAL:32::J | |
1092 | "j <INSTR_INDEX>" | |
1093 | *mipsI: | |
1094 | *mipsII: | |
1095 | *mipsIII: | |
1096 | *mipsIV: | |
1097 | // start-sanitize-r5900 | |
1098 | *r5900: | |
1099 | // end-sanitize-r5900 | |
1100 | *r3900: | |
1101 | // start-sanitize-tx19 | |
1102 | *tx19: | |
1103 | // end-sanitize-tx19 | |
1104 | { | |
1105 | /* NOTE: The region used is that of the delay slot and NOT the | |
1106 | current instruction */ | |
1107 | address_word region = NIA & MASK (63, 28); | |
1108 | DSPC = region | (INSTR_INDEX << 2); | |
1109 | DELAYSLOT (); | |
1110 | /* FIXME-WAS: ??? Gdb gets confused if the PC is sign-extended, so | |
1111 | we just truncate it to 32 bits here. -- DSPC = VL4_8 (DSPC); */ | |
1112 | } | |
1113 | ||
1114 | ||
1115 | 000011,26.INSTR_INDEX:NORMAL:32::JAL | |
1116 | "jal <INSTR_INDEX>" | |
1117 | *mipsI: | |
1118 | *mipsII: | |
1119 | *mipsIII: | |
1120 | *mipsIV: | |
1121 | // start-sanitize-r5900 | |
1122 | *r5900: | |
1123 | // end-sanitize-r5900 | |
1124 | *r3900: | |
1125 | // start-sanitize-tx19 | |
1126 | *tx19: | |
1127 | // end-sanitize-tx19 | |
1128 | { | |
1129 | /* NOTE: The region used is that of the delay slot and NOT the | |
1130 | current instruction */ | |
1131 | address_word region = NIA & MASK (63, 28); | |
1132 | GPR (31) = CIA + 8; | |
1133 | DSPC = region | (INSTR_INDEX << 2); | |
1134 | DELAYSLOT (); | |
1135 | /* FIXME-WAS: ??? Gdb gets confused if the PC is sign-extended, so | |
1136 | we just truncate it to 32 bits here. -- DSPC = VL4_8 (DSPC); */ | |
1137 | } | |
1138 | ||
1139 | ||
1140 | 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR | |
1141 | "jalr r<RS>":RD == 31 | |
1142 | "jalr r<RD>, r<RS>" | |
1143 | *mipsI: | |
1144 | *mipsII: | |
1145 | *mipsIII: | |
1146 | *mipsIV: | |
1147 | // start-sanitize-r5900 | |
1148 | *r5900: | |
1149 | // end-sanitize-r5900 | |
1150 | *r3900: | |
1151 | // start-sanitize-tx19 | |
1152 | *tx19: | |
1153 | // end-sanitize-tx19 | |
1154 | { | |
1155 | address_word temp = GPR (RS); | |
1156 | GPR (RD) = CIA + 8; | |
1157 | DSPC = temp; | |
1158 | DELAYSLOT (); | |
1159 | /* FIXME-WAS: ??? Gdb gets confused if the PC is sign-extended, so | |
1160 | we just truncate it to 32 bits here. -- DSPC = VL4_8 (DSPC); */ | |
1161 | } | |
1162 | ||
1163 | ||
1164 | 000000,5.RS,000000000000000001000:SPECIAL:32::JR | |
1165 | "jr r<RS>" | |
1166 | *mipsI: | |
1167 | *mipsII: | |
1168 | *mipsIII: | |
1169 | *mipsIV: | |
1170 | // start-sanitize-r5900 | |
1171 | *r5900: | |
1172 | // end-sanitize-r5900 | |
1173 | *r3900: | |
1174 | // start-sanitize-tx19 | |
1175 | *tx19: | |
1176 | // end-sanitize-tx19 | |
1177 | { | |
1178 | DSPC = GPR (RS); | |
1179 | DELAYSLOT (); | |
1180 | /* FIXME-WAS: ??? Gdb gets confused if the PC is sign-extended, so | |
1181 | we just truncate it to 32 bits here. -- DSPC = VL4_8 (DSPC); */ | |
1182 | } | |
1183 | ||
1184 | ||
1185 | 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB | |
1186 | "lb r<RT>, <OFFSET>(r<BASE>)" | |
1187 | *mipsI: | |
1188 | *mipsII: | |
1189 | *mipsIII: | |
1190 | *mipsIV: | |
1191 | // start-sanitize-r5900 | |
1192 | *r5900: | |
1193 | // end-sanitize-r5900 | |
1194 | *r3900: | |
1195 | // start-sanitize-tx19 | |
1196 | *tx19: | |
1197 | // end-sanitize-tx19 | |
1198 | { | |
1199 | unsigned32 instruction = instruction_0; | |
1200 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1201 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1202 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
1203 | { | |
1204 | uword64 vaddr = ((uword64)op1 + offset); | |
1205 | uword64 paddr; | |
1206 | int uncached; | |
1207 | { | |
1208 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1209 | { | |
1210 | uword64 memval = 0; | |
1211 | uword64 memval1 = 0; | |
1212 | uword64 mask = 0x7; | |
1213 | unsigned int shift = 0; | |
1214 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
1215 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
1216 | unsigned int byte UNUSED; | |
1217 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
1218 | LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); | |
1219 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1220 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8)); | |
1221 | } | |
1222 | } | |
1223 | } | |
1224 | } | |
1225 | ||
1226 | ||
1227 | 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU | |
1228 | "lbu r<RT>, <OFFSET>(r<BASE>)" | |
1229 | *mipsI: | |
1230 | *mipsII: | |
1231 | *mipsIII: | |
1232 | *mipsIV: | |
1233 | // start-sanitize-r5900 | |
1234 | *r5900: | |
1235 | // end-sanitize-r5900 | |
1236 | *r3900: | |
1237 | // start-sanitize-tx19 | |
1238 | *tx19: | |
1239 | // end-sanitize-tx19 | |
1240 | { | |
1241 | unsigned32 instruction = instruction_0; | |
1242 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1243 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1244 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
1245 | { | |
1246 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
1247 | unsigned64 paddr; | |
1248 | int uncached; | |
1249 | { | |
1250 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1251 | { | |
1252 | unsigned64 memval = 0; | |
1253 | unsigned64 memval1 = 0; | |
1254 | unsigned64 mask = 0x7; | |
1255 | unsigned int shift = 0; | |
1256 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
1257 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
1258 | unsigned int byte UNUSED; | |
1259 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
1260 | LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); | |
1261 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1262 | GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF)); | |
1263 | } | |
1264 | } | |
1265 | } | |
1266 | } | |
1267 | ||
1268 | ||
1269 | 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD | |
1270 | "ld r<RT>, <OFFSET>(r<BASE>)" | |
1271 | *mipsIII: | |
1272 | *mipsIV: | |
1273 | // start-sanitize-r5900 | |
1274 | *r5900: | |
1275 | // end-sanitize-r5900 | |
1276 | *r3900: | |
1277 | // start-sanitize-tx19 | |
1278 | *tx19: | |
1279 | // end-sanitize-tx19 | |
1280 | { | |
1281 | unsigned32 instruction = instruction_0; | |
1282 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1283 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1284 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
1285 | { | |
1286 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
1287 | unsigned64 paddr; | |
1288 | int uncached; | |
1289 | if ((vaddr & 7) != 0) | |
1290 | SignalException(AddressLoad); | |
1291 | else | |
1292 | { | |
1293 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1294 | { | |
1295 | unsigned64 memval = 0; | |
1296 | unsigned64 memval1 = 0; | |
1297 | unsigned64 mask = 0x7; | |
1298 | unsigned int shift = 4; | |
1299 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
1300 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
1301 | unsigned int byte UNUSED; | |
1302 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); | |
1303 | GPR[destreg] = memval; | |
1304 | } | |
1305 | } | |
1306 | } | |
1307 | } | |
1308 | ||
1309 | ||
49a6eed5 | 1310 | 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz |
f2b30012 AC |
1311 | "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
1312 | *mipsII: | |
1313 | *mipsIII: | |
1314 | *mipsIV: | |
1315 | // start-sanitize-r5900 | |
1316 | *r5900: | |
1317 | // end-sanitize-r5900 | |
1318 | *r3900: | |
1319 | // start-sanitize-tx19 | |
1320 | *tx19: | |
1321 | // end-sanitize-tx19 | |
1322 | { | |
1323 | unsigned32 instruction = instruction_0; | |
1324 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1325 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1326 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
1327 | { | |
1328 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
1329 | unsigned64 paddr; | |
1330 | int uncached; | |
1331 | if ((vaddr & 7) != 0) | |
1332 | SignalException(AddressLoad); | |
1333 | else | |
1334 | { | |
1335 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1336 | { | |
1337 | unsigned64 memval = 0; | |
1338 | unsigned64 memval1 = 0; | |
1339 | unsigned64 mask = 0x7; | |
1340 | unsigned int shift = 4; | |
1341 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
1342 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
1343 | unsigned int byte UNUSED; | |
1344 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); | |
1345 | COP_LD(((instruction >> 26) & 0x3),destreg,memval);; | |
1346 | } | |
1347 | } | |
1348 | } | |
1349 | } | |
1350 | ||
1351 | ||
1352 | 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL | |
1353 | "ldl r<RT>, <OFFSET>(r<BASE>)" | |
1354 | *mipsIII: | |
1355 | *mipsIV: | |
1356 | // start-sanitize-r5900 | |
1357 | *r5900: | |
1358 | // end-sanitize-r5900 | |
1359 | *r3900: | |
1360 | // start-sanitize-tx19 | |
1361 | *tx19: | |
1362 | // end-sanitize-tx19 | |
1363 | { | |
1364 | unsigned32 instruction = instruction_0; | |
1365 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1366 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1367 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
1368 | { | |
1369 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
1370 | unsigned64 paddr; | |
1371 | int uncached; | |
1372 | { | |
1373 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1374 | { | |
1375 | unsigned64 memval = 0; | |
1376 | unsigned64 memval1 = 0; | |
1377 | unsigned64 mask = 7; | |
1378 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
1379 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
1380 | int byte; | |
1381 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
1382 | byte = ((vaddr & mask) ^ bigend); | |
1383 | if (!!ByteSwapMem) | |
1384 | paddr &= ~mask; | |
1385 | LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL); | |
1386 | GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1))); | |
1387 | } | |
1388 | } | |
1389 | } | |
1390 | } | |
1391 | ||
1392 | ||
1393 | 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR | |
1394 | "ldr r<RT>, <OFFSET>(r<BASE>)" | |
1395 | *mipsIII: | |
1396 | *mipsIV: | |
1397 | // start-sanitize-r5900 | |
1398 | *r5900: | |
1399 | // end-sanitize-r5900 | |
1400 | *r3900: | |
1401 | // start-sanitize-tx19 | |
1402 | *tx19: | |
1403 | // end-sanitize-tx19 | |
1404 | { | |
1405 | unsigned32 instruction = instruction_0; | |
1406 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1407 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1408 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
1409 | { | |
1410 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
1411 | unsigned64 paddr; | |
1412 | int uncached; | |
1413 | { | |
1414 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1415 | { | |
1416 | unsigned64 memval = 0; | |
1417 | unsigned64 memval1 = 0; | |
1418 | unsigned64 mask = 7; | |
1419 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
1420 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
1421 | int byte; | |
1422 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
1423 | byte = ((vaddr & mask) ^ bigend); | |
1424 | if (!ByteSwapMem) | |
1425 | paddr &= ~mask; | |
1426 | LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL); | |
1427 | { | |
1428 | unsigned64 srcmask; | |
1429 | if (byte == 0) | |
1430 | srcmask = 0; | |
1431 | else | |
1432 | srcmask = ((unsigned64)-1 << (8 * (8 - byte))); | |
1433 | GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte))); | |
1434 | } | |
1435 | } | |
1436 | } | |
1437 | } | |
1438 | } | |
1439 | ||
1440 | ||
1441 | 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH | |
1442 | "lh r<RT>, <OFFSET>(r<BASE>)" | |
1443 | *mipsI: | |
1444 | *mipsII: | |
1445 | *mipsIII: | |
1446 | *mipsIV: | |
1447 | // start-sanitize-r5900 | |
1448 | *r5900: | |
1449 | // end-sanitize-r5900 | |
1450 | *r3900: | |
1451 | // start-sanitize-tx19 | |
1452 | *tx19: | |
1453 | // end-sanitize-tx19 | |
1454 | { | |
1455 | unsigned32 instruction = instruction_0; | |
1456 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1457 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1458 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
1459 | { | |
1460 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
1461 | unsigned64 paddr; | |
1462 | int uncached; | |
1463 | if ((vaddr & 1) != 0) | |
1464 | SignalException(AddressLoad); | |
1465 | else | |
1466 | { | |
1467 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1468 | { | |
1469 | unsigned64 memval = 0; | |
1470 | unsigned64 memval1 = 0; | |
1471 | unsigned64 mask = 0x7; | |
1472 | unsigned int shift = 1; | |
1473 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
1474 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
1475 | unsigned int byte UNUSED; | |
1476 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
1477 | LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); | |
1478 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1479 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16)); | |
1480 | } | |
1481 | } | |
1482 | } | |
1483 | } | |
1484 | ||
1485 | ||
1486 | 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU | |
1487 | "lhu r<RT>, <OFFSET>(r<BASE>)" | |
1488 | *mipsI: | |
1489 | *mipsII: | |
1490 | *mipsIII: | |
1491 | *mipsIV: | |
1492 | // start-sanitize-r5900 | |
1493 | *r5900: | |
1494 | // end-sanitize-r5900 | |
1495 | *r3900: | |
1496 | // start-sanitize-tx19 | |
1497 | *tx19: | |
1498 | // end-sanitize-tx19 | |
1499 | { | |
1500 | unsigned32 instruction = instruction_0; | |
1501 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1502 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1503 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
1504 | { | |
1505 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
1506 | unsigned64 paddr; | |
1507 | int uncached; | |
1508 | if ((vaddr & 1) != 0) | |
1509 | SignalException(AddressLoad); | |
1510 | else | |
1511 | { | |
1512 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1513 | { | |
1514 | unsigned64 memval = 0; | |
1515 | unsigned64 memval1 = 0; | |
1516 | unsigned64 mask = 0x7; | |
1517 | unsigned int shift = 1; | |
1518 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
1519 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
1520 | unsigned int byte UNUSED; | |
1521 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
1522 | LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); | |
1523 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1524 | GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF)); | |
1525 | } | |
1526 | } | |
1527 | } | |
1528 | } | |
1529 | ||
1530 | ||
1531 | 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL | |
1532 | "ll r<RT>, <OFFSET>(r<BASE>)" | |
1533 | *mipsII: | |
1534 | *mipsIII: | |
1535 | *mipsIV: | |
1536 | // start-sanitize-r5900 | |
1537 | *r5900: | |
1538 | // end-sanitize-r5900 | |
1539 | *r3900: | |
1540 | // start-sanitize-tx19 | |
1541 | *tx19: | |
1542 | // end-sanitize-tx19 | |
1543 | { | |
1544 | unsigned32 instruction = instruction_0; | |
1545 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1546 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1547 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
1548 | { | |
1549 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
1550 | unsigned64 paddr; | |
1551 | int uncached; | |
1552 | if ((vaddr & 3) != 0) | |
1553 | SignalException(AddressLoad); | |
1554 | else | |
1555 | { | |
1556 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1557 | { | |
1558 | unsigned64 memval = 0; | |
1559 | unsigned64 memval1 = 0; | |
1560 | unsigned64 mask = 0x7; | |
1561 | unsigned int shift = 2; | |
1562 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
1563 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
1564 | unsigned int byte UNUSED; | |
1565 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
1566 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
1567 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1568 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); | |
1569 | LLBIT = 1; | |
1570 | } | |
1571 | } | |
1572 | } | |
1573 | } | |
1574 | ||
1575 | ||
1576 | 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD | |
1577 | "lld r<RT>, <OFFSET>(r<BASE>)" | |
1578 | *mipsIII: | |
1579 | *mipsIV: | |
1580 | // start-sanitize-r5900 | |
1581 | *r5900: | |
1582 | // end-sanitize-r5900 | |
1583 | *r3900: | |
1584 | // start-sanitize-tx19 | |
1585 | *tx19: | |
1586 | // end-sanitize-tx19 | |
1587 | { | |
1588 | unsigned32 instruction = instruction_0; | |
1589 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1590 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1591 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
1592 | { | |
1593 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
1594 | unsigned64 paddr; | |
1595 | int uncached; | |
1596 | if ((vaddr & 7) != 0) | |
1597 | SignalException(AddressLoad); | |
1598 | else | |
1599 | { | |
1600 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1601 | { | |
1602 | unsigned64 memval = 0; | |
1603 | unsigned64 memval1 = 0; | |
1604 | unsigned64 mask = 0x7; | |
1605 | unsigned int shift = 4; | |
1606 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
1607 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
1608 | unsigned int byte UNUSED; | |
1609 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); | |
1610 | GPR[destreg] = memval; | |
1611 | LLBIT = 1; | |
1612 | } | |
1613 | } | |
1614 | } | |
1615 | } | |
1616 | ||
1617 | ||
1618 | 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI | |
1619 | "lui r<RT>, <IMMEDIATE>" | |
1620 | *mipsI: | |
1621 | *mipsII: | |
1622 | *mipsIII: | |
1623 | *mipsIV: | |
1624 | // start-sanitize-r5900 | |
1625 | *r5900: | |
1626 | // end-sanitize-r5900 | |
1627 | *r3900: | |
1628 | // start-sanitize-tx19 | |
1629 | *tx19: | |
1630 | // end-sanitize-tx19 | |
1631 | { | |
1632 | unsigned32 instruction = instruction_0; | |
1633 | t_reg op2 UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1634 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1635 | { | |
1636 | GPR[destreg] = (op2 << 16); | |
1637 | } | |
1638 | } | |
1639 | ||
1640 | ||
1641 | 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW | |
1642 | "lw r<RT>, <OFFSET>(r<BASE>)" | |
1643 | *mipsI: | |
1644 | *mipsII: | |
1645 | *mipsIII: | |
1646 | *mipsIV: | |
1647 | // start-sanitize-r5900 | |
1648 | *r5900: | |
1649 | // end-sanitize-r5900 | |
1650 | *r3900: | |
1651 | // start-sanitize-tx19 | |
1652 | *tx19: | |
1653 | // end-sanitize-tx19 | |
1654 | { | |
1655 | unsigned32 instruction = instruction_0; | |
1656 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1657 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1658 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
1659 | { | |
1660 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
1661 | unsigned64 paddr; | |
1662 | int uncached; | |
1663 | if ((vaddr & 3) != 0) | |
1664 | SignalException(AddressLoad); | |
1665 | else | |
1666 | { | |
1667 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1668 | { | |
1669 | unsigned64 memval = 0; | |
1670 | unsigned64 memval1 = 0; | |
1671 | unsigned64 mask = 0x7; | |
1672 | unsigned int shift = 2; | |
1673 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
1674 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
1675 | unsigned int byte UNUSED; | |
1676 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
1677 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
1678 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1679 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); | |
1680 | } | |
1681 | } | |
1682 | } | |
1683 | } | |
1684 | ||
1685 | ||
49a6eed5 | 1686 | 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz |
f2b30012 AC |
1687 | "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
1688 | *mipsI: | |
1689 | *mipsII: | |
1690 | *mipsIII: | |
1691 | *mipsIV: | |
1692 | // start-sanitize-r5900 | |
1693 | *r5900: | |
1694 | // end-sanitize-r5900 | |
1695 | *r3900: | |
1696 | // start-sanitize-tx19 | |
1697 | *tx19: | |
1698 | // end-sanitize-tx19 | |
1699 | { | |
1700 | unsigned32 instruction = instruction_0; | |
1701 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1702 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1703 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
1704 | { | |
1705 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
1706 | unsigned64 paddr; | |
1707 | int uncached; | |
1708 | if ((vaddr & 3) != 0) | |
1709 | SignalException(AddressLoad); | |
1710 | else | |
1711 | { | |
1712 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1713 | { | |
1714 | unsigned64 memval = 0; | |
1715 | unsigned64 memval1 = 0; | |
1716 | unsigned64 mask = 0x7; | |
1717 | unsigned int shift = 2; | |
1718 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
1719 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
1720 | unsigned int byte UNUSED; | |
1721 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
1722 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
1723 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1724 | COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF)); | |
1725 | } | |
1726 | } | |
1727 | } | |
1728 | } | |
1729 | ||
1730 | ||
1731 | 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL | |
1732 | "lwl r<RT>, <OFFSET>(r<BASE>)" | |
1733 | *mipsI: | |
1734 | *mipsII: | |
1735 | *mipsIII: | |
1736 | *mipsIV: | |
1737 | // start-sanitize-r5900 | |
1738 | *r5900: | |
1739 | // end-sanitize-r5900 | |
1740 | *r3900: | |
1741 | // start-sanitize-tx19 | |
1742 | *tx19: | |
1743 | // end-sanitize-tx19 | |
1744 | { | |
1745 | unsigned32 instruction = instruction_0; | |
1746 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1747 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1748 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
1749 | { | |
1750 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
1751 | unsigned64 paddr; | |
1752 | int uncached; | |
1753 | { | |
1754 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1755 | { | |
1756 | unsigned64 memval = 0; | |
1757 | unsigned64 memval1 = 0; | |
1758 | unsigned64 mask = 3; | |
1759 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
1760 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
1761 | int byte; | |
1762 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
1763 | byte = ((vaddr & mask) ^ bigend); | |
1764 | if (!!ByteSwapMem) | |
1765 | paddr &= ~mask; | |
1766 | LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL); | |
1767 | if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { | |
1768 | memval >>= 32; | |
1769 | } | |
1770 | GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1))); | |
1771 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
1772 | } | |
1773 | } | |
1774 | } | |
1775 | } | |
1776 | ||
1777 | ||
1778 | 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR | |
1779 | "lwr r<RT>, <OFFSET>(r<BASE>)" | |
1780 | *mipsI: | |
1781 | *mipsII: | |
1782 | *mipsIII: | |
1783 | *mipsIV: | |
1784 | // start-sanitize-r5900 | |
1785 | *r5900: | |
1786 | // end-sanitize-r5900 | |
1787 | *r3900: | |
1788 | // start-sanitize-tx19 | |
1789 | *tx19: | |
1790 | // end-sanitize-tx19 | |
1791 | { | |
1792 | unsigned32 instruction = instruction_0; | |
1793 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1794 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1795 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
1796 | { | |
1797 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
1798 | unsigned64 paddr; | |
1799 | int uncached; | |
1800 | { | |
1801 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1802 | { | |
1803 | unsigned64 memval = 0; | |
1804 | unsigned64 memval1 = 0; | |
1805 | unsigned64 mask = 3; | |
1806 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
1807 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
1808 | int byte; | |
1809 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
1810 | byte = ((vaddr & mask) ^ bigend); | |
1811 | if (!ByteSwapMem) | |
1812 | paddr &= ~mask; | |
1813 | LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL); | |
1814 | if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { | |
1815 | memval >>= 32; | |
1816 | } | |
1817 | { | |
1818 | unsigned64 srcmask; | |
1819 | if (byte == 0) | |
1820 | srcmask = 0; | |
1821 | else | |
1822 | srcmask = ((unsigned64)-1 << (8 * (4 - byte))); | |
1823 | GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte))); | |
1824 | } | |
1825 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
1826 | } | |
1827 | } | |
1828 | } | |
1829 | } | |
1830 | ||
1831 | ||
1832 | 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU | |
1833 | "lwu r<RT>, <OFFSET>(r<BASE>)" | |
1834 | *mipsIII: | |
1835 | *mipsIV: | |
1836 | // start-sanitize-r5900 | |
1837 | *r5900: | |
1838 | // end-sanitize-r5900 | |
1839 | *r3900: | |
1840 | // start-sanitize-tx19 | |
1841 | *tx19: | |
1842 | // end-sanitize-tx19 | |
1843 | { | |
1844 | unsigned32 instruction = instruction_0; | |
1845 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
1846 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
1847 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
1848 | { | |
1849 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
1850 | unsigned64 paddr; | |
1851 | int uncached; | |
1852 | if ((vaddr & 3) != 0) | |
1853 | SignalException(AddressLoad); | |
1854 | else | |
1855 | { | |
1856 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1857 | { | |
1858 | unsigned64 memval = 0; | |
1859 | unsigned64 memval1 = 0; | |
1860 | unsigned64 mask = 0x7; | |
1861 | unsigned int shift = 2; | |
1862 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
1863 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
1864 | unsigned int byte UNUSED; | |
1865 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
1866 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
1867 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1868 | GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF)); | |
1869 | } | |
1870 | } | |
1871 | } | |
1872 | } | |
1873 | ||
1874 | ||
1875 | 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI | |
1876 | "mfhi r<RD>" | |
1877 | *mipsI: | |
1878 | *mipsII: | |
1879 | *mipsIII: | |
1880 | *mipsIV: | |
1881 | // start-sanitize-r5900 | |
1882 | *r5900: | |
1883 | // end-sanitize-r5900 | |
1884 | *r3900: | |
1885 | // start-sanitize-tx19 | |
1886 | *tx19: | |
1887 | // end-sanitize-tx19 | |
1888 | { | |
1889 | GPR (RD) = HI; | |
1890 | HIACCESS = 3; | |
1891 | } | |
1892 | ||
1893 | ||
1894 | 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO | |
1895 | "mflo r<RD>" | |
1896 | *mipsI: | |
1897 | *mipsII: | |
1898 | *mipsIII: | |
1899 | *mipsIV: | |
1900 | // start-sanitize-r5900 | |
1901 | *r5900: | |
1902 | // end-sanitize-r5900 | |
1903 | *r3900: | |
1904 | // start-sanitize-tx19 | |
1905 | *tx19: | |
1906 | // end-sanitize-tx19 | |
1907 | { | |
1908 | GPR (RD) = LO; | |
1909 | LOACCESS = 3; /* 3rd instruction will be safe */ | |
1910 | } | |
1911 | ||
1912 | ||
1913 | 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN | |
1914 | "movn r<RD>, r<RS>, r<RT>" | |
1915 | *mipsIV: | |
1916 | // start-sanitize-r5900 | |
1917 | *r5900: | |
1918 | // end-sanitize-r5900 | |
1919 | { | |
1920 | if (GPR (RT) != 0) | |
1921 | GPR (RD) = GPR (RS); | |
1922 | } | |
1923 | ||
1924 | ||
1925 | 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ | |
1926 | "movz r<RD>, r<RS>, r<RT>" | |
1927 | *mipsIV: | |
1928 | // start-sanitize-r5900 | |
1929 | *r5900: | |
1930 | // end-sanitize-r5900 | |
1931 | { | |
1932 | if (GPR (RT) == 0) | |
1933 | GPR (RD) = GPR (RS); | |
1934 | } | |
1935 | ||
1936 | ||
1937 | 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI | |
1938 | "mthi r<RS>" | |
1939 | *mipsI: | |
1940 | *mipsII: | |
1941 | *mipsIII: | |
1942 | *mipsIV: | |
1943 | // start-sanitize-r5900 | |
1944 | *r5900: | |
1945 | // end-sanitize-r5900 | |
1946 | *r3900: | |
1947 | // start-sanitize-tx19 | |
1948 | *tx19: | |
1949 | // end-sanitize-tx19 | |
1950 | { | |
1951 | if (HIACCESS != 0) | |
1952 | sim_warning ("MT (move-to) over-writing HI register value"); | |
1953 | HI = GPR (RS); | |
1954 | HIACCESS = 3; /* 3rd instruction will be safe */ | |
1955 | } | |
1956 | ||
1957 | ||
1958 | 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO | |
1959 | "mtlo r<RS>" | |
1960 | *mipsI: | |
1961 | *mipsII: | |
1962 | *mipsIII: | |
1963 | *mipsIV: | |
1964 | // start-sanitize-r5900 | |
1965 | *r5900: | |
1966 | // end-sanitize-r5900 | |
1967 | *r3900: | |
1968 | // start-sanitize-tx19 | |
1969 | *tx19: | |
1970 | // end-sanitize-tx19 | |
1971 | { | |
1972 | if (LOACCESS != 0) | |
1973 | sim_warning ("MT (move-to) over-writing LO register value"); | |
1974 | LO = GPR (RS); | |
1975 | LOACCESS = 3; /* 3rd instruction will be safe */ | |
1976 | } | |
1977 | ||
1978 | ||
1979 | 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT | |
1980 | "mult r<RS>, r<RT>" | |
1981 | *mipsI: | |
1982 | *mipsII: | |
1983 | *mipsIII: | |
1984 | *mipsIV: | |
1985 | // start-sanitize-r5900 | |
1986 | *r5900: | |
1987 | // end-sanitize-r5900 | |
1988 | *r3900: | |
1989 | // start-sanitize-tx19 | |
1990 | *tx19: | |
1991 | // end-sanitize-tx19 | |
1992 | { | |
1993 | signed64 prod; | |
1994 | CHECKHILO ("Multiplication"); | |
1995 | prod = (((signed64)(signed32) GPR (RS)) | |
1996 | * ((signed64)(signed32) GPR (RT))); | |
1997 | LO = EXTEND32 (VL4_8 (prod)); | |
1998 | HI = EXTEND32 (VH4_8 (prod)); | |
1999 | } | |
2000 | ||
2001 | ||
2002 | 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU | |
2003 | "multu r<RS>, r<RT>" | |
2004 | *mipsI: | |
2005 | *mipsII: | |
2006 | *mipsIII: | |
2007 | *mipsIV: | |
2008 | // start-sanitize-r5900 | |
2009 | *r5900: | |
2010 | // end-sanitize-r5900 | |
2011 | *r3900: | |
2012 | // start-sanitize-tx19 | |
2013 | *tx19: | |
2014 | // end-sanitize-tx19 | |
2015 | { | |
2016 | unsigned64 prod; | |
2017 | CHECKHILO ("Multiplication"); | |
2018 | prod = (((unsigned64)(unsigned32) GPR (RS)) | |
2019 | * ((unsigned64)(unsigned32) GPR (RT))); | |
2020 | LO = EXTEND32 (VL4_8 (prod)); | |
2021 | HI = EXTEND32 (VH4_8 (prod)); | |
2022 | } | |
2023 | ||
2024 | ||
2025 | 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR | |
2026 | "nor r<RD>, r<RS>, r<RT>" | |
2027 | *mipsI: | |
2028 | *mipsII: | |
2029 | *mipsIII: | |
2030 | *mipsIV: | |
2031 | // start-sanitize-r5900 | |
2032 | *r5900: | |
2033 | // end-sanitize-r5900 | |
2034 | *r3900: | |
2035 | // start-sanitize-tx19 | |
2036 | *tx19: | |
2037 | // end-sanitize-tx19 | |
2038 | { | |
2039 | GPR (RD) = ~ (GPR (RS) | GPR (RT)); | |
2040 | } | |
2041 | ||
2042 | ||
2043 | 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR | |
2044 | "or r<RD>, r<RS>, r<RT>" | |
2045 | *mipsI: | |
2046 | *mipsII: | |
2047 | *mipsIII: | |
2048 | *mipsIV: | |
2049 | // start-sanitize-r5900 | |
2050 | *r5900: | |
2051 | // end-sanitize-r5900 | |
2052 | *r3900: | |
2053 | // start-sanitize-tx19 | |
2054 | *tx19: | |
2055 | // end-sanitize-tx19 | |
2056 | { | |
2057 | GPR (RD) = (GPR (RS) | GPR (RT)); | |
2058 | } | |
2059 | ||
2060 | ||
2061 | 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI | |
2062 | "ori r<RD>, r<RS>, <IMMEDIATE>" | |
2063 | *mipsI: | |
2064 | *mipsII: | |
2065 | *mipsIII: | |
2066 | *mipsIV: | |
2067 | // start-sanitize-r5900 | |
2068 | *r5900: | |
2069 | // end-sanitize-r5900 | |
2070 | *r3900: | |
2071 | // start-sanitize-tx19 | |
2072 | *tx19: | |
2073 | // end-sanitize-tx19 | |
2074 | { | |
2075 | GPR (RD) = (GPR (RS) | IMMEDIATE); | |
2076 | } | |
2077 | ||
2078 | ||
2079 | 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF | |
2080 | *mipsIV: | |
2081 | // start-sanitize-r5900 | |
2082 | *r5900: | |
2083 | // end-sanitize-r5900 | |
2084 | { | |
2085 | unsigned32 instruction = instruction_0; | |
2086 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
2087 | int hint UNUSED = ((instruction >> 16) & 0x0000001F); | |
2088 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
2089 | { | |
2090 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
2091 | unsigned64 paddr; | |
2092 | int uncached; | |
2093 | { | |
2094 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
2095 | Prefetch(uncached,paddr,vaddr,isDATA,hint); | |
2096 | } | |
2097 | } | |
2098 | } | |
2099 | ||
2100 | 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB | |
2101 | "sb r<RT>, <OFFSET>(r<BASE>)" | |
2102 | *mipsI: | |
2103 | *mipsII: | |
2104 | *mipsIII: | |
2105 | *mipsIV: | |
2106 | // start-sanitize-r5900 | |
2107 | *r5900: | |
2108 | // end-sanitize-r5900 | |
2109 | *r3900: | |
2110 | // start-sanitize-tx19 | |
2111 | *tx19: | |
2112 | // end-sanitize-tx19 | |
2113 | { | |
2114 | unsigned32 instruction = instruction_0; | |
2115 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
2116 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
2117 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
2118 | { | |
2119 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
2120 | unsigned64 paddr; | |
2121 | int uncached; | |
2122 | { | |
2123 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2124 | { | |
2125 | unsigned64 memval = 0; | |
2126 | unsigned64 memval1 = 0; | |
2127 | unsigned64 mask = 0x7; | |
2128 | unsigned int shift = 0; | |
2129 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
2130 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
2131 | unsigned int byte; | |
2132 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
2133 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
2134 | memval = ((unsigned64) op2 << (8 * byte)); | |
2135 | { | |
2136 | StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL); | |
2137 | } | |
2138 | } | |
2139 | } | |
2140 | } | |
2141 | } | |
2142 | ||
2143 | ||
2144 | 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC | |
2145 | "sc r<RT>, <OFFSET>(r<BASE>)" | |
2146 | *mipsII: | |
2147 | *mipsIII: | |
2148 | *mipsIV: | |
2149 | // start-sanitize-r5900 | |
2150 | *r5900: | |
2151 | // end-sanitize-r5900 | |
2152 | *r3900: | |
2153 | // start-sanitize-tx19 | |
2154 | *tx19: | |
2155 | // end-sanitize-tx19 | |
2156 | { | |
2157 | unsigned32 instruction = instruction_0; | |
2158 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
2159 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
2160 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
2161 | { | |
2162 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
2163 | unsigned64 paddr; | |
2164 | int uncached; | |
2165 | if ((vaddr & 3) != 0) | |
2166 | SignalException(AddressStore); | |
2167 | else | |
2168 | { | |
2169 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2170 | { | |
2171 | unsigned64 memval = 0; | |
2172 | unsigned64 memval1 = 0; | |
2173 | unsigned64 mask = 0x7; | |
2174 | unsigned int byte; | |
2175 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
2176 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
2177 | memval = ((unsigned64) op2 << (8 * byte)); | |
2178 | if (LLBIT) | |
2179 | { | |
2180 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
2181 | } | |
2182 | GPR[(instruction >> 16) & 0x0000001F] = LLBIT; | |
2183 | } | |
2184 | } | |
2185 | } | |
2186 | } | |
2187 | ||
2188 | ||
2189 | 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD | |
2190 | "scd r<RT>, <OFFSET>(r<BASE>)" | |
2191 | *mipsIII: | |
2192 | *mipsIV: | |
2193 | // start-sanitize-r5900 | |
2194 | *r5900: | |
2195 | // end-sanitize-r5900 | |
2196 | *r3900: | |
2197 | // start-sanitize-tx19 | |
2198 | *tx19: | |
2199 | // end-sanitize-tx19 | |
2200 | { | |
2201 | unsigned32 instruction = instruction_0; | |
2202 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
2203 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
2204 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
2205 | { | |
2206 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
2207 | unsigned64 paddr; | |
2208 | int uncached; | |
2209 | if ((vaddr & 7) != 0) | |
2210 | SignalException(AddressStore); | |
2211 | else | |
2212 | { | |
2213 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2214 | { | |
2215 | unsigned64 memval = 0; | |
2216 | unsigned64 memval1 = 0; | |
2217 | memval = op2; | |
2218 | if (LLBIT) | |
2219 | { | |
2220 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
2221 | } | |
2222 | GPR[(instruction >> 16) & 0x0000001F] = LLBIT; | |
2223 | } | |
2224 | } | |
2225 | } | |
2226 | } | |
2227 | ||
2228 | ||
2229 | 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD | |
2230 | "sd r<RT>, <OFFSET>(r<BASE>)" | |
2231 | *mipsIII: | |
2232 | *mipsIV: | |
2233 | // start-sanitize-r5900 | |
2234 | *r5900: | |
2235 | // end-sanitize-r5900 | |
2236 | *r3900: | |
2237 | // start-sanitize-tx19 | |
2238 | *tx19: | |
2239 | // end-sanitize-tx19 | |
2240 | { | |
2241 | unsigned32 instruction = instruction_0; | |
2242 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
2243 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
2244 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
2245 | { | |
2246 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
2247 | unsigned64 paddr; | |
2248 | int uncached; | |
2249 | if ((vaddr & 7) != 0) | |
2250 | SignalException(AddressStore); | |
2251 | else | |
2252 | { | |
2253 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2254 | { | |
2255 | unsigned64 memval = 0; | |
2256 | unsigned64 memval1 = 0; | |
2257 | memval = op2; | |
2258 | { | |
2259 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
2260 | } | |
2261 | } | |
2262 | } | |
2263 | } | |
2264 | } | |
2265 | ||
2266 | ||
49a6eed5 | 2267 | 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz |
f2b30012 AC |
2268 | "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
2269 | *mipsII: | |
2270 | *mipsIII: | |
2271 | *mipsIV: | |
2272 | // start-sanitize-r5900 | |
2273 | *r5900: | |
2274 | // end-sanitize-r5900 | |
2275 | *r3900: | |
2276 | // start-sanitize-tx19 | |
2277 | *tx19: | |
2278 | // end-sanitize-tx19 | |
2279 | { | |
2280 | unsigned32 instruction = instruction_0; | |
2281 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
2282 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
2283 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
2284 | { | |
2285 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
2286 | unsigned64 paddr; | |
2287 | int uncached; | |
2288 | if ((vaddr & 7) != 0) | |
2289 | SignalException(AddressStore); | |
2290 | else | |
2291 | { | |
2292 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2293 | { | |
2294 | unsigned64 memval = 0; | |
2295 | unsigned64 memval1 = 0; | |
2296 | memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg); | |
2297 | { | |
2298 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
2299 | } | |
2300 | } | |
2301 | } | |
2302 | } | |
2303 | } | |
2304 | ||
2305 | ||
2306 | 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL | |
2307 | "sdl r<RT>, <OFFSET>(r<BASE>)" | |
2308 | *mipsIII: | |
2309 | *mipsIV: | |
2310 | // start-sanitize-r5900 | |
2311 | *r5900: | |
2312 | // end-sanitize-r5900 | |
2313 | *r3900: | |
2314 | // start-sanitize-tx19 | |
2315 | *tx19: | |
2316 | // end-sanitize-tx19 | |
2317 | { | |
2318 | unsigned32 instruction = instruction_0; | |
2319 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
2320 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
2321 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
2322 | { | |
2323 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
2324 | unsigned64 paddr; | |
2325 | int uncached; | |
2326 | { | |
2327 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2328 | { | |
2329 | unsigned64 memval = 0; | |
2330 | unsigned64 memval1 = 0; | |
2331 | unsigned64 mask = 7; | |
2332 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
2333 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
2334 | int byte; | |
2335 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
2336 | byte = ((vaddr & mask) ^ bigend); | |
2337 | if (!!ByteSwapMem) | |
2338 | paddr &= ~mask; | |
2339 | memval = (op2 >> (8 * (7 - byte))); | |
2340 | StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL); | |
2341 | } | |
2342 | } | |
2343 | } | |
2344 | } | |
2345 | ||
2346 | ||
2347 | 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR | |
2348 | "sdr r<RT>, <OFFSET>(r<BASE>)" | |
2349 | *mipsIII: | |
2350 | *mipsIV: | |
2351 | // start-sanitize-r5900 | |
2352 | *r5900: | |
2353 | // end-sanitize-r5900 | |
2354 | *r3900: | |
2355 | // start-sanitize-tx19 | |
2356 | *tx19: | |
2357 | // end-sanitize-tx19 | |
2358 | { | |
2359 | unsigned32 instruction = instruction_0; | |
2360 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
2361 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
2362 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
2363 | { | |
2364 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
2365 | unsigned64 paddr; | |
2366 | int uncached; | |
2367 | { | |
2368 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2369 | { | |
2370 | unsigned64 memval = 0; | |
2371 | unsigned64 memval1 = 0; | |
2372 | unsigned64 mask = 7; | |
2373 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
2374 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
2375 | int byte; | |
2376 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
2377 | byte = ((vaddr & mask) ^ bigend); | |
2378 | if (!ByteSwapMem) | |
2379 | paddr &= ~mask; | |
2380 | memval = ((unsigned64) op2 << (byte * 8)); | |
2381 | StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,memval1,paddr,vaddr,isREAL); | |
2382 | } | |
2383 | } | |
2384 | } | |
2385 | } | |
2386 | ||
2387 | ||
2388 | 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH | |
2389 | "sh r<RT>, <OFFSET>(r<BASE>)" | |
2390 | *mipsI: | |
2391 | *mipsII: | |
2392 | *mipsIII: | |
2393 | *mipsIV: | |
2394 | // start-sanitize-r5900 | |
2395 | *r5900: | |
2396 | // end-sanitize-r5900 | |
2397 | *r3900: | |
2398 | // start-sanitize-tx19 | |
2399 | *tx19: | |
2400 | // end-sanitize-tx19 | |
2401 | { | |
2402 | unsigned32 instruction = instruction_0; | |
2403 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
2404 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
2405 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
2406 | { | |
2407 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
2408 | unsigned64 paddr; | |
2409 | int uncached; | |
2410 | if ((vaddr & 1) != 0) | |
2411 | SignalException(AddressStore); | |
2412 | else | |
2413 | { | |
2414 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2415 | { | |
2416 | unsigned64 memval = 0; | |
2417 | unsigned64 memval1 = 0; | |
2418 | unsigned64 mask = 0x7; | |
2419 | unsigned int shift = 1; | |
2420 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
2421 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
2422 | unsigned int byte; | |
2423 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
2424 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
2425 | memval = ((unsigned64) op2 << (8 * byte)); | |
2426 | { | |
2427 | StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL); | |
2428 | } | |
2429 | } | |
2430 | } | |
2431 | } | |
2432 | } | |
2433 | ||
2434 | ||
2435 | 00000000000,5.RT,5.RD,5.SA,000000:SPECIAL:32::SLL | |
2436 | "sll r<RD>, r<RT>, <SA>" | |
2437 | *mipsI: | |
2438 | *mipsII: | |
2439 | *mipsIII: | |
2440 | *mipsIV: | |
2441 | // start-sanitize-r5900 | |
2442 | *r5900: | |
2443 | // end-sanitize-r5900 | |
2444 | *r3900: | |
2445 | // start-sanitize-tx19 | |
2446 | *tx19: | |
2447 | // end-sanitize-tx19 | |
2448 | { | |
2449 | int s = SA; | |
2450 | unsigned32 temp = (GPR (RT) << s); | |
2451 | GPR (RD) = EXTEND32 (temp); | |
2452 | } | |
2453 | ||
2454 | ||
2455 | 000000,ooooo,5.RT,5.RD,00000000100:SPECIAL:32::SLLV | |
2456 | "sllv r<RD>, r<RT>, r<RS>" | |
2457 | *mipsI: | |
2458 | *mipsII: | |
2459 | *mipsIII: | |
2460 | *mipsIV: | |
2461 | // start-sanitize-r5900 | |
2462 | *r5900: | |
2463 | // end-sanitize-r5900 | |
2464 | *r3900: | |
2465 | // start-sanitize-tx19 | |
2466 | *tx19: | |
2467 | // end-sanitize-tx19 | |
2468 | { | |
2469 | int s = MASKED (GPR (RS), 4, 0); | |
2470 | unsigned32 temp = (GPR (RT) << s); | |
2471 | GPR (RD) = EXTEND32 (temp); | |
2472 | } | |
2473 | ||
2474 | ||
2475 | 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT | |
2476 | "slt r<RD>, r<RS>, r<RT>" | |
2477 | *mipsI: | |
2478 | *mipsII: | |
2479 | *mipsIII: | |
2480 | *mipsIV: | |
2481 | // start-sanitize-r5900 | |
2482 | *r5900: | |
2483 | // end-sanitize-r5900 | |
2484 | *r3900: | |
2485 | // start-sanitize-tx19 | |
2486 | *tx19: | |
2487 | // end-sanitize-tx19 | |
2488 | { | |
2489 | if (GPR (RS) < GPR (RT)) | |
2490 | GPR (RD) = 1; | |
2491 | else | |
2492 | GPR (RD) = 0; | |
2493 | } | |
2494 | ||
2495 | ||
2496 | 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI | |
2497 | "slti r<RD>, r<RS>, <IMMEDIATE>" | |
2498 | *mipsI: | |
2499 | *mipsII: | |
2500 | *mipsIII: | |
2501 | *mipsIV: | |
2502 | // start-sanitize-r5900 | |
2503 | *r5900: | |
2504 | // end-sanitize-r5900 | |
2505 | *r3900: | |
2506 | // start-sanitize-tx19 | |
2507 | *tx19: | |
2508 | // end-sanitize-tx19 | |
2509 | { | |
2510 | if (GPR (RS) < EXTEND16 (IMMEDIATE)) | |
2511 | GPR (RD) = 1; | |
2512 | else | |
2513 | GPR (RD) = 0; | |
2514 | } | |
2515 | ||
2516 | ||
2517 | 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU | |
2518 | "sltiu r<RD>, r<RS>, <IMMEDIATE>" | |
2519 | *mipsI: | |
2520 | *mipsII: | |
2521 | *mipsIII: | |
2522 | *mipsIV: | |
2523 | // start-sanitize-r5900 | |
2524 | *r5900: | |
2525 | // end-sanitize-r5900 | |
2526 | *r3900: | |
2527 | // start-sanitize-tx19 | |
2528 | *tx19: | |
2529 | // end-sanitize-tx19 | |
2530 | { | |
2531 | if ((unsigned_word) GPR (RS) < (unsigned_word) EXTEND16 (IMMEDIATE)) | |
2532 | GPR (RD) = 1; | |
2533 | else | |
2534 | GPR (RD) = 0; | |
2535 | } | |
2536 | ||
2537 | 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU | |
2538 | "sltu r<RD>, r<RS>, r<RT>" | |
2539 | *mipsI: | |
2540 | *mipsII: | |
2541 | *mipsIII: | |
2542 | *mipsIV: | |
2543 | // start-sanitize-r5900 | |
2544 | *r5900: | |
2545 | // end-sanitize-r5900 | |
2546 | *r3900: | |
2547 | // start-sanitize-tx19 | |
2548 | *tx19: | |
2549 | // end-sanitize-tx19 | |
2550 | { | |
2551 | if ((unsigned_word) GPR (RS) < (unsigned_word) GPR (RT)) | |
2552 | GPR (RD) = 1; | |
2553 | else | |
2554 | GPR (RD) = 0; | |
2555 | } | |
2556 | ||
2557 | ||
2558 | 000000,00000,5.RT,5.RD,5.SA,000011:SPECIAL:32::SRA | |
2559 | "sra r<RD>, r<RT>, <SA>" | |
2560 | *mipsI: | |
2561 | *mipsII: | |
2562 | *mipsIII: | |
2563 | *mipsIV: | |
2564 | // start-sanitize-r5900 | |
2565 | *r5900: | |
2566 | // end-sanitize-r5900 | |
2567 | *r3900: | |
2568 | // start-sanitize-tx19 | |
2569 | *tx19: | |
2570 | // end-sanitize-tx19 | |
2571 | { | |
2572 | int s = SA; | |
2573 | signed32 temp = (signed32) GPR (RT) >> s; | |
2574 | GPR (RD) = EXTEND32 (temp); | |
2575 | } | |
2576 | ||
2577 | ||
2578 | 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV | |
2579 | "srav r<RD>, r<RT>, r<RS>" | |
2580 | *mipsI: | |
2581 | *mipsII: | |
2582 | *mipsIII: | |
2583 | *mipsIV: | |
2584 | // start-sanitize-r5900 | |
2585 | *r5900: | |
2586 | // end-sanitize-r5900 | |
2587 | *r3900: | |
2588 | // start-sanitize-tx19 | |
2589 | *tx19: | |
2590 | // end-sanitize-tx19 | |
2591 | { | |
2592 | int s = MASKED (GPR (RS), 4, 0); | |
2593 | signed32 temp = (signed32) GPR (RT) >> s; | |
2594 | GPR (RD) = EXTEND32 (temp); | |
2595 | } | |
2596 | ||
2597 | ||
2598 | 000000,00000,5.RT,5.RD,5.SA,000010:SPECIAL:32::SRL | |
2599 | "srl r<RD>, r<RT>, <SA>" | |
2600 | *mipsI: | |
2601 | *mipsII: | |
2602 | *mipsIII: | |
2603 | *mipsIV: | |
2604 | // start-sanitize-r5900 | |
2605 | *r5900: | |
2606 | // end-sanitize-r5900 | |
2607 | *r3900: | |
2608 | // start-sanitize-tx19 | |
2609 | *tx19: | |
2610 | // end-sanitize-tx19 | |
2611 | { | |
2612 | int s = SA; | |
2613 | unsigned32 temp = (unsigned32) GPR (RT) >> s; | |
2614 | GPR (RD) = EXTEND32 (temp); | |
2615 | } | |
2616 | ||
2617 | ||
2618 | 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV | |
2619 | "srlv r<RD>, r<RT>, r<RS>" | |
2620 | *mipsI: | |
2621 | *mipsII: | |
2622 | *mipsIII: | |
2623 | *mipsIV: | |
2624 | // start-sanitize-r5900 | |
2625 | *r5900: | |
2626 | // end-sanitize-r5900 | |
2627 | *r3900: | |
2628 | // start-sanitize-tx19 | |
2629 | *tx19: | |
2630 | // end-sanitize-tx19 | |
2631 | { | |
2632 | int s = MASKED (GPR (RS), 4, 0); | |
2633 | unsigned32 temp = (unsigned32) GPR (RT) >> s; | |
2634 | GPR (RD) = EXTEND32 (temp); | |
2635 | } | |
2636 | ||
2637 | ||
2638 | 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB | |
2639 | "sub r<RD>, r<RS>, r<RT>" | |
2640 | *mipsI: | |
2641 | *mipsII: | |
2642 | *mipsIII: | |
2643 | *mipsIV: | |
2644 | // start-sanitize-r5900 | |
2645 | *r5900: | |
2646 | // end-sanitize-r5900 | |
2647 | *r3900: | |
2648 | // start-sanitize-tx19 | |
2649 | *tx19: | |
2650 | // end-sanitize-tx19 | |
2651 | { | |
2652 | ALU32_BEGIN (GPR (RS)); | |
2653 | ALU32_SUB (GPR (RT)); | |
2654 | ALU32_END (GPR (RD)); | |
2655 | } | |
2656 | ||
2657 | ||
2658 | 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU | |
2659 | "subu r<RD>, r<RS>, r<RT>" | |
2660 | *mipsI: | |
2661 | *mipsII: | |
2662 | *mipsIII: | |
2663 | *mipsIV: | |
2664 | // start-sanitize-r5900 | |
2665 | *r5900: | |
2666 | // end-sanitize-r5900 | |
2667 | *r3900: | |
2668 | // start-sanitize-tx19 | |
2669 | *tx19: | |
2670 | // end-sanitize-tx19 | |
2671 | { | |
2672 | GPR (RD) = EXTEND32 (GPR (RS) - GPR (RT)); | |
2673 | } | |
2674 | ||
2675 | ||
2676 | 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW | |
2677 | "sw r<RT>, <OFFSET>(r<BASE>)" | |
2678 | *mipsI: | |
2679 | *mipsII: | |
2680 | *mipsIII: | |
2681 | *mipsIV: | |
2682 | // start-sanitize-r5900 | |
2683 | *r5900: | |
2684 | // end-sanitize-r5900 | |
2685 | *r3900: | |
2686 | // start-sanitize-tx19 | |
2687 | *tx19: | |
2688 | // end-sanitize-tx19 | |
2689 | { | |
2690 | unsigned32 instruction = instruction_0; | |
2691 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
2692 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
2693 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
2694 | { | |
2695 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
2696 | unsigned64 paddr; | |
2697 | int uncached; | |
2698 | if ((vaddr & 3) != 0) | |
2699 | SignalException(AddressStore); | |
2700 | else | |
2701 | { | |
2702 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2703 | { | |
2704 | unsigned64 memval = 0; | |
2705 | unsigned64 memval1 = 0; | |
2706 | unsigned64 mask = 0x7; | |
2707 | unsigned int byte; | |
2708 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
2709 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
2710 | memval = ((unsigned64) op2 << (8 * byte)); | |
2711 | { | |
2712 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
2713 | } | |
2714 | } | |
2715 | } | |
2716 | } | |
2717 | } | |
2718 | ||
2719 | ||
49a6eed5 | 2720 | 1110,ZZ!0!1!3,5.RS,5.RT,16.OFFSET:NORMAL:32::SWCz |
f2b30012 AC |
2721 | "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
2722 | *mipsI: | |
2723 | *mipsII: | |
2724 | *mipsIII: | |
2725 | *mipsIV: | |
2726 | // start-sanitize-r5900 | |
2727 | *r5900: | |
2728 | // end-sanitize-r5900 | |
2729 | *r3900: | |
2730 | // start-sanitize-tx19 | |
2731 | *tx19: | |
2732 | // end-sanitize-tx19 | |
2733 | { | |
2734 | unsigned32 instruction = instruction_0; | |
2735 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
2736 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
2737 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
2738 | { | |
2739 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
2740 | unsigned64 paddr; | |
2741 | int uncached; | |
2742 | if ((vaddr & 3) != 0) | |
2743 | SignalException(AddressStore); | |
2744 | else | |
2745 | { | |
2746 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2747 | { | |
2748 | unsigned64 memval = 0; | |
2749 | unsigned64 memval1 = 0; | |
2750 | unsigned64 mask = 0x7; | |
2751 | unsigned int byte; | |
2752 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
2753 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
2754 | memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte)); | |
2755 | { | |
2756 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
2757 | } | |
2758 | } | |
2759 | } | |
2760 | } | |
2761 | } | |
2762 | ||
2763 | ||
2764 | 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL | |
2765 | "swl r<RT>, <OFFSET>(r<BASE>)" | |
2766 | *mipsI: | |
2767 | *mipsII: | |
2768 | *mipsIII: | |
2769 | *mipsIV: | |
2770 | // start-sanitize-r5900 | |
2771 | *r5900: | |
2772 | // end-sanitize-r5900 | |
2773 | *r3900: | |
2774 | // start-sanitize-tx19 | |
2775 | *tx19: | |
2776 | // end-sanitize-tx19 | |
2777 | { | |
2778 | unsigned32 instruction = instruction_0; | |
2779 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
2780 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
2781 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
2782 | { | |
2783 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
2784 | unsigned64 paddr; | |
2785 | int uncached; | |
2786 | { | |
2787 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2788 | { | |
2789 | unsigned64 memval = 0; | |
2790 | unsigned64 memval1 = 0; | |
2791 | unsigned64 mask = 3; | |
2792 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
2793 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
2794 | int byte; | |
2795 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
2796 | byte = ((vaddr & mask) ^ bigend); | |
2797 | if (!!ByteSwapMem) | |
2798 | paddr &= ~mask; | |
2799 | memval = (op2 >> (8 * (3 - byte))); | |
2800 | if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { | |
2801 | memval <<= 32; | |
2802 | } | |
2803 | StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL); | |
2804 | } | |
2805 | } | |
2806 | } | |
2807 | } | |
2808 | ||
2809 | ||
2810 | 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR | |
2811 | "swr r<RT>, <OFFSET>(r<BASE>)" | |
2812 | *mipsI: | |
2813 | *mipsII: | |
2814 | *mipsIII: | |
2815 | *mipsIV: | |
2816 | // start-sanitize-r5900 | |
2817 | *r5900: | |
2818 | // end-sanitize-r5900 | |
2819 | *r3900: | |
2820 | // start-sanitize-tx19 | |
2821 | *tx19: | |
2822 | // end-sanitize-tx19 | |
2823 | { | |
2824 | unsigned32 instruction = instruction_0; | |
2825 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
2826 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
2827 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
2828 | { | |
2829 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
2830 | unsigned64 paddr; | |
2831 | int uncached; | |
2832 | { | |
2833 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2834 | { | |
2835 | unsigned64 memval = 0; | |
2836 | unsigned64 memval1 = 0; | |
2837 | unsigned64 mask = 3; | |
2838 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
2839 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
2840 | int byte; | |
2841 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
2842 | byte = ((vaddr & mask) ^ bigend); | |
2843 | if (!ByteSwapMem) | |
2844 | paddr &= ~mask; | |
2845 | memval = ((unsigned64) op2 << (byte * 8)); | |
2846 | if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { | |
2847 | memval <<= 32; | |
2848 | } | |
2849 | StoreMemory(uncached,(AccessLength_WORD - byte),memval,memval1,paddr,vaddr,isREAL); | |
2850 | } | |
2851 | } | |
2852 | } | |
2853 | } | |
2854 | ||
2855 | ||
2856 | 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC | |
2857 | "sync":STYPE == 0 | |
2858 | "sync <STYPE>" | |
2859 | *mipsII: | |
2860 | *mipsIII: | |
2861 | *mipsIV: | |
2862 | // start-sanitize-r5900 | |
2863 | *r5900: | |
2864 | // end-sanitize-r5900 | |
2865 | *r3900: | |
2866 | // start-sanitize-tx19 | |
2867 | *tx19: | |
2868 | // end-sanitize-tx19 | |
2869 | { | |
2870 | SyncOperation (STYPE); | |
2871 | } | |
2872 | ||
2873 | ||
2874 | 000000,20.CODE,001100:SPECIAL:32::SYSCALL | |
2875 | "syscall <CODE>" | |
2876 | *mipsI: | |
2877 | *mipsII: | |
2878 | *mipsIII: | |
2879 | *mipsIV: | |
2880 | // start-sanitize-r5900 | |
2881 | *r5900: | |
2882 | // end-sanitize-r5900 | |
2883 | *r3900: | |
2884 | // start-sanitize-tx19 | |
2885 | *tx19: | |
2886 | // end-sanitize-tx19 | |
2887 | { | |
2888 | SignalException (SystemCall, instruction_0); | |
2889 | } | |
2890 | ||
2891 | ||
2892 | 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ | |
2893 | "teq r<RS>, r<RT>" | |
2894 | *mipsII: | |
2895 | *mipsIII: | |
2896 | *mipsIV: | |
2897 | // start-sanitize-r5900 | |
2898 | *r5900: | |
2899 | // end-sanitize-r5900 | |
2900 | *r3900: | |
2901 | // start-sanitize-tx19 | |
2902 | *tx19: | |
2903 | // end-sanitize-tx19 | |
2904 | { | |
2905 | if (GPR (RS) == GPR (RT)) | |
2906 | SignalException (Trap, instruction_0); | |
2907 | } | |
2908 | ||
2909 | ||
2910 | 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI | |
2911 | "teqi r<RS>, <IMMEDIATE>" | |
2912 | *mipsII: | |
2913 | *mipsIII: | |
2914 | *mipsIV: | |
2915 | // start-sanitize-r5900 | |
2916 | *r5900: | |
2917 | // end-sanitize-r5900 | |
2918 | *r3900: | |
2919 | // start-sanitize-tx19 | |
2920 | *tx19: | |
2921 | // end-sanitize-tx19 | |
2922 | { | |
2923 | if (GPR (RS) == EXTEND16 (IMMEDIATE)) | |
2924 | SignalException (Trap, instruction_0); | |
2925 | } | |
2926 | ||
2927 | ||
2928 | 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE | |
2929 | "tge r<RS>, r<RT>" | |
2930 | *mipsII: | |
2931 | *mipsIII: | |
2932 | *mipsIV: | |
2933 | // start-sanitize-r5900 | |
2934 | *r5900: | |
2935 | // end-sanitize-r5900 | |
2936 | *r3900: | |
2937 | // start-sanitize-tx19 | |
2938 | *tx19: | |
2939 | // end-sanitize-tx19 | |
2940 | { | |
2941 | if (GPR (RS) >= GPR (RT)) | |
2942 | SignalException (Trap, instruction_0); | |
2943 | } | |
2944 | ||
2945 | ||
2946 | 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI | |
2947 | "tgei r<RS>, <IMMEDIATE>" | |
2948 | *mipsII: | |
2949 | *mipsIII: | |
2950 | *mipsIV: | |
2951 | // start-sanitize-r5900 | |
2952 | *r5900: | |
2953 | // end-sanitize-r5900 | |
2954 | *r3900: | |
2955 | // start-sanitize-tx19 | |
2956 | *tx19: | |
2957 | // end-sanitize-tx19 | |
2958 | { | |
2959 | if (GPR (RS) >= EXTEND16 (IMMEDIATE)) | |
2960 | SignalException (Trap, instruction_0); | |
2961 | } | |
2962 | ||
2963 | ||
2964 | 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU | |
2965 | "tgeiu r<RS>, <IMMEDIATE>" | |
2966 | *mipsII: | |
2967 | *mipsIII: | |
2968 | *mipsIV: | |
2969 | // start-sanitize-r5900 | |
2970 | *r5900: | |
2971 | // end-sanitize-r5900 | |
2972 | *r3900: | |
2973 | // start-sanitize-tx19 | |
2974 | *tx19: | |
2975 | // end-sanitize-tx19 | |
2976 | { | |
2977 | if ((unsigned_word) GPR (RS) >= (unsigned_word) EXTEND16 (IMMEDIATE)) | |
2978 | SignalException (Trap, instruction_0); | |
2979 | } | |
2980 | ||
2981 | ||
2982 | 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU | |
2983 | "tgeu r<RS>, r<RT>" | |
2984 | *mipsII: | |
2985 | *mipsIII: | |
2986 | *mipsIV: | |
2987 | // start-sanitize-r5900 | |
2988 | *r5900: | |
2989 | // end-sanitize-r5900 | |
2990 | *r3900: | |
2991 | // start-sanitize-tx19 | |
2992 | *tx19: | |
2993 | // end-sanitize-tx19 | |
2994 | { | |
2995 | if ((unsigned_word) GPR (RS) >= (unsigned_word) GPR (RT)) | |
2996 | SignalException (Trap, instruction_0); | |
2997 | } | |
2998 | ||
2999 | ||
3000 | 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT | |
3001 | "tlt r<RS>, r<RT>" | |
3002 | *mipsII: | |
3003 | *mipsIII: | |
3004 | *mipsIV: | |
3005 | // start-sanitize-r5900 | |
3006 | *r5900: | |
3007 | // end-sanitize-r5900 | |
3008 | *r3900: | |
3009 | // start-sanitize-tx19 | |
3010 | *tx19: | |
3011 | // end-sanitize-tx19 | |
3012 | { | |
3013 | if (GPR (RS) < GPR (RT)) | |
3014 | SignalException (Trap, instruction_0); | |
3015 | } | |
3016 | ||
3017 | ||
3018 | 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI | |
3019 | "tlti r<RS>, <IMMEDIATE>" | |
3020 | *mipsII: | |
3021 | *mipsIII: | |
3022 | *mipsIV: | |
3023 | // start-sanitize-r5900 | |
3024 | *r5900: | |
3025 | // end-sanitize-r5900 | |
3026 | *r3900: | |
3027 | // start-sanitize-tx19 | |
3028 | *tx19: | |
3029 | // end-sanitize-tx19 | |
3030 | { | |
3031 | if (GPR (RS) < EXTEND16 (IMMEDIATE)) | |
3032 | SignalException (Trap, instruction_0); | |
3033 | } | |
3034 | ||
3035 | ||
3036 | 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU | |
3037 | "tltiu r<RS>, <IMMEDIATE>" | |
3038 | *mipsII: | |
3039 | *mipsIII: | |
3040 | *mipsIV: | |
3041 | // start-sanitize-r5900 | |
3042 | *r5900: | |
3043 | // end-sanitize-r5900 | |
3044 | *r3900: | |
3045 | // start-sanitize-tx19 | |
3046 | *tx19: | |
3047 | // end-sanitize-tx19 | |
3048 | { | |
3049 | if ((unsigned_word) GPR (RS) < (unsigned_word) EXTEND16 (IMMEDIATE)) | |
3050 | SignalException (Trap, instruction_0); | |
3051 | } | |
3052 | ||
3053 | ||
3054 | 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU | |
3055 | "tltu r<RS>, r<RT>" | |
3056 | *mipsII: | |
3057 | *mipsIII: | |
3058 | *mipsIV: | |
3059 | // start-sanitize-r5900 | |
3060 | *r5900: | |
3061 | // end-sanitize-r5900 | |
3062 | *r3900: | |
3063 | // start-sanitize-tx19 | |
3064 | *tx19: | |
3065 | // end-sanitize-tx19 | |
3066 | { | |
3067 | if ((unsigned_word) GPR (RS) < (unsigned_word) GPR (RT)) | |
3068 | SignalException (Trap, instruction_0); | |
3069 | } | |
3070 | ||
3071 | ||
3072 | 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE | |
3073 | "tne r<RS>, r<RT>" | |
3074 | *mipsII: | |
3075 | *mipsIII: | |
3076 | *mipsIV: | |
3077 | // start-sanitize-r5900 | |
3078 | *r5900: | |
3079 | // end-sanitize-r5900 | |
3080 | *r3900: | |
3081 | // start-sanitize-tx19 | |
3082 | *tx19: | |
3083 | // end-sanitize-tx19 | |
3084 | { | |
3085 | if (GPR (RS) != GPR (RT)) | |
3086 | SignalException (Trap, instruction_0); | |
3087 | } | |
3088 | ||
3089 | ||
3090 | 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI | |
3091 | "tne r<RS>, <IMMEDIATE>" | |
3092 | *mipsII: | |
3093 | *mipsIII: | |
3094 | *mipsIV: | |
3095 | // start-sanitize-r5900 | |
3096 | *r5900: | |
3097 | // end-sanitize-r5900 | |
3098 | *r3900: | |
3099 | // start-sanitize-tx19 | |
3100 | *tx19: | |
3101 | // end-sanitize-tx19 | |
3102 | { | |
3103 | if (GPR (RS) != EXTEND16 (IMMEDIATE)) | |
3104 | SignalException (Trap, instruction_0); | |
3105 | } | |
3106 | ||
3107 | ||
3108 | 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR | |
3109 | "xor r<RD>, r<RS>, r<RT>" | |
3110 | *mipsI: | |
3111 | *mipsII: | |
3112 | *mipsIII: | |
3113 | *mipsIV: | |
3114 | // start-sanitize-r5900 | |
3115 | *r5900: | |
3116 | // end-sanitize-r5900 | |
3117 | *r3900: | |
3118 | // start-sanitize-tx19 | |
3119 | *tx19: | |
3120 | // end-sanitize-tx19 | |
3121 | { | |
3122 | GPR (RD) = GPR (RS) ^ GPR (RT); | |
3123 | } | |
3124 | ||
3125 | ||
3126 | 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI | |
3127 | "xori r<RD>, r<RS>, <IMMEDIATE>" | |
3128 | *mipsI: | |
3129 | *mipsII: | |
3130 | *mipsIII: | |
3131 | *mipsIV: | |
3132 | // start-sanitize-r5900 | |
3133 | *r5900: | |
3134 | // end-sanitize-r5900 | |
3135 | *r3900: | |
3136 | // start-sanitize-tx19 | |
3137 | *tx19: | |
3138 | // end-sanitize-tx19 | |
3139 | { | |
3140 | GPR (RD) = GPR (RS) ^ IMMEDIATE; | |
3141 | } | |
3142 | ||
3143 | \f | |
3144 | // | |
3145 | // MIPS Architecture: | |
3146 | // | |
3147 | // FPU Instruction Set (COP1 & COP1X) | |
3148 | // | |
3149 | ||
3150 | ||
3151 | 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt | |
3152 | "abs.%s<FMT> f<FD>, f<FS>" | |
3153 | *mipsI: | |
3154 | *mipsII: | |
3155 | *mipsIII: | |
3156 | *mipsIV: | |
3157 | // start-sanitize-r5900 | |
3158 | *r5900: | |
3159 | // end-sanitize-r5900 | |
3160 | *r3900: | |
3161 | // start-sanitize-tx19 | |
3162 | *tx19: | |
3163 | // end-sanitize-tx19 | |
3164 | { | |
3165 | unsigned32 instruction = instruction_0; | |
3166 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3167 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3168 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3169 | { | |
3170 | if ((format != fmt_single) && (format != fmt_double)) | |
3171 | SignalException(ReservedInstruction,instruction); | |
3172 | else | |
3173 | StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format)); | |
3174 | } | |
3175 | } | |
3176 | ||
3177 | ||
3178 | 010001,10,3.FMT,kkkkk,5.FS,5.FD,000000:COP1:32,f::ADD | |
3179 | "add.%s<FMT> f<FD>, f<FS>, f<FT>" | |
3180 | *mipsI: | |
3181 | *mipsII: | |
3182 | *mipsIII: | |
3183 | *mipsIV: | |
3184 | // start-sanitize-r5900 | |
3185 | *r5900: | |
3186 | // end-sanitize-r5900 | |
3187 | *r3900: | |
3188 | // start-sanitize-tx19 | |
3189 | *tx19: | |
3190 | // end-sanitize-tx19 | |
3191 | { | |
3192 | unsigned32 instruction = instruction_0; | |
3193 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3194 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3195 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
3196 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3197 | { | |
3198 | if ((format != fmt_single) && (format != fmt_double)) | |
3199 | SignalException(ReservedInstruction,instruction); | |
3200 | else | |
3201 | StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format)); | |
3202 | } | |
3203 | } | |
3204 | ||
3205 | ||
3206 | // | |
3207 | // FIXME: This does not correctly resolve mipsI-mipsIV differences. | |
3208 | // | |
3209 | // BC1F | |
3210 | // BC1FL | |
3211 | // BC1T | |
3212 | // BC1TL | |
3213 | 010001,01000,3.CC,1.N,1.DTF,16.OFFSET:COP1S:32,f::BC1 | |
3214 | "bc1%s<ND,TF> <OFFSET>":CC == 0 | |
3215 | "bc1%s<ND,TF> <CC>, <OFFSET>" | |
3216 | *mipsI: | |
3217 | *mipsII: | |
3218 | *mipsIII: | |
3219 | *mipsIV: | |
3220 | // start-sanitize-r5900 | |
3221 | *r5900: | |
3222 | // end-sanitize-r5900 | |
3223 | *r3900: | |
3224 | // start-sanitize-tx19 | |
3225 | *tx19: | |
3226 | // end-sanitize-tx19 | |
3227 | { | |
3228 | unsigned32 instruction = instruction_0; | |
3229 | t_reg offset UNUSED = SIGNEXTEND((t_reg)(((instruction >> 0) & 0x0000FFFF) << 2),18); | |
3230 | int boolean UNUSED = ((instruction >> 16) & 0x00000001); | |
3231 | int likely UNUSED = ((instruction >> 17) & 0x00000001); | |
3232 | int condition_code UNUSED = ((instruction >> 18) & 0x00000007); | |
3233 | { | |
3234 | if (condition_code != 0) | |
3235 | SignalException(ReservedInstruction,instruction); | |
3236 | else { | |
3237 | int condition = (PREVCOC1() == boolean); | |
3238 | /* NOTE: The branch occurs AFTER the next instruction has been executed */ | |
3239 | if (condition) { | |
3240 | DSPC = (PC + offset); | |
3241 | DELAYSLOT(); | |
3242 | } | |
3243 | else if (likely) { | |
3244 | NULLIFY(); | |
3245 | } | |
3246 | } | |
3247 | } | |
3248 | } | |
3249 | ||
3250 | ||
3251 | // | |
3252 | // FIXME: This does not correctly differentiate between mips* | |
3253 | // | |
3254 | 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt | |
3255 | "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0 | |
3256 | "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>" | |
3257 | *mipsI: | |
3258 | *mipsII: | |
3259 | *mipsIII: | |
3260 | *mipsIV: | |
3261 | // start-sanitize-r5900 | |
3262 | *r5900: | |
3263 | // end-sanitize-r5900 | |
3264 | *r3900: | |
3265 | // start-sanitize-tx19 | |
3266 | *tx19: | |
3267 | // end-sanitize-tx19 | |
3268 | { | |
3269 | unsigned32 instruction = instruction_0; | |
3270 | int cmpflags UNUSED = ((instruction >> 0) & 0x0000000F); | |
3271 | int condition_code UNUSED = ((instruction >> 8) & 0x00000007); | |
3272 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3273 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
3274 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3275 | if (condition_code != 0) | |
3276 | { | |
3277 | SignalException(ReservedInstruction,instruction); | |
3278 | } | |
3279 | else | |
3280 | { | |
3281 | if ((format != fmt_single) && (format != fmt_double)) | |
3282 | SignalException(ReservedInstruction,instruction); | |
3283 | else { | |
3284 | if (condition_code != 0) | |
3285 | SignalException(ReservedInstruction,instruction); | |
3286 | else | |
3287 | { | |
3288 | int ignore = 0; | |
3289 | int less = 0; | |
3290 | int equal = 0; | |
3291 | int unordered = 1; | |
3292 | unsigned64 ofs = ValueFPR(fs,format); | |
3293 | unsigned64 oft = ValueFPR(ft,format); | |
3294 | if (NaN(ofs,format) || NaN(oft,format)) { | |
3295 | if (FCSR & FP_ENABLE(IO)) { | |
3296 | FCSR |= FP_CAUSE(IO); | |
3297 | SignalException(FPE); | |
3298 | ignore = 1; | |
3299 | } | |
3300 | } else { | |
3301 | less = Less(ofs,oft,format); | |
3302 | equal = Equal(ofs,oft,format); | |
3303 | unordered = 0; | |
3304 | } | |
3305 | if (!ignore) { | |
3306 | int condition = (((cmpflags & (1 << 2)) && less) || ((cmpflags & (1 << 1)) && equal) || ((cmpflags & (1 << 0)) && unordered)); | |
3307 | SETFCC(condition_code,condition); | |
3308 | } | |
3309 | } | |
3310 | } | |
3311 | } | |
3312 | } | |
3313 | ||
3314 | ||
3315 | 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt | |
3316 | "ceil.l.%s<FMT> f<FD>, f<FS>" | |
3317 | *mipsIII: | |
3318 | *mipsIV: | |
3319 | // start-sanitize-r5900 | |
3320 | *r5900: | |
3321 | // end-sanitize-r5900 | |
3322 | *r3900: | |
3323 | // start-sanitize-tx19 | |
3324 | *tx19: | |
3325 | // end-sanitize-tx19 | |
3326 | { | |
3327 | unsigned32 instruction = instruction_0; | |
3328 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3329 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3330 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3331 | { | |
3332 | if ((format != fmt_single) && (format != fmt_double)) | |
3333 | SignalException(ReservedInstruction,instruction); | |
3334 | else | |
3335 | StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long)); | |
3336 | } | |
3337 | } | |
3338 | ||
3339 | ||
3340 | 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W | |
3341 | *mipsII: | |
3342 | *mipsIII: | |
3343 | *mipsIV: | |
3344 | // start-sanitize-r5900 | |
3345 | *r5900: | |
3346 | // end-sanitize-r5900 | |
3347 | *r3900: | |
3348 | // start-sanitize-tx19 | |
3349 | *tx19: | |
3350 | // end-sanitize-tx19 | |
3351 | { | |
3352 | unsigned32 instruction = instruction_0; | |
3353 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3354 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3355 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3356 | { | |
3357 | if ((format != fmt_single) && (format != fmt_double)) | |
3358 | SignalException(ReservedInstruction,instruction); | |
3359 | else | |
3360 | StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word)); | |
3361 | } | |
3362 | } | |
3363 | ||
3364 | ||
3365 | // CFC1 | |
3366 | // CTC1 | |
3367 | 01000100,x,10,kkkkk,vvvvv,00000000000:COP1S:32::CxC1 | |
3368 | *mipsI: | |
3369 | *mipsII: | |
3370 | *mipsIII: | |
3371 | *mipsIV: | |
3372 | // start-sanitize-r5900 | |
3373 | *r5900: | |
3374 | // end-sanitize-r5900 | |
3375 | *r3900: | |
3376 | // start-sanitize-tx19 | |
3377 | *tx19: | |
3378 | // end-sanitize-tx19 | |
3379 | { | |
3380 | unsigned32 instruction = instruction_0; | |
3381 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3382 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
3383 | int to UNUSED = ((instruction >> 23) & 0x00000001); | |
3384 | { | |
3385 | if (to) { | |
3386 | if (fs == 0) { | |
3387 | PENDING_FILL((fs + FCR0IDX),VL4_8(GPR[ft])); | |
3388 | } else if (fs == 31) { | |
3389 | PENDING_FILL((fs + FCR31IDX),VL4_8(GPR[ft])); | |
3390 | } /* else NOP */ | |
3391 | PENDING_FILL(COCIDX,0); /* special case */ | |
3392 | } else { /* control from */ | |
3393 | if (fs == 0) { | |
3394 | PENDING_FILL(ft,SIGNEXTEND(FCR0,32)); | |
3395 | } else if (fs == 31) { | |
3396 | PENDING_FILL(ft,SIGNEXTEND(FCR31,32)); | |
3397 | } /* else NOP */ | |
3398 | } | |
3399 | } | |
3400 | } | |
3401 | ||
3402 | ||
3403 | // | |
3404 | // FIXME: Does not correctly differentiate between mips* | |
3405 | // | |
3406 | 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt | |
3407 | "cvt.d.%s<FMT> f<FD>, f<FS>" | |
3408 | *mipsI: | |
3409 | *mipsII: | |
3410 | *mipsIII: | |
3411 | *mipsIV: | |
3412 | // start-sanitize-r5900 | |
3413 | *r5900: | |
3414 | // end-sanitize-r5900 | |
3415 | *r3900: | |
3416 | // start-sanitize-tx19 | |
3417 | *tx19: | |
3418 | // end-sanitize-tx19 | |
3419 | { | |
3420 | unsigned32 instruction = instruction_0; | |
3421 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3422 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3423 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3424 | { | |
3425 | if ((format == fmt_double) | 0) | |
3426 | SignalException(ReservedInstruction,instruction); | |
3427 | else | |
3428 | StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double)); | |
3429 | } | |
3430 | } | |
3431 | ||
3432 | ||
3433 | 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt | |
3434 | "cvt.l.%s<FMT> f<FD>, f<FS>" | |
3435 | *mipsIII: | |
3436 | *mipsIV: | |
3437 | // start-sanitize-r5900 | |
3438 | *r5900: | |
3439 | // end-sanitize-r5900 | |
3440 | *r3900: | |
3441 | // start-sanitize-tx19 | |
3442 | *tx19: | |
3443 | // end-sanitize-tx19 | |
3444 | { | |
3445 | unsigned32 instruction = instruction_0; | |
3446 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3447 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3448 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3449 | { | |
3450 | if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word))) | |
3451 | SignalException(ReservedInstruction,instruction); | |
3452 | else | |
3453 | StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long)); | |
3454 | } | |
3455 | } | |
3456 | ||
3457 | ||
3458 | // | |
3459 | // FIXME: Does not correctly differentiate between mips* | |
3460 | // | |
3461 | 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt | |
3462 | "cvt.s.%s<FMT> f<FD>, f<FS>" | |
3463 | *mipsI: | |
3464 | *mipsII: | |
3465 | *mipsIII: | |
3466 | *mipsIV: | |
3467 | // start-sanitize-r5900 | |
3468 | *r5900: | |
3469 | // end-sanitize-r5900 | |
3470 | *r3900: | |
3471 | // start-sanitize-tx19 | |
3472 | *tx19: | |
3473 | // end-sanitize-tx19 | |
3474 | { | |
3475 | unsigned32 instruction = instruction_0; | |
3476 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3477 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3478 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3479 | { | |
3480 | if ((format == fmt_single) | 0) | |
3481 | SignalException(ReservedInstruction,instruction); | |
3482 | else | |
3483 | StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single)); | |
3484 | } | |
3485 | } | |
3486 | ||
3487 | ||
3488 | 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt | |
3489 | "cvt.w.%s<FMT> f<FD>, f<FS>" | |
3490 | *mipsI: | |
3491 | *mipsII: | |
3492 | *mipsIII: | |
3493 | *mipsIV: | |
3494 | // start-sanitize-r5900 | |
3495 | *r5900: | |
3496 | // end-sanitize-r5900 | |
3497 | *r3900: | |
3498 | // start-sanitize-tx19 | |
3499 | *tx19: | |
3500 | // end-sanitize-tx19 | |
3501 | { | |
3502 | unsigned32 instruction = instruction_0; | |
3503 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3504 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3505 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3506 | { | |
3507 | if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word))) | |
3508 | SignalException(ReservedInstruction,instruction); | |
3509 | else | |
3510 | StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word)); | |
3511 | } | |
3512 | } | |
3513 | ||
3514 | ||
3515 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt | |
3516 | "div.%s<FMT> f<FD>, f<FS>, f<FT>" | |
3517 | *mipsI: | |
3518 | *mipsII: | |
3519 | *mipsIII: | |
3520 | *mipsIV: | |
3521 | // start-sanitize-r5900 | |
3522 | *r5900: | |
3523 | // end-sanitize-r5900 | |
3524 | *r3900: | |
3525 | // start-sanitize-tx19 | |
3526 | *tx19: | |
3527 | // end-sanitize-tx19 | |
3528 | { | |
3529 | unsigned32 instruction = instruction_0; | |
3530 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3531 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3532 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
3533 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3534 | { | |
3535 | if ((format != fmt_single) && (format != fmt_double)) | |
3536 | SignalException(ReservedInstruction,instruction); | |
3537 | else | |
3538 | StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format)); | |
3539 | } | |
3540 | } | |
3541 | ||
3542 | ||
3543 | // DMFC1 | |
3544 | // DMTC1 | |
3545 | 01000100,x,01,5.FT,vvvvv,00000000000:COP1S:64::DMxC1 | |
3546 | *mipsIII: | |
3547 | *mipsIV: | |
3548 | // start-sanitize-r5900 | |
3549 | *r5900: | |
3550 | // end-sanitize-r5900 | |
3551 | *r3900: | |
3552 | // start-sanitize-tx19 | |
3553 | *tx19: | |
3554 | // end-sanitize-tx19 | |
3555 | { | |
3556 | unsigned32 instruction = instruction_0; | |
3557 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3558 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
3559 | int to UNUSED = ((instruction >> 23) & 0x00000001); | |
3560 | { | |
3561 | if (to) { | |
3562 | if (SizeFGR() == 64) { | |
3563 | PENDING_FILL((fs + FGRIDX),GPR[ft]); | |
3564 | } else | |
3565 | if ((fs & 0x1) == 0) | |
3566 | { | |
3567 | PENDING_FILL(((fs + 1) + FGRIDX),VH4_8(GPR[ft])); | |
3568 | PENDING_FILL((fs + FGRIDX),VL4_8(GPR[ft])); | |
3569 | } | |
3570 | } else { | |
3571 | if (SizeFGR() == 64) { | |
3572 | PENDING_FILL(ft,FGR[fs]); | |
3573 | } else | |
3574 | if ((fs & 0x1) == 0) { | |
3575 | PENDING_FILL(ft,(SET64HI(FGR[fs+1]) | FGR[fs])); | |
3576 | } else { | |
3577 | PENDING_FILL(ft,SET64HI(0xDEADC0DE) | 0xBAD0BAD0); | |
3578 | } | |
3579 | } | |
3580 | } | |
3581 | } | |
3582 | ||
3583 | ||
3584 | 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt | |
3585 | "floor.l.%s<FMT> f<FD>, f<FS>" | |
3586 | *mipsIII: | |
3587 | *mipsIV: | |
3588 | // start-sanitize-r5900 | |
3589 | *r5900: | |
3590 | // end-sanitize-r5900 | |
3591 | *r3900: | |
3592 | // start-sanitize-tx19 | |
3593 | *tx19: | |
3594 | // end-sanitize-tx19 | |
3595 | { | |
3596 | unsigned32 instruction = instruction_0; | |
3597 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3598 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3599 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3600 | { | |
3601 | if ((format != fmt_single) && (format != fmt_double)) | |
3602 | SignalException(ReservedInstruction,instruction); | |
3603 | else | |
3604 | StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long)); | |
3605 | } | |
3606 | } | |
3607 | ||
3608 | ||
3609 | 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt | |
3610 | "floor.w.%s<FMT> f<FD>, f<FS>" | |
3611 | *mipsII: | |
3612 | *mipsIII: | |
3613 | *mipsIV: | |
3614 | // start-sanitize-r5900 | |
3615 | *r5900: | |
3616 | // end-sanitize-r5900 | |
3617 | *r3900: | |
3618 | // start-sanitize-tx19 | |
3619 | *tx19: | |
3620 | // end-sanitize-tx19 | |
3621 | { | |
3622 | unsigned32 instruction = instruction_0; | |
3623 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3624 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3625 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3626 | { | |
3627 | if ((format != fmt_single) && (format != fmt_double)) | |
3628 | SignalException(ReservedInstruction,instruction); | |
3629 | else | |
3630 | StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word)); | |
3631 | } | |
3632 | } | |
3633 | ||
3634 | ||
3635 | // LDC1 | |
3636 | 110101,5.BASE,5.FT,16.OFFSET:COP1:32::LDC1 | |
3637 | ||
3638 | ||
3639 | 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1 | |
3640 | "ldxc1 f<FD>, r<INDEX>(r<BASE>)" | |
3641 | *mipsIV: | |
3642 | // start-sanitize-r5900 | |
3643 | *r5900: | |
3644 | // end-sanitize-r5900 | |
3645 | { | |
3646 | unsigned32 instruction = instruction_0; | |
3647 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3648 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
3649 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
3650 | { | |
3651 | unsigned64 vaddr = ((unsigned64)op1 + op2); | |
3652 | unsigned64 paddr; | |
3653 | int uncached; | |
3654 | if ((vaddr & 7) != 0) | |
3655 | SignalException(AddressLoad); | |
3656 | else | |
3657 | { | |
3658 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
3659 | { | |
3660 | unsigned64 memval = 0; | |
3661 | unsigned64 memval1 = 0; | |
3662 | unsigned64 mask = 0x7; | |
3663 | unsigned int shift = 4; | |
3664 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
3665 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
3666 | unsigned int byte UNUSED; | |
3667 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); | |
3668 | COP_LD(1,destreg,memval);; | |
3669 | } | |
3670 | } | |
3671 | } | |
3672 | } | |
3673 | ||
3674 | ||
3675 | // LWC1 | |
3676 | 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1 | |
3677 | ||
3678 | ||
3679 | 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1 | |
3680 | "lwxc1 f<FD>, r<INDEX>(r<BASE>)" | |
3681 | *mipsIV: | |
3682 | // start-sanitize-r5900 | |
3683 | *r5900: | |
3684 | // end-sanitize-r5900 | |
3685 | { | |
3686 | unsigned32 instruction = instruction_0; | |
3687 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3688 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
3689 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
3690 | { | |
3691 | unsigned64 vaddr = ((unsigned64)op1 + op2); | |
3692 | unsigned64 paddr; | |
3693 | int uncached; | |
3694 | if ((vaddr & 3) != 0) | |
3695 | SignalException(AddressLoad); | |
3696 | else | |
3697 | { | |
3698 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
3699 | { | |
3700 | unsigned64 memval = 0; | |
3701 | unsigned64 memval1 = 0; | |
3702 | unsigned64 mask = 0x7; | |
3703 | unsigned int shift = 2; | |
3704 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
3705 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
3706 | unsigned int byte UNUSED; | |
3707 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
3708 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
3709 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
3710 | COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF)); | |
3711 | } | |
3712 | } | |
3713 | } | |
3714 | } | |
3715 | ||
3716 | ||
3717 | ||
3718 | // | |
3719 | // FIXME: Not correct for mips* | |
3720 | // | |
3721 | 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D | |
3722 | "madd.d f<FD>, f<FR>, f<FS>, f<FT>" | |
3723 | *mipsIV: | |
3724 | // start-sanitize-r5900 | |
3725 | *r5900: | |
3726 | // end-sanitize-r5900 | |
3727 | { | |
3728 | unsigned32 instruction = instruction_0; | |
3729 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3730 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3731 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
3732 | int fr UNUSED = ((instruction >> 21) & 0x0000001F); | |
3733 | { | |
3734 | StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double)); | |
3735 | } | |
3736 | } | |
3737 | ||
3738 | ||
3739 | 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S | |
3740 | "madd.s f<FD>, f<FR>, f<FS>, f<FT>" | |
3741 | *mipsIV: | |
3742 | // start-sanitize-r5900 | |
3743 | *r5900: | |
3744 | // end-sanitize-r5900 | |
3745 | { | |
3746 | unsigned32 instruction = instruction_0; | |
3747 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3748 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3749 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
3750 | int fr UNUSED = ((instruction >> 21) & 0x0000001F); | |
3751 | { | |
3752 | StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single)); | |
3753 | } | |
3754 | } | |
3755 | ||
3756 | ||
3757 | // MFC1 | |
3758 | 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1 | |
3759 | "mXc1 r<RT>, f<FS>" | |
3760 | *mipsI: | |
3761 | *mipsII: | |
3762 | *mipsIII: | |
3763 | *mipsIV: | |
3764 | // start-sanitize-r5900 | |
3765 | *r5900: | |
3766 | // end-sanitize-r5900 | |
3767 | *r3900: | |
3768 | // start-sanitize-tx19 | |
3769 | *tx19: | |
3770 | // end-sanitize-tx19 | |
3771 | { | |
3772 | unsigned32 instruction = instruction_0; | |
3773 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3774 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
3775 | int to UNUSED = ((instruction >> 23) & 0x00000001); | |
3776 | { | |
3777 | if (to) { | |
3778 | if (SizeFGR() == 64) { | |
3779 | PENDING_FILL((fs + FGRIDX),(SET64HI(0xDEADC0DE) | VL4_8(GPR[ft]))); | |
3780 | } else { | |
3781 | PENDING_FILL((fs + FGRIDX),VL4_8(GPR[ft])); | |
3782 | } | |
3783 | } else { | |
3784 | PENDING_FILL(ft,SIGNEXTEND(FGR[fs],32)); | |
3785 | } | |
3786 | } | |
3787 | } | |
3788 | ||
3789 | ||
3790 | 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt | |
3791 | "mov.%s<FMT> f<FD>, f<FS>" | |
3792 | *mipsI: | |
3793 | *mipsII: | |
3794 | *mipsIII: | |
3795 | *mipsIV: | |
3796 | // start-sanitize-r5900 | |
3797 | *r5900: | |
3798 | // end-sanitize-r5900 | |
3799 | *r3900: | |
3800 | // start-sanitize-tx19 | |
3801 | *tx19: | |
3802 | // end-sanitize-tx19 | |
3803 | { | |
3804 | unsigned32 instruction = instruction_0; | |
3805 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3806 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3807 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3808 | { | |
3809 | StoreFPR(destreg,format,ValueFPR(fs,format)); | |
3810 | } | |
3811 | } | |
3812 | ||
3813 | ||
3814 | // MOVF | |
3815 | 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf | |
3816 | "mov%s<TF> r<RD>, r<FS>, <CC>" | |
3817 | *mipsIV: | |
3818 | // start-sanitize-r5900 | |
3819 | *r5900: | |
3820 | // end-sanitize-r5900 | |
3821 | { | |
3822 | unsigned32 instruction = instruction_0; | |
3823 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
3824 | int boolean UNUSED = ((instruction >> 16) & 0x00000001); | |
3825 | int condition_code UNUSED = ((instruction >> 18) & 0x00000007); | |
3826 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
3827 | { | |
3828 | if (GETFCC(condition_code) == boolean) | |
3829 | GPR[destreg] = op1; | |
3830 | } | |
3831 | } | |
3832 | ||
3833 | ||
3834 | // MOVF.fmt | |
3835 | 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt | |
3836 | "mov%s<TF>.%s<FMT> | |
3837 | *mipsIV: | |
3838 | // start-sanitize-r5900 | |
3839 | *r5900: | |
3840 | // end-sanitize-r5900 | |
3841 | { | |
3842 | unsigned32 instruction = instruction_0; | |
3843 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3844 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3845 | int boolean UNUSED = ((instruction >> 16) & 0x00000001); | |
3846 | int condition_code UNUSED = ((instruction >> 18) & 0x00000007); | |
3847 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3848 | { | |
3849 | if (GETFCC(condition_code) == boolean) | |
3850 | StoreFPR(destreg,format,ValueFPR(fs,format)); | |
3851 | else | |
3852 | StoreFPR(destreg,format,ValueFPR(destreg,format)); | |
3853 | } | |
3854 | } | |
3855 | ||
3856 | ||
3857 | 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt | |
3858 | *mipsIV: | |
3859 | // start-sanitize-r5900 | |
3860 | *r5900: | |
3861 | // end-sanitize-r5900 | |
3862 | { | |
3863 | unsigned32 instruction = instruction_0; | |
3864 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3865 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3866 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
3867 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3868 | { | |
3869 | StoreFPR(destreg,format,ValueFPR(fs,format)); | |
3870 | } | |
3871 | } | |
3872 | ||
3873 | ||
3874 | // MOVT see MOVtf | |
3875 | ||
3876 | ||
3877 | // MOVT.fmt see MOVtf.fmt | |
3878 | ||
3879 | ||
3880 | ||
3881 | 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt | |
3882 | "movz.%s<FMT> f<FD>, f<FS>, r<RT>" | |
3883 | *mipsIV: | |
3884 | // start-sanitize-r5900 | |
3885 | *r5900: | |
3886 | // end-sanitize-r5900 | |
3887 | { | |
3888 | unsigned32 instruction = instruction_0; | |
3889 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3890 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3891 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
3892 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3893 | { | |
3894 | StoreFPR(destreg,format,ValueFPR(fs,format)); | |
3895 | } | |
3896 | } | |
3897 | ||
3898 | ||
3899 | // MSUB.fmt | |
3900 | 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D | |
3901 | "msub.d f<FD>, f<FR>, f<FS>, f<FT>" | |
3902 | *mipsIV: | |
3903 | // start-sanitize-r5900 | |
3904 | *r5900: | |
3905 | // end-sanitize-r5900 | |
3906 | { | |
3907 | unsigned32 instruction = instruction_0; | |
3908 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3909 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3910 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
3911 | int fr UNUSED = ((instruction >> 21) & 0x0000001F); | |
3912 | { | |
3913 | StoreFPR(destreg,fmt_double,(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double)); | |
3914 | } | |
3915 | } | |
3916 | ||
3917 | ||
3918 | // MSUB.fmt | |
3919 | 010011,bbbbb,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S | |
3920 | "msub.s f<FD>, f<FR>, f<FS>, f<FT>" | |
3921 | *mipsIV: | |
3922 | // start-sanitize-r5900 | |
3923 | *r5900: | |
3924 | // end-sanitize-r5900 | |
3925 | { | |
3926 | unsigned32 instruction = instruction_0; | |
3927 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3928 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3929 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
3930 | int fr UNUSED = ((instruction >> 21) & 0x0000001F); | |
3931 | { | |
3932 | StoreFPR(destreg,fmt_single,(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single)); | |
3933 | } | |
3934 | } | |
3935 | ||
3936 | ||
3937 | // MTC1 see MxC1 | |
3938 | ||
3939 | ||
3940 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt | |
3941 | "mul.%s<FMT> f<FD>, f<FS>, f<FT>" | |
3942 | *mipsI: | |
3943 | *mipsII: | |
3944 | *mipsIII: | |
3945 | *mipsIV: | |
3946 | // start-sanitize-r5900 | |
3947 | *r5900: | |
3948 | // end-sanitize-r5900 | |
3949 | *r3900: | |
3950 | // start-sanitize-tx19 | |
3951 | *tx19: | |
3952 | // end-sanitize-tx19 | |
3953 | { | |
3954 | unsigned32 instruction = instruction_0; | |
3955 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3956 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3957 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
3958 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3959 | { | |
3960 | if ((format != fmt_single) && (format != fmt_double)) | |
3961 | SignalException(ReservedInstruction,instruction); | |
3962 | else | |
3963 | StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format)); | |
3964 | } | |
3965 | } | |
3966 | ||
3967 | ||
3968 | 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt | |
3969 | "neg.%s<FMT> f<FD>, f<FS>" | |
3970 | *mipsI: | |
3971 | *mipsII: | |
3972 | *mipsIII: | |
3973 | *mipsIV: | |
3974 | // start-sanitize-r5900 | |
3975 | *r5900: | |
3976 | // end-sanitize-r5900 | |
3977 | *r3900: | |
3978 | // start-sanitize-tx19 | |
3979 | *tx19: | |
3980 | // end-sanitize-tx19 | |
3981 | { | |
3982 | unsigned32 instruction = instruction_0; | |
3983 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
3984 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
3985 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
3986 | { | |
3987 | if ((format != fmt_single) && (format != fmt_double)) | |
3988 | SignalException(ReservedInstruction,instruction); | |
3989 | else | |
3990 | StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format)); | |
3991 | } | |
3992 | } | |
3993 | ||
3994 | ||
3995 | // NMADD.fmt | |
3996 | 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D | |
3997 | "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>" | |
3998 | *mipsIV: | |
3999 | { | |
4000 | unsigned32 instruction = instruction_0; | |
4001 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
4002 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
4003 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
4004 | int fr UNUSED = ((instruction >> 21) & 0x0000001F); | |
4005 | { | |
4006 | StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double)); | |
4007 | } | |
4008 | } | |
4009 | ||
4010 | ||
4011 | // NMADD.fmt | |
4012 | 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S | |
4013 | "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>" | |
4014 | *mipsIV: | |
4015 | { | |
4016 | unsigned32 instruction = instruction_0; | |
4017 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
4018 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
4019 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
4020 | int fr UNUSED = ((instruction >> 21) & 0x0000001F); | |
4021 | { | |
4022 | StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single)); | |
4023 | } | |
4024 | } | |
4025 | ||
4026 | ||
4027 | // NMSUB.fmt | |
4028 | 010011,bbbbb,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D | |
4029 | "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>" | |
4030 | *mipsIV: | |
4031 | { | |
4032 | unsigned32 instruction = instruction_0; | |
4033 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
4034 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
4035 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
4036 | int fr UNUSED = ((instruction >> 21) & 0x0000001F); | |
4037 | { | |
4038 | StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double)); | |
4039 | } | |
4040 | } | |
4041 | ||
4042 | ||
4043 | // NMSUB.fmt | |
4044 | 010011,bbbbb,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S | |
4045 | "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>" | |
4046 | *mipsIV: | |
4047 | { | |
4048 | unsigned32 instruction = instruction_0; | |
4049 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
4050 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
4051 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
4052 | int fr UNUSED = ((instruction >> 21) & 0x0000001F); | |
4053 | { | |
4054 | StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single)); | |
4055 | } | |
4056 | } | |
4057 | ||
4058 | ||
4059 | 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX | |
49a6eed5 | 4060 | "prefx <HINT>, r<INDEX>(r<BASE>)" |
f2b30012 AC |
4061 | *mipsIV: |
4062 | { | |
4063 | unsigned32 instruction = instruction_0; | |
4064 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
4065 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
4066 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
4067 | { | |
4068 | unsigned64 vaddr = ((unsigned64)op1 + (unsigned64)op2); | |
4069 | unsigned64 paddr; | |
4070 | int uncached; | |
4071 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4072 | Prefetch(uncached,paddr,vaddr,isDATA,fs); | |
4073 | } | |
4074 | } | |
4075 | ||
4076 | 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt | |
4077 | *mipsIV: | |
4078 | "recip.%s<FMT> f<FD>, f<FS>" | |
4079 | { | |
4080 | unsigned32 instruction = instruction_0; | |
4081 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
4082 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
4083 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
4084 | { | |
4085 | if ((format != fmt_single) && (format != fmt_double)) | |
4086 | SignalException(ReservedInstruction,instruction); | |
4087 | else | |
4088 | StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format)); | |
4089 | } | |
4090 | } | |
4091 | ||
4092 | ||
4093 | 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt | |
49a6eed5 | 4094 | "round.l.%s<FMT> f<FD>, f<FS>" |
f2b30012 AC |
4095 | *mipsIII: |
4096 | *mipsIV: | |
4097 | // start-sanitize-r5900 | |
4098 | *r5900: | |
4099 | // end-sanitize-r5900 | |
4100 | *r3900: | |
4101 | // start-sanitize-tx19 | |
4102 | *tx19: | |
4103 | // end-sanitize-tx19 | |
4104 | { | |
4105 | unsigned32 instruction = instruction_0; | |
4106 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
4107 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
4108 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
4109 | { | |
4110 | if ((format != fmt_single) && (format != fmt_double)) | |
4111 | SignalException(ReservedInstruction,instruction); | |
4112 | else | |
4113 | StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long)); | |
4114 | } | |
4115 | } | |
4116 | ||
4117 | ||
4118 | 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt | |
49a6eed5 | 4119 | "round.w.%s<FMT> f<FD>, f<FS>" |
f2b30012 AC |
4120 | *mipsII: |
4121 | *mipsIII: | |
4122 | *mipsIV: | |
4123 | // start-sanitize-r5900 | |
4124 | *r5900: | |
4125 | // end-sanitize-r5900 | |
4126 | *r3900: | |
4127 | // start-sanitize-tx19 | |
4128 | *tx19: | |
4129 | // end-sanitize-tx19 | |
4130 | { | |
4131 | unsigned32 instruction = instruction_0; | |
4132 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
4133 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
4134 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
4135 | { | |
4136 | if ((format != fmt_single) && (format != fmt_double)) | |
4137 | SignalException(ReservedInstruction,instruction); | |
4138 | else | |
4139 | StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word)); | |
4140 | } | |
4141 | } | |
4142 | ||
4143 | ||
4144 | 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt | |
4145 | *mipsIV: | |
4146 | "rsqrt.%s<FMT> f<FD>, f<FS>" | |
4147 | { | |
4148 | unsigned32 instruction = instruction_0; | |
4149 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
4150 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
4151 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
4152 | { | |
4153 | if ((format != fmt_single) && (format != fmt_double)) | |
4154 | SignalException(ReservedInstruction,instruction); | |
4155 | else | |
4156 | StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format))); | |
4157 | } | |
4158 | } | |
4159 | ||
4160 | ||
4161 | // SDC1 | |
4162 | ||
4163 | ||
4164 | 010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1 | |
4165 | *mipsIV: | |
4166 | // start-sanitize-r5900 | |
4167 | *r5900: | |
4168 | // end-sanitize-r5900 | |
4169 | { | |
4170 | unsigned32 instruction = instruction_0; | |
4171 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
4172 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
4173 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
4174 | { | |
4175 | unsigned64 vaddr = ((unsigned64)op1 + op2); | |
4176 | unsigned64 paddr; | |
4177 | int uncached; | |
4178 | if ((vaddr & 7) != 0) | |
4179 | SignalException(AddressStore); | |
4180 | else | |
4181 | { | |
4182 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
4183 | { | |
4184 | unsigned64 memval = 0; | |
4185 | unsigned64 memval1 = 0; | |
4186 | memval = (unsigned64)COP_SD(1,fs); | |
4187 | { | |
4188 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
4189 | } | |
4190 | } | |
4191 | } | |
4192 | } | |
4193 | } | |
4194 | ||
4195 | ||
4196 | 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt | |
4197 | "sqrt.%s<FMT> f<FD>, f<FS>" | |
4198 | *mipsII: | |
4199 | *mipsIII: | |
4200 | *mipsIV: | |
4201 | // start-sanitize-r5900 | |
4202 | *r5900: | |
4203 | // end-sanitize-r5900 | |
4204 | *r3900: | |
4205 | // start-sanitize-tx19 | |
4206 | *tx19: | |
4207 | // end-sanitize-tx19 | |
4208 | { | |
4209 | unsigned32 instruction = instruction_0; | |
4210 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
4211 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
4212 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
4213 | { | |
4214 | if ((format != fmt_single) && (format != fmt_double)) | |
4215 | SignalException(ReservedInstruction,instruction); | |
4216 | else | |
4217 | StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format))); | |
4218 | } | |
4219 | } | |
4220 | ||
4221 | ||
4222 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt | |
4223 | "sub.%s<FMT> f<FD>, f<FS>, f<FT>" | |
4224 | *mipsI: | |
4225 | *mipsII: | |
4226 | *mipsIII: | |
4227 | *mipsIV: | |
4228 | // start-sanitize-r5900 | |
4229 | *r5900: | |
4230 | // end-sanitize-r5900 | |
4231 | *r3900: | |
4232 | // start-sanitize-tx19 | |
4233 | *tx19: | |
4234 | // end-sanitize-tx19 | |
4235 | { | |
4236 | unsigned32 instruction = instruction_0; | |
4237 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
4238 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
4239 | int ft UNUSED = ((instruction >> 16) & 0x0000001F); | |
4240 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
4241 | { | |
4242 | if ((format != fmt_single) && (format != fmt_double)) | |
4243 | SignalException(ReservedInstruction,instruction); | |
4244 | else | |
4245 | StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format)); | |
4246 | } | |
4247 | } | |
4248 | ||
4249 | ||
4250 | // SWC1 | |
4251 | ||
4252 | ||
4253 | 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1 | |
4254 | "swxc1 f<FT>, r<OFFSET>(r<BASE>)" | |
4255 | *mipsIV: | |
4256 | // start-sanitize-r5900 | |
4257 | *r5900: | |
4258 | // end-sanitize-r5900 | |
4259 | { | |
4260 | unsigned32 instruction = instruction_0; | |
4261 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
4262 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
4263 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
4264 | { | |
4265 | unsigned64 vaddr = ((unsigned64)op1 + op2); | |
4266 | unsigned64 paddr; | |
4267 | int uncached; | |
4268 | if ((vaddr & 3) != 0) | |
4269 | SignalException(AddressStore); | |
4270 | else | |
4271 | { | |
4272 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
4273 | { | |
4274 | unsigned64 memval = 0; | |
4275 | unsigned64 memval1 = 0; | |
4276 | unsigned64 mask = 0x7; | |
4277 | unsigned int byte; | |
4278 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
4279 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
4280 | memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte)); | |
4281 | { | |
4282 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
4283 | } | |
4284 | } | |
4285 | } | |
4286 | } | |
4287 | } | |
4288 | ||
4289 | ||
4290 | 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt | |
4291 | "trunc.l.%s<FMT> f<FD>, f<FS>" | |
4292 | *mipsIII: | |
4293 | *mipsIV: | |
4294 | // start-sanitize-r5900 | |
4295 | *r5900: | |
4296 | // end-sanitize-r5900 | |
4297 | *r3900: | |
4298 | // start-sanitize-tx19 | |
4299 | *tx19: | |
4300 | // end-sanitize-tx19 | |
4301 | { | |
4302 | unsigned32 instruction = instruction_0; | |
4303 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
4304 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
4305 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
4306 | { | |
4307 | if ((format != fmt_single) && (format != fmt_double)) | |
4308 | SignalException(ReservedInstruction,instruction); | |
4309 | else | |
4310 | StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long)); | |
4311 | } | |
4312 | } | |
4313 | ||
4314 | ||
4315 | 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W | |
4316 | "trunc.w.%s<FMT> f<FD>, f<FS>" | |
4317 | *mipsII: | |
4318 | *mipsIII: | |
4319 | *mipsIV: | |
4320 | // start-sanitize-r5900 | |
4321 | *r5900: | |
4322 | // end-sanitize-r5900 | |
4323 | *r3900: | |
4324 | // start-sanitize-tx19 | |
4325 | *tx19: | |
4326 | // end-sanitize-tx19 | |
4327 | { | |
4328 | unsigned32 instruction = instruction_0; | |
4329 | int destreg UNUSED = ((instruction >> 6) & 0x0000001F); | |
4330 | int fs UNUSED = ((instruction >> 11) & 0x0000001F); | |
4331 | int format UNUSED = ((instruction >> 21) & 0x00000007); | |
4332 | { | |
4333 | if ((format != fmt_single) && (format != fmt_double)) | |
4334 | SignalException(ReservedInstruction,instruction); | |
4335 | else | |
4336 | StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word)); | |
4337 | } | |
4338 | } | |
4339 | ||
4340 | \f | |
4341 | // | |
4342 | // MIPS Architecture: | |
4343 | // | |
4344 | // System Control Instruction Set (COP0) | |
4345 | // | |
4346 | ||
4347 | ||
4348 | 010000,01000,00000,16.OFFSET:COP0:32::BC0F | |
4349 | "bc0f <OFFSET>" | |
4350 | *mipsI: | |
4351 | *mipsII: | |
4352 | *mipsIII: | |
4353 | *mipsIV: | |
4354 | // start-sanitize-r5900 | |
4355 | *r5900: | |
4356 | // end-sanitize-r5900 | |
4357 | ||
4358 | ||
4359 | 010000,01000,00010,16.OFFSET:COP0:32::BC0FL | |
4360 | "bc0fl <OFFSET>" | |
4361 | *mipsI: | |
4362 | *mipsII: | |
4363 | *mipsIII: | |
4364 | *mipsIV: | |
4365 | // start-sanitize-r5900 | |
4366 | *r5900: | |
4367 | // end-sanitize-r5900 | |
4368 | ||
4369 | ||
4370 | 010000,01000,00001,16.OFFSET:COP0:32::BC0T | |
4371 | "bc0t <OFFSET>" | |
4372 | *mipsI: | |
4373 | *mipsII: | |
4374 | *mipsIII: | |
4375 | *mipsIV: | |
4376 | // start-sanitize-r5900 | |
4377 | *r5900: | |
4378 | // end-sanitize-r5900 | |
4379 | ||
4380 | ||
4381 | ||
49a6eed5 | 4382 | 010000,01000,00011,16.OFFSET:COP0:32::BC0TL |
f2b30012 AC |
4383 | "bc0tl <OFFSET>" |
4384 | *mipsI: | |
4385 | *mipsII: | |
4386 | *mipsIII: | |
4387 | *mipsIV: | |
4388 | // start-sanitize-r5900 | |
4389 | *r5900: | |
4390 | // end-sanitize-r5900 | |
4391 | ||
4392 | ||
4393 | 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE | |
4394 | *mipsIII: | |
4395 | *mipsIV: | |
4396 | // start-sanitize-r5900 | |
4397 | *r5900: | |
4398 | // end-sanitize-r5900 | |
4399 | *r3900: | |
4400 | // start-sanitize-tx19 | |
4401 | *tx19: | |
4402 | // end-sanitize-tx19 | |
4403 | { | |
4404 | unsigned32 instruction = instruction_0; | |
4405 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
4406 | int hint UNUSED = ((instruction >> 16) & 0x0000001F); | |
4407 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
4408 | { | |
4409 | unsigned64 vaddr = (op1 + offset); | |
4410 | unsigned64 paddr; | |
4411 | int uncached; | |
4412 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4413 | CacheOp(hint,vaddr,paddr,instruction); | |
4414 | } | |
4415 | } | |
4416 | ||
4417 | ||
4418 | 010000,10000,000000000000000,111001:COP0:32::DI | |
4419 | "di" | |
4420 | *mipsI: | |
4421 | *mipsII: | |
4422 | *mipsIII: | |
4423 | *mipsIV: | |
4424 | // start-sanitize-r5900 | |
4425 | *r5900: | |
4426 | // end-sanitize-r5900 | |
4427 | ||
4428 | ||
4429 | 010000,10000,000000000000000,111000:COP0:32::EI | |
4430 | "ei" | |
4431 | *mipsI: | |
4432 | *mipsII: | |
4433 | *mipsIII: | |
4434 | *mipsIV: | |
4435 | // start-sanitize-r5900 | |
4436 | *r5900: | |
4437 | // end-sanitize-r5900 | |
4438 | ||
4439 | ||
4440 | 010000,10000,000000000000000,011000:COP0:32::ERET | |
4441 | "eret" | |
4442 | *mipsIII: | |
4443 | *mipsIV: | |
4444 | // start-sanitize-r5900 | |
4445 | *r5900: | |
4446 | // end-sanitize-r5900 | |
4447 | ||
4448 | ||
49a6eed5 AC |
4449 | 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0 |
4450 | "mfc0 r<RT>, r<RD> # <REGX>" | |
f2b30012 AC |
4451 | *mipsI: |
4452 | *mipsII: | |
4453 | *mipsIII: | |
4454 | *mipsIV: | |
4455 | // start-sanitize-r5900 | |
4456 | *r5900: | |
4457 | // end-sanitize-r5900 | |
4458 | ||
4459 | ||
49a6eed5 AC |
4460 | 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0 |
4461 | "mtc0 r<RT>, r<RD> # <REGX>" | |
f2b30012 AC |
4462 | *mipsI: |
4463 | *mipsII: | |
4464 | *mipsIII: | |
4465 | *mipsIV: | |
4466 | // start-sanitize-r5900 | |
4467 | *r5900: | |
4468 | // end-sanitize-r5900 | |
4469 | ||
4470 | ||
4471 | 010000,10000,000000000000000,001000:COP0:32::TLBP | |
4472 | "tlbp" | |
4473 | *mipsI: | |
4474 | *mipsII: | |
4475 | *mipsIII: | |
4476 | *mipsIV: | |
4477 | // start-sanitize-r5900 | |
4478 | *r5900: | |
4479 | // end-sanitize-r5900 | |
4480 | ||
4481 | ||
4482 | 010000,10000,000000000000000,000001:COP0:32::TLBR | |
4483 | "tlbr" | |
4484 | *mipsI: | |
4485 | *mipsII: | |
4486 | *mipsIII: | |
4487 | *mipsIV: | |
4488 | // start-sanitize-r5900 | |
4489 | *r5900: | |
4490 | // end-sanitize-r5900 | |
4491 | ||
4492 | ||
4493 | 010000,10000,000000000000000,000010:COP0:32::TLBWI | |
4494 | "tlbwi" | |
4495 | *mipsI: | |
4496 | *mipsII: | |
4497 | *mipsIII: | |
4498 | *mipsIV: | |
4499 | // start-sanitize-r5900 | |
4500 | *r5900: | |
4501 | // end-sanitize-r5900 | |
4502 | ||
4503 | ||
4504 | 010000,10000,000000000000000,000110:COP0:32::TLBWR | |
4505 | "tlbwr" | |
4506 | *mipsI: | |
4507 | *mipsII: | |
4508 | *mipsIII: | |
4509 | *mipsIV: | |
4510 | // start-sanitize-r5900 | |
4511 | *r5900: | |
4512 | // end-sanitize-r5900 | |
4513 | ||
4514 | \f | |
4515 | // | |
4516 | // MIPS Architecture: | |
4517 | // | |
4518 | // CPU Instruction Set (mips16) | |
4519 | // | |
4520 | ||
4521 | // The instructions in this section are ordered according | |
4522 | // to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf. | |
4523 | ||
4524 | ||
4525 | // Load and Store Instructions | |
4526 | ||
4527 | ||
4528 | 10000,xxx,ddd,55555:RRI:16::LB | |
4529 | *mips16: | |
4530 | { | |
4531 | unsigned32 instruction = instruction_0; | |
4532 | t_reg op1 = (instruction >> 8) & 0x7; | |
4533 | int destreg = (instruction >> 5) & 0x7; | |
4534 | int offset = (instruction >> 0) & 0x1f; | |
4535 | if (op1 < 2) | |
4536 | op1 += 16; | |
4537 | op1 = GPR[op1]; | |
4538 | if (destreg < 2) | |
4539 | destreg += 16; | |
4540 | if (have_extendval) | |
4541 | { | |
4542 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
4543 | if (offset >= 0x8000) | |
4544 | offset -= 0x10000; | |
4545 | have_extendval = 0; | |
4546 | } | |
4547 | else | |
4548 | { | |
4549 | } | |
4550 | if (have_extendval) | |
4551 | SignalException (ReservedInstruction, instruction); | |
4552 | { | |
4553 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
4554 | unsigned64 paddr; | |
4555 | int uncached; | |
4556 | { | |
4557 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4558 | { | |
4559 | unsigned64 memval = 0; | |
4560 | unsigned64 memval1 = 0; | |
4561 | unsigned64 mask = 0x7; | |
4562 | unsigned int shift = 0; | |
4563 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
4564 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
4565 | unsigned int byte UNUSED; | |
4566 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
4567 | LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); | |
4568 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
4569 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8)); | |
4570 | } | |
4571 | } | |
4572 | } | |
4573 | } | |
4574 | ||
4575 | ||
4576 | 10100,xxx,ddd,55555:RRI:16::LBU | |
4577 | *mips16: | |
4578 | { | |
4579 | unsigned32 instruction = instruction_0; | |
4580 | t_reg op1 = (instruction >> 8) & 0x7; | |
4581 | int destreg = (instruction >> 5) & 0x7; | |
4582 | int offset = (instruction >> 0) & 0x1f; | |
4583 | if (op1 < 2) | |
4584 | op1 += 16; | |
4585 | op1 = GPR[op1]; | |
4586 | if (destreg < 2) | |
4587 | destreg += 16; | |
4588 | if (have_extendval) | |
4589 | { | |
4590 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
4591 | if (offset >= 0x8000) | |
4592 | offset -= 0x10000; | |
4593 | have_extendval = 0; | |
4594 | } | |
4595 | else | |
4596 | { | |
4597 | } | |
4598 | if (have_extendval) | |
4599 | SignalException (ReservedInstruction, instruction); | |
4600 | { | |
4601 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
4602 | unsigned64 paddr; | |
4603 | int uncached; | |
4604 | { | |
4605 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4606 | { | |
4607 | unsigned64 memval = 0; | |
4608 | unsigned64 memval1 = 0; | |
4609 | unsigned64 mask = 0x7; | |
4610 | unsigned int shift = 0; | |
4611 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
4612 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
4613 | unsigned int byte UNUSED; | |
4614 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
4615 | LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); | |
4616 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
4617 | GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF)); | |
4618 | } | |
4619 | } | |
4620 | } | |
4621 | } | |
4622 | ||
4623 | ||
4624 | 10001,xxx,ddd,HHHHH:RRI:16::LH | |
4625 | *mips16: | |
4626 | { | |
4627 | unsigned32 instruction = instruction_0; | |
4628 | t_reg op1 = (instruction >> 8) & 0x7; | |
4629 | int destreg = (instruction >> 5) & 0x7; | |
4630 | int offset = (instruction >> 0) & 0x1f; | |
4631 | if (op1 < 2) | |
4632 | op1 += 16; | |
4633 | op1 = GPR[op1]; | |
4634 | if (destreg < 2) | |
4635 | destreg += 16; | |
4636 | if (have_extendval) | |
4637 | { | |
4638 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
4639 | if (offset >= 0x8000) | |
4640 | offset -= 0x10000; | |
4641 | have_extendval = 0; | |
4642 | } | |
4643 | else | |
4644 | { | |
4645 | offset <<= 1; | |
4646 | } | |
4647 | if (have_extendval) | |
4648 | SignalException (ReservedInstruction, instruction); | |
4649 | { | |
4650 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
4651 | unsigned64 paddr; | |
4652 | int uncached; | |
4653 | if ((vaddr & 1) != 0) | |
4654 | SignalException(AddressLoad); | |
4655 | else | |
4656 | { | |
4657 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4658 | { | |
4659 | unsigned64 memval = 0; | |
4660 | unsigned64 memval1 = 0; | |
4661 | unsigned64 mask = 0x7; | |
4662 | unsigned int shift = 1; | |
4663 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
4664 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
4665 | unsigned int byte UNUSED; | |
4666 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
4667 | LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); | |
4668 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
4669 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16)); | |
4670 | } | |
4671 | } | |
4672 | } | |
4673 | } | |
4674 | ||
4675 | ||
4676 | 10101,xxx,ddd,HHHHH:RRI:16::LHU | |
4677 | *mips16: | |
4678 | { | |
4679 | unsigned32 instruction = instruction_0; | |
4680 | t_reg op1 = (instruction >> 8) & 0x7; | |
4681 | int destreg = (instruction >> 5) & 0x7; | |
4682 | int offset = (instruction >> 0) & 0x1f; | |
4683 | if (op1 < 2) | |
4684 | op1 += 16; | |
4685 | op1 = GPR[op1]; | |
4686 | if (destreg < 2) | |
4687 | destreg += 16; | |
4688 | if (have_extendval) | |
4689 | { | |
4690 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
4691 | if (offset >= 0x8000) | |
4692 | offset -= 0x10000; | |
4693 | have_extendval = 0; | |
4694 | } | |
4695 | else | |
4696 | { | |
4697 | offset <<= 1; | |
4698 | } | |
4699 | if (have_extendval) | |
4700 | SignalException (ReservedInstruction, instruction); | |
4701 | { | |
4702 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
4703 | unsigned64 paddr; | |
4704 | int uncached; | |
4705 | if ((vaddr & 1) != 0) | |
4706 | SignalException(AddressLoad); | |
4707 | else | |
4708 | { | |
4709 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4710 | { | |
4711 | unsigned64 memval = 0; | |
4712 | unsigned64 memval1 = 0; | |
4713 | unsigned64 mask = 0x7; | |
4714 | unsigned int shift = 1; | |
4715 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
4716 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
4717 | unsigned int byte UNUSED; | |
4718 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
4719 | LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); | |
4720 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
4721 | GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF)); | |
4722 | } | |
4723 | } | |
4724 | } | |
4725 | } | |
4726 | ||
4727 | ||
4728 | 10011,xxx,ddd,WWWWW:RRI:16::LW | |
4729 | *mips16: | |
4730 | { | |
4731 | unsigned32 instruction = instruction_0; | |
4732 | t_reg op1 = (instruction >> 8) & 0x7; | |
4733 | int destreg = (instruction >> 5) & 0x7; | |
4734 | int offset = (instruction >> 0) & 0x1f; | |
4735 | if (op1 < 2) | |
4736 | op1 += 16; | |
4737 | op1 = GPR[op1]; | |
4738 | if (destreg < 2) | |
4739 | destreg += 16; | |
4740 | if (have_extendval) | |
4741 | { | |
4742 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
4743 | if (offset >= 0x8000) | |
4744 | offset -= 0x10000; | |
4745 | have_extendval = 0; | |
4746 | } | |
4747 | else | |
4748 | { | |
4749 | offset <<= 2; | |
4750 | } | |
4751 | if (have_extendval) | |
4752 | SignalException (ReservedInstruction, instruction); | |
4753 | { | |
4754 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
4755 | unsigned64 paddr; | |
4756 | int uncached; | |
4757 | if ((vaddr & 3) != 0) | |
4758 | SignalException(AddressLoad); | |
4759 | else | |
4760 | { | |
4761 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4762 | { | |
4763 | unsigned64 memval = 0; | |
4764 | unsigned64 memval1 = 0; | |
4765 | unsigned64 mask = 0x7; | |
4766 | unsigned int shift = 2; | |
4767 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
4768 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
4769 | unsigned int byte UNUSED; | |
4770 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
4771 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
4772 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
4773 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); | |
4774 | } | |
4775 | } | |
4776 | } | |
4777 | } | |
4778 | ||
4779 | ||
4780 | 10110,ddd,VVVVVVVV,P:RI:16::LWPC | |
4781 | *mips16: | |
4782 | { | |
4783 | unsigned32 instruction = instruction_0; | |
4784 | int destreg = (instruction >> 8) & 0x7; | |
4785 | int offset = (instruction >> 0) & 0xff; | |
4786 | t_reg op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3; | |
4787 | if (destreg < 2) | |
4788 | destreg += 16; | |
4789 | if (have_extendval) | |
4790 | { | |
4791 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
4792 | if (offset >= 0x8000) | |
4793 | offset -= 0x10000; | |
4794 | have_extendval = 0; | |
4795 | } | |
4796 | else | |
4797 | { | |
4798 | offset <<= 2; | |
4799 | } | |
4800 | if (have_extendval) | |
4801 | SignalException (ReservedInstruction, instruction); | |
4802 | { | |
4803 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
4804 | unsigned64 paddr; | |
4805 | int uncached; | |
4806 | if ((vaddr & 3) != 0) | |
4807 | SignalException(AddressLoad); | |
4808 | else | |
4809 | { | |
4810 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4811 | { | |
4812 | unsigned64 memval = 0; | |
4813 | unsigned64 memval1 = 0; | |
4814 | unsigned64 mask = 0x7; | |
4815 | unsigned int shift = 2; | |
4816 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
4817 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
4818 | unsigned int byte UNUSED; | |
4819 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
4820 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
4821 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
4822 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); | |
4823 | } | |
4824 | } | |
4825 | } | |
4826 | } | |
4827 | ||
4828 | ||
4829 | 10010,ddd,VVVVVVVV,s:RI:16::LWSP | |
4830 | *mips16: | |
4831 | { | |
4832 | unsigned32 instruction = instruction_0; | |
4833 | int destreg = (instruction >> 8) & 0x7; | |
4834 | int offset = (instruction >> 0) & 0xff; | |
4835 | t_reg op1 = 29; | |
4836 | if (destreg < 2) | |
4837 | destreg += 16; | |
4838 | if (have_extendval) | |
4839 | { | |
4840 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
4841 | if (offset >= 0x8000) | |
4842 | offset -= 0x10000; | |
4843 | have_extendval = 0; | |
4844 | } | |
4845 | else | |
4846 | { | |
4847 | offset <<= 2; | |
4848 | } | |
4849 | op1 = GPR[op1]; | |
4850 | if (have_extendval) | |
4851 | SignalException (ReservedInstruction, instruction); | |
4852 | { | |
4853 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
4854 | unsigned64 paddr; | |
4855 | int uncached; | |
4856 | if ((vaddr & 3) != 0) | |
4857 | SignalException(AddressLoad); | |
4858 | else | |
4859 | { | |
4860 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4861 | { | |
4862 | unsigned64 memval = 0; | |
4863 | unsigned64 memval1 = 0; | |
4864 | unsigned64 mask = 0x7; | |
4865 | unsigned int shift = 2; | |
4866 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
4867 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
4868 | unsigned int byte UNUSED; | |
4869 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
4870 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
4871 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
4872 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); | |
4873 | } | |
4874 | } | |
4875 | } | |
4876 | } | |
4877 | ||
4878 | ||
4879 | 10111,xxx,ddd,WWWWW:RRI:16::LWU | |
4880 | *mips16: | |
4881 | { | |
4882 | unsigned32 instruction = instruction_0; | |
4883 | t_reg op1 = (instruction >> 8) & 0x7; | |
4884 | int destreg = (instruction >> 5) & 0x7; | |
4885 | int offset = (instruction >> 0) & 0x1f; | |
4886 | if (op1 < 2) | |
4887 | op1 += 16; | |
4888 | op1 = GPR[op1]; | |
4889 | if (destreg < 2) | |
4890 | destreg += 16; | |
4891 | if (have_extendval) | |
4892 | { | |
4893 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
4894 | if (offset >= 0x8000) | |
4895 | offset -= 0x10000; | |
4896 | have_extendval = 0; | |
4897 | } | |
4898 | else | |
4899 | { | |
4900 | offset <<= 2; | |
4901 | } | |
4902 | if (have_extendval) | |
4903 | SignalException (ReservedInstruction, instruction); | |
4904 | { | |
4905 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
4906 | unsigned64 paddr; | |
4907 | int uncached; | |
4908 | if ((vaddr & 3) != 0) | |
4909 | SignalException(AddressLoad); | |
4910 | else | |
4911 | { | |
4912 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4913 | { | |
4914 | unsigned64 memval = 0; | |
4915 | unsigned64 memval1 = 0; | |
4916 | unsigned64 mask = 0x7; | |
4917 | unsigned int shift = 2; | |
4918 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
4919 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
4920 | unsigned int byte UNUSED; | |
4921 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
4922 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
4923 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
4924 | GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF)); | |
4925 | } | |
4926 | } | |
4927 | } | |
4928 | } | |
4929 | ||
4930 | ||
4931 | 00111,xxx,ddd,DDDDD:RRI:16::LD | |
4932 | *mips16: | |
4933 | { | |
4934 | unsigned32 instruction = instruction_0; | |
4935 | t_reg op1 = (instruction >> 8) & 0x7; | |
4936 | int destreg = (instruction >> 5) & 0x7; | |
4937 | int offset = (instruction >> 0) & 0x1f; | |
4938 | if (op1 < 2) | |
4939 | op1 += 16; | |
4940 | op1 = GPR[op1]; | |
4941 | if (destreg < 2) | |
4942 | destreg += 16; | |
4943 | if (have_extendval) | |
4944 | { | |
4945 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
4946 | if (offset >= 0x8000) | |
4947 | offset -= 0x10000; | |
4948 | have_extendval = 0; | |
4949 | } | |
4950 | else | |
4951 | { | |
4952 | offset <<= 3; | |
4953 | } | |
4954 | if (have_extendval) | |
4955 | SignalException (ReservedInstruction, instruction); | |
4956 | { | |
4957 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
4958 | unsigned64 paddr; | |
4959 | int uncached; | |
4960 | if ((vaddr & 7) != 0) | |
4961 | SignalException(AddressLoad); | |
4962 | else | |
4963 | { | |
4964 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4965 | { | |
4966 | unsigned64 memval = 0; | |
4967 | unsigned64 memval1 = 0; | |
4968 | unsigned64 mask = 0x7; | |
4969 | unsigned int shift = 4; | |
4970 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
4971 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
4972 | unsigned int byte UNUSED; | |
4973 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); | |
4974 | GPR[destreg] = memval; | |
4975 | } | |
4976 | } | |
4977 | } | |
4978 | } | |
4979 | ||
4980 | ||
4981 | 11111100,ddd,5.RD,P:RI64:16::LDPC | |
4982 | *mips16: | |
4983 | { | |
4984 | unsigned32 instruction = instruction_0; | |
4985 | int destreg = (instruction >> 5) & 0x7; | |
4986 | int offset = (instruction >> 0) & 0x1f; | |
4987 | t_reg op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x7; | |
4988 | if (destreg < 2) | |
4989 | destreg += 16; | |
4990 | if (have_extendval) | |
4991 | { | |
4992 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
4993 | if (offset >= 0x8000) | |
4994 | offset -= 0x10000; | |
4995 | have_extendval = 0; | |
4996 | } | |
4997 | else | |
4998 | { | |
4999 | offset <<= 3; | |
5000 | } | |
5001 | if (have_extendval) | |
5002 | SignalException (ReservedInstruction, instruction); | |
5003 | { | |
5004 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
5005 | unsigned64 paddr; | |
5006 | int uncached; | |
5007 | if ((vaddr & 7) != 0) | |
5008 | SignalException(AddressLoad); | |
5009 | else | |
5010 | { | |
5011 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
5012 | { | |
5013 | unsigned64 memval = 0; | |
5014 | unsigned64 memval1 = 0; | |
5015 | unsigned64 mask = 0x7; | |
5016 | unsigned int shift = 4; | |
5017 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
5018 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
5019 | unsigned int byte UNUSED; | |
5020 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); | |
5021 | GPR[destreg] = memval; | |
5022 | } | |
5023 | } | |
5024 | } | |
5025 | } | |
5026 | ||
5027 | ||
5028 | 11111000,ddd,5.RD,s:RI64:16::LDSP | |
5029 | *mips16: | |
5030 | { | |
5031 | unsigned32 instruction = instruction_0; | |
5032 | int destreg = (instruction >> 5) & 0x7; | |
5033 | int offset = (instruction >> 0) & 0x1f; | |
5034 | t_reg op1 = 29; | |
5035 | if (destreg < 2) | |
5036 | destreg += 16; | |
5037 | if (have_extendval) | |
5038 | { | |
5039 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5040 | if (offset >= 0x8000) | |
5041 | offset -= 0x10000; | |
5042 | have_extendval = 0; | |
5043 | } | |
5044 | else | |
5045 | { | |
5046 | offset <<= 3; | |
5047 | } | |
5048 | op1 = GPR[op1]; | |
5049 | if (have_extendval) | |
5050 | SignalException (ReservedInstruction, instruction); | |
5051 | { | |
5052 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
5053 | unsigned64 paddr; | |
5054 | int uncached; | |
5055 | if ((vaddr & 7) != 0) | |
5056 | SignalException(AddressLoad); | |
5057 | else | |
5058 | { | |
5059 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
5060 | { | |
5061 | unsigned64 memval = 0; | |
5062 | unsigned64 memval1 = 0; | |
5063 | unsigned64 mask = 0x7; | |
5064 | unsigned int shift = 4; | |
5065 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
5066 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
5067 | unsigned int byte UNUSED; | |
5068 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); | |
5069 | GPR[destreg] = memval; | |
5070 | } | |
5071 | } | |
5072 | } | |
5073 | } | |
5074 | ||
5075 | ||
5076 | 11000,xxx,yyy,55555:RRI:16::SB | |
5077 | *mips16: | |
5078 | { | |
5079 | unsigned32 instruction = instruction_0; | |
5080 | t_reg op1 = (instruction >> 8) & 0x7; | |
5081 | t_reg op2 = (instruction >> 5) & 0x7; | |
5082 | int offset = (instruction >> 0) & 0x1f; | |
5083 | if (op1 < 2) | |
5084 | op1 += 16; | |
5085 | op1 = GPR[op1]; | |
5086 | if (op2 < 2) | |
5087 | op2 += 16; | |
5088 | op2 = GPR[op2]; | |
5089 | if (have_extendval) | |
5090 | { | |
5091 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5092 | if (offset >= 0x8000) | |
5093 | offset -= 0x10000; | |
5094 | have_extendval = 0; | |
5095 | } | |
5096 | else | |
5097 | { | |
5098 | } | |
5099 | if (have_extendval) | |
5100 | SignalException (ReservedInstruction, instruction); | |
5101 | { | |
5102 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
5103 | unsigned64 paddr; | |
5104 | int uncached; | |
5105 | { | |
5106 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
5107 | { | |
5108 | unsigned64 memval = 0; | |
5109 | unsigned64 memval1 = 0; | |
5110 | unsigned64 mask = 0x7; | |
5111 | unsigned int shift = 0; | |
5112 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
5113 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
5114 | unsigned int byte; | |
5115 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
5116 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
5117 | memval = ((unsigned64) op2 << (8 * byte)); | |
5118 | { | |
5119 | StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL); | |
5120 | } | |
5121 | } | |
5122 | } | |
5123 | } | |
5124 | } | |
5125 | ||
5126 | ||
5127 | 11001,xxx,yyy,HHHHH:RRI:16::SH | |
5128 | *mips16: | |
5129 | { | |
5130 | unsigned32 instruction = instruction_0; | |
5131 | t_reg op1 = (instruction >> 8) & 0x7; | |
5132 | t_reg op2 = (instruction >> 5) & 0x7; | |
5133 | int offset = (instruction >> 0) & 0x1f; | |
5134 | if (op1 < 2) | |
5135 | op1 += 16; | |
5136 | op1 = GPR[op1]; | |
5137 | if (op2 < 2) | |
5138 | op2 += 16; | |
5139 | op2 = GPR[op2]; | |
5140 | if (have_extendval) | |
5141 | { | |
5142 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5143 | if (offset >= 0x8000) | |
5144 | offset -= 0x10000; | |
5145 | have_extendval = 0; | |
5146 | } | |
5147 | else | |
5148 | { | |
5149 | offset <<= 1; | |
5150 | } | |
5151 | if (have_extendval) | |
5152 | SignalException (ReservedInstruction, instruction); | |
5153 | { | |
5154 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
5155 | unsigned64 paddr; | |
5156 | int uncached; | |
5157 | if ((vaddr & 1) != 0) | |
5158 | SignalException(AddressStore); | |
5159 | else | |
5160 | { | |
5161 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
5162 | { | |
5163 | unsigned64 memval = 0; | |
5164 | unsigned64 memval1 = 0; | |
5165 | unsigned64 mask = 0x7; | |
5166 | unsigned int shift = 1; | |
5167 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
5168 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
5169 | unsigned int byte; | |
5170 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
5171 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
5172 | memval = ((unsigned64) op2 << (8 * byte)); | |
5173 | { | |
5174 | StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL); | |
5175 | } | |
5176 | } | |
5177 | } | |
5178 | } | |
5179 | } | |
5180 | ||
5181 | ||
5182 | 11011,xxx,yyy,WWWWW:RRI:16::SW | |
5183 | *mips16: | |
5184 | { | |
5185 | unsigned32 instruction = instruction_0; | |
5186 | t_reg op1 = (instruction >> 8) & 0x7; | |
5187 | t_reg op2 = (instruction >> 5) & 0x7; | |
5188 | int offset = (instruction >> 0) & 0x1f; | |
5189 | if (op1 < 2) | |
5190 | op1 += 16; | |
5191 | op1 = GPR[op1]; | |
5192 | if (op2 < 2) | |
5193 | op2 += 16; | |
5194 | op2 = GPR[op2]; | |
5195 | if (have_extendval) | |
5196 | { | |
5197 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5198 | if (offset >= 0x8000) | |
5199 | offset -= 0x10000; | |
5200 | have_extendval = 0; | |
5201 | } | |
5202 | else | |
5203 | { | |
5204 | offset <<= 2; | |
5205 | } | |
5206 | if (have_extendval) | |
5207 | SignalException (ReservedInstruction, instruction); | |
5208 | { | |
5209 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
5210 | unsigned64 paddr; | |
5211 | int uncached; | |
5212 | if ((vaddr & 3) != 0) | |
5213 | SignalException(AddressStore); | |
5214 | else | |
5215 | { | |
5216 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
5217 | { | |
5218 | unsigned64 memval = 0; | |
5219 | unsigned64 memval1 = 0; | |
5220 | unsigned64 mask = 0x7; | |
5221 | unsigned int byte; | |
5222 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
5223 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
5224 | memval = ((unsigned64) op2 << (8 * byte)); | |
5225 | { | |
5226 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
5227 | } | |
5228 | } | |
5229 | } | |
5230 | } | |
5231 | } | |
5232 | ||
5233 | ||
5234 | 11010,yyy,VVVVVVVV,s:RI:16::SWSP | |
5235 | *mips16: | |
5236 | { | |
5237 | unsigned32 instruction = instruction_0; | |
5238 | t_reg op2 = (instruction >> 8) & 0x7; | |
5239 | int offset = (instruction >> 0) & 0xff; | |
5240 | t_reg op1 = 29; | |
5241 | if (op2 < 2) | |
5242 | op2 += 16; | |
5243 | op2 = GPR[op2]; | |
5244 | if (have_extendval) | |
5245 | { | |
5246 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5247 | if (offset >= 0x8000) | |
5248 | offset -= 0x10000; | |
5249 | have_extendval = 0; | |
5250 | } | |
5251 | else | |
5252 | { | |
5253 | offset <<= 2; | |
5254 | } | |
5255 | op1 = GPR[op1]; | |
5256 | if (have_extendval) | |
5257 | SignalException (ReservedInstruction, instruction); | |
5258 | { | |
5259 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
5260 | unsigned64 paddr; | |
5261 | int uncached; | |
5262 | if ((vaddr & 3) != 0) | |
5263 | SignalException(AddressStore); | |
5264 | else | |
5265 | { | |
5266 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
5267 | { | |
5268 | unsigned64 memval = 0; | |
5269 | unsigned64 memval1 = 0; | |
5270 | unsigned64 mask = 0x7; | |
5271 | unsigned int byte; | |
5272 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
5273 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
5274 | memval = ((unsigned64) op2 << (8 * byte)); | |
5275 | { | |
5276 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
5277 | } | |
5278 | } | |
5279 | } | |
5280 | } | |
5281 | } | |
5282 | ||
5283 | ||
5284 | 01100010,VVVVVVVV,Q,s:I8:16::SWRASP | |
5285 | *mips16: | |
5286 | { | |
5287 | unsigned32 instruction = instruction_0; | |
5288 | int offset = (instruction >> 0) & 0xff; | |
5289 | t_reg op2 = 31; | |
5290 | t_reg op1 = 29; | |
5291 | if (have_extendval) | |
5292 | { | |
5293 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5294 | if (offset >= 0x8000) | |
5295 | offset -= 0x10000; | |
5296 | have_extendval = 0; | |
5297 | } | |
5298 | else | |
5299 | { | |
5300 | offset <<= 2; | |
5301 | } | |
5302 | op2 = GPR[op2]; | |
5303 | op1 = GPR[op1]; | |
5304 | if (have_extendval) | |
5305 | SignalException (ReservedInstruction, instruction); | |
5306 | { | |
5307 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
5308 | unsigned64 paddr; | |
5309 | int uncached; | |
5310 | if ((vaddr & 3) != 0) | |
5311 | SignalException(AddressStore); | |
5312 | else | |
5313 | { | |
5314 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
5315 | { | |
5316 | unsigned64 memval = 0; | |
5317 | unsigned64 memval1 = 0; | |
5318 | unsigned64 mask = 0x7; | |
5319 | unsigned int byte; | |
5320 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
5321 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
5322 | memval = ((unsigned64) op2 << (8 * byte)); | |
5323 | { | |
5324 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
5325 | } | |
5326 | } | |
5327 | } | |
5328 | } | |
5329 | } | |
5330 | ||
5331 | ||
5332 | 01111,xxx,yyy,DDDDD:RRI:16::SD | |
5333 | *mips16: | |
5334 | { | |
5335 | unsigned32 instruction = instruction_0; | |
5336 | t_reg op1 = (instruction >> 8) & 0x7; | |
5337 | t_reg op2 = (instruction >> 5) & 0x7; | |
5338 | int offset = (instruction >> 0) & 0x1f; | |
5339 | if (op1 < 2) | |
5340 | op1 += 16; | |
5341 | op1 = GPR[op1]; | |
5342 | if (op2 < 2) | |
5343 | op2 += 16; | |
5344 | op2 = GPR[op2]; | |
5345 | if (have_extendval) | |
5346 | { | |
5347 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5348 | if (offset >= 0x8000) | |
5349 | offset -= 0x10000; | |
5350 | have_extendval = 0; | |
5351 | } | |
5352 | else | |
5353 | { | |
5354 | offset <<= 3; | |
5355 | } | |
5356 | if (have_extendval) | |
5357 | SignalException (ReservedInstruction, instruction); | |
5358 | { | |
5359 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
5360 | unsigned64 paddr; | |
5361 | int uncached; | |
5362 | if ((vaddr & 7) != 0) | |
5363 | SignalException(AddressStore); | |
5364 | else | |
5365 | { | |
5366 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
5367 | { | |
5368 | unsigned64 memval = 0; | |
5369 | unsigned64 memval1 = 0; | |
5370 | memval = op2; | |
5371 | { | |
5372 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
5373 | } | |
5374 | } | |
5375 | } | |
5376 | } | |
5377 | } | |
5378 | ||
5379 | ||
5380 | 11111001,yyy,5.RD,s:RI64:16::SDSP | |
5381 | *mips16: | |
5382 | { | |
5383 | unsigned32 instruction = instruction_0; | |
5384 | t_reg op2 = (instruction >> 5) & 0x7; | |
5385 | int offset = (instruction >> 0) & 0x1f; | |
5386 | t_reg op1 = 29; | |
5387 | if (op2 < 2) | |
5388 | op2 += 16; | |
5389 | op2 = GPR[op2]; | |
5390 | if (have_extendval) | |
5391 | { | |
5392 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5393 | if (offset >= 0x8000) | |
5394 | offset -= 0x10000; | |
5395 | have_extendval = 0; | |
5396 | } | |
5397 | else | |
5398 | { | |
5399 | offset <<= 3; | |
5400 | } | |
5401 | op1 = GPR[op1]; | |
5402 | if (have_extendval) | |
5403 | SignalException (ReservedInstruction, instruction); | |
5404 | { | |
5405 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
5406 | unsigned64 paddr; | |
5407 | int uncached; | |
5408 | if ((vaddr & 7) != 0) | |
5409 | SignalException(AddressStore); | |
5410 | else | |
5411 | { | |
5412 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
5413 | { | |
5414 | unsigned64 memval = 0; | |
5415 | unsigned64 memval1 = 0; | |
5416 | memval = op2; | |
5417 | { | |
5418 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
5419 | } | |
5420 | } | |
5421 | } | |
5422 | } | |
5423 | } | |
5424 | ||
5425 | ||
5426 | 11111010,CCCCCCCC,s,Q:I64:16::SDRASP | |
5427 | *mips16: | |
5428 | { | |
5429 | unsigned32 instruction = instruction_0; | |
5430 | int offset = (instruction >> 0) & 0xff; | |
5431 | t_reg op1 = 29; | |
5432 | t_reg op2 = 31; | |
5433 | if (have_extendval) | |
5434 | { | |
5435 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5436 | if (offset >= 0x8000) | |
5437 | offset -= 0x10000; | |
5438 | have_extendval = 0; | |
5439 | } | |
5440 | else | |
5441 | { | |
5442 | offset <<= 3; | |
5443 | } | |
5444 | op1 = GPR[op1]; | |
5445 | op2 = GPR[op2]; | |
5446 | if (have_extendval) | |
5447 | SignalException (ReservedInstruction, instruction); | |
5448 | { | |
5449 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
5450 | unsigned64 paddr; | |
5451 | int uncached; | |
5452 | if ((vaddr & 7) != 0) | |
5453 | SignalException(AddressStore); | |
5454 | else | |
5455 | { | |
5456 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
5457 | { | |
5458 | unsigned64 memval = 0; | |
5459 | unsigned64 memval1 = 0; | |
5460 | memval = op2; | |
5461 | { | |
5462 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
5463 | } | |
5464 | } | |
5465 | } | |
5466 | } | |
5467 | } | |
5468 | ||
5469 | ||
5470 | // ALU Immediate Instructions | |
5471 | ||
5472 | ||
5473 | 01101,ddd,UUUUUUUU,Z:RI:16::LI | |
5474 | *mips16: | |
5475 | { | |
5476 | unsigned32 instruction = instruction_0; | |
5477 | int destreg = (instruction >> 8) & 0x7; | |
5478 | int op2 = (instruction >> 0) & 0xff; | |
5479 | t_reg op1 = 0; | |
5480 | if (destreg < 2) | |
5481 | destreg += 16; | |
5482 | if (have_extendval) | |
5483 | { | |
5484 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5485 | have_extendval = 0; | |
5486 | } | |
5487 | else | |
5488 | { | |
5489 | } | |
5490 | if (have_extendval) | |
5491 | SignalException (ReservedInstruction, instruction); | |
5492 | { | |
5493 | if (destreg != 0) | |
5494 | GPR[destreg] = (op1 | op2); | |
5495 | } | |
5496 | } | |
5497 | ||
5498 | ||
5499 | 01000,xxx,ddd,04444:RRI_A:16::ADDIU | |
5500 | *mips16: | |
5501 | { | |
5502 | unsigned32 instruction = instruction_0; | |
5503 | t_reg op1 = (instruction >> 8) & 0x7; | |
5504 | int destreg = (instruction >> 5) & 0x7; | |
5505 | int op2 = (instruction >> 0) & 0xf; | |
5506 | if (op1 < 2) | |
5507 | op1 += 16; | |
5508 | op1 = GPR[op1]; | |
5509 | if (destreg < 2) | |
5510 | destreg += 16; | |
5511 | if (have_extendval) | |
5512 | { | |
5513 | op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0); | |
5514 | if (op2 >= 0x4000) | |
5515 | op2 -= 0x8000; | |
5516 | have_extendval = 0; | |
5517 | } | |
5518 | else | |
5519 | { | |
5520 | if (op2 >= 0x8) | |
5521 | op2 -= 0x10; | |
5522 | } | |
5523 | if (have_extendval) | |
5524 | SignalException (ReservedInstruction, instruction); | |
5525 | { | |
5526 | unsigned int temp = (unsigned int)(op1 + op2); | |
5527 | signed int tempS UNUSED = (signed int)temp; | |
5528 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
5529 | } | |
5530 | } | |
5531 | ||
5532 | ||
5533 | 01001,www,kkkkkkkk:RI:16::ADDIU8 | |
5534 | *mips16: | |
5535 | { | |
5536 | unsigned32 instruction = instruction_0; | |
5537 | t_reg op1 = (instruction >> 8) & 0x7; | |
5538 | int destreg; | |
5539 | int op2 = (instruction >> 0) & 0xff; | |
5540 | if (op1 < 2) | |
5541 | op1 += 16; | |
5542 | destreg = op1; | |
5543 | op1 = GPR[op1]; | |
5544 | if (have_extendval) | |
5545 | { | |
5546 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5547 | if (op2 >= 0x8000) | |
5548 | op2 -= 0x10000; | |
5549 | have_extendval = 0; | |
5550 | } | |
5551 | else | |
5552 | { | |
5553 | if (op2 >= 0x80) | |
5554 | op2 -= 0x100; | |
5555 | } | |
5556 | if (have_extendval) | |
5557 | SignalException (ReservedInstruction, instruction); | |
5558 | { | |
5559 | unsigned int temp = (unsigned int)(op1 + op2); | |
5560 | signed int tempS UNUSED = (signed int)temp; | |
5561 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
5562 | } | |
5563 | } | |
5564 | ||
5565 | ||
5566 | 01100011,KKKKKKKK,S:I8:16::ADJSP | |
5567 | *mips16: | |
5568 | { | |
5569 | unsigned32 instruction = instruction_0; | |
5570 | int op2 = (instruction >> 0) & 0xff; | |
5571 | t_reg op1 = 29; | |
5572 | int destreg; | |
5573 | if (have_extendval) | |
5574 | { | |
5575 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5576 | if (op2 >= 0x8000) | |
5577 | op2 -= 0x10000; | |
5578 | have_extendval = 0; | |
5579 | } | |
5580 | else | |
5581 | { | |
5582 | if (op2 >= 0x80) | |
5583 | op2 -= 0x100; | |
5584 | op2 <<= 3; | |
5585 | } | |
5586 | destreg = op1; | |
5587 | op1 = GPR[op1]; | |
5588 | if (have_extendval) | |
5589 | SignalException (ReservedInstruction, instruction); | |
5590 | { | |
5591 | unsigned int temp = (unsigned int)(op1 + op2); | |
5592 | signed int tempS UNUSED = (signed int)temp; | |
5593 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
5594 | } | |
5595 | } | |
5596 | ||
5597 | ||
5598 | 00001,ddd,AAAAAAAA,P:RI:16::ADDIUPC | |
5599 | *mips16: | |
5600 | { | |
5601 | unsigned32 instruction = instruction_0; | |
5602 | int destreg = (instruction >> 8) & 0x7; | |
5603 | int op2 = (instruction >> 0) & 0xff; | |
5604 | t_reg op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3; | |
5605 | if (destreg < 2) | |
5606 | destreg += 16; | |
5607 | if (have_extendval) | |
5608 | { | |
5609 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5610 | if (op2 >= 0x8000) | |
5611 | op2 -= 0x10000; | |
5612 | have_extendval = 0; | |
5613 | } | |
5614 | else | |
5615 | { | |
5616 | op2 <<= 2; | |
5617 | } | |
5618 | if (have_extendval) | |
5619 | SignalException (ReservedInstruction, instruction); | |
5620 | { | |
5621 | unsigned int temp = (unsigned int)(op1 + op2); | |
5622 | signed int tempS UNUSED = (signed int)temp; | |
5623 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
5624 | } | |
5625 | } | |
5626 | ||
5627 | ||
5628 | 00000,ddd,AAAAAAAA,s:RI:16::ADDIUSP | |
5629 | *mips16: | |
5630 | { | |
5631 | unsigned32 instruction = instruction_0; | |
5632 | int destreg = (instruction >> 8) & 0x7; | |
5633 | int op2 = (instruction >> 0) & 0xff; | |
5634 | t_reg op1 = 29; | |
5635 | if (destreg < 2) | |
5636 | destreg += 16; | |
5637 | if (have_extendval) | |
5638 | { | |
5639 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5640 | if (op2 >= 0x8000) | |
5641 | op2 -= 0x10000; | |
5642 | have_extendval = 0; | |
5643 | } | |
5644 | else | |
5645 | { | |
5646 | op2 <<= 2; | |
5647 | } | |
5648 | op1 = GPR[op1]; | |
5649 | if (have_extendval) | |
5650 | SignalException (ReservedInstruction, instruction); | |
5651 | { | |
5652 | unsigned int temp = (unsigned int)(op1 + op2); | |
5653 | signed int tempS UNUSED = (signed int)temp; | |
5654 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
5655 | } | |
5656 | } | |
5657 | ||
5658 | ||
5659 | 01000,xxx,ddd,14444:RRI_A:16::DADDIU | |
5660 | *mips16: | |
5661 | { | |
5662 | unsigned32 instruction = instruction_0; | |
5663 | t_reg op1 = (instruction >> 8) & 0x7; | |
5664 | int destreg = (instruction >> 5) & 0x7; | |
5665 | int op2 = (instruction >> 0) & 0xf; | |
5666 | if (op1 < 2) | |
5667 | op1 += 16; | |
5668 | op1 = GPR[op1]; | |
5669 | if (destreg < 2) | |
5670 | destreg += 16; | |
5671 | if (have_extendval) | |
5672 | { | |
5673 | op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0); | |
5674 | if (op2 >= 0x4000) | |
5675 | op2 -= 0x8000; | |
5676 | have_extendval = 0; | |
5677 | } | |
5678 | else | |
5679 | { | |
5680 | if (op2 >= 0x8) | |
5681 | op2 -= 0x10; | |
5682 | } | |
5683 | if (have_extendval) | |
5684 | SignalException (ReservedInstruction, instruction); | |
5685 | { | |
5686 | unsigned64 temp = (unsigned64)(op1 + op2); | |
5687 | word64 tempS UNUSED = (word64)temp; | |
5688 | GPR[destreg] = (unsigned64)temp; | |
5689 | } | |
5690 | } | |
5691 | ||
5692 | ||
5693 | 11111101,www,jjjjj:RI64:16::DADDIU5 | |
5694 | *mips16: | |
5695 | { | |
5696 | unsigned32 instruction = instruction_0; | |
5697 | t_reg op1 = (instruction >> 5) & 0x7; | |
5698 | int destreg; | |
5699 | int op2 = (instruction >> 0) & 0x1f; | |
5700 | if (op1 < 2) | |
5701 | op1 += 16; | |
5702 | destreg = op1; | |
5703 | op1 = GPR[op1]; | |
5704 | if (have_extendval) | |
5705 | { | |
5706 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5707 | if (op2 >= 0x8000) | |
5708 | op2 -= 0x10000; | |
5709 | have_extendval = 0; | |
5710 | } | |
5711 | else | |
5712 | { | |
5713 | if (op2 >= 0x10) | |
5714 | op2 -= 0x20; | |
5715 | } | |
5716 | if (have_extendval) | |
5717 | SignalException (ReservedInstruction, instruction); | |
5718 | { | |
5719 | unsigned64 temp = (unsigned64)(op1 + op2); | |
5720 | word64 tempS UNUSED = (word64)temp; | |
5721 | GPR[destreg] = (unsigned64)temp; | |
5722 | } | |
5723 | } | |
5724 | ||
5725 | ||
5726 | 11111011,KKKKKKKK,S:I64:16::DADJSP | |
5727 | *mips16: | |
5728 | { | |
5729 | unsigned32 instruction = instruction_0; | |
5730 | int op2 = (instruction >> 0) & 0xff; | |
5731 | t_reg op1 = 29; | |
5732 | int destreg; | |
5733 | if (have_extendval) | |
5734 | { | |
5735 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5736 | if (op2 >= 0x8000) | |
5737 | op2 -= 0x10000; | |
5738 | have_extendval = 0; | |
5739 | } | |
5740 | else | |
5741 | { | |
5742 | if (op2 >= 0x80) | |
5743 | op2 -= 0x100; | |
5744 | op2 <<= 3; | |
5745 | } | |
5746 | destreg = op1; | |
5747 | op1 = GPR[op1]; | |
5748 | if (have_extendval) | |
5749 | SignalException (ReservedInstruction, instruction); | |
5750 | { | |
5751 | unsigned64 temp = (unsigned64)(op1 + op2); | |
5752 | word64 tempS UNUSED = (word64)temp; | |
5753 | GPR[destreg] = (unsigned64)temp; | |
5754 | } | |
5755 | } | |
5756 | ||
5757 | ||
5758 | 11111110,ddd,EEEEE,P:RI64:16::DADDIUPC | |
5759 | *mips16: | |
5760 | { | |
5761 | unsigned32 instruction = instruction_0; | |
5762 | int destreg = (instruction >> 5) & 0x7; | |
5763 | int op2 = (instruction >> 0) & 0x1f; | |
5764 | t_reg op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3; | |
5765 | if (destreg < 2) | |
5766 | destreg += 16; | |
5767 | if (have_extendval) | |
5768 | { | |
5769 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5770 | if (op2 >= 0x8000) | |
5771 | op2 -= 0x10000; | |
5772 | have_extendval = 0; | |
5773 | } | |
5774 | else | |
5775 | { | |
5776 | op2 <<= 2; | |
5777 | } | |
5778 | if (have_extendval) | |
5779 | SignalException (ReservedInstruction, instruction); | |
5780 | { | |
5781 | unsigned64 temp = (unsigned64)(op1 + op2); | |
5782 | word64 tempS UNUSED = (word64)temp; | |
5783 | GPR[destreg] = (unsigned64)temp; | |
5784 | } | |
5785 | } | |
5786 | ||
5787 | ||
5788 | 11111111,ddd,EEEEE,s:RI64:16::DADDIUSP | |
5789 | *mips16: | |
5790 | { | |
5791 | unsigned32 instruction = instruction_0; | |
5792 | int destreg = (instruction >> 5) & 0x7; | |
5793 | int op2 = (instruction >> 0) & 0x1f; | |
5794 | t_reg op1 = 29; | |
5795 | if (destreg < 2) | |
5796 | destreg += 16; | |
5797 | if (have_extendval) | |
5798 | { | |
5799 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5800 | if (op2 >= 0x8000) | |
5801 | op2 -= 0x10000; | |
5802 | have_extendval = 0; | |
5803 | } | |
5804 | else | |
5805 | { | |
5806 | op2 <<= 2; | |
5807 | } | |
5808 | op1 = GPR[op1]; | |
5809 | if (have_extendval) | |
5810 | SignalException (ReservedInstruction, instruction); | |
5811 | { | |
5812 | unsigned64 temp = (unsigned64)(op1 + op2); | |
5813 | word64 tempS UNUSED = (word64)temp; | |
5814 | GPR[destreg] = (unsigned64)temp; | |
5815 | } | |
5816 | } | |
5817 | ||
5818 | ||
5819 | 01010,xxx,88888888,T:RI:16::SLTI | |
5820 | *mips16: | |
5821 | { | |
5822 | unsigned32 instruction = instruction_0; | |
5823 | t_reg op1 = (instruction >> 8) & 0x7; | |
5824 | int op2 = (instruction >> 0) & 0xff; | |
5825 | int destreg = 24; | |
5826 | if (op1 < 2) | |
5827 | op1 += 16; | |
5828 | op1 = GPR[op1]; | |
5829 | if (have_extendval) | |
5830 | { | |
5831 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5832 | if (op2 >= 0x8000) | |
5833 | op2 -= 0x10000; | |
5834 | have_extendval = 0; | |
5835 | } | |
5836 | else | |
5837 | { | |
5838 | } | |
5839 | if (have_extendval) | |
5840 | SignalException (ReservedInstruction, instruction); | |
5841 | { | |
5842 | if ((word64)op1 < (word64)op2) | |
5843 | GPR[destreg] = 1; | |
5844 | else | |
5845 | GPR[destreg] = 0; | |
5846 | } | |
5847 | } | |
5848 | ||
5849 | ||
5850 | 01011,xxx,88888888,T:RI:16::SLTIU | |
5851 | *mips16: | |
5852 | { | |
5853 | unsigned32 instruction = instruction_0; | |
5854 | t_reg op1 = (instruction >> 8) & 0x7; | |
5855 | int op2 = (instruction >> 0) & 0xff; | |
5856 | int destreg = 24; | |
5857 | if (op1 < 2) | |
5858 | op1 += 16; | |
5859 | op1 = GPR[op1]; | |
5860 | if (have_extendval) | |
5861 | { | |
5862 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5863 | if (op2 >= 0x8000) | |
5864 | op2 -= 0x10000; | |
5865 | have_extendval = 0; | |
5866 | } | |
5867 | else | |
5868 | { | |
5869 | } | |
5870 | if (have_extendval) | |
5871 | SignalException (ReservedInstruction, instruction); | |
5872 | { | |
5873 | if ((unsigned64)op1 < (unsigned64)op2) | |
5874 | GPR[destreg] = 1; | |
5875 | else | |
5876 | GPR[destreg] = 0; | |
5877 | } | |
5878 | } | |
5879 | ||
5880 | ||
5881 | 11101,xxx,yyy,01010,T:RR:16::CMP | |
5882 | *mips16: | |
5883 | { | |
5884 | unsigned32 instruction = instruction_0; | |
5885 | t_reg op1 = (instruction >> 8) & 0x7; | |
5886 | t_reg op2 = (instruction >> 5) & 0x7; | |
5887 | int destreg = 24; | |
5888 | if (op1 < 2) | |
5889 | op1 += 16; | |
5890 | op1 = GPR[op1]; | |
5891 | if (op2 < 2) | |
5892 | op2 += 16; | |
5893 | op2 = GPR[op2]; | |
5894 | if (have_extendval) | |
5895 | SignalException (ReservedInstruction, instruction); | |
5896 | { | |
5897 | GPR[destreg] = (op1 ^ op2); | |
5898 | } | |
5899 | } | |
5900 | ||
5901 | ||
5902 | 01110,xxx,UUUUUUUU,T:RI:16::CMPI | |
5903 | *mips16: | |
5904 | { | |
5905 | unsigned32 instruction = instruction_0; | |
5906 | t_reg op1 = (instruction >> 8) & 0x7; | |
5907 | int op2 = (instruction >> 0) & 0xff; | |
5908 | int destreg = 24; | |
5909 | if (op1 < 2) | |
5910 | op1 += 16; | |
5911 | op1 = GPR[op1]; | |
5912 | if (have_extendval) | |
5913 | { | |
5914 | op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
5915 | have_extendval = 0; | |
5916 | } | |
5917 | else | |
5918 | { | |
5919 | } | |
5920 | if (have_extendval) | |
5921 | SignalException (ReservedInstruction, instruction); | |
5922 | { | |
5923 | GPR[destreg] = (op1 ^ op2); | |
5924 | } | |
5925 | } | |
5926 | ||
5927 | ||
5928 | // Two/Three Operand, Register-Type | |
5929 | ||
5930 | ||
5931 | 11100,xxx,yyy,ddd,01:RRR:16::ADDU | |
5932 | *mips16: | |
5933 | { | |
5934 | unsigned32 instruction = instruction_0; | |
5935 | t_reg op1 = (instruction >> 8) & 0x7; | |
5936 | t_reg op2 = (instruction >> 5) & 0x7; | |
5937 | int destreg = (instruction >> 2) & 0x7; | |
5938 | if (op1 < 2) | |
5939 | op1 += 16; | |
5940 | op1 = GPR[op1]; | |
5941 | if (op2 < 2) | |
5942 | op2 += 16; | |
5943 | op2 = GPR[op2]; | |
5944 | if (destreg < 2) | |
5945 | destreg += 16; | |
5946 | if (have_extendval) | |
5947 | SignalException (ReservedInstruction, instruction); | |
5948 | { | |
5949 | unsigned int temp = (unsigned int)(op1 + op2); | |
5950 | signed int tempS UNUSED = (signed int)temp; | |
5951 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
5952 | } | |
5953 | } | |
5954 | ||
5955 | ||
5956 | 11100,xxx,yyy,ddd,11:RRR:16::SUBU | |
5957 | *mips16: | |
5958 | { | |
5959 | unsigned32 instruction = instruction_0; | |
5960 | t_reg op1 = (instruction >> 8) & 0x7; | |
5961 | t_reg op2 = (instruction >> 5) & 0x7; | |
5962 | int destreg = (instruction >> 2) & 0x7; | |
5963 | if (op1 < 2) | |
5964 | op1 += 16; | |
5965 | op1 = GPR[op1]; | |
5966 | if (op2 < 2) | |
5967 | op2 += 16; | |
5968 | op2 = GPR[op2]; | |
5969 | if (destreg < 2) | |
5970 | destreg += 16; | |
5971 | if (have_extendval) | |
5972 | SignalException (ReservedInstruction, instruction); | |
5973 | { | |
5974 | unsigned int temp = (unsigned int)(op1 - op2); | |
5975 | signed int tempS UNUSED = (signed int)temp; | |
5976 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
5977 | } | |
5978 | } | |
5979 | ||
5980 | ||
5981 | 11100,xxx,yyy,ddd,00:RRR:16::DADDU | |
5982 | *mips16: | |
5983 | { | |
5984 | unsigned32 instruction = instruction_0; | |
5985 | t_reg op1 = (instruction >> 8) & 0x7; | |
5986 | t_reg op2 = (instruction >> 5) & 0x7; | |
5987 | int destreg = (instruction >> 2) & 0x7; | |
5988 | if (op1 < 2) | |
5989 | op1 += 16; | |
5990 | op1 = GPR[op1]; | |
5991 | if (op2 < 2) | |
5992 | op2 += 16; | |
5993 | op2 = GPR[op2]; | |
5994 | if (destreg < 2) | |
5995 | destreg += 16; | |
5996 | if (have_extendval) | |
5997 | SignalException (ReservedInstruction, instruction); | |
5998 | { | |
5999 | unsigned64 temp = (unsigned64)(op1 + op2); | |
6000 | word64 tempS UNUSED = (word64)temp; | |
6001 | GPR[destreg] = (unsigned64)temp; | |
6002 | } | |
6003 | } | |
6004 | ||
6005 | ||
6006 | 11100,xxx,yyy,ddd,10:RRR:16::DSUBU | |
6007 | *mips16: | |
6008 | { | |
6009 | unsigned32 instruction = instruction_0; | |
6010 | t_reg op1 = (instruction >> 8) & 0x7; | |
6011 | t_reg op2 = (instruction >> 5) & 0x7; | |
6012 | int destreg = (instruction >> 2) & 0x7; | |
6013 | if (op1 < 2) | |
6014 | op1 += 16; | |
6015 | op1 = GPR[op1]; | |
6016 | if (op2 < 2) | |
6017 | op2 += 16; | |
6018 | op2 = GPR[op2]; | |
6019 | if (destreg < 2) | |
6020 | destreg += 16; | |
6021 | if (have_extendval) | |
6022 | SignalException (ReservedInstruction, instruction); | |
6023 | { | |
6024 | unsigned64 temp = (unsigned64)(op1 - op2); | |
6025 | word64 tempS UNUSED = (word64)temp; | |
6026 | GPR[destreg] = (unsigned64)temp; | |
6027 | } | |
6028 | } | |
6029 | ||
6030 | ||
6031 | 11101,xxx,yyy,00010,T:RR:16::SLT | |
6032 | *mips16: | |
6033 | { | |
6034 | unsigned32 instruction = instruction_0; | |
6035 | t_reg op1 = (instruction >> 8) & 0x7; | |
6036 | t_reg op2 = (instruction >> 5) & 0x7; | |
6037 | int destreg = 24; | |
6038 | if (op1 < 2) | |
6039 | op1 += 16; | |
6040 | op1 = GPR[op1]; | |
6041 | if (op2 < 2) | |
6042 | op2 += 16; | |
6043 | op2 = GPR[op2]; | |
6044 | if (have_extendval) | |
6045 | SignalException (ReservedInstruction, instruction); | |
6046 | { | |
6047 | if ((word64)op1 < (word64)op2) | |
6048 | GPR[destreg] = 1; | |
6049 | else | |
6050 | GPR[destreg] = 0; | |
6051 | } | |
6052 | } | |
6053 | ||
6054 | ||
6055 | 11101,xxx,yyy,00011,T:RR:16::SLTU | |
6056 | *mips16: | |
6057 | { | |
6058 | unsigned32 instruction = instruction_0; | |
6059 | t_reg op1 = (instruction >> 8) & 0x7; | |
6060 | t_reg op2 = (instruction >> 5) & 0x7; | |
6061 | int destreg = 24; | |
6062 | if (op1 < 2) | |
6063 | op1 += 16; | |
6064 | op1 = GPR[op1]; | |
6065 | if (op2 < 2) | |
6066 | op2 += 16; | |
6067 | op2 = GPR[op2]; | |
6068 | if (have_extendval) | |
6069 | SignalException (ReservedInstruction, instruction); | |
6070 | { | |
6071 | if ((unsigned64)op1 < (unsigned64)op2) | |
6072 | GPR[destreg] = 1; | |
6073 | else | |
6074 | GPR[destreg] = 0; | |
6075 | } | |
6076 | } | |
6077 | ||
6078 | ||
6079 | 11101,ddd,yyy,01011,Z:RR:16::NEG | |
6080 | *mips16: | |
6081 | { | |
6082 | unsigned32 instruction = instruction_0; | |
6083 | int destreg = (instruction >> 8) & 0x7; | |
6084 | t_reg op2 = (instruction >> 5) & 0x7; | |
6085 | t_reg op1 = 0; | |
6086 | if (destreg < 2) | |
6087 | destreg += 16; | |
6088 | if (op2 < 2) | |
6089 | op2 += 16; | |
6090 | op2 = GPR[op2]; | |
6091 | if (have_extendval) | |
6092 | SignalException (ReservedInstruction, instruction); | |
6093 | { | |
6094 | unsigned int temp = (unsigned int)(op1 - op2); | |
6095 | signed int tempS UNUSED = (signed int)temp; | |
6096 | GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32); | |
6097 | } | |
6098 | } | |
6099 | ||
6100 | ||
6101 | 11101,www,yyy,01100:RR:16::AND | |
6102 | *mips16: | |
6103 | { | |
6104 | unsigned32 instruction = instruction_0; | |
6105 | t_reg op1 = (instruction >> 8) & 0x7; | |
6106 | int destreg; | |
6107 | t_reg op2 = (instruction >> 5) & 0x7; | |
6108 | if (op1 < 2) | |
6109 | op1 += 16; | |
6110 | destreg = op1; | |
6111 | op1 = GPR[op1]; | |
6112 | if (op2 < 2) | |
6113 | op2 += 16; | |
6114 | op2 = GPR[op2]; | |
6115 | if (have_extendval) | |
6116 | SignalException (ReservedInstruction, instruction); | |
6117 | { | |
6118 | GPR[destreg] = (op1 & op2); | |
6119 | } | |
6120 | } | |
6121 | ||
6122 | ||
6123 | 11101,www,yyy,01101:RR:16::OR | |
6124 | *mips16: | |
6125 | { | |
6126 | unsigned32 instruction = instruction_0; | |
6127 | t_reg op1 = (instruction >> 8) & 0x7; | |
6128 | int destreg; | |
6129 | t_reg op2 = (instruction >> 5) & 0x7; | |
6130 | if (op1 < 2) | |
6131 | op1 += 16; | |
6132 | destreg = op1; | |
6133 | op1 = GPR[op1]; | |
6134 | if (op2 < 2) | |
6135 | op2 += 16; | |
6136 | op2 = GPR[op2]; | |
6137 | if (have_extendval) | |
6138 | SignalException (ReservedInstruction, instruction); | |
6139 | { | |
6140 | if (destreg != 0) | |
6141 | GPR[destreg] = (op1 | op2); | |
6142 | } | |
6143 | } | |
6144 | ||
6145 | ||
6146 | 11101,www,yyy,01110:RR:16::XOR | |
6147 | *mips16: | |
6148 | { | |
6149 | unsigned32 instruction = instruction_0; | |
6150 | t_reg op1 = (instruction >> 8) & 0x7; | |
6151 | int destreg; | |
6152 | t_reg op2 = (instruction >> 5) & 0x7; | |
6153 | if (op1 < 2) | |
6154 | op1 += 16; | |
6155 | destreg = op1; | |
6156 | op1 = GPR[op1]; | |
6157 | if (op2 < 2) | |
6158 | op2 += 16; | |
6159 | op2 = GPR[op2]; | |
6160 | if (have_extendval) | |
6161 | SignalException (ReservedInstruction, instruction); | |
6162 | { | |
6163 | GPR[destreg] = (op1 ^ op2); | |
6164 | } | |
6165 | } | |
6166 | ||
6167 | ||
6168 | 11101,ddd,yyy,01111,Z:RR:16::NOT | |
6169 | *mips16: | |
6170 | { | |
6171 | unsigned32 instruction = instruction_0; | |
6172 | int destreg = (instruction >> 8) & 0x7; | |
6173 | t_reg op2 = (instruction >> 5) & 0x7; | |
6174 | t_reg op1 = 0; | |
6175 | if (destreg < 2) | |
6176 | destreg += 16; | |
6177 | if (op2 < 2) | |
6178 | op2 += 16; | |
6179 | op2 = GPR[op2]; | |
6180 | if (have_extendval) | |
6181 | SignalException (ReservedInstruction, instruction); | |
6182 | { | |
6183 | if (destreg != 0) | |
6184 | GPR[destreg] = ~(op1 | op2); | |
6185 | } | |
6186 | } | |
6187 | ||
6188 | ||
6189 | 01100111,ddd,XXXXX,z:I8_MOVR32:16::MOVR32 | |
6190 | *mips16: | |
6191 | { | |
6192 | unsigned32 instruction = instruction_0; | |
6193 | int destreg = (instruction >> 5) & 0x7; | |
6194 | t_reg op1 = (instruction >> 0) & 0x1f; | |
6195 | t_reg op2 = 0; | |
6196 | if (destreg < 2) | |
6197 | destreg += 16; | |
6198 | op1 = GPR[op1]; | |
6199 | if (have_extendval) | |
6200 | SignalException (ReservedInstruction, instruction); | |
6201 | { | |
6202 | if (destreg != 0) | |
6203 | GPR[destreg] = (op1 | op2); | |
6204 | } | |
6205 | } | |
6206 | ||
6207 | ||
6208 | 01100101,YYYYY,xxx,z:I8_MOV32R:16::MOV32R | |
6209 | *mips16: | |
6210 | { | |
6211 | unsigned32 instruction = instruction_0; | |
6212 | int destreg = (instruction >> 3) & 0x1f; | |
6213 | t_reg op1 = (instruction >> 0) & 0x7; | |
6214 | t_reg op2 = 0; | |
6215 | destreg = (destreg >> 2) | ((destreg & 3) << 3); | |
6216 | if (op1 < 2) | |
6217 | op1 += 16; | |
6218 | op1 = GPR[op1]; | |
6219 | if (have_extendval) | |
6220 | SignalException (ReservedInstruction, instruction); | |
6221 | { | |
6222 | if (destreg != 0) | |
6223 | GPR[destreg] = (op1 | op2); | |
6224 | } | |
6225 | } | |
6226 | ||
6227 | ||
6228 | 00110,ddd,yyy,sss,00:ISHIFT:16::SLL | |
6229 | *mips16: | |
6230 | { | |
6231 | unsigned32 instruction = instruction_0; | |
6232 | int destreg = (instruction >> 8) & 0x7; | |
6233 | t_reg op2 = (instruction >> 5) & 0x7; | |
6234 | int op1 = (instruction >> 2) & 0x7; | |
6235 | if (destreg < 2) | |
6236 | destreg += 16; | |
6237 | if (op2 < 2) | |
6238 | op2 += 16; | |
6239 | op2 = GPR[op2]; | |
6240 | if (have_extendval) | |
6241 | { | |
6242 | op1 = (extendval >> 6) & 0x1f; | |
6243 | have_extendval = 0; | |
6244 | } | |
6245 | else | |
6246 | { | |
6247 | if (op1 == 0) | |
6248 | op1 = 8; | |
6249 | } | |
6250 | if (have_extendval) | |
6251 | SignalException (ReservedInstruction, instruction); | |
6252 | { | |
6253 | GPR[destreg] = ((unsigned64)op2 << op1); | |
6254 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
6255 | } | |
6256 | } | |
6257 | ||
6258 | ||
6259 | 00110,ddd,yyy,sss,10:ISHIFT:16::SRL | |
6260 | *mips16: | |
6261 | { | |
6262 | unsigned32 instruction = instruction_0; | |
6263 | int destreg = (instruction >> 8) & 0x7; | |
6264 | t_reg op2 = (instruction >> 5) & 0x7; | |
6265 | int op1 = (instruction >> 2) & 0x7; | |
6266 | if (destreg < 2) | |
6267 | destreg += 16; | |
6268 | if (op2 < 2) | |
6269 | op2 += 16; | |
6270 | op2 = GPR[op2]; | |
6271 | if (have_extendval) | |
6272 | { | |
6273 | op1 = (extendval >> 6) & 0x1f; | |
6274 | have_extendval = 0; | |
6275 | } | |
6276 | else | |
6277 | { | |
6278 | if (op1 == 0) | |
6279 | op1 = 8; | |
6280 | } | |
6281 | if (have_extendval) | |
6282 | SignalException (ReservedInstruction, instruction); | |
6283 | { | |
6284 | GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); | |
6285 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
6286 | } | |
6287 | } | |
6288 | ||
6289 | ||
6290 | 00110,ddd,yyy,sss,11:ISHIFT:16::SRA | |
6291 | *mips16: | |
6292 | { | |
6293 | unsigned32 instruction = instruction_0; | |
6294 | int destreg = (instruction >> 8) & 0x7; | |
6295 | t_reg op2 = (instruction >> 5) & 0x7; | |
6296 | int op1 = (instruction >> 2) & 0x7; | |
6297 | if (destreg < 2) | |
6298 | destreg += 16; | |
6299 | if (op2 < 2) | |
6300 | op2 += 16; | |
6301 | op2 = GPR[op2]; | |
6302 | if (have_extendval) | |
6303 | { | |
6304 | op1 = (extendval >> 6) & 0x1f; | |
6305 | have_extendval = 0; | |
6306 | } | |
6307 | else | |
6308 | { | |
6309 | if (op1 == 0) | |
6310 | op1 = 8; | |
6311 | } | |
6312 | if (have_extendval) | |
6313 | SignalException (ReservedInstruction, instruction); | |
6314 | { | |
6315 | unsigned int highbit = (unsigned int)1 << 31; | |
6316 | GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); | |
6317 | GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0); | |
6318 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
6319 | } | |
6320 | } | |
6321 | ||
6322 | ||
6323 | 11101,xxx,vvv,00100:RR:16::SLLV | |
6324 | *mips16: | |
6325 | { | |
6326 | unsigned32 instruction = instruction_0; | |
6327 | t_reg op1 = (instruction >> 8) & 0x7; | |
6328 | t_reg op2 = (instruction >> 5) & 0x7; | |
6329 | int destreg; | |
6330 | if (op1 < 2) | |
6331 | op1 += 16; | |
6332 | op1 = GPR[op1]; | |
6333 | if (op2 < 2) | |
6334 | op2 += 16; | |
6335 | destreg = op2; | |
6336 | op2 = GPR[op2]; | |
6337 | if (have_extendval) | |
6338 | SignalException (ReservedInstruction, instruction); | |
6339 | { | |
6340 | op1 &= 0x1F; | |
6341 | GPR[destreg] = ((unsigned64)op2 << op1); | |
6342 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
6343 | } | |
6344 | } | |
6345 | ||
6346 | ||
6347 | 11101,xxx,vvv,00110:RR:16::SRLV | |
6348 | *mips16: | |
6349 | { | |
6350 | unsigned32 instruction = instruction_0; | |
6351 | t_reg op1 = (instruction >> 8) & 0x7; | |
6352 | t_reg op2 = (instruction >> 5) & 0x7; | |
6353 | int destreg; | |
6354 | if (op1 < 2) | |
6355 | op1 += 16; | |
6356 | op1 = GPR[op1]; | |
6357 | if (op2 < 2) | |
6358 | op2 += 16; | |
6359 | destreg = op2; | |
6360 | op2 = GPR[op2]; | |
6361 | if (have_extendval) | |
6362 | SignalException (ReservedInstruction, instruction); | |
6363 | { | |
6364 | op1 &= 0x1F; | |
6365 | GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); | |
6366 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
6367 | } | |
6368 | } | |
6369 | ||
6370 | ||
6371 | 11101,xxx,vvv,00111:RR:16::SRAV | |
6372 | *mips16: | |
6373 | { | |
6374 | unsigned32 instruction = instruction_0; | |
6375 | t_reg op1 = (instruction >> 8) & 0x7; | |
6376 | t_reg op2 = (instruction >> 5) & 0x7; | |
6377 | int destreg; | |
6378 | if (op1 < 2) | |
6379 | op1 += 16; | |
6380 | op1 = GPR[op1]; | |
6381 | if (op2 < 2) | |
6382 | op2 += 16; | |
6383 | destreg = op2; | |
6384 | op2 = GPR[op2]; | |
6385 | if (have_extendval) | |
6386 | SignalException (ReservedInstruction, instruction); | |
6387 | { | |
6388 | unsigned int highbit = (unsigned int)1 << 31; | |
6389 | op1 &= 0x1F; | |
6390 | GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1); | |
6391 | GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0); | |
6392 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
6393 | } | |
6394 | } | |
6395 | ||
6396 | ||
6397 | 00110,ddd,yyy,[[[,01:ISHIFT:16::DSLL | |
6398 | *mips16: | |
6399 | { | |
6400 | unsigned32 instruction = instruction_0; | |
6401 | int destreg = (instruction >> 8) & 0x7; | |
6402 | t_reg op2 = (instruction >> 5) & 0x7; | |
6403 | int op1 = (instruction >> 2) & 0x7; | |
6404 | if (destreg < 2) | |
6405 | destreg += 16; | |
6406 | if (op2 < 2) | |
6407 | op2 += 16; | |
6408 | op2 = GPR[op2]; | |
6409 | if (have_extendval) | |
6410 | { | |
6411 | op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20); | |
6412 | have_extendval = 0; | |
6413 | } | |
6414 | else | |
6415 | { | |
6416 | if (op1 == 0) | |
6417 | op1 = 8; | |
6418 | } | |
6419 | if (have_extendval) | |
6420 | SignalException (ReservedInstruction, instruction); | |
6421 | { | |
6422 | GPR[destreg] = ((unsigned64)op2 << op1); | |
6423 | } | |
6424 | } | |
6425 | ||
6426 | ||
6427 | 11101,XXX,vvv,01000:RR:16::DSRL | |
6428 | *mips16: | |
6429 | { | |
6430 | unsigned32 instruction = instruction_0; | |
6431 | int op1 = (instruction >> 8) & 0x7; | |
6432 | t_reg op2 = (instruction >> 5) & 0x7; | |
6433 | int destreg; | |
6434 | if (have_extendval) | |
6435 | { | |
6436 | op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20); | |
6437 | have_extendval = 0; | |
6438 | } | |
6439 | else | |
6440 | { | |
6441 | if (op1 == 0) | |
6442 | op1 = 8; | |
6443 | } | |
6444 | if (op2 < 2) | |
6445 | op2 += 16; | |
6446 | destreg = op2; | |
6447 | op2 = GPR[op2]; | |
6448 | if (have_extendval) | |
6449 | SignalException (ReservedInstruction, instruction); | |
6450 | { | |
6451 | GPR[destreg] = ((unsigned64)(op2) >> op1); | |
6452 | } | |
6453 | } | |
6454 | ||
6455 | ||
6456 | 11101,xxx,vvv,10011:RR:16::DSRA | |
6457 | *mips16: | |
6458 | { | |
6459 | unsigned32 instruction = instruction_0; | |
6460 | int op1 = (instruction >> 8) & 0x7; | |
6461 | t_reg op2 = (instruction >> 5) & 0x7; | |
6462 | int destreg; | |
6463 | if (have_extendval) | |
6464 | { | |
6465 | op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20); | |
6466 | have_extendval = 0; | |
6467 | } | |
6468 | else | |
6469 | { | |
6470 | if (op1 == 0) | |
6471 | op1 = 8; | |
6472 | } | |
6473 | if (op2 < 2) | |
6474 | op2 += 16; | |
6475 | destreg = op2; | |
6476 | op2 = GPR[op2]; | |
6477 | if (have_extendval) | |
6478 | SignalException (ReservedInstruction, instruction); | |
6479 | { | |
6480 | unsigned64 highbit = (unsigned64)1 << 63; | |
6481 | GPR[destreg] = ((unsigned64)(op2) >> op1); | |
6482 | GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0); | |
6483 | } | |
6484 | } | |
6485 | ||
6486 | ||
6487 | 11101,xxx,vvv,10100:RR:16::DSLLV | |
6488 | *mips16: | |
6489 | { | |
6490 | unsigned32 instruction = instruction_0; | |
6491 | t_reg op1 = (instruction >> 8) & 0x7; | |
6492 | t_reg op2 = (instruction >> 5) & 0x7; | |
6493 | int destreg; | |
6494 | if (op1 < 2) | |
6495 | op1 += 16; | |
6496 | op1 = GPR[op1]; | |
6497 | if (op2 < 2) | |
6498 | op2 += 16; | |
6499 | destreg = op2; | |
6500 | op2 = GPR[op2]; | |
6501 | if (have_extendval) | |
6502 | SignalException (ReservedInstruction, instruction); | |
6503 | { | |
6504 | op1 &= 0x3F; | |
6505 | GPR[destreg] = ((unsigned64)op2 << op1); | |
6506 | } | |
6507 | } | |
6508 | ||
6509 | ||
6510 | 11101,xxx,vvv,10110:RR:16::DSRLV | |
6511 | *mips16: | |
6512 | { | |
6513 | unsigned32 instruction = instruction_0; | |
6514 | t_reg op1 = (instruction >> 8) & 0x7; | |
6515 | t_reg op2 = (instruction >> 5) & 0x7; | |
6516 | int destreg; | |
6517 | if (op1 < 2) | |
6518 | op1 += 16; | |
6519 | op1 = GPR[op1]; | |
6520 | if (op2 < 2) | |
6521 | op2 += 16; | |
6522 | destreg = op2; | |
6523 | op2 = GPR[op2]; | |
6524 | if (have_extendval) | |
6525 | SignalException (ReservedInstruction, instruction); | |
6526 | { | |
6527 | op1 &= 0x3F; | |
6528 | GPR[destreg] = ((unsigned64)(op2) >> op1); | |
6529 | } | |
6530 | } | |
6531 | ||
6532 | ||
6533 | 11101,xxx,vvv,10111:RR:16::DSRAV | |
6534 | *mips16: | |
6535 | { | |
6536 | unsigned32 instruction = instruction_0; | |
6537 | t_reg op1 = (instruction >> 8) & 0x7; | |
6538 | t_reg op2 = (instruction >> 5) & 0x7; | |
6539 | int destreg; | |
6540 | if (op1 < 2) | |
6541 | op1 += 16; | |
6542 | op1 = GPR[op1]; | |
6543 | if (op2 < 2) | |
6544 | op2 += 16; | |
6545 | destreg = op2; | |
6546 | op2 = GPR[op2]; | |
6547 | if (have_extendval) | |
6548 | SignalException (ReservedInstruction, instruction); | |
6549 | { | |
6550 | unsigned64 highbit = (unsigned64)1 << 63; | |
6551 | op1 &= 0x3F; | |
6552 | GPR[destreg] = ((unsigned64)(op2) >> op1); | |
6553 | GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0); | |
6554 | } | |
6555 | } | |
6556 | ||
6557 | ||
6558 | // Multiply /Divide Instructions | |
6559 | ||
6560 | ||
6561 | 11101,xxx,yyy,11000:RR:16::MULT | |
6562 | *mips16: | |
6563 | { | |
6564 | unsigned32 instruction = instruction_0; | |
6565 | t_reg op1 = (instruction >> 8) & 0x7; | |
6566 | t_reg op2 = (instruction >> 5) & 0x7; | |
6567 | if (op1 < 2) | |
6568 | op1 += 16; | |
6569 | op1 = GPR[op1]; | |
6570 | if (op2 < 2) | |
6571 | op2 += 16; | |
6572 | op2 = GPR[op2]; | |
6573 | if (have_extendval) | |
6574 | SignalException (ReservedInstruction, instruction); | |
6575 | { | |
6576 | CHECKHILO("Multiplication"); | |
6577 | { | |
6578 | unsigned64 temp = ((word64) op1 * (word64) op2); | |
6579 | LO = SIGNEXTEND((unsigned64)VL4_8(temp),32); | |
6580 | HI = SIGNEXTEND((unsigned64)VH4_8(temp),32); | |
6581 | } | |
6582 | } | |
6583 | } | |
6584 | ||
6585 | ||
6586 | 11101,xxx,yyy,11001:RR:16::MULTU | |
6587 | *mips16: | |
6588 | { | |
6589 | unsigned32 instruction = instruction_0; | |
6590 | t_reg op1 = (instruction >> 8) & 0x7; | |
6591 | t_reg op2 = (instruction >> 5) & 0x7; | |
6592 | if (op1 < 2) | |
6593 | op1 += 16; | |
6594 | op1 = GPR[op1]; | |
6595 | if (op2 < 2) | |
6596 | op2 += 16; | |
6597 | op2 = GPR[op2]; | |
6598 | if (have_extendval) | |
6599 | SignalException (ReservedInstruction, instruction); | |
6600 | { | |
6601 | CHECKHILO("Multiplication"); | |
6602 | { | |
6603 | unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff)); | |
6604 | LO = SIGNEXTEND((unsigned64)VL4_8(temp),32); | |
6605 | HI = SIGNEXTEND((unsigned64)VH4_8(temp),32); | |
6606 | } | |
6607 | } | |
6608 | } | |
6609 | ||
6610 | ||
6611 | 11101,xxx,yyy,11010:RR:16::DIV | |
6612 | *mips16: | |
6613 | { | |
6614 | unsigned32 instruction = instruction_0; | |
6615 | t_reg op1 = (instruction >> 8) & 0x7; | |
6616 | t_reg op2 = (instruction >> 5) & 0x7; | |
6617 | if (op1 < 2) | |
6618 | op1 += 16; | |
6619 | op1 = GPR[op1]; | |
6620 | if (op2 < 2) | |
6621 | op2 += 16; | |
6622 | op2 = GPR[op2]; | |
6623 | if (have_extendval) | |
6624 | SignalException (ReservedInstruction, instruction); | |
6625 | { | |
6626 | CHECKHILO("Division"); | |
6627 | { | |
6628 | int d1 = op1; | |
6629 | int d2 = op2; | |
6630 | if (d2 == 0) | |
6631 | { | |
6632 | LO = SIGNEXTEND(0x80000000,32); | |
6633 | HI = SIGNEXTEND(0,32); | |
6634 | } | |
6635 | else if (d2 == -1 && d1 == 0x80000000) | |
6636 | { | |
6637 | LO = SIGNEXTEND(0x80000000,32); | |
6638 | HI = SIGNEXTEND(0,32); | |
6639 | } | |
6640 | else | |
6641 | { | |
6642 | LO = SIGNEXTEND((d1 / d2),32); | |
6643 | HI = SIGNEXTEND((d1 % d2),32); | |
6644 | } | |
6645 | } | |
6646 | } | |
6647 | } | |
6648 | ||
6649 | ||
6650 | 11101,xxx,yyy,11011:RR:16::DIVU | |
6651 | *mips16: | |
6652 | { | |
6653 | unsigned32 instruction = instruction_0; | |
6654 | t_reg op1 = (instruction >> 8) & 0x7; | |
6655 | t_reg op2 = (instruction >> 5) & 0x7; | |
6656 | if (op1 < 2) | |
6657 | op1 += 16; | |
6658 | op1 = GPR[op1]; | |
6659 | if (op2 < 2) | |
6660 | op2 += 16; | |
6661 | op2 = GPR[op2]; | |
6662 | if (have_extendval) | |
6663 | SignalException (ReservedInstruction, instruction); | |
6664 | { | |
6665 | CHECKHILO("Division"); | |
6666 | { | |
6667 | unsigned int d1 = op1; | |
6668 | unsigned int d2 = op2; | |
6669 | if (d2 == 0) | |
6670 | { | |
6671 | LO = SIGNEXTEND(0x80000000,32); | |
6672 | HI = SIGNEXTEND(0,32); | |
6673 | } | |
6674 | else if (d2 == -1 && d1 == 0x80000000) | |
6675 | { | |
6676 | LO = SIGNEXTEND(0x80000000,32); | |
6677 | HI = SIGNEXTEND(0,32); | |
6678 | } | |
6679 | else | |
6680 | { | |
6681 | LO = SIGNEXTEND((d1 / d2),32); | |
6682 | HI = SIGNEXTEND((d1 % d2),32); | |
6683 | } | |
6684 | } | |
6685 | } | |
6686 | } | |
6687 | ||
6688 | ||
6689 | 11101,ddd,00010000:RR:16::MFHI | |
6690 | *mips16: | |
6691 | { | |
6692 | unsigned32 instruction = instruction_0; | |
6693 | int destreg = (instruction >> 8) & 0x7; | |
6694 | if (destreg < 2) | |
6695 | destreg += 16; | |
6696 | if (have_extendval) | |
6697 | SignalException (ReservedInstruction, instruction); | |
6698 | { | |
6699 | GPR[destreg] = HI; | |
6700 | HIACCESS = 3; /* 3rd instruction will be safe */ | |
6701 | } | |
6702 | } | |
6703 | ||
6704 | ||
6705 | 11101,ddd,00010010:RR:16::MFLO | |
6706 | *mips16: | |
6707 | { | |
6708 | unsigned32 instruction = instruction_0; | |
6709 | int destreg = (instruction >> 8) & 0x7; | |
6710 | if (destreg < 2) | |
6711 | destreg += 16; | |
6712 | if (have_extendval) | |
6713 | SignalException (ReservedInstruction, instruction); | |
6714 | { | |
6715 | GPR[destreg] = LO; | |
6716 | LOACCESS = 3; /* 3rd instruction will be safe */ | |
6717 | } | |
6718 | } | |
6719 | ||
6720 | ||
6721 | 11101,xxx,yyy,11100:RR:16::DMULT | |
6722 | *mips16: | |
6723 | { | |
6724 | unsigned32 instruction = instruction_0; | |
6725 | t_reg op1 = (instruction >> 8) & 0x7; | |
6726 | t_reg op2 = (instruction >> 5) & 0x7; | |
6727 | if (op1 < 2) | |
6728 | op1 += 16; | |
6729 | op1 = GPR[op1]; | |
6730 | if (op2 < 2) | |
6731 | op2 += 16; | |
6732 | op2 = GPR[op2]; | |
6733 | if (have_extendval) | |
6734 | SignalException (ReservedInstruction, instruction); | |
6735 | { | |
6736 | CHECKHILO("Multiplication"); | |
6737 | { | |
6738 | unsigned64 mid; | |
6739 | unsigned64 midhi; | |
6740 | unsigned64 temp; | |
6741 | int sign = 0; | |
6742 | if (op1 < 0) { op1 = - op1; ++sign; } | |
6743 | if (op2 < 0) { op2 = - op2; ++sign; } | |
6744 | LO = ((unsigned64)VL4_8(op1) * VL4_8(op2)); | |
6745 | HI = ((unsigned64)VH4_8(op1) * VH4_8(op2)); | |
6746 | mid = ((unsigned64)VH4_8(op1) * VL4_8(op2)); | |
6747 | midhi = SET64HI(VL4_8(mid)); | |
6748 | temp = (LO + midhi); | |
6749 | if ((temp == midhi) ? (LO != 0) : (temp < midhi)) | |
6750 | HI += 1; | |
6751 | HI += VH4_8(mid); | |
6752 | mid = ((unsigned64)VL4_8(op1) * VH4_8(op2)); | |
6753 | midhi = SET64HI(VL4_8(mid)); | |
6754 | LO = (temp + midhi); | |
6755 | if ((LO == midhi) ? (temp != 0) : (LO < midhi)) | |
6756 | HI += 1; | |
6757 | HI += VH4_8(mid); | |
6758 | if (sign & 1) { LO = - LO; HI = (LO == 0 ? 0 : -1) - HI; } | |
6759 | } | |
6760 | } | |
6761 | } | |
6762 | ||
6763 | ||
6764 | 11101,xxx,yyy,11101:RR:16::DMULTU | |
6765 | *mips16: | |
6766 | { | |
6767 | unsigned32 instruction = instruction_0; | |
6768 | t_reg op1 = (instruction >> 8) & 0x7; | |
6769 | t_reg op2 = (instruction >> 5) & 0x7; | |
6770 | if (op1 < 2) | |
6771 | op1 += 16; | |
6772 | op1 = GPR[op1]; | |
6773 | if (op2 < 2) | |
6774 | op2 += 16; | |
6775 | op2 = GPR[op2]; | |
6776 | if (have_extendval) | |
6777 | SignalException (ReservedInstruction, instruction); | |
6778 | { | |
6779 | CHECKHILO("Multiplication"); | |
6780 | { | |
6781 | unsigned64 mid; | |
6782 | unsigned64 midhi; | |
6783 | unsigned64 temp; | |
6784 | LO = ((unsigned64)VL4_8(op1) * VL4_8(op2)); | |
6785 | HI = ((unsigned64)VH4_8(op1) * VH4_8(op2)); | |
6786 | mid = ((unsigned64)VH4_8(op1) * VL4_8(op2)); | |
6787 | midhi = SET64HI(VL4_8(mid)); | |
6788 | temp = (LO + midhi); | |
6789 | if ((temp == midhi) ? (LO != 0) : (temp < midhi)) | |
6790 | HI += 1; | |
6791 | HI += VH4_8(mid); | |
6792 | mid = ((unsigned64)VL4_8(op1) * VH4_8(op2)); | |
6793 | midhi = SET64HI(VL4_8(mid)); | |
6794 | LO = (temp + midhi); | |
6795 | if ((LO == midhi) ? (temp != 0) : (LO < midhi)) | |
6796 | HI += 1; | |
6797 | HI += VH4_8(mid); | |
6798 | } | |
6799 | } | |
6800 | } | |
6801 | ||
6802 | ||
6803 | 11101,xxx,yyy,11110:RR:16::DDIV | |
6804 | *mips16: | |
6805 | { | |
6806 | unsigned32 instruction = instruction_0; | |
6807 | t_reg op1 = (instruction >> 8) & 0x7; | |
6808 | t_reg op2 = (instruction >> 5) & 0x7; | |
6809 | if (op1 < 2) | |
6810 | op1 += 16; | |
6811 | op1 = GPR[op1]; | |
6812 | if (op2 < 2) | |
6813 | op2 += 16; | |
6814 | op2 = GPR[op2]; | |
6815 | if (have_extendval) | |
6816 | SignalException (ReservedInstruction, instruction); | |
6817 | { | |
6818 | CHECKHILO("Division"); | |
6819 | { | |
6820 | word64 d1 = op1; | |
6821 | word64 d2 = op2; | |
6822 | if (d2 == 0) | |
6823 | { | |
6824 | LO = SIGNED64 (0x8000000000000000); | |
6825 | HI = 0; | |
6826 | } | |
6827 | else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000)) | |
6828 | { | |
6829 | LO = SIGNED64 (0x8000000000000000); | |
6830 | HI = 0; | |
6831 | } | |
6832 | else | |
6833 | { | |
6834 | LO = (d1 / d2); | |
6835 | HI = (d1 % d2); | |
6836 | } | |
6837 | } | |
6838 | } | |
6839 | } | |
6840 | ||
6841 | ||
6842 | 11101,xxx,yyy,11111:RR:16::DDIVU | |
6843 | *mips16: | |
6844 | { | |
6845 | unsigned32 instruction = instruction_0; | |
6846 | t_reg op1 = (instruction >> 8) & 0x7; | |
6847 | t_reg op2 = (instruction >> 5) & 0x7; | |
6848 | if (op1 < 2) | |
6849 | op1 += 16; | |
6850 | op1 = GPR[op1]; | |
6851 | if (op2 < 2) | |
6852 | op2 += 16; | |
6853 | op2 = GPR[op2]; | |
6854 | if (have_extendval) | |
6855 | SignalException (ReservedInstruction, instruction); | |
6856 | { | |
6857 | CHECKHILO("Division"); | |
6858 | { | |
6859 | unsigned64 d1 = op1; | |
6860 | unsigned64 d2 = op2; | |
6861 | if (d2 == 0) | |
6862 | { | |
6863 | LO = SIGNED64 (0x8000000000000000); | |
6864 | HI = 0; | |
6865 | } | |
6866 | else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000)) | |
6867 | { | |
6868 | LO = SIGNED64 (0x8000000000000000); | |
6869 | HI = 0; | |
6870 | } | |
6871 | else | |
6872 | { | |
6873 | LO = (d1 / d2); | |
6874 | HI = (d1 % d2); | |
6875 | } | |
6876 | } | |
6877 | } | |
6878 | } | |
6879 | ||
6880 | ||
6881 | // Jump and Branch Instructions | |
6882 | ||
6883 | ||
6884 | // JALX | |
6885 | // JAL | |
6886 | 00011,aaaaaaaaaaa:I:16::JAL | |
6887 | *mips16: | |
6888 | { | |
6889 | unsigned32 instruction = instruction_0; | |
6890 | ut_reg op1 = (instruction >> 0) & 0x7ff; | |
6891 | { | |
6892 | unsigned64 paddr; | |
6893 | int uncached; | |
6894 | if (AddressTranslation (PC &~ (unsigned64) 1, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL)) | |
6895 | { | |
6896 | unsigned64 memval; | |
6897 | unsigned int reverse = (ReverseEndian ? 3 : 0); | |
6898 | unsigned int bigend = (BigEndianCPU ? 3 : 0); | |
6899 | unsigned int byte; | |
6900 | paddr = ((paddr & ~0x7) | ((paddr & 0x7) ^ (reverse << 1))); | |
6901 | LoadMemory (&memval,0,uncached, AccessLength_HALFWORD, paddr, PC, isINSTRUCTION, isREAL); | |
6902 | byte = (((PC &~ (unsigned64) 1) & 0x7) ^ (bigend << 1)); | |
6903 | memval = (memval >> (8 * byte)) & 0xffff; | |
6904 | op1 = (((op1 & 0x1f) << 23) | |
6905 | | ((op1 & 0x3e0) << 13) | |
6906 | | (memval << 2)); | |
6907 | if ((instruction & 0x400) == 0) | |
6908 | op1 |= 1; | |
6909 | PC += 2; | |
6910 | } | |
6911 | } | |
6912 | op1 |= PC & ~ (unsigned64) 0x0fffffff; | |
6913 | if (have_extendval) | |
6914 | SignalException (ReservedInstruction, instruction); | |
6915 | { | |
6916 | int destreg = 31; | |
6917 | GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */ | |
6918 | /* NOTE: ??? Gdb gets confused if the PC is sign-extended, | |
6919 | so we just truncate it to 32 bits here. */ | |
6920 | op1 = VL4_8(op1); | |
6921 | /* NOTE: The jump occurs AFTER the next instruction has been executed */ | |
6922 | DSPC = op1; | |
6923 | JALDELAYSLOT(); | |
6924 | } | |
6925 | } | |
6926 | ||
6927 | ||
6928 | 11101,xxx,00000000:RR:16::JR | |
6929 | *mips16: | |
6930 | { | |
6931 | unsigned32 instruction = instruction_0; | |
6932 | t_reg op1 = (instruction >> 8) & 0x7; | |
6933 | if (op1 < 2) | |
6934 | op1 += 16; | |
6935 | op1 = GPR[op1]; | |
6936 | if (have_extendval) | |
6937 | SignalException (ReservedInstruction, instruction); | |
6938 | { | |
6939 | /* NOTE: ??? Gdb gets confused if the PC is sign-extended, | |
6940 | so we just truncate it to 32 bits here. */ | |
6941 | op1 = VL4_8(op1); | |
6942 | /* NOTE: The jump occurs AFTER the next instruction has been executed */ | |
6943 | DSPC = op1; | |
6944 | DELAYSLOT(); | |
6945 | } | |
6946 | } | |
6947 | ||
6948 | ||
6949 | 1110100000100000,r:RR:16::JRRA | |
6950 | *mips16: | |
6951 | { | |
6952 | unsigned32 instruction = instruction_0; | |
6953 | t_reg op1 = 31; | |
6954 | op1 = GPR[op1]; | |
6955 | if (have_extendval) | |
6956 | SignalException (ReservedInstruction, instruction); | |
6957 | { | |
6958 | /* NOTE: ??? Gdb gets confused if the PC is sign-extended, | |
6959 | so we just truncate it to 32 bits here. */ | |
6960 | op1 = VL4_8(op1); | |
6961 | /* NOTE: The jump occurs AFTER the next instruction has been executed */ | |
6962 | DSPC = op1; | |
6963 | DELAYSLOT(); | |
6964 | } | |
6965 | } | |
6966 | ||
6967 | ||
6968 | 11101,xxx,01000000,R:RR:16::JALR | |
6969 | *mips16: | |
6970 | { | |
6971 | unsigned32 instruction = instruction_0; | |
6972 | t_reg op1 = (instruction >> 8) & 0x7; | |
6973 | int destreg = 31; | |
6974 | if (op1 < 2) | |
6975 | op1 += 16; | |
6976 | op1 = GPR[op1]; | |
6977 | if (have_extendval) | |
6978 | SignalException (ReservedInstruction, instruction); | |
6979 | { | |
6980 | GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */ | |
6981 | /* NOTE: ??? Gdb gets confused if the PC is sign-extended, | |
6982 | so we just truncate it to 32 bits here. */ | |
6983 | op1 = VL4_8(op1); | |
6984 | /* NOTE: The jump occurs AFTER the next instruction has been executed */ | |
6985 | DSPC = op1; | |
6986 | DELAYSLOT(); | |
6987 | } | |
6988 | } | |
6989 | ||
6990 | ||
6991 | 00100,xxx,pppppppp,z:RI:16::BEQZ | |
6992 | *mips16: | |
6993 | { | |
6994 | unsigned32 instruction = instruction_0; | |
6995 | t_reg op1 = (instruction >> 8) & 0x7; | |
6996 | int offset = (instruction >> 0) & 0xff; | |
6997 | t_reg op2 = 0; | |
6998 | if (op1 < 2) | |
6999 | op1 += 16; | |
7000 | op1 = GPR[op1]; | |
7001 | if (have_extendval) | |
7002 | { | |
7003 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
7004 | if (offset >= 0x8000) | |
7005 | offset -= 0x10000; | |
7006 | have_extendval = 0; | |
7007 | } | |
7008 | else | |
7009 | { | |
7010 | if (offset >= 0x80) | |
7011 | offset -= 0x100; | |
7012 | } | |
7013 | offset *= 2; | |
7014 | if (have_extendval) | |
7015 | SignalException (ReservedInstruction, instruction); | |
7016 | { | |
7017 | int condition = (op1 == op2); | |
7018 | if (condition) | |
7019 | PC = PC + offset; | |
7020 | } | |
7021 | } | |
7022 | ||
7023 | ||
7024 | 00101,xxx,pppppppp,z:RI:16::BNEZ | |
7025 | *mips16: | |
7026 | { | |
7027 | unsigned32 instruction = instruction_0; | |
7028 | t_reg op1 = (instruction >> 8) & 0x7; | |
7029 | int offset = (instruction >> 0) & 0xff; | |
7030 | t_reg op2 = 0; | |
7031 | if (op1 < 2) | |
7032 | op1 += 16; | |
7033 | op1 = GPR[op1]; | |
7034 | if (have_extendval) | |
7035 | { | |
7036 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
7037 | if (offset >= 0x8000) | |
7038 | offset -= 0x10000; | |
7039 | have_extendval = 0; | |
7040 | } | |
7041 | else | |
7042 | { | |
7043 | if (offset >= 0x80) | |
7044 | offset -= 0x100; | |
7045 | } | |
7046 | offset *= 2; | |
7047 | if (have_extendval) | |
7048 | SignalException (ReservedInstruction, instruction); | |
7049 | { | |
7050 | int condition = (op1 != op2); | |
7051 | if (condition) | |
7052 | PC = PC + offset; | |
7053 | } | |
7054 | } | |
7055 | ||
7056 | ||
7057 | 01100000,pppppppp,t,z:I8:16::BTEQZ | |
7058 | *mips16: | |
7059 | { | |
7060 | unsigned32 instruction = instruction_0; | |
7061 | int offset = (instruction >> 0) & 0xff; | |
7062 | t_reg op1 = 24; | |
7063 | t_reg op2 = 0; | |
7064 | if (have_extendval) | |
7065 | { | |
7066 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
7067 | if (offset >= 0x8000) | |
7068 | offset -= 0x10000; | |
7069 | have_extendval = 0; | |
7070 | } | |
7071 | else | |
7072 | { | |
7073 | if (offset >= 0x80) | |
7074 | offset -= 0x100; | |
7075 | } | |
7076 | offset *= 2; | |
7077 | op1 = GPR[op1]; | |
7078 | if (have_extendval) | |
7079 | SignalException (ReservedInstruction, instruction); | |
7080 | { | |
7081 | int condition = (op1 == op2); | |
7082 | if (condition) | |
7083 | PC = PC + offset; | |
7084 | } | |
7085 | } | |
7086 | ||
7087 | ||
7088 | 01100001,pppppppp,t,z:I8:16::BTNEZ | |
7089 | *mips16: | |
7090 | { | |
7091 | unsigned32 instruction = instruction_0; | |
7092 | int offset = (instruction >> 0) & 0xff; | |
7093 | t_reg op1 = 24; | |
7094 | t_reg op2 = 0; | |
7095 | if (have_extendval) | |
7096 | { | |
7097 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
7098 | if (offset >= 0x8000) | |
7099 | offset -= 0x10000; | |
7100 | have_extendval = 0; | |
7101 | } | |
7102 | else | |
7103 | { | |
7104 | if (offset >= 0x80) | |
7105 | offset -= 0x100; | |
7106 | } | |
7107 | offset *= 2; | |
7108 | op1 = GPR[op1]; | |
7109 | if (have_extendval) | |
7110 | SignalException (ReservedInstruction, instruction); | |
7111 | { | |
7112 | int condition = (op1 != op2); | |
7113 | if (condition) | |
7114 | PC = PC + offset; | |
7115 | } | |
7116 | } | |
7117 | ||
7118 | ||
7119 | 00010,qqqqqqqqqqq,z,Z:I:16::B | |
7120 | *mips16: | |
7121 | { | |
7122 | unsigned32 instruction = instruction_0; | |
7123 | int offset = (instruction >> 0) & 0x7ff; | |
7124 | t_reg op2 = 0; | |
7125 | t_reg op1 = 0; | |
7126 | if (have_extendval) | |
7127 | { | |
7128 | offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0); | |
7129 | if (offset >= 0x8000) | |
7130 | offset -= 0x10000; | |
7131 | have_extendval = 0; | |
7132 | } | |
7133 | else | |
7134 | { | |
7135 | if (offset >= 0x400) | |
7136 | offset -= 0x800; | |
7137 | } | |
7138 | offset *= 2; | |
7139 | if (have_extendval) | |
7140 | SignalException (ReservedInstruction, instruction); | |
7141 | { | |
7142 | int condition = (op1 == op2); | |
7143 | if (condition) | |
7144 | PC = PC + offset; | |
7145 | } | |
7146 | } | |
7147 | ||
7148 | ||
7149 | // Special Instructions | |
7150 | ||
7151 | ||
7152 | // See the front of the mips16 doc | |
7153 | 11110,eeeeeeeeeee:I:16::EXTEND | |
7154 | *mips16: | |
7155 | { | |
7156 | unsigned32 instruction = instruction_0; | |
7157 | int ext = (instruction >> 0) & 0x7ff; | |
7158 | if (have_extendval) | |
7159 | SignalException (ReservedInstruction, instruction); | |
7160 | { | |
7161 | extendval = ext; | |
7162 | have_extendval = 1; | |
7163 | } | |
7164 | } | |
7165 | ||
7166 | ||
7167 | 01100,******,00101:RR:16::BREAK | |
7168 | *mips16: | |
7169 | { | |
7170 | unsigned32 instruction = instruction_0; | |
7171 | if (have_extendval) | |
7172 | SignalException (ReservedInstruction, instruction); | |
7173 | { | |
7174 | SignalException(BreakPoint,instruction); | |
7175 | } | |
7176 | } | |
7177 | ||
7178 | \f | |
7179 | // start-sanitize-r5900 | |
7180 | ||
7181 | // FIXME: The instructions below which are typically r5900 specific | |
7182 | // need to be merged back into the above. | |
7183 | ||
7184 | // end-sanitize-r5900 | |
7185 | // start-sanitize-r5900 | |
7186 | ||
7187 | 011100,5.RS,5.RT,0000000000011010:MMINORM:32::DIV1 | |
7188 | *r5900: | |
7189 | { | |
7190 | unsigned32 instruction = instruction_0; | |
7191 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7192 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7193 | { | |
7194 | CHECKHILO("Division"); | |
7195 | { | |
7196 | int d1 = op1; | |
7197 | int d2 = op2; | |
7198 | if (d2 == 0) | |
7199 | { | |
7200 | LO1 = SIGNEXTEND(0x80000000,32); | |
7201 | HI1 = SIGNEXTEND(0,32); | |
7202 | } | |
7203 | else if (d2 == -1 && d1 == 0x80000000) | |
7204 | { | |
7205 | LO1 = SIGNEXTEND(0x80000000,32); | |
7206 | HI1 = SIGNEXTEND(0,32); | |
7207 | } | |
7208 | else | |
7209 | { | |
7210 | LO1 = SIGNEXTEND((d1 / d2),32); | |
7211 | HI1 = SIGNEXTEND((d1 % d2),32); | |
7212 | } | |
7213 | } | |
7214 | } | |
7215 | } | |
7216 | ||
7217 | // end-sanitize-r5900 | |
7218 | // start-sanitize-r5900 | |
7219 | ||
7220 | 011100,5.RS,5.RT,0000000000011011:MMINORM:32::DIVU1 | |
7221 | *r5900: | |
7222 | { | |
7223 | unsigned32 instruction = instruction_0; | |
7224 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7225 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7226 | { | |
7227 | CHECKHILO("Division"); | |
7228 | { | |
7229 | unsigned int d1 = op1; | |
7230 | unsigned int d2 = op2; | |
7231 | if (d2 == 0) | |
7232 | { | |
7233 | LO1 = SIGNEXTEND(0x80000000,32); | |
7234 | HI1 = SIGNEXTEND(0,32); | |
7235 | } | |
7236 | else if (d2 == -1 && d1 == 0x80000000) | |
7237 | { | |
7238 | LO1 = SIGNEXTEND(0x80000000,32); | |
7239 | HI1 = SIGNEXTEND(0,32); | |
7240 | } | |
7241 | else | |
7242 | { | |
7243 | LO1 = SIGNEXTEND((d1 / d2),32); | |
7244 | HI1 = SIGNEXTEND((d1 % d2),32); | |
7245 | } | |
7246 | } | |
7247 | } | |
7248 | } | |
7249 | ||
7250 | // end-sanitize-r5900 | |
7251 | ||
f2b30012 | 7252 | 011101,26.INSTR_INDEX:NORMAL:32::JALX |
f2b30012 AC |
7253 | // start-sanitize-r5900 |
7254 | *r5900: | |
7255 | // end-sanitize-r5900 | |
7256 | *r3900: | |
7257 | // start-sanitize-tx19 | |
7258 | *tx19: | |
7259 | // end-sanitize-tx19 | |
7260 | { | |
7261 | unsigned32 instruction = instruction_0; | |
7262 | ut_reg op1 UNUSED = (((instruction >> 0) & 0x03FFFFFF) << 2); | |
7263 | op1 |= (PC & ~0x0FFFFFFF); /* address of instruction in delay slot for the jump */ | |
7264 | { | |
7265 | int destreg = 31; | |
7266 | GPR[destreg] = (PC + 4); /* NOTE: The PC is already 4 ahead within the simulator */ | |
7267 | op1 ^= 1; | |
7268 | /* NOTE: ??? Gdb gets confused if the PC is sign-extended, | |
7269 | so we just truncate it to 32 bits here. */ | |
7270 | op1 = VL4_8(op1); | |
7271 | /* NOTE: The jump occurs AFTER the next instruction has been executed */ | |
7272 | DSPC = op1; | |
7273 | JALDELAYSLOT(); | |
7274 | } | |
7275 | } | |
7276 | ||
7277 | // start-sanitize-r5900 | |
7278 | ||
7279 | 011110,5.RS,5.RT,16.OFFSET:NORMAL:128::LQ | |
7280 | *r5900: | |
7281 | { | |
7282 | unsigned32 instruction = instruction_0; | |
7283 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
7284 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
7285 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7286 | { | |
7287 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
7288 | unsigned64 paddr; | |
7289 | int uncached; | |
7290 | if ((vaddr & 15) != 0) | |
7291 | SignalException(AddressLoad); | |
7292 | else | |
7293 | { | |
7294 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
7295 | { | |
7296 | unsigned64 memval = 0; | |
7297 | unsigned64 memval1 = 0; | |
7298 | unsigned64 mask = 0x7; | |
7299 | unsigned int shift = 8; | |
7300 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
7301 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
7302 | unsigned int byte UNUSED; | |
7303 | LoadMemory(&memval,&memval1,uncached,AccessLength_QUADWORD,paddr,vaddr,isDATA,isREAL); | |
7304 | GPR[destreg] = memval; | |
7305 | GPR1[destreg] = memval1; | |
7306 | } | |
7307 | } | |
7308 | } | |
7309 | } | |
7310 | ||
7311 | // end-sanitize-r5900 | |
7312 | // start-sanitize-r5900 | |
7313 | ||
7314 | 011100,5.RS,5.RT,5.RD,00000000000:MMINORM:32::MADD | |
7315 | *r5900: | |
7316 | *r3900: | |
7317 | { | |
7318 | unsigned32 instruction = instruction_0; | |
7319 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7320 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7321 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7322 | { | |
7323 | word64 prod = (word64)WORD64(VL4_8(HI),VL4_8(LO)) + ((word64)SIGNEXTEND(op1,32) * (word64)SIGNEXTEND(op2,32)); | |
7324 | LO = SIGNEXTEND(prod,32); | |
7325 | HI = SIGNEXTEND( VH4_8(prod), 32); | |
7326 | if( destreg != 0 ) GPR[destreg] = LO; | |
7327 | } | |
7328 | } | |
7329 | ||
7330 | // end-sanitize-r5900 | |
7331 | // start-sanitize-r5900 | |
7332 | ||
7333 | 011100,5.RS,5.RT,5.RD,00000000001:MMINORM:32::MADDU | |
7334 | *r5900: | |
7335 | *r3900: | |
7336 | { | |
7337 | unsigned32 instruction = instruction_0; | |
7338 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7339 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7340 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7341 | { | |
7342 | unsigned64 prod = (unsigned64)WORD64(VL4_8(HI),VL4_8(LO)) + ((unsigned64)VL4_8(op1) * (unsigned64)VL4_8(op2)); | |
7343 | LO = SIGNEXTEND(prod,32); | |
7344 | HI = SIGNEXTEND( VH4_8(prod), 32); | |
7345 | if( destreg != 0 ) GPR[destreg] = LO; | |
7346 | } | |
7347 | } | |
7348 | ||
7349 | // end-sanitize-r5900 | |
7350 | // start-sanitize-r5900 | |
7351 | ||
7352 | 011100,5.RS,5.RT,5.RD,00000100000:MMINORM:32::MADD1 | |
7353 | *r5900: | |
7354 | { | |
7355 | unsigned32 instruction = instruction_0; | |
7356 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7357 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7358 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7359 | { | |
7360 | word64 prod = (word64)WORD64(VL4_8(HI1),VL4_8(LO1)) + ((word64)SIGNEXTEND(op1,32) * (word64)SIGNEXTEND(op2,32)); | |
7361 | LO1 = SIGNEXTEND(prod,32); | |
7362 | HI1 = SIGNEXTEND( VH4_8(prod), 32); | |
7363 | if( destreg != 0 ) GPR[destreg] = LO1; | |
7364 | } | |
7365 | } | |
7366 | ||
7367 | // end-sanitize-r5900 | |
7368 | // start-sanitize-r5900 | |
7369 | ||
7370 | 011100,5.RS,5.RT,5.RD,00000100001:MMINORM:32::MADDU1 | |
7371 | *r5900: | |
7372 | { | |
7373 | unsigned32 instruction = instruction_0; | |
7374 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7375 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7376 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7377 | { | |
7378 | unsigned64 prod = (unsigned64)WORD64(VL4_8(HI1),VL4_8(LO1)) + ((unsigned64)VL4_8(op1) * (unsigned64)VL4_8(op2)); | |
7379 | LO1 = SIGNEXTEND(prod,32); | |
7380 | HI1 = SIGNEXTEND( VH4_8(prod), 32); | |
7381 | if( destreg != 0 ) GPR[destreg] = LO1; | |
7382 | } | |
7383 | } | |
7384 | ||
7385 | // end-sanitize-r5900 | |
f2b30012 AC |
7386 | // start-sanitize-r5900 |
7387 | ||
7388 | 0111000000000000,5.RD,00000010000:MMINORM:32::MFHI1 | |
7389 | *r5900: | |
7390 | { | |
7391 | unsigned32 instruction = instruction_0; | |
7392 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7393 | { | |
7394 | GPR[destreg] = HI1; | |
7395 | HI1ACCESS = 3; /* 3rd instruction will be safe */ | |
7396 | } | |
7397 | } | |
7398 | ||
7399 | // end-sanitize-r5900 | |
7400 | // start-sanitize-r5900 | |
7401 | ||
7402 | 0111000000000000,5.RD,00000010010:MMINORM:32::MFLO1 | |
7403 | *r5900: | |
7404 | { | |
7405 | unsigned32 instruction = instruction_0; | |
7406 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7407 | { | |
7408 | GPR[destreg] = LO1; | |
7409 | LO1ACCESS = 3; /* 3rd instruction will be safe */ | |
7410 | } | |
7411 | } | |
7412 | ||
7413 | // end-sanitize-r5900 | |
7414 | // start-sanitize-r5900 | |
7415 | ||
7416 | 0000000000000000,5.RD,00000101000:SPECIAL:32::MFSA | |
7417 | *r5900: | |
7418 | { | |
7419 | unsigned32 instruction = instruction_0; | |
7420 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7421 | { | |
7422 | GPR[destreg] = SA; | |
7423 | } | |
7424 | } | |
7425 | ||
7426 | // end-sanitize-r5900 | |
7427 | // start-sanitize-r5900 | |
7428 | ||
7429 | 011100,5.RS,000000000000000010001:MMINORM:32::MTHI1 | |
7430 | *r5900: | |
7431 | { | |
7432 | unsigned32 instruction = instruction_0; | |
7433 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7434 | { | |
7435 | if (HI1ACCESS != 0) | |
7436 | sim_warning("MT (move-to) over-writing HI register value"); | |
7437 | HI1 = op1; | |
7438 | HI1ACCESS = 3; /* 3rd instruction will be safe */ | |
7439 | } | |
7440 | } | |
7441 | ||
7442 | // end-sanitize-r5900 | |
7443 | // start-sanitize-r5900 | |
7444 | ||
7445 | 011100,5.RS,000000000000000010011:MMINORM:32::MTLO1 | |
7446 | *r5900: | |
7447 | { | |
7448 | unsigned32 instruction = instruction_0; | |
7449 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7450 | { | |
7451 | if (LO1ACCESS != 0) | |
7452 | sim_warning("MT (move-to) over-writing LO register value"); | |
7453 | LO1 = op1; | |
7454 | LO1ACCESS = 3; /* 3rd instruction will be safe */ | |
7455 | } | |
7456 | } | |
7457 | ||
7458 | // end-sanitize-r5900 | |
7459 | // start-sanitize-r5900 | |
7460 | ||
7461 | 000000,5.RS,000000000000000101001:SPECIAL:32::MTSA | |
7462 | *r5900: | |
7463 | { | |
7464 | unsigned32 instruction = instruction_0; | |
7465 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7466 | { | |
7467 | SA = op1; | |
7468 | } | |
7469 | } | |
7470 | ||
7471 | // end-sanitize-r5900 | |
7472 | // start-sanitize-r5900 | |
7473 | ||
7474 | 000001,5.RS,11000,16.IMMEDIATE:REGIMM:32::MTSAB | |
7475 | *r5900: | |
7476 | { | |
7477 | unsigned32 instruction = instruction_0; | |
7478 | t_reg op2 UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
7479 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7480 | { | |
7481 | SA = ((op1 & 0xF) ^ (op2 & 0xF)) * 8; | |
7482 | } | |
7483 | } | |
7484 | ||
7485 | // end-sanitize-r5900 | |
7486 | // start-sanitize-r5900 | |
7487 | ||
7488 | 000001,5.RS,11001,16.IMMEDIATE:REGIMM:32::MTSAH | |
7489 | *r5900: | |
7490 | { | |
7491 | unsigned32 instruction = instruction_0; | |
7492 | t_reg op2 UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
7493 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7494 | { | |
7495 | SA = ((op1 & 0x7) ^ (op2 & 0x7)) * 16; | |
7496 | } | |
7497 | } | |
7498 | ||
7499 | // end-sanitize-r5900 | |
7500 | // start-sanitize-r5900 | |
7501 | ||
7502 | 011100,5.RS,5.RT,5.RD,00000011000:MMINORM:32::MULT1 | |
7503 | *r5900: | |
7504 | { | |
7505 | unsigned32 instruction = instruction_0; | |
7506 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7507 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7508 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7509 | { | |
7510 | CHECKHILO("Multiplication"); | |
7511 | { | |
7512 | unsigned64 temp = ((word64) op1 * (word64) op2); | |
7513 | LO1 = SIGNEXTEND((unsigned64)VL4_8(temp),32); | |
7514 | HI1 = SIGNEXTEND((unsigned64)VH4_8(temp),32); | |
7515 | if ( destreg != 0 ) | |
7516 | GPR[destreg] = LO1; | |
7517 | } | |
7518 | } | |
7519 | } | |
7520 | ||
7521 | // end-sanitize-r5900 | |
7522 | // start-sanitize-r5900 | |
7523 | ||
7524 | 011100,5.RS,5.RT,5.RD,00000011001:MMINORM:32::MULTU1 | |
7525 | *r5900: | |
7526 | { | |
7527 | unsigned32 instruction = instruction_0; | |
7528 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7529 | t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7530 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7531 | { | |
7532 | CHECKHILO("Multiplication"); | |
7533 | { | |
7534 | unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff)); | |
7535 | LO1 = SIGNEXTEND((unsigned64)VL4_8(temp),32); | |
7536 | HI1 = SIGNEXTEND((unsigned64)VH4_8(temp),32); | |
7537 | if ( destreg != 0 ) | |
7538 | GPR[destreg] = LO1; | |
7539 | } | |
7540 | } | |
7541 | } | |
7542 | ||
7543 | // end-sanitize-r5900 | |
7544 | // start-sanitize-r5900 | |
7545 | ||
7546 | 01110000000,5.RT,5.RD,00101101000:MMI1:32::PABSH | |
7547 | *r5900: | |
7548 | { | |
7549 | unsigned32 instruction = instruction_0; | |
7550 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7551 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7552 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7553 | { | |
7554 | int i; | |
7555 | for(i=0;i<HALFWORDS_IN_MMI_REGS;i++) | |
7556 | { | |
7557 | if (RT_SH(i) >= 0) | |
7558 | GPR_SH(destreg,i) = RT_SH(i); | |
7559 | else if (RT_SH(i) == -32768) | |
7560 | GPR_SH(destreg,i) = 32767; | |
7561 | else | |
7562 | GPR_SH(destreg,i) = -RT_SH(i); | |
7563 | } | |
7564 | } | |
7565 | } | |
7566 | ||
7567 | // end-sanitize-r5900 | |
7568 | // start-sanitize-r5900 | |
7569 | ||
7570 | 01110000000,5.RT,5.RD,00001101000:MMI1:32::PABSW | |
7571 | *r5900: | |
7572 | { | |
7573 | unsigned32 instruction = instruction_0; | |
7574 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7575 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7576 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7577 | { | |
7578 | int i; | |
7579 | for(i=0;i<WORDS_IN_MMI_REGS;i++) | |
7580 | { | |
7581 | if (RT_SW(i) >= 0) | |
7582 | GPR_SW(destreg,i) = RT_SW(i); | |
7583 | else if (RT_SW(i) == (int)0x80000000) | |
7584 | GPR_SW(destreg,i) = (int)0x7FFFFFFF; | |
7585 | else | |
7586 | GPR_SW(destreg,i) = -RT_SW(i); | |
7587 | } | |
7588 | } | |
7589 | } | |
7590 | ||
7591 | // end-sanitize-r5900 | |
7592 | // start-sanitize-r5900 | |
7593 | ||
7594 | 011100,5.RS,5.RT,5.RD,01000001000:MMI0:32::PADDB | |
7595 | *r5900: | |
7596 | { | |
7597 | unsigned32 instruction = instruction_0; | |
7598 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7599 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7600 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7601 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7602 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7603 | { | |
7604 | int i; | |
7605 | for (i=0; i < BYTES_IN_MMI_REGS; i++) | |
7606 | { | |
7607 | int s = RS_SB(i); | |
7608 | int t = RT_SB(i); | |
7609 | int r = s + t; | |
7610 | GPR_SB(destreg,i) = r; | |
7611 | } | |
7612 | } | |
7613 | } | |
7614 | ||
7615 | // end-sanitize-r5900 | |
7616 | // start-sanitize-r5900 | |
7617 | ||
7618 | 011100,5.RS,5.RT,5.RD,00100001000:MMI0:32::PADDH | |
7619 | *r5900: | |
7620 | { | |
7621 | unsigned32 instruction = instruction_0; | |
7622 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7623 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7624 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7625 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7626 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7627 | { | |
7628 | int i; | |
7629 | for (i=0; i < HALFWORDS_IN_MMI_REGS; i++) | |
7630 | { | |
7631 | int s = RS_SH(i); | |
7632 | int t = RT_SH(i); | |
7633 | int r = s + t; | |
7634 | GPR_SH(destreg,i) = r; | |
7635 | } | |
7636 | } | |
7637 | } | |
7638 | ||
7639 | // end-sanitize-r5900 | |
7640 | // start-sanitize-r5900 | |
7641 | ||
7642 | 011100,5.RS,5.RT,5.RD,00000001000:MMI0:32::PADDW | |
7643 | *r5900: | |
7644 | { | |
7645 | unsigned32 instruction = instruction_0; | |
7646 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7647 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7648 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7649 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7650 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7651 | { | |
7652 | int i; | |
7653 | for (i=0; i < WORDS_IN_MMI_REGS; i++) | |
7654 | { | |
7655 | signed64 s = RS_SW(i); | |
7656 | signed64 t = RT_SW(i); | |
7657 | signed64 r = s + t; | |
7658 | GPR_SW(destreg,i) = r; | |
7659 | } | |
7660 | } | |
7661 | } | |
7662 | ||
7663 | // end-sanitize-r5900 | |
7664 | // start-sanitize-r5900 | |
7665 | ||
7666 | 011100,5.RS,5.RT,5.RD,11000001000:MMI0:32::PADDSB | |
7667 | *r5900: | |
7668 | { | |
7669 | unsigned32 instruction = instruction_0; | |
7670 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7671 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7672 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7673 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7674 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7675 | { | |
7676 | int i; | |
7677 | for (i=0; i < BYTES_IN_MMI_REGS; i++) | |
7678 | { | |
7679 | int s = RS_SB(i); | |
7680 | int t = RT_SB(i); | |
7681 | int r = s + t; | |
7682 | if (r > 127) | |
7683 | GPR_SB(destreg,i) = 127; | |
7684 | else if (r < -128) | |
7685 | GPR_SB(destreg,i) = -128; | |
7686 | else | |
7687 | GPR_SB(destreg,i) = r; | |
7688 | } | |
7689 | } | |
7690 | } | |
7691 | ||
7692 | // end-sanitize-r5900 | |
7693 | // start-sanitize-r5900 | |
7694 | ||
7695 | 011100,5.RS,5.RT,5.RD,10100001000:MMI0:32::PADDSH | |
7696 | *r5900: | |
7697 | { | |
7698 | unsigned32 instruction = instruction_0; | |
7699 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7700 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7701 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7702 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7703 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7704 | { | |
7705 | int i; | |
7706 | for (i=0; i < HALFWORDS_IN_MMI_REGS; i++) | |
7707 | { | |
7708 | int s = RS_SH(i); | |
7709 | int t = RT_SH(i); | |
7710 | int r = s + t; | |
7711 | if (r > 32767) | |
7712 | GPR_SH(destreg,i) = 32767; | |
7713 | else if (r < -32768) | |
7714 | GPR_SH(destreg,i) = -32768; | |
7715 | else | |
7716 | GPR_SH(destreg,i) = r; | |
7717 | } | |
7718 | } | |
7719 | } | |
7720 | ||
7721 | // end-sanitize-r5900 | |
7722 | // start-sanitize-r5900 | |
7723 | ||
7724 | 011100,5.RS,5.RT,5.RD,10000001000:MMI0:32::PADDSW | |
7725 | *r5900: | |
7726 | { | |
7727 | unsigned32 instruction = instruction_0; | |
7728 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7729 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7730 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7731 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7732 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7733 | { | |
7734 | int i; | |
7735 | for (i=0; i < WORDS_IN_MMI_REGS; i++) | |
7736 | { | |
7737 | signed64 s = RS_SW(i); | |
7738 | signed64 t = RT_SW(i); | |
7739 | signed64 r = s + t; | |
7740 | if (r > (int)0x7FFFFFFF) | |
7741 | GPR_SW(destreg,i) = (int)0x7FFFFFFF; | |
7742 | else if (r < (int)0x80000000) | |
7743 | GPR_SW(destreg,i) = (int)0x80000000; | |
7744 | else | |
7745 | GPR_SW(destreg,i) = r; | |
7746 | } | |
7747 | } | |
7748 | } | |
7749 | ||
7750 | // end-sanitize-r5900 | |
7751 | // start-sanitize-r5900 | |
7752 | ||
7753 | 011100,5.RS,5.RT,5.RD,11000101000:MMI1:32::PADDUB | |
7754 | *r5900: | |
7755 | { | |
7756 | unsigned32 instruction = instruction_0; | |
7757 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7758 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7759 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7760 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7761 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7762 | { | |
7763 | int i; | |
7764 | for (i=0; i < BYTES_IN_MMI_REGS; i++) | |
7765 | { | |
7766 | unsigned int s = RS_UB(i); | |
7767 | unsigned int t = RT_UB(i); | |
7768 | unsigned int r = s + t; | |
7769 | if (r > 0xFF) | |
7770 | GPR_UB(destreg,i) = 0xFF; | |
7771 | else | |
7772 | GPR_UB(destreg,i) = r; | |
7773 | } | |
7774 | } | |
7775 | } | |
7776 | ||
7777 | // end-sanitize-r5900 | |
7778 | // start-sanitize-r5900 | |
7779 | ||
7780 | 011100,5.RS,5.RT,5.RD,10100101000:MMI1:32::PADDUH | |
7781 | *r5900: | |
7782 | { | |
7783 | unsigned32 instruction = instruction_0; | |
7784 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7785 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7786 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7787 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7788 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7789 | { | |
7790 | int i; | |
7791 | for (i=0; i < HALFWORDS_IN_MMI_REGS; i++) | |
7792 | { | |
7793 | unsigned int s = RS_UH(i); | |
7794 | unsigned int t = RT_UH(i); | |
7795 | unsigned int r = s + t; | |
7796 | if (r > 0xFFFF) | |
7797 | GPR_UH(destreg,i) = 0xFFFF; | |
7798 | else | |
7799 | GPR_UH(destreg,i) = r; | |
7800 | } | |
7801 | } | |
7802 | } | |
7803 | ||
7804 | // end-sanitize-r5900 | |
7805 | // start-sanitize-r5900 | |
7806 | ||
7807 | 011100,5.RS,5.RT,5.RD,10000101000:MMI1:32::PADDUW | |
7808 | *r5900: | |
7809 | { | |
7810 | unsigned32 instruction = instruction_0; | |
7811 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7812 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7813 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7814 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7815 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7816 | { | |
7817 | int i; | |
7818 | for (i=0; i < WORDS_IN_MMI_REGS; i++) | |
7819 | { | |
7820 | unsigned64 s = RS_UW(i); | |
7821 | unsigned64 t = RT_UW(i); | |
7822 | unsigned64 r = s + t; | |
7823 | if (r > 0xFFFFFFFF) | |
7824 | GPR_UW(destreg,i) = 0xFFFFFFFF; | |
7825 | else | |
7826 | GPR_UW(destreg,i) = r; | |
7827 | } | |
7828 | } | |
7829 | } | |
7830 | ||
7831 | // end-sanitize-r5900 | |
7832 | // start-sanitize-r5900 | |
7833 | ||
7834 | 011100,5.RS,5.RT,5.RD,00100101000:MMI1:32::PADSBH | |
7835 | *r5900: | |
7836 | { | |
7837 | unsigned32 instruction = instruction_0; | |
7838 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7839 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7840 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7841 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7842 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7843 | { | |
7844 | int i; | |
7845 | for(i=0;i<HALFWORDS_IN_MMI_REGS/2;i++) | |
7846 | GPR_SH(destreg,i) = RS_SH(i) - RT_SH(i); | |
7847 | for(;i<HALFWORDS_IN_MMI_REGS;i++) | |
7848 | GPR_SH(destreg,i) = RS_SH(i) + RT_SH(i); | |
7849 | } | |
7850 | } | |
7851 | ||
7852 | // end-sanitize-r5900 | |
7853 | // start-sanitize-r5900 | |
7854 | ||
7855 | 011100,5.RS,5.RT,5.RD,10010001001:MMI2:32::PAND | |
7856 | *r5900: | |
7857 | { | |
7858 | unsigned32 instruction = instruction_0; | |
7859 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7860 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7861 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7862 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7863 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7864 | { | |
7865 | int i; | |
7866 | for(i=0;i<WORDS_IN_MMI_REGS;i++) | |
7867 | GPR_UW(destreg,i) = (RS_UW(i) & RT_UW(i)); | |
7868 | } | |
7869 | } | |
7870 | ||
7871 | // end-sanitize-r5900 | |
7872 | // start-sanitize-r5900 | |
7873 | ||
7874 | 011100,5.RS,5.RT,5.RD,01010101000:MMI1:32::PCEQB | |
7875 | *r5900: | |
7876 | { | |
7877 | unsigned32 instruction = instruction_0; | |
7878 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7879 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7880 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7881 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7882 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7883 | { | |
7884 | int i; | |
7885 | for(i=0;i<BYTES_IN_MMI_REGS;i++) | |
7886 | { | |
7887 | if (RS_SB(i) == RT_SB(i)) GPR_SB(destreg,i) = 0xFF; | |
7888 | else GPR_SB(destreg,i) = 0; | |
7889 | } | |
7890 | } | |
7891 | } | |
7892 | ||
7893 | // end-sanitize-r5900 | |
7894 | // start-sanitize-r5900 | |
7895 | ||
7896 | 011100,5.RS,5.RT,5.RD,00110101000:MMI1:32::PCEQH | |
7897 | *r5900: | |
7898 | { | |
7899 | unsigned32 instruction = instruction_0; | |
7900 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7901 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7902 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7903 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7904 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7905 | { | |
7906 | int i; | |
7907 | for(i=0;i<HALFWORDS_IN_MMI_REGS;i++) | |
7908 | { | |
7909 | if (RS_SH(i) == RT_SH(i)) GPR_SH(destreg,i) = 0xFFFF; | |
7910 | else GPR_SH(destreg,i) = 0; | |
7911 | } | |
7912 | } | |
7913 | } | |
7914 | ||
7915 | // end-sanitize-r5900 | |
7916 | // start-sanitize-r5900 | |
7917 | ||
7918 | 011100,5.RS,5.RT,5.RD,00010101000:MMI1:32::PCEQW | |
7919 | *r5900: | |
7920 | { | |
7921 | unsigned32 instruction = instruction_0; | |
7922 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7923 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7924 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7925 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7926 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7927 | { | |
7928 | int i; | |
7929 | for(i=0;i<WORDS_IN_MMI_REGS;i++) | |
7930 | { | |
7931 | if (RS_SW(i) == RT_SW(i)) GPR_SW(destreg,i) = 0xFFFFFFFF; | |
7932 | else GPR_SW(destreg,i) = 0; | |
7933 | } | |
7934 | } | |
7935 | } | |
7936 | ||
7937 | // end-sanitize-r5900 | |
7938 | // start-sanitize-r5900 | |
7939 | ||
7940 | 011100,5.RS,5.RT,5.RD,01010001000:MMI0:32::PCGTB | |
7941 | *r5900: | |
7942 | { | |
7943 | unsigned32 instruction = instruction_0; | |
7944 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7945 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7946 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7947 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7948 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7949 | { | |
7950 | int i; | |
7951 | for(i=0;i<BYTES_IN_MMI_REGS;i++) | |
7952 | { | |
7953 | if (RS_SB(i) > RT_SB(i)) GPR_SB(destreg,i) = 0xFF; | |
7954 | else GPR_SB(destreg,i) = 0; | |
7955 | } | |
7956 | } | |
7957 | } | |
7958 | ||
7959 | // end-sanitize-r5900 | |
7960 | // start-sanitize-r5900 | |
7961 | ||
7962 | 011100,5.RS,5.RT,5.RD,00110001000:MMI0:32::PCGTH | |
7963 | *r5900: | |
7964 | { | |
7965 | unsigned32 instruction = instruction_0; | |
7966 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7967 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7968 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7969 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7970 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7971 | { | |
7972 | int i; | |
7973 | for(i=0;i<HALFWORDS_IN_MMI_REGS;i++) | |
7974 | { | |
7975 | if (RS_SH(i) > RT_SH(i)) GPR_SH(destreg,i) = 0xFFFF; | |
7976 | else GPR_SH(destreg,i) = 0; | |
7977 | } | |
7978 | } | |
7979 | } | |
7980 | ||
7981 | // end-sanitize-r5900 | |
7982 | // start-sanitize-r5900 | |
7983 | ||
7984 | 011100,5.RS,5.RT,5.RD,00010001000:MMI0:32::PCGTW | |
7985 | *r5900: | |
7986 | { | |
7987 | unsigned32 instruction = instruction_0; | |
7988 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
7989 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
7990 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
7991 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
7992 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
7993 | { | |
7994 | int i; | |
7995 | for(i=0;i<WORDS_IN_MMI_REGS;i++) | |
7996 | { | |
7997 | if (RS_SW(i) > RT_SW(i)) GPR_SW(destreg,i) = 0xFFFFFFFF; | |
7998 | else GPR_SW(destreg,i) = 0; | |
7999 | } | |
8000 | } | |
8001 | } | |
8002 | ||
8003 | // end-sanitize-r5900 | |
8004 | // start-sanitize-r5900 | |
8005 | ||
8006 | 01110000000,5.RT,5.RD,11011101001:MMI3:32::PCPYH | |
8007 | *r5900: | |
8008 | { | |
8009 | unsigned32 instruction = instruction_0; | |
8010 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8011 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8012 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8013 | { | |
8014 | GPR_UH(destreg,7) = GPR_UH(destreg,6) = GPR_UH(destreg,5) = GPR_UH(destreg,4) = RT_UH(4); | |
8015 | GPR_UH(destreg,3) = GPR_UH(destreg,2) = GPR_UH(destreg,1) = GPR_UH(destreg,0) = RT_UH(0); | |
8016 | } | |
8017 | } | |
8018 | ||
8019 | // end-sanitize-r5900 | |
8020 | // start-sanitize-r5900 | |
8021 | ||
8022 | 011100,5.RS,5.RT,5.RD,01110001001:MMI2:32::PCPYLD | |
8023 | *r5900: | |
8024 | { | |
8025 | unsigned32 instruction = instruction_0; | |
8026 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8027 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8028 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8029 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8030 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8031 | { | |
8032 | GPR_UD(destreg,0) = RT_UD(0); | |
8033 | GPR_UD(destreg,1) = RS_UD(0); | |
8034 | } | |
8035 | } | |
8036 | ||
8037 | // end-sanitize-r5900 | |
8038 | // start-sanitize-r5900 | |
8039 | ||
8040 | 011100,5.RS,5.RT,5.RD,01110101001:MMI3:32::PCPYUD | |
8041 | *r5900: | |
8042 | { | |
8043 | unsigned32 instruction = instruction_0; | |
8044 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8045 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8046 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8047 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8048 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8049 | { | |
8050 | GPR_UD(destreg,0) = RS_UD(1); | |
8051 | GPR_UD(destreg,1) = RT_UD(1); | |
8052 | } | |
8053 | } | |
8054 | ||
8055 | // end-sanitize-r5900 | |
8056 | // start-sanitize-r5900 | |
8057 | ||
8058 | 011100,5.RS,5.RT,0000011101001001:MMI2:32::PDIVBW | |
8059 | *r5900: | |
8060 | { | |
8061 | unsigned32 instruction = instruction_0; | |
8062 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8063 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8064 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8065 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8066 | { | |
8067 | signed32 devisor = RT_SH(0); | |
8068 | if (devisor == -1) | |
8069 | { | |
8070 | LO_SW(0) = -RS_SW(0); | |
8071 | HI_SW(0) = 0; | |
8072 | LO_SW(1) = -RS_SW(1); | |
8073 | HI_SW(1) = 0; | |
8074 | LO_SW(2) = -RS_SW(2); | |
8075 | HI_SW(2) = 0; | |
8076 | LO_SW(3) = -RS_SW(3); | |
8077 | HI_SW(3) = 0; | |
8078 | } | |
8079 | else if (devisor != 0) | |
8080 | { | |
8081 | LO_SW(0) = RS_SW(0) / devisor; | |
8082 | HI_SW(0) = SIGNEXTEND( (RS_SW(0) % devisor), 16 ); | |
8083 | LO_SW(1) = RS_SW(1) / devisor; | |
8084 | HI_SW(1) = SIGNEXTEND( (RS_SW(1) % devisor), 16 ); | |
8085 | LO_SW(2) = RS_SW(2) / devisor; | |
8086 | HI_SW(2) = SIGNEXTEND( (RS_SW(2) % devisor), 16 ); | |
8087 | LO_SW(3) = RS_SW(3) / devisor; | |
8088 | HI_SW(3) = SIGNEXTEND( (RS_SW(3) % devisor), 16 ); | |
8089 | } | |
8090 | } | |
8091 | } | |
8092 | ||
8093 | // end-sanitize-r5900 | |
8094 | // start-sanitize-r5900 | |
8095 | ||
8096 | 011100,5.RS,5.RT,0000001101101001:MMI3:32::PDIVUW | |
8097 | *r5900: | |
8098 | { | |
8099 | unsigned32 instruction = instruction_0; | |
8100 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8101 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8102 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8103 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8104 | { | |
8105 | if (RT_UW(0) != 0) | |
8106 | { | |
8107 | LO = (signed32)(RS_UW(0) / RT_UW(0)); | |
8108 | HI = (signed32)(RS_UW(0) % RT_UW(0)); | |
8109 | } | |
8110 | if (RT_UW(2) != 0) | |
8111 | { | |
8112 | LO1 = (signed32)(RS_UW(2) / RT_UW(2)); | |
8113 | HI1 = (signed32)(RS_UW(2) % RT_UW(2)); | |
8114 | } | |
8115 | } | |
8116 | } | |
8117 | ||
8118 | // end-sanitize-r5900 | |
8119 | // start-sanitize-r5900 | |
8120 | ||
8121 | 011100,5.RS,5.RT,0000001101001001:MMI2:32::PDIVW | |
8122 | *r5900: | |
8123 | { | |
8124 | unsigned32 instruction = instruction_0; | |
8125 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8126 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8127 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8128 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8129 | { | |
8130 | if (RT_SW(0) == -1) | |
8131 | { | |
8132 | LO = -RS_SW(0); | |
8133 | HI = 0; | |
8134 | } | |
8135 | else if (RT_UW(0) != 0) | |
8136 | { | |
8137 | LO = (signed32)(RS_SW(0) / RT_SW(0)); | |
8138 | HI = (signed32)(RS_SW(0) % RT_SW(0)); | |
8139 | } | |
8140 | if (RT_SW(2) == -1) | |
8141 | { | |
8142 | LO1 = -RS_SW(2); | |
8143 | HI1 = 0; | |
8144 | } | |
8145 | else if (RT_UW(2) != 0) | |
8146 | { | |
8147 | LO1 = (signed32)(RS_SW(2) / RT_SW(2)); | |
8148 | HI1 = (signed32)(RS_SW(2) % RT_SW(2)); | |
8149 | } | |
8150 | } | |
8151 | } | |
8152 | ||
8153 | // end-sanitize-r5900 | |
8154 | // start-sanitize-r5900 | |
8155 | ||
8156 | 01110000000,5.RT,5.RD,11010101001:MMI3:32::PEXCH | |
8157 | *r5900: | |
8158 | { | |
8159 | unsigned32 instruction = instruction_0; | |
8160 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8161 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8162 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8163 | { | |
8164 | GPR_UH(destreg,0) = RT_UH(0); | |
8165 | GPR_UH(destreg,1) = RT_UH(2); | |
8166 | GPR_UH(destreg,2) = RT_UH(1); | |
8167 | GPR_UH(destreg,3) = RT_UH(3); | |
8168 | GPR_UH(destreg,4) = RT_UH(4); | |
8169 | GPR_UH(destreg,5) = RT_UH(6); | |
8170 | GPR_UH(destreg,6) = RT_UH(5); | |
8171 | GPR_UH(destreg,7) = RT_UH(7); | |
8172 | } | |
8173 | } | |
8174 | ||
8175 | // end-sanitize-r5900 | |
8176 | // start-sanitize-r5900 | |
8177 | ||
8178 | 01110000000,5.RT,5.RD,11110101001:MMI3:32::PEXCW | |
8179 | *r5900: | |
8180 | { | |
8181 | unsigned32 instruction = instruction_0; | |
8182 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8183 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8184 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8185 | { | |
8186 | GPR_UW(destreg,0) = RT_UW(0); | |
8187 | GPR_UW(destreg,1) = RT_UW(2); | |
8188 | GPR_UW(destreg,2) = RT_UW(1); | |
8189 | GPR_UW(destreg,3) = RT_UW(3); | |
8190 | } | |
8191 | } | |
8192 | ||
8193 | // end-sanitize-r5900 | |
8194 | // start-sanitize-r5900 | |
8195 | ||
8196 | 01110000000,5.RT,5.RD,11010001001:MMI2:32::PEXOH | |
8197 | *r5900: | |
8198 | { | |
8199 | unsigned32 instruction = instruction_0; | |
8200 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8201 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8202 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8203 | { | |
8204 | GPR_UH(destreg,0) = RT_UH(2); | |
8205 | GPR_UH(destreg,1) = RT_UH(1); | |
8206 | GPR_UH(destreg,2) = RT_UH(0); | |
8207 | GPR_UH(destreg,3) = RT_UH(3); | |
8208 | GPR_UH(destreg,4) = RT_UH(6); | |
8209 | GPR_UH(destreg,5) = RT_UH(5); | |
8210 | GPR_UH(destreg,6) = RT_UH(4); | |
8211 | GPR_UH(destreg,7) = RT_UH(7); | |
8212 | } | |
8213 | } | |
8214 | ||
8215 | // end-sanitize-r5900 | |
8216 | // start-sanitize-r5900 | |
8217 | ||
8218 | 01110000000,5.RT,5.RD,11110001001:MMI2:32::PEXOW | |
8219 | *r5900: | |
8220 | { | |
8221 | unsigned32 instruction = instruction_0; | |
8222 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8223 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8224 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8225 | { | |
8226 | GPR_UW(destreg,0) = RT_UW(2); | |
8227 | GPR_UW(destreg,1) = RT_UW(1); | |
8228 | GPR_UW(destreg,2) = RT_UW(0); | |
8229 | GPR_UW(destreg,3) = RT_UW(3); | |
8230 | } | |
8231 | } | |
8232 | ||
8233 | // end-sanitize-r5900 | |
8234 | // start-sanitize-r5900 | |
8235 | ||
8236 | 01110000000,5.RT,5.RD,11110001000:MMI0:32::PEXT5 | |
8237 | *r5900: | |
8238 | { | |
8239 | unsigned32 instruction = instruction_0; | |
8240 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8241 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8242 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8243 | { | |
8244 | int i; | |
8245 | for(i=0;i<WORDS_IN_MMI_REGS;i++) | |
8246 | { | |
8247 | unsigned32 x = RT_UW(i); | |
8248 | GPR_UW(destreg,i) = ((x & (1 << 15)) << (31 - 15)) | |
8249 | | ((x & (31 << 10)) << (19 - 10)) | |
8250 | | ((x & (31 << 5)) << (11 - 5)) | |
8251 | | ((x & (31 << 0)) << (3 - 0)); | |
8252 | } | |
8253 | } | |
8254 | } | |
8255 | ||
8256 | // end-sanitize-r5900 | |
8257 | // start-sanitize-r5900 | |
8258 | ||
8259 | 011100,5.RS,5.RT,5.RD,11010001000:MMI0:32::PEXTLB | |
8260 | *r5900: | |
8261 | { | |
8262 | unsigned32 instruction = instruction_0; | |
8263 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8264 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8265 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8266 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8267 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8268 | { | |
8269 | GPR_UB(destreg,0) = RT_UB(0); | |
8270 | GPR_UB(destreg,1) = RS_UB(0); | |
8271 | GPR_UB(destreg,2) = RT_UB(1); | |
8272 | GPR_UB(destreg,3) = RS_UB(1); | |
8273 | GPR_UB(destreg,4) = RT_UB(2); | |
8274 | GPR_UB(destreg,5) = RS_UB(2); | |
8275 | GPR_UB(destreg,6) = RT_UB(3); | |
8276 | GPR_UB(destreg,7) = RS_UB(3); | |
8277 | GPR_UB(destreg,8) = RT_UB(4); | |
8278 | GPR_UB(destreg,9) = RS_UB(4); | |
8279 | GPR_UB(destreg,10) = RT_UB(5); | |
8280 | GPR_UB(destreg,11) = RS_UB(5); | |
8281 | GPR_UB(destreg,12) = RT_UB(6); | |
8282 | GPR_UB(destreg,13) = RS_UB(6); | |
8283 | GPR_UB(destreg,14) = RT_UB(7); | |
8284 | GPR_UB(destreg,15) = RS_UB(7); | |
8285 | } | |
8286 | } | |
8287 | ||
8288 | // end-sanitize-r5900 | |
8289 | // start-sanitize-r5900 | |
8290 | ||
8291 | 011100,5.RS,5.RT,5.RD,10110001000:MMI0:32::PEXTLH | |
8292 | *r5900: | |
8293 | { | |
8294 | unsigned32 instruction = instruction_0; | |
8295 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8296 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8297 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8298 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8299 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8300 | { | |
8301 | GPR_UH(destreg,0) = RT_UH(0); | |
8302 | GPR_UH(destreg,1) = RS_UH(0); | |
8303 | GPR_UH(destreg,2) = RT_UH(1); | |
8304 | GPR_UH(destreg,3) = RS_UH(1); | |
8305 | GPR_UH(destreg,4) = RT_UH(2); | |
8306 | GPR_UH(destreg,5) = RS_UH(2); | |
8307 | GPR_UH(destreg,6) = RT_UH(3); | |
8308 | GPR_UH(destreg,7) = RS_UH(3); | |
8309 | } | |
8310 | } | |
8311 | ||
8312 | // end-sanitize-r5900 | |
8313 | // start-sanitize-r5900 | |
8314 | ||
8315 | 011100,5.RS,5.RT,5.RD,10010001000:MMI0:32::PEXTLW | |
8316 | *r5900: | |
8317 | { | |
8318 | unsigned32 instruction = instruction_0; | |
8319 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8320 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8321 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8322 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8323 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8324 | { | |
8325 | GPR_UW(destreg,0) = RT_UW(0); | |
8326 | GPR_UW(destreg,1) = RS_UW(0); | |
8327 | GPR_UW(destreg,2) = RT_UW(1); | |
8328 | GPR_UW(destreg,3) = RS_UW(1); | |
8329 | } | |
8330 | } | |
8331 | ||
8332 | // end-sanitize-r5900 | |
8333 | // start-sanitize-r5900 | |
8334 | ||
8335 | 011100,5.RS,5.RT,5.RD,11010101000:MMI1:32::PEXTUB | |
8336 | *r5900: | |
8337 | { | |
8338 | unsigned32 instruction = instruction_0; | |
8339 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8340 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8341 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8342 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8343 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8344 | { | |
8345 | GPR_UB(destreg,0) = RT_UB(8); | |
8346 | GPR_UB(destreg,1) = RS_UB(8); | |
8347 | GPR_UB(destreg,2) = RT_UB(9); | |
8348 | GPR_UB(destreg,3) = RS_UB(9); | |
8349 | GPR_UB(destreg,4) = RT_UB(10); | |
8350 | GPR_UB(destreg,5) = RS_UB(10); | |
8351 | GPR_UB(destreg,6) = RT_UB(11); | |
8352 | GPR_UB(destreg,7) = RS_UB(11); | |
8353 | GPR_UB(destreg,8) = RT_UB(12); | |
8354 | GPR_UB(destreg,9) = RS_UB(12); | |
8355 | GPR_UB(destreg,10) = RT_UB(13); | |
8356 | GPR_UB(destreg,11) = RS_UB(13); | |
8357 | GPR_UB(destreg,12) = RT_UB(14); | |
8358 | GPR_UB(destreg,13) = RS_UB(14); | |
8359 | GPR_UB(destreg,14) = RT_UB(15); | |
8360 | GPR_UB(destreg,15) = RS_UB(15); | |
8361 | } | |
8362 | } | |
8363 | ||
8364 | // end-sanitize-r5900 | |
8365 | // start-sanitize-r5900 | |
8366 | ||
8367 | 011100,5.RS,5.RT,5.RD,10110101000:MMI1:32::PEXTUH | |
8368 | *r5900: | |
8369 | { | |
8370 | unsigned32 instruction = instruction_0; | |
8371 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8372 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8373 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8374 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8375 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8376 | { | |
8377 | GPR_UH(destreg,0) = RT_UH(4); | |
8378 | GPR_UH(destreg,1) = RS_UH(4); | |
8379 | GPR_UH(destreg,2) = RT_UH(5); | |
8380 | GPR_UH(destreg,3) = RS_UH(5); | |
8381 | GPR_UH(destreg,4) = RT_UH(6); | |
8382 | GPR_UH(destreg,5) = RS_UH(6); | |
8383 | GPR_UH(destreg,6) = RT_UH(7); | |
8384 | GPR_UH(destreg,7) = RS_UH(7); | |
8385 | } | |
8386 | } | |
8387 | ||
8388 | // end-sanitize-r5900 | |
8389 | // start-sanitize-r5900 | |
8390 | ||
8391 | 011100,5.RS,5.RT,5.RD,10010101000:MMI1:32::PEXTUW | |
8392 | *r5900: | |
8393 | { | |
8394 | unsigned32 instruction = instruction_0; | |
8395 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8396 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8397 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8398 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8399 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8400 | { | |
8401 | GPR_UW(destreg,0) = RT_UW(2); | |
8402 | GPR_UW(destreg,1) = RS_UW(2); | |
8403 | GPR_UW(destreg,2) = RT_UW(3); | |
8404 | GPR_UW(destreg,3) = RS_UW(3); | |
8405 | } | |
8406 | } | |
8407 | ||
8408 | // end-sanitize-r5900 | |
8409 | // start-sanitize-r5900 | |
8410 | ||
8411 | 011100,5.RS,5.RT,5.RD,10001001001:MMI2:32::PHMADDH | |
8412 | *r5900: | |
8413 | { | |
8414 | unsigned32 instruction = instruction_0; | |
8415 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8416 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8417 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8418 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8419 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8420 | { | |
8421 | GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(1) * RT_SH(1)) + (RS_SH(0) * RT_SH(0)); | |
8422 | GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(3) * RT_SH(3)) + (RS_SH(2) * RT_SH(2)); | |
8423 | GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(5) * RT_SH(5)) + (RS_SH(4) * RT_SH(4)); | |
8424 | GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(7) * RT_SH(7)) + (RS_SH(6) * RT_SH(6)); | |
8425 | } | |
8426 | } | |
8427 | ||
8428 | // end-sanitize-r5900 | |
8429 | // start-sanitize-r5900 | |
8430 | ||
8431 | 011100,5.RS,5.RT,5.RD,10101001001:MMI2:32::PHMSUBH | |
8432 | *r5900: | |
8433 | { | |
8434 | unsigned32 instruction = instruction_0; | |
8435 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8436 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8437 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8438 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8439 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8440 | { | |
8441 | GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(1) * RT_SH(1)) - (RS_SH(0) * RT_SH(0)); | |
8442 | GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(3) * RT_SH(3)) - (RS_SH(2) * RT_SH(2)); | |
8443 | GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(5) * RT_SH(5)) - (RS_SH(4) * RT_SH(4)); | |
8444 | GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(7) * RT_SH(7)) - (RS_SH(6) * RT_SH(6)); | |
8445 | } | |
8446 | } | |
8447 | ||
8448 | // end-sanitize-r5900 | |
8449 | // start-sanitize-r5900 | |
8450 | ||
8451 | 011100,5.RS,5.RT,5.RD,01010001001:MMI2:32::PINTH | |
8452 | *r5900: | |
8453 | { | |
8454 | unsigned32 instruction = instruction_0; | |
8455 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8456 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8457 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8458 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8459 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8460 | { | |
8461 | GPR_UH(destreg,0) = RT_UH(0); | |
8462 | GPR_UH(destreg,1) = RS_UH(4); | |
8463 | GPR_UH(destreg,2) = RT_UH(1); | |
8464 | GPR_UH(destreg,3) = RS_UH(5); | |
8465 | GPR_UH(destreg,4) = RT_UH(2); | |
8466 | GPR_UH(destreg,5) = RS_UH(6); | |
8467 | GPR_UH(destreg,6) = RT_UH(3); | |
8468 | GPR_UH(destreg,7) = RS_UH(7); | |
8469 | } | |
8470 | } | |
8471 | ||
8472 | // end-sanitize-r5900 | |
8473 | // start-sanitize-r5900 | |
8474 | ||
8475 | 011100,5.RS,5.RT,5.RD,01010101001:MMI3:32::PINTOH | |
8476 | *r5900: | |
8477 | { | |
8478 | unsigned32 instruction = instruction_0; | |
8479 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8480 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8481 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8482 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8483 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8484 | { | |
8485 | GPR_UH(destreg,0) = RT_UH(0); | |
8486 | GPR_UH(destreg,1) = RS_UH(0); | |
8487 | GPR_UH(destreg,2) = RT_UH(2); | |
8488 | GPR_UH(destreg,3) = RS_UH(2); | |
8489 | GPR_UH(destreg,4) = RT_UH(4); | |
8490 | GPR_UH(destreg,5) = RS_UH(4); | |
8491 | GPR_UH(destreg,6) = RT_UH(6); | |
8492 | GPR_UH(destreg,7) = RS_UH(6); | |
8493 | } | |
8494 | } | |
8495 | ||
8496 | // end-sanitize-r5900 | |
8497 | // start-sanitize-r5900 | |
8498 | ||
8499 | 011100,5.RS,00000,5.RD,00000000100:MMINORM:32::PLZCW | |
8500 | *r5900: | |
8501 | { | |
8502 | unsigned32 instruction = instruction_0; | |
8503 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8504 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8505 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8506 | { | |
8507 | unsigned long value; | |
8508 | int test; | |
8509 | int count; | |
8510 | int i; | |
8511 | value = RS_UW(0); | |
8512 | count = 0; | |
8513 | test = !!(value & (1 << 31)); | |
8514 | for(i=30; i>=0 && (test == !!(value & (1 << i))); i--) | |
8515 | count++; | |
8516 | GPR_UW(destreg,0) = count; | |
8517 | value = RS_UW(1); | |
8518 | count = 0; | |
8519 | test = !!(value & (1 << 31)); | |
8520 | for(i=30; i>=0 && (test == !!(value & (1 << i))); i--) | |
8521 | count++; | |
8522 | GPR_UW(destreg,1) = count; | |
8523 | } | |
8524 | } | |
8525 | ||
8526 | // end-sanitize-r5900 | |
8527 | // start-sanitize-r5900 | |
8528 | ||
8529 | 011100,5.RS,5.RT,5.RD,10000001001:MMI2:32::PMADDH | |
8530 | *r5900: | |
8531 | { | |
8532 | unsigned32 instruction = instruction_0; | |
8533 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8534 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8535 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8536 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8537 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8538 | { | |
8539 | GPR_SW(destreg,0) = LO_SW(0) += (RS_SH(0) * RT_SH(0)); | |
8540 | LO_SW(1) += (RS_SH(1) * RT_SH(1)); | |
8541 | GPR_SW(destreg,1) = HI_SW(0) += (RS_SH(2) * RT_SH(2)); | |
8542 | HI_SW(1) += (RS_SH(3) * RT_SH(3)); | |
8543 | GPR_SW(destreg,2) = LO_SW(2) += (RS_SH(4) * RT_SH(4)); | |
8544 | LO_SW(3) += (RS_SH(5) * RT_SH(5)); | |
8545 | GPR_SW(destreg,3) = HI_SW(2) += (RS_SH(6) * RT_SH(6)); | |
8546 | HI_SW(3) += (RS_SH(7) * RT_SH(7)); | |
8547 | } | |
8548 | } | |
8549 | ||
8550 | // end-sanitize-r5900 | |
8551 | // start-sanitize-r5900 | |
8552 | ||
8553 | 011100,5.RS,5.RT,5.RD,00000101001:MMI3:32::PMADDUW | |
8554 | *r5900: | |
8555 | { | |
8556 | unsigned32 instruction = instruction_0; | |
8557 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8558 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8559 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8560 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8561 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8562 | { | |
8563 | unsigned64 sum0 = UNSIGNED64( HI_SW(0), LO_SW(0) ); | |
8564 | unsigned64 sum1 = UNSIGNED64( HI_SW(2), LO_SW(2) ); | |
8565 | unsigned64 prod0 = (unsigned64)RS_UW(0) * (unsigned64)RT_UW(0); | |
8566 | unsigned64 prod1 = (unsigned64)RS_UW(2) * (unsigned64)RT_UW(2); | |
8567 | sum0 += prod0; | |
8568 | sum1 += prod1; | |
8569 | GPR_UD(destreg,0) = sum0; | |
8570 | GPR_UD(destreg,1) = sum1; | |
8571 | LO = SIGNEXTEND( sum0, 32 ); | |
8572 | HI = SIGNEXTEND( VH4_8(sum0), 32 ); | |
8573 | LO1 = SIGNEXTEND( sum1, 32 ); | |
8574 | HI1 = SIGNEXTEND( VH4_8(sum1), 32 ); | |
8575 | } | |
8576 | } | |
8577 | ||
8578 | // end-sanitize-r5900 | |
8579 | // start-sanitize-r5900 | |
8580 | ||
8581 | 011100,5.RS,5.RT,5.RD,00000001001:MMI2:32::PMADDW | |
8582 | *r5900: | |
8583 | { | |
8584 | unsigned32 instruction = instruction_0; | |
8585 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8586 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8587 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8588 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8589 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8590 | { | |
8591 | signed64 sum0 = WORD64( HI_SW(0), LO_SW(0) ); | |
8592 | signed64 sum1 = WORD64( HI_SW(2), LO_SW(2) ); | |
8593 | signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0); | |
8594 | signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2); | |
8595 | sum0 += prod0; | |
8596 | sum1 += prod1; | |
8597 | GPR_SD(destreg,0) = sum0; | |
8598 | GPR_SD(destreg,1) = sum1; | |
8599 | LO = SIGNEXTEND( sum0, 32 ); | |
8600 | HI = SIGNEXTEND( VH4_8(sum0), 32 ); | |
8601 | LO1 = SIGNEXTEND( sum1, 32 ); | |
8602 | HI1 = SIGNEXTEND( VH4_8(sum1), 32 ); | |
8603 | } | |
8604 | } | |
8605 | ||
8606 | // end-sanitize-r5900 | |
8607 | // start-sanitize-r5900 | |
8608 | ||
8609 | 011100,5.RS,5.RT,5.RD,00111001000:MMI0:32::PMAXH | |
8610 | *r5900: | |
8611 | { | |
8612 | unsigned32 instruction = instruction_0; | |
8613 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8614 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8615 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8616 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8617 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8618 | { | |
8619 | int i; | |
8620 | for(i=0;i<HALFWORDS_IN_MMI_REGS;i++) | |
8621 | { | |
8622 | if (RS_SH(i) > RT_SH(i)) GPR_SH(destreg,i) = RS_SH(i); | |
8623 | else GPR_SH(destreg,i) = RT_SH(i); | |
8624 | } | |
8625 | } | |
8626 | } | |
8627 | ||
8628 | // end-sanitize-r5900 | |
8629 | // start-sanitize-r5900 | |
8630 | ||
8631 | 011100,5.RS,5.RT,5.RD,00011001000:MMI0:32::PMAXW | |
8632 | *r5900: | |
8633 | { | |
8634 | unsigned32 instruction = instruction_0; | |
8635 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8636 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8637 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8638 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8639 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8640 | { | |
8641 | int i; | |
8642 | for(i=0;i<WORDS_IN_MMI_REGS;i++) | |
8643 | { | |
8644 | if (RS_SW(i) > RT_SW(i)) GPR_SW(destreg,i) = RS_SW(i); | |
8645 | else GPR_SW(destreg,i) = RT_SW(i); | |
8646 | } | |
8647 | } | |
8648 | } | |
8649 | ||
8650 | // end-sanitize-r5900 | |
8651 | // start-sanitize-r5900 | |
8652 | ||
8653 | 0111000000000000,5.RD,01000001001:MMI2:32::PMFHI | |
8654 | *r5900: | |
8655 | { | |
8656 | unsigned32 instruction = instruction_0; | |
8657 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8658 | { | |
8659 | GPR_SD(destreg,0) = HI; | |
8660 | GPR_SD(destreg,1) = HI1; | |
8661 | } | |
8662 | } | |
8663 | ||
8664 | // end-sanitize-r5900 | |
8665 | // start-sanitize-r5900 | |
8666 | ||
8667 | 0111000000000000,5.RD,01001001001:MMI2:32::PMFLO | |
8668 | *r5900: | |
8669 | { | |
8670 | unsigned32 instruction = instruction_0; | |
8671 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8672 | { | |
8673 | GPR_SD(destreg,0) = LO; | |
8674 | GPR_SD(destreg,1) = LO1; | |
8675 | } | |
8676 | } | |
8677 | ||
8678 | // end-sanitize-r5900 | |
8679 | // start-sanitize-r5900 | |
8680 | ||
8681 | 0111000000000000,5.RD,5.SA,110000:MMINORM:32::PMFHL | |
8682 | *r5900: | |
8683 | { | |
8684 | unsigned32 instruction = instruction_0; | |
8685 | int op1 UNUSED = ((instruction >> 6) & 0x0000001F); | |
8686 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8687 | { | |
8688 | if (op1 == 0) | |
8689 | { | |
8690 | GPR_UW(destreg,0) = LO_UW(0); | |
8691 | GPR_UW(destreg,1) = HI_UW(0); | |
8692 | GPR_UW(destreg,2) = LO_UW(2); | |
8693 | GPR_UW(destreg,3) = HI_UW(2); | |
8694 | } | |
8695 | else if (op1 == 1) | |
8696 | { | |
8697 | GPR_UW(destreg,0) = LO_UW(1); | |
8698 | GPR_UW(destreg,1) = HI_UW(1); | |
8699 | GPR_UW(destreg,2) = LO_UW(3); | |
8700 | GPR_UW(destreg,3) = HI_UW(3); | |
8701 | } | |
8702 | else if (op1 == 2) | |
8703 | { | |
8704 | /* NOTE: This code implements a saturate according to the | |
8705 | figure on page B-115 and not according to the | |
8706 | definition on page B-113 */ | |
8707 | signed64 t = ((unsigned64)HI_UW(0) << 32) | (unsigned64)LO_UW(0); | |
8708 | signed64 u = ((unsigned64)HI_UW(2) << 32) | (unsigned64)LO_UW(2); | |
8709 | if ( t > SIGNED64 (0x000000007FFFFFFF) ) | |
8710 | GPR_SD(destreg,0) = SIGNED64 (0x000000007FFFFFFF); | |
8711 | else if ( t < - SIGNED64 (0x0000000080000000) ) | |
8712 | GPR_SD(destreg,0) = - SIGNED64 (0x0000000080000000); | |
8713 | else | |
8714 | GPR_SD(destreg,0) = t; | |
8715 | if ( u > SIGNED64 (0x000000007FFFFFFF) ) | |
8716 | GPR_SD(destreg,1) = SIGNED64 (0x000000007FFFFFFF); | |
8717 | else if ( u < - SIGNED64 (0x0000000080000000) ) | |
8718 | GPR_SD(destreg,1) = - SIGNED64 (0x0000000080000000); | |
8719 | else | |
8720 | GPR_SD(destreg,1) = u; | |
8721 | } | |
8722 | else if (op1 == 3) | |
8723 | { | |
8724 | GPR_UH(destreg,0) = LO_UH(0); | |
8725 | GPR_UH(destreg,1) = LO_UH(2); | |
8726 | GPR_UH(destreg,2) = HI_UH(0); | |
8727 | GPR_UH(destreg,3) = HI_UH(2); | |
8728 | GPR_UH(destreg,4) = LO_UH(4); | |
8729 | GPR_UH(destreg,5) = LO_UH(6); | |
8730 | GPR_UH(destreg,6) = HI_UH(4); | |
8731 | GPR_UH(destreg,7) = HI_UH(6); | |
8732 | } | |
8733 | else if (op1 == 4) | |
8734 | { | |
8735 | if (LO_SW(0) > 0x7FFF) | |
8736 | GPR_UH(destreg,0) = 0x7FFF; | |
8737 | else if (LO_SW(0) < -0x8000) | |
8738 | GPR_UH(destreg,0) = 0x8000; | |
8739 | else | |
8740 | GPR_UH(destreg,0) = LO_UH(0); | |
8741 | if (LO_SW(1) > 0x7FFF) | |
8742 | GPR_UH(destreg,1) = 0x7FFF; | |
8743 | else if (LO_SW(1) < -0x8000) | |
8744 | GPR_UH(destreg,1) = 0x8000; | |
8745 | else | |
8746 | GPR_UH(destreg,1) = LO_UH(2); | |
8747 | if (HI_SW(0) > 0x7FFF) | |
8748 | GPR_UH(destreg,2) = 0x7FFF; | |
8749 | else if (HI_SW(0) < -0x8000) | |
8750 | GPR_UH(destreg,2) = 0x8000; | |
8751 | else | |
8752 | GPR_UH(destreg,2) = HI_UH(0); | |
8753 | if (HI_SW(1) > 0x7FFF) | |
8754 | GPR_UH(destreg,3) = 0x7FFF; | |
8755 | else if (HI_SW(1) < -0x8000) | |
8756 | GPR_UH(destreg,3) = 0x8000; | |
8757 | else | |
8758 | GPR_UH(destreg,3) = HI_UH(2); | |
8759 | if (LO_SW(2) > 0x7FFF) | |
8760 | GPR_UH(destreg,4) = 0x7FFF; | |
8761 | else if (LO_SW(2) < -0x8000) | |
8762 | GPR_UH(destreg,4) = 0x8000; | |
8763 | else | |
8764 | GPR_UH(destreg,4) = LO_UH(4); | |
8765 | if (LO_SW(3) > 0x7FFF) | |
8766 | GPR_UH(destreg,5) = 0x7FFF; | |
8767 | else if (LO_SW(3) < -0x8000) | |
8768 | GPR_UH(destreg,5) = 0x8000; | |
8769 | else | |
8770 | GPR_UH(destreg,5) = LO_UH(6); | |
8771 | if (HI_SW(2) > 0x7FFF) | |
8772 | GPR_UH(destreg,6) = 0x7FFF; | |
8773 | else if (HI_SW(2) < -0x8000) | |
8774 | GPR_UH(destreg,6) = 0x8000; | |
8775 | else | |
8776 | GPR_UH(destreg,6) = HI_UH(4); | |
8777 | if (HI_SW(3) > 0x7FFF) | |
8778 | GPR_UH(destreg,7) = 0x7FFF; | |
8779 | else if (HI_SW(3) < -0x8000) | |
8780 | GPR_UH(destreg,7) = 0x8000; | |
8781 | else | |
8782 | GPR_UH(destreg,7) = HI_UH(6); | |
8783 | } | |
8784 | } | |
8785 | } | |
8786 | ||
8787 | // end-sanitize-r5900 | |
8788 | // start-sanitize-r5900 | |
8789 | ||
8790 | 011100,5.RS,5.RT,5.RD,00111101000:MMI1:32::PMINH | |
8791 | *r5900: | |
8792 | { | |
8793 | unsigned32 instruction = instruction_0; | |
8794 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8795 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8796 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8797 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8798 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8799 | { | |
8800 | int i; | |
8801 | for(i=0;i<HALFWORDS_IN_MMI_REGS;i++) | |
8802 | { | |
8803 | if (RS_SH(i) < RT_SH(i)) GPR_SH(destreg,i) = RS_SH(i); | |
8804 | else GPR_SH(destreg,i) = RT_SH(i); | |
8805 | } | |
8806 | } | |
8807 | } | |
8808 | ||
8809 | // end-sanitize-r5900 | |
8810 | // start-sanitize-r5900 | |
8811 | ||
8812 | 011100,5.RS,5.RT,5.RD,00011101000:MMI1:32::PMINW | |
8813 | *r5900: | |
8814 | { | |
8815 | unsigned32 instruction = instruction_0; | |
8816 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8817 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8818 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8819 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8820 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8821 | { | |
8822 | int i; | |
8823 | for(i=0;i<WORDS_IN_MMI_REGS;i++) | |
8824 | { | |
8825 | if (RS_SW(i) < RT_SW(i)) GPR_SW(destreg,i) = RS_SW(i); | |
8826 | else GPR_SW(destreg,i) = RT_SW(i); | |
8827 | } | |
8828 | } | |
8829 | } | |
8830 | ||
8831 | // end-sanitize-r5900 | |
8832 | // start-sanitize-r5900 | |
8833 | ||
8834 | 011100,5.RS,5.RT,5.RD,10100001001:MMI2:32::PMSUBH | |
8835 | *r5900: | |
8836 | { | |
8837 | unsigned32 instruction = instruction_0; | |
8838 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8839 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8840 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8841 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8842 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8843 | { | |
8844 | GPR_SW(destreg,0) = LO_SW(0) -= (RS_SH(0) * RT_SH(0)); | |
8845 | LO_SW(1) -= (RS_SH(1) * RT_SH(1)); | |
8846 | GPR_SW(destreg,1) = HI_SW(0) -= (RS_SH(2) * RT_SH(2)); | |
8847 | HI_SW(1) -= (RS_SH(3) * RT_SH(3)); | |
8848 | GPR_SW(destreg,2) = LO_SW(2) -= (RS_SH(4) * RT_SH(4)); | |
8849 | LO_SW(3) -= (RS_SH(5) * RT_SH(5)); | |
8850 | GPR_SW(destreg,3) = HI_SW(2) -= (RS_SH(6) * RT_SH(6)); | |
8851 | HI_SW(3) -= (RS_SH(7) * RT_SH(7)); | |
8852 | } | |
8853 | } | |
8854 | ||
8855 | // end-sanitize-r5900 | |
8856 | // start-sanitize-r5900 | |
8857 | ||
8858 | 011100,5.RS,5.RT,5.RD,00100001001:MMI2:32::PMSUBW | |
8859 | *r5900: | |
8860 | { | |
8861 | unsigned32 instruction = instruction_0; | |
8862 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8863 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8864 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8865 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8866 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8867 | { | |
8868 | signed64 sum0 = WORD64( HI_SW(0), LO_SW(0) ); | |
8869 | signed64 sum1 = WORD64( HI_SW(2), LO_SW(2) ); | |
8870 | signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0); | |
8871 | signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2); | |
8872 | sum0 -= prod0; | |
8873 | sum1 -= prod1; | |
8874 | GPR_SD(destreg,0) = sum0; | |
8875 | GPR_SD(destreg,1) = sum1; | |
8876 | LO = SIGNEXTEND( sum0, 32 ); | |
8877 | HI = SIGNEXTEND( VH4_8(sum0), 32 ); | |
8878 | LO1 = SIGNEXTEND( sum1, 32 ); | |
8879 | HI1 = SIGNEXTEND( VH4_8(sum1), 32 ); | |
8880 | } | |
8881 | } | |
8882 | ||
8883 | // end-sanitize-r5900 | |
8884 | // start-sanitize-r5900 | |
8885 | ||
8886 | 011100,5.RS,000000000001000101001:MMI3:32::PMTHI | |
8887 | *r5900: | |
8888 | { | |
8889 | unsigned32 instruction = instruction_0; | |
8890 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8891 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8892 | { | |
8893 | HI = RS_SD(0); | |
8894 | HI1 = RS_SD(1); | |
8895 | } | |
8896 | } | |
8897 | ||
8898 | // end-sanitize-r5900 | |
8899 | // start-sanitize-r5900 | |
8900 | ||
8901 | 011100,5.RS,000000000001001101001:MMI3:32::PMTLO | |
8902 | *r5900: | |
8903 | { | |
8904 | unsigned32 instruction = instruction_0; | |
8905 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8906 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8907 | { | |
8908 | LO = RS_SD(0); | |
8909 | LO1 = RS_SD(1); | |
8910 | } | |
8911 | } | |
8912 | ||
8913 | // end-sanitize-r5900 | |
8914 | // start-sanitize-r5900 | |
8915 | ||
8916 | 011100,5.RS,000000000000000110001:MMINORM:32::PMTHL.LW | |
8917 | *r5900: | |
8918 | { | |
8919 | unsigned32 instruction = instruction_0; | |
8920 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8921 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8922 | { | |
8923 | LO_UW(0) = RS_UW(0); | |
8924 | HI_UW(0) = RS_UW(1); | |
8925 | LO_UW(2) = RS_UW(2); | |
8926 | HI_UW(2) = RS_UW(3); | |
8927 | } | |
8928 | } | |
8929 | ||
8930 | // end-sanitize-r5900 | |
8931 | // start-sanitize-r5900 | |
8932 | ||
8933 | 011100,5.RS,5.RT,5.RD,11100001001:MMI2:32::PMULTH | |
8934 | *r5900: | |
8935 | { | |
8936 | unsigned32 instruction = instruction_0; | |
8937 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8938 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8939 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8940 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8941 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8942 | { | |
8943 | GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(0) * RT_SH(0)); | |
8944 | LO_SW(1) = (RS_SH(1) * RT_SH(1)); | |
8945 | GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(2) * RT_SH(2)); | |
8946 | HI_SW(1) = (RS_SH(3) * RT_SH(3)); | |
8947 | GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(4) * RT_SH(4)); | |
8948 | LO_SW(3) = (RS_SH(5) * RT_SH(5)); | |
8949 | GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(6) * RT_SH(6)); | |
8950 | HI_SW(3) = (RS_SH(7) * RT_SH(7)); | |
8951 | } | |
8952 | } | |
8953 | ||
8954 | // end-sanitize-r5900 | |
8955 | // start-sanitize-r5900 | |
8956 | ||
8957 | 011100,5.RS,5.RT,5.RD,01100101001:MMI3:32::PMULTUW | |
8958 | *r5900: | |
8959 | { | |
8960 | unsigned32 instruction = instruction_0; | |
8961 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8962 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8963 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8964 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8965 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8966 | { | |
8967 | unsigned64 sum0 = 0; | |
8968 | unsigned64 sum1 = 0; | |
8969 | unsigned64 prod0 = (unsigned64)RS_UW(0) * (unsigned64)RT_UW(0); | |
8970 | unsigned64 prod1 = (unsigned64)RS_UW(2) * (unsigned64)RT_UW(2); | |
8971 | sum0 = prod0; | |
8972 | sum1 = prod1; | |
8973 | GPR_UD(destreg,0) = sum0; | |
8974 | GPR_UD(destreg,1) = sum1; | |
8975 | LO = SIGNEXTEND( sum0, 32 ); | |
8976 | HI = SIGNEXTEND( VH4_8(sum0), 32 ); | |
8977 | LO1 = SIGNEXTEND( sum1, 32 ); | |
8978 | HI1 = SIGNEXTEND( VH4_8(sum1), 32 ); | |
8979 | } | |
8980 | } | |
8981 | ||
8982 | // end-sanitize-r5900 | |
8983 | // start-sanitize-r5900 | |
8984 | ||
8985 | 011100,5.RS,5.RT,5.RD,01100001001:MMI2:32::PMULTW | |
8986 | *r5900: | |
8987 | { | |
8988 | unsigned32 instruction = instruction_0; | |
8989 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
8990 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
8991 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
8992 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
8993 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
8994 | { | |
8995 | signed64 sum0 = 0; | |
8996 | signed64 sum1 = 0; | |
8997 | signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0); | |
8998 | signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2); | |
8999 | sum0 = prod0; | |
9000 | sum1 = prod1; | |
9001 | GPR_SD(destreg,0) = sum0; | |
9002 | GPR_SD(destreg,1) = sum1; | |
9003 | LO = SIGNEXTEND( sum0, 32 ); | |
9004 | HI = SIGNEXTEND( VH4_8(sum0), 32 ); | |
9005 | LO1 = SIGNEXTEND( sum1, 32 ); | |
9006 | HI1 = SIGNEXTEND( VH4_8(sum1), 32 ); | |
9007 | } | |
9008 | } | |
9009 | ||
9010 | // end-sanitize-r5900 | |
9011 | // start-sanitize-r5900 | |
9012 | ||
9013 | 011100,5.RS,5.RT,5.RD,10011101001:MMI3:32::PNOR | |
9014 | *r5900: | |
9015 | { | |
9016 | unsigned32 instruction = instruction_0; | |
9017 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9018 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9019 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9020 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9021 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9022 | { | |
9023 | int i; | |
9024 | for(i=0;i<WORDS_IN_MMI_REGS;i++) | |
9025 | GPR_UW(destreg,i) = ~(RS_UW(i) | RT_UW(i)); | |
9026 | } | |
9027 | } | |
9028 | ||
9029 | // end-sanitize-r5900 | |
9030 | // start-sanitize-r5900 | |
9031 | ||
9032 | 011100,5.RS,5.RT,5.RD,10010101001:MMI3:32::POR | |
9033 | *r5900: | |
9034 | { | |
9035 | unsigned32 instruction = instruction_0; | |
9036 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9037 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9038 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9039 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9040 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9041 | { | |
9042 | int i; | |
9043 | for(i=0;i<WORDS_IN_MMI_REGS;i++) | |
9044 | GPR_UW(destreg,i) = (RS_UW(i) | RT_UW(i)); | |
9045 | } | |
9046 | } | |
9047 | ||
9048 | // end-sanitize-r5900 | |
9049 | // start-sanitize-r5900 | |
9050 | ||
9051 | 01110000000,5.RT,5.RD,11111001000:MMI0:32::PPAC5 | |
9052 | *r5900: | |
9053 | { | |
9054 | unsigned32 instruction = instruction_0; | |
9055 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9056 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9057 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9058 | { | |
9059 | int i; | |
9060 | for(i=0;i<WORDS_IN_MMI_REGS;i++) | |
9061 | { | |
9062 | unsigned32 x = RT_UW(i); | |
9063 | GPR_UW(destreg,i) = ((x & (1 << 31)) >> (31 - 15)) | |
9064 | | ((x & (31 << 19)) >> (19 - 10)) | |
9065 | | ((x & (31 << 11)) >> (11 - 5)) | |
9066 | | ((x & (31 << 3)) >> (3 - 0)); | |
9067 | } | |
9068 | } | |
9069 | } | |
9070 | ||
9071 | // end-sanitize-r5900 | |
9072 | // start-sanitize-r5900 | |
9073 | ||
9074 | 011100,5.RS,5.RT,5.RD,11011001000:MMI0:32::PPACB | |
9075 | *r5900: | |
9076 | { | |
9077 | unsigned32 instruction = instruction_0; | |
9078 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9079 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9080 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9081 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9082 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9083 | { | |
9084 | GPR_UB(destreg,0) = RT_UB(0); | |
9085 | GPR_UB(destreg,1) = RT_UB(2); | |
9086 | GPR_UB(destreg,2) = RT_UB(4); | |
9087 | GPR_UB(destreg,3) = RT_UB(6); | |
9088 | GPR_UB(destreg,4) = RT_UB(8); | |
9089 | GPR_UB(destreg,5) = RT_UB(10); | |
9090 | GPR_UB(destreg,6) = RT_UB(12); | |
9091 | GPR_UB(destreg,7) = RT_UB(14); | |
9092 | GPR_UB(destreg,8) = RS_UB(0); | |
9093 | GPR_UB(destreg,9) = RS_UB(2); | |
9094 | GPR_UB(destreg,10) = RS_UB(4); | |
9095 | GPR_UB(destreg,11) = RS_UB(6); | |
9096 | GPR_UB(destreg,12) = RS_UB(8); | |
9097 | GPR_UB(destreg,13) = RS_UB(10); | |
9098 | GPR_UB(destreg,14) = RS_UB(12); | |
9099 | GPR_UB(destreg,15) = RS_UB(14); | |
9100 | } | |
9101 | } | |
9102 | ||
9103 | // end-sanitize-r5900 | |
9104 | // start-sanitize-r5900 | |
9105 | ||
9106 | 011100,5.RS,5.RT,5.RD,10111001000:MMI0:32::PPACH | |
9107 | *r5900: | |
9108 | { | |
9109 | unsigned32 instruction = instruction_0; | |
9110 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9111 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9112 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9113 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9114 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9115 | { | |
9116 | GPR_UH(destreg,0) = RT_UH(0); | |
9117 | GPR_UH(destreg,1) = RT_UH(2); | |
9118 | GPR_UH(destreg,2) = RT_UH(4); | |
9119 | GPR_UH(destreg,3) = RT_UH(6); | |
9120 | GPR_UH(destreg,4) = RS_UH(0); | |
9121 | GPR_UH(destreg,5) = RS_UH(2); | |
9122 | GPR_UH(destreg,6) = RS_UH(4); | |
9123 | GPR_UH(destreg,7) = RS_UH(6); | |
9124 | } | |
9125 | } | |
9126 | ||
9127 | // end-sanitize-r5900 | |
9128 | // start-sanitize-r5900 | |
9129 | ||
9130 | 011100,5.RS,5.RT,5.RD,10011001000:MMI0:32::PPACW | |
9131 | *r5900: | |
9132 | { | |
9133 | unsigned32 instruction = instruction_0; | |
9134 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9135 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9136 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9137 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9138 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9139 | { | |
9140 | GPR_UW(destreg,0) = RT_UW(0); | |
9141 | GPR_UW(destreg,1) = RT_UW(2); | |
9142 | GPR_UW(destreg,2) = RS_UW(0); | |
9143 | GPR_UW(destreg,3) = RS_UW(2); | |
9144 | } | |
9145 | } | |
9146 | ||
9147 | // end-sanitize-r5900 | |
9148 | // start-sanitize-r5900 | |
9149 | ||
9150 | 01110000000,5.RT,5.RD,11011001001:MMI2:32::PREVH | |
9151 | *r5900: | |
9152 | { | |
9153 | unsigned32 instruction = instruction_0; | |
9154 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9155 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9156 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9157 | { | |
9158 | GPR_UH(destreg,0) = RT_UH(3); | |
9159 | GPR_UH(destreg,1) = RT_UH(2); | |
9160 | GPR_UH(destreg,2) = RT_UH(1); | |
9161 | GPR_UH(destreg,3) = RT_UH(0); | |
9162 | GPR_UH(destreg,4) = RT_UH(7); | |
9163 | GPR_UH(destreg,5) = RT_UH(6); | |
9164 | GPR_UH(destreg,6) = RT_UH(5); | |
9165 | GPR_UH(destreg,7) = RT_UH(4); | |
9166 | } | |
9167 | } | |
9168 | ||
9169 | // end-sanitize-r5900 | |
9170 | // start-sanitize-r5900 | |
9171 | ||
9172 | 01110000000,5.RT,5.RD,11111001001:MMI2:32::PROT3W | |
9173 | *r5900: | |
9174 | { | |
9175 | unsigned32 instruction = instruction_0; | |
9176 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9177 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9178 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9179 | { | |
9180 | GPR_UW(destreg,0) = RT_UW(0); | |
9181 | GPR_UW(destreg,1) = RT_UW(3); | |
9182 | GPR_UW(destreg,2) = RT_UW(1); | |
9183 | GPR_UW(destreg,3) = RT_UW(2); | |
9184 | } | |
9185 | } | |
9186 | ||
9187 | // end-sanitize-r5900 | |
9188 | // start-sanitize-r5900 | |
9189 | ||
9190 | 01110000000,5.RT,5.RD,5.SA,110100:MMINORM:32::PSLLH | |
9191 | *r5900: | |
9192 | { | |
9193 | unsigned32 instruction = instruction_0; | |
9194 | int op1 UNUSED = ((instruction >> 6) & 0x0000001F); | |
9195 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9196 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9197 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9198 | { | |
9199 | int shift_by = op1 & (16-1); | |
9200 | int i; | |
9201 | for(i=0;i<HALFWORDS_IN_MMI_REGS;i++) | |
9202 | GPR_UH(destreg,i) = (RT_UH(i) << shift_by); | |
9203 | } | |
9204 | } | |
9205 | ||
9206 | // end-sanitize-r5900 | |
9207 | // start-sanitize-r5900 | |
9208 | ||
9209 | 011100,5.RS,5.RT,5.RD,00010001001:MMI2:32::PSLLVW | |
9210 | *r5900: | |
9211 | { | |
9212 | unsigned32 instruction = instruction_0; | |
9213 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9214 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9215 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9216 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9217 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9218 | { | |
9219 | int s0 = (RS_UB(0) & 0x1F); | |
9220 | int s1 = (RS_UB(8) & 0x1F); | |
9221 | signed32 temp0 = RT_UW(0) << s0; | |
9222 | signed32 temp1 = RT_UW(2) << s1; | |
9223 | GPR_SD(destreg,0) = (signed64)temp0; | |
9224 | GPR_SD(destreg,1) = (signed64)temp1; | |
9225 | } | |
9226 | } | |
9227 | ||
9228 | // end-sanitize-r5900 | |
9229 | // start-sanitize-r5900 | |
9230 | ||
9231 | 01110000000,5.RT,5.RD,5.SA,111100:MMINORM:32::PSLLW | |
9232 | *r5900: | |
9233 | { | |
9234 | unsigned32 instruction = instruction_0; | |
9235 | int op1 UNUSED = ((instruction >> 6) & 0x0000001F); | |
9236 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9237 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9238 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9239 | { | |
9240 | int shift_by = op1 & (32-1); | |
9241 | int i; | |
9242 | for(i=0;i<WORDS_IN_MMI_REGS;i++) | |
9243 | GPR_UW(destreg,i) = (RT_UW(i) << shift_by); | |
9244 | } | |
9245 | } | |
9246 | ||
9247 | // end-sanitize-r5900 | |
9248 | // start-sanitize-r5900 | |
9249 | ||
9250 | 01110000000,5.RT,5.RD,5.SA,110111:MMINORM:32::PSRAH | |
9251 | *r5900: | |
9252 | { | |
9253 | unsigned32 instruction = instruction_0; | |
9254 | int op1 UNUSED = ((instruction >> 6) & 0x0000001F); | |
9255 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9256 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9257 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9258 | { | |
9259 | int shift_by = op1 & (16-1); | |
9260 | int i; | |
9261 | for(i=0;i<HALFWORDS_IN_MMI_REGS;i++) | |
9262 | GPR_SH(destreg,i) = SIGNEXTEND( (RT_SH(i) >> shift_by), (16-shift_by) ); | |
9263 | } | |
9264 | } | |
9265 | ||
9266 | // end-sanitize-r5900 | |
9267 | // start-sanitize-r5900 | |
9268 | ||
9269 | 011100,5.RS,5.RT,5.RD,00011101001:MMI3:32::PSRAVW | |
9270 | *r5900: | |
9271 | { | |
9272 | unsigned32 instruction = instruction_0; | |
9273 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9274 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9275 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9276 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9277 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9278 | { | |
9279 | GPR_SD(destreg,0) = SIGNEXTEND( (RT_SW (0) >> (RS_UB(0) & 0x1F)), 32-(RS_UB(0) & 0x1F) ); | |
9280 | GPR_SD(destreg,1) = SIGNEXTEND( (RT_SW (2) >> (RS_UB(8) & 0x1F)), 32-(RS_UB(8) & 0x1F) ); | |
9281 | } | |
9282 | } | |
9283 | ||
9284 | // end-sanitize-r5900 | |
9285 | // start-sanitize-r5900 | |
9286 | ||
9287 | 01110000000,5.RT,5.RD,5.SA,111111:MMINORM:32::PSRAW | |
9288 | *r5900: | |
9289 | { | |
9290 | unsigned32 instruction = instruction_0; | |
9291 | int op1 UNUSED = ((instruction >> 6) & 0x0000001F); | |
9292 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9293 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9294 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9295 | { | |
9296 | int shift_by = op1 & (32-1); | |
9297 | int i; | |
9298 | for(i=0;i<WORDS_IN_MMI_REGS;i++) | |
9299 | GPR_SW(destreg,i) = SIGNEXTEND( (RT_SW(i) >> shift_by), (32-shift_by) ); | |
9300 | } | |
9301 | } | |
9302 | ||
9303 | // end-sanitize-r5900 | |
9304 | // start-sanitize-r5900 | |
9305 | ||
9306 | 01110000000,5.RT,5.RD,5.SA,110110:MMINORM:32::PSRLH | |
9307 | *r5900: | |
9308 | { | |
9309 | unsigned32 instruction = instruction_0; | |
9310 | int op1 UNUSED = ((instruction >> 6) & 0x0000001F); | |
9311 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9312 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9313 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9314 | { | |
9315 | int shift_by = op1 & (16-1); | |
9316 | int i; | |
9317 | for(i=0;i<HALFWORDS_IN_MMI_REGS;i++) | |
9318 | GPR_UH(destreg,i) = (RT_UH(i) >> shift_by); | |
9319 | } | |
9320 | } | |
9321 | ||
9322 | // end-sanitize-r5900 | |
9323 | // start-sanitize-r5900 | |
9324 | ||
9325 | 011100,5.RS,5.RT,5.RD,00011001001:MMI2:32::PSRLVW | |
9326 | *r5900: | |
9327 | { | |
9328 | unsigned32 instruction = instruction_0; | |
9329 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9330 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9331 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9332 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9333 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9334 | { | |
9335 | GPR_UD(destreg,0) = SIGNEXTEND ( RT_UW(0) >> (RS_UB(0) & 0x1F), 31); | |
9336 | GPR_UD(destreg,1) = SIGNEXTEND ( RT_UW(2) >> (RS_UB(8) & 0x1F), 31); | |
9337 | } | |
9338 | } | |
9339 | ||
9340 | // end-sanitize-r5900 | |
9341 | // start-sanitize-r5900 | |
9342 | ||
9343 | 01110000000,5.RT,5.RD,5.SA,111110:MMINORM:32::PSRLW | |
9344 | *r5900: | |
9345 | { | |
9346 | unsigned32 instruction = instruction_0; | |
9347 | int op1 UNUSED = ((instruction >> 6) & 0x0000001F); | |
9348 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9349 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9350 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9351 | { | |
9352 | int shift_by = op1 & (32-1); | |
9353 | int i; | |
9354 | for(i=0;i<WORDS_IN_MMI_REGS;i++) | |
9355 | GPR_UW(destreg,i) = (RT_UW(i) >> shift_by); | |
9356 | } | |
9357 | } | |
9358 | ||
9359 | // end-sanitize-r5900 | |
9360 | // start-sanitize-r5900 | |
9361 | ||
9362 | 011100,5.RS,5.RT,5.RD,01001001000:MMI0:32::PSUBB | |
9363 | *r5900: | |
9364 | { | |
9365 | unsigned32 instruction = instruction_0; | |
9366 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9367 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9368 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9369 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9370 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9371 | { | |
9372 | int i; | |
9373 | for (i=0; i < BYTES_IN_MMI_REGS; i++) | |
9374 | { | |
9375 | int s = RS_SB(i); | |
9376 | int t = RT_SB(i); | |
9377 | int r = s - t; | |
9378 | GPR_SB(destreg,i) = r; | |
9379 | } | |
9380 | } | |
9381 | } | |
9382 | ||
9383 | // end-sanitize-r5900 | |
9384 | // start-sanitize-r5900 | |
9385 | ||
9386 | 011100,5.RS,5.RT,5.RD,00101001000:MMI0:32::PSUBH | |
9387 | *r5900: | |
9388 | { | |
9389 | unsigned32 instruction = instruction_0; | |
9390 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9391 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9392 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9393 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9394 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9395 | { | |
9396 | int i; | |
9397 | for (i=0; i < HALFWORDS_IN_MMI_REGS; i++) | |
9398 | { | |
9399 | int s = RS_SH(i); | |
9400 | int t = RT_SH(i); | |
9401 | int r = s - t; | |
9402 | GPR_SH(destreg,i) = r; | |
9403 | } | |
9404 | } | |
9405 | } | |
9406 | ||
9407 | // end-sanitize-r5900 | |
9408 | // start-sanitize-r5900 | |
9409 | ||
9410 | 011100,5.RS,5.RT,5.RD,11001001000:MMI0:32::PSUBSB | |
9411 | *r5900: | |
9412 | { | |
9413 | unsigned32 instruction = instruction_0; | |
9414 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9415 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9416 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9417 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9418 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9419 | { | |
9420 | int i; | |
9421 | for (i=0; i < BYTES_IN_MMI_REGS; i++) | |
9422 | { | |
9423 | int s = RS_SB(i); | |
9424 | int t = RT_SB(i); | |
9425 | int r = s - t; | |
9426 | if (r > 127) | |
9427 | GPR_SB(destreg,i) = 127; | |
9428 | else if (r < -128) | |
9429 | GPR_SB(destreg,i) = -128; | |
9430 | else | |
9431 | GPR_SB(destreg,i) = r; | |
9432 | } | |
9433 | } | |
9434 | } | |
9435 | ||
9436 | // end-sanitize-r5900 | |
9437 | // start-sanitize-r5900 | |
9438 | ||
9439 | 011100,5.RS,5.RT,5.RD,10101001000:MMI0:32::PSUBSH | |
9440 | *r5900: | |
9441 | { | |
9442 | unsigned32 instruction = instruction_0; | |
9443 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9444 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9445 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9446 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9447 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9448 | { | |
9449 | int i; | |
9450 | for (i=0; i < HALFWORDS_IN_MMI_REGS; i++) | |
9451 | { | |
9452 | int s = RS_SH(i); | |
9453 | int t = RT_SH(i); | |
9454 | int r = s - t; | |
9455 | if (r > 32767) | |
9456 | GPR_SH(destreg,i) = 32767; | |
9457 | else if (r < -32768) | |
9458 | GPR_SH(destreg,i) = -32768; | |
9459 | else | |
9460 | GPR_SH(destreg,i) = r; | |
9461 | } | |
9462 | } | |
9463 | } | |
9464 | ||
9465 | // end-sanitize-r5900 | |
9466 | // start-sanitize-r5900 | |
9467 | ||
9468 | 011100,5.RS,5.RT,5.RD,10001001000:MMI0:32::PSUBSW | |
9469 | *r5900: | |
9470 | { | |
9471 | unsigned32 instruction = instruction_0; | |
9472 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9473 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9474 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9475 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9476 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9477 | { | |
9478 | int i; | |
9479 | for (i=0; i < WORDS_IN_MMI_REGS; i++) | |
9480 | { | |
9481 | signed64 s = RS_SW(i); | |
9482 | signed64 t = RT_SW(i); | |
9483 | signed64 r = s - t; | |
9484 | if (r > (int)0x7FFFFFFF) | |
9485 | GPR_SW(destreg,i) = (int)0x7FFFFFFF; | |
9486 | else if (r < (int)0x80000000) | |
9487 | GPR_SW(destreg,i) = (int)0x80000000; | |
9488 | else | |
9489 | GPR_SW(destreg,i) = r; | |
9490 | } | |
9491 | } | |
9492 | } | |
9493 | ||
9494 | // end-sanitize-r5900 | |
9495 | // start-sanitize-r5900 | |
9496 | ||
9497 | 011100,5.RS,5.RT,5.RD,11001101000:MMI1:32::PSUBUB | |
9498 | *r5900: | |
9499 | { | |
9500 | unsigned32 instruction = instruction_0; | |
9501 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9502 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9503 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9504 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9505 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9506 | { | |
9507 | int i; | |
9508 | for (i=0; i < BYTES_IN_MMI_REGS; i++) | |
9509 | { | |
9510 | unsigned int s = RS_UB(i); | |
9511 | unsigned int t = RT_UB(i); | |
9512 | unsigned int r = s - t; | |
9513 | if (r > 0xFF) | |
9514 | GPR_UB(destreg,i) = 0; | |
9515 | else | |
9516 | GPR_UB(destreg,i) = r; | |
9517 | } | |
9518 | } | |
9519 | } | |
9520 | ||
9521 | // end-sanitize-r5900 | |
9522 | // start-sanitize-r5900 | |
9523 | ||
9524 | 011100,5.RS,5.RT,5.RD,10101101000:MMI1:32::PSUBUH | |
9525 | *r5900: | |
9526 | { | |
9527 | unsigned32 instruction = instruction_0; | |
9528 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9529 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9530 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9531 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9532 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9533 | { | |
9534 | int i; | |
9535 | for (i=0; i < HALFWORDS_IN_MMI_REGS; i++) | |
9536 | { | |
9537 | unsigned int s = RS_UH(i); | |
9538 | unsigned int t = RT_UH(i); | |
9539 | unsigned int r = s - t; | |
9540 | if (r > 0xFFFF) | |
9541 | GPR_UH(destreg,i) = 0; | |
9542 | else | |
9543 | GPR_UH(destreg,i) = r; | |
9544 | } | |
9545 | } | |
9546 | } | |
9547 | ||
9548 | // end-sanitize-r5900 | |
9549 | // start-sanitize-r5900 | |
9550 | ||
9551 | 011100,5.RS,5.RT,5.RD,10001101000:MMI1:32::PSUBUW | |
9552 | *r5900: | |
9553 | { | |
9554 | unsigned32 instruction = instruction_0; | |
9555 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9556 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9557 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9558 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9559 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9560 | { | |
9561 | int i; | |
9562 | for (i=0; i < WORDS_IN_MMI_REGS; i++) | |
9563 | { | |
9564 | unsigned64 s = RS_UW(i); | |
9565 | unsigned64 t = RT_UW(i); | |
9566 | unsigned64 r = s - t; | |
9567 | if (r > 0xFFFFFFFF) | |
9568 | GPR_UW(destreg,i) = 0; | |
9569 | else | |
9570 | GPR_UW(destreg,i) = r; | |
9571 | } | |
9572 | } | |
9573 | } | |
9574 | ||
9575 | // end-sanitize-r5900 | |
9576 | // start-sanitize-r5900 | |
9577 | ||
9578 | 011100,5.RS,5.RT,5.RD,00001001000:MMI0:32::PSUBW | |
9579 | *r5900: | |
9580 | { | |
9581 | unsigned32 instruction = instruction_0; | |
9582 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9583 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9584 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9585 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9586 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9587 | { | |
9588 | int i; | |
9589 | for (i=0; i < WORDS_IN_MMI_REGS; i++) | |
9590 | { | |
9591 | signed64 s = RS_SW(i); | |
9592 | signed64 t = RT_SW(i); | |
9593 | signed64 r = s - t; | |
9594 | GPR_SW(destreg,i) = r; | |
9595 | } | |
9596 | } | |
9597 | } | |
9598 | ||
9599 | // end-sanitize-r5900 | |
9600 | // start-sanitize-r5900 | |
9601 | ||
9602 | 011100,5.RS,5.RT,5.RD,10011001001:MMI2:32::PXOR | |
9603 | *r5900: | |
9604 | { | |
9605 | unsigned32 instruction = instruction_0; | |
9606 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9607 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9608 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9609 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9610 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9611 | { | |
9612 | int i; | |
9613 | for(i=0;i<WORDS_IN_MMI_REGS;i++) | |
9614 | GPR_UW(destreg,i) = (RS_UW(i) ^ RT_UW(i)); | |
9615 | } | |
9616 | } | |
9617 | ||
9618 | // end-sanitize-r5900 | |
9619 | // start-sanitize-r5900 | |
9620 | ||
9621 | 011100,5.RS,5.RT,5.RD,11011101000:MMI1:32::QFSRV | |
9622 | *r5900: | |
9623 | { | |
9624 | unsigned32 instruction = instruction_0; | |
9625 | int destreg UNUSED = ((instruction >> 11) & 0x0000001F); | |
9626 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9627 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9628 | t_reg rs_reg UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9629 | t_reg rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)]; | |
9630 | { | |
9631 | int bytes = (SA / 8) % 16; | |
9632 | if (SA % 8) | |
9633 | SignalException(ReservedInstruction,instruction); | |
9634 | else | |
9635 | { | |
9636 | int i; | |
9637 | for(i=0;i<(16-bytes);i++) | |
9638 | GPR_SB(destreg,i) = RT_SB(bytes+i); | |
9639 | for(;i<16;i++) | |
9640 | GPR_SB(destreg,i) = RS_SB(i-(16-bytes)); | |
9641 | } | |
9642 | } | |
9643 | } | |
9644 | ||
9645 | // end-sanitize-r5900 | |
9646 | // start-sanitize-r5900 | |
9647 | ||
9648 | 011111,5.RS,5.RT,16.OFFSET:NORMAL:128::SQ | |
9649 | *r5900: | |
9650 | { | |
9651 | unsigned32 instruction = instruction_0; | |
9652 | t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
9653 | t_reg rt_reg UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9654 | t_reg rt_reg1 = GPR1[((instruction >> 16) & 0x0000001F)]; | |
9655 | t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9656 | { | |
9657 | unsigned64 vaddr = ((unsigned64)op1 + offset); | |
9658 | unsigned64 paddr; | |
9659 | int uncached; | |
9660 | if ((vaddr & 15) != 0) | |
9661 | SignalException(AddressStore); | |
9662 | else | |
9663 | { | |
9664 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
9665 | { | |
9666 | unsigned64 memval = 0; | |
9667 | unsigned64 memval1 = 0; | |
9668 | memval = rt_reg; | |
9669 | memval1 = rt_reg1; | |
9670 | { | |
9671 | StoreMemory(uncached,AccessLength_QUADWORD,memval,memval1,paddr,vaddr,isREAL); | |
9672 | } | |
9673 | } | |
9674 | } | |
9675 | } | |
9676 | } | |
9677 | ||
9678 | // end-sanitize-r5900 | |
9679 | \f | |
9680 | // start-sanitize-cygnus-never | |
9681 | ||
49a6eed5 AC |
9682 | // // FIXME FIXME FIXME What is this instruction? |
9683 | // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT> | |
9684 | // *mipsI: | |
9685 | // *mipsII: | |
9686 | // *mipsIII: | |
9687 | // *mipsIV: | |
9688 | // // start-sanitize-r5900 | |
9689 | // *r5900: | |
9690 | // // end-sanitize-r5900 | |
9691 | // *r3900: | |
9692 | // // start-sanitize-tx19 | |
9693 | // *tx19: | |
9694 | // // end-sanitize-tx19 | |
9695 | // { | |
9696 | // unsigned32 instruction = instruction_0; | |
9697 | // t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16); | |
9698 | // t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9699 | // t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9700 | // { | |
9701 | // if (CoProcPresent(3)) | |
9702 | // SignalException(CoProcessorUnusable); | |
9703 | // else | |
9704 | // SignalException(ReservedInstruction,instruction); | |
9705 | // } | |
9706 | // } | |
9707 | ||
9708 | // end-sanitize-cygnus-never | |
9709 | // start-sanitize-cygnus-never | |
9710 | ||
9711 | // // FIXME FIXME FIXME What is this? | |
9712 | // 11100,******,00001:RR:16::SDBBP | |
9713 | // *mips16: | |
9714 | // { | |
9715 | // unsigned32 instruction = instruction_0; | |
9716 | // if (have_extendval) | |
9717 | // SignalException (ReservedInstruction, instruction); | |
9718 | // { | |
9719 | // SignalException(DebugBreakPoint,instruction); | |
9720 | // } | |
9721 | // } | |
f2b30012 AC |
9722 | |
9723 | // end-sanitize-cygnus-never | |
9724 | // start-sanitize-cygnus-never | |
9725 | ||
49a6eed5 AC |
9726 | // // FIXME FIXME FIXME What is this? |
9727 | // 000000,********************,001110:SPECIAL:32::SDBBP | |
9728 | // *r3900: | |
9729 | // { | |
9730 | // unsigned32 instruction = instruction_0; | |
9731 | // { | |
9732 | // SignalException(DebugBreakPoint,instruction); | |
9733 | // } | |
9734 | // } | |
f2b30012 AC |
9735 | |
9736 | // end-sanitize-cygnus-never | |
9737 | // start-sanitize-cygnus-never | |
9738 | ||
49a6eed5 AC |
9739 | // // FIXME FIXME FIXME This apparently belongs to the vr4100 which |
9740 | // // isn't yet reconized by this simulator. | |
9741 | // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16 | |
9742 | // *vr4100: | |
9743 | // { | |
9744 | // unsigned32 instruction = instruction_0; | |
9745 | // t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9746 | // t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9747 | // { | |
9748 | // CHECKHILO("Multiply-Add"); | |
9749 | // { | |
9750 | // unsigned64 temp = (op1 * op2); | |
9751 | // temp += (SET64HI(VL4_8(HI)) | VL4_8(LO)); | |
9752 | // LO = SIGNEXTEND((unsigned64)VL4_8(temp),32); | |
9753 | // HI = SIGNEXTEND((unsigned64)VH4_8(temp),32); | |
9754 | // } | |
9755 | // } | |
9756 | // } | |
f2b30012 AC |
9757 | |
9758 | // end-sanitize-cygnus-never | |
49a6eed5 AC |
9759 | // start-sanitize-cygnus-never |
9760 | ||
9761 | // // FIXME FIXME FIXME This apparently belongs to the vr4100 which | |
9762 | // // isn't yet reconized by this simulator. | |
9763 | // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16 | |
9764 | // *vr4100: | |
9765 | // { | |
9766 | // unsigned32 instruction = instruction_0; | |
9767 | // t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)]; | |
9768 | // t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
9769 | // { | |
9770 | // CHECKHILO("Multiply-Add"); | |
9771 | // { | |
9772 | // unsigned64 temp = (op1 * op2); | |
9773 | // LO = LO + temp; | |
9774 | // } | |
9775 | // } | |
9776 | // } | |
9777 | ||
9778 | // start-sanitize-cygnus-never |