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[deliverable/binutils-gdb.git] / sim / mips / mips.igen
CommitLineData
ca6f76d1
AC		 1// -*- C -*-
2//
1ee7d2b1
FCE		 3// In mips.igen, the semantics for many of the instructions were created
4// using code generated by gencode. Those semantic segments could be
5// greatly simplified.
6//
f2b30012
AC		 7// <insn> ::=
8// <insn-word> { "+" <insn-word> }
9// ":" <format-name>
10// ":" <filter-flags>
11// ":" <options>
12// ":" <name>
13// <nl>
14// { <insn-model> }
15// { <insn-mnemonic> }
16// <code-block>
17//
18
19
20// IGEN config - mips16
a48e8c8d
AC		 21// :option:16::insn-bit-size:16
22// :option:16::hi-bit-nr:15
89d09738
AC		 23:option:16::insn-specifying-widths:true
24:option:16::gen-delayed-branch:false
f2b30012 25
90ad43b2 26// IGEN config - mips32/64..
a48e8c8d
AC		 27// :option:32::insn-bit-size:32
28// :option:32::hi-bit-nr:31
89d09738
AC		 29:option:32::insn-specifying-widths:true
30:option:32::gen-delayed-branch:false
f2b30012
AC		 31
32
49a6eed5 33// Generate separate simulators for each target
89d09738 34// :option:::multi-sim:true
49a6eed5 35
f2b30012
AC		 36
37// Models known by this simulator
15232df4
FCE		 38:model:::mipsI:mips3000:
39:model:::mipsII:mips6000:
40:model:::mipsIII:mips4000:
41:model:::mipsIV:mips8000:
89d09738 42:model:::mips16:mips16:
f2b30012 43// start-sanitize-r5900
a48e8c8d 44:model:::r5900:mips5900:
f2b30012 45// end-sanitize-r5900
a48e8c8d 46:model:::r3900:mips3900:
f2b30012 47// start-sanitize-tx19
89d09738 48:model:::tx19:tx19:
f2b30012 49// end-sanitize-tx19
a83d7d87 50:model:::vr4100:mips4100:
f14397f0
GRK		 51// start-sanitize-vr4xxx
52:model:::vr4121:mips4121:
53// end-sanitize-vr4xxx
15232df4
FCE		 54// start-sanitize-vr4320
55:model:::vr4320:mips4320:
56// end-sanitize-vr4320
a83d7d87 57// start-sanitize-cygnus
a48e8c8d 58:model:::vr5400:mips5400:
23850e92 59:model:::mdmx:mdmx:
a83d7d87 60// end-sanitize-cygnus
a48e8c8d 61:model:::vr5000:mips5000:
f2b30012
AC		 62
63
64
65// Pseudo instructions known by IGEN
89d09738 66:internal::::illegal:
f2b30012 67{
030843d7 68 SignalException (ReservedInstruction, 0);
f2b30012
AC		 69}
70
71
030843d7
AC		 72// Pseudo instructions known by interp.c
73// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
74000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
75"rsvd <OP>"
76{
77 SignalException (ReservedInstruction, instruction_0);
78}
79
f2b30012
AC		 80
81
f3bdd368
AC		 82// Helper:
83//
84// Simulate a 32 bit delayslot instruction
85//
86
87:function:::address_word:delayslot32:address_word target
88{
89 instruction_word delay_insn;
90 sim_events_slip (SD, 1);
91 DSPC = CIA;
92 CIA = CIA + 4; /* NOTE not mips16 */
93 STATE |= simDELAYSLOT;
94 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
95 idecode_issue (CPU_, delay_insn, (CIA));
96 STATE &= ~simDELAYSLOT;
97 return target;
98}
99
100:function:::address_word:nullify_next_insn32:
101{
102 sim_events_slip (SD, 1);
103 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
104 return CIA + 8;
105}
106
a83d7d87
AC		 107// start-sanitize-branchbug4011
108:function:::void:check_4011_branch_bug:
109{
110 if (BRANCHBUG4011_OPTION == 2 && BRANCHBUG4011_LAST_TARGET == CIA)
111 sim_engine_abort (SD, CPU, CIA, "4011 BRANCH BUG: %s at 0x%08lx was target of branch at 0x%08lx\n",
112 itable[MY_INDEX].name,
113 (long) CIA,
114 (long) BRANCHBUG4011_LAST_CIA);
115}
f3bdd368 116
a83d7d87
AC		 117:function:::void:mark_4011_branch_bug:address_word target
118{
119 if (BRANCHBUG4011_OPTION)
120 {
121 BRANCHBUG4011_OPTION = 2;
122 BRANCHBUG4011_LAST_TARGET = target;
123 BRANCHBUG4011_LAST_CIA = CIA;
124 }
125}
f3bdd368 126
a83d7d87 127// end-sanitize-branchbug4011
421cbaae
AC		 128// Helper:
129//
130// Check that an access to a HI/LO register meets timing requirements
131//
132// The following requirements exist:
133//
134// - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
135// - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
136// - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
137// corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
138//
139
140:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
141{
142 if (history->mf.timestamp + 3 > time)
143 {
144 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
145 itable[MY_INDEX].name,
146 new, (long) CIA,
147 (long) history->mf.cia);
148 return 0;
149 }
150 return 1;
151}
152
153:function:::int:check_mt_hilo:hilo_history *history
3fa454e9 154*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 155*vr4100:
3fa454e9 156*vr5000:
f14397f0
GRK		 157// start-sanitize-vr4xxx
158*vr4121:
159// end-sanitize-vr4xxx
3fa454e9
FCE		 160// start-sanitize-vr4320
161*vr4320:
162// end-sanitize-vr4320
a83d7d87 163// start-sanitize-cygnus
3fa454e9 164*vr5400:
a83d7d87 165// end-sanitize-cygnus
421cbaae
AC		 166{
167 signed64 time = sim_events_time (SD);
168 int ok = check_mf_cycles (SD_, history, time, "MT");
169 history->mt.timestamp = time;
170 history->mt.cia = CIA;
171 return ok;
172}
173
3fa454e9
FCE		 174:function:::int:check_mt_hilo:hilo_history *history
175*r3900:
176// start-sanitize-tx19
177*tx19:
178// end-sanitize-tx19
0e797366
AC		 179// start-sanitize-r5900
180*r5900:
181// end-sanitize-r5900
3fa454e9
FCE		 182{
183 signed64 time = sim_events_time (SD);
184 history->mt.timestamp = time;
185 history->mt.cia = CIA;
186 return 1;
187}
188
0e797366 189
421cbaae 190:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
0e797366 191*mipsI,mipsII,mipsIII,mipsIV:
57791952 192*vr4100:
0e797366 193*vr5000:
f14397f0
GRK		 194// start-sanitize-vr4xxx
195*vr4121:
196// end-sanitize-vr4xxx
0e797366
AC		 197// start-sanitize-vr4320
198*vr4320:
199// end-sanitize-vr4320
a83d7d87 200// start-sanitize-cygnus
0e797366 201*vr5400:
a83d7d87 202// end-sanitize-cygnus
0e797366
AC		 203*r3900:
204// start-sanitize-tx19
205*tx19:
206// end-sanitize-tx19
421cbaae
AC		 207{
208 signed64 time = sim_events_time (SD);
209 int ok = 1;
210 if (peer != NULL
211 && peer->mt.timestamp > history->op.timestamp
aaa2c908
GRK		 212 && history->mt.timestamp < history->op.timestamp
213 && ! (history->mf.timestamp > history->op.timestamp
214 && history->mf.timestamp < peer->mt.timestamp)
215 && ! (peer->mf.timestamp > history->op.timestamp
216 && peer->mf.timestamp < peer->mt.timestamp))
421cbaae
AC		 217 {
218 /* The peer has been written to since the last OP yet we have
219 not */
220 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
221 itable[MY_INDEX].name,
222 (long) CIA,
223 (long) history->op.cia,
224 (long) peer->mt.cia);
225 ok = 0;
226 }
227 history->mf.timestamp = time;
228 history->mf.cia = CIA;
229 return ok;
230}
231
0e797366
AC		 232// start-sanitize-r5900
233// The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
234:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
235// end-sanitize-r5900
236// start-sanitize-r5900
237*r5900:
238// end-sanitize-r5900
239// start-sanitize-r5900
240{
241 /* FIXME: could record the fact that a stall occured if we want */
242 signed64 time = sim_events_time (SD);
243 history->mf.timestamp = time;
244 history->mf.cia = CIA;
245 return 1;
246}
247// end-sanitize-r5900
248
249
94dda41a
GRK		 250:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
251*mipsI,mipsII,mipsIII,mipsIV:
57791952 252*vr4100:
94dda41a 253*vr5000:
f14397f0
GRK		 254// start-sanitize-vr4xxx
255*vr4121:
256// end-sanitize-vr4xxx
94dda41a
GRK		 257// start-sanitize-vr4320
258*vr4320:
259// end-sanitize-vr4320
a83d7d87 260// start-sanitize-cygnus
94dda41a 261*vr5400:
a83d7d87 262// end-sanitize-cygnus
94dda41a
GRK		 263{
264 signed64 time = sim_events_time (SD);
265 int ok = (check_mf_cycles (SD_, hi, time, "OP")
266 && check_mf_cycles (SD_, lo, time, "OP"));
267 hi->op.timestamp = time;
268 lo->op.timestamp = time;
269 hi->op.cia = CIA;
270 lo->op.cia = CIA;
271 return ok;
272}
273
94dda41a
GRK		 274// The r3900 mult and multu insns _can_ be exectuted immediatly after
275// a mf{hi,lo}
276:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
277*r3900:
278// start-sanitize-tx19
279*tx19:
280// end-sanitize-tx19
0e797366
AC		 281// start-sanitize-r5900
282*r5900:
283// end-sanitize-r5900
94dda41a 284{
0e797366 285 /* FIXME: could record the fact that a stall occured if we want */
94dda41a
GRK		 286 signed64 time = sim_events_time (SD);
287 hi->op.timestamp = time;
288 lo->op.timestamp = time;
289 hi->op.cia = CIA;
290 lo->op.cia = CIA;
291 return 1;
292}
293
0e797366 294
94dda41a 295:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
421cbaae 296*mipsI,mipsII,mipsIII,mipsIV:
57791952 297*vr4100:
421cbaae 298*vr5000:
f14397f0
GRK		 299// start-sanitize-vr4xxx
300*vr4121:
301// end-sanitize-vr4xxx
421cbaae
AC		 302// start-sanitize-vr4320
303*vr4320:
304// end-sanitize-vr4320
a83d7d87 305// start-sanitize-cygnus
421cbaae 306*vr5400:
a83d7d87 307// end-sanitize-cygnus
421cbaae
AC		 308*r3900:
309// start-sanitize-tx19
310*tx19:
311// end-sanitize-tx19
421cbaae
AC		 312{
313 signed64 time = sim_events_time (SD);
314 int ok = (check_mf_cycles (SD_, hi, time, "OP")
315 && check_mf_cycles (SD_, lo, time, "OP"));
316 hi->op.timestamp = time;
317 lo->op.timestamp = time;
318 hi->op.cia = CIA;
319 lo->op.cia = CIA;
320 return ok;
321}
322
323
0e797366
AC		 324// start-sanitize-r5900
325// The r5900 div et.al insns _can_ be exectuted immediatly after
326// a mf{hi,lo}
327:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
328// end-sanitize-r5900
329// start-sanitize-r5900
330*r5900:
331// end-sanitize-r5900
332// start-sanitize-r5900
333{
334 /* FIXME: could record the fact that a stall occured if we want */
335 signed64 time = sim_events_time (SD);
336 hi->op.timestamp = time;
337 lo->op.timestamp = time;
338 hi->op.cia = CIA;
339 lo->op.cia = CIA;
340 return 1;
341}
342// end-sanitize-r5900
343
344
421cbaae 345
f2b30012 346//
7ce8b917 347// Mips Architecture:
f2b30012
AC		 348//
349// CPU Instruction Set (mipsI - mipsIV)
350//
351
352
c0a4c3ba 353
f2b30012
AC		 354000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
355"add r<RD>, r<RS>, r<RT>"
23850e92 356*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 357*vr4100:
23850e92 358*vr5000:
f14397f0
GRK		 359// start-sanitize-vr4xxx
360*vr4121:
361// end-sanitize-vr4xxx
15232df4
FCE		 362// start-sanitize-vr4320
363*vr4320:
364// end-sanitize-vr4320
a83d7d87 365// start-sanitize-cygnus
90ad43b2 366*vr5400:
a83d7d87 367// end-sanitize-cygnus
f2b30012
AC		 368// start-sanitize-r5900
369*r5900:
370// end-sanitize-r5900
371*r3900:
372// start-sanitize-tx19
373*tx19:
374// end-sanitize-tx19
375{
26feb3a8
AC		 376 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
377 {
378 ALU32_BEGIN (GPR[RS]);
379 ALU32_ADD (GPR[RT]);
380 ALU32_END (GPR[RD]);
381 }
382 TRACE_ALU_RESULT (GPR[RD]);
f2b30012
AC		 383}
384
385
c0a4c3ba 386
f2b30012
AC		 387001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
388"addi r<RT>, r<RS>, IMMEDIATE"
23850e92 389*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 390*vr4100:
23850e92 391*vr5000:
f14397f0
GRK		 392// start-sanitize-vr4xxx
393*vr4121:
394// end-sanitize-vr4xxx
15232df4
FCE		 395// start-sanitize-vr4320
396*vr4320:
397// end-sanitize-vr4320
a83d7d87 398// start-sanitize-cygnus
90ad43b2 399*vr5400:
a83d7d87 400// end-sanitize-cygnus
f2b30012
AC		 401// start-sanitize-r5900
402*r5900:
403// end-sanitize-r5900
404*r3900:
405// start-sanitize-tx19
406*tx19:
407// end-sanitize-tx19
408{
26feb3a8
AC		 409 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
410 {
411 ALU32_BEGIN (GPR[RS]);
412 ALU32_ADD (EXTEND16 (IMMEDIATE));
413 ALU32_END (GPR[RT]);
414 }
415 TRACE_ALU_RESULT (GPR[RT]);
f2b30012
AC		 416}
417
418
c0a4c3ba
AC		 419
420:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
421{
f3bdd368
AC		 422 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
423 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
424 TRACE_ALU_RESULT (GPR[rt]);
c0a4c3ba
AC		 425}
426
f2b30012 427001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
f3bdd368 428"addiu r<RT>, r<RS>, <IMMEDIATE>"
23850e92 429*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 430*vr4100:
23850e92 431*vr5000:
f14397f0
GRK		 432// start-sanitize-vr4xxx
433*vr4121:
434// end-sanitize-vr4xxx
15232df4
FCE		 435// start-sanitize-vr4320
436*vr4320:
437// end-sanitize-vr4320
a83d7d87 438// start-sanitize-cygnus
90ad43b2 439*vr5400:
a83d7d87 440// end-sanitize-cygnus
f2b30012
AC		 441// start-sanitize-r5900
442*r5900:
443// end-sanitize-r5900
444*r3900:
445// start-sanitize-tx19
446*tx19:
447// end-sanitize-tx19
448{
c0a4c3ba 449 do_addiu (SD_, RS, RT, IMMEDIATE);
f2b30012
AC		 450}
451
452
c0a4c3ba
AC		 453
454:function:::void:do_addu:int rs, int rt, int rd
455{
f3bdd368
AC		 456 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
457 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
458 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 459}
460
f2b30012 461000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
ebcfd86a 462"addu r<RD>, r<RS>, r<RT>"
23850e92 463*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 464*vr4100:
23850e92 465*vr5000:
f14397f0
GRK		 466// start-sanitize-vr4xxx
467*vr4121:
468// end-sanitize-vr4xxx
15232df4
FCE		 469// start-sanitize-vr4320
470*vr4320:
471// end-sanitize-vr4320
a83d7d87 472// start-sanitize-cygnus
90ad43b2 473*vr5400:
a83d7d87 474// end-sanitize-cygnus
f2b30012
AC		 475// start-sanitize-r5900
476*r5900:
477// end-sanitize-r5900
478*r3900:
479// start-sanitize-tx19
480*tx19:
481// end-sanitize-tx19
482{
c0a4c3ba 483 do_addu (SD_, RS, RT, RD);
f2b30012
AC		 484}
485
486
c0a4c3ba
AC		 487
488:function:::void:do_and:int rs, int rt, int rd
489{
f3bdd368 490 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 491 GPR[rd] = GPR[rs] & GPR[rt];
f3bdd368 492 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 493}
494
f2b30012
AC		 495000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
496"and r<RD>, r<RS>, r<RT>"
23850e92 497*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 498*vr4100:
23850e92 499*vr5000:
f14397f0
GRK		 500// start-sanitize-vr4xxx
501*vr4121:
502// end-sanitize-vr4xxx
15232df4
FCE		 503// start-sanitize-vr4320
504*vr4320:
505// end-sanitize-vr4320
a83d7d87 506// start-sanitize-cygnus
90ad43b2 507*vr5400:
a83d7d87 508// end-sanitize-cygnus
f2b30012
AC		 509// start-sanitize-r5900
510*r5900:
511// end-sanitize-r5900
512*r3900:
513// start-sanitize-tx19
514*tx19:
515// end-sanitize-tx19
516{
c0a4c3ba 517 do_and (SD_, RS, RT, RD);
f2b30012
AC		 518}
519
520
c0a4c3ba 521
f2b30012 522001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
23850e92
JL		 523"and r<RT>, r<RS>, <IMMEDIATE>"
524*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 525*vr4100:
23850e92 526*vr5000:
f14397f0
GRK		 527// start-sanitize-vr4xxx
528*vr4121:
529// end-sanitize-vr4xxx
15232df4
FCE		 530// start-sanitize-vr4320
531*vr4320:
532// end-sanitize-vr4320
a83d7d87 533// start-sanitize-cygnus
90ad43b2 534*vr5400:
a83d7d87 535// end-sanitize-cygnus
f2b30012
AC		 536// start-sanitize-r5900
537*r5900:
538// end-sanitize-r5900
539*r3900:
540// start-sanitize-tx19
541*tx19:
542// end-sanitize-tx19
543{
97f4d183 544 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
055ee297 545 GPR[RT] = GPR[RS] & IMMEDIATE;
97f4d183 546 TRACE_ALU_RESULT (GPR[RT]);
f2b30012
AC		 547}
548
549
c0a4c3ba 550
f2b30012 551000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
7ce8b917 552"beq r<RS>, r<RT>, <OFFSET>"
23850e92 553*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 554*vr4100:
23850e92 555*vr5000:
f14397f0
GRK		 556// start-sanitize-vr4xxx
557*vr4121:
558// end-sanitize-vr4xxx
15232df4
FCE		 559// start-sanitize-vr4320
560*vr4320:
561// end-sanitize-vr4320
a83d7d87 562// start-sanitize-cygnus
90ad43b2 563*vr5400:
a83d7d87 564// end-sanitize-cygnus
f2b30012
AC		 565// start-sanitize-r5900
566*r5900:
567// end-sanitize-r5900
568*r3900:
569// start-sanitize-tx19
570*tx19:
571// end-sanitize-tx19
572{
055ee297 573 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 574 check_branch_bug ();
030843d7 575 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
a83d7d87
AC		 576 {
577 mark_branch_bug (NIA+offset);
578 DELAY_SLOT (NIA + offset);
579 }
f2b30012
AC		 580}
581
582
c0a4c3ba 583
f2b30012
AC		 584010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
585"beql r<RS>, r<RT>, <OFFSET>"
586*mipsII:
587*mipsIII:
588*mipsIV:
1ee7d2b1 589*vr4100:
23850e92 590*vr5000:
f14397f0
GRK		 591// start-sanitize-vr4xxx
592*vr4121:
593// end-sanitize-vr4xxx
15232df4
FCE		 594// start-sanitize-vr4320
595*vr4320:
596// end-sanitize-vr4320
a83d7d87 597// start-sanitize-cygnus
90ad43b2 598*vr5400:
a83d7d87 599// end-sanitize-cygnus
f2b30012
AC		 600// start-sanitize-r5900
601*r5900:
602// end-sanitize-r5900
603*r3900:
604// start-sanitize-tx19
605*tx19:
606// end-sanitize-tx19
607{
055ee297 608 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 609 check_branch_bug ();
030843d7 610 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
a83d7d87
AC		 611 {
612 mark_branch_bug (NIA+offset);
613 DELAY_SLOT (NIA + offset);
614 }
055ee297 615 else
49a76833 616 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 617}
618
619
c0a4c3ba 620
f2b30012
AC		 621000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
622"bgez r<RS>, <OFFSET>"
23850e92 623*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 624*vr4100:
23850e92 625*vr5000:
f14397f0
GRK		 626// start-sanitize-vr4xxx
627*vr4121:
628// end-sanitize-vr4xxx
15232df4
FCE		 629// start-sanitize-vr4320
630*vr4320:
631// end-sanitize-vr4320
a83d7d87 632// start-sanitize-cygnus
90ad43b2 633*vr5400:
a83d7d87 634// end-sanitize-cygnus
f2b30012
AC		 635// start-sanitize-r5900
636*r5900:
637// end-sanitize-r5900
638*r3900:
639// start-sanitize-tx19
640*tx19:
641// end-sanitize-tx19
642{
055ee297 643 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 644 check_branch_bug ();
030843d7 645 if ((signed_word) GPR[RS] >= 0)
a83d7d87
AC		 646 {
647 mark_branch_bug (NIA+offset);
648 DELAY_SLOT (NIA + offset);
649 }
f2b30012
AC		 650}
651
652
c0a4c3ba 653
f2b30012
AC		 654000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
655"bgezal r<RS>, <OFFSET>"
23850e92 656*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 657*vr4100:
23850e92 658*vr5000:
f14397f0
GRK		 659// start-sanitize-vr4xxx
660*vr4121:
661// end-sanitize-vr4xxx
15232df4
FCE		 662// start-sanitize-vr4320
663*vr4320:
664// end-sanitize-vr4320
a83d7d87 665// start-sanitize-cygnus
90ad43b2 666*vr5400:
a83d7d87 667// end-sanitize-cygnus
f2b30012
AC		 668// start-sanitize-r5900
669*r5900:
670// end-sanitize-r5900
671*r3900:
672// start-sanitize-tx19
673*tx19:
674// end-sanitize-tx19
675{
055ee297 676 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 677 check_branch_bug ();
055ee297 678 RA = (CIA + 8);
030843d7 679 if ((signed_word) GPR[RS] >= 0)
a83d7d87
AC		 680 {
681 mark_branch_bug (NIA+offset);
682 DELAY_SLOT (NIA + offset);
683 }
f2b30012
AC		 684}
685
686
c0a4c3ba 687
f2b30012
AC		 688000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
689"bgezall r<RS>, <OFFSET>"
690*mipsII:
691*mipsIII:
692*mipsIV:
1ee7d2b1 693*vr4100:
23850e92 694*vr5000:
f14397f0
GRK		 695// start-sanitize-vr4xxx
696*vr4121:
697// end-sanitize-vr4xxx
15232df4
FCE		 698// start-sanitize-vr4320
699*vr4320:
700// end-sanitize-vr4320
a83d7d87 701// start-sanitize-cygnus
90ad43b2 702*vr5400:
a83d7d87 703// end-sanitize-cygnus
f2b30012
AC		 704// start-sanitize-r5900
705*r5900:
706// end-sanitize-r5900
707*r3900:
708// start-sanitize-tx19
709*tx19:
710// end-sanitize-tx19
711{
055ee297 712 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 713 check_branch_bug ();
055ee297 714 RA = (CIA + 8);
f2b30012
AC		 715 /* NOTE: The branch occurs AFTER the next instruction has been
716 executed */
030843d7 717 if ((signed_word) GPR[RS] >= 0)
a83d7d87
AC		 718 {
719 mark_branch_bug (NIA+offset);
720 DELAY_SLOT (NIA + offset);
721 }
f2b30012 722 else
49a76833 723 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 724}
725
726
c0a4c3ba 727
f2b30012
AC		 728000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
729"bgezl r<RS>, <OFFSET>"
730*mipsII:
731*mipsIII:
732*mipsIV:
1ee7d2b1 733*vr4100:
23850e92 734*vr5000:
f14397f0
GRK		 735// start-sanitize-vr4xxx
736*vr4121:
737// end-sanitize-vr4xxx
15232df4
FCE		 738// start-sanitize-vr4320
739*vr4320:
740// end-sanitize-vr4320
a83d7d87 741// start-sanitize-cygnus
90ad43b2 742*vr5400:
a83d7d87 743// end-sanitize-cygnus
f2b30012
AC		 744// start-sanitize-r5900
745*r5900:
746// end-sanitize-r5900
747*r3900:
748// start-sanitize-tx19
749*tx19:
750// end-sanitize-tx19
751{
055ee297 752 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 753 check_branch_bug ();
030843d7 754 if ((signed_word) GPR[RS] >= 0)
a83d7d87
AC		 755 {
756 mark_branch_bug (NIA+offset);
757 DELAY_SLOT (NIA + offset);
758 }
f2b30012 759 else
49a76833 760 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 761}
762
763
c0a4c3ba 764
f2b30012
AC		 765000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
766"bgtz r<RS>, <OFFSET>"
23850e92 767*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 768*vr4100:
23850e92 769*vr5000:
f14397f0
GRK		 770// start-sanitize-vr4xxx
771*vr4121:
772// end-sanitize-vr4xxx
15232df4
FCE		 773// start-sanitize-vr4320
774*vr4320:
775// end-sanitize-vr4320
a83d7d87 776// start-sanitize-cygnus
90ad43b2 777*vr5400:
a83d7d87 778// end-sanitize-cygnus
f2b30012
AC		 779// start-sanitize-r5900
780*r5900:
781// end-sanitize-r5900
782*r3900:
783// start-sanitize-tx19
784*tx19:
785// end-sanitize-tx19
786{
055ee297 787 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 788 check_branch_bug ();
030843d7 789 if ((signed_word) GPR[RS] > 0)
a83d7d87
AC		 790 {
791 mark_branch_bug (NIA+offset);
792 DELAY_SLOT (NIA + offset);
793 }
f2b30012
AC		 794}
795
796
c0a4c3ba 797
f2b30012
AC		 798010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
799"bgtzl r<RS>, <OFFSET>"
800*mipsII:
801*mipsIII:
802*mipsIV:
1ee7d2b1 803*vr4100:
23850e92 804*vr5000:
f14397f0
GRK		 805// start-sanitize-vr4xxx
806*vr4121:
807// end-sanitize-vr4xxx
15232df4
FCE		 808// start-sanitize-vr4320
809*vr4320:
810// end-sanitize-vr4320
a83d7d87 811// start-sanitize-cygnus
90ad43b2 812*vr5400:
a83d7d87 813// end-sanitize-cygnus
f2b30012
AC		 814// start-sanitize-r5900
815*r5900:
816// end-sanitize-r5900
817*r3900:
818// start-sanitize-tx19
819*tx19:
820// end-sanitize-tx19
821{
055ee297 822 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 823 check_branch_bug ();
f2b30012
AC		 824 /* NOTE: The branch occurs AFTER the next instruction has been
825 executed */
030843d7 826 if ((signed_word) GPR[RS] > 0)
a83d7d87
AC		 827 {
828 mark_branch_bug (NIA+offset);
829 DELAY_SLOT (NIA + offset);
830 }
f2b30012 831 else
49a76833 832 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 833}
834
835
c0a4c3ba 836
f2b30012
AC		 837000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
838"blez r<RS>, <OFFSET>"
23850e92 839*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 840*vr4100:
23850e92 841*vr5000:
f14397f0
GRK		 842// start-sanitize-vr4xxx
843*vr4121:
844// end-sanitize-vr4xxx
15232df4
FCE		 845// start-sanitize-vr4320
846*vr4320:
847// end-sanitize-vr4320
a83d7d87 848// start-sanitize-cygnus
90ad43b2 849*vr5400:
a83d7d87 850// end-sanitize-cygnus
f2b30012
AC		 851// start-sanitize-r5900
852*r5900:
853// end-sanitize-r5900
854*r3900:
855// start-sanitize-tx19
856*tx19:
857// end-sanitize-tx19
858{
055ee297 859 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 860 check_branch_bug ();
f2b30012
AC		 861 /* NOTE: The branch occurs AFTER the next instruction has been
862 executed */
030843d7 863 if ((signed_word) GPR[RS] <= 0)
a83d7d87
AC		 864 {
865 mark_branch_bug (NIA+offset);
866 DELAY_SLOT (NIA + offset);
867 }
f2b30012
AC		 868}
869
870
c0a4c3ba 871
f2b30012
AC		 872010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
873"bgezl r<RS>, <OFFSET>"
874*mipsII:
875*mipsIII:
876*mipsIV:
1ee7d2b1 877*vr4100:
23850e92 878*vr5000:
f14397f0
GRK		 879// start-sanitize-vr4xxx
880*vr4121:
881// end-sanitize-vr4xxx
15232df4
FCE		 882// start-sanitize-vr4320
883*vr4320:
884// end-sanitize-vr4320
a83d7d87 885// start-sanitize-cygnus
90ad43b2 886*vr5400:
a83d7d87 887// end-sanitize-cygnus
f2b30012
AC		 888// start-sanitize-r5900
889*r5900:
890// end-sanitize-r5900
891*r3900:
892// start-sanitize-tx19
893*tx19:
894// end-sanitize-tx19
895{
055ee297 896 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 897 check_branch_bug ();
030843d7 898 if ((signed_word) GPR[RS] <= 0)
a83d7d87
AC		 899 {
900 mark_branch_bug (NIA+offset);
901 DELAY_SLOT (NIA + offset);
902 }
f2b30012 903 else
49a76833 904 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 905}
906
907
c0a4c3ba 908
f2b30012
AC		 909000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
910"bltz r<RS>, <OFFSET>"
23850e92 911*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 912*vr4100:
23850e92 913*vr5000:
f14397f0
GRK		 914// start-sanitize-vr4xxx
915*vr4121:
916// end-sanitize-vr4xxx
15232df4
FCE		 917// start-sanitize-vr4320
918*vr4320:
919// end-sanitize-vr4320
a83d7d87 920// start-sanitize-cygnus
90ad43b2 921*vr5400:
a83d7d87 922// end-sanitize-cygnus
f2b30012
AC		 923// start-sanitize-r5900
924*r5900:
925// end-sanitize-r5900
926*r3900:
927// start-sanitize-tx19
928*tx19:
929// end-sanitize-tx19
930{
055ee297 931 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 932 check_branch_bug ();
030843d7 933 if ((signed_word) GPR[RS] < 0)
a83d7d87
AC		 934 {
935 mark_branch_bug (NIA+offset);
936 DELAY_SLOT (NIA + offset);
937 }
f2b30012
AC		 938}
939
940
c0a4c3ba 941
f2b30012
AC		 942000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
943"bltzal r<RS>, <OFFSET>"
23850e92 944*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 945*vr4100:
23850e92 946*vr5000:
f14397f0
GRK		 947// start-sanitize-vr4xxx
948*vr4121:
949// end-sanitize-vr4xxx
15232df4
FCE		 950// start-sanitize-vr4320
951*vr4320:
952// end-sanitize-vr4320
a83d7d87 953// start-sanitize-cygnus
90ad43b2 954*vr5400:
a83d7d87 955// end-sanitize-cygnus
f2b30012
AC		 956// start-sanitize-r5900
957*r5900:
958// end-sanitize-r5900
959*r3900:
960// start-sanitize-tx19
961*tx19:
962// end-sanitize-tx19
963{
055ee297 964 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 965 check_branch_bug ();
055ee297 966 RA = (CIA + 8);
f2b30012
AC		 967 /* NOTE: The branch occurs AFTER the next instruction has been
968 executed */
030843d7 969 if ((signed_word) GPR[RS] < 0)
a83d7d87
AC		 970 {
971 mark_branch_bug (NIA+offset);
972 DELAY_SLOT (NIA + offset);
973 }
f2b30012
AC		 974}
975
976
c0a4c3ba 977
f2b30012
AC		 978000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
979"bltzall r<RS>, <OFFSET>"
980*mipsII:
981*mipsIII:
982*mipsIV:
1ee7d2b1 983*vr4100:
23850e92 984*vr5000:
f14397f0
GRK		 985// start-sanitize-vr4xxx
986*vr4121:
987// end-sanitize-vr4xxx
15232df4
FCE		 988// start-sanitize-vr4320
989*vr4320:
990// end-sanitize-vr4320
a83d7d87 991// start-sanitize-cygnus
90ad43b2 992*vr5400:
a83d7d87 993// end-sanitize-cygnus
f2b30012
AC		 994// start-sanitize-r5900
995*r5900:
996// end-sanitize-r5900
997*r3900:
998// start-sanitize-tx19
999*tx19:
1000// end-sanitize-tx19
1001{
055ee297 1002 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 1003 check_branch_bug ();
055ee297 1004 RA = (CIA + 8);
030843d7 1005 if ((signed_word) GPR[RS] < 0)
a83d7d87
AC		 1006 {
1007 mark_branch_bug (NIA+offset);
1008 DELAY_SLOT (NIA + offset);
1009 }
f2b30012 1010 else
49a76833 1011 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 1012}
1013
1014
c0a4c3ba 1015
f2b30012
AC		 1016000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
1017"bltzl r<RS>, <OFFSET>"
1018*mipsII:
1019*mipsIII:
1020*mipsIV:
1ee7d2b1 1021*vr4100:
23850e92 1022*vr5000:
f14397f0
GRK		 1023// start-sanitize-vr4xxx
1024*vr4121:
1025// end-sanitize-vr4xxx
15232df4
FCE		 1026// start-sanitize-vr4320
1027*vr4320:
1028// end-sanitize-vr4320
a83d7d87 1029// start-sanitize-cygnus
90ad43b2 1030*vr5400:
a83d7d87 1031// end-sanitize-cygnus
f2b30012
AC		 1032// start-sanitize-r5900
1033*r5900:
1034// end-sanitize-r5900
1035*r3900:
1036// start-sanitize-tx19
1037*tx19:
1038// end-sanitize-tx19
1039{
055ee297 1040 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 1041 check_branch_bug ();
f2b30012
AC		 1042 /* NOTE: The branch occurs AFTER the next instruction has been
1043 executed */
030843d7 1044 if ((signed_word) GPR[RS] < 0)
a83d7d87
AC		 1045 {
1046 mark_branch_bug (NIA+offset);
1047 DELAY_SLOT (NIA + offset);
1048 }
f2b30012 1049 else
49a76833 1050 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 1051}
1052
1053
c0a4c3ba 1054
f2b30012
AC		 1055000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
1056"bne r<RS>, r<RT>, <OFFSET>"
23850e92 1057*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 1058*vr4100:
23850e92 1059*vr5000:
f14397f0
GRK		 1060// start-sanitize-vr4xxx
1061*vr4121:
1062// end-sanitize-vr4xxx
15232df4
FCE		 1063// start-sanitize-vr4320
1064*vr4320:
1065// end-sanitize-vr4320
a83d7d87 1066// start-sanitize-cygnus
90ad43b2 1067*vr5400:
a83d7d87 1068// end-sanitize-cygnus
f2b30012
AC		 1069// start-sanitize-r5900
1070*r5900:
1071// end-sanitize-r5900
1072*r3900:
1073// start-sanitize-tx19
1074*tx19:
1075// end-sanitize-tx19
1076{
055ee297 1077 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 1078 check_branch_bug ();
030843d7 1079 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
a83d7d87
AC		 1080 {
1081 mark_branch_bug (NIA+offset);
1082 DELAY_SLOT (NIA + offset);
1083 }
f2b30012
AC		 1084}
1085
1086
c0a4c3ba 1087
f2b30012
AC		 1088010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1089"bnel r<RS>, r<RT>, <OFFSET>"
1090*mipsII:
1091*mipsIII:
1092*mipsIV:
1ee7d2b1 1093*vr4100:
23850e92 1094*vr5000:
f14397f0
GRK		 1095// start-sanitize-vr4xxx
1096*vr4121:
1097// end-sanitize-vr4xxx
15232df4
FCE		 1098// start-sanitize-vr4320
1099*vr4320:
1100// end-sanitize-vr4320
a83d7d87 1101// start-sanitize-cygnus
90ad43b2 1102*vr5400:
a83d7d87 1103// end-sanitize-cygnus
f2b30012
AC		 1104// start-sanitize-r5900
1105*r5900:
1106// end-sanitize-r5900
1107*r3900:
1108// start-sanitize-tx19
1109*tx19:
1110// end-sanitize-tx19
1111{
085c1cb9 1112 address_word offset = EXTEND16 (OFFSET) << 2;
a83d7d87 1113 check_branch_bug ();
030843d7 1114 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
a83d7d87
AC		 1115 {
1116 mark_branch_bug (NIA+offset);
1117 DELAY_SLOT (NIA + offset);
1118 }
f2b30012 1119 else
49a76833 1120 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 1121}
1122
1123
c0a4c3ba 1124
49a6eed5 1125000000,20.CODE,001101:SPECIAL:32::BREAK
f2b30012 1126"break"
23850e92 1127*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 1128*vr4100:
23850e92 1129*vr5000:
f14397f0
GRK		 1130// start-sanitize-vr4xxx
1131*vr4121:
1132// end-sanitize-vr4xxx
15232df4
FCE		 1133// start-sanitize-vr4320
1134*vr4320:
1135// end-sanitize-vr4320
a83d7d87 1136// start-sanitize-cygnus
90ad43b2 1137*vr5400:
a83d7d87 1138// end-sanitize-cygnus
f2b30012
AC		 1139// start-sanitize-r5900
1140*r5900:
1141// end-sanitize-r5900
1142*r3900:
1143// start-sanitize-tx19
1144*tx19:
1145// end-sanitize-tx19
1146{
895a7dc2
IC		 1147 /* Check for some break instruction which are reserved for use by the simulator. */
1148 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1149 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1150 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1151 {
1152 sim_engine_halt (SD, CPU, NULL, cia,
1153 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1154 }
1155 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1156 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1157 {
1158 if (STATE & simDELAYSLOT)
1159 PC = cia - 4; /* reference the branch instruction */
1160 else
1161 PC = cia;
1162 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1163 }
1164// start-sanitize-sky
1ee7d2b1 1165#ifdef TARGET_SKY
895a7dc2
IC		 1166 else if (break_code == (HALT_INSTRUCTION_PASS & HALT_INSTRUCTION_MASK))
1167 {
1168 sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
1169 }
1170 else if (break_code == (HALT_INSTRUCTION_FAIL & HALT_INSTRUCTION_MASK))
1171 {
1172 sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 15);
1173 }
1ee7d2b1
FCE		 1174 else if (break_code == (PRINTF_INSTRUCTION & HALT_INSTRUCTION_MASK))
1175 {
1176 sim_monitor(SD, CPU, cia, 316); /* Magic number for idt printf routine. */
1177 }
1178 else if (break_code == (LOAD_INSTRUCTION & HALT_INSTRUCTION_MASK))
1179 {
1180 /* This is a multi-phase load instruction. Load next configured
1181 executable and return its starting PC in A0 ($4). */
1182
1183 if (STATE_MLOAD_INDEX (SD) == STATE_MLOAD_COUNT (SD))
1184 {
1185 sim_io_eprintf (SD, "Cannot load program %d. Not enough load-next options.\n",
1186 STATE_MLOAD_COUNT (SD));
1187 A0 = 0;
1188 }
1189 else
1190 {
1191 char* next = STATE_MLOAD_NAME (SD) [STATE_MLOAD_INDEX (SD)];
1192 SIM_RC rc;
1193
1194 STATE_MLOAD_INDEX (SD) ++;
1195
1196 /* call sim_load_file, preserving most previous state */
1197 rc = sim_load (SD, next, NULL, 0);
1198 if(rc != SIM_RC_OK)
1199 {
1200 sim_io_eprintf (SD, "Error during multi-phase load #%d.\n",
1201 STATE_MLOAD_INDEX (SD));
1202 A0 = 0;
1203 }
1204 else
1205 A0 = STATE_START_ADDR (SD);
1206 }
1207 }
1208#endif TARGET_SKY
895a7dc2
IC		 1209// end-sanitize-sky
1210
1ee7d2b1
FCE		 1211 else
1212 {
1213 /* If we get this far, we're not an instruction reserved by the sim. Raise
1214 the exception. */
1215 SignalException(BreakPoint, instruction_0);
1216 }
f2b30012
AC		 1217}
1218
1219
c0a4c3ba 1220
f2b30012
AC		 1221
1222
c0a4c3ba 1223
f2b30012
AC		 1224000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1225"dadd r<RD>, r<RS>, r<RT>"
1226*mipsIII:
1227*mipsIV:
1ee7d2b1 1228*vr4100:
23850e92 1229*vr5000:
f14397f0
GRK		 1230// start-sanitize-vr4xxx
1231*vr4121:
1232// end-sanitize-vr4xxx
15232df4
FCE		 1233// start-sanitize-vr4320
1234*vr4320:
1235// end-sanitize-vr4320
a83d7d87 1236// start-sanitize-cygnus
90ad43b2 1237*vr5400:
a83d7d87 1238// end-sanitize-cygnus
f2b30012
AC		 1239// start-sanitize-r5900
1240*r5900:
1241// end-sanitize-r5900
f2b30012
AC		 1242// start-sanitize-tx19
1243*tx19:
1244// end-sanitize-tx19
1245{
ca6f76d1 1246 /* this check's for overflow */
26feb3a8
AC		 1247 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1248 {
1249 ALU64_BEGIN (GPR[RS]);
1250 ALU64_ADD (GPR[RT]);
1251 ALU64_END (GPR[RD]);
1252 }
1253 TRACE_ALU_RESULT (GPR[RD]);
f2b30012
AC		 1254}
1255
1256
c0a4c3ba 1257
f2b30012
AC		 1258011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1259"daddi r<RT>, r<RS>, <IMMEDIATE>"
1260*mipsIII:
1261*mipsIV:
1ee7d2b1 1262*vr4100:
23850e92 1263*vr5000:
f14397f0
GRK		 1264// start-sanitize-vr4xxx
1265*vr4121:
1266// end-sanitize-vr4xxx
15232df4
FCE		 1267// start-sanitize-vr4320
1268*vr4320:
1269// end-sanitize-vr4320
a83d7d87 1270// start-sanitize-cygnus
90ad43b2 1271*vr5400:
a83d7d87 1272// end-sanitize-cygnus
f2b30012
AC		 1273// start-sanitize-r5900
1274*r5900:
1275// end-sanitize-r5900
f2b30012
AC		 1276// start-sanitize-tx19
1277*tx19:
1278// end-sanitize-tx19
1279{
26feb3a8
AC		 1280 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1281 {
1282 ALU64_BEGIN (GPR[RS]);
1283 ALU64_ADD (EXTEND16 (IMMEDIATE));
1284 ALU64_END (GPR[RT]);
1285 }
1286 TRACE_ALU_RESULT (GPR[RT]);
f2b30012
AC		 1287}
1288
1289
c0a4c3ba
AC		 1290
1291:function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
1292{
f3bdd368 1293 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
c0a4c3ba 1294 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
f3bdd368 1295 TRACE_ALU_RESULT (GPR[rt]);
c0a4c3ba
AC		 1296}
1297
f2b30012
AC		 1298011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1299"daddu r<RT>, r<RS>, <IMMEDIATE>"
1300*mipsIII:
1301*mipsIV:
1ee7d2b1 1302*vr4100:
23850e92 1303*vr5000:
f14397f0
GRK		 1304// start-sanitize-vr4xxx
1305*vr4121:
1306// end-sanitize-vr4xxx
15232df4
FCE		 1307// start-sanitize-vr4320
1308*vr4320:
1309// end-sanitize-vr4320
a83d7d87 1310// start-sanitize-cygnus
90ad43b2 1311*vr5400:
a83d7d87 1312// end-sanitize-cygnus
f2b30012
AC		 1313// start-sanitize-r5900
1314*r5900:
1315// end-sanitize-r5900
f2b30012
AC		 1316// start-sanitize-tx19
1317*tx19:
1318// end-sanitize-tx19
1319{
c0a4c3ba 1320 do_daddiu (SD_, RS, RT, IMMEDIATE);
f2b30012
AC		 1321}
1322
1323
c0a4c3ba
AC		 1324
1325:function:::void:do_daddu:int rs, int rt, int rd
1326{
f3bdd368 1327 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 1328 GPR[rd] = GPR[rs] + GPR[rt];
f3bdd368 1329 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 1330}
1331
f2b30012
AC		 1332000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1333"daddu r<RD>, r<RS>, r<RT>"
1334*mipsIII:
1335*mipsIV:
1ee7d2b1 1336*vr4100:
23850e92 1337*vr5000:
f14397f0
GRK		 1338// start-sanitize-vr4xxx
1339*vr4121:
1340// end-sanitize-vr4xxx
15232df4
FCE		 1341// start-sanitize-vr4320
1342*vr4320:
1343// end-sanitize-vr4320
a83d7d87 1344// start-sanitize-cygnus
90ad43b2 1345*vr5400:
a83d7d87 1346// end-sanitize-cygnus
f2b30012
AC		 1347// start-sanitize-r5900
1348*r5900:
1349// end-sanitize-r5900
f2b30012
AC		 1350// start-sanitize-tx19
1351*tx19:
1352// end-sanitize-tx19
1353{
c0a4c3ba 1354 do_daddu (SD_, RS, RT, RD);
f2b30012
AC		 1355}
1356
1357
c0a4c3ba
AC		 1358
1359:function:64::void:do_ddiv:int rs, int rt
f2b30012 1360{
94dda41a 1361 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 1362 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
f2b30012 1363 {
c0a4c3ba
AC		 1364 signed64 n = GPR[rs];
1365 signed64 d = GPR[rt];
f2b30012
AC		 1366 if (d == 0)
1367 {
1368 LO = SIGNED64 (0x8000000000000000);
1369 HI = 0;
1370 }
1371 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1372 {
1373 LO = SIGNED64 (0x8000000000000000);
1374 HI = 0;
1375 }
1376 else
1377 {
1378 LO = (n / d);
1379 HI = (n % d);
1380 }
1381 }
f3bdd368 1382 TRACE_ALU_RESULT2 (HI, LO);
f2b30012
AC		 1383}
1384
c0a4c3ba
AC		 1385000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1386"ddiv r<RS>, r<RT>"
f2b30012
AC		 1387*mipsIII:
1388*mipsIV:
1ee7d2b1 1389*vr4100:
23850e92 1390*vr5000:
f14397f0
GRK		 1391// start-sanitize-vr4xxx
1392*vr4121:
1393// end-sanitize-vr4xxx
15232df4
FCE		 1394// start-sanitize-vr4320
1395*vr4320:
1396// end-sanitize-vr4320
a83d7d87 1397// start-sanitize-cygnus
90ad43b2 1398*vr5400:
a83d7d87 1399// end-sanitize-cygnus
c0a4c3ba
AC		 1400// start-sanitize-r5900
1401*r5900:
1402// end-sanitize-r5900
f2b30012
AC		 1403// start-sanitize-tx19
1404*tx19:
1405// end-sanitize-tx19
c0a4c3ba
AC		 1406{
1407 do_ddiv (SD_, RS, RT);
1408}
1409
1410
1411
1412:function:64::void:do_ddivu:int rs, int rt
f2b30012 1413{
94dda41a 1414 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 1415 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
f2b30012 1416 {
c0a4c3ba
AC		 1417 unsigned64 n = GPR[rs];
1418 unsigned64 d = GPR[rt];
f2b30012
AC		 1419 if (d == 0)
1420 {
1421 LO = SIGNED64 (0x8000000000000000);
1422 HI = 0;
1423 }
1424 else
1425 {
1426 LO = (n / d);
1427 HI = (n % d);
1428 }
1429 }
f3bdd368 1430 TRACE_ALU_RESULT2 (HI, LO);
f2b30012
AC		 1431}
1432
c0a4c3ba
AC		 1433000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1434"ddivu r<RS>, r<RT>"
1435*mipsIII:
1436*mipsIV:
1ee7d2b1 1437*vr4100:
23850e92 1438*vr5000:
f14397f0
GRK		 1439// start-sanitize-vr4xxx
1440*vr4121:
1441// end-sanitize-vr4xxx
15232df4
FCE		 1442// start-sanitize-vr4320
1443*vr4320:
1444// end-sanitize-vr4320
a83d7d87 1445// start-sanitize-cygnus
90ad43b2 1446*vr5400:
a83d7d87 1447// end-sanitize-cygnus
f2b30012
AC		 1448// start-sanitize-tx19
1449*tx19:
1450// end-sanitize-tx19
c0a4c3ba
AC		 1451{
1452 do_ddivu (SD_, RS, RT);
1453}
1454
1455
1456
1457:function:::void:do_div:int rs, int rt
f2b30012 1458{
94dda41a 1459 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 1460 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
f2b30012 1461 {
c0a4c3ba
AC		 1462 signed32 n = GPR[rs];
1463 signed32 d = GPR[rt];
f2b30012
AC		 1464 if (d == 0)
1465 {
1466 LO = EXTEND32 (0x80000000);
1467 HI = EXTEND32 (0);
1468 }
ca6f76d1 1469 else if (n == SIGNED32 (0x80000000) && d == -1)
f2b30012
AC		 1470 {
1471 LO = EXTEND32 (0x80000000);
1472 HI = EXTEND32 (0);
1473 }
1474 else
1475 {
1476 LO = EXTEND32 (n / d);
1477 HI = EXTEND32 (n % d);
1478 }
1479 }
f3bdd368 1480 TRACE_ALU_RESULT2 (HI, LO);
f2b30012
AC		 1481}
1482
c0a4c3ba
AC		 1483000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1484"div r<RS>, r<RT>"
23850e92 1485*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 1486*vr4100:
23850e92 1487*vr5000:
f14397f0
GRK		 1488// start-sanitize-vr4xxx
1489*vr4121:
1490// end-sanitize-vr4xxx
15232df4
FCE		 1491// start-sanitize-vr4320
1492*vr4320:
1493// end-sanitize-vr4320
a83d7d87 1494// start-sanitize-cygnus
90ad43b2 1495*vr5400:
a83d7d87 1496// end-sanitize-cygnus
f2b30012
AC		 1497// start-sanitize-r5900
1498*r5900:
1499// end-sanitize-r5900
1500*r3900:
1501// start-sanitize-tx19
1502*tx19:
1503// end-sanitize-tx19
c0a4c3ba
AC		 1504{
1505 do_div (SD_, RS, RT);
1506}
1507
1508
1509
1510:function:::void:do_divu:int rs, int rt
f2b30012 1511{
94dda41a 1512 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 1513 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
f2b30012 1514 {
c0a4c3ba
AC		 1515 unsigned32 n = GPR[rs];
1516 unsigned32 d = GPR[rt];
f2b30012
AC		 1517 if (d == 0)
1518 {
1519 LO = EXTEND32 (0x80000000);
1520 HI = EXTEND32 (0);
1521 }
1522 else
1523 {
1524 LO = EXTEND32 (n / d);
1525 HI = EXTEND32 (n % d);
1526 }
1527 }
f3bdd368 1528 TRACE_ALU_RESULT2 (HI, LO);
f2b30012
AC		 1529}
1530
c0a4c3ba
AC		 1531000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1532"divu r<RS>, r<RT>"
1533*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 1534*vr4100:
c0a4c3ba 1535*vr5000:
f14397f0
GRK		 1536// start-sanitize-vr4xxx
1537*vr4121:
1538// end-sanitize-vr4xxx
c0a4c3ba
AC		 1539// start-sanitize-vr4320
1540*vr4320:
1541// end-sanitize-vr4320
a83d7d87 1542// start-sanitize-cygnus
c0a4c3ba 1543*vr5400:
a83d7d87 1544// end-sanitize-cygnus
c0a4c3ba
AC		 1545// start-sanitize-r5900
1546*r5900:
1547// end-sanitize-r5900
1548*r3900:
1549// start-sanitize-tx19
1550*tx19:
1551// end-sanitize-tx19
1552{
1553 do_divu (SD_, RS, RT);
1554}
1555
f2b30012 1556
c0a4c3ba
AC		 1557
1558:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
23850e92
JL		 1559{
1560 unsigned64 lo;
1561 unsigned64 hi;
1562 unsigned64 m00;
1563 unsigned64 m01;
1564 unsigned64 m10;
1565 unsigned64 m11;
1566 unsigned64 mid;
1567 int sign;
1568 unsigned64 op1 = GPR[rs];
1569 unsigned64 op2 = GPR[rt];
94dda41a 1570 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 1571 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
23850e92
JL		 1572 /* make signed multiply unsigned */
1573 sign = 0;
1574 if (signed_p)
1575 {
1576 if (op1 < 0)
1577 {
1578 op1 = - op1;
1579 ++sign;
1580 }
1581 if (op2 < 0)
1582 {
1583 op2 = - op2;
1584 ++sign;
1585 }
1586 }
1587 /* multuply out the 4 sub products */
1588 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1589 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1590 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1591 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1592 /* add the products */
1593 mid = ((unsigned64) VH4_8 (m00)
1594 + (unsigned64) VL4_8 (m10)
1595 + (unsigned64) VL4_8 (m01));
1596 lo = U8_4 (mid, m00);
1597 hi = (m11
1598 + (unsigned64) VH4_8 (mid)
1599 + (unsigned64) VH4_8 (m01)
1600 + (unsigned64) VH4_8 (m10));
1601 /* fix the sign */
1602 if (sign & 1)
1603 {
1604 lo = -lo;
1605 if (lo == 0)
1606 hi = -hi;
1607 else
1608 hi = -hi - 1;
1609 }
1610 /* save the result HI/LO (and a gpr) */
1611 LO = lo;
1612 HI = hi;
1613 if (rd != 0)
1614 GPR[rd] = lo;
f3bdd368 1615 TRACE_ALU_RESULT2 (HI, LO);
23850e92
JL		 1616}
1617
c0a4c3ba
AC		 1618:function:::void:do_dmult:int rs, int rt, int rd
1619{
1620 do_dmultx (SD_, rs, rt, rd, 1);
1621}
23850e92 1622
f2b30012
AC		 1623000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1624"dmult r<RS>, r<RT>"
23850e92 1625*mipsIII,mipsIV:
1ee7d2b1 1626*vr4100:
f14397f0
GRK		 1627// start-sanitize-vr4xxx
1628*vr4121:
1629// end-sanitize-vr4xxx
f2b30012
AC		 1630// start-sanitize-tx19
1631*tx19:
1632// end-sanitize-tx19
15232df4
FCE		 1633// start-sanitize-vr4320
1634*vr4320:
1635// end-sanitize-vr4320
f2b30012 1636{
c0a4c3ba 1637 do_dmult (SD_, RS, RT, 0);
f2b30012
AC		 1638}
1639
23850e92
JL		 1640000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1641"dmult r<RS>, r<RT>":RD == 0
1642"dmult r<RD>, r<RS>, r<RT>"
1643*vr5000:
a83d7d87 1644// start-sanitize-cygnus
90ad43b2 1645*vr5400:
a83d7d87 1646// end-sanitize-cygnus
23850e92 1647{
c0a4c3ba 1648 do_dmult (SD_, RS, RT, RD);
23850e92
JL		 1649}
1650
1651
1652
c0a4c3ba
AC		 1653:function:::void:do_dmultu:int rs, int rt, int rd
1654{
1655 do_dmultx (SD_, rs, rt, rd, 0);
1656}
1657
23850e92
JL		 1658000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1659"dmultu r<RS>, r<RT>"
1660*mipsIII,mipsIV:
1ee7d2b1 1661*vr4100:
f14397f0
GRK		 1662// start-sanitize-vr4xxx
1663*vr4121:
1664// end-sanitize-vr4xxx
f2b30012
AC		 1665// start-sanitize-tx19
1666*tx19:
1667// end-sanitize-tx19
15232df4
FCE		 1668// start-sanitize-vr4320
1669*vr4320:
1670// end-sanitize-vr4320
f2b30012 1671{
c0a4c3ba 1672 do_dmultu (SD_, RS, RT, 0);
23850e92
JL		 1673}
1674
1675000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1676"dmultu r<RD>, r<RS>, r<RT>":RD == 0
1677"dmultu r<RS>, r<RT>"
1678*vr5000:
a83d7d87 1679// start-sanitize-cygnus
23850e92 1680*vr5400:
a83d7d87 1681// end-sanitize-cygnus
23850e92 1682{
c0a4c3ba 1683 do_dmultu (SD_, RS, RT, RD);
f2b30012
AC		 1684}
1685
1686
23850e92 1687
055ee297 168800000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
01b9cd49 1689"dsll r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1690*mipsIII:
1691*mipsIV:
1ee7d2b1 1692*vr4100:
23850e92 1693*vr5000:
f14397f0
GRK		 1694// start-sanitize-vr4xxx
1695*vr4121:
1696// end-sanitize-vr4xxx
15232df4
FCE		 1697// start-sanitize-vr4320
1698*vr4320:
1699// end-sanitize-vr4320
a83d7d87 1700// start-sanitize-cygnus
90ad43b2 1701*vr5400:
a83d7d87 1702// end-sanitize-cygnus
f2b30012
AC		 1703// start-sanitize-r5900
1704*r5900:
1705// end-sanitize-r5900
f2b30012
AC		 1706// start-sanitize-tx19
1707*tx19:
1708// end-sanitize-tx19
1709{
01b9cd49 1710 int s = SHIFT;
055ee297 1711 GPR[RD] = GPR[RT] << s;
f2b30012
AC		 1712}
1713
1714
055ee297 171500000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
01b9cd49 1716"dsll32 r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1717*mipsIII:
1718*mipsIV:
1ee7d2b1 1719*vr4100:
23850e92 1720*vr5000:
f14397f0
GRK		 1721// start-sanitize-vr4xxx
1722*vr4121:
1723// end-sanitize-vr4xxx
15232df4
FCE		 1724// start-sanitize-vr4320
1725*vr4320:
1726// end-sanitize-vr4320
a83d7d87 1727// start-sanitize-cygnus
90ad43b2 1728*vr5400:
a83d7d87 1729// end-sanitize-cygnus
f2b30012
AC		 1730// start-sanitize-r5900
1731*r5900:
1732// end-sanitize-r5900
f2b30012
AC		 1733// start-sanitize-tx19
1734*tx19:
1735// end-sanitize-tx19
1736{
01b9cd49 1737 int s = 32 + SHIFT;
055ee297 1738 GPR[RD] = GPR[RT] << s;
f2b30012
AC		 1739}
1740
1741
c0a4c3ba 1742
f2b30012
AC		 1743000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1744"dsllv r<RD>, r<RT>, r<RS>"
1745*mipsIII:
1746*mipsIV:
1ee7d2b1 1747*vr4100:
23850e92 1748*vr5000:
f14397f0
GRK		 1749// start-sanitize-vr4xxx
1750*vr4121:
1751// end-sanitize-vr4xxx
15232df4
FCE		 1752// start-sanitize-vr4320
1753*vr4320:
1754// end-sanitize-vr4320
a83d7d87 1755// start-sanitize-cygnus
90ad43b2 1756*vr5400:
a83d7d87 1757// end-sanitize-cygnus
f2b30012
AC		 1758// start-sanitize-r5900
1759*r5900:
1760// end-sanitize-r5900
f2b30012
AC		 1761// start-sanitize-tx19
1762*tx19:
1763// end-sanitize-tx19
1764{
055ee297
AC		 1765 int s = MASKED64 (GPR[RS], 5, 0);
1766 GPR[RD] = GPR[RT] << s;
f2b30012
AC		 1767}
1768
1769
c0a4c3ba 1770
055ee297 177100000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
01b9cd49 1772"dsra r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1773*mipsIII:
1774*mipsIV:
1ee7d2b1 1775*vr4100:
23850e92 1776*vr5000:
f14397f0
GRK		 1777// start-sanitize-vr4xxx
1778*vr4121:
1779// end-sanitize-vr4xxx
15232df4
FCE		 1780// start-sanitize-vr4320
1781*vr4320:
1782// end-sanitize-vr4320
a83d7d87 1783// start-sanitize-cygnus
90ad43b2 1784*vr5400:
a83d7d87 1785// end-sanitize-cygnus
f2b30012
AC		 1786// start-sanitize-r5900
1787*r5900:
1788// end-sanitize-r5900
f2b30012
AC		 1789// start-sanitize-tx19
1790*tx19:
1791// end-sanitize-tx19
1792{
01b9cd49 1793 int s = SHIFT;
055ee297 1794 GPR[RD] = ((signed64) GPR[RT]) >> s;
f2b30012
AC		 1795}
1796
1797
055ee297 179800000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
01b9cd49 1799"dsra32 r<RT>, r<RD>, <SHIFT>"
f2b30012
AC		 1800*mipsIII:
1801*mipsIV:
1ee7d2b1 1802*vr4100:
23850e92 1803*vr5000:
f14397f0
GRK		 1804// start-sanitize-vr4xxx
1805*vr4121:
1806// end-sanitize-vr4xxx
15232df4
FCE		 1807// start-sanitize-vr4320
1808*vr4320:
1809// end-sanitize-vr4320
a83d7d87 1810// start-sanitize-cygnus
90ad43b2 1811*vr5400:
a83d7d87 1812// end-sanitize-cygnus
f2b30012
AC		 1813// start-sanitize-r5900
1814*r5900:
1815// end-sanitize-r5900
f2b30012
AC		 1816// start-sanitize-tx19
1817*tx19:
1818// end-sanitize-tx19
1819{
01b9cd49 1820 int s = 32 + SHIFT;
055ee297 1821 GPR[RD] = ((signed64) GPR[RT]) >> s;
f2b30012
AC		 1822}
1823
1824
74025eee 1825:function:::void:do_dsrav:int rs, int rt, int rd
c0a4c3ba
AC		 1826{
1827 int s = MASKED64 (GPR[rs], 5, 0);
f3bdd368 1828 TRACE_ALU_INPUT2 (GPR[rt], s);
c0a4c3ba 1829 GPR[rd] = ((signed64) GPR[rt]) >> s;
f3bdd368 1830 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 1831}
1832
f2b30012
AC		 1833000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1834"dsra32 r<RT>, r<RD>, r<RS>"
1835*mipsIII:
1836*mipsIV:
1ee7d2b1 1837*vr4100:
23850e92 1838*vr5000:
f14397f0
GRK		 1839// start-sanitize-vr4xxx
1840*vr4121:
1841// end-sanitize-vr4xxx
15232df4
FCE		 1842// start-sanitize-vr4320
1843*vr4320:
1844// end-sanitize-vr4320
a83d7d87 1845// start-sanitize-cygnus
90ad43b2 1846*vr5400:
a83d7d87 1847// end-sanitize-cygnus
f2b30012
AC		 1848// start-sanitize-r5900
1849*r5900:
1850// end-sanitize-r5900
f2b30012
AC		 1851// start-sanitize-tx19
1852*tx19:
1853// end-sanitize-tx19
1854{
74025eee 1855 do_dsrav (SD_, RS, RT, RD);
f2b30012
AC		 1856}
1857
1858
055ee297 185900000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
74025eee 1860"dsrl r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1861*mipsIII:
1862*mipsIV:
1ee7d2b1 1863*vr4100:
23850e92 1864*vr5000:
f14397f0
GRK		 1865// start-sanitize-vr4xxx
1866*vr4121:
1867// end-sanitize-vr4xxx
15232df4
FCE		 1868// start-sanitize-vr4320
1869*vr4320:
1870// end-sanitize-vr4320
a83d7d87 1871// start-sanitize-cygnus
90ad43b2 1872*vr5400:
a83d7d87 1873// end-sanitize-cygnus
f2b30012
AC		 1874// start-sanitize-r5900
1875*r5900:
1876// end-sanitize-r5900
f2b30012
AC		 1877// start-sanitize-tx19
1878*tx19:
1879// end-sanitize-tx19
1880{
01b9cd49 1881 int s = SHIFT;
055ee297 1882 GPR[RD] = (unsigned64) GPR[RT] >> s;
f2b30012
AC		 1883}
1884
1885
055ee297 188600000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
01b9cd49 1887"dsrl32 r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1888*mipsIII:
1889*mipsIV:
1ee7d2b1 1890*vr4100:
23850e92 1891*vr5000:
f14397f0
GRK		 1892// start-sanitize-vr4xxx
1893*vr4121:
1894// end-sanitize-vr4xxx
15232df4
FCE		 1895// start-sanitize-vr4320
1896*vr4320:
1897// end-sanitize-vr4320
a83d7d87 1898// start-sanitize-cygnus
90ad43b2 1899*vr5400:
a83d7d87 1900// end-sanitize-cygnus
f2b30012
AC		 1901// start-sanitize-r5900
1902*r5900:
1903// end-sanitize-r5900
f2b30012
AC		 1904// start-sanitize-tx19
1905*tx19:
1906// end-sanitize-tx19
1907{
01b9cd49 1908 int s = 32 + SHIFT;
055ee297 1909 GPR[RD] = (unsigned64) GPR[RT] >> s;
f2b30012
AC		 1910}
1911
1912
1913000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1914"dsrl32 r<RD>, r<RT>, r<RS>"
1915*mipsIII:
1916*mipsIV:
1ee7d2b1 1917*vr4100:
23850e92 1918*vr5000:
f14397f0
GRK		 1919// start-sanitize-vr4xxx
1920*vr4121:
1921// end-sanitize-vr4xxx
15232df4
FCE		 1922// start-sanitize-vr4320
1923*vr4320:
1924// end-sanitize-vr4320
a83d7d87 1925// start-sanitize-cygnus
90ad43b2 1926*vr5400:
a83d7d87 1927// end-sanitize-cygnus
f2b30012
AC		 1928// start-sanitize-r5900
1929*r5900:
1930// end-sanitize-r5900
f2b30012
AC		 1931// start-sanitize-tx19
1932*tx19:
1933// end-sanitize-tx19
1934{
055ee297
AC		 1935 int s = MASKED64 (GPR[RS], 5, 0);
1936 GPR[RD] = (unsigned64) GPR[RT] >> s;
f2b30012
AC		 1937}
1938
1939
1940000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1941"dsub r<RD>, r<RS>, r<RT>"
1942*mipsIII:
1943*mipsIV:
1ee7d2b1 1944*vr4100:
23850e92 1945*vr5000:
f14397f0
GRK		 1946// start-sanitize-vr4xxx
1947*vr4121:
1948// end-sanitize-vr4xxx
15232df4
FCE		 1949// start-sanitize-vr4320
1950*vr4320:
1951// end-sanitize-vr4320
a83d7d87 1952// start-sanitize-cygnus
90ad43b2 1953*vr5400:
a83d7d87 1954// end-sanitize-cygnus
f2b30012
AC		 1955// start-sanitize-r5900
1956*r5900:
1957// end-sanitize-r5900
f2b30012
AC		 1958// start-sanitize-tx19
1959*tx19:
1960// end-sanitize-tx19
1961{
26feb3a8
AC		 1962 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1963 {
1964 ALU64_BEGIN (GPR[RS]);
1965 ALU64_SUB (GPR[RT]);
1966 ALU64_END (GPR[RD]);
1967 }
1968 TRACE_ALU_RESULT (GPR[RD]);
f2b30012
AC		 1969}
1970
1971
c0a4c3ba
AC		 1972:function:::void:do_dsubu:int rs, int rt, int rd
1973{
f3bdd368 1974 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 1975 GPR[rd] = GPR[rs] - GPR[rt];
f3bdd368 1976 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 1977}
1978
f2b30012
AC		 1979000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1980"dsubu r<RD>, r<RS>, r<RT>"
1981*mipsIII:
1982*mipsIV:
1ee7d2b1 1983*vr4100:
23850e92 1984*vr5000:
f14397f0
GRK		 1985// start-sanitize-vr4xxx
1986*vr4121:
1987// end-sanitize-vr4xxx
15232df4
FCE		 1988// start-sanitize-vr4320
1989*vr4320:
1990// end-sanitize-vr4320
a83d7d87 1991// start-sanitize-cygnus
90ad43b2 1992*vr5400:
a83d7d87 1993// end-sanitize-cygnus
f2b30012
AC		 1994// start-sanitize-r5900
1995*r5900:
1996// end-sanitize-r5900
f2b30012
AC		 1997// start-sanitize-tx19
1998*tx19:
1999// end-sanitize-tx19
2000{
c0a4c3ba 2001 do_dsubu (SD_, RS, RT, RD);
f2b30012
AC		 2002}
2003
2004
2005000010,26.INSTR_INDEX:NORMAL:32::J
2006"j <INSTR_INDEX>"
23850e92 2007*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2008*vr4100:
23850e92 2009*vr5000:
f14397f0
GRK		 2010// start-sanitize-vr4xxx
2011*vr4121:
2012// end-sanitize-vr4xxx
15232df4
FCE		 2013// start-sanitize-vr4320
2014*vr4320:
2015// end-sanitize-vr4320
a83d7d87 2016// start-sanitize-cygnus
90ad43b2 2017*vr5400:
a83d7d87 2018// end-sanitize-cygnus
f2b30012
AC		 2019// start-sanitize-r5900
2020*r5900:
2021// end-sanitize-r5900
2022*r3900:
2023// start-sanitize-tx19
2024*tx19:
2025// end-sanitize-tx19
2026{
49a76833 2027 /* NOTE: The region used is that of the delay slot NIA and NOT the
f2b30012 2028 current instruction */
49a76833
AC		 2029 address_word region = (NIA & MASK (63, 28));
2030 DELAY_SLOT (region | (INSTR_INDEX << 2));
f2b30012
AC		 2031}
2032
2033
2034000011,26.INSTR_INDEX:NORMAL:32::JAL
2035"jal <INSTR_INDEX>"
23850e92 2036*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2037*vr4100:
23850e92 2038*vr5000:
f14397f0
GRK		 2039// start-sanitize-vr4xxx
2040*vr4121:
2041// end-sanitize-vr4xxx
15232df4
FCE		 2042// start-sanitize-vr4320
2043*vr4320:
2044// end-sanitize-vr4320
a83d7d87 2045// start-sanitize-cygnus
90ad43b2 2046*vr5400:
a83d7d87 2047// end-sanitize-cygnus
f2b30012
AC		 2048// start-sanitize-r5900
2049*r5900:
2050// end-sanitize-r5900
2051*r3900:
2052// start-sanitize-tx19
2053*tx19:
2054// end-sanitize-tx19
2055{
2056 /* NOTE: The region used is that of the delay slot and NOT the
2057 current instruction */
49a76833 2058 address_word region = (NIA & MASK (63, 28));
055ee297 2059 GPR[31] = CIA + 8;
49a76833 2060 DELAY_SLOT (region | (INSTR_INDEX << 2));
f2b30012
AC		 2061}
2062
2063
2064000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
2065"jalr r<RS>":RD == 31
2066"jalr r<RD>, r<RS>"
23850e92 2067*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2068*vr4100:
23850e92 2069*vr5000:
f14397f0
GRK		 2070// start-sanitize-vr4xxx
2071*vr4121:
2072// end-sanitize-vr4xxx
15232df4
FCE		 2073// start-sanitize-vr4320
2074*vr4320:
2075// end-sanitize-vr4320
a83d7d87 2076// start-sanitize-cygnus
90ad43b2 2077*vr5400:
a83d7d87 2078// end-sanitize-cygnus
f2b30012
AC		 2079// start-sanitize-r5900
2080*r5900:
2081// end-sanitize-r5900
2082*r3900:
2083// start-sanitize-tx19
2084*tx19:
2085// end-sanitize-tx19
2086{
055ee297
AC		 2087 address_word temp = GPR[RS];
2088 GPR[RD] = CIA + 8;
49a76833 2089 DELAY_SLOT (temp);
f2b30012
AC		 2090}
2091
2092
2093000000,5.RS,000000000000000001000:SPECIAL:32::JR
2094"jr r<RS>"
23850e92 2095*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2096*vr4100:
23850e92 2097*vr5000:
f14397f0
GRK		 2098// start-sanitize-vr4xxx
2099*vr4121:
2100// end-sanitize-vr4xxx
15232df4
FCE		 2101// start-sanitize-vr4320
2102*vr4320:
2103// end-sanitize-vr4320
a83d7d87 2104// start-sanitize-cygnus
90ad43b2 2105*vr5400:
a83d7d87 2106// end-sanitize-cygnus
f2b30012
AC		 2107// start-sanitize-r5900
2108*r5900:
2109// end-sanitize-r5900
2110*r3900:
2111// start-sanitize-tx19
2112*tx19:
2113// end-sanitize-tx19
2114{
49a76833 2115 DELAY_SLOT (GPR[RS]);
f2b30012
AC		 2116}
2117
2118
ebcfd86a 2119:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
a48e8c8d 2120{
ebcfd86a
FCE		 2121 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2122 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2123 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2124 unsigned int byte;
a48e8c8d
AC		 2125 address_word paddr;
2126 int uncached;
ebcfd86a
FCE		 2127 unsigned64 memval;
2128 address_word vaddr;
2129
2130 vaddr = base + offset;
2131 if ((vaddr & access) != 0)
2132 SignalExceptionAddressLoad ();
2133 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2134 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2135 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
2136 byte = ((vaddr & mask) ^ bigendiancpu);
2137 return (memval >> (8 * byte));
a48e8c8d
AC		 2138}
2139
ebcfd86a 2140
f2b30012
AC		 2141100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
2142"lb r<RT>, <OFFSET>(r<BASE>)"
23850e92 2143*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2144*vr4100:
23850e92 2145*vr5000:
f14397f0
GRK		 2146// start-sanitize-vr4xxx
2147*vr4121:
2148// end-sanitize-vr4xxx
15232df4
FCE		 2149// start-sanitize-vr4320
2150*vr4320:
2151// end-sanitize-vr4320
a83d7d87 2152// start-sanitize-cygnus
90ad43b2 2153*vr5400:
a83d7d87 2154// end-sanitize-cygnus
f2b30012
AC		 2155// start-sanitize-r5900
2156*r5900:
2157// end-sanitize-r5900
2158*r3900:
2159// start-sanitize-tx19
2160*tx19:
2161// end-sanitize-tx19
2162{
ebcfd86a 2163 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
f2b30012
AC		 2164}
2165
2166
2167100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2168"lbu r<RT>, <OFFSET>(r<BASE>)"
23850e92 2169*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2170*vr4100:
23850e92 2171*vr5000:
f14397f0
GRK		 2172// start-sanitize-vr4xxx
2173*vr4121:
2174// end-sanitize-vr4xxx
15232df4
FCE		 2175// start-sanitize-vr4320
2176*vr4320:
2177// end-sanitize-vr4320
a83d7d87 2178// start-sanitize-cygnus
90ad43b2 2179*vr5400:
a83d7d87 2180// end-sanitize-cygnus
f2b30012
AC		 2181// start-sanitize-r5900
2182*r5900:
2183// end-sanitize-r5900
2184*r3900:
2185// start-sanitize-tx19
2186*tx19:
2187// end-sanitize-tx19
2188{
ebcfd86a 2189 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
f2b30012
AC		 2190}
2191
2192
2193110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2194"ld r<RT>, <OFFSET>(r<BASE>)"
2195*mipsIII:
2196*mipsIV:
1ee7d2b1 2197*vr4100:
23850e92 2198*vr5000:
f14397f0
GRK		 2199// start-sanitize-vr4xxx
2200*vr4121:
2201// end-sanitize-vr4xxx
15232df4
FCE		 2202// start-sanitize-vr4320
2203*vr4320:
2204// end-sanitize-vr4320
a83d7d87 2205// start-sanitize-cygnus
90ad43b2 2206*vr5400:
a83d7d87 2207// end-sanitize-cygnus
f2b30012
AC		 2208// start-sanitize-r5900
2209*r5900:
2210// end-sanitize-r5900
f2b30012
AC		 2211// start-sanitize-tx19
2212*tx19:
2213// end-sanitize-tx19
2214{
ebcfd86a 2215 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
f2b30012
AC		 2216}
2217
2218
49a6eed5 22191101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
f2b30012
AC		 2220"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2221*mipsII:
2222*mipsIII:
2223*mipsIV:
1ee7d2b1 2224*vr4100:
23850e92 2225*vr5000:
f14397f0
GRK		 2226// start-sanitize-vr4xxx
2227*vr4121:
2228// end-sanitize-vr4xxx
15232df4
FCE		 2229// start-sanitize-vr4320
2230*vr4320:
2231// end-sanitize-vr4320
a83d7d87 2232// start-sanitize-cygnus
90ad43b2 2233*vr5400:
a83d7d87 2234// end-sanitize-cygnus
f2b30012
AC		 2235*r3900:
2236// start-sanitize-tx19
2237*tx19:
2238// end-sanitize-tx19
2239{
ebcfd86a 2240 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
f2b30012
AC		 2241}
2242
2243
15232df4
FCE		 2244
2245
f2b30012
AC		 2246011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2247"ldl r<RT>, <OFFSET>(r<BASE>)"
2248*mipsIII:
2249*mipsIV:
1ee7d2b1 2250*vr4100:
23850e92 2251*vr5000:
f14397f0
GRK		 2252// start-sanitize-vr4xxx
2253*vr4121:
2254// end-sanitize-vr4xxx
15232df4
FCE		 2255// start-sanitize-vr4320
2256*vr4320:
2257// end-sanitize-vr4320
a83d7d87 2258// start-sanitize-cygnus
90ad43b2 2259*vr5400:
a83d7d87 2260// end-sanitize-cygnus
f2b30012
AC		 2261// start-sanitize-r5900
2262*r5900:
2263// end-sanitize-r5900
f2b30012
AC		 2264// start-sanitize-tx19
2265*tx19:
2266// end-sanitize-tx19
2267{
ebcfd86a 2268 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 2269}
2270
2271
2272011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2273"ldr r<RT>, <OFFSET>(r<BASE>)"
2274*mipsIII:
2275*mipsIV:
1ee7d2b1 2276*vr4100:
23850e92 2277*vr5000:
f14397f0
GRK		 2278// start-sanitize-vr4xxx
2279*vr4121:
2280// end-sanitize-vr4xxx
15232df4
FCE		 2281// start-sanitize-vr4320
2282*vr4320:
2283// end-sanitize-vr4320
a83d7d87 2284// start-sanitize-cygnus
90ad43b2 2285*vr5400:
a83d7d87 2286// end-sanitize-cygnus
f2b30012
AC		 2287// start-sanitize-r5900
2288*r5900:
2289// end-sanitize-r5900
f2b30012
AC		 2290// start-sanitize-tx19
2291*tx19:
2292// end-sanitize-tx19
2293{
ebcfd86a 2294 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 2295}
2296
2297
2298100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2299"lh r<RT>, <OFFSET>(r<BASE>)"
23850e92 2300*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2301*vr4100:
23850e92 2302*vr5000:
f14397f0
GRK		 2303// start-sanitize-vr4xxx
2304*vr4121:
2305// end-sanitize-vr4xxx
15232df4
FCE		 2306// start-sanitize-vr4320
2307*vr4320:
2308// end-sanitize-vr4320
a83d7d87 2309// start-sanitize-cygnus
90ad43b2 2310*vr5400:
a83d7d87 2311// end-sanitize-cygnus
f2b30012
AC		 2312// start-sanitize-r5900
2313*r5900:
2314// end-sanitize-r5900
2315*r3900:
2316// start-sanitize-tx19
2317*tx19:
2318// end-sanitize-tx19
2319{
ebcfd86a 2320 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
f2b30012
AC		 2321}
2322
2323
2324100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2325"lhu r<RT>, <OFFSET>(r<BASE>)"
23850e92 2326*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2327*vr4100:
23850e92 2328*vr5000:
f14397f0
GRK		 2329// start-sanitize-vr4xxx
2330*vr4121:
2331// end-sanitize-vr4xxx
15232df4
FCE		 2332// start-sanitize-vr4320
2333*vr4320:
2334// end-sanitize-vr4320
a83d7d87 2335// start-sanitize-cygnus
90ad43b2 2336*vr5400:
a83d7d87 2337// end-sanitize-cygnus
f2b30012
AC		 2338// start-sanitize-r5900
2339*r5900:
2340// end-sanitize-r5900
2341*r3900:
2342// start-sanitize-tx19
2343*tx19:
2344// end-sanitize-tx19
2345{
ebcfd86a 2346 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
f2b30012
AC		 2347}
2348
2349
2350110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2351"ll r<RT>, <OFFSET>(r<BASE>)"
2352*mipsII:
2353*mipsIII:
2354*mipsIV:
1ee7d2b1 2355*vr4100:
23850e92 2356*vr5000:
f14397f0
GRK		 2357// start-sanitize-vr4xxx
2358*vr4121:
2359// end-sanitize-vr4xxx
15232df4
FCE		 2360// start-sanitize-vr4320
2361*vr4320:
2362// end-sanitize-vr4320
a83d7d87 2363// start-sanitize-cygnus
90ad43b2 2364*vr5400:
a83d7d87 2365// end-sanitize-cygnus
f2b30012
AC		 2366// start-sanitize-r5900
2367*r5900:
2368// end-sanitize-r5900
f2b30012
AC		 2369// start-sanitize-tx19
2370*tx19:
2371// end-sanitize-tx19
2372{
2373 unsigned32 instruction = instruction_0;
055ee297
AC		 2374 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2375 int destreg = ((instruction >> 16) & 0x0000001F);
2376 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2377 {
49a76833
AC		 2378 address_word vaddr = ((unsigned64)op1 + offset);
2379 address_word paddr;
f2b30012
AC		 2380 int uncached;
2381 if ((vaddr & 3) != 0)
055ee297 2382 SignalExceptionAddressLoad();
f2b30012
AC		 2383 else
2384 {
2385 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2386 {
2387 unsigned64 memval = 0;
2388 unsigned64 memval1 = 0;
2389 unsigned64 mask = 0x7;
2390 unsigned int shift = 2;
055ee297
AC		 2391 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2392 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2393 unsigned int byte;
f2b30012
AC		 2394 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2395 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2396 byte = ((vaddr & mask) ^ (bigend << shift));
2397 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2398 LLBIT = 1;
2399 }
2400 }
2401 }
2402}
2403
2404
2405110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2406"lld r<RT>, <OFFSET>(r<BASE>)"
2407*mipsIII:
2408*mipsIV:
1ee7d2b1 2409*vr4100:
23850e92 2410*vr5000:
f14397f0
GRK		 2411// start-sanitize-vr4xxx
2412*vr4121:
2413// end-sanitize-vr4xxx
15232df4
FCE		 2414// start-sanitize-vr4320
2415*vr4320:
2416// end-sanitize-vr4320
a83d7d87 2417// start-sanitize-cygnus
90ad43b2 2418*vr5400:
a83d7d87 2419// end-sanitize-cygnus
f2b30012
AC		 2420// start-sanitize-r5900
2421*r5900:
2422// end-sanitize-r5900
f2b30012
AC		 2423// start-sanitize-tx19
2424*tx19:
2425// end-sanitize-tx19
2426{
2427 unsigned32 instruction = instruction_0;
055ee297
AC		 2428 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2429 int destreg = ((instruction >> 16) & 0x0000001F);
2430 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2431 {
49a76833
AC		 2432 address_word vaddr = ((unsigned64)op1 + offset);
2433 address_word paddr;
f2b30012
AC		 2434 int uncached;
2435 if ((vaddr & 7) != 0)
055ee297 2436 SignalExceptionAddressLoad();
f2b30012
AC		 2437 else
2438 {
2439 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2440 {
2441 unsigned64 memval = 0;
2442 unsigned64 memval1 = 0;
f2b30012
AC		 2443 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2444 GPR[destreg] = memval;
2445 LLBIT = 1;
2446 }
2447 }
2448 }
2449}
2450
2451
2452001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2453"lui r<RT>, <IMMEDIATE>"
23850e92 2454*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2455*vr4100:
23850e92 2456*vr5000:
f14397f0
GRK		 2457// start-sanitize-vr4xxx
2458*vr4121:
2459// end-sanitize-vr4xxx
15232df4
FCE		 2460// start-sanitize-vr4320
2461*vr4320:
2462// end-sanitize-vr4320
a83d7d87 2463// start-sanitize-cygnus
90ad43b2 2464*vr5400:
a83d7d87 2465// end-sanitize-cygnus
f2b30012
AC		 2466// start-sanitize-r5900
2467*r5900:
2468// end-sanitize-r5900
2469*r3900:
2470// start-sanitize-tx19
2471*tx19:
2472// end-sanitize-tx19
2473{
97f4d183 2474 TRACE_ALU_INPUT1 (IMMEDIATE);
055ee297 2475 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
97f4d183 2476 TRACE_ALU_RESULT (GPR[RT]);
f2b30012
AC		 2477}
2478
2479
2480100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2481"lw r<RT>, <OFFSET>(r<BASE>)"
23850e92 2482*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2483*vr4100:
23850e92 2484*vr5000:
f14397f0
GRK		 2485// start-sanitize-vr4xxx
2486*vr4121:
2487// end-sanitize-vr4xxx
15232df4
FCE		 2488// start-sanitize-vr4320
2489*vr4320:
2490// end-sanitize-vr4320
a83d7d87 2491// start-sanitize-cygnus
90ad43b2 2492*vr5400:
a83d7d87 2493// end-sanitize-cygnus
f2b30012
AC		 2494// start-sanitize-r5900
2495*r5900:
2496// end-sanitize-r5900
2497*r3900:
2498// start-sanitize-tx19
2499*tx19:
2500// end-sanitize-tx19
2501{
ebcfd86a 2502 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
f2b30012
AC		 2503}
2504
2505
49a6eed5 25061100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
f2b30012 2507"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
23850e92 2508*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2509*vr4100:
23850e92 2510*vr5000:
f14397f0
GRK		 2511// start-sanitize-vr4xxx
2512*vr4121:
2513// end-sanitize-vr4xxx
15232df4
FCE		 2514// start-sanitize-vr4320
2515*vr4320:
2516// end-sanitize-vr4320
a83d7d87 2517// start-sanitize-cygnus
90ad43b2 2518*vr5400:
a83d7d87 2519// end-sanitize-cygnus
f2b30012
AC		 2520// start-sanitize-r5900
2521*r5900:
2522// end-sanitize-r5900
2523*r3900:
2524// start-sanitize-tx19
2525*tx19:
2526// end-sanitize-tx19
2527{
ebcfd86a
FCE		 2528 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2529}
2530
2531
2532:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2533{
2534 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2535 address_word reverseendian = (ReverseEndian ? -1 : 0);
2536 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2537 unsigned int byte;
0e797366 2538 unsigned int word;
ebcfd86a
FCE		 2539 address_word paddr;
2540 int uncached;
2541 unsigned64 memval;
2542 address_word vaddr;
0e797366
AC		 2543 int nr_lhs_bits;
2544 int nr_rhs_bits;
2545 unsigned_word lhs_mask;
2546 unsigned_word temp;
ebcfd86a
FCE		 2547
2548 vaddr = base + offset;
2549 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2550 paddr = (paddr ^ (reverseendian & mask));
2551 if (BigEndianMem == 0)
2552 paddr = paddr & ~access;
0e797366
AC		 2553
2554 /* compute where within the word/mem we are */
2555 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2556 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2557 nr_lhs_bits = 8 * byte + 8;
2558 nr_rhs_bits = 8 * access - 8 * byte;
2559 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2560
2561 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2562 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2563 (long) ((unsigned64) paddr >> 32), (long) paddr,
2564 word, byte, nr_lhs_bits, nr_rhs_bits); */
2565
2566 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2567 if (word == 0)
ebcfd86a 2568 {
0e797366
AC		 2569 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2570 temp = (memval << nr_rhs_bits);
ebcfd86a
FCE		 2571 }
2572 else
2573 {
0e797366
AC		 2574 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2575 temp = (memval >> nr_lhs_bits);
ebcfd86a 2576 }
0e797366
AC		 2577 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2578 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2579
2580 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2581 (long) ((unsigned64) memval >> 32), (long) memval,
2582 (long) ((unsigned64) temp >> 32), (long) temp,
2583 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2584 (long) (rt >> 32), (long) rt); */
ebcfd86a 2585 return rt;
f2b30012
AC		 2586}
2587
2588
2589100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2590"lwl r<RT>, <OFFSET>(r<BASE>)"
23850e92 2591*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2592*vr4100:
23850e92 2593*vr5000:
f14397f0
GRK		 2594// start-sanitize-vr4xxx
2595*vr4121:
2596// end-sanitize-vr4xxx
15232df4
FCE		 2597// start-sanitize-vr4320
2598*vr4320:
2599// end-sanitize-vr4320
a83d7d87 2600// start-sanitize-cygnus
90ad43b2 2601*vr5400:
a83d7d87 2602// end-sanitize-cygnus
f2b30012
AC		 2603// start-sanitize-r5900
2604*r5900:
2605// end-sanitize-r5900
2606*r3900:
2607// start-sanitize-tx19
2608*tx19:
2609// end-sanitize-tx19
2610{
ebcfd86a
FCE		 2611 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2612}
2613
2614
2615:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2616{
2617 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2618 address_word reverseendian = (ReverseEndian ? -1 : 0);
2619 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2620 unsigned int byte;
2621 address_word paddr;
2622 int uncached;
2623 unsigned64 memval;
2624 address_word vaddr;
2625
2626 vaddr = base + offset;
2627 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2628 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2629 paddr = (paddr ^ (reverseendian & mask));
2630 if (BigEndianMem != 0)
2631 paddr = paddr & ~access;
2632 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2633 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
2634 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2635 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2636 (long) paddr, byte, (long) paddr, (long) memval); */
f2b30012 2637 {
ebcfd86a
FCE		 2638 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2639 rt &= ~screen;
2640 rt |= (memval >> (8 * byte)) & screen;
f2b30012 2641 }
ebcfd86a 2642 return rt;
f2b30012
AC		 2643}
2644
2645
2646100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2647"lwr r<RT>, <OFFSET>(r<BASE>)"
23850e92 2648*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2649*vr4100:
23850e92 2650*vr5000:
f14397f0
GRK		 2651// start-sanitize-vr4xxx
2652*vr4121:
2653// end-sanitize-vr4xxx
15232df4
FCE		 2654// start-sanitize-vr4320
2655*vr4320:
2656// end-sanitize-vr4320
a83d7d87 2657// start-sanitize-cygnus
90ad43b2 2658*vr5400:
a83d7d87 2659// end-sanitize-cygnus
f2b30012
AC		 2660// start-sanitize-r5900
2661*r5900:
2662// end-sanitize-r5900
2663*r3900:
2664// start-sanitize-tx19
2665*tx19:
2666// end-sanitize-tx19
2667{
ebcfd86a 2668 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
f2b30012
AC		 2669}
2670
2671
2672100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2673"lwu r<RT>, <OFFSET>(r<BASE>)"
2674*mipsIII:
2675*mipsIV:
1ee7d2b1 2676*vr4100:
23850e92 2677*vr5000:
f14397f0
GRK		 2678// start-sanitize-vr4xxx
2679*vr4121:
2680// end-sanitize-vr4xxx
15232df4
FCE		 2681// start-sanitize-vr4320
2682*vr4320:
2683// end-sanitize-vr4320
a83d7d87 2684// start-sanitize-cygnus
90ad43b2 2685*vr5400:
a83d7d87 2686// end-sanitize-cygnus
f2b30012
AC		 2687// start-sanitize-r5900
2688*r5900:
2689// end-sanitize-r5900
f2b30012
AC		 2690// start-sanitize-tx19
2691*tx19:
2692// end-sanitize-tx19
2693{
ebcfd86a 2694 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
f2b30012
AC		 2695}
2696
2697
c0a4c3ba
AC		 2698:function:::void:do_mfhi:int rd
2699{
421cbaae 2700 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 2701 TRACE_ALU_INPUT1 (HI);
c0a4c3ba 2702 GPR[rd] = HI;
f3bdd368 2703 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 2704}
2705
f2b30012
AC		 2706000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2707"mfhi r<RD>"
23850e92 2708*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2709*vr4100:
23850e92 2710*vr5000:
f14397f0
GRK		 2711// start-sanitize-vr4xxx
2712*vr4121:
2713// end-sanitize-vr4xxx
15232df4
FCE		 2714// start-sanitize-vr4320
2715*vr4320:
2716// end-sanitize-vr4320
a83d7d87 2717// start-sanitize-cygnus
90ad43b2 2718*vr5400:
a83d7d87 2719// end-sanitize-cygnus
f2b30012
AC		 2720// start-sanitize-r5900
2721*r5900:
2722// end-sanitize-r5900
2723*r3900:
2724// start-sanitize-tx19
2725*tx19:
2726// end-sanitize-tx19
2727{
c0a4c3ba
AC		 2728 do_mfhi (SD_, RD);
2729}
2730
2731
2732
2733:function:::void:do_mflo:int rd
2734{
421cbaae 2735 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
f3bdd368 2736 TRACE_ALU_INPUT1 (LO);
c0a4c3ba 2737 GPR[rd] = LO;
f3bdd368 2738 TRACE_ALU_RESULT (GPR[rd]);
f2b30012
AC		 2739}
2740
f2b30012
AC		 2741000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2742"mflo r<RD>"
23850e92 2743*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2744*vr4100:
23850e92 2745*vr5000:
f14397f0
GRK		 2746// start-sanitize-vr4xxx
2747*vr4121:
2748// end-sanitize-vr4xxx
15232df4
FCE		 2749// start-sanitize-vr4320
2750*vr4320:
2751// end-sanitize-vr4320
a83d7d87 2752// start-sanitize-cygnus
90ad43b2 2753*vr5400:
a83d7d87 2754// end-sanitize-cygnus
f2b30012
AC		 2755// start-sanitize-r5900
2756*r5900:
2757// end-sanitize-r5900
2758*r3900:
2759// start-sanitize-tx19
2760*tx19:
2761// end-sanitize-tx19
2762{
c0a4c3ba 2763 do_mflo (SD_, RD);
f2b30012
AC		 2764}
2765
2766
c0a4c3ba 2767
f2b30012
AC		 2768000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2769"movn r<RD>, r<RS>, r<RT>"
2770*mipsIV:
23850e92 2771*vr5000:
f14397f0
GRK		 2772// start-sanitize-vr4xxx
2773*vr4121:
2774// end-sanitize-vr4xxx
15232df4
FCE		 2775// start-sanitize-vr4320
2776*vr4320:
2777// end-sanitize-vr4320
a83d7d87 2778// start-sanitize-cygnus
90ad43b2 2779*vr5400:
a83d7d87 2780// end-sanitize-cygnus
f2b30012
AC		 2781// start-sanitize-r5900
2782*r5900:
2783// end-sanitize-r5900
2784{
055ee297
AC		 2785 if (GPR[RT] != 0)
2786 GPR[RD] = GPR[RS];
f2b30012
AC		 2787}
2788
2789
c0a4c3ba 2790
f2b30012
AC		 2791000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2792"movz r<RD>, r<RS>, r<RT>"
2793*mipsIV:
23850e92 2794*vr5000:
15232df4
FCE		 2795// start-sanitize-vr4320
2796*vr4320:
2797// end-sanitize-vr4320
a83d7d87 2798// start-sanitize-cygnus
90ad43b2 2799*vr5400:
a83d7d87 2800// end-sanitize-cygnus
f2b30012
AC		 2801// start-sanitize-r5900
2802*r5900:
2803// end-sanitize-r5900
2804{
055ee297
AC		 2805 if (GPR[RT] == 0)
2806 GPR[RD] = GPR[RS];
f2b30012
AC		 2807}
2808
2809
c0a4c3ba 2810
f2b30012
AC		 2811000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2812"mthi r<RS>"
23850e92 2813*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2814*vr4100:
23850e92 2815*vr5000:
f14397f0
GRK		 2816// start-sanitize-vr4xxx
2817*vr4121:
2818// end-sanitize-vr4xxx
15232df4
FCE		 2819// start-sanitize-vr4320
2820*vr4320:
2821// end-sanitize-vr4320
a83d7d87 2822// start-sanitize-cygnus
90ad43b2 2823*vr5400:
a83d7d87 2824// end-sanitize-cygnus
f2b30012
AC		 2825// start-sanitize-r5900
2826*r5900:
2827// end-sanitize-r5900
2828*r3900:
2829// start-sanitize-tx19
2830*tx19:
2831// end-sanitize-tx19
2832{
421cbaae 2833 check_mt_hilo (SD_, HIHISTORY);
055ee297 2834 HI = GPR[RS];
f2b30012
AC		 2835}
2836
2837
c0a4c3ba 2838
f2b30012
AC		 2839000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2840"mtlo r<RS>"
23850e92 2841*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2842*vr4100:
23850e92 2843*vr5000:
f14397f0
GRK		 2844// start-sanitize-vr4xxx
2845*vr4121:
2846// end-sanitize-vr4xxx
15232df4
FCE		 2847// start-sanitize-vr4320
2848*vr4320:
2849// end-sanitize-vr4320
a83d7d87 2850// start-sanitize-cygnus
90ad43b2 2851*vr5400:
a83d7d87 2852// end-sanitize-cygnus
f2b30012
AC		 2853// start-sanitize-r5900
2854*r5900:
2855// end-sanitize-r5900
2856*r3900:
2857// start-sanitize-tx19
2858*tx19:
2859// end-sanitize-tx19
2860{
421cbaae 2861 check_mt_hilo (SD_, LOHISTORY);
055ee297 2862 LO = GPR[RS];
f2b30012
AC		 2863}
2864
2865
c0a4c3ba
AC		 2866
2867:function:::void:do_mult:int rs, int rt, int rd
2868{
2869 signed64 prod;
94dda41a 2870 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 2871 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba
AC		 2872 prod = (((signed64)(signed32) GPR[rs])
2873 * ((signed64)(signed32) GPR[rt]));
2874 LO = EXTEND32 (VL4_8 (prod));
2875 HI = EXTEND32 (VH4_8 (prod));
2876 if (rd != 0)
2877 GPR[rd] = LO;
f3bdd368 2878 TRACE_ALU_RESULT2 (HI, LO);
c0a4c3ba
AC		 2879}
2880
030843d7 2881000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
f2b30012 2882"mult r<RS>, r<RT>"
23850e92 2883*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2884*vr4100:
f14397f0
GRK		 2885// start-sanitize-vr4xxx
2886*vr4121:
2887// end-sanitize-vr4xxx
15232df4
FCE		 2888// start-sanitize-vr4320
2889*vr4320:
2890// end-sanitize-vr4320
030843d7 2891{
c0a4c3ba 2892 do_mult (SD_, RS, RT, 0);
030843d7 2893}
15232df4
FCE		 2894
2895
030843d7
AC		 2896000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2897"mult r<RD>, r<RS>, r<RT>"
23850e92 2898*vr5000:
a83d7d87 2899// start-sanitize-cygnus
90ad43b2 2900*vr5400:
a83d7d87 2901// end-sanitize-cygnus
f2b30012
AC		 2902// start-sanitize-r5900
2903*r5900:
2904// end-sanitize-r5900
2905*r3900:
2906// start-sanitize-tx19
2907*tx19:
2908// end-sanitize-tx19
2909{
c0a4c3ba
AC		 2910 do_mult (SD_, RS, RT, RD);
2911}
2912
2913
2914:function:::void:do_multu:int rs, int rt, int rd
2915{
2916 unsigned64 prod;
94dda41a 2917 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
f3bdd368 2918 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba
AC		 2919 prod = (((unsigned64)(unsigned32) GPR[rs])
2920 * ((unsigned64)(unsigned32) GPR[rt]));
f2b30012
AC		 2921 LO = EXTEND32 (VL4_8 (prod));
2922 HI = EXTEND32 (VH4_8 (prod));
c0a4c3ba
AC		 2923 if (rd != 0)
2924 GPR[rd] = LO;
f3bdd368 2925 TRACE_ALU_RESULT2 (HI, LO);
f2b30012
AC		 2926}
2927
030843d7 2928000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
f2b30012 2929"multu r<RS>, r<RT>"
23850e92 2930*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2931*vr4100:
f14397f0
GRK		 2932// start-sanitize-vr4xxx
2933*vr4121:
2934// end-sanitize-vr4xxx
15232df4
FCE		 2935// start-sanitize-vr4320
2936*vr4320:
2937// end-sanitize-vr4320
030843d7 2938{
c0a4c3ba 2939 do_multu (SD_, RS, RT, 0);
030843d7 2940}
c0a4c3ba 2941
030843d7
AC		 2942000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2943"multu r<RD>, r<RS>, r<RT>"
23850e92 2944*vr5000:
a83d7d87 2945// start-sanitize-cygnus
90ad43b2 2946*vr5400:
a83d7d87 2947// end-sanitize-cygnus
f2b30012
AC		 2948// start-sanitize-r5900
2949*r5900:
2950// end-sanitize-r5900
2951*r3900:
2952// start-sanitize-tx19
2953*tx19:
2954// end-sanitize-tx19
2955{
c0a4c3ba 2956 do_multu (SD_, RS, RT, 0);
f2b30012
AC		 2957}
2958
2959
c0a4c3ba
AC		 2960:function:::void:do_nor:int rs, int rt, int rd
2961{
f3bdd368 2962 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 2963 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
f3bdd368 2964 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 2965}
2966
f2b30012
AC		 2967000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2968"nor r<RD>, r<RS>, r<RT>"
23850e92 2969*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 2970*vr4100:
23850e92 2971*vr5000:
f14397f0
GRK		 2972// start-sanitize-vr4xxx
2973*vr4121:
2974// end-sanitize-vr4xxx
15232df4
FCE		 2975// start-sanitize-vr4320
2976*vr4320:
2977// end-sanitize-vr4320
a83d7d87 2978// start-sanitize-cygnus
90ad43b2 2979*vr5400:
a83d7d87 2980// end-sanitize-cygnus
f2b30012
AC		 2981// start-sanitize-r5900
2982*r5900:
2983// end-sanitize-r5900
2984*r3900:
2985// start-sanitize-tx19
2986*tx19:
2987// end-sanitize-tx19
2988{
c0a4c3ba 2989 do_nor (SD_, RS, RT, RD);
f2b30012
AC		 2990}
2991
2992
c0a4c3ba
AC		 2993:function:::void:do_or:int rs, int rt, int rd
2994{
f3bdd368 2995 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 2996 GPR[rd] = (GPR[rs] | GPR[rt]);
f3bdd368 2997 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 2998}
2999
f2b30012
AC		 3000000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
3001"or r<RD>, r<RS>, r<RT>"
23850e92 3002*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3003*vr4100:
23850e92 3004*vr5000:
f14397f0
GRK		 3005// start-sanitize-vr4xxx
3006*vr4121:
3007// end-sanitize-vr4xxx
15232df4
FCE		 3008// start-sanitize-vr4320
3009*vr4320:
3010// end-sanitize-vr4320
a83d7d87 3011// start-sanitize-cygnus
90ad43b2 3012*vr5400:
a83d7d87 3013// end-sanitize-cygnus
f2b30012
AC		 3014// start-sanitize-r5900
3015*r5900:
3016// end-sanitize-r5900
3017*r3900:
3018// start-sanitize-tx19
3019*tx19:
3020// end-sanitize-tx19
3021{
c0a4c3ba 3022 do_or (SD_, RS, RT, RD);
f2b30012
AC		 3023}
3024
3025
f3bdd368
AC		 3026
3027:function:::void:do_ori:int rs, int rt, unsigned immediate
3028{
3029 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3030 GPR[rt] = (GPR[rs] | immediate);
3031 TRACE_ALU_RESULT (GPR[rt]);
3032}
3033
f2b30012 3034001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
055ee297 3035"ori r<RT>, r<RS>, <IMMEDIATE>"
23850e92 3036*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3037*vr4100:
23850e92 3038*vr5000:
f14397f0
GRK		 3039// start-sanitize-vr4xxx
3040*vr4121:
3041// end-sanitize-vr4xxx
15232df4
FCE		 3042// start-sanitize-vr4320
3043*vr4320:
3044// end-sanitize-vr4320
a83d7d87 3045// start-sanitize-cygnus
90ad43b2 3046*vr5400:
a83d7d87 3047// end-sanitize-cygnus
f2b30012
AC		 3048// start-sanitize-r5900
3049*r5900:
3050// end-sanitize-r5900
3051*r3900:
3052// start-sanitize-tx19
3053*tx19:
3054// end-sanitize-tx19
3055{
f3bdd368 3056 do_ori (SD_, RS, RT, IMMEDIATE);
f2b30012
AC		 3057}
3058
3059
3060110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
3061*mipsIV:
23850e92 3062*vr5000:
15232df4
FCE		 3063// start-sanitize-vr4320
3064*vr4320:
3065// end-sanitize-vr4320
a83d7d87 3066// start-sanitize-cygnus
90ad43b2 3067*vr5400:
a83d7d87 3068// end-sanitize-cygnus
f2b30012
AC		 3069// start-sanitize-r5900
3070*r5900:
3071// end-sanitize-r5900
3072{
3073 unsigned32 instruction = instruction_0;
055ee297
AC		 3074 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3075 int hint = ((instruction >> 16) & 0x0000001F);
3076 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 3077 {
49a76833
AC		 3078 address_word vaddr = ((unsigned64)op1 + offset);
3079 address_word paddr;
f2b30012
AC		 3080 int uncached;
3081 {
3082 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3083 Prefetch(uncached,paddr,vaddr,isDATA,hint);
3084 }
3085 }
3086}
3087
ebcfd86a
FCE		 3088:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
3089{
3090 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3091 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
3092 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
3093 unsigned int byte;
3094 address_word paddr;
3095 int uncached;
3096 unsigned64 memval;
3097 address_word vaddr;
3098
3099 vaddr = base + offset;
3100 if ((vaddr & access) != 0)
3101 SignalExceptionAddressStore ();
3102 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3103 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
3104 byte = ((vaddr & mask) ^ bigendiancpu);
3105 memval = (word << (8 * byte));
3106 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
3107}
3108
3109
f2b30012
AC		 3110101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
3111"sb r<RT>, <OFFSET>(r<BASE>)"
23850e92 3112*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3113*vr4100:
23850e92 3114*vr5000:
f14397f0
GRK		 3115// start-sanitize-vr4xxx
3116*vr4121:
3117// end-sanitize-vr4xxx
15232df4
FCE		 3118// start-sanitize-vr4320
3119*vr4320:
3120// end-sanitize-vr4320
a83d7d87 3121// start-sanitize-cygnus
90ad43b2 3122*vr5400:
a83d7d87 3123// end-sanitize-cygnus
f2b30012
AC		 3124// start-sanitize-r5900
3125*r5900:
3126// end-sanitize-r5900
3127*r3900:
3128// start-sanitize-tx19
3129*tx19:
3130// end-sanitize-tx19
3131{
ebcfd86a 3132 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 3133}
3134
3135
3136111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
3137"sc r<RT>, <OFFSET>(r<BASE>)"
3138*mipsII:
3139*mipsIII:
3140*mipsIV:
1ee7d2b1 3141*vr4100:
23850e92 3142*vr5000:
f14397f0
GRK		 3143// start-sanitize-vr4xxx
3144*vr4121:
3145// end-sanitize-vr4xxx
15232df4
FCE		 3146// start-sanitize-vr4320
3147*vr4320:
3148// end-sanitize-vr4320
a83d7d87 3149// start-sanitize-cygnus
90ad43b2 3150*vr5400:
a83d7d87 3151// end-sanitize-cygnus
f2b30012
AC		 3152// start-sanitize-r5900
3153*r5900:
3154// end-sanitize-r5900
f2b30012
AC		 3155// start-sanitize-tx19
3156*tx19:
3157// end-sanitize-tx19
3158{
3159 unsigned32 instruction = instruction_0;
055ee297
AC		 3160 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3161 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3162 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 3163 {
49a76833
AC		 3164 address_word vaddr = ((unsigned64)op1 + offset);
3165 address_word paddr;
f2b30012
AC		 3166 int uncached;
3167 if ((vaddr & 3) != 0)
055ee297 3168 SignalExceptionAddressStore();
f2b30012
AC		 3169 else
3170 {
3171 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3172 {
3173 unsigned64 memval = 0;
3174 unsigned64 memval1 = 0;
3175 unsigned64 mask = 0x7;
3176 unsigned int byte;
3177 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3178 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3179 memval = ((unsigned64) op2 << (8 * byte));
3180 if (LLBIT)
3181 {
3182 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3183 }
3184 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
3185 }
3186 }
3187 }
3188}
3189
3190
3191111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
3192"scd r<RT>, <OFFSET>(r<BASE>)"
3193*mipsIII:
3194*mipsIV:
1ee7d2b1 3195*vr4100:
23850e92 3196*vr5000:
f14397f0
GRK		 3197// start-sanitize-vr4xxx
3198*vr4121:
3199// end-sanitize-vr4xxx
15232df4
FCE		 3200// start-sanitize-vr4320
3201*vr4320:
3202// end-sanitize-vr4320
a83d7d87 3203// start-sanitize-cygnus
90ad43b2 3204*vr5400:
a83d7d87 3205// end-sanitize-cygnus
f2b30012
AC		 3206// start-sanitize-r5900
3207*r5900:
3208// end-sanitize-r5900
f2b30012
AC		 3209// start-sanitize-tx19
3210*tx19:
3211// end-sanitize-tx19
3212{
3213 unsigned32 instruction = instruction_0;
055ee297
AC		 3214 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3215 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3216 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 3217 {
49a76833
AC		 3218 address_word vaddr = ((unsigned64)op1 + offset);
3219 address_word paddr;
f2b30012
AC		 3220 int uncached;
3221 if ((vaddr & 7) != 0)
055ee297 3222 SignalExceptionAddressStore();
f2b30012
AC		 3223 else
3224 {
3225 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3226 {
3227 unsigned64 memval = 0;
3228 unsigned64 memval1 = 0;
3229 memval = op2;
3230 if (LLBIT)
3231 {
3232 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
3233 }
3234 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
3235 }
3236 }
3237 }
3238}
3239
3240
3241111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
3242"sd r<RT>, <OFFSET>(r<BASE>)"
3243*mipsIII:
3244*mipsIV:
1ee7d2b1 3245*vr4100:
23850e92 3246*vr5000:
f14397f0
GRK		 3247// start-sanitize-vr4xxx
3248*vr4121:
3249// end-sanitize-vr4xxx
15232df4
FCE		 3250// start-sanitize-vr4320
3251*vr4320:
3252// end-sanitize-vr4320
a83d7d87 3253// start-sanitize-cygnus
90ad43b2 3254*vr5400:
a83d7d87 3255// end-sanitize-cygnus
f2b30012
AC		 3256// start-sanitize-r5900
3257*r5900:
3258// end-sanitize-r5900
f2b30012
AC		 3259// start-sanitize-tx19
3260*tx19:
3261// end-sanitize-tx19
ebcfd86a
FCE		 3262{
3263 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
15232df4 3264}
15232df4
FCE		 3265
3266
ebcfd86a
FCE		 32671111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3268"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3269*mipsII:
3270*mipsIII:
3271*mipsIV:
1ee7d2b1 3272*vr4100:
ebcfd86a 3273*vr5000:
f14397f0
GRK		 3274// start-sanitize-vr4xxx
3275*vr4121:
3276// end-sanitize-vr4xxx
ebcfd86a
FCE		 3277// start-sanitize-vr4320
3278*vr4320:
3279// end-sanitize-vr4320
a83d7d87 3280// start-sanitize-cygnus
ebcfd86a 3281*vr5400:
a83d7d87 3282// end-sanitize-cygnus
ebcfd86a
FCE		 3283// start-sanitize-tx19
3284*tx19:
3285// end-sanitize-tx19
3286{
3287 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3288}
3289
15232df4 3290
f2b30012
AC		 3291101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3292"sdl r<RT>, <OFFSET>(r<BASE>)"
3293*mipsIII:
3294*mipsIV:
1ee7d2b1 3295*vr4100:
23850e92 3296*vr5000:
f14397f0
GRK		 3297// start-sanitize-vr4xxx
3298*vr4121:
3299// end-sanitize-vr4xxx
15232df4
FCE		 3300// start-sanitize-vr4320
3301*vr4320:
3302// end-sanitize-vr4320
a83d7d87 3303// start-sanitize-cygnus
90ad43b2 3304*vr5400:
a83d7d87 3305// end-sanitize-cygnus
f2b30012
AC		 3306// start-sanitize-r5900
3307*r5900:
3308// end-sanitize-r5900
f2b30012
AC		 3309// start-sanitize-tx19
3310*tx19:
3311// end-sanitize-tx19
3312{
ebcfd86a 3313 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 3314}
3315
3316
3317101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3318"sdr r<RT>, <OFFSET>(r<BASE>)"
3319*mipsIII:
3320*mipsIV:
1ee7d2b1 3321*vr4100:
23850e92 3322*vr5000:
f14397f0
GRK		 3323// start-sanitize-vr4xxx
3324*vr4121:
3325// end-sanitize-vr4xxx
15232df4
FCE		 3326// start-sanitize-vr4320
3327*vr4320:
3328// end-sanitize-vr4320
a83d7d87 3329// start-sanitize-cygnus
90ad43b2 3330*vr5400:
a83d7d87 3331// end-sanitize-cygnus
f2b30012
AC		 3332// start-sanitize-r5900
3333*r5900:
3334// end-sanitize-r5900
f2b30012
AC		 3335// start-sanitize-tx19
3336*tx19:
3337// end-sanitize-tx19
3338{
ebcfd86a 3339 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 3340}
3341
3342
3343101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3344"sh r<RT>, <OFFSET>(r<BASE>)"
23850e92 3345*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3346*vr4100:
23850e92 3347*vr5000:
f14397f0
GRK		 3348// start-sanitize-vr4xxx
3349*vr4121:
3350// end-sanitize-vr4xxx
15232df4
FCE		 3351// start-sanitize-vr4320
3352*vr4320:
3353// end-sanitize-vr4320
a83d7d87 3354// start-sanitize-cygnus
90ad43b2 3355*vr5400:
a83d7d87 3356// end-sanitize-cygnus
f2b30012
AC		 3357// start-sanitize-r5900
3358*r5900:
3359// end-sanitize-r5900
3360*r3900:
3361// start-sanitize-tx19
3362*tx19:
3363// end-sanitize-tx19
3364{
ebcfd86a 3365 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 3366}
3367
3368
c0a4c3ba
AC		 3369:function:::void:do_sll:int rt, int rd, int shift
3370{
3371 unsigned32 temp = (GPR[rt] << shift);
f3bdd368 3372 TRACE_ALU_INPUT2 (GPR[rt], shift);
c0a4c3ba 3373 GPR[rd] = EXTEND32 (temp);
f3bdd368 3374 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 3375}
3376
055ee297
AC		 337700000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
3378"sll r<RD>, r<RT>, <SHIFT>"
23850e92 3379*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3380*vr4100:
23850e92 3381*vr5000:
f14397f0
GRK		 3382// start-sanitize-vr4xxx
3383*vr4121:
3384// end-sanitize-vr4xxx
15232df4
FCE		 3385// start-sanitize-vr4320
3386*vr4320:
3387// end-sanitize-vr4320
a83d7d87 3388// start-sanitize-cygnus
90ad43b2 3389*vr5400:
a83d7d87 3390// end-sanitize-cygnus
f2b30012
AC		 3391// start-sanitize-r5900
3392*r5900:
3393// end-sanitize-r5900
3394*r3900:
3395// start-sanitize-tx19
3396*tx19:
3397// end-sanitize-tx19
3398{
c0a4c3ba 3399 do_sll (SD_, RT, RD, SHIFT);
f2b30012
AC		 3400}
3401
3402
c0a4c3ba
AC		 3403:function:::void:do_sllv:int rs, int rt, int rd
3404{
3405 int s = MASKED (GPR[rs], 4, 0);
3406 unsigned32 temp = (GPR[rt] << s);
f3bdd368 3407 TRACE_ALU_INPUT2 (GPR[rt], s);
c0a4c3ba 3408 GPR[rd] = EXTEND32 (temp);
f3bdd368 3409 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 3410}
3411
055ee297 3412000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
f2b30012 3413"sllv r<RD>, r<RT>, r<RS>"
23850e92 3414*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3415*vr4100:
23850e92 3416*vr5000:
f14397f0
GRK		 3417// start-sanitize-vr4xxx
3418*vr4121:
3419// end-sanitize-vr4xxx
15232df4
FCE		 3420// start-sanitize-vr4320
3421*vr4320:
3422// end-sanitize-vr4320
a83d7d87 3423// start-sanitize-cygnus
90ad43b2 3424*vr5400:
a83d7d87 3425// end-sanitize-cygnus
f2b30012
AC		 3426// start-sanitize-r5900
3427*r5900:
3428// end-sanitize-r5900
3429*r3900:
3430// start-sanitize-tx19
3431*tx19:
3432// end-sanitize-tx19
3433{
c0a4c3ba 3434 do_sllv (SD_, RS, RT, RD);
f2b30012
AC		 3435}
3436
3437
c0a4c3ba
AC		 3438:function:::void:do_slt:int rs, int rt, int rd
3439{
f3bdd368 3440 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 3441 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
f3bdd368 3442 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 3443}
3444
f2b30012
AC		 3445000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
3446"slt r<RD>, r<RS>, r<RT>"
23850e92 3447*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3448*vr4100:
23850e92 3449*vr5000:
f14397f0
GRK		 3450// start-sanitize-vr4xxx
3451*vr4121:
3452// end-sanitize-vr4xxx
15232df4
FCE		 3453// start-sanitize-vr4320
3454*vr4320:
3455// end-sanitize-vr4320
a83d7d87 3456// start-sanitize-cygnus
90ad43b2 3457*vr5400:
a83d7d87 3458// end-sanitize-cygnus
f2b30012
AC		 3459// start-sanitize-r5900
3460*r5900:
3461// end-sanitize-r5900
3462*r3900:
3463// start-sanitize-tx19
3464*tx19:
3465// end-sanitize-tx19
3466{
c0a4c3ba 3467 do_slt (SD_, RS, RT, RD);
f2b30012
AC		 3468}
3469
3470
c0a4c3ba
AC		 3471:function:::void:do_slti:int rs, int rt, unsigned16 immediate
3472{
f3bdd368 3473 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
c0a4c3ba 3474 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
f3bdd368 3475 TRACE_ALU_RESULT (GPR[rt]);
c0a4c3ba
AC		 3476}
3477
f2b30012 3478001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
055ee297 3479"slti r<RT>, r<RS>, <IMMEDIATE>"
23850e92 3480*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3481*vr4100:
23850e92 3482*vr5000:
f14397f0
GRK		 3483// start-sanitize-vr4xxx
3484*vr4121:
3485// end-sanitize-vr4xxx
15232df4
FCE		 3486// start-sanitize-vr4320
3487*vr4320:
3488// end-sanitize-vr4320
a83d7d87 3489// start-sanitize-cygnus
90ad43b2 3490*vr5400:
a83d7d87 3491// end-sanitize-cygnus
f2b30012
AC		 3492// start-sanitize-r5900
3493*r5900:
3494// end-sanitize-r5900
3495*r3900:
3496// start-sanitize-tx19
3497*tx19:
3498// end-sanitize-tx19
3499{
c0a4c3ba 3500 do_slti (SD_, RS, RT, IMMEDIATE);
f2b30012
AC		 3501}
3502
3503
c0a4c3ba
AC		 3504:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3505{
f3bdd368 3506 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
c0a4c3ba 3507 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
f3bdd368 3508 TRACE_ALU_RESULT (GPR[rt]);
c0a4c3ba
AC		 3509}
3510
f2b30012 3511001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
055ee297 3512"sltiu r<RT>, r<RS>, <IMMEDIATE>"
23850e92 3513*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3514*vr4100:
23850e92 3515*vr5000:
f14397f0
GRK		 3516// start-sanitize-vr4xxx
3517*vr4121:
3518// end-sanitize-vr4xxx
15232df4
FCE		 3519// start-sanitize-vr4320
3520*vr4320:
3521// end-sanitize-vr4320
a83d7d87 3522// start-sanitize-cygnus
90ad43b2 3523*vr5400:
a83d7d87 3524// end-sanitize-cygnus
f2b30012
AC		 3525// start-sanitize-r5900
3526*r5900:
3527// end-sanitize-r5900
3528*r3900:
3529// start-sanitize-tx19
3530*tx19:
3531// end-sanitize-tx19
3532{
c0a4c3ba
AC		 3533 do_sltiu (SD_, RS, RT, IMMEDIATE);
3534}
3535
3536
3537
3538:function:::void:do_sltu:int rs, int rt, int rd
3539{
f3bdd368 3540 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 3541 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
f3bdd368 3542 TRACE_ALU_RESULT (GPR[rd]);
f2b30012
AC		 3543}
3544
3545000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3546"sltu r<RD>, r<RS>, r<RT>"
23850e92 3547*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3548*vr4100:
23850e92 3549*vr5000:
f14397f0
GRK		 3550// start-sanitize-vr4xxx
3551*vr4121:
3552// end-sanitize-vr4xxx
15232df4
FCE		 3553// start-sanitize-vr4320
3554*vr4320:
3555// end-sanitize-vr4320
a83d7d87 3556// start-sanitize-cygnus
90ad43b2 3557*vr5400:
a83d7d87 3558// end-sanitize-cygnus
f2b30012
AC		 3559// start-sanitize-r5900
3560*r5900:
3561// end-sanitize-r5900
3562*r3900:
3563// start-sanitize-tx19
3564*tx19:
3565// end-sanitize-tx19
3566{
f3bdd368 3567 do_sltu (SD_, RS, RT, RD);
f2b30012
AC		 3568}
3569
3570
c0a4c3ba
AC		 3571:function:::void:do_sra:int rt, int rd, int shift
3572{
3573 signed32 temp = (signed32) GPR[rt] >> shift;
f3bdd368 3574 TRACE_ALU_INPUT2 (GPR[rt], shift);
c0a4c3ba 3575 GPR[rd] = EXTEND32 (temp);
f3bdd368 3576 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 3577}
3578
055ee297
AC		 3579000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3580"sra r<RD>, r<RT>, <SHIFT>"
23850e92 3581*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3582*vr4100:
23850e92 3583*vr5000:
f14397f0
GRK		 3584// start-sanitize-vr4xxx
3585*vr4121:
3586// end-sanitize-vr4xxx
15232df4
FCE		 3587// start-sanitize-vr4320
3588*vr4320:
3589// end-sanitize-vr4320
a83d7d87 3590// start-sanitize-cygnus
90ad43b2 3591*vr5400:
a83d7d87 3592// end-sanitize-cygnus
f2b30012
AC		 3593// start-sanitize-r5900
3594*r5900:
3595// end-sanitize-r5900
3596*r3900:
3597// start-sanitize-tx19
3598*tx19:
3599// end-sanitize-tx19
3600{
c0a4c3ba 3601 do_sra (SD_, RT, RD, SHIFT);
f2b30012
AC		 3602}
3603
3604
74025eee
AC		 3605
3606:function:::void:do_srav:int rs, int rt, int rd
3607{
3608 int s = MASKED (GPR[rs], 4, 0);
3609 signed32 temp = (signed32) GPR[rt] >> s;
3610 TRACE_ALU_INPUT2 (GPR[rt], s);
3611 GPR[rd] = EXTEND32 (temp);
3612 TRACE_ALU_RESULT (GPR[rd]);
3613}
3614
f2b30012
AC		 3615000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3616"srav r<RD>, r<RT>, r<RS>"
23850e92 3617*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3618*vr4100:
23850e92 3619*vr5000:
f14397f0
GRK		 3620// start-sanitize-vr4xxx
3621*vr4121:
3622// end-sanitize-vr4xxx
15232df4
FCE		 3623// start-sanitize-vr4320
3624*vr4320:
3625// end-sanitize-vr4320
a83d7d87 3626// start-sanitize-cygnus
90ad43b2 3627*vr5400:
a83d7d87 3628// end-sanitize-cygnus
f2b30012
AC		 3629// start-sanitize-r5900
3630*r5900:
3631// end-sanitize-r5900
3632*r3900:
3633// start-sanitize-tx19
3634*tx19:
3635// end-sanitize-tx19
3636{
74025eee 3637 do_srav (SD_, RS, RT, RD);
f2b30012
AC		 3638}
3639
3640
74025eee 3641
c0a4c3ba
AC		 3642:function:::void:do_srl:int rt, int rd, int shift
3643{
3644 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
f3bdd368 3645 TRACE_ALU_INPUT2 (GPR[rt], shift);
c0a4c3ba 3646 GPR[rd] = EXTEND32 (temp);
f3bdd368 3647 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 3648}
3649
055ee297
AC		 3650000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3651"srl r<RD>, r<RT>, <SHIFT>"
23850e92 3652*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3653*vr4100:
23850e92 3654*vr5000:
f14397f0
GRK		 3655// start-sanitize-vr4xxx
3656*vr4121:
3657// end-sanitize-vr4xxx
15232df4
FCE		 3658// start-sanitize-vr4320
3659*vr4320:
3660// end-sanitize-vr4320
a83d7d87 3661// start-sanitize-cygnus
90ad43b2 3662*vr5400:
a83d7d87 3663// end-sanitize-cygnus
f2b30012
AC		 3664// start-sanitize-r5900
3665*r5900:
3666// end-sanitize-r5900
3667*r3900:
3668// start-sanitize-tx19
3669*tx19:
3670// end-sanitize-tx19
3671{
c0a4c3ba 3672 do_srl (SD_, RT, RD, SHIFT);
f2b30012
AC		 3673}
3674
3675
c0a4c3ba
AC		 3676:function:::void:do_srlv:int rs, int rt, int rd
3677{
3678 int s = MASKED (GPR[rs], 4, 0);
3679 unsigned32 temp = (unsigned32) GPR[rt] >> s;
f3bdd368 3680 TRACE_ALU_INPUT2 (GPR[rt], s);
c0a4c3ba 3681 GPR[rd] = EXTEND32 (temp);
f3bdd368 3682 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 3683}
3684
f2b30012
AC		 3685000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3686"srlv r<RD>, r<RT>, r<RS>"
23850e92 3687*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3688*vr4100:
23850e92 3689*vr5000:
f14397f0
GRK		 3690// start-sanitize-vr4xxx
3691*vr4121:
3692// end-sanitize-vr4xxx
15232df4
FCE		 3693// start-sanitize-vr4320
3694*vr4320:
3695// end-sanitize-vr4320
a83d7d87 3696// start-sanitize-cygnus
90ad43b2 3697*vr5400:
a83d7d87 3698// end-sanitize-cygnus
f2b30012
AC		 3699// start-sanitize-r5900
3700*r5900:
3701// end-sanitize-r5900
3702*r3900:
3703// start-sanitize-tx19
3704*tx19:
3705// end-sanitize-tx19
3706{
c0a4c3ba 3707 do_srlv (SD_, RS, RT, RD);
f2b30012
AC		 3708}
3709
3710
3711000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3712"sub r<RD>, r<RS>, r<RT>"
23850e92 3713*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3714*vr4100:
23850e92 3715*vr5000:
f14397f0
GRK		 3716// start-sanitize-vr4xxx
3717*vr4121:
3718// end-sanitize-vr4xxx
15232df4
FCE		 3719// start-sanitize-vr4320
3720*vr4320:
3721// end-sanitize-vr4320
a83d7d87 3722// start-sanitize-cygnus
90ad43b2 3723*vr5400:
a83d7d87 3724// end-sanitize-cygnus
f2b30012
AC		 3725// start-sanitize-r5900
3726*r5900:
3727// end-sanitize-r5900
3728*r3900:
3729// start-sanitize-tx19
3730*tx19:
3731// end-sanitize-tx19
3732{
26feb3a8
AC		 3733 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3734 {
3735 ALU32_BEGIN (GPR[RS]);
3736 ALU32_SUB (GPR[RT]);
3737 ALU32_END (GPR[RD]);
3738 }
3739 TRACE_ALU_RESULT (GPR[RD]);
f2b30012
AC		 3740}
3741
3742
c0a4c3ba
AC		 3743:function:::void:do_subu:int rs, int rt, int rd
3744{
f3bdd368
AC		 3745 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3746 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3747 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 3748}
3749
f2b30012
AC		 3750000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3751"subu r<RD>, r<RS>, r<RT>"
23850e92 3752*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3753*vr4100:
23850e92 3754*vr5000:
f14397f0
GRK		 3755// start-sanitize-vr4xxx
3756*vr4121:
3757// end-sanitize-vr4xxx
15232df4
FCE		 3758// start-sanitize-vr4320
3759*vr4320:
3760// end-sanitize-vr4320
a83d7d87 3761// start-sanitize-cygnus
90ad43b2 3762*vr5400:
a83d7d87 3763// end-sanitize-cygnus
f2b30012
AC		 3764// start-sanitize-r5900
3765*r5900:
3766// end-sanitize-r5900
3767*r3900:
3768// start-sanitize-tx19
3769*tx19:
3770// end-sanitize-tx19
3771{
c0a4c3ba 3772 do_subu (SD_, RS, RT, RD);
f2b30012
AC		 3773}
3774
3775
3776101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3777"sw r<RT>, <OFFSET>(r<BASE>)"
23850e92 3778*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3779*vr4100:
f14397f0
GRK		 3780// start-sanitize-vr4xxx
3781*vr4121:
3782// end-sanitize-vr4xxx
ebcfd86a
FCE		 3783// start-sanitize-tx19
3784*tx19:
3785// end-sanitize-tx19
3786*r3900:
15232df4
FCE		 3787// start-sanitize-vr4320
3788*vr4320:
3789// end-sanitize-vr4320
ebcfd86a 3790*vr5000:
a83d7d87 3791// start-sanitize-cygnus
90ad43b2 3792*vr5400:
a83d7d87 3793// end-sanitize-cygnus
f2b30012
AC		 3794// start-sanitize-r5900
3795*r5900:
3796// end-sanitize-r5900
f2b30012 3797{
ebcfd86a 3798 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 3799}
3800
3801
085c1cb9 38021110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
f2b30012 3803"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
23850e92 3804*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3805*vr4100:
23850e92 3806*vr5000:
f14397f0
GRK		 3807// start-sanitize-vr4xxx
3808*vr4121:
3809// end-sanitize-vr4xxx
15232df4
FCE		 3810// start-sanitize-vr4320
3811*vr4320:
3812// end-sanitize-vr4320
a83d7d87 3813// start-sanitize-cygnus
90ad43b2 3814*vr5400:
a83d7d87 3815// end-sanitize-cygnus
f2b30012
AC		 3816*r3900:
3817// start-sanitize-tx19
3818*tx19:
3819// end-sanitize-tx19
3820{
ebcfd86a
FCE		 3821 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3822}
3823
3824
3825
3826:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3827{
3828 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3829 address_word reverseendian = (ReverseEndian ? -1 : 0);
3830 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3831 unsigned int byte;
0e797366 3832 unsigned int word;
ebcfd86a
FCE		 3833 address_word paddr;
3834 int uncached;
3835 unsigned64 memval;
3836 address_word vaddr;
0e797366
AC		 3837 int nr_lhs_bits;
3838 int nr_rhs_bits;
ebcfd86a
FCE		 3839
3840 vaddr = base + offset;
3841 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3842 paddr = (paddr ^ (reverseendian & mask));
3843 if (BigEndianMem == 0)
3844 paddr = paddr & ~access;
0e797366
AC		 3845
3846 /* compute where within the word/mem we are */
3847 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3848 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3849 nr_lhs_bits = 8 * byte + 8;
3850 nr_rhs_bits = 8 * access - 8 * byte;
3851 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3852 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3853 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3854 (long) ((unsigned64) paddr >> 32), (long) paddr,
3855 word, byte, nr_lhs_bits, nr_rhs_bits); */
3856
3857 if (word == 0)
3858 {
3859 memval = (rt >> nr_rhs_bits);
3860 }
ebcfd86a 3861 else
0e797366
AC		 3862 {
3863 memval = (rt << nr_lhs_bits);
3864 }
3865 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3866 (long) ((unsigned64) rt >> 32), (long) rt,
3867 (long) ((unsigned64) memval >> 32), (long) memval); */
3868 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
f2b30012
AC		 3869}
3870
3871
3872101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3873"swl r<RT>, <OFFSET>(r<BASE>)"
23850e92 3874*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3875*vr4100:
23850e92 3876*vr5000:
f14397f0
GRK		 3877// start-sanitize-vr4xxx
3878*vr4121:
3879// end-sanitize-vr4xxx
15232df4
FCE		 3880// start-sanitize-vr4320
3881*vr4320:
3882// end-sanitize-vr4320
a83d7d87 3883// start-sanitize-cygnus
90ad43b2 3884*vr5400:
a83d7d87 3885// end-sanitize-cygnus
f2b30012
AC		 3886// start-sanitize-r5900
3887*r5900:
3888// end-sanitize-r5900
3889*r3900:
3890// start-sanitize-tx19
3891*tx19:
3892// end-sanitize-tx19
3893{
ebcfd86a 3894 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 3895}
3896
3897
ebcfd86a
FCE		 3898:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3899{
3900 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3901 address_word reverseendian = (ReverseEndian ? -1 : 0);
3902 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3903 unsigned int byte;
3904 address_word paddr;
3905 int uncached;
3906 unsigned64 memval;
3907 address_word vaddr;
3908
3909 vaddr = base + offset;
3910 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3911 paddr = (paddr ^ (reverseendian & mask));
3912 if (BigEndianMem != 0)
3913 paddr &= ~access;
3914 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3915 memval = (rt << (byte * 8));
3916 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3917}
3918
f2b30012
AC		 3919101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3920"swr r<RT>, <OFFSET>(r<BASE>)"
23850e92 3921*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3922*vr4100:
23850e92 3923*vr5000:
f14397f0
GRK		 3924// start-sanitize-vr4xxx
3925*vr4121:
3926// end-sanitize-vr4xxx
15232df4
FCE		 3927// start-sanitize-vr4320
3928*vr4320:
3929// end-sanitize-vr4320
a83d7d87 3930// start-sanitize-cygnus
90ad43b2 3931*vr5400:
a83d7d87 3932// end-sanitize-cygnus
f2b30012
AC		 3933// start-sanitize-r5900
3934*r5900:
3935// end-sanitize-r5900
3936*r3900:
3937// start-sanitize-tx19
3938*tx19:
3939// end-sanitize-tx19
3940{
ebcfd86a 3941 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 3942}
3943
3944
3945000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3946"sync":STYPE == 0
3947"sync <STYPE>"
3948*mipsII:
3949*mipsIII:
3950*mipsIV:
1ee7d2b1 3951*vr4100:
23850e92 3952*vr5000:
f14397f0
GRK		 3953// start-sanitize-vr4xxx
3954*vr4121:
3955// end-sanitize-vr4xxx
15232df4
FCE		 3956// start-sanitize-vr4320
3957*vr4320:
3958// end-sanitize-vr4320
a83d7d87 3959// start-sanitize-cygnus
90ad43b2 3960*vr5400:
a83d7d87 3961// end-sanitize-cygnus
f2b30012
AC		 3962// start-sanitize-r5900
3963*r5900:
3964// end-sanitize-r5900
3965*r3900:
3966// start-sanitize-tx19
3967*tx19:
3968// end-sanitize-tx19
3969{
085c1cb9 3970 SyncOperation (STYPE);
f2b30012
AC		 3971}
3972
3973
3974000000,20.CODE,001100:SPECIAL:32::SYSCALL
3975"syscall <CODE>"
23850e92 3976*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 3977*vr4100:
23850e92 3978*vr5000:
f14397f0
GRK		 3979// start-sanitize-vr4xxx
3980*vr4121:
3981// end-sanitize-vr4xxx
15232df4
FCE		 3982// start-sanitize-vr4320
3983*vr4320:
3984// end-sanitize-vr4320
a83d7d87 3985// start-sanitize-cygnus
90ad43b2 3986*vr5400:
a83d7d87 3987// end-sanitize-cygnus
f2b30012
AC		 3988// start-sanitize-r5900
3989*r5900:
3990// end-sanitize-r5900
3991*r3900:
3992// start-sanitize-tx19
3993*tx19:
3994// end-sanitize-tx19
3995{
055ee297 3996 SignalException(SystemCall, instruction_0);
f2b30012
AC		 3997}
3998
3999
4000000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
4001"teq r<RS>, r<RT>"
4002*mipsII:
4003*mipsIII:
4004*mipsIV:
1ee7d2b1 4005*vr4100:
23850e92 4006*vr5000:
f14397f0
GRK		 4007// start-sanitize-vr4xxx
4008*vr4121:
4009// end-sanitize-vr4xxx
15232df4
FCE		 4010// start-sanitize-vr4320
4011*vr4320:
4012// end-sanitize-vr4320
a83d7d87 4013// start-sanitize-cygnus
90ad43b2 4014*vr5400:
a83d7d87 4015// end-sanitize-cygnus
f2b30012
AC		 4016// start-sanitize-r5900
4017*r5900:
4018// end-sanitize-r5900
f2b30012
AC		 4019// start-sanitize-tx19
4020*tx19:
4021// end-sanitize-tx19
4022{
a94c5493 4023 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
055ee297 4024 SignalException(Trap, instruction_0);
f2b30012
AC		 4025}
4026
4027
4028000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
4029"teqi r<RS>, <IMMEDIATE>"
4030*mipsII:
4031*mipsIII:
4032*mipsIV:
1ee7d2b1 4033*vr4100:
23850e92 4034*vr5000:
f14397f0
GRK		 4035// start-sanitize-vr4xxx
4036*vr4121:
4037// end-sanitize-vr4xxx
15232df4
FCE		 4038// start-sanitize-vr4320
4039*vr4320:
4040// end-sanitize-vr4320
a83d7d87 4041// start-sanitize-cygnus
90ad43b2 4042*vr5400:
a83d7d87 4043// end-sanitize-cygnus
f2b30012
AC		 4044// start-sanitize-r5900
4045*r5900:
4046// end-sanitize-r5900
f2b30012
AC		 4047// start-sanitize-tx19
4048*tx19:
4049// end-sanitize-tx19
4050{
a94c5493 4051 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
055ee297 4052 SignalException(Trap, instruction_0);
f2b30012
AC		 4053}
4054
4055
4056000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
4057"tge r<RS>, r<RT>"
4058*mipsII:
4059*mipsIII:
4060*mipsIV:
1ee7d2b1 4061*vr4100:
23850e92 4062*vr5000:
f14397f0
GRK		 4063// start-sanitize-vr4xxx
4064*vr4121:
4065// end-sanitize-vr4xxx
15232df4
FCE		 4066// start-sanitize-vr4320
4067*vr4320:
4068// end-sanitize-vr4320
a83d7d87 4069// start-sanitize-cygnus
90ad43b2 4070*vr5400:
a83d7d87 4071// end-sanitize-cygnus
f2b30012
AC		 4072// start-sanitize-r5900
4073*r5900:
4074// end-sanitize-r5900
f2b30012
AC		 4075// start-sanitize-tx19
4076*tx19:
4077// end-sanitize-tx19
4078{
a94c5493 4079 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
055ee297 4080 SignalException(Trap, instruction_0);
f2b30012
AC		 4081}
4082
4083
4084000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
4085"tgei r<RS>, <IMMEDIATE>"
4086*mipsII:
4087*mipsIII:
4088*mipsIV:
1ee7d2b1 4089*vr4100:
23850e92 4090*vr5000:
f14397f0
GRK		 4091// start-sanitize-vr4xxx
4092*vr4121:
4093// end-sanitize-vr4xxx
15232df4
FCE		 4094// start-sanitize-vr4320
4095*vr4320:
4096// end-sanitize-vr4320
a83d7d87 4097// start-sanitize-cygnus
90ad43b2 4098*vr5400:
a83d7d87 4099// end-sanitize-cygnus
f2b30012
AC		 4100// start-sanitize-r5900
4101*r5900:
4102// end-sanitize-r5900
f2b30012
AC		 4103// start-sanitize-tx19
4104*tx19:
4105// end-sanitize-tx19
4106{
a94c5493 4107 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
055ee297 4108 SignalException(Trap, instruction_0);
f2b30012
AC		 4109}
4110
4111
4112000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
4113"tgeiu r<RS>, <IMMEDIATE>"
4114*mipsII:
4115*mipsIII:
4116*mipsIV:
1ee7d2b1 4117*vr4100:
23850e92 4118*vr5000:
f14397f0
GRK		 4119// start-sanitize-vr4xxx
4120*vr4121:
4121// end-sanitize-vr4xxx
15232df4
FCE		 4122// start-sanitize-vr4320
4123*vr4320:
4124// end-sanitize-vr4320
a83d7d87 4125// start-sanitize-cygnus
90ad43b2 4126*vr5400:
a83d7d87 4127// end-sanitize-cygnus
f2b30012
AC		 4128// start-sanitize-r5900
4129*r5900:
4130// end-sanitize-r5900
f2b30012
AC		 4131// start-sanitize-tx19
4132*tx19:
4133// end-sanitize-tx19
4134{
055ee297
AC		 4135 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
4136 SignalException(Trap, instruction_0);
f2b30012
AC		 4137}
4138
4139
4140000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
4141"tgeu r<RS>, r<RT>"
4142*mipsII:
4143*mipsIII:
4144*mipsIV:
1ee7d2b1 4145*vr4100:
23850e92 4146*vr5000:
f14397f0
GRK		 4147// start-sanitize-vr4xxx
4148*vr4121:
4149// end-sanitize-vr4xxx
15232df4
FCE		 4150// start-sanitize-vr4320
4151*vr4320:
4152// end-sanitize-vr4320
a83d7d87 4153// start-sanitize-cygnus
90ad43b2 4154*vr5400:
a83d7d87 4155// end-sanitize-cygnus
f2b30012
AC		 4156// start-sanitize-r5900
4157*r5900:
4158// end-sanitize-r5900
f2b30012
AC		 4159// start-sanitize-tx19
4160*tx19:
4161// end-sanitize-tx19
4162{
055ee297
AC		 4163 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
4164 SignalException(Trap, instruction_0);
f2b30012
AC		 4165}
4166
4167
4168000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
4169"tlt r<RS>, r<RT>"
4170*mipsII:
4171*mipsIII:
4172*mipsIV:
1ee7d2b1 4173*vr4100:
23850e92 4174*vr5000:
f14397f0
GRK		 4175// start-sanitize-vr4xxx
4176*vr4121:
4177// end-sanitize-vr4xxx
15232df4
FCE		 4178// start-sanitize-vr4320
4179*vr4320:
4180// end-sanitize-vr4320
a83d7d87 4181// start-sanitize-cygnus
90ad43b2 4182*vr5400:
a83d7d87 4183// end-sanitize-cygnus
f2b30012
AC		 4184// start-sanitize-r5900
4185*r5900:
4186// end-sanitize-r5900
f2b30012
AC		 4187// start-sanitize-tx19
4188*tx19:
4189// end-sanitize-tx19
4190{
a94c5493 4191 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
055ee297 4192 SignalException(Trap, instruction_0);
f2b30012
AC		 4193}
4194
4195
4196000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
4197"tlti r<RS>, <IMMEDIATE>"
4198*mipsII:
4199*mipsIII:
4200*mipsIV:
1ee7d2b1 4201*vr4100:
23850e92 4202*vr5000:
f14397f0
GRK		 4203// start-sanitize-vr4xxx
4204*vr4121:
4205// end-sanitize-vr4xxx
15232df4
FCE		 4206// start-sanitize-vr4320
4207*vr4320:
4208// end-sanitize-vr4320
a83d7d87 4209// start-sanitize-cygnus
90ad43b2 4210*vr5400:
a83d7d87 4211// end-sanitize-cygnus
f2b30012
AC		 4212// start-sanitize-r5900
4213*r5900:
4214// end-sanitize-r5900
f2b30012
AC		 4215// start-sanitize-tx19
4216*tx19:
4217// end-sanitize-tx19
4218{
a94c5493 4219 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
055ee297 4220 SignalException(Trap, instruction_0);
f2b30012
AC		 4221}
4222
4223
4224000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
4225"tltiu r<RS>, <IMMEDIATE>"
4226*mipsII:
4227*mipsIII:
4228*mipsIV:
1ee7d2b1 4229*vr4100:
23850e92 4230*vr5000:
f14397f0
GRK		 4231// start-sanitize-vr4xxx
4232*vr4121:
4233// end-sanitize-vr4xxx
15232df4
FCE		 4234// start-sanitize-vr4320
4235*vr4320:
4236// end-sanitize-vr4320
a83d7d87 4237// start-sanitize-cygnus
90ad43b2 4238*vr5400:
a83d7d87 4239// end-sanitize-cygnus
f2b30012
AC		 4240// start-sanitize-r5900
4241*r5900:
4242// end-sanitize-r5900
f2b30012
AC		 4243// start-sanitize-tx19
4244*tx19:
4245// end-sanitize-tx19
4246{
055ee297
AC		 4247 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
4248 SignalException(Trap, instruction_0);
f2b30012
AC		 4249}
4250
4251
4252000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
4253"tltu r<RS>, r<RT>"
4254*mipsII:
4255*mipsIII:
4256*mipsIV:
1ee7d2b1 4257*vr4100:
23850e92 4258*vr5000:
f14397f0
GRK		 4259// start-sanitize-vr4xxx
4260*vr4121:
4261// end-sanitize-vr4xxx
15232df4
FCE		 4262// start-sanitize-vr4320
4263*vr4320:
4264// end-sanitize-vr4320
a83d7d87 4265// start-sanitize-cygnus
90ad43b2 4266*vr5400:
a83d7d87 4267// end-sanitize-cygnus
f2b30012
AC		 4268// start-sanitize-r5900
4269*r5900:
4270// end-sanitize-r5900
f2b30012
AC		 4271// start-sanitize-tx19
4272*tx19:
4273// end-sanitize-tx19
4274{
055ee297
AC		 4275 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
4276 SignalException(Trap, instruction_0);
f2b30012
AC		 4277}
4278
4279
4280000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
4281"tne r<RS>, r<RT>"
4282*mipsII:
4283*mipsIII:
4284*mipsIV:
1ee7d2b1 4285*vr4100:
23850e92 4286*vr5000:
f14397f0
GRK		 4287// start-sanitize-vr4xxx
4288*vr4121:
4289// end-sanitize-vr4xxx
15232df4
FCE		 4290// start-sanitize-vr4320
4291*vr4320:
4292// end-sanitize-vr4320
a83d7d87 4293// start-sanitize-cygnus
90ad43b2 4294*vr5400:
a83d7d87 4295// end-sanitize-cygnus
f2b30012
AC		 4296// start-sanitize-r5900
4297*r5900:
4298// end-sanitize-r5900
f2b30012
AC		 4299// start-sanitize-tx19
4300*tx19:
4301// end-sanitize-tx19
4302{
a94c5493 4303 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
055ee297 4304 SignalException(Trap, instruction_0);
f2b30012
AC		 4305}
4306
4307
4308000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
4309"tne r<RS>, <IMMEDIATE>"
4310*mipsII:
4311*mipsIII:
4312*mipsIV:
1ee7d2b1 4313*vr4100:
23850e92 4314*vr5000:
f14397f0
GRK		 4315// start-sanitize-vr4xxx
4316*vr4121:
4317// end-sanitize-vr4xxx
15232df4
FCE		 4318// start-sanitize-vr4320
4319*vr4320:
4320// end-sanitize-vr4320
a83d7d87 4321// start-sanitize-cygnus
90ad43b2 4322*vr5400:
a83d7d87 4323// end-sanitize-cygnus
f2b30012
AC		 4324// start-sanitize-r5900
4325*r5900:
4326// end-sanitize-r5900
f2b30012
AC		 4327// start-sanitize-tx19
4328*tx19:
4329// end-sanitize-tx19
4330{
a94c5493 4331 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
055ee297 4332 SignalException(Trap, instruction_0);
f2b30012
AC		 4333}
4334
4335
c0a4c3ba
AC		 4336:function:::void:do_xor:int rs, int rt, int rd
4337{
f3bdd368 4338 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
c0a4c3ba 4339 GPR[rd] = GPR[rs] ^ GPR[rt];
f3bdd368 4340 TRACE_ALU_RESULT (GPR[rd]);
c0a4c3ba
AC		 4341}
4342
f2b30012
AC		 4343000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
4344"xor r<RD>, r<RS>, r<RT>"
23850e92 4345*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 4346*vr4100:
23850e92 4347*vr5000:
f14397f0
GRK		 4348// start-sanitize-vr4xxx
4349*vr4121:
4350// end-sanitize-vr4xxx
15232df4
FCE		 4351// start-sanitize-vr4320
4352*vr4320:
4353// end-sanitize-vr4320
a83d7d87 4354// start-sanitize-cygnus
90ad43b2 4355*vr5400:
a83d7d87 4356// end-sanitize-cygnus
f2b30012
AC		 4357// start-sanitize-r5900
4358*r5900:
4359// end-sanitize-r5900
4360*r3900:
4361// start-sanitize-tx19
4362*tx19:
4363// end-sanitize-tx19
4364{
c0a4c3ba 4365 do_xor (SD_, RS, RT, RD);
f2b30012
AC		 4366}
4367
4368
c0a4c3ba
AC		 4369:function:::void:do_xori:int rs, int rt, unsigned16 immediate
4370{
f3bdd368 4371 TRACE_ALU_INPUT2 (GPR[rs], immediate);
c0a4c3ba 4372 GPR[rt] = GPR[rs] ^ immediate;
f3bdd368 4373 TRACE_ALU_RESULT (GPR[rt]);
c0a4c3ba
AC		 4374}
4375
f2b30012 4376001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
055ee297 4377"xori r<RT>, r<RS>, <IMMEDIATE>"
23850e92 4378*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 4379*vr4100:
23850e92 4380*vr5000:
f14397f0
GRK		 4381// start-sanitize-vr4xxx
4382*vr4121:
4383// end-sanitize-vr4xxx
15232df4
FCE		 4384// start-sanitize-vr4320
4385*vr4320:
4386// end-sanitize-vr4320
a83d7d87 4387// start-sanitize-cygnus
90ad43b2 4388*vr5400:
a83d7d87 4389// end-sanitize-cygnus
f2b30012
AC		 4390// start-sanitize-r5900
4391*r5900:
4392// end-sanitize-r5900
4393*r3900:
4394// start-sanitize-tx19
4395*tx19:
4396// end-sanitize-tx19
4397{
c0a4c3ba 4398 do_xori (SD_, RS, RT, IMMEDIATE);
f2b30012
AC		 4399}
4400
4401\f
4402//
4403// MIPS Architecture:
4404//
4405// FPU Instruction Set (COP1 & COP1X)
4406//
4407
4408
89d09738 4409:%s::::FMT:int fmt
055ee297
AC		 4410{
4411 switch (fmt)
4412 {
4413 case fmt_single: return "s";
4414 case fmt_double: return "d";
4415 case fmt_word: return "w";
4416 case fmt_long: return "l";
4417 default: return "?";
4418 }
4419}
4420
030843d7
AC		 4421:%s::::X:int x
4422{
4423 switch (x)
4424 {
4425 case 0: return "f";
4426 case 1: return "t";
4427 default: return "?";
4428 }
4429}
4430
89d09738 4431:%s::::TF:int tf
055ee297
AC		 4432{
4433 if (tf)
4434 return "t";
4435 else
4436 return "f";
4437}
4438
89d09738 4439:%s::::ND:int nd
055ee297
AC		 4440{
4441 if (nd)
4442 return "l";
4443 else
4444 return "";
4445}
4446
89d09738 4447:%s::::COND:int cond
055ee297
AC		 4448{
4449 switch (cond)
4450 {
4451 case 00: return "f";
4452 case 01: return "un";
4453 case 02: return "eq";
4454 case 03: return "ueq";
4455 case 04: return "olt";
4456 case 05: return "ult";
4457 case 06: return "ole";
4458 case 07: return "ule";
4459 case 010: return "sf";
4460 case 011: return "ngle";
4461 case 012: return "seq";
4462 case 013: return "ngl";
4463 case 014: return "lt";
4464 case 015: return "nge";
4465 case 016: return "le";
4466 case 017: return "ngt";
4467 default: return "?";
4468 }
4469}
4470
4471
f2b30012
AC		 4472010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
4473"abs.%s<FMT> f<FD>, f<FS>"
23850e92 4474*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 4475*vr4100:
23850e92 4476*vr5000:
f14397f0
GRK		 4477// start-sanitize-vr4xxx
4478*vr4121:
4479// end-sanitize-vr4xxx
15232df4
FCE		 4480// start-sanitize-vr4320
4481*vr4320:
4482// end-sanitize-vr4320
a83d7d87 4483// start-sanitize-cygnus
90ad43b2 4484*vr5400:
a83d7d87 4485// end-sanitize-cygnus
f2b30012
AC		 4486*r3900:
4487// start-sanitize-tx19
4488*tx19:
4489// end-sanitize-tx19
4490{
4491 unsigned32 instruction = instruction_0;
055ee297
AC		 4492 int destreg = ((instruction >> 6) & 0x0000001F);
4493 int fs = ((instruction >> 11) & 0x0000001F);
4494 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4495 {
4496 if ((format != fmt_single) && (format != fmt_double))
4497 SignalException(ReservedInstruction,instruction);
4498 else
4499 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
4500 }
4501}
4502
4503
055ee297 4504
a48e8c8d 4505010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
f2b30012 4506"add.%s<FMT> f<FD>, f<FS>, f<FT>"
23850e92 4507*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 4508*vr4100:
23850e92 4509*vr5000:
f14397f0
GRK		 4510// start-sanitize-vr4xxx
4511*vr4121:
4512// end-sanitize-vr4xxx
15232df4
FCE		 4513// start-sanitize-vr4320
4514*vr4320:
4515// end-sanitize-vr4320
a83d7d87 4516// start-sanitize-cygnus
90ad43b2 4517*vr5400:
a83d7d87 4518// end-sanitize-cygnus
f2b30012
AC		 4519*r3900:
4520// start-sanitize-tx19
4521*tx19:
4522// end-sanitize-tx19
4523{
4524 unsigned32 instruction = instruction_0;
055ee297
AC		 4525 int destreg = ((instruction >> 6) & 0x0000001F);
4526 int fs = ((instruction >> 11) & 0x0000001F);
4527 int ft = ((instruction >> 16) & 0x0000001F);
4528 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4529 {
4530 if ((format != fmt_single) && (format != fmt_double))
055ee297 4531 SignalException(ReservedInstruction, instruction);
f2b30012
AC		 4532 else
4533 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
4534 }
4535}
4536
4537
23850e92 4538
f2b30012
AC		 4539// BC1F
4540// BC1FL
4541// BC1T
4542// BC1TL
23850e92 4543
82aeada7 4544010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
23850e92
JL		 4545"bc1%s<TF>%s<ND> <OFFSET>"
4546*mipsI,mipsII,mipsIII:
1ee7d2b1 4547*vr4100:
f14397f0
GRK		 4548// start-sanitize-vr4xxx
4549*vr4121:
4550// end-sanitize-vr4xxx
4551// start-sanitize-vr4320
4552*vr4320:
4553// end-sanitize-vr4320
23850e92
JL		 4554// start-sanitize-r5900
4555*r5900:
4556// end-sanitize-r5900
4557{
a83d7d87 4558 check_branch_bug ();
a48e8c8d 4559 TRACE_BRANCH_INPUT (PREVCOC1());
23850e92
JL		 4560 if (PREVCOC1() == TF)
4561 {
a48e8c8d
AC		 4562 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4563 TRACE_BRANCH_RESULT (dest);
a83d7d87 4564 mark_branch_bug (dest);
a48e8c8d 4565 DELAY_SLOT (dest);
23850e92
JL		 4566 }
4567 else if (ND)
4568 {
a48e8c8d 4569 TRACE_BRANCH_RESULT (0);
23850e92
JL		 4570 NULLIFY_NEXT_INSTRUCTION ();
4571 }
a48e8c8d
AC		 4572 else
4573 {
4574 TRACE_BRANCH_RESULT (NIA);
4575 }
23850e92
JL		 4576}
4577
82aeada7 4578010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
055ee297
AC		 4579"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4580"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
f2b30012 4581*mipsIV:
23850e92 4582*vr5000:
a83d7d87 4583// start-sanitize-cygnus
90ad43b2 4584*vr5400:
a83d7d87 4585// end-sanitize-cygnus
f2b30012
AC		 4586*r3900:
4587// start-sanitize-tx19
4588*tx19:
4589// end-sanitize-tx19
4590{
a83d7d87 4591 check_branch_bug ();
23850e92
JL		 4592 if (GETFCC(CC) == TF)
4593 {
a83d7d87
AC		 4594 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4595 mark_branch_bug (dest);
4596 DELAY_SLOT (dest);
23850e92
JL		 4597 }
4598 else if (ND)
4599 {
4600 NULLIFY_NEXT_INSTRUCTION ();
f2b30012 4601 }
f2b30012
AC		 4602}
4603
4604
23850e92 4605
702968c5
FCE		 4606
4607
4608
23850e92
JL		 4609// C.EQ.S
4610// C.EQ.D
4611// ...
4612
4613:function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
4614{
4615 if ((fmt != fmt_single) && (fmt != fmt_double))
4616 SignalException (ReservedInstruction, insn);
4617 else
4618 {
4619 int less;
4620 int equal;
4621 int unordered;
4622 int condition;
4623 unsigned64 ofs = ValueFPR (fs, fmt);
4624 unsigned64 oft = ValueFPR (ft, fmt);
4625 if (NaN (ofs, fmt) || NaN (oft, fmt))
4626 {
4627 if (FCSR & FP_ENABLE (IO))
4628 {
4629 FCSR |= FP_CAUSE (IO);
4630 SignalExceptionFPE ();
4631 }
4632 less = 0;
4633 equal = 0;
4634 unordered = 1;
4635 }
4636 else
4637 {
4638 less = Less (ofs, oft, fmt);
4639 equal = Equal (ofs, oft, fmt);
4640 unordered = 0;
4641 }
4642 condition = (((cond & (1 << 2)) && less)
4643 || ((cond & (1 << 1)) && equal)
4644 || ((cond & (1 << 0)) && unordered));
4645 SETFCC (cc, condition);
4646 }
4647}
4648
f14397f0 4649010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
a83d7d87 4650"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
f14397f0 4651*mipsI,mipsII,mipsIII:
23850e92
JL		 4652{
4653 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4654}
4655
f14397f0 4656010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
f2b30012
AC		 4657"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4658"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
f2b30012 4659*mipsIV:
1ee7d2b1 4660*vr4100:
23850e92 4661*vr5000:
f14397f0
GRK		 4662// start-sanitize-vr4xxx
4663*vr4121:
4664// end-sanitize-vr4xxx
15232df4
FCE		 4665// start-sanitize-vr4320
4666*vr4320:
4667// end-sanitize-vr4320
a83d7d87 4668// start-sanitize-cygnus
90ad43b2 4669*vr5400:
a83d7d87 4670// end-sanitize-cygnus
f2b30012
AC		 4671*r3900:
4672// start-sanitize-tx19
4673*tx19:
4674// end-sanitize-tx19
4675{
23850e92 4676 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
f2b30012
AC		 4677}
4678
4679
4680010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4681"ceil.l.%s<FMT> f<FD>, f<FS>"
4682*mipsIII:
4683*mipsIV:
1ee7d2b1 4684*vr4100:
23850e92 4685*vr5000:
f14397f0
GRK		 4686// start-sanitize-vr4xxx
4687*vr4121:
4688// end-sanitize-vr4xxx
15232df4
FCE		 4689// start-sanitize-vr4320
4690*vr4320:
4691// end-sanitize-vr4320
a83d7d87 4692// start-sanitize-cygnus
90ad43b2 4693*vr5400:
a83d7d87 4694// end-sanitize-cygnus
f2b30012
AC		 4695// start-sanitize-r5900
4696*r5900:
4697// end-sanitize-r5900
4698*r3900:
4699// start-sanitize-tx19
4700*tx19:
4701// end-sanitize-tx19
4702{
4703 unsigned32 instruction = instruction_0;
055ee297
AC		 4704 int destreg = ((instruction >> 6) & 0x0000001F);
4705 int fs = ((instruction >> 11) & 0x0000001F);
4706 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4707 {
4708 if ((format != fmt_single) && (format != fmt_double))
4709 SignalException(ReservedInstruction,instruction);
4710 else
4711 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4712 }
4713}
4714
4715
4716010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4717*mipsII:
4718*mipsIII:
4719*mipsIV:
1ee7d2b1 4720*vr4100:
23850e92 4721*vr5000:
f14397f0
GRK		 4722// start-sanitize-vr4xxx
4723*vr4121:
4724// end-sanitize-vr4xxx
15232df4
FCE		 4725// start-sanitize-vr4320
4726*vr4320:
4727// end-sanitize-vr4320
a83d7d87 4728// start-sanitize-cygnus
90ad43b2 4729*vr5400:
a83d7d87 4730// end-sanitize-cygnus
f2b30012
AC		 4731// start-sanitize-r5900
4732*r5900:
4733// end-sanitize-r5900
4734*r3900:
4735// start-sanitize-tx19
4736*tx19:
4737// end-sanitize-tx19
4738{
4739 unsigned32 instruction = instruction_0;
055ee297
AC		 4740 int destreg = ((instruction >> 6) & 0x0000001F);
4741 int fs = ((instruction >> 11) & 0x0000001F);
4742 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4743 {
4744 if ((format != fmt_single) && (format != fmt_double))
4745 SignalException(ReservedInstruction,instruction);
4746 else
4747 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4748 }
4749}
4750
4751
4752// CFC1
4753// CTC1
030843d7
AC		 4754010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4755"c%s<X>c1 r<RT>, f<FS>"
f2b30012
AC		 4756*mipsI:
4757*mipsII:
4758*mipsIII:
030843d7
AC		 4759{
4760 if (X)
4761 {
4762 if (FS == 0)
4763 PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4764 else if (FS == 31)
4765 PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4766 /* else NOP */
4767 PENDING_FILL(COCIDX,0); /* special case */
4768 }
4769 else
4770 { /* control from */
4771 if (FS == 0)
4772 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4773 else if (FS == 31)
4774 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4775 /* else NOP */
4776 }
4777}
4778010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4779"c%s<X>c1 r<RT>, f<FS>"
f2b30012 4780*mipsIV:
1ee7d2b1 4781*vr4100:
23850e92 4782*vr5000:
f14397f0
GRK		 4783// start-sanitize-vr4xxx
4784*vr4121:
4785// end-sanitize-vr4xxx
15232df4
FCE		 4786// start-sanitize-vr4320
4787*vr4320:
4788// end-sanitize-vr4320
a83d7d87 4789// start-sanitize-cygnus
90ad43b2 4790*vr5400:
a83d7d87 4791// end-sanitize-cygnus
f2b30012
AC		 4792*r3900:
4793// start-sanitize-tx19
4794*tx19:
4795// end-sanitize-tx19
4796{
030843d7
AC		 4797 if (X)
4798 {
f89c0689
AC		 4799 /* control to */
4800 TRACE_ALU_INPUT1 (GPR[RT]);
030843d7 4801 if (FS == 0)
f89c0689
AC		 4802 {
4803 FCR0 = VL4_8(GPR[RT]);
4804 TRACE_ALU_RESULT (FCR0);
4805 }
030843d7 4806 else if (FS == 31)
f89c0689
AC		 4807 {
4808 FCR31 = VL4_8(GPR[RT]);
4809 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4810 TRACE_ALU_RESULT (FCR31);
4811 }
4812 else
4813 {
4814 TRACE_ALU_RESULT0 ();
4815 }
030843d7 4816 /* else NOP */
030843d7
AC		 4817 }
4818 else
4819 { /* control from */
4820 if (FS == 0)
f89c0689
AC		 4821 {
4822 TRACE_ALU_INPUT1 (FCR0);
4823 GPR[RT] = SIGNEXTEND (FCR0, 32);
4824 }
030843d7 4825 else if (FS == 31)
f89c0689
AC		 4826 {
4827 TRACE_ALU_INPUT1 (FCR31);
4828 GPR[RT] = SIGNEXTEND (FCR31, 32);
4829 }
4830 TRACE_ALU_RESULT (GPR[RT]);
030843d7 4831 /* else NOP */
f2b30012 4832 }
f2b30012
AC		 4833}
4834
4835
4836//
4837// FIXME: Does not correctly differentiate between mips*
4838//
4839010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4840"cvt.d.%s<FMT> f<FD>, f<FS>"
23850e92 4841*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 4842*vr4100:
23850e92 4843*vr5000:
f14397f0
GRK		 4844// start-sanitize-vr4xxx
4845*vr4121:
4846// end-sanitize-vr4xxx
15232df4
FCE		 4847// start-sanitize-vr4320
4848*vr4320:
4849// end-sanitize-vr4320
a83d7d87 4850// start-sanitize-cygnus
90ad43b2 4851*vr5400:
a83d7d87 4852// end-sanitize-cygnus
f2b30012
AC		 4853*r3900:
4854// start-sanitize-tx19
4855*tx19:
4856// end-sanitize-tx19
4857{
4858 unsigned32 instruction = instruction_0;
055ee297
AC		 4859 int destreg = ((instruction >> 6) & 0x0000001F);
4860 int fs = ((instruction >> 11) & 0x0000001F);
4861 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4862 {
4863 if ((format == fmt_double) | 0)
4864 SignalException(ReservedInstruction,instruction);
4865 else
4866 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4867 }
4868}
4869
4870
4871010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4872"cvt.l.%s<FMT> f<FD>, f<FS>"
4873*mipsIII:
4874*mipsIV:
1ee7d2b1 4875*vr4100:
23850e92 4876*vr5000:
f14397f0
GRK		 4877// start-sanitize-vr4xxx
4878*vr4121:
4879// end-sanitize-vr4xxx
15232df4
FCE		 4880// start-sanitize-vr4320
4881*vr4320:
4882// end-sanitize-vr4320
a83d7d87 4883// start-sanitize-cygnus
90ad43b2 4884*vr5400:
a83d7d87 4885// end-sanitize-cygnus
f2b30012
AC		 4886*r3900:
4887// start-sanitize-tx19
4888*tx19:
4889// end-sanitize-tx19
4890{
4891 unsigned32 instruction = instruction_0;
055ee297
AC		 4892 int destreg = ((instruction >> 6) & 0x0000001F);
4893 int fs = ((instruction >> 11) & 0x0000001F);
4894 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4895 {
4896 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4897 SignalException(ReservedInstruction,instruction);
4898 else
4899 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4900 }
4901}
4902
4903
4904//
4905// FIXME: Does not correctly differentiate between mips*
4906//
4907010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4908"cvt.s.%s<FMT> f<FD>, f<FS>"
23850e92 4909*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 4910*vr4100:
23850e92 4911*vr5000:
f14397f0
GRK		 4912// start-sanitize-vr4xxx
4913*vr4121:
4914// end-sanitize-vr4xxx
15232df4
FCE		 4915// start-sanitize-vr4320
4916*vr4320:
4917// end-sanitize-vr4320
a83d7d87 4918// start-sanitize-cygnus
90ad43b2 4919*vr5400:
a83d7d87 4920// end-sanitize-cygnus
f2b30012
AC		 4921*r3900:
4922// start-sanitize-tx19
4923*tx19:
4924// end-sanitize-tx19
4925{
4926 unsigned32 instruction = instruction_0;
055ee297
AC		 4927 int destreg = ((instruction >> 6) & 0x0000001F);
4928 int fs = ((instruction >> 11) & 0x0000001F);
4929 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4930 {
4931 if ((format == fmt_single) | 0)
4932 SignalException(ReservedInstruction,instruction);
4933 else
4934 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4935 }
4936}
4937
4938
4939010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4940"cvt.w.%s<FMT> f<FD>, f<FS>"
23850e92 4941*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 4942*vr4100:
23850e92 4943*vr5000:
f14397f0
GRK		 4944// start-sanitize-vr4xxx
4945*vr4121:
4946// end-sanitize-vr4xxx
15232df4
FCE		 4947// start-sanitize-vr4320
4948*vr4320:
4949// end-sanitize-vr4320
a83d7d87 4950// start-sanitize-cygnus
90ad43b2 4951*vr5400:
a83d7d87 4952// end-sanitize-cygnus
f2b30012
AC		 4953*r3900:
4954// start-sanitize-tx19
4955*tx19:
4956// end-sanitize-tx19
4957{
4958 unsigned32 instruction = instruction_0;
055ee297
AC		 4959 int destreg = ((instruction >> 6) & 0x0000001F);
4960 int fs = ((instruction >> 11) & 0x0000001F);
4961 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4962 {
4963 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4964 SignalException(ReservedInstruction,instruction);
4965 else
4966 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4967 }
4968}
4969
4970
4971010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4972"div.%s<FMT> f<FD>, f<FS>, f<FT>"
23850e92 4973*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 4974*vr4100:
23850e92 4975*vr5000:
f14397f0
GRK		 4976// start-sanitize-vr4xxx
4977*vr4121:
4978// end-sanitize-vr4xxx
15232df4
FCE		 4979// start-sanitize-vr4320
4980*vr4320:
4981// end-sanitize-vr4320
a83d7d87 4982// start-sanitize-cygnus
90ad43b2 4983*vr5400:
a83d7d87 4984// end-sanitize-cygnus
f2b30012
AC		 4985*r3900:
4986// start-sanitize-tx19
4987*tx19:
4988// end-sanitize-tx19
4989{
4990 unsigned32 instruction = instruction_0;
055ee297
AC		 4991 int destreg = ((instruction >> 6) & 0x0000001F);
4992 int fs = ((instruction >> 11) & 0x0000001F);
4993 int ft = ((instruction >> 16) & 0x0000001F);
4994 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4995 {
4996 if ((format != fmt_single) && (format != fmt_double))
4997 SignalException(ReservedInstruction,instruction);
4998 else
4999 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
5000 }
5001}
5002
5003
5004// DMFC1
5005// DMTC1
030843d7
AC		 5006010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
5007"dm%s<X>c1 r<RT>, f<FS>"
f2b30012 5008*mipsIII:
030843d7
AC		 5009{
5010 if (X)
5011 {
5012 if (SizeFGR() == 64)
5013 PENDING_FILL((FS + FGRIDX),GPR[RT]);
5014 else if ((FS & 0x1) == 0)
5015 {
5016 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
5017 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
5018 }
5019 }
5020 else
5021 {
5022 if (SizeFGR() == 64)
5023 PENDING_FILL(RT,FGR[FS]);
5024 else if ((FS & 0x1) == 0)
5025 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
5026 else
5027 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
5028 }
5029}
5030010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
5031"dm%s<X>c1 r<RT>, f<FS>"
f2b30012 5032*mipsIV:
1ee7d2b1 5033*vr4100:
23850e92 5034*vr5000:
f14397f0
GRK		 5035// start-sanitize-vr4xxx
5036*vr4121:
5037// end-sanitize-vr4xxx
15232df4
FCE		 5038// start-sanitize-vr4320
5039*vr4320:
5040// end-sanitize-vr4320
a83d7d87 5041// start-sanitize-cygnus
90ad43b2 5042*vr5400:
a83d7d87 5043// end-sanitize-cygnus
f2b30012
AC		 5044// start-sanitize-r5900
5045*r5900:
5046// end-sanitize-r5900
5047*r3900:
5048// start-sanitize-tx19
5049*tx19:
5050// end-sanitize-tx19
5051{
030843d7
AC		 5052 if (X)
5053 {
5054 if (SizeFGR() == 64)
23850e92 5055 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
030843d7 5056 else if ((FS & 0x1) == 0)
23850e92 5057 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
f2b30012 5058 }
030843d7
AC		 5059 else
5060 {
5061 if (SizeFGR() == 64)
5062 GPR[RT] = FGR[FS];
5063 else if ((FS & 0x1) == 0)
5064 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
5065 else
5066 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
5067 }
f2b30012
AC		 5068}
5069
5070
5071010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
5072"floor.l.%s<FMT> f<FD>, f<FS>"
5073*mipsIII:
5074*mipsIV:
1ee7d2b1 5075*vr4100:
23850e92 5076*vr5000:
f14397f0
GRK		 5077// start-sanitize-vr4xxx
5078*vr4121:
5079// end-sanitize-vr4xxx
15232df4
FCE		 5080// start-sanitize-vr4320
5081*vr4320:
5082// end-sanitize-vr4320
a83d7d87 5083// start-sanitize-cygnus
90ad43b2 5084*vr5400:
a83d7d87 5085// end-sanitize-cygnus
f2b30012
AC		 5086// start-sanitize-r5900
5087*r5900:
5088// end-sanitize-r5900
5089*r3900:
5090// start-sanitize-tx19
5091*tx19:
5092// end-sanitize-tx19
5093{
5094 unsigned32 instruction = instruction_0;
055ee297
AC		 5095 int destreg = ((instruction >> 6) & 0x0000001F);
5096 int fs = ((instruction >> 11) & 0x0000001F);
5097 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5098 {
5099 if ((format != fmt_single) && (format != fmt_double))
5100 SignalException(ReservedInstruction,instruction);
5101 else
5102 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
5103 }
5104}
5105
5106
5107010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
5108"floor.w.%s<FMT> f<FD>, f<FS>"
5109*mipsII:
5110*mipsIII:
5111*mipsIV:
1ee7d2b1 5112*vr4100:
23850e92 5113*vr5000:
f14397f0
GRK		 5114// start-sanitize-vr4xxx
5115*vr4121:
5116// end-sanitize-vr4xxx
15232df4
FCE		 5117// start-sanitize-vr4320
5118*vr4320:
5119// end-sanitize-vr4320
a83d7d87 5120// start-sanitize-cygnus
90ad43b2 5121*vr5400:
a83d7d87 5122// end-sanitize-cygnus
f2b30012
AC		 5123// start-sanitize-r5900
5124*r5900:
5125// end-sanitize-r5900
5126*r3900:
5127// start-sanitize-tx19
5128*tx19:
5129// end-sanitize-tx19
5130{
5131 unsigned32 instruction = instruction_0;
055ee297
AC		 5132 int destreg = ((instruction >> 6) & 0x0000001F);
5133 int fs = ((instruction >> 11) & 0x0000001F);
5134 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5135 {
5136 if ((format != fmt_single) && (format != fmt_double))
5137 SignalException(ReservedInstruction,instruction);
5138 else
5139 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
5140 }
5141}
5142
5143
030843d7 5144110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
a94c5493 5145"ldc1 f<FT>, <OFFSET>(r<BASE>)"
030843d7
AC		 5146*mipsII:
5147*mipsIII:
5148*mipsIV:
1ee7d2b1 5149*vr4100:
23850e92 5150*vr5000:
f14397f0
GRK		 5151// start-sanitize-vr4xxx
5152*vr4121:
5153// end-sanitize-vr4xxx
15232df4
FCE		 5154// start-sanitize-vr4320
5155*vr4320:
5156// end-sanitize-vr4320
a83d7d87 5157// start-sanitize-cygnus
030843d7 5158*vr5400:
a83d7d87 5159// end-sanitize-cygnus
030843d7
AC		 5160*r3900:
5161// start-sanitize-tx19
5162*tx19:
5163// end-sanitize-tx19
5164{
ebcfd86a 5165 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
030843d7 5166}
f2b30012
AC		 5167
5168
5169010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
5170"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
5171*mipsIV:
23850e92 5172*vr5000:
15232df4
FCE		 5173// start-sanitize-vr4320
5174*vr4320:
5175// end-sanitize-vr4320
a83d7d87 5176// start-sanitize-cygnus
90ad43b2 5177*vr5400:
a83d7d87 5178// end-sanitize-cygnus
f2b30012 5179{
ebcfd86a 5180 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
f2b30012
AC		 5181}
5182
5183
f2b30012 5184
030843d7 5185110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
23850e92
JL		 5186"lwc1 f<FT>, <OFFSET>(r<BASE>)"
5187*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 5188*vr4100:
23850e92 5189*vr5000:
f14397f0
GRK		 5190// start-sanitize-vr4xxx
5191*vr4121:
5192// end-sanitize-vr4xxx
15232df4
FCE		 5193// start-sanitize-vr4320
5194*vr4320:
5195// end-sanitize-vr4320
a83d7d87 5196// start-sanitize-cygnus
90ad43b2 5197*vr5400:
a83d7d87 5198// end-sanitize-cygnus
f2b30012
AC		 5199// start-sanitize-r5900
5200*r5900:
5201// end-sanitize-r5900
030843d7
AC		 5202*r3900:
5203// start-sanitize-tx19
5204*tx19:
5205// end-sanitize-tx19
5206{
ebcfd86a 5207 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
030843d7
AC		 5208}
5209
5210
5211010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
5212"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
5213*mipsIV:
23850e92 5214*vr5000:
15232df4
FCE		 5215// start-sanitize-vr4320
5216*vr4320:
5217// end-sanitize-vr4320
a83d7d87 5218// start-sanitize-cygnus
030843d7 5219*vr5400:
a83d7d87 5220// end-sanitize-cygnus
f2b30012 5221{
ebcfd86a 5222 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
f2b30012
AC		 5223}
5224
5225
5226
5227//
5228// FIXME: Not correct for mips*
5229//
a48e8c8d 5230010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
f2b30012
AC		 5231"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
5232*mipsIV:
23850e92 5233*vr5000:
15232df4
FCE		 5234// start-sanitize-vr4320
5235*vr4320:
5236// end-sanitize-vr4320
a83d7d87 5237// start-sanitize-cygnus
90ad43b2 5238*vr5400:
a83d7d87 5239// end-sanitize-cygnus
f2b30012
AC		 5240{
5241 unsigned32 instruction = instruction_0;
055ee297
AC		 5242 int destreg = ((instruction >> 6) & 0x0000001F);
5243 int fs = ((instruction >> 11) & 0x0000001F);
5244 int ft = ((instruction >> 16) & 0x0000001F);
5245 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 5246 {
5247 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
5248 }
5249}
5250
5251
a48e8c8d 5252010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
f2b30012
AC		 5253"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
5254*mipsIV:
23850e92 5255*vr5000:
15232df4
FCE		 5256// start-sanitize-vr4320
5257*vr4320:
5258// end-sanitize-vr4320
a83d7d87 5259// start-sanitize-cygnus
90ad43b2 5260*vr5400:
a83d7d87 5261// end-sanitize-cygnus
f2b30012
AC		 5262{
5263 unsigned32 instruction = instruction_0;
055ee297
AC		 5264 int destreg = ((instruction >> 6) & 0x0000001F);
5265 int fs = ((instruction >> 11) & 0x0000001F);
5266 int ft = ((instruction >> 16) & 0x0000001F);
5267 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 5268 {
5269 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
5270 }
5271}
5272
5273
5274// MFC1
030843d7 5275// MTC1
f2b30012 5276010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
030843d7 5277"m%s<X>c1 r<RT>, f<FS>"
f2b30012
AC		 5278*mipsI:
5279*mipsII:
5280*mipsIII:
030843d7
AC		 5281{
5282 if (X)
5283 { /*MTC1*/
5284 if (SizeFGR() == 64)
5285 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
5286 else
5287 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
5288 }
5289 else /*MFC1*/
5290 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
5291}
5292010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
5293"m%s<X>c1 r<RT>, f<FS>"
f2b30012 5294*mipsIV:
1ee7d2b1 5295*vr4100:
23850e92 5296*vr5000:
f14397f0
GRK		 5297// start-sanitize-vr4xxx
5298*vr4121:
5299// end-sanitize-vr4xxx
15232df4
FCE		 5300// start-sanitize-vr4320
5301*vr4320:
5302// end-sanitize-vr4320
a83d7d87 5303// start-sanitize-cygnus
90ad43b2 5304*vr5400:
a83d7d87 5305// end-sanitize-cygnus
f2b30012
AC		 5306*r3900:
5307// start-sanitize-tx19
5308*tx19:
5309// end-sanitize-tx19
5310{
f14397f0 5311 int fs = FS;
030843d7 5312 if (X)
23850e92
JL		 5313 /*MTC1*/
5314 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
030843d7
AC		 5315 else /*MFC1*/
5316 GPR[RT] = SIGNEXTEND(FGR[FS],32);
f2b30012
AC		 5317}
5318
5319
5320010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
5321"mov.%s<FMT> f<FD>, f<FS>"
23850e92 5322*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 5323*vr4100:
23850e92 5324*vr5000:
f14397f0
GRK		 5325// start-sanitize-vr4xxx
5326*vr4121:
5327// end-sanitize-vr4xxx
15232df4
FCE		 5328// start-sanitize-vr4320
5329*vr4320:
5330// end-sanitize-vr4320
a83d7d87 5331// start-sanitize-cygnus
90ad43b2 5332*vr5400:
a83d7d87 5333// end-sanitize-cygnus
f2b30012
AC		 5334*r3900:
5335// start-sanitize-tx19
5336*tx19:
5337// end-sanitize-tx19
5338{
5339 unsigned32 instruction = instruction_0;
055ee297
AC		 5340 int destreg = ((instruction >> 6) & 0x0000001F);
5341 int fs = ((instruction >> 11) & 0x0000001F);
5342 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5343 {
5344 StoreFPR(destreg,format,ValueFPR(fs,format));
5345 }
5346}
5347
5348
5349// MOVF
5350000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
055ee297 5351"mov%s<TF> r<RD>, r<RS>, <CC>"
f2b30012 5352*mipsIV:
23850e92 5353*vr5000:
15232df4
FCE		 5354// start-sanitize-vr4320
5355*vr4320:
5356// end-sanitize-vr4320
a83d7d87 5357// start-sanitize-cygnus
90ad43b2 5358*vr5400:
a83d7d87 5359// end-sanitize-cygnus
f2b30012
AC		 5360// start-sanitize-r5900
5361*r5900:
5362// end-sanitize-r5900
5363{
055ee297
AC		 5364 if (GETFCC(CC) == TF)
5365 GPR[RD] = GPR[RS];
f2b30012
AC		 5366}
5367
5368
5369// MOVF.fmt
5370010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
055ee297 5371"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
f2b30012 5372*mipsIV:
23850e92 5373*vr5000:
15232df4
FCE		 5374// start-sanitize-vr4320
5375*vr4320:
5376// end-sanitize-vr4320
a83d7d87 5377// start-sanitize-cygnus
90ad43b2 5378*vr5400:
a83d7d87 5379// end-sanitize-cygnus
f2b30012
AC		 5380// start-sanitize-r5900
5381*r5900:
5382// end-sanitize-r5900
5383{
5384 unsigned32 instruction = instruction_0;
055ee297 5385 int format = ((instruction >> 21) & 0x00000007);
f2b30012 5386 {
055ee297
AC		 5387 if (GETFCC(CC) == TF)
5388 StoreFPR (FD, format, ValueFPR (FS, format));
f2b30012 5389 else
055ee297 5390 StoreFPR (FD, format, ValueFPR (FD, format));
f2b30012
AC		 5391 }
5392}
5393
5394
5395010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
5396*mipsIV:
23850e92 5397*vr5000:
15232df4
FCE		 5398// start-sanitize-vr4320
5399*vr4320:
5400// end-sanitize-vr4320
a83d7d87 5401// start-sanitize-cygnus
90ad43b2 5402*vr5400:
a83d7d87 5403// end-sanitize-cygnus
f2b30012
AC		 5404// start-sanitize-r5900
5405*r5900:
5406// end-sanitize-r5900
5407{
5408 unsigned32 instruction = instruction_0;
055ee297
AC		 5409 int destreg = ((instruction >> 6) & 0x0000001F);
5410 int fs = ((instruction >> 11) & 0x0000001F);
5411 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5412 {
5413 StoreFPR(destreg,format,ValueFPR(fs,format));
5414 }
5415}
5416
5417
5418// MOVT see MOVtf
5419
5420
5421// MOVT.fmt see MOVtf.fmt
5422
5423
5424
5425010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
5426"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
5427*mipsIV:
23850e92 5428*vr5000:
15232df4
FCE		 5429// start-sanitize-vr4320
5430*vr4320:
5431// end-sanitize-vr4320
a83d7d87 5432// start-sanitize-cygnus
90ad43b2 5433*vr5400:
a83d7d87 5434// end-sanitize-cygnus
f2b30012
AC		 5435// start-sanitize-r5900
5436*r5900:
5437// end-sanitize-r5900
5438{
5439 unsigned32 instruction = instruction_0;
055ee297
AC		 5440 int destreg = ((instruction >> 6) & 0x0000001F);
5441 int fs = ((instruction >> 11) & 0x0000001F);
5442 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5443 {
5444 StoreFPR(destreg,format,ValueFPR(fs,format));
5445 }
5446}
5447
5448
5449// MSUB.fmt
5450010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
5451"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
5452*mipsIV:
23850e92 5453*vr5000:
15232df4
FCE		 5454// start-sanitize-vr4320
5455*vr4320:
5456// end-sanitize-vr4320
a83d7d87 5457// start-sanitize-cygnus
90ad43b2 5458*vr5400:
a83d7d87 5459// end-sanitize-cygnus
f2b30012
AC		 5460// start-sanitize-r5900
5461*r5900:
5462// end-sanitize-r5900
5463{
5464 unsigned32 instruction = instruction_0;
055ee297
AC		 5465 int destreg = ((instruction >> 6) & 0x0000001F);
5466 int fs = ((instruction >> 11) & 0x0000001F);
5467 int ft = ((instruction >> 16) & 0x0000001F);
5468 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012 5469 {
23850e92 5470 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
f2b30012
AC		 5471 }
5472}
5473
5474
5475// MSUB.fmt
055ee297 5476010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
f2b30012
AC		 5477"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
5478*mipsIV:
23850e92 5479*vr5000:
15232df4
FCE		 5480// start-sanitize-vr4320
5481*vr4320:
5482// end-sanitize-vr4320
a83d7d87 5483// start-sanitize-cygnus
90ad43b2 5484*vr5400:
a83d7d87 5485// end-sanitize-cygnus
f2b30012
AC		 5486// start-sanitize-r5900
5487*r5900:
5488// end-sanitize-r5900
5489{
5490 unsigned32 instruction = instruction_0;
055ee297
AC		 5491 int destreg = ((instruction >> 6) & 0x0000001F);
5492 int fs = ((instruction >> 11) & 0x0000001F);
5493 int ft = ((instruction >> 16) & 0x0000001F);
5494 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012 5495 {
23850e92 5496 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
f2b30012
AC		 5497 }
5498}
5499
5500
5501// MTC1 see MxC1
5502
5503
5504010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
5505"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
23850e92 5506*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 5507*vr4100:
23850e92 5508*vr5000:
f14397f0
GRK		 5509// start-sanitize-vr4xxx
5510*vr4121:
5511// end-sanitize-vr4xxx
15232df4
FCE		 5512// start-sanitize-vr4320
5513*vr4320:
5514// end-sanitize-vr4320
a83d7d87 5515// start-sanitize-cygnus
90ad43b2 5516*vr5400:
a83d7d87 5517// end-sanitize-cygnus
f2b30012
AC		 5518*r3900:
5519// start-sanitize-tx19
5520*tx19:
5521// end-sanitize-tx19
5522{
5523 unsigned32 instruction = instruction_0;
055ee297
AC		 5524 int destreg = ((instruction >> 6) & 0x0000001F);
5525 int fs = ((instruction >> 11) & 0x0000001F);
5526 int ft = ((instruction >> 16) & 0x0000001F);
5527 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5528 {
5529 if ((format != fmt_single) && (format != fmt_double))
5530 SignalException(ReservedInstruction,instruction);
5531 else
5532 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
5533 }
5534}
5535
5536
5537010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
5538"neg.%s<FMT> f<FD>, f<FS>"
23850e92 5539*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 5540*vr4100:
23850e92 5541*vr5000:
f14397f0
GRK		 5542// start-sanitize-vr4xxx
5543*vr4121:
5544// end-sanitize-vr4xxx
15232df4
FCE		 5545// start-sanitize-vr4320
5546*vr4320:
5547// end-sanitize-vr4320
a83d7d87 5548// start-sanitize-cygnus
90ad43b2 5549*vr5400:
a83d7d87 5550// end-sanitize-cygnus
f2b30012
AC		 5551*r3900:
5552// start-sanitize-tx19
5553*tx19:
5554// end-sanitize-tx19
5555{
5556 unsigned32 instruction = instruction_0;
055ee297
AC		 5557 int destreg = ((instruction >> 6) & 0x0000001F);
5558 int fs = ((instruction >> 11) & 0x0000001F);
5559 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5560 {
5561 if ((format != fmt_single) && (format != fmt_double))
5562 SignalException(ReservedInstruction,instruction);
5563 else
5564 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
5565 }
5566}
5567
5568
5569// NMADD.fmt
5570010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
5571"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
5572*mipsIV:
23850e92 5573*vr5000:
15232df4
FCE		 5574// start-sanitize-vr4320
5575*vr4320:
5576// end-sanitize-vr4320
a83d7d87 5577// start-sanitize-cygnus
90ad43b2 5578*vr5400:
a83d7d87 5579// end-sanitize-cygnus
f2b30012
AC		 5580{
5581 unsigned32 instruction = instruction_0;
055ee297
AC		 5582 int destreg = ((instruction >> 6) & 0x0000001F);
5583 int fs = ((instruction >> 11) & 0x0000001F);
5584 int ft = ((instruction >> 16) & 0x0000001F);
5585 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 5586 {
5587 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5588 }
5589}
5590
5591
5592// NMADD.fmt
5593010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
5594"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
5595*mipsIV:
23850e92 5596*vr5000:
15232df4
FCE		 5597// start-sanitize-vr4320
5598*vr4320:
5599// end-sanitize-vr4320
a83d7d87 5600// start-sanitize-cygnus
90ad43b2 5601*vr5400:
a83d7d87 5602// end-sanitize-cygnus
f2b30012
AC		 5603{
5604 unsigned32 instruction = instruction_0;
055ee297
AC		 5605 int destreg = ((instruction >> 6) & 0x0000001F);
5606 int fs = ((instruction >> 11) & 0x0000001F);
5607 int ft = ((instruction >> 16) & 0x0000001F);
5608 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 5609 {
5610 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5611 }
5612}
5613
5614
5615// NMSUB.fmt
055ee297 5616010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
f2b30012
AC		 5617"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
5618*mipsIV:
23850e92 5619*vr5000:
15232df4
FCE		 5620// start-sanitize-vr4320
5621*vr4320:
5622// end-sanitize-vr4320
a83d7d87 5623// start-sanitize-cygnus
90ad43b2 5624*vr5400:
a83d7d87 5625// end-sanitize-cygnus
f2b30012
AC		 5626{
5627 unsigned32 instruction = instruction_0;
055ee297
AC		 5628 int destreg = ((instruction >> 6) & 0x0000001F);
5629 int fs = ((instruction >> 11) & 0x0000001F);
5630 int ft = ((instruction >> 16) & 0x0000001F);
5631 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 5632 {
5633 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5634 }
5635}
5636
5637
5638// NMSUB.fmt
055ee297 5639010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
f2b30012
AC		 5640"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
5641*mipsIV:
23850e92 5642*vr5000:
15232df4
FCE		 5643// start-sanitize-vr4320
5644*vr4320:
5645// end-sanitize-vr4320
a83d7d87 5646// start-sanitize-cygnus
90ad43b2 5647*vr5400:
a83d7d87 5648// end-sanitize-cygnus
f2b30012
AC		 5649{
5650 unsigned32 instruction = instruction_0;
055ee297
AC		 5651 int destreg = ((instruction >> 6) & 0x0000001F);
5652 int fs = ((instruction >> 11) & 0x0000001F);
5653 int ft = ((instruction >> 16) & 0x0000001F);
5654 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 5655 {
5656 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5657 }
5658}
5659
5660
5661010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
49a6eed5 5662"prefx <HINT>, r<INDEX>(r<BASE>)"
f2b30012 5663*mipsIV:
23850e92 5664*vr5000:
15232df4
FCE		 5665// start-sanitize-vr4320
5666*vr4320:
5667// end-sanitize-vr4320
a83d7d87 5668// start-sanitize-cygnus
90ad43b2 5669*vr5400:
a83d7d87 5670// end-sanitize-cygnus
f2b30012
AC		 5671{
5672 unsigned32 instruction = instruction_0;
055ee297
AC		 5673 int fs = ((instruction >> 11) & 0x0000001F);
5674 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5675 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 5676 {
49a76833
AC		 5677 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
5678 address_word paddr;
f2b30012
AC		 5679 int uncached;
5680 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5681 Prefetch(uncached,paddr,vaddr,isDATA,fs);
5682 }
5683}
5684
5685010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
5686*mipsIV:
5687"recip.%s<FMT> f<FD>, f<FS>"
23850e92 5688*vr5000:
15232df4
FCE		 5689// start-sanitize-vr4320
5690*vr4320:
5691// end-sanitize-vr4320
a83d7d87 5692// start-sanitize-cygnus
90ad43b2 5693*vr5400:
a83d7d87 5694// end-sanitize-cygnus
f2b30012
AC		 5695{
5696 unsigned32 instruction = instruction_0;
055ee297
AC		 5697 int destreg = ((instruction >> 6) & 0x0000001F);
5698 int fs = ((instruction >> 11) & 0x0000001F);
5699 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5700 {
5701 if ((format != fmt_single) && (format != fmt_double))
5702 SignalException(ReservedInstruction,instruction);
5703 else
5704 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5705 }
5706}
5707
5708
5709010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
49a6eed5 5710"round.l.%s<FMT> f<FD>, f<FS>"
f2b30012
AC		 5711*mipsIII:
5712*mipsIV:
1ee7d2b1 5713*vr4100:
23850e92 5714*vr5000:
f14397f0
GRK		 5715// start-sanitize-vr4xxx
5716*vr4121:
5717// end-sanitize-vr4xxx
15232df4
FCE		 5718// start-sanitize-vr4320
5719*vr4320:
5720// end-sanitize-vr4320
a83d7d87 5721// start-sanitize-cygnus
90ad43b2 5722*vr5400:
a83d7d87 5723// end-sanitize-cygnus
f2b30012
AC		 5724// start-sanitize-r5900
5725*r5900:
5726// end-sanitize-r5900
5727*r3900:
5728// start-sanitize-tx19
5729*tx19:
5730// end-sanitize-tx19
5731{
5732 unsigned32 instruction = instruction_0;
055ee297
AC		 5733 int destreg = ((instruction >> 6) & 0x0000001F);
5734 int fs = ((instruction >> 11) & 0x0000001F);
5735 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5736 {
5737 if ((format != fmt_single) && (format != fmt_double))
5738 SignalException(ReservedInstruction,instruction);
5739 else
5740 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5741 }
5742}
5743
5744
5745010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
49a6eed5 5746"round.w.%s<FMT> f<FD>, f<FS>"
f2b30012
AC		 5747*mipsII:
5748*mipsIII:
5749*mipsIV:
1ee7d2b1 5750*vr4100:
23850e92 5751*vr5000:
f14397f0
GRK		 5752// start-sanitize-vr4xxx
5753*vr4121:
5754// end-sanitize-vr4xxx
15232df4
FCE		 5755// start-sanitize-vr4320
5756*vr4320:
5757// end-sanitize-vr4320
a83d7d87 5758// start-sanitize-cygnus
90ad43b2 5759*vr5400:
a83d7d87 5760// end-sanitize-cygnus
f2b30012
AC		 5761// start-sanitize-r5900
5762*r5900:
5763// end-sanitize-r5900
5764*r3900:
5765// start-sanitize-tx19
5766*tx19:
5767// end-sanitize-tx19
5768{
5769 unsigned32 instruction = instruction_0;
055ee297
AC		 5770 int destreg = ((instruction >> 6) & 0x0000001F);
5771 int fs = ((instruction >> 11) & 0x0000001F);
5772 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5773 {
5774 if ((format != fmt_single) && (format != fmt_double))
5775 SignalException(ReservedInstruction,instruction);
5776 else
5777 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5778 }
5779}
5780
5781
5782010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5783*mipsIV:
5784"rsqrt.%s<FMT> f<FD>, f<FS>"
23850e92 5785*vr5000:
15232df4
FCE		 5786// start-sanitize-vr4320
5787*vr4320:
5788// end-sanitize-vr4320
a83d7d87 5789// start-sanitize-cygnus
90ad43b2 5790*vr5400:
a83d7d87 5791// end-sanitize-cygnus
f2b30012
AC		 5792{
5793 unsigned32 instruction = instruction_0;
055ee297
AC		 5794 int destreg = ((instruction >> 6) & 0x0000001F);
5795 int fs = ((instruction >> 11) & 0x0000001F);
5796 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5797 {
5798 if ((format != fmt_single) && (format != fmt_double))
5799 SignalException(ReservedInstruction,instruction);
5800 else
085c1cb9 5801 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
f2b30012
AC		 5802 }
5803}
5804
5805
030843d7
AC		 5806111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5807"sdc1 f<FT>, <OFFSET>(r<BASE>)"
5808*mipsII:
5809*mipsIII:
5810*mipsIV:
1ee7d2b1 5811*vr4100:
23850e92 5812*vr5000:
f14397f0
GRK		 5813// start-sanitize-vr4xxx
5814*vr4121:
5815// end-sanitize-vr4xxx
15232df4
FCE		 5816// start-sanitize-vr4320
5817*vr4320:
5818// end-sanitize-vr4320
a83d7d87 5819// start-sanitize-cygnus
030843d7 5820*vr5400:
a83d7d87 5821// end-sanitize-cygnus
030843d7
AC		 5822*r3900:
5823// start-sanitize-tx19
5824*tx19:
5825// end-sanitize-tx19
5826{
ebcfd86a 5827 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
030843d7 5828}
f2b30012
AC		 5829
5830
ebcfd86a
FCE		 5831010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
5832"ldxc1 f<FS>, r<INDEX>(r<BASE>)"
f2b30012 5833*mipsIV:
23850e92 5834*vr5000:
15232df4
FCE		 5835// start-sanitize-vr4320
5836*vr4320:
5837// end-sanitize-vr4320
a83d7d87 5838// start-sanitize-cygnus
90ad43b2 5839*vr5400:
a83d7d87 5840// end-sanitize-cygnus
f2b30012 5841{
ebcfd86a 5842 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
f2b30012
AC		 5843}
5844
5845
5846010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5847"sqrt.%s<FMT> f<FD>, f<FS>"
5848*mipsII:
5849*mipsIII:
5850*mipsIV:
1ee7d2b1 5851*vr4100:
23850e92 5852*vr5000:
f14397f0
GRK		 5853// start-sanitize-vr4xxx
5854*vr4121:
5855// end-sanitize-vr4xxx
15232df4
FCE		 5856// start-sanitize-vr4320
5857*vr4320:
5858// end-sanitize-vr4320
a83d7d87 5859// start-sanitize-cygnus
90ad43b2 5860*vr5400:
a83d7d87 5861// end-sanitize-cygnus
f2b30012
AC		 5862*r3900:
5863// start-sanitize-tx19
5864*tx19:
5865// end-sanitize-tx19
5866{
5867 unsigned32 instruction = instruction_0;
055ee297
AC		 5868 int destreg = ((instruction >> 6) & 0x0000001F);
5869 int fs = ((instruction >> 11) & 0x0000001F);
5870 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5871 {
5872 if ((format != fmt_single) && (format != fmt_double))
5873 SignalException(ReservedInstruction,instruction);
5874 else
5875 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5876 }
5877}
5878
5879
5880010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5881"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
23850e92 5882*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 5883*vr4100:
23850e92 5884*vr5000:
f14397f0
GRK		 5885// start-sanitize-vr4xxx
5886*vr4121:
5887// end-sanitize-vr4xxx
15232df4
FCE		 5888// start-sanitize-vr4320
5889*vr4320:
5890// end-sanitize-vr4320
a83d7d87 5891// start-sanitize-cygnus
90ad43b2 5892*vr5400:
a83d7d87 5893// end-sanitize-cygnus
f2b30012
AC		 5894*r3900:
5895// start-sanitize-tx19
5896*tx19:
5897// end-sanitize-tx19
5898{
5899 unsigned32 instruction = instruction_0;
055ee297
AC		 5900 int destreg = ((instruction >> 6) & 0x0000001F);
5901 int fs = ((instruction >> 11) & 0x0000001F);
5902 int ft = ((instruction >> 16) & 0x0000001F);
5903 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 5904 {
5905 if ((format != fmt_single) && (format != fmt_double))
5906 SignalException(ReservedInstruction,instruction);
5907 else
5908 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5909 }
5910}
5911
5912
f2b30012 5913
030843d7
AC		 5914111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5915"swc1 f<FT>, <OFFSET>(r<BASE>)"
23850e92 5916*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 5917*vr4100:
23850e92 5918*vr5000:
f14397f0
GRK		 5919// start-sanitize-vr4xxx
5920*vr4121:
5921// end-sanitize-vr4xxx
15232df4
FCE		 5922// start-sanitize-vr4320
5923*vr4320:
5924// end-sanitize-vr4320
a83d7d87 5925// start-sanitize-cygnus
90ad43b2 5926*vr5400:
a83d7d87 5927// end-sanitize-cygnus
f2b30012
AC		 5928// start-sanitize-r5900
5929*r5900:
5930// end-sanitize-r5900
030843d7
AC		 5931*r3900:
5932// start-sanitize-tx19
5933*tx19:
5934// end-sanitize-tx19
5935{
5936 unsigned32 instruction = instruction_0;
5937 signed_word offset = EXTEND16 (OFFSET);
5938 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5939 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5940 {
5941 address_word vaddr = ((uword64)op1 + offset);
5942 address_word paddr;
5943 int uncached;
5944 if ((vaddr & 3) != 0)
5945 SignalExceptionAddressStore();
5946 else
5947 {
5948 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5949 {
5950 uword64 memval = 0;
5951 uword64 memval1 = 0;
2b5d87df
GRK		 5952 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5953 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5954 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
030843d7 5955 unsigned int byte;
2b5d87df
GRK		 5956 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5957 byte = ((vaddr & mask) ^ bigendiancpu);
030843d7 5958 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
2b5d87df 5959 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
030843d7
AC		 5960 }
5961 }
5962 }
5963}
5964
5965
5966010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5967"swxc1 f<FS>, r<INDEX>(r<BASE>)"
5968*mipsIV:
23850e92 5969*vr5000:
15232df4
FCE		 5970// start-sanitize-vr4320
5971*vr4320:
5972// end-sanitize-vr4320
a83d7d87 5973// start-sanitize-cygnus
030843d7 5974*vr5400:
a83d7d87 5975// end-sanitize-cygnus
f2b30012
AC		 5976{
5977 unsigned32 instruction = instruction_0;
055ee297
AC		 5978 int fs = ((instruction >> 11) & 0x0000001F);
5979 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5980 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 5981 {
49a76833
AC		 5982 address_word vaddr = ((unsigned64)op1 + op2);
5983 address_word paddr;
f2b30012
AC		 5984 int uncached;
5985 if ((vaddr & 3) != 0)
055ee297 5986 SignalExceptionAddressStore();
f2b30012
AC		 5987 else
5988 {
5989 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5990 {
5991 unsigned64 memval = 0;
5992 unsigned64 memval1 = 0;
5993 unsigned64 mask = 0x7;
5994 unsigned int byte;
5995 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5996 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5997 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5998 {
5999 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
6000 }
6001 }
6002 }
6003 }
6004}
6005
6006
6007010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
6008"trunc.l.%s<FMT> f<FD>, f<FS>"
6009*mipsIII:
6010*mipsIV:
1ee7d2b1 6011*vr4100:
23850e92 6012*vr5000:
f14397f0
GRK		 6013// start-sanitize-vr4xxx
6014*vr4121:
6015// end-sanitize-vr4xxx
15232df4
FCE		 6016// start-sanitize-vr4320
6017*vr4320:
6018// end-sanitize-vr4320
a83d7d87 6019// start-sanitize-cygnus
90ad43b2 6020*vr5400:
a83d7d87 6021// end-sanitize-cygnus
f2b30012
AC		 6022// start-sanitize-r5900
6023*r5900:
6024// end-sanitize-r5900
6025*r3900:
6026// start-sanitize-tx19
6027*tx19:
6028// end-sanitize-tx19
6029{
6030 unsigned32 instruction = instruction_0;
055ee297
AC		 6031 int destreg = ((instruction >> 6) & 0x0000001F);
6032 int fs = ((instruction >> 11) & 0x0000001F);
6033 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 6034 {
6035 if ((format != fmt_single) && (format != fmt_double))
6036 SignalException(ReservedInstruction,instruction);
6037 else
6038 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
6039 }
6040}
6041
6042
6043010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
6044"trunc.w.%s<FMT> f<FD>, f<FS>"
6045*mipsII:
6046*mipsIII:
6047*mipsIV:
1ee7d2b1 6048*vr4100:
23850e92 6049*vr5000:
f14397f0
GRK		 6050// start-sanitize-vr4xxx
6051*vr4121:
6052// end-sanitize-vr4xxx
15232df4
FCE		 6053// start-sanitize-vr4320
6054*vr4320:
6055// end-sanitize-vr4320
a83d7d87 6056// start-sanitize-cygnus
90ad43b2 6057*vr5400:
a83d7d87 6058// end-sanitize-cygnus
f2b30012
AC		 6059// start-sanitize-r5900
6060*r5900:
6061// end-sanitize-r5900
6062*r3900:
6063// start-sanitize-tx19
6064*tx19:
6065// end-sanitize-tx19
6066{
6067 unsigned32 instruction = instruction_0;
055ee297
AC		 6068 int destreg = ((instruction >> 6) & 0x0000001F);
6069 int fs = ((instruction >> 11) & 0x0000001F);
6070 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 6071 {
6072 if ((format != fmt_single) && (format != fmt_double))
6073 SignalException(ReservedInstruction,instruction);
6074 else
6075 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
6076 }
6077}
6078
6079\f
6080//
6081// MIPS Architecture:
6082//
6083// System Control Instruction Set (COP0)
6084//
6085
6086
6087010000,01000,00000,16.OFFSET:COP0:32::BC0F
6088"bc0f <OFFSET>"
23850e92 6089*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 6090*vr4100:
23850e92 6091*vr5000:
f14397f0
GRK		 6092// start-sanitize-vr4xxx
6093*vr4121:
6094// end-sanitize-vr4xxx
15232df4
FCE		 6095// start-sanitize-vr4320
6096*vr4320:
6097// end-sanitize-vr4320
a83d7d87 6098// start-sanitize-cygnus
90ad43b2 6099*vr5400:
a83d7d87 6100// end-sanitize-cygnus
f2b30012
AC		 6101
6102
6103010000,01000,00010,16.OFFSET:COP0:32::BC0FL
6104"bc0fl <OFFSET>"
23850e92 6105*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 6106*vr4100:
23850e92 6107*vr5000:
f14397f0
GRK		 6108// start-sanitize-vr4xxx
6109*vr4121:
6110// end-sanitize-vr4xxx
15232df4
FCE		 6111// start-sanitize-vr4320
6112*vr4320:
6113// end-sanitize-vr4320
a83d7d87 6114// start-sanitize-cygnus
90ad43b2 6115*vr5400:
a83d7d87 6116// end-sanitize-cygnus
f2b30012
AC		 6117
6118
6119010000,01000,00001,16.OFFSET:COP0:32::BC0T
6120"bc0t <OFFSET>"
23850e92 6121*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 6122*vr4100:
f14397f0
GRK		 6123// start-sanitize-vr4xxx
6124*vr4121:
6125// end-sanitize-vr4xxx
f2b30012
AC		 6126
6127
49a6eed5 6128010000,01000,00011,16.OFFSET:COP0:32::BC0TL
f2b30012 6129"bc0tl <OFFSET>"
23850e92 6130*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 6131*vr4100:
23850e92 6132*vr5000:
f14397f0
GRK		 6133// start-sanitize-vr4xxx
6134*vr4121:
6135// end-sanitize-vr4xxx
15232df4
FCE		 6136// start-sanitize-vr4320
6137*vr4320:
6138// end-sanitize-vr4320
a83d7d87 6139// start-sanitize-cygnus
90ad43b2 6140*vr5400:
a83d7d87 6141// end-sanitize-cygnus
f2b30012
AC		 6142
6143
6144101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
6145*mipsIII:
6146*mipsIV:
1ee7d2b1 6147*vr4100:
23850e92 6148*vr5000:
f14397f0
GRK		 6149// start-sanitize-vr4xxx
6150*vr4121:
6151// end-sanitize-vr4xxx
15232df4
FCE		 6152// start-sanitize-vr4320
6153*vr4320:
6154// end-sanitize-vr4320
a83d7d87 6155// start-sanitize-cygnus
90ad43b2 6156*vr5400:
a83d7d87 6157// end-sanitize-cygnus
f2b30012
AC		 6158*r3900:
6159// start-sanitize-tx19
6160*tx19:
6161// end-sanitize-tx19
6162{
6163 unsigned32 instruction = instruction_0;
055ee297
AC		 6164 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
6165 int hint = ((instruction >> 16) & 0x0000001F);
6166 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 6167 {
49a76833
AC		 6168 address_word vaddr = (op1 + offset);
6169 address_word paddr;
f2b30012
AC		 6170 int uncached;
6171 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
6172 CacheOp(hint,vaddr,paddr,instruction);
6173 }
6174}
6175
6176
6177010000,10000,000000000000000,111001:COP0:32::DI
6178"di"
23850e92 6179*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 6180*vr4100:
23850e92 6181*vr5000:
f14397f0
GRK		 6182// start-sanitize-vr4xxx
6183*vr4121:
6184// end-sanitize-vr4xxx
15232df4
FCE		 6185// start-sanitize-vr4320
6186*vr4320:
6187// end-sanitize-vr4320
a83d7d87 6188// start-sanitize-cygnus
90ad43b2 6189*vr5400:
a83d7d87 6190// end-sanitize-cygnus
f2b30012
AC		 6191
6192
6193010000,10000,000000000000000,111000:COP0:32::EI
6194"ei"
23850e92 6195*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 6196*vr4100:
23850e92 6197*vr5000:
f14397f0
GRK		 6198// start-sanitize-vr4xxx
6199*vr4121:
6200// end-sanitize-vr4xxx
15232df4
FCE		 6201// start-sanitize-vr4320
6202*vr4320:
6203// end-sanitize-vr4320
a83d7d87 6204// start-sanitize-cygnus
90ad43b2 6205*vr5400:
a83d7d87 6206// end-sanitize-cygnus
f2b30012
AC		 6207
6208
6209010000,10000,000000000000000,011000:COP0:32::ERET
6210"eret"
6211*mipsIII:
6212*mipsIV:
1ee7d2b1 6213*vr4100:
23850e92 6214*vr5000:
f14397f0
GRK		 6215// start-sanitize-vr4xxx
6216*vr4121:
6217// end-sanitize-vr4xxx
15232df4
FCE		 6218// start-sanitize-vr4320
6219*vr4320:
6220// end-sanitize-vr4320
a83d7d87 6221// start-sanitize-cygnus
90ad43b2 6222*vr5400:
a83d7d87 6223// end-sanitize-cygnus
f2b30012
AC		 6224// start-sanitize-r5900
6225*r5900:
6226// end-sanitize-r5900
97f4d183
AC		 6227{
6228 if (SR & status_ERL)
6229 {
6230 /* Oops, not yet available */
6231 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
6232 NIA = EPC;
6233 SR &= ~status_ERL;
6234 }
6235 else
6236 {
6237 NIA = EPC;
6238 SR &= ~status_EXL;
6239 }
6240}
f2b30012
AC		 6241
6242
49a6eed5
AC		 6243010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
6244"mfc0 r<RT>, r<RD> # <REGX>"
23850e92 6245*mipsI,mipsII,mipsIII,mipsIV:
3fa454e9 6246*r3900:
1ee7d2b1 6247*vr4100:
23850e92 6248*vr5000:
f14397f0
GRK		 6249// start-sanitize-vr4xxx
6250*vr4121:
6251// end-sanitize-vr4xxx
15232df4
FCE		 6252// start-sanitize-vr4320
6253*vr4320:
6254// end-sanitize-vr4320
a83d7d87 6255// start-sanitize-cygnus
90ad43b2 6256*vr5400:
a83d7d87 6257// end-sanitize-cygnus
f2b30012
AC		 6258// start-sanitize-r5900
6259*r5900:
6260// end-sanitize-r5900
030843d7 6261{
97f4d183 6262 TRACE_ALU_INPUT0 ();
030843d7 6263 DecodeCoproc (instruction_0);
97f4d183 6264 TRACE_ALU_RESULT (GPR[RT]);
030843d7 6265}
f2b30012 6266
49a6eed5
AC		 6267010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
6268"mtc0 r<RT>, r<RD> # <REGX>"
23850e92 6269*mipsI,mipsII,mipsIII,mipsIV:
f3bdd368
AC		 6270// start-sanitize-tx19
6271*tx19:
6272// end-sanitize-tx19
ebcfd86a 6273*r3900:
1ee7d2b1 6274*vr4100:
f14397f0
GRK		 6275// start-sanitize-vr4xxx
6276*vr4121:
6277// end-sanitize-vr4xxx
15232df4
FCE		 6278// start-sanitize-vr4320
6279*vr4320:
6280// end-sanitize-vr4320
ebcfd86a 6281*vr5000:
a83d7d87 6282// start-sanitize-cygnus
90ad43b2 6283*vr5400:
a83d7d87 6284// end-sanitize-cygnus
f2b30012 6285// start-sanitize-r5900
3fa454e9
FCE		 6286*r5900:
6287// end-sanitize-r5900
6288{
6289 DecodeCoproc (instruction_0);
6290}
6291
6292
6293010000,10000,000000000000000,010000:COP0:32::RFE
6294"rfe"
6295*mipsI,mipsII,mipsIII,mipsIV:
6296// start-sanitize-tx19
6297*tx19:
6298// end-sanitize-tx19
6299*r3900:
1ee7d2b1 6300*vr4100:
f14397f0
GRK		 6301// start-sanitize-vr4xxx
6302*vr4121:
6303// end-sanitize-vr4xxx
3fa454e9
FCE		 6304// start-sanitize-vr4320
6305*vr4320:
6306// end-sanitize-vr4320
6307*vr5000:
a83d7d87 6308// start-sanitize-cygnus
3fa454e9 6309*vr5400:
a83d7d87 6310// end-sanitize-cygnus
3fa454e9 6311// start-sanitize-r5900
f2b30012
AC		 6312*r5900:
6313// end-sanitize-r5900
030843d7
AC		 6314{
6315 DecodeCoproc (instruction_0);
6316}
f2b30012
AC		 6317
6318
702968c5
FCE		 63190100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
6320"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
6321*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 6322*vr4100:
f14397f0
GRK		 6323// start-sanitize-vr4xxx
6324*vr4121:
6325// end-sanitize-vr4xxx
702968c5
FCE		 6326// start-sanitize-r5900
6327*r5900:
6328// end-sanitize-r5900
6329*r3900:
6330// start-sanitize-tx19
6331*tx19:
6332// end-sanitize-tx19
6333{
6334 DecodeCoproc (instruction_0);
6335}
6336
6337
6338
f2b30012
AC		 6339010000,10000,000000000000000,001000:COP0:32::TLBP
6340"tlbp"
23850e92 6341*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 6342*vr4100:
23850e92 6343*vr5000:
f14397f0
GRK		 6344// start-sanitize-vr4xxx
6345*vr4121:
6346// end-sanitize-vr4xxx
15232df4
FCE		 6347// start-sanitize-vr4320
6348*vr4320:
6349// end-sanitize-vr4320
a83d7d87 6350// start-sanitize-cygnus
90ad43b2 6351*vr5400:
a83d7d87 6352// end-sanitize-cygnus
f2b30012
AC		 6353
6354
6355010000,10000,000000000000000,000001:COP0:32::TLBR
6356"tlbr"
23850e92 6357*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 6358*vr4100:
23850e92 6359*vr5000:
f14397f0
GRK		 6360// start-sanitize-vr4xxx
6361*vr4121:
6362// end-sanitize-vr4xxx
15232df4
FCE		 6363// start-sanitize-vr4320
6364*vr4320:
6365// end-sanitize-vr4320
a83d7d87 6366// start-sanitize-cygnus
90ad43b2 6367*vr5400:
a83d7d87 6368// end-sanitize-cygnus
f2b30012
AC		 6369
6370
6371010000,10000,000000000000000,000010:COP0:32::TLBWI
6372"tlbwi"
23850e92 6373*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 6374*vr4100:
23850e92 6375*vr5000:
f14397f0
GRK		 6376// start-sanitize-vr4xxx
6377*vr4121:
6378// end-sanitize-vr4xxx
15232df4
FCE		 6379// start-sanitize-vr4320
6380*vr4320:
6381// end-sanitize-vr4320
a83d7d87 6382// start-sanitize-cygnus
90ad43b2 6383*vr5400:
a83d7d87 6384// end-sanitize-cygnus
f2b30012
AC		 6385
6386
6387010000,10000,000000000000000,000110:COP0:32::TLBWR
6388"tlbwr"
23850e92 6389*mipsI,mipsII,mipsIII,mipsIV:
1ee7d2b1 6390*vr4100:
23850e92 6391*vr5000:
f14397f0
GRK		 6392// start-sanitize-vr4xxx
6393*vr4121:
6394// end-sanitize-vr4xxx
15232df4
FCE		 6395// start-sanitize-vr4320
6396*vr4320:
6397// end-sanitize-vr4320
a83d7d87 6398// start-sanitize-cygnus
90ad43b2 6399*vr5400:
a83d7d87 6400// end-sanitize-cygnus
f2b30012
AC		 6401
6402\f
f3bdd368 6403:include:::m16.igen
a83d7d87 6404// start-sanitize-cygnus
a48e8c8d 6405:include:64,f::mdmx.igen
a83d7d87 6406// end-sanitize-cygnus
f2b30012 6407// start-sanitize-r5900
89d09738 6408:include::r5900:r5900.igen
f2b30012 6409// end-sanitize-r5900
ebcfd86a 6410:include:::tx.igen
a83d7d87 6411:include:::vr.igen
f2b30012
AC		 6412\f
6413// start-sanitize-cygnus-never
6414
49a6eed5
AC		 6415// // FIXME FIXME FIXME What is this instruction?
6416// 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
6417// *mipsI:
6418// *mipsII:
6419// *mipsIII:
6420// *mipsIV:
6421// // start-sanitize-r5900
6422// *r5900:
6423// // end-sanitize-r5900
6424// *r3900:
6425// // start-sanitize-tx19
6426// *tx19:
6427// // end-sanitize-tx19
6428// {
6429// unsigned32 instruction = instruction_0;
055ee297
AC		 6430// signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
6431// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
6432// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
49a6eed5
AC		 6433// {
6434// if (CoProcPresent(3))
6435// SignalException(CoProcessorUnusable);
6436// else
6437// SignalException(ReservedInstruction,instruction);
6438// }
6439// }
6440
6441// end-sanitize-cygnus-never
6442// start-sanitize-cygnus-never
6443
6444// // FIXME FIXME FIXME What is this?
6445// 11100,******,00001:RR:16::SDBBP
6446// *mips16:
6447// {
6448// unsigned32 instruction = instruction_0;
6449// if (have_extendval)
6450// SignalException (ReservedInstruction, instruction);
6451// {
6452// SignalException(DebugBreakPoint,instruction);
6453// }
6454// }
f2b30012
AC		 6455
6456// end-sanitize-cygnus-never
6457// start-sanitize-cygnus-never
6458
49a6eed5
AC		 6459// // FIXME FIXME FIXME What is this?
6460// 000000,********************,001110:SPECIAL:32::SDBBP
6461// *r3900:
6462// {
6463// unsigned32 instruction = instruction_0;
6464// {
6465// SignalException(DebugBreakPoint,instruction);
6466// }
6467// }
f2b30012
AC		 6468
6469// end-sanitize-cygnus-never
GDB Binutils - Deliverables
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