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Implement 32 bit MIPS16 instructions listed in m16.igen.
[deliverable/binutils-gdb.git] / sim / mips / mips.igen
CommitLineData
ca6f76d1
AC		 1// -*- C -*-
2//
f2b30012
AC		 3// <insn> ::=
4// <insn-word> { "+" <insn-word> }
5// ":" <format-name>
6// ":" <filter-flags>
7// ":" <options>
8// ":" <name>
9// <nl>
10// { <insn-model> }
11// { <insn-mnemonic> }
12// <code-block>
13//
14
15
16// IGEN config - mips16
a48e8c8d
AC		 17// :option:16::insn-bit-size:16
18// :option:16::hi-bit-nr:15
89d09738
AC		 19:option:16::insn-specifying-widths:true
20:option:16::gen-delayed-branch:false
f2b30012 21
90ad43b2 22// IGEN config - mips32/64..
a48e8c8d
AC		 23// :option:32::insn-bit-size:32
24// :option:32::hi-bit-nr:31
89d09738
AC		 25:option:32::insn-specifying-widths:true
26:option:32::gen-delayed-branch:false
f2b30012
AC		 27
28
49a6eed5 29// Generate separate simulators for each target
89d09738 30// :option:::multi-sim:true
49a6eed5 31
f2b30012
AC		 32
33// Models known by this simulator
15232df4
FCE		 34:model:::mipsI:mips3000:
35:model:::mipsII:mips6000:
36:model:::mipsIII:mips4000:
37:model:::mipsIV:mips8000:
89d09738 38:model:::mips16:mips16:
f2b30012 39// start-sanitize-r5900
a48e8c8d 40:model:::r5900:mips5900:
f2b30012 41// end-sanitize-r5900
a48e8c8d 42:model:::r3900:mips3900:
f2b30012 43// start-sanitize-tx19
89d09738 44:model:::tx19:tx19:
f2b30012 45// end-sanitize-tx19
15232df4
FCE		 46// start-sanitize-vr4320
47:model:::vr4320:mips4320:
48// end-sanitize-vr4320
90ad43b2 49// start-sanitize-vr5400
a48e8c8d 50:model:::vr5400:mips5400:
23850e92 51:model:::mdmx:mdmx:
90ad43b2 52// end-sanitize-vr5400
a48e8c8d 53:model:::vr5000:mips5000:
f2b30012
AC		 54
55
56
57// Pseudo instructions known by IGEN
89d09738 58:internal::::illegal:
f2b30012 59{
030843d7 60 SignalException (ReservedInstruction, 0);
f2b30012
AC		 61}
62
63
030843d7
AC		 64// Pseudo instructions known by interp.c
65// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
66000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
67"rsvd <OP>"
68{
69 SignalException (ReservedInstruction, instruction_0);
70}
71
f2b30012
AC		 72
73
74//
7ce8b917 75// Mips Architecture:
f2b30012
AC		 76//
77// CPU Instruction Set (mipsI - mipsIV)
78//
79
80
c0a4c3ba 81
f2b30012
AC		 82000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
83"add r<RD>, r<RS>, r<RT>"
23850e92
JL		 84*mipsI,mipsII,mipsIII,mipsIV:
85*vr5000:
15232df4
FCE		 86// start-sanitize-vr4320
87*vr4320:
88// end-sanitize-vr4320
90ad43b2
AC		 89// start-sanitize-vr5400
90*vr5400:
91// end-sanitize-vr5400
f2b30012
AC		 92// start-sanitize-r5900
93*r5900:
94// end-sanitize-r5900
95*r3900:
96// start-sanitize-tx19
97*tx19:
98// end-sanitize-tx19
99{
055ee297
AC		 100 ALU32_BEGIN (GPR[RS]);
101 ALU32_ADD (GPR[RT]);
102 ALU32_END (GPR[RD]);
f2b30012
AC		 103}
104
105
c0a4c3ba 106
f2b30012
AC		 107001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
108"addi r<RT>, r<RS>, IMMEDIATE"
23850e92
JL		 109*mipsI,mipsII,mipsIII,mipsIV:
110*vr5000:
15232df4
FCE		 111// start-sanitize-vr4320
112*vr4320:
113// end-sanitize-vr4320
90ad43b2
AC		 114// start-sanitize-vr5400
115*vr5400:
116// end-sanitize-vr5400
f2b30012
AC		 117// start-sanitize-r5900
118*r5900:
119// end-sanitize-r5900
120*r3900:
121// start-sanitize-tx19
122*tx19:
123// end-sanitize-tx19
124{
055ee297 125 ALU32_BEGIN (GPR[RS]);
f2b30012 126 ALU32_ADD (EXTEND16 (IMMEDIATE));
055ee297 127 ALU32_END (GPR[RT]);
f2b30012
AC		 128}
129
130
c0a4c3ba
AC		 131
132:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
133{
134 signed32 temp = GPR[rs] + EXTEND16 (immediate);
135 GPR[rt] = EXTEND32 (temp);
136}
137
f2b30012 138001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
ebcfd86a 139"addu r<RT>, r<RS>, <IMMEDIATE>"
23850e92
JL		 140*mipsI,mipsII,mipsIII,mipsIV:
141*vr5000:
15232df4
FCE		 142// start-sanitize-vr4320
143*vr4320:
144// end-sanitize-vr4320
90ad43b2
AC		 145// start-sanitize-vr5400
146*vr5400:
147// end-sanitize-vr5400
f2b30012
AC		 148// start-sanitize-r5900
149*r5900:
150// end-sanitize-r5900
151*r3900:
152// start-sanitize-tx19
153*tx19:
154// end-sanitize-tx19
155{
c0a4c3ba 156 do_addiu (SD_, RS, RT, IMMEDIATE);
f2b30012
AC		 157}
158
159
c0a4c3ba
AC		 160
161:function:::void:do_addu:int rs, int rt, int rd
162{
163 signed32 temp = GPR[rs] + GPR[rt];
164 GPR[rd] = EXTEND32 (temp);
165}
166
f2b30012 167000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
ebcfd86a 168"addu r<RD>, r<RS>, r<RT>"
23850e92
JL		 169*mipsI,mipsII,mipsIII,mipsIV:
170*vr5000:
15232df4
FCE		 171// start-sanitize-vr4320
172*vr4320:
173// end-sanitize-vr4320
90ad43b2
AC		 174// start-sanitize-vr5400
175*vr5400:
176// end-sanitize-vr5400
f2b30012
AC		 177// start-sanitize-r5900
178*r5900:
179// end-sanitize-r5900
180*r3900:
181// start-sanitize-tx19
182*tx19:
183// end-sanitize-tx19
184{
c0a4c3ba 185 do_addu (SD_, RS, RT, RD);
f2b30012
AC		 186}
187
188
c0a4c3ba
AC		 189
190:function:::void:do_and:int rs, int rt, int rd
191{
192 GPR[rd] = GPR[rs] & GPR[rt];
193}
194
f2b30012
AC		 195000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
196"and r<RD>, r<RS>, r<RT>"
23850e92
JL		 197*mipsI,mipsII,mipsIII,mipsIV:
198*vr5000:
15232df4
FCE		 199// start-sanitize-vr4320
200*vr4320:
201// end-sanitize-vr4320
90ad43b2
AC		 202// start-sanitize-vr5400
203*vr5400:
204// end-sanitize-vr5400
f2b30012
AC		 205// start-sanitize-r5900
206*r5900:
207// end-sanitize-r5900
208*r3900:
209// start-sanitize-tx19
210*tx19:
211// end-sanitize-tx19
212{
c0a4c3ba 213 do_and (SD_, RS, RT, RD);
f2b30012
AC		 214}
215
216
c0a4c3ba 217
f2b30012 218001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
23850e92
JL		 219"and r<RT>, r<RS>, <IMMEDIATE>"
220*mipsI,mipsII,mipsIII,mipsIV:
221*vr5000:
15232df4
FCE		 222// start-sanitize-vr4320
223*vr4320:
224// end-sanitize-vr4320
90ad43b2
AC		 225// start-sanitize-vr5400
226*vr5400:
227// end-sanitize-vr5400
f2b30012
AC		 228// start-sanitize-r5900
229*r5900:
230// end-sanitize-r5900
231*r3900:
232// start-sanitize-tx19
233*tx19:
234// end-sanitize-tx19
235{
055ee297 236 GPR[RT] = GPR[RS] & IMMEDIATE;
f2b30012
AC		 237}
238
239
c0a4c3ba 240
f2b30012 241000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
7ce8b917 242"beq r<RS>, r<RT>, <OFFSET>"
23850e92
JL		 243*mipsI,mipsII,mipsIII,mipsIV:
244*vr5000:
15232df4
FCE		 245// start-sanitize-vr4320
246*vr4320:
247// end-sanitize-vr4320
90ad43b2
AC		 248// start-sanitize-vr5400
249*vr5400:
250// end-sanitize-vr5400
f2b30012
AC		 251// start-sanitize-r5900
252*r5900:
253// end-sanitize-r5900
254*r3900:
255// start-sanitize-tx19
256*tx19:
257// end-sanitize-tx19
258{
055ee297 259 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 260 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
261 DELAY_SLOT (NIA + offset);
f2b30012
AC		 262}
263
264
c0a4c3ba 265
f2b30012
AC		 266010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
267"beql r<RS>, r<RT>, <OFFSET>"
268*mipsII:
269*mipsIII:
270*mipsIV:
23850e92 271*vr5000:
15232df4
FCE		 272// start-sanitize-vr4320
273*vr4320:
274// end-sanitize-vr4320
90ad43b2
AC		 275// start-sanitize-vr5400
276*vr5400:
277// end-sanitize-vr5400
f2b30012
AC		 278// start-sanitize-r5900
279*r5900:
280// end-sanitize-r5900
281*r3900:
282// start-sanitize-tx19
283*tx19:
284// end-sanitize-tx19
285{
055ee297 286 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 287 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
288 DELAY_SLOT (NIA + offset);
055ee297 289 else
49a76833 290 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 291}
292
293
c0a4c3ba 294
f2b30012
AC		 295000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
296"bgez r<RS>, <OFFSET>"
23850e92
JL		 297*mipsI,mipsII,mipsIII,mipsIV:
298*vr5000:
15232df4
FCE		 299// start-sanitize-vr4320
300*vr4320:
301// end-sanitize-vr4320
90ad43b2
AC		 302// start-sanitize-vr5400
303*vr5400:
304// end-sanitize-vr5400
f2b30012
AC		 305// start-sanitize-r5900
306*r5900:
307// end-sanitize-r5900
308*r3900:
309// start-sanitize-tx19
310*tx19:
311// end-sanitize-tx19
312{
055ee297 313 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 314 if ((signed_word) GPR[RS] >= 0)
315 DELAY_SLOT (NIA + offset);
f2b30012
AC		 316}
317
318
c0a4c3ba 319
f2b30012
AC		 320000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
321"bgezal r<RS>, <OFFSET>"
23850e92
JL		 322*mipsI,mipsII,mipsIII,mipsIV:
323*vr5000:
15232df4
FCE		 324// start-sanitize-vr4320
325*vr4320:
326// end-sanitize-vr4320
90ad43b2
AC		 327// start-sanitize-vr5400
328*vr5400:
329// end-sanitize-vr5400
f2b30012
AC		 330// start-sanitize-r5900
331*r5900:
332// end-sanitize-r5900
333*r3900:
334// start-sanitize-tx19
335*tx19:
336// end-sanitize-tx19
337{
055ee297
AC		 338 address_word offset = EXTEND16 (OFFSET) << 2;
339 RA = (CIA + 8);
030843d7
AC		 340 if ((signed_word) GPR[RS] >= 0)
341 DELAY_SLOT (NIA + offset);
f2b30012
AC		 342}
343
344
c0a4c3ba 345
f2b30012
AC		 346000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
347"bgezall r<RS>, <OFFSET>"
348*mipsII:
349*mipsIII:
350*mipsIV:
23850e92 351*vr5000:
15232df4
FCE		 352// start-sanitize-vr4320
353*vr4320:
354// end-sanitize-vr4320
90ad43b2
AC		 355// start-sanitize-vr5400
356*vr5400:
357// end-sanitize-vr5400
f2b30012
AC		 358// start-sanitize-r5900
359*r5900:
360// end-sanitize-r5900
361*r3900:
362// start-sanitize-tx19
363*tx19:
364// end-sanitize-tx19
365{
055ee297
AC		 366 address_word offset = EXTEND16 (OFFSET) << 2;
367 RA = (CIA + 8);
f2b30012
AC		 368 /* NOTE: The branch occurs AFTER the next instruction has been
369 executed */
030843d7
AC		 370 if ((signed_word) GPR[RS] >= 0)
371 DELAY_SLOT (NIA + offset);
f2b30012 372 else
49a76833 373 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 374}
375
376
c0a4c3ba 377
f2b30012
AC		 378000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
379"bgezl r<RS>, <OFFSET>"
380*mipsII:
381*mipsIII:
382*mipsIV:
23850e92 383*vr5000:
15232df4
FCE		 384// start-sanitize-vr4320
385*vr4320:
386// end-sanitize-vr4320
90ad43b2
AC		 387// start-sanitize-vr5400
388*vr5400:
389// end-sanitize-vr5400
f2b30012
AC		 390// start-sanitize-r5900
391*r5900:
392// end-sanitize-r5900
393*r3900:
394// start-sanitize-tx19
395*tx19:
396// end-sanitize-tx19
397{
055ee297 398 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 399 if ((signed_word) GPR[RS] >= 0)
400 DELAY_SLOT (NIA + offset);
f2b30012 401 else
49a76833 402 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 403}
404
405
c0a4c3ba 406
f2b30012
AC		 407000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
408"bgtz r<RS>, <OFFSET>"
23850e92
JL		 409*mipsI,mipsII,mipsIII,mipsIV:
410*vr5000:
15232df4
FCE		 411// start-sanitize-vr4320
412*vr4320:
413// end-sanitize-vr4320
90ad43b2
AC		 414// start-sanitize-vr5400
415*vr5400:
416// end-sanitize-vr5400
f2b30012
AC		 417// start-sanitize-r5900
418*r5900:
419// end-sanitize-r5900
420*r3900:
421// start-sanitize-tx19
422*tx19:
423// end-sanitize-tx19
424{
055ee297 425 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 426 if ((signed_word) GPR[RS] > 0)
427 DELAY_SLOT (NIA + offset);
f2b30012
AC		 428}
429
430
c0a4c3ba 431
f2b30012
AC		 432010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
433"bgtzl r<RS>, <OFFSET>"
434*mipsII:
435*mipsIII:
436*mipsIV:
23850e92 437*vr5000:
15232df4
FCE		 438// start-sanitize-vr4320
439*vr4320:
440// end-sanitize-vr4320
90ad43b2
AC		 441// start-sanitize-vr5400
442*vr5400:
443// end-sanitize-vr5400
f2b30012
AC		 444// start-sanitize-r5900
445*r5900:
446// end-sanitize-r5900
447*r3900:
448// start-sanitize-tx19
449*tx19:
450// end-sanitize-tx19
451{
055ee297 452 address_word offset = EXTEND16 (OFFSET) << 2;
f2b30012
AC		 453 /* NOTE: The branch occurs AFTER the next instruction has been
454 executed */
030843d7
AC		 455 if ((signed_word) GPR[RS] > 0)
456 DELAY_SLOT (NIA + offset);
f2b30012 457 else
49a76833 458 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 459}
460
461
c0a4c3ba 462
f2b30012
AC		 463000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
464"blez r<RS>, <OFFSET>"
23850e92
JL		 465*mipsI,mipsII,mipsIII,mipsIV:
466*vr5000:
15232df4
FCE		 467// start-sanitize-vr4320
468*vr4320:
469// end-sanitize-vr4320
90ad43b2
AC		 470// start-sanitize-vr5400
471*vr5400:
472// end-sanitize-vr5400
f2b30012
AC		 473// start-sanitize-r5900
474*r5900:
475// end-sanitize-r5900
476*r3900:
477// start-sanitize-tx19
478*tx19:
479// end-sanitize-tx19
480{
055ee297 481 address_word offset = EXTEND16 (OFFSET) << 2;
f2b30012
AC		 482 /* NOTE: The branch occurs AFTER the next instruction has been
483 executed */
030843d7
AC		 484 if ((signed_word) GPR[RS] <= 0)
485 DELAY_SLOT (NIA + offset);
f2b30012
AC		 486}
487
488
c0a4c3ba 489
f2b30012
AC		 490010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
491"bgezl r<RS>, <OFFSET>"
492*mipsII:
493*mipsIII:
494*mipsIV:
23850e92 495*vr5000:
15232df4
FCE		 496// start-sanitize-vr4320
497*vr4320:
498// end-sanitize-vr4320
90ad43b2
AC		 499// start-sanitize-vr5400
500*vr5400:
501// end-sanitize-vr5400
f2b30012
AC		 502// start-sanitize-r5900
503*r5900:
504// end-sanitize-r5900
505*r3900:
506// start-sanitize-tx19
507*tx19:
508// end-sanitize-tx19
509{
055ee297 510 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 511 if ((signed_word) GPR[RS] <= 0)
512 DELAY_SLOT (NIA + offset);
f2b30012 513 else
49a76833 514 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 515}
516
517
c0a4c3ba 518
f2b30012
AC		 519000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
520"bltz r<RS>, <OFFSET>"
23850e92
JL		 521*mipsI,mipsII,mipsIII,mipsIV:
522*vr5000:
15232df4
FCE		 523// start-sanitize-vr4320
524*vr4320:
525// end-sanitize-vr4320
90ad43b2
AC		 526// start-sanitize-vr5400
527*vr5400:
528// end-sanitize-vr5400
f2b30012
AC		 529// start-sanitize-r5900
530*r5900:
531// end-sanitize-r5900
532*r3900:
533// start-sanitize-tx19
534*tx19:
535// end-sanitize-tx19
536{
055ee297 537 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 538 if ((signed_word) GPR[RS] < 0)
539 DELAY_SLOT (NIA + offset);
f2b30012
AC		 540}
541
542
c0a4c3ba 543
f2b30012
AC		 544000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
545"bltzal r<RS>, <OFFSET>"
23850e92
JL		 546*mipsI,mipsII,mipsIII,mipsIV:
547*vr5000:
15232df4
FCE		 548// start-sanitize-vr4320
549*vr4320:
550// end-sanitize-vr4320
90ad43b2
AC		 551// start-sanitize-vr5400
552*vr5400:
553// end-sanitize-vr5400
f2b30012
AC		 554// start-sanitize-r5900
555*r5900:
556// end-sanitize-r5900
557*r3900:
558// start-sanitize-tx19
559*tx19:
560// end-sanitize-tx19
561{
055ee297
AC		 562 address_word offset = EXTEND16 (OFFSET) << 2;
563 RA = (CIA + 8);
f2b30012
AC		 564 /* NOTE: The branch occurs AFTER the next instruction has been
565 executed */
030843d7
AC		 566 if ((signed_word) GPR[RS] < 0)
567 DELAY_SLOT (NIA + offset);
f2b30012
AC		 568}
569
570
c0a4c3ba 571
f2b30012
AC		 572000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
573"bltzall r<RS>, <OFFSET>"
574*mipsII:
575*mipsIII:
576*mipsIV:
23850e92 577*vr5000:
15232df4
FCE		 578// start-sanitize-vr4320
579*vr4320:
580// end-sanitize-vr4320
90ad43b2
AC		 581// start-sanitize-vr5400
582*vr5400:
583// end-sanitize-vr5400
f2b30012
AC		 584// start-sanitize-r5900
585*r5900:
586// end-sanitize-r5900
587*r3900:
588// start-sanitize-tx19
589*tx19:
590// end-sanitize-tx19
591{
055ee297
AC		 592 address_word offset = EXTEND16 (OFFSET) << 2;
593 RA = (CIA + 8);
030843d7
AC		 594 if ((signed_word) GPR[RS] < 0)
595 DELAY_SLOT (NIA + offset);
f2b30012 596 else
49a76833 597 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 598}
599
600
c0a4c3ba 601
f2b30012
AC		 602000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
603"bltzl r<RS>, <OFFSET>"
604*mipsII:
605*mipsIII:
606*mipsIV:
23850e92 607*vr5000:
15232df4
FCE		 608// start-sanitize-vr4320
609*vr4320:
610// end-sanitize-vr4320
90ad43b2
AC		 611// start-sanitize-vr5400
612*vr5400:
613// end-sanitize-vr5400
f2b30012
AC		 614// start-sanitize-r5900
615*r5900:
616// end-sanitize-r5900
617*r3900:
618// start-sanitize-tx19
619*tx19:
620// end-sanitize-tx19
621{
055ee297 622 address_word offset = EXTEND16 (OFFSET) << 2;
f2b30012
AC		 623 /* NOTE: The branch occurs AFTER the next instruction has been
624 executed */
030843d7
AC		 625 if ((signed_word) GPR[RS] < 0)
626 DELAY_SLOT (NIA + offset);
f2b30012 627 else
49a76833 628 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 629}
630
631
c0a4c3ba 632
f2b30012
AC		 633000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
634"bne r<RS>, r<RT>, <OFFSET>"
23850e92
JL		 635*mipsI,mipsII,mipsIII,mipsIV:
636*vr5000:
15232df4
FCE		 637// start-sanitize-vr4320
638*vr4320:
639// end-sanitize-vr4320
90ad43b2
AC		 640// start-sanitize-vr5400
641*vr5400:
642// end-sanitize-vr5400
f2b30012
AC		 643// start-sanitize-r5900
644*r5900:
645// end-sanitize-r5900
646*r3900:
647// start-sanitize-tx19
648*tx19:
649// end-sanitize-tx19
650{
055ee297 651 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 652 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
653 DELAY_SLOT (NIA + offset);
f2b30012
AC		 654}
655
656
c0a4c3ba 657
f2b30012
AC		 658010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
659"bnel r<RS>, r<RT>, <OFFSET>"
660*mipsII:
661*mipsIII:
662*mipsIV:
23850e92 663*vr5000:
15232df4
FCE		 664// start-sanitize-vr4320
665*vr4320:
666// end-sanitize-vr4320
90ad43b2
AC		 667// start-sanitize-vr5400
668*vr5400:
669// end-sanitize-vr5400
f2b30012
AC		 670// start-sanitize-r5900
671*r5900:
672// end-sanitize-r5900
673*r3900:
674// start-sanitize-tx19
675*tx19:
676// end-sanitize-tx19
677{
085c1cb9 678 address_word offset = EXTEND16 (OFFSET) << 2;
030843d7
AC		 679 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
680 DELAY_SLOT (NIA + offset);
f2b30012 681 else
49a76833 682 NULLIFY_NEXT_INSTRUCTION ();
f2b30012
AC		 683}
684
685
c0a4c3ba 686
49a6eed5 687000000,20.CODE,001101:SPECIAL:32::BREAK
f2b30012 688"break"
23850e92
JL		 689*mipsI,mipsII,mipsIII,mipsIV:
690*vr5000:
15232df4
FCE		 691// start-sanitize-vr4320
692*vr4320:
693// end-sanitize-vr4320
90ad43b2
AC		 694// start-sanitize-vr5400
695*vr5400:
696// end-sanitize-vr5400
f2b30012
AC		 697// start-sanitize-r5900
698*r5900:
699// end-sanitize-r5900
700*r3900:
701// start-sanitize-tx19
702*tx19:
703// end-sanitize-tx19
704{
055ee297 705 SignalException(BreakPoint, instruction_0);
f2b30012
AC		 706}
707
708
c0a4c3ba 709
49a6eed5 7100100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
f2b30012 711"cop<ZZ> <COP_FUN>"
23850e92 712*mipsI,mipsII,mipsIII,mipsIV:
f2b30012
AC		 713// start-sanitize-r5900
714*r5900:
715// end-sanitize-r5900
716*r3900:
717// start-sanitize-tx19
718*tx19:
719// end-sanitize-tx19
720{
085c1cb9 721 DecodeCoproc (instruction_0);
f2b30012
AC		 722}
723
724
c0a4c3ba 725
f2b30012
AC		 726000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
727"dadd r<RD>, r<RS>, r<RT>"
728*mipsIII:
729*mipsIV:
23850e92 730*vr5000:
15232df4
FCE		 731// start-sanitize-vr4320
732*vr4320:
733// end-sanitize-vr4320
90ad43b2
AC		 734// start-sanitize-vr5400
735*vr5400:
736// end-sanitize-vr5400
f2b30012
AC		 737// start-sanitize-r5900
738*r5900:
739// end-sanitize-r5900
f2b30012
AC		 740// start-sanitize-tx19
741*tx19:
742// end-sanitize-tx19
743{
ca6f76d1 744 /* this check's for overflow */
055ee297
AC		 745 ALU64_BEGIN (GPR[RS]);
746 ALU64_ADD (GPR[RT]);
ca6f76d1 747 ALU64_END (GPR[RD]);
f2b30012
AC		 748}
749
750
c0a4c3ba 751
f2b30012
AC		 752011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
753"daddi r<RT>, r<RS>, <IMMEDIATE>"
754*mipsIII:
755*mipsIV:
23850e92 756*vr5000:
15232df4
FCE		 757// start-sanitize-vr4320
758*vr4320:
759// end-sanitize-vr4320
90ad43b2
AC		 760// start-sanitize-vr5400
761*vr5400:
762// end-sanitize-vr5400
f2b30012
AC		 763// start-sanitize-r5900
764*r5900:
765// end-sanitize-r5900
f2b30012
AC		 766// start-sanitize-tx19
767*tx19:
768// end-sanitize-tx19
769{
055ee297 770 ALU64_BEGIN (GPR[RS]);
f2b30012 771 ALU64_ADD (EXTEND16 (IMMEDIATE));
055ee297 772 ALU64_END (GPR[RT]);
f2b30012
AC		 773}
774
775
c0a4c3ba
AC		 776
777:function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
778{
779 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
780}
781
f2b30012
AC		 782011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
783"daddu r<RT>, r<RS>, <IMMEDIATE>"
784*mipsIII:
785*mipsIV:
23850e92 786*vr5000:
15232df4
FCE		 787// start-sanitize-vr4320
788*vr4320:
789// end-sanitize-vr4320
90ad43b2
AC		 790// start-sanitize-vr5400
791*vr5400:
792// end-sanitize-vr5400
f2b30012
AC		 793// start-sanitize-r5900
794*r5900:
795// end-sanitize-r5900
f2b30012
AC		 796// start-sanitize-tx19
797*tx19:
798// end-sanitize-tx19
799{
c0a4c3ba 800 do_daddiu (SD_, RS, RT, IMMEDIATE);
f2b30012
AC		 801}
802
803
c0a4c3ba
AC		 804
805:function:::void:do_daddu:int rs, int rt, int rd
806{
807 GPR[rd] = GPR[rs] + GPR[rt];
808}
809
f2b30012
AC		 810000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
811"daddu r<RD>, r<RS>, r<RT>"
812*mipsIII:
813*mipsIV:
23850e92 814*vr5000:
15232df4
FCE		 815// start-sanitize-vr4320
816*vr4320:
817// end-sanitize-vr4320
90ad43b2
AC		 818// start-sanitize-vr5400
819*vr5400:
820// end-sanitize-vr5400
f2b30012
AC		 821// start-sanitize-r5900
822*r5900:
823// end-sanitize-r5900
f2b30012
AC		 824// start-sanitize-tx19
825*tx19:
826// end-sanitize-tx19
827{
c0a4c3ba 828 do_daddu (SD_, RS, RT, RD);
f2b30012
AC		 829}
830
831
c0a4c3ba
AC		 832
833:function:64::void:do_ddiv:int rs, int rt
f2b30012
AC		 834{
835 CHECKHILO ("Division");
836 {
c0a4c3ba
AC		 837 signed64 n = GPR[rs];
838 signed64 d = GPR[rt];
f2b30012
AC		 839 if (d == 0)
840 {
841 LO = SIGNED64 (0x8000000000000000);
842 HI = 0;
843 }
844 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
845 {
846 LO = SIGNED64 (0x8000000000000000);
847 HI = 0;
848 }
849 else
850 {
851 LO = (n / d);
852 HI = (n % d);
853 }
854 }
855}
856
c0a4c3ba
AC		 857000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
858"ddiv r<RS>, r<RT>"
f2b30012
AC		 859*mipsIII:
860*mipsIV:
23850e92 861*vr5000:
15232df4
FCE		 862// start-sanitize-vr4320
863*vr4320:
864// end-sanitize-vr4320
90ad43b2
AC		 865// start-sanitize-vr5400
866*vr5400:
867// end-sanitize-vr5400
c0a4c3ba
AC		 868// start-sanitize-r5900
869*r5900:
870// end-sanitize-r5900
f2b30012
AC		 871// start-sanitize-tx19
872*tx19:
873// end-sanitize-tx19
c0a4c3ba
AC		 874{
875 do_ddiv (SD_, RS, RT);
876}
877
878
879
880:function:64::void:do_ddivu:int rs, int rt
f2b30012
AC		 881{
882 CHECKHILO ("Division");
883 {
c0a4c3ba
AC		 884 unsigned64 n = GPR[rs];
885 unsigned64 d = GPR[rt];
f2b30012
AC		 886 if (d == 0)
887 {
888 LO = SIGNED64 (0x8000000000000000);
889 HI = 0;
890 }
891 else
892 {
893 LO = (n / d);
894 HI = (n % d);
895 }
896 }
897}
898
c0a4c3ba
AC		 899000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
900"ddivu r<RS>, r<RT>"
901*mipsIII:
902*mipsIV:
23850e92 903*vr5000:
15232df4
FCE		 904// start-sanitize-vr4320
905*vr4320:
906// end-sanitize-vr4320
90ad43b2
AC		 907// start-sanitize-vr5400
908*vr5400:
909// end-sanitize-vr5400
f2b30012
AC		 910// start-sanitize-tx19
911*tx19:
912// end-sanitize-tx19
c0a4c3ba
AC		 913{
914 do_ddivu (SD_, RS, RT);
915}
916
917
918
919:function:::void:do_div:int rs, int rt
f2b30012
AC		 920{
921 CHECKHILO("Division");
922 {
c0a4c3ba
AC		 923 signed32 n = GPR[rs];
924 signed32 d = GPR[rt];
f2b30012
AC		 925 if (d == 0)
926 {
927 LO = EXTEND32 (0x80000000);
928 HI = EXTEND32 (0);
929 }
ca6f76d1 930 else if (n == SIGNED32 (0x80000000) && d == -1)
f2b30012
AC		 931 {
932 LO = EXTEND32 (0x80000000);
933 HI = EXTEND32 (0);
934 }
935 else
936 {
937 LO = EXTEND32 (n / d);
938 HI = EXTEND32 (n % d);
939 }
940 }
941}
942
c0a4c3ba
AC		 943000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
944"div r<RS>, r<RT>"
23850e92
JL		 945*mipsI,mipsII,mipsIII,mipsIV:
946*vr5000:
15232df4
FCE		 947// start-sanitize-vr4320
948*vr4320:
949// end-sanitize-vr4320
90ad43b2
AC		 950// start-sanitize-vr5400
951*vr5400:
952// end-sanitize-vr5400
f2b30012
AC		 953// start-sanitize-r5900
954*r5900:
955// end-sanitize-r5900
956*r3900:
957// start-sanitize-tx19
958*tx19:
959// end-sanitize-tx19
c0a4c3ba
AC		 960{
961 do_div (SD_, RS, RT);
962}
963
964
965
966:function:::void:do_divu:int rs, int rt
f2b30012
AC		 967{
968 CHECKHILO ("Division");
969 {
c0a4c3ba
AC		 970 unsigned32 n = GPR[rs];
971 unsigned32 d = GPR[rt];
f2b30012
AC		 972 if (d == 0)
973 {
974 LO = EXTEND32 (0x80000000);
975 HI = EXTEND32 (0);
976 }
977 else
978 {
979 LO = EXTEND32 (n / d);
980 HI = EXTEND32 (n % d);
981 }
982 }
983}
984
c0a4c3ba
AC		 985000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
986"divu r<RS>, r<RT>"
987*mipsI,mipsII,mipsIII,mipsIV:
988*vr5000:
989// start-sanitize-vr4320
990*vr4320:
991// end-sanitize-vr4320
992// start-sanitize-vr5400
993*vr5400:
994// end-sanitize-vr5400
995// start-sanitize-r5900
996*r5900:
997// end-sanitize-r5900
998*r3900:
999// start-sanitize-tx19
1000*tx19:
1001// end-sanitize-tx19
1002{
1003 do_divu (SD_, RS, RT);
1004}
1005
f2b30012 1006
c0a4c3ba
AC		 1007
1008:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
23850e92
JL		 1009{
1010 unsigned64 lo;
1011 unsigned64 hi;
1012 unsigned64 m00;
1013 unsigned64 m01;
1014 unsigned64 m10;
1015 unsigned64 m11;
1016 unsigned64 mid;
1017 int sign;
1018 unsigned64 op1 = GPR[rs];
1019 unsigned64 op2 = GPR[rt];
1020 CHECKHILO ("Multiplication");
1021 /* make signed multiply unsigned */
1022 sign = 0;
1023 if (signed_p)
1024 {
1025 if (op1 < 0)
1026 {
1027 op1 = - op1;
1028 ++sign;
1029 }
1030 if (op2 < 0)
1031 {
1032 op2 = - op2;
1033 ++sign;
1034 }
1035 }
1036 /* multuply out the 4 sub products */
1037 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1038 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1039 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1040 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1041 /* add the products */
1042 mid = ((unsigned64) VH4_8 (m00)
1043 + (unsigned64) VL4_8 (m10)
1044 + (unsigned64) VL4_8 (m01));
1045 lo = U8_4 (mid, m00);
1046 hi = (m11
1047 + (unsigned64) VH4_8 (mid)
1048 + (unsigned64) VH4_8 (m01)
1049 + (unsigned64) VH4_8 (m10));
1050 /* fix the sign */
1051 if (sign & 1)
1052 {
1053 lo = -lo;
1054 if (lo == 0)
1055 hi = -hi;
1056 else
1057 hi = -hi - 1;
1058 }
1059 /* save the result HI/LO (and a gpr) */
1060 LO = lo;
1061 HI = hi;
1062 if (rd != 0)
1063 GPR[rd] = lo;
1064}
1065
c0a4c3ba
AC		 1066:function:::void:do_dmult:int rs, int rt, int rd
1067{
1068 do_dmultx (SD_, rs, rt, rd, 1);
1069}
23850e92 1070
f2b30012
AC		 1071000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1072"dmult r<RS>, r<RT>"
23850e92 1073*mipsIII,mipsIV:
f2b30012
AC		 1074// start-sanitize-tx19
1075*tx19:
1076// end-sanitize-tx19
15232df4
FCE		 1077// start-sanitize-vr4320
1078*vr4320:
1079// end-sanitize-vr4320
f2b30012 1080{
c0a4c3ba 1081 do_dmult (SD_, RS, RT, 0);
f2b30012
AC		 1082}
1083
23850e92
JL		 1084000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1085"dmult r<RS>, r<RT>":RD == 0
1086"dmult r<RD>, r<RS>, r<RT>"
1087*vr5000:
90ad43b2
AC		 1088// start-sanitize-vr5400
1089*vr5400:
1090// end-sanitize-vr5400
23850e92 1091{
c0a4c3ba 1092 do_dmult (SD_, RS, RT, RD);
23850e92
JL		 1093}
1094
1095
1096
c0a4c3ba
AC		 1097:function:::void:do_dmultu:int rs, int rt, int rd
1098{
1099 do_dmultx (SD_, rs, rt, rd, 0);
1100}
1101
23850e92
JL		 1102000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1103"dmultu r<RS>, r<RT>"
1104*mipsIII,mipsIV:
f2b30012
AC		 1105// start-sanitize-tx19
1106*tx19:
1107// end-sanitize-tx19
15232df4
FCE		 1108// start-sanitize-vr4320
1109*vr4320:
1110// end-sanitize-vr4320
f2b30012 1111{
c0a4c3ba 1112 do_dmultu (SD_, RS, RT, 0);
23850e92
JL		 1113}
1114
1115000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1116"dmultu r<RD>, r<RS>, r<RT>":RD == 0
1117"dmultu r<RS>, r<RT>"
1118*vr5000:
1119// start-sanitize-vr5400
1120*vr5400:
1121// end-sanitize-vr5400
1122{
c0a4c3ba 1123 do_dmultu (SD_, RS, RT, RD);
f2b30012
AC		 1124}
1125
1126
23850e92 1127
055ee297 112800000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
01b9cd49 1129"dsll r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1130*mipsIII:
1131*mipsIV:
23850e92 1132*vr5000:
15232df4
FCE		 1133// start-sanitize-vr4320
1134*vr4320:
1135// end-sanitize-vr4320
90ad43b2
AC		 1136// start-sanitize-vr5400
1137*vr5400:
1138// end-sanitize-vr5400
f2b30012
AC		 1139// start-sanitize-r5900
1140*r5900:
1141// end-sanitize-r5900
f2b30012
AC		 1142// start-sanitize-tx19
1143*tx19:
1144// end-sanitize-tx19
1145{
01b9cd49 1146 int s = SHIFT;
055ee297 1147 GPR[RD] = GPR[RT] << s;
f2b30012
AC		 1148}
1149
1150
055ee297 115100000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
01b9cd49 1152"dsll32 r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1153*mipsIII:
1154*mipsIV:
23850e92 1155*vr5000:
15232df4
FCE		 1156// start-sanitize-vr4320
1157*vr4320:
1158// end-sanitize-vr4320
90ad43b2
AC		 1159// start-sanitize-vr5400
1160*vr5400:
1161// end-sanitize-vr5400
f2b30012
AC		 1162// start-sanitize-r5900
1163*r5900:
1164// end-sanitize-r5900
f2b30012
AC		 1165// start-sanitize-tx19
1166*tx19:
1167// end-sanitize-tx19
1168{
01b9cd49 1169 int s = 32 + SHIFT;
055ee297 1170 GPR[RD] = GPR[RT] << s;
f2b30012
AC		 1171}
1172
1173
c0a4c3ba 1174
f2b30012
AC		 1175000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1176"dsllv r<RD>, r<RT>, r<RS>"
1177*mipsIII:
1178*mipsIV:
23850e92 1179*vr5000:
15232df4
FCE		 1180// start-sanitize-vr4320
1181*vr4320:
1182// end-sanitize-vr4320
90ad43b2
AC		 1183// start-sanitize-vr5400
1184*vr5400:
1185// end-sanitize-vr5400
f2b30012
AC		 1186// start-sanitize-r5900
1187*r5900:
1188// end-sanitize-r5900
f2b30012
AC		 1189// start-sanitize-tx19
1190*tx19:
1191// end-sanitize-tx19
1192{
055ee297
AC		 1193 int s = MASKED64 (GPR[RS], 5, 0);
1194 GPR[RD] = GPR[RT] << s;
f2b30012
AC		 1195}
1196
1197
c0a4c3ba 1198
055ee297 119900000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
01b9cd49 1200"dsra r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1201*mipsIII:
1202*mipsIV:
23850e92 1203*vr5000:
15232df4
FCE		 1204// start-sanitize-vr4320
1205*vr4320:
1206// end-sanitize-vr4320
90ad43b2
AC		 1207// start-sanitize-vr5400
1208*vr5400:
1209// end-sanitize-vr5400
f2b30012
AC		 1210// start-sanitize-r5900
1211*r5900:
1212// end-sanitize-r5900
f2b30012
AC		 1213// start-sanitize-tx19
1214*tx19:
1215// end-sanitize-tx19
1216{
01b9cd49 1217 int s = SHIFT;
055ee297 1218 GPR[RD] = ((signed64) GPR[RT]) >> s;
f2b30012
AC		 1219}
1220
1221
055ee297 122200000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
01b9cd49 1223"dsra32 r<RT>, r<RD>, <SHIFT>"
f2b30012
AC		 1224*mipsIII:
1225*mipsIV:
23850e92 1226*vr5000:
15232df4
FCE		 1227// start-sanitize-vr4320
1228*vr4320:
1229// end-sanitize-vr4320
90ad43b2
AC		 1230// start-sanitize-vr5400
1231*vr5400:
1232// end-sanitize-vr5400
f2b30012
AC		 1233// start-sanitize-r5900
1234*r5900:
1235// end-sanitize-r5900
f2b30012
AC		 1236// start-sanitize-tx19
1237*tx19:
1238// end-sanitize-tx19
1239{
01b9cd49 1240 int s = 32 + SHIFT;
055ee297 1241 GPR[RD] = ((signed64) GPR[RT]) >> s;
f2b30012
AC		 1242}
1243
1244
c0a4c3ba
AC		 1245:function:::void:do_srav:int rs, int rt, int rd
1246{
1247 int s = MASKED64 (GPR[rs], 5, 0);
1248 GPR[rd] = ((signed64) GPR[rt]) >> s;
1249}
1250
f2b30012
AC		 1251000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1252"dsra32 r<RT>, r<RD>, r<RS>"
1253*mipsIII:
1254*mipsIV:
23850e92 1255*vr5000:
15232df4
FCE		 1256// start-sanitize-vr4320
1257*vr4320:
1258// end-sanitize-vr4320
90ad43b2
AC		 1259// start-sanitize-vr5400
1260*vr5400:
1261// end-sanitize-vr5400
f2b30012
AC		 1262// start-sanitize-r5900
1263*r5900:
1264// end-sanitize-r5900
f2b30012
AC		 1265// start-sanitize-tx19
1266*tx19:
1267// end-sanitize-tx19
1268{
c0a4c3ba 1269 do_srav (SD_, RS, RT, RD);
f2b30012
AC		 1270}
1271
1272
055ee297 127300000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
01b9cd49 1274"dsrav r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1275*mipsIII:
1276*mipsIV:
23850e92 1277*vr5000:
15232df4
FCE		 1278// start-sanitize-vr4320
1279*vr4320:
1280// end-sanitize-vr4320
90ad43b2
AC		 1281// start-sanitize-vr5400
1282*vr5400:
1283// end-sanitize-vr5400
f2b30012
AC		 1284// start-sanitize-r5900
1285*r5900:
1286// end-sanitize-r5900
f2b30012
AC		 1287// start-sanitize-tx19
1288*tx19:
1289// end-sanitize-tx19
1290{
01b9cd49 1291 int s = SHIFT;
055ee297 1292 GPR[RD] = (unsigned64) GPR[RT] >> s;
f2b30012
AC		 1293}
1294
1295
055ee297 129600000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
01b9cd49 1297"dsrl32 r<RD>, r<RT>, <SHIFT>"
f2b30012
AC		 1298*mipsIII:
1299*mipsIV:
23850e92 1300*vr5000:
15232df4
FCE		 1301// start-sanitize-vr4320
1302*vr4320:
1303// end-sanitize-vr4320
90ad43b2
AC		 1304// start-sanitize-vr5400
1305*vr5400:
1306// end-sanitize-vr5400
f2b30012
AC		 1307// start-sanitize-r5900
1308*r5900:
1309// end-sanitize-r5900
f2b30012
AC		 1310// start-sanitize-tx19
1311*tx19:
1312// end-sanitize-tx19
1313{
01b9cd49 1314 int s = 32 + SHIFT;
055ee297 1315 GPR[RD] = (unsigned64) GPR[RT] >> s;
f2b30012
AC		 1316}
1317
1318
1319000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1320"dsrl32 r<RD>, r<RT>, r<RS>"
1321*mipsIII:
1322*mipsIV:
23850e92 1323*vr5000:
15232df4
FCE		 1324// start-sanitize-vr4320
1325*vr4320:
1326// end-sanitize-vr4320
90ad43b2
AC		 1327// start-sanitize-vr5400
1328*vr5400:
1329// end-sanitize-vr5400
f2b30012
AC		 1330// start-sanitize-r5900
1331*r5900:
1332// end-sanitize-r5900
f2b30012
AC		 1333// start-sanitize-tx19
1334*tx19:
1335// end-sanitize-tx19
1336{
055ee297
AC		 1337 int s = MASKED64 (GPR[RS], 5, 0);
1338 GPR[RD] = (unsigned64) GPR[RT] >> s;
f2b30012
AC		 1339}
1340
1341
1342000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1343"dsub r<RD>, r<RS>, r<RT>"
1344*mipsIII:
1345*mipsIV:
23850e92 1346*vr5000:
15232df4
FCE		 1347// start-sanitize-vr4320
1348*vr4320:
1349// end-sanitize-vr4320
90ad43b2
AC		 1350// start-sanitize-vr5400
1351*vr5400:
1352// end-sanitize-vr5400
f2b30012
AC		 1353// start-sanitize-r5900
1354*r5900:
1355// end-sanitize-r5900
f2b30012
AC		 1356// start-sanitize-tx19
1357*tx19:
1358// end-sanitize-tx19
1359{
055ee297
AC		 1360 ALU64_BEGIN (GPR[RS]);
1361 ALU64_SUB (GPR[RT]);
1362 ALU64_END (GPR[RD]);
f2b30012
AC		 1363}
1364
1365
c0a4c3ba
AC		 1366:function:::void:do_dsubu:int rs, int rt, int rd
1367{
1368 GPR[rd] = GPR[rs] - GPR[rt];
1369}
1370
f2b30012
AC		 1371000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1372"dsubu r<RD>, r<RS>, r<RT>"
1373*mipsIII:
1374*mipsIV:
23850e92 1375*vr5000:
15232df4
FCE		 1376// start-sanitize-vr4320
1377*vr4320:
1378// end-sanitize-vr4320
90ad43b2
AC		 1379// start-sanitize-vr5400
1380*vr5400:
1381// end-sanitize-vr5400
f2b30012
AC		 1382// start-sanitize-r5900
1383*r5900:
1384// end-sanitize-r5900
f2b30012
AC		 1385// start-sanitize-tx19
1386*tx19:
1387// end-sanitize-tx19
1388{
c0a4c3ba 1389 do_dsubu (SD_, RS, RT, RD);
f2b30012
AC		 1390}
1391
1392
1393000010,26.INSTR_INDEX:NORMAL:32::J
1394"j <INSTR_INDEX>"
23850e92
JL		 1395*mipsI,mipsII,mipsIII,mipsIV:
1396*vr5000:
15232df4
FCE		 1397// start-sanitize-vr4320
1398*vr4320:
1399// end-sanitize-vr4320
90ad43b2
AC		 1400// start-sanitize-vr5400
1401*vr5400:
1402// end-sanitize-vr5400
f2b30012
AC		 1403// start-sanitize-r5900
1404*r5900:
1405// end-sanitize-r5900
1406*r3900:
1407// start-sanitize-tx19
1408*tx19:
1409// end-sanitize-tx19
1410{
49a76833 1411 /* NOTE: The region used is that of the delay slot NIA and NOT the
f2b30012 1412 current instruction */
49a76833
AC		 1413 address_word region = (NIA & MASK (63, 28));
1414 DELAY_SLOT (region | (INSTR_INDEX << 2));
f2b30012
AC		 1415}
1416
1417
1418000011,26.INSTR_INDEX:NORMAL:32::JAL
1419"jal <INSTR_INDEX>"
23850e92
JL		 1420*mipsI,mipsII,mipsIII,mipsIV:
1421*vr5000:
15232df4
FCE		 1422// start-sanitize-vr4320
1423*vr4320:
1424// end-sanitize-vr4320
90ad43b2
AC		 1425// start-sanitize-vr5400
1426*vr5400:
1427// end-sanitize-vr5400
f2b30012
AC		 1428// start-sanitize-r5900
1429*r5900:
1430// end-sanitize-r5900
1431*r3900:
1432// start-sanitize-tx19
1433*tx19:
1434// end-sanitize-tx19
1435{
1436 /* NOTE: The region used is that of the delay slot and NOT the
1437 current instruction */
49a76833 1438 address_word region = (NIA & MASK (63, 28));
055ee297 1439 GPR[31] = CIA + 8;
49a76833 1440 DELAY_SLOT (region | (INSTR_INDEX << 2));
f2b30012
AC		 1441}
1442
1443
1444000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1445"jalr r<RS>":RD == 31
1446"jalr r<RD>, r<RS>"
23850e92
JL		 1447*mipsI,mipsII,mipsIII,mipsIV:
1448*vr5000:
15232df4
FCE		 1449// start-sanitize-vr4320
1450*vr4320:
1451// end-sanitize-vr4320
90ad43b2
AC		 1452// start-sanitize-vr5400
1453*vr5400:
1454// end-sanitize-vr5400
f2b30012
AC		 1455// start-sanitize-r5900
1456*r5900:
1457// end-sanitize-r5900
1458*r3900:
1459// start-sanitize-tx19
1460*tx19:
1461// end-sanitize-tx19
1462{
055ee297
AC		 1463 address_word temp = GPR[RS];
1464 GPR[RD] = CIA + 8;
49a76833 1465 DELAY_SLOT (temp);
f2b30012
AC		 1466}
1467
1468
1469000000,5.RS,000000000000000001000:SPECIAL:32::JR
1470"jr r<RS>"
23850e92
JL		 1471*mipsI,mipsII,mipsIII,mipsIV:
1472*vr5000:
15232df4
FCE		 1473// start-sanitize-vr4320
1474*vr4320:
1475// end-sanitize-vr4320
90ad43b2
AC		 1476// start-sanitize-vr5400
1477*vr5400:
1478// end-sanitize-vr5400
f2b30012
AC		 1479// start-sanitize-r5900
1480*r5900:
1481// end-sanitize-r5900
1482*r3900:
1483// start-sanitize-tx19
1484*tx19:
1485// end-sanitize-tx19
1486{
49a76833 1487 DELAY_SLOT (GPR[RS]);
f2b30012
AC		 1488}
1489
1490
ebcfd86a 1491:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
a48e8c8d 1492{
ebcfd86a
FCE		 1493 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1494 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1495 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1496 unsigned int byte;
a48e8c8d
AC		 1497 address_word paddr;
1498 int uncached;
ebcfd86a
FCE		 1499 unsigned64 memval;
1500 address_word vaddr;
1501
1502 vaddr = base + offset;
1503 if ((vaddr & access) != 0)
1504 SignalExceptionAddressLoad ();
1505 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1506 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1507 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1508 byte = ((vaddr & mask) ^ bigendiancpu);
1509 return (memval >> (8 * byte));
a48e8c8d
AC		 1510}
1511
ebcfd86a 1512
f2b30012
AC		 1513100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1514"lb r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 1515*mipsI,mipsII,mipsIII,mipsIV:
1516*vr5000:
15232df4
FCE		 1517// start-sanitize-vr4320
1518*vr4320:
1519// end-sanitize-vr4320
90ad43b2
AC		 1520// start-sanitize-vr5400
1521*vr5400:
1522// end-sanitize-vr5400
f2b30012
AC		 1523// start-sanitize-r5900
1524*r5900:
1525// end-sanitize-r5900
1526*r3900:
1527// start-sanitize-tx19
1528*tx19:
1529// end-sanitize-tx19
1530{
ebcfd86a 1531 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
f2b30012
AC		 1532}
1533
1534
1535100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1536"lbu r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 1537*mipsI,mipsII,mipsIII,mipsIV:
1538*vr5000:
15232df4
FCE		 1539// start-sanitize-vr4320
1540*vr4320:
1541// end-sanitize-vr4320
90ad43b2
AC		 1542// start-sanitize-vr5400
1543*vr5400:
1544// end-sanitize-vr5400
f2b30012
AC		 1545// start-sanitize-r5900
1546*r5900:
1547// end-sanitize-r5900
1548*r3900:
1549// start-sanitize-tx19
1550*tx19:
1551// end-sanitize-tx19
1552{
ebcfd86a 1553 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
f2b30012
AC		 1554}
1555
1556
1557110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1558"ld r<RT>, <OFFSET>(r<BASE>)"
1559*mipsIII:
1560*mipsIV:
23850e92 1561*vr5000:
15232df4
FCE		 1562// start-sanitize-vr4320
1563*vr4320:
1564// end-sanitize-vr4320
90ad43b2
AC		 1565// start-sanitize-vr5400
1566*vr5400:
1567// end-sanitize-vr5400
f2b30012
AC		 1568// start-sanitize-r5900
1569*r5900:
1570// end-sanitize-r5900
f2b30012
AC		 1571// start-sanitize-tx19
1572*tx19:
1573// end-sanitize-tx19
1574{
ebcfd86a 1575 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
f2b30012
AC		 1576}
1577
1578
49a6eed5 15791101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
f2b30012
AC		 1580"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1581*mipsII:
1582*mipsIII:
1583*mipsIV:
23850e92 1584*vr5000:
15232df4
FCE		 1585// start-sanitize-vr4320
1586*vr4320:
1587// end-sanitize-vr4320
90ad43b2
AC		 1588// start-sanitize-vr5400
1589*vr5400:
1590// end-sanitize-vr5400
f2b30012
AC		 1591*r3900:
1592// start-sanitize-tx19
1593*tx19:
1594// end-sanitize-tx19
1595{
ebcfd86a 1596 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
f2b30012
AC		 1597}
1598
1599
15232df4
FCE		 1600
1601
f2b30012
AC		 1602011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1603"ldl r<RT>, <OFFSET>(r<BASE>)"
1604*mipsIII:
1605*mipsIV:
23850e92 1606*vr5000:
15232df4
FCE		 1607// start-sanitize-vr4320
1608*vr4320:
1609// end-sanitize-vr4320
90ad43b2
AC		 1610// start-sanitize-vr5400
1611*vr5400:
1612// end-sanitize-vr5400
f2b30012
AC		 1613// start-sanitize-r5900
1614*r5900:
1615// end-sanitize-r5900
f2b30012
AC		 1616// start-sanitize-tx19
1617*tx19:
1618// end-sanitize-tx19
1619{
ebcfd86a 1620 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 1621}
1622
1623
1624011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1625"ldr r<RT>, <OFFSET>(r<BASE>)"
1626*mipsIII:
1627*mipsIV:
23850e92 1628*vr5000:
15232df4
FCE		 1629// start-sanitize-vr4320
1630*vr4320:
1631// end-sanitize-vr4320
90ad43b2
AC		 1632// start-sanitize-vr5400
1633*vr5400:
1634// end-sanitize-vr5400
f2b30012
AC		 1635// start-sanitize-r5900
1636*r5900:
1637// end-sanitize-r5900
f2b30012
AC		 1638// start-sanitize-tx19
1639*tx19:
1640// end-sanitize-tx19
1641{
ebcfd86a 1642 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 1643}
1644
1645
1646100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1647"lh r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 1648*mipsI,mipsII,mipsIII,mipsIV:
1649*vr5000:
15232df4
FCE		 1650// start-sanitize-vr4320
1651*vr4320:
1652// end-sanitize-vr4320
90ad43b2
AC		 1653// start-sanitize-vr5400
1654*vr5400:
1655// end-sanitize-vr5400
f2b30012
AC		 1656// start-sanitize-r5900
1657*r5900:
1658// end-sanitize-r5900
1659*r3900:
1660// start-sanitize-tx19
1661*tx19:
1662// end-sanitize-tx19
1663{
ebcfd86a 1664 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
f2b30012
AC		 1665}
1666
1667
1668100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1669"lhu r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 1670*mipsI,mipsII,mipsIII,mipsIV:
1671*vr5000:
15232df4
FCE		 1672// start-sanitize-vr4320
1673*vr4320:
1674// end-sanitize-vr4320
90ad43b2
AC		 1675// start-sanitize-vr5400
1676*vr5400:
1677// end-sanitize-vr5400
f2b30012
AC		 1678// start-sanitize-r5900
1679*r5900:
1680// end-sanitize-r5900
1681*r3900:
1682// start-sanitize-tx19
1683*tx19:
1684// end-sanitize-tx19
1685{
ebcfd86a 1686 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
f2b30012
AC		 1687}
1688
1689
1690110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1691"ll r<RT>, <OFFSET>(r<BASE>)"
1692*mipsII:
1693*mipsIII:
1694*mipsIV:
23850e92 1695*vr5000:
15232df4
FCE		 1696// start-sanitize-vr4320
1697*vr4320:
1698// end-sanitize-vr4320
90ad43b2
AC		 1699// start-sanitize-vr5400
1700*vr5400:
1701// end-sanitize-vr5400
f2b30012
AC		 1702// start-sanitize-r5900
1703*r5900:
1704// end-sanitize-r5900
f2b30012
AC		 1705// start-sanitize-tx19
1706*tx19:
1707// end-sanitize-tx19
1708{
1709 unsigned32 instruction = instruction_0;
055ee297
AC		 1710 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1711 int destreg = ((instruction >> 16) & 0x0000001F);
1712 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1713 {
49a76833
AC		 1714 address_word vaddr = ((unsigned64)op1 + offset);
1715 address_word paddr;
f2b30012
AC		 1716 int uncached;
1717 if ((vaddr & 3) != 0)
055ee297 1718 SignalExceptionAddressLoad();
f2b30012
AC		 1719 else
1720 {
1721 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1722 {
1723 unsigned64 memval = 0;
1724 unsigned64 memval1 = 0;
1725 unsigned64 mask = 0x7;
1726 unsigned int shift = 2;
055ee297
AC		 1727 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1728 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1729 unsigned int byte;
f2b30012
AC		 1730 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1731 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1732 byte = ((vaddr & mask) ^ (bigend << shift));
1733 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1734 LLBIT = 1;
1735 }
1736 }
1737 }
1738}
1739
1740
1741110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1742"lld r<RT>, <OFFSET>(r<BASE>)"
1743*mipsIII:
1744*mipsIV:
23850e92 1745*vr5000:
15232df4
FCE		 1746// start-sanitize-vr4320
1747*vr4320:
1748// end-sanitize-vr4320
90ad43b2
AC		 1749// start-sanitize-vr5400
1750*vr5400:
1751// end-sanitize-vr5400
f2b30012
AC		 1752// start-sanitize-r5900
1753*r5900:
1754// end-sanitize-r5900
f2b30012
AC		 1755// start-sanitize-tx19
1756*tx19:
1757// end-sanitize-tx19
1758{
1759 unsigned32 instruction = instruction_0;
055ee297
AC		 1760 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1761 int destreg = ((instruction >> 16) & 0x0000001F);
1762 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 1763 {
49a76833
AC		 1764 address_word vaddr = ((unsigned64)op1 + offset);
1765 address_word paddr;
f2b30012
AC		 1766 int uncached;
1767 if ((vaddr & 7) != 0)
055ee297 1768 SignalExceptionAddressLoad();
f2b30012
AC		 1769 else
1770 {
1771 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1772 {
1773 unsigned64 memval = 0;
1774 unsigned64 memval1 = 0;
f2b30012
AC		 1775 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1776 GPR[destreg] = memval;
1777 LLBIT = 1;
1778 }
1779 }
1780 }
1781}
1782
1783
1784001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1785"lui r<RT>, <IMMEDIATE>"
23850e92
JL		 1786*mipsI,mipsII,mipsIII,mipsIV:
1787*vr5000:
15232df4
FCE		 1788// start-sanitize-vr4320
1789*vr4320:
1790// end-sanitize-vr4320
90ad43b2
AC		 1791// start-sanitize-vr5400
1792*vr5400:
1793// end-sanitize-vr5400
f2b30012
AC		 1794// start-sanitize-r5900
1795*r5900:
1796// end-sanitize-r5900
1797*r3900:
1798// start-sanitize-tx19
1799*tx19:
1800// end-sanitize-tx19
1801{
055ee297 1802 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
f2b30012
AC		 1803}
1804
1805
1806100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1807"lw r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 1808*mipsI,mipsII,mipsIII,mipsIV:
1809*vr5000:
15232df4
FCE		 1810// start-sanitize-vr4320
1811*vr4320:
1812// end-sanitize-vr4320
90ad43b2
AC		 1813// start-sanitize-vr5400
1814*vr5400:
1815// end-sanitize-vr5400
f2b30012
AC		 1816// start-sanitize-r5900
1817*r5900:
1818// end-sanitize-r5900
1819*r3900:
1820// start-sanitize-tx19
1821*tx19:
1822// end-sanitize-tx19
1823{
ebcfd86a 1824 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
f2b30012
AC		 1825}
1826
1827
49a6eed5 18281100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
f2b30012 1829"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 1830*mipsI,mipsII,mipsIII,mipsIV:
1831*vr5000:
15232df4
FCE		 1832// start-sanitize-vr4320
1833*vr4320:
1834// end-sanitize-vr4320
90ad43b2
AC		 1835// start-sanitize-vr5400
1836*vr5400:
1837// end-sanitize-vr5400
f2b30012
AC		 1838// start-sanitize-r5900
1839*r5900:
1840// end-sanitize-r5900
1841*r3900:
1842// start-sanitize-tx19
1843*tx19:
1844// end-sanitize-tx19
1845{
ebcfd86a
FCE		 1846 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1847}
1848
1849
1850:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1851{
1852 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1853 address_word reverseendian = (ReverseEndian ? -1 : 0);
1854 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1855 unsigned int byte;
1856 address_word paddr;
1857 int uncached;
1858 unsigned64 memval;
1859 address_word vaddr;
1860
1861 vaddr = base + offset;
1862 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1863 paddr = (paddr ^ (reverseendian & mask));
1864 if (BigEndianMem == 0)
1865 paddr = paddr & ~access;
1866 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1867 LoadMemory (&memval, NULL, uncached, byte & access, paddr, vaddr, isDATA, isREAL);
1868 /* printf ("ll: 0x%08lx %d@0x%08lx 0x%08lx\n",
1869 (long) vaddr, byte, (long) paddr, (long) memval); */
1870 if ((byte & ~access) == 0)
1871 {
1872 int bits = 8 * (access - byte);
1873 unsigned_word screen = LSMASK (bits - 1, 0);
1874 rt &= screen;
1875 rt |= ((memval << bits) & ~screen);
1876 }
1877 else
1878 {
1879 unsigned_word screen = LSMASK (8 * (access - (byte & access)) - 1, 0);
1880 rt &= screen;
1881 rt |= ((memval >> (8 * (mask - byte))) & ~screen);
1882 }
1883 return rt;
f2b30012
AC		 1884}
1885
1886
1887100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1888"lwl r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 1889*mipsI,mipsII,mipsIII,mipsIV:
1890*vr5000:
15232df4
FCE		 1891// start-sanitize-vr4320
1892*vr4320:
1893// end-sanitize-vr4320
90ad43b2
AC		 1894// start-sanitize-vr5400
1895*vr5400:
1896// end-sanitize-vr5400
f2b30012
AC		 1897// start-sanitize-r5900
1898*r5900:
1899// end-sanitize-r5900
1900*r3900:
1901// start-sanitize-tx19
1902*tx19:
1903// end-sanitize-tx19
1904{
ebcfd86a
FCE		 1905 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
1906}
1907
1908
1909:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1910{
1911 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1912 address_word reverseendian = (ReverseEndian ? -1 : 0);
1913 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1914 unsigned int byte;
1915 address_word paddr;
1916 int uncached;
1917 unsigned64 memval;
1918 address_word vaddr;
1919
1920 vaddr = base + offset;
1921 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1922 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1923 paddr = (paddr ^ (reverseendian & mask));
1924 if (BigEndianMem != 0)
1925 paddr = paddr & ~access;
1926 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1927 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
1928 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1929 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1930 (long) paddr, byte, (long) paddr, (long) memval); */
f2b30012 1931 {
ebcfd86a
FCE		 1932 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1933 rt &= ~screen;
1934 rt |= (memval >> (8 * byte)) & screen;
f2b30012 1935 }
ebcfd86a 1936 return rt;
f2b30012
AC		 1937}
1938
1939
1940100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1941"lwr r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 1942*mipsI,mipsII,mipsIII,mipsIV:
1943*vr5000:
15232df4
FCE		 1944// start-sanitize-vr4320
1945*vr4320:
1946// end-sanitize-vr4320
90ad43b2
AC		 1947// start-sanitize-vr5400
1948*vr5400:
1949// end-sanitize-vr5400
f2b30012
AC		 1950// start-sanitize-r5900
1951*r5900:
1952// end-sanitize-r5900
1953*r3900:
1954// start-sanitize-tx19
1955*tx19:
1956// end-sanitize-tx19
1957{
ebcfd86a 1958 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
f2b30012
AC		 1959}
1960
1961
1962100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
1963"lwu r<RT>, <OFFSET>(r<BASE>)"
1964*mipsIII:
1965*mipsIV:
23850e92 1966*vr5000:
15232df4
FCE		 1967// start-sanitize-vr4320
1968*vr4320:
1969// end-sanitize-vr4320
90ad43b2
AC		 1970// start-sanitize-vr5400
1971*vr5400:
1972// end-sanitize-vr5400
f2b30012
AC		 1973// start-sanitize-r5900
1974*r5900:
1975// end-sanitize-r5900
f2b30012
AC		 1976// start-sanitize-tx19
1977*tx19:
1978// end-sanitize-tx19
1979{
ebcfd86a 1980 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
f2b30012
AC		 1981}
1982
1983
c0a4c3ba
AC		 1984:function:::void:do_mfhi:int rd
1985{
1986 GPR[rd] = HI;
1987#if 0
1988 HIACCESS = 3;
1989#endif
1990}
1991
f2b30012
AC		 1992000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1993"mfhi r<RD>"
23850e92
JL		 1994*mipsI,mipsII,mipsIII,mipsIV:
1995*vr5000:
15232df4
FCE		 1996// start-sanitize-vr4320
1997*vr4320:
1998// end-sanitize-vr4320
90ad43b2
AC		 1999// start-sanitize-vr5400
2000*vr5400:
2001// end-sanitize-vr5400
f2b30012
AC		 2002// start-sanitize-r5900
2003*r5900:
2004// end-sanitize-r5900
2005*r3900:
2006// start-sanitize-tx19
2007*tx19:
2008// end-sanitize-tx19
2009{
c0a4c3ba
AC		 2010 do_mfhi (SD_, RD);
2011}
2012
2013
2014
2015:function:::void:do_mflo:int rd
2016{
2017 GPR[rd] = LO;
030843d7 2018#if 0
c0a4c3ba 2019 LOACCESS = 3; /* 3rd instruction will be safe */
030843d7 2020#endif
f2b30012
AC		 2021}
2022
f2b30012
AC		 2023000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2024"mflo r<RD>"
23850e92
JL		 2025*mipsI,mipsII,mipsIII,mipsIV:
2026*vr5000:
15232df4
FCE		 2027// start-sanitize-vr4320
2028*vr4320:
2029// end-sanitize-vr4320
90ad43b2
AC		 2030// start-sanitize-vr5400
2031*vr5400:
2032// end-sanitize-vr5400
f2b30012
AC		 2033// start-sanitize-r5900
2034*r5900:
2035// end-sanitize-r5900
2036*r3900:
2037// start-sanitize-tx19
2038*tx19:
2039// end-sanitize-tx19
2040{
c0a4c3ba 2041 do_mflo (SD_, RD);
f2b30012
AC		 2042}
2043
2044
c0a4c3ba 2045
f2b30012
AC		 2046000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2047"movn r<RD>, r<RS>, r<RT>"
2048*mipsIV:
23850e92 2049*vr5000:
15232df4
FCE		 2050// start-sanitize-vr4320
2051*vr4320:
2052// end-sanitize-vr4320
90ad43b2
AC		 2053// start-sanitize-vr5400
2054*vr5400:
2055// end-sanitize-vr5400
f2b30012
AC		 2056// start-sanitize-r5900
2057*r5900:
2058// end-sanitize-r5900
2059{
055ee297
AC		 2060 if (GPR[RT] != 0)
2061 GPR[RD] = GPR[RS];
f2b30012
AC		 2062}
2063
2064
c0a4c3ba 2065
f2b30012
AC		 2066000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2067"movz r<RD>, r<RS>, r<RT>"
2068*mipsIV:
23850e92 2069*vr5000:
15232df4
FCE		 2070// start-sanitize-vr4320
2071*vr4320:
2072// end-sanitize-vr4320
90ad43b2
AC		 2073// start-sanitize-vr5400
2074*vr5400:
2075// end-sanitize-vr5400
f2b30012
AC		 2076// start-sanitize-r5900
2077*r5900:
2078// end-sanitize-r5900
2079{
055ee297
AC		 2080 if (GPR[RT] == 0)
2081 GPR[RD] = GPR[RS];
f2b30012
AC		 2082}
2083
2084
c0a4c3ba 2085
f2b30012
AC		 2086000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2087"mthi r<RS>"
23850e92
JL		 2088*mipsI,mipsII,mipsIII,mipsIV:
2089*vr5000:
15232df4
FCE		 2090// start-sanitize-vr4320
2091*vr4320:
2092// end-sanitize-vr4320
90ad43b2
AC		 2093// start-sanitize-vr5400
2094*vr5400:
2095// end-sanitize-vr5400
f2b30012
AC		 2096// start-sanitize-r5900
2097*r5900:
2098// end-sanitize-r5900
2099*r3900:
2100// start-sanitize-tx19
2101*tx19:
2102// end-sanitize-tx19
2103{
030843d7 2104#if 0
f2b30012 2105 if (HIACCESS != 0)
055ee297 2106 sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
030843d7 2107#endif
055ee297 2108 HI = GPR[RS];
030843d7 2109#if 0
f2b30012 2110 HIACCESS = 3; /* 3rd instruction will be safe */
030843d7 2111#endif
f2b30012
AC		 2112}
2113
2114
c0a4c3ba 2115
f2b30012
AC		 2116000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2117"mtlo r<RS>"
23850e92
JL		 2118*mipsI,mipsII,mipsIII,mipsIV:
2119*vr5000:
15232df4
FCE		 2120// start-sanitize-vr4320
2121*vr4320:
2122// end-sanitize-vr4320
90ad43b2
AC		 2123// start-sanitize-vr5400
2124*vr5400:
2125// end-sanitize-vr5400
f2b30012
AC		 2126// start-sanitize-r5900
2127*r5900:
2128// end-sanitize-r5900
2129*r3900:
2130// start-sanitize-tx19
2131*tx19:
2132// end-sanitize-tx19
2133{
030843d7 2134#if 0
f2b30012 2135 if (LOACCESS != 0)
055ee297 2136 sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
030843d7 2137#endif
055ee297 2138 LO = GPR[RS];
030843d7 2139#if 0
f2b30012 2140 LOACCESS = 3; /* 3rd instruction will be safe */
030843d7 2141#endif
f2b30012
AC		 2142}
2143
2144
c0a4c3ba
AC		 2145
2146:function:::void:do_mult:int rs, int rt, int rd
2147{
2148 signed64 prod;
2149 CHECKHILO ("Multiplication");
2150 prod = (((signed64)(signed32) GPR[rs])
2151 * ((signed64)(signed32) GPR[rt]));
2152 LO = EXTEND32 (VL4_8 (prod));
2153 HI = EXTEND32 (VH4_8 (prod));
2154 if (rd != 0)
2155 GPR[rd] = LO;
2156}
2157
030843d7 2158000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
f2b30012 2159"mult r<RS>, r<RT>"
23850e92 2160*mipsI,mipsII,mipsIII,mipsIV:
15232df4
FCE		 2161// start-sanitize-vr4320
2162*vr4320:
2163// end-sanitize-vr4320
030843d7 2164{
c0a4c3ba 2165 do_mult (SD_, RS, RT, 0);
030843d7 2166}
15232df4
FCE		 2167
2168
030843d7
AC		 2169000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2170"mult r<RD>, r<RS>, r<RT>"
23850e92 2171*vr5000:
90ad43b2
AC		 2172// start-sanitize-vr5400
2173*vr5400:
2174// end-sanitize-vr5400
f2b30012
AC		 2175// start-sanitize-r5900
2176*r5900:
2177// end-sanitize-r5900
2178*r3900:
2179// start-sanitize-tx19
2180*tx19:
2181// end-sanitize-tx19
2182{
c0a4c3ba
AC		 2183 do_mult (SD_, RS, RT, RD);
2184}
2185
2186
2187:function:::void:do_multu:int rs, int rt, int rd
2188{
2189 unsigned64 prod;
f2b30012 2190 CHECKHILO ("Multiplication");
c0a4c3ba
AC		 2191 prod = (((unsigned64)(unsigned32) GPR[rs])
2192 * ((unsigned64)(unsigned32) GPR[rt]));
f2b30012
AC		 2193 LO = EXTEND32 (VL4_8 (prod));
2194 HI = EXTEND32 (VH4_8 (prod));
c0a4c3ba
AC		 2195 if (rd != 0)
2196 GPR[rd] = LO;
f2b30012
AC		 2197}
2198
030843d7 2199000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
f2b30012 2200"multu r<RS>, r<RT>"
23850e92 2201*mipsI,mipsII,mipsIII,mipsIV:
15232df4
FCE		 2202// start-sanitize-vr4320
2203*vr4320:
2204// end-sanitize-vr4320
030843d7 2205{
c0a4c3ba 2206 do_multu (SD_, RS, RT, 0);
030843d7 2207}
c0a4c3ba 2208
030843d7
AC		 2209000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2210"multu r<RD>, r<RS>, r<RT>"
23850e92 2211*vr5000:
90ad43b2
AC		 2212// start-sanitize-vr5400
2213*vr5400:
2214// end-sanitize-vr5400
f2b30012
AC		 2215// start-sanitize-r5900
2216*r5900:
2217// end-sanitize-r5900
2218*r3900:
2219// start-sanitize-tx19
2220*tx19:
2221// end-sanitize-tx19
2222{
c0a4c3ba 2223 do_multu (SD_, RS, RT, 0);
f2b30012
AC		 2224}
2225
2226
c0a4c3ba
AC		 2227:function:::void:do_nor:int rs, int rt, int rd
2228{
2229 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2230}
2231
f2b30012
AC		 2232000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2233"nor r<RD>, r<RS>, r<RT>"
23850e92
JL		 2234*mipsI,mipsII,mipsIII,mipsIV:
2235*vr5000:
15232df4
FCE		 2236// start-sanitize-vr4320
2237*vr4320:
2238// end-sanitize-vr4320
90ad43b2
AC		 2239// start-sanitize-vr5400
2240*vr5400:
2241// end-sanitize-vr5400
f2b30012
AC		 2242// start-sanitize-r5900
2243*r5900:
2244// end-sanitize-r5900
2245*r3900:
2246// start-sanitize-tx19
2247*tx19:
2248// end-sanitize-tx19
2249{
c0a4c3ba 2250 do_nor (SD_, RS, RT, RD);
f2b30012
AC		 2251}
2252
2253
c0a4c3ba
AC		 2254:function:::void:do_or:int rs, int rt, int rd
2255{
2256 GPR[rd] = (GPR[rs] | GPR[rt]);
2257}
2258
f2b30012
AC		 2259000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2260"or r<RD>, r<RS>, r<RT>"
23850e92
JL		 2261*mipsI,mipsII,mipsIII,mipsIV:
2262*vr5000:
15232df4
FCE		 2263// start-sanitize-vr4320
2264*vr4320:
2265// end-sanitize-vr4320
90ad43b2
AC		 2266// start-sanitize-vr5400
2267*vr5400:
2268// end-sanitize-vr5400
f2b30012
AC		 2269// start-sanitize-r5900
2270*r5900:
2271// end-sanitize-r5900
2272*r3900:
2273// start-sanitize-tx19
2274*tx19:
2275// end-sanitize-tx19
2276{
c0a4c3ba 2277 do_or (SD_, RS, RT, RD);
f2b30012
AC		 2278}
2279
2280
2281001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
055ee297 2282"ori r<RT>, r<RS>, <IMMEDIATE>"
23850e92
JL		 2283*mipsI,mipsII,mipsIII,mipsIV:
2284*vr5000:
15232df4
FCE		 2285// start-sanitize-vr4320
2286*vr4320:
2287// end-sanitize-vr4320
90ad43b2
AC		 2288// start-sanitize-vr5400
2289*vr5400:
2290// end-sanitize-vr5400
f2b30012
AC		 2291// start-sanitize-r5900
2292*r5900:
2293// end-sanitize-r5900
2294*r3900:
2295// start-sanitize-tx19
2296*tx19:
2297// end-sanitize-tx19
2298{
055ee297 2299 GPR[RT] = (GPR[RS] | IMMEDIATE);
f2b30012
AC		 2300}
2301
2302
2303110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2304*mipsIV:
23850e92 2305*vr5000:
15232df4
FCE		 2306// start-sanitize-vr4320
2307*vr4320:
2308// end-sanitize-vr4320
90ad43b2
AC		 2309// start-sanitize-vr5400
2310*vr5400:
2311// end-sanitize-vr5400
f2b30012
AC		 2312// start-sanitize-r5900
2313*r5900:
2314// end-sanitize-r5900
2315{
2316 unsigned32 instruction = instruction_0;
055ee297
AC		 2317 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2318 int hint = ((instruction >> 16) & 0x0000001F);
2319 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2320 {
49a76833
AC		 2321 address_word vaddr = ((unsigned64)op1 + offset);
2322 address_word paddr;
f2b30012
AC		 2323 int uncached;
2324 {
2325 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2326 Prefetch(uncached,paddr,vaddr,isDATA,hint);
2327 }
2328 }
2329}
2330
ebcfd86a
FCE		 2331:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2332{
2333 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2334 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2335 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2336 unsigned int byte;
2337 address_word paddr;
2338 int uncached;
2339 unsigned64 memval;
2340 address_word vaddr;
2341
2342 vaddr = base + offset;
2343 if ((vaddr & access) != 0)
2344 SignalExceptionAddressStore ();
2345 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2346 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2347 byte = ((vaddr & mask) ^ bigendiancpu);
2348 memval = (word << (8 * byte));
2349 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2350}
2351
2352
f2b30012
AC		 2353101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2354"sb r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 2355*mipsI,mipsII,mipsIII,mipsIV:
2356*vr5000:
15232df4
FCE		 2357// start-sanitize-vr4320
2358*vr4320:
2359// end-sanitize-vr4320
90ad43b2
AC		 2360// start-sanitize-vr5400
2361*vr5400:
2362// end-sanitize-vr5400
f2b30012
AC		 2363// start-sanitize-r5900
2364*r5900:
2365// end-sanitize-r5900
2366*r3900:
2367// start-sanitize-tx19
2368*tx19:
2369// end-sanitize-tx19
2370{
ebcfd86a 2371 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 2372}
2373
2374
2375111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2376"sc r<RT>, <OFFSET>(r<BASE>)"
2377*mipsII:
2378*mipsIII:
2379*mipsIV:
23850e92 2380*vr5000:
15232df4
FCE		 2381// start-sanitize-vr4320
2382*vr4320:
2383// end-sanitize-vr4320
90ad43b2
AC		 2384// start-sanitize-vr5400
2385*vr5400:
2386// end-sanitize-vr5400
f2b30012
AC		 2387// start-sanitize-r5900
2388*r5900:
2389// end-sanitize-r5900
f2b30012
AC		 2390// start-sanitize-tx19
2391*tx19:
2392// end-sanitize-tx19
2393{
2394 unsigned32 instruction = instruction_0;
055ee297
AC		 2395 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2396 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2397 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2398 {
49a76833
AC		 2399 address_word vaddr = ((unsigned64)op1 + offset);
2400 address_word paddr;
f2b30012
AC		 2401 int uncached;
2402 if ((vaddr & 3) != 0)
055ee297 2403 SignalExceptionAddressStore();
f2b30012
AC		 2404 else
2405 {
2406 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2407 {
2408 unsigned64 memval = 0;
2409 unsigned64 memval1 = 0;
2410 unsigned64 mask = 0x7;
2411 unsigned int byte;
2412 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2413 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2414 memval = ((unsigned64) op2 << (8 * byte));
2415 if (LLBIT)
2416 {
2417 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2418 }
2419 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2420 }
2421 }
2422 }
2423}
2424
2425
2426111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2427"scd r<RT>, <OFFSET>(r<BASE>)"
2428*mipsIII:
2429*mipsIV:
23850e92 2430*vr5000:
15232df4
FCE		 2431// start-sanitize-vr4320
2432*vr4320:
2433// end-sanitize-vr4320
90ad43b2
AC		 2434// start-sanitize-vr5400
2435*vr5400:
2436// end-sanitize-vr5400
f2b30012
AC		 2437// start-sanitize-r5900
2438*r5900:
2439// end-sanitize-r5900
f2b30012
AC		 2440// start-sanitize-tx19
2441*tx19:
2442// end-sanitize-tx19
2443{
2444 unsigned32 instruction = instruction_0;
055ee297
AC		 2445 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2446 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2447 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 2448 {
49a76833
AC		 2449 address_word vaddr = ((unsigned64)op1 + offset);
2450 address_word paddr;
f2b30012
AC		 2451 int uncached;
2452 if ((vaddr & 7) != 0)
055ee297 2453 SignalExceptionAddressStore();
f2b30012
AC		 2454 else
2455 {
2456 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2457 {
2458 unsigned64 memval = 0;
2459 unsigned64 memval1 = 0;
2460 memval = op2;
2461 if (LLBIT)
2462 {
2463 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2464 }
2465 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2466 }
2467 }
2468 }
2469}
2470
2471
2472111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2473"sd r<RT>, <OFFSET>(r<BASE>)"
2474*mipsIII:
2475*mipsIV:
23850e92 2476*vr5000:
15232df4
FCE		 2477// start-sanitize-vr4320
2478*vr4320:
2479// end-sanitize-vr4320
90ad43b2
AC		 2480// start-sanitize-vr5400
2481*vr5400:
2482// end-sanitize-vr5400
f2b30012
AC		 2483// start-sanitize-r5900
2484*r5900:
2485// end-sanitize-r5900
f2b30012
AC		 2486// start-sanitize-tx19
2487*tx19:
2488// end-sanitize-tx19
ebcfd86a
FCE		 2489{
2490 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
15232df4 2491}
15232df4
FCE		 2492
2493
ebcfd86a
FCE		 24941111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2495"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2496*mipsII:
2497*mipsIII:
2498*mipsIV:
2499*vr5000:
2500// start-sanitize-vr4320
2501*vr4320:
2502// end-sanitize-vr4320
2503// start-sanitize-vr5400
2504*vr5400:
2505// end-sanitize-vr5400
2506// start-sanitize-r5900
2507*r5900:
2508// end-sanitize-r5900
2509// start-sanitize-tx19
2510*tx19:
2511// end-sanitize-tx19
2512{
2513 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2514}
2515
15232df4 2516
f2b30012
AC		 2517101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2518"sdl r<RT>, <OFFSET>(r<BASE>)"
2519*mipsIII:
2520*mipsIV:
23850e92 2521*vr5000:
15232df4
FCE		 2522// start-sanitize-vr4320
2523*vr4320:
2524// end-sanitize-vr4320
90ad43b2
AC		 2525// start-sanitize-vr5400
2526*vr5400:
2527// end-sanitize-vr5400
f2b30012
AC		 2528// start-sanitize-r5900
2529*r5900:
2530// end-sanitize-r5900
f2b30012
AC		 2531// start-sanitize-tx19
2532*tx19:
2533// end-sanitize-tx19
2534{
ebcfd86a 2535 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 2536}
2537
2538
2539101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2540"sdr r<RT>, <OFFSET>(r<BASE>)"
2541*mipsIII:
2542*mipsIV:
23850e92 2543*vr5000:
15232df4
FCE		 2544// start-sanitize-vr4320
2545*vr4320:
2546// end-sanitize-vr4320
90ad43b2
AC		 2547// start-sanitize-vr5400
2548*vr5400:
2549// end-sanitize-vr5400
f2b30012
AC		 2550// start-sanitize-r5900
2551*r5900:
2552// end-sanitize-r5900
f2b30012
AC		 2553// start-sanitize-tx19
2554*tx19:
2555// end-sanitize-tx19
2556{
ebcfd86a 2557 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 2558}
2559
2560
2561101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2562"sh r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 2563*mipsI,mipsII,mipsIII,mipsIV:
2564*vr5000:
15232df4
FCE		 2565// start-sanitize-vr4320
2566*vr4320:
2567// end-sanitize-vr4320
90ad43b2
AC		 2568// start-sanitize-vr5400
2569*vr5400:
2570// end-sanitize-vr5400
f2b30012
AC		 2571// start-sanitize-r5900
2572*r5900:
2573// end-sanitize-r5900
2574*r3900:
2575// start-sanitize-tx19
2576*tx19:
2577// end-sanitize-tx19
2578{
ebcfd86a 2579 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 2580}
2581
2582
c0a4c3ba
AC		 2583:function:::void:do_sll:int rt, int rd, int shift
2584{
2585 unsigned32 temp = (GPR[rt] << shift);
2586 GPR[rd] = EXTEND32 (temp);
2587}
2588
055ee297
AC		 258900000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2590"sll r<RD>, r<RT>, <SHIFT>"
23850e92
JL		 2591*mipsI,mipsII,mipsIII,mipsIV:
2592*vr5000:
15232df4
FCE		 2593// start-sanitize-vr4320
2594*vr4320:
2595// end-sanitize-vr4320
90ad43b2
AC		 2596// start-sanitize-vr5400
2597*vr5400:
2598// end-sanitize-vr5400
f2b30012
AC		 2599// start-sanitize-r5900
2600*r5900:
2601// end-sanitize-r5900
2602*r3900:
2603// start-sanitize-tx19
2604*tx19:
2605// end-sanitize-tx19
2606{
c0a4c3ba 2607 do_sll (SD_, RT, RD, SHIFT);
f2b30012
AC		 2608}
2609
2610
c0a4c3ba
AC		 2611:function:::void:do_sllv:int rs, int rt, int rd
2612{
2613 int s = MASKED (GPR[rs], 4, 0);
2614 unsigned32 temp = (GPR[rt] << s);
2615 GPR[rd] = EXTEND32 (temp);
2616}
2617
055ee297 2618000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
f2b30012 2619"sllv r<RD>, r<RT>, r<RS>"
23850e92
JL		 2620*mipsI,mipsII,mipsIII,mipsIV:
2621*vr5000:
15232df4
FCE		 2622// start-sanitize-vr4320
2623*vr4320:
2624// end-sanitize-vr4320
90ad43b2
AC		 2625// start-sanitize-vr5400
2626*vr5400:
2627// end-sanitize-vr5400
f2b30012
AC		 2628// start-sanitize-r5900
2629*r5900:
2630// end-sanitize-r5900
2631*r3900:
2632// start-sanitize-tx19
2633*tx19:
2634// end-sanitize-tx19
2635{
c0a4c3ba 2636 do_sllv (SD_, RS, RT, RD);
f2b30012
AC		 2637}
2638
2639
c0a4c3ba
AC		 2640:function:::void:do_slt:int rs, int rt, int rd
2641{
2642 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2643}
2644
f2b30012
AC		 2645000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2646"slt r<RD>, r<RS>, r<RT>"
23850e92
JL		 2647*mipsI,mipsII,mipsIII,mipsIV:
2648*vr5000:
15232df4
FCE		 2649// start-sanitize-vr4320
2650*vr4320:
2651// end-sanitize-vr4320
90ad43b2
AC		 2652// start-sanitize-vr5400
2653*vr5400:
2654// end-sanitize-vr5400
f2b30012
AC		 2655// start-sanitize-r5900
2656*r5900:
2657// end-sanitize-r5900
2658*r3900:
2659// start-sanitize-tx19
2660*tx19:
2661// end-sanitize-tx19
2662{
c0a4c3ba 2663 do_slt (SD_, RS, RT, RD);
f2b30012
AC		 2664}
2665
2666
c0a4c3ba
AC		 2667:function:::void:do_slti:int rs, int rt, unsigned16 immediate
2668{
2669 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2670}
2671
f2b30012 2672001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
055ee297 2673"slti r<RT>, r<RS>, <IMMEDIATE>"
23850e92
JL		 2674*mipsI,mipsII,mipsIII,mipsIV:
2675*vr5000:
15232df4
FCE		 2676// start-sanitize-vr4320
2677*vr4320:
2678// end-sanitize-vr4320
90ad43b2
AC		 2679// start-sanitize-vr5400
2680*vr5400:
2681// end-sanitize-vr5400
f2b30012
AC		 2682// start-sanitize-r5900
2683*r5900:
2684// end-sanitize-r5900
2685*r3900:
2686// start-sanitize-tx19
2687*tx19:
2688// end-sanitize-tx19
2689{
c0a4c3ba 2690 do_slti (SD_, RS, RT, IMMEDIATE);
f2b30012
AC		 2691}
2692
2693
c0a4c3ba
AC		 2694:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2695{
2696 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2697}
2698
f2b30012 2699001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
055ee297 2700"sltiu r<RT>, r<RS>, <IMMEDIATE>"
23850e92
JL		 2701*mipsI,mipsII,mipsIII,mipsIV:
2702*vr5000:
15232df4
FCE		 2703// start-sanitize-vr4320
2704*vr4320:
2705// end-sanitize-vr4320
90ad43b2
AC		 2706// start-sanitize-vr5400
2707*vr5400:
2708// end-sanitize-vr5400
f2b30012
AC		 2709// start-sanitize-r5900
2710*r5900:
2711// end-sanitize-r5900
2712*r3900:
2713// start-sanitize-tx19
2714*tx19:
2715// end-sanitize-tx19
2716{
c0a4c3ba
AC		 2717 do_sltiu (SD_, RS, RT, IMMEDIATE);
2718}
2719
2720
2721
2722:function:::void:do_sltu:int rs, int rt, int rd
2723{
2724 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
f2b30012
AC		 2725}
2726
2727000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2728"sltu r<RD>, r<RS>, r<RT>"
23850e92
JL		 2729*mipsI,mipsII,mipsIII,mipsIV:
2730*vr5000:
15232df4
FCE		 2731// start-sanitize-vr4320
2732*vr4320:
2733// end-sanitize-vr4320
90ad43b2
AC		 2734// start-sanitize-vr5400
2735*vr5400:
2736// end-sanitize-vr5400
f2b30012
AC		 2737// start-sanitize-r5900
2738*r5900:
2739// end-sanitize-r5900
2740*r3900:
2741// start-sanitize-tx19
2742*tx19:
2743// end-sanitize-tx19
2744{
c0a4c3ba 2745 do_sltiu (SD_, RS, RT, RD);
f2b30012
AC		 2746}
2747
2748
c0a4c3ba
AC		 2749:function:::void:do_sra:int rt, int rd, int shift
2750{
2751 signed32 temp = (signed32) GPR[rt] >> shift;
2752 GPR[rd] = EXTEND32 (temp);
2753}
2754
055ee297
AC		 2755000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2756"sra r<RD>, r<RT>, <SHIFT>"
23850e92
JL		 2757*mipsI,mipsII,mipsIII,mipsIV:
2758*vr5000:
15232df4
FCE		 2759// start-sanitize-vr4320
2760*vr4320:
2761// end-sanitize-vr4320
90ad43b2
AC		 2762// start-sanitize-vr5400
2763*vr5400:
2764// end-sanitize-vr5400
f2b30012
AC		 2765// start-sanitize-r5900
2766*r5900:
2767// end-sanitize-r5900
2768*r3900:
2769// start-sanitize-tx19
2770*tx19:
2771// end-sanitize-tx19
2772{
c0a4c3ba 2773 do_sra (SD_, RT, RD, SHIFT);
f2b30012
AC		 2774}
2775
2776
2777000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2778"srav r<RD>, r<RT>, r<RS>"
23850e92
JL		 2779*mipsI,mipsII,mipsIII,mipsIV:
2780*vr5000:
15232df4
FCE		 2781// start-sanitize-vr4320
2782*vr4320:
2783// end-sanitize-vr4320
90ad43b2
AC		 2784// start-sanitize-vr5400
2785*vr5400:
2786// end-sanitize-vr5400
f2b30012
AC		 2787// start-sanitize-r5900
2788*r5900:
2789// end-sanitize-r5900
2790*r3900:
2791// start-sanitize-tx19
2792*tx19:
2793// end-sanitize-tx19
2794{
055ee297
AC		 2795 int s = MASKED (GPR[RS], 4, 0);
2796 signed32 temp = (signed32) GPR[RT] >> s;
2797 GPR[RD] = EXTEND32 (temp);
f2b30012
AC		 2798}
2799
2800
c0a4c3ba
AC		 2801:function:::void:do_srl:int rt, int rd, int shift
2802{
2803 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2804 GPR[rd] = EXTEND32 (temp);
2805}
2806
055ee297
AC		 2807000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2808"srl r<RD>, r<RT>, <SHIFT>"
23850e92
JL		 2809*mipsI,mipsII,mipsIII,mipsIV:
2810*vr5000:
15232df4
FCE		 2811// start-sanitize-vr4320
2812*vr4320:
2813// end-sanitize-vr4320
90ad43b2
AC		 2814// start-sanitize-vr5400
2815*vr5400:
2816// end-sanitize-vr5400
f2b30012
AC		 2817// start-sanitize-r5900
2818*r5900:
2819// end-sanitize-r5900
2820*r3900:
2821// start-sanitize-tx19
2822*tx19:
2823// end-sanitize-tx19
2824{
c0a4c3ba 2825 do_srl (SD_, RT, RD, SHIFT);
f2b30012
AC		 2826}
2827
2828
c0a4c3ba
AC		 2829:function:::void:do_srlv:int rs, int rt, int rd
2830{
2831 int s = MASKED (GPR[rs], 4, 0);
2832 unsigned32 temp = (unsigned32) GPR[rt] >> s;
2833 GPR[rd] = EXTEND32 (temp);
2834}
2835
f2b30012
AC		 2836000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2837"srlv r<RD>, r<RT>, r<RS>"
23850e92
JL		 2838*mipsI,mipsII,mipsIII,mipsIV:
2839*vr5000:
15232df4
FCE		 2840// start-sanitize-vr4320
2841*vr4320:
2842// end-sanitize-vr4320
90ad43b2
AC		 2843// start-sanitize-vr5400
2844*vr5400:
2845// end-sanitize-vr5400
f2b30012
AC		 2846// start-sanitize-r5900
2847*r5900:
2848// end-sanitize-r5900
2849*r3900:
2850// start-sanitize-tx19
2851*tx19:
2852// end-sanitize-tx19
2853{
c0a4c3ba 2854 do_srlv (SD_, RS, RT, RD);
f2b30012
AC		 2855}
2856
2857
2858000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2859"sub r<RD>, r<RS>, r<RT>"
23850e92
JL		 2860*mipsI,mipsII,mipsIII,mipsIV:
2861*vr5000:
15232df4
FCE		 2862// start-sanitize-vr4320
2863*vr4320:
2864// end-sanitize-vr4320
90ad43b2
AC		 2865// start-sanitize-vr5400
2866*vr5400:
2867// end-sanitize-vr5400
f2b30012
AC		 2868// start-sanitize-r5900
2869*r5900:
2870// end-sanitize-r5900
2871*r3900:
2872// start-sanitize-tx19
2873*tx19:
2874// end-sanitize-tx19
2875{
055ee297
AC		 2876 ALU32_BEGIN (GPR[RS]);
2877 ALU32_SUB (GPR[RT]);
2878 ALU32_END (GPR[RD]);
f2b30012
AC		 2879}
2880
2881
c0a4c3ba
AC		 2882:function:::void:do_subu:int rs, int rt, int rd
2883{
2884 signed32 temp = GPR[rs] - GPR[rt];
2885 GPR[rd] = EXTEND32 (temp);
2886}
2887
f2b30012
AC		 2888000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2889"subu r<RD>, r<RS>, r<RT>"
23850e92
JL		 2890*mipsI,mipsII,mipsIII,mipsIV:
2891*vr5000:
15232df4
FCE		 2892// start-sanitize-vr4320
2893*vr4320:
2894// end-sanitize-vr4320
90ad43b2
AC		 2895// start-sanitize-vr5400
2896*vr5400:
2897// end-sanitize-vr5400
f2b30012
AC		 2898// start-sanitize-r5900
2899*r5900:
2900// end-sanitize-r5900
2901*r3900:
2902// start-sanitize-tx19
2903*tx19:
2904// end-sanitize-tx19
2905{
c0a4c3ba 2906 do_subu (SD_, RS, RT, RD);
f2b30012
AC		 2907}
2908
2909
2910101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2911"sw r<RT>, <OFFSET>(r<BASE>)"
23850e92 2912*mipsI,mipsII,mipsIII,mipsIV:
ebcfd86a
FCE		 2913// start-sanitize-tx19
2914*tx19:
2915// end-sanitize-tx19
2916*r3900:
15232df4
FCE		 2917// start-sanitize-vr4320
2918*vr4320:
2919// end-sanitize-vr4320
ebcfd86a 2920*vr5000:
90ad43b2
AC		 2921// start-sanitize-vr5400
2922*vr5400:
2923// end-sanitize-vr5400
f2b30012
AC		 2924// start-sanitize-r5900
2925*r5900:
2926// end-sanitize-r5900
f2b30012 2927{
ebcfd86a 2928 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 2929}
2930
2931
085c1cb9 29321110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
f2b30012 2933"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 2934*mipsI,mipsII,mipsIII,mipsIV:
2935*vr5000:
15232df4
FCE		 2936// start-sanitize-vr4320
2937*vr4320:
2938// end-sanitize-vr4320
90ad43b2
AC		 2939// start-sanitize-vr5400
2940*vr5400:
2941// end-sanitize-vr5400
f2b30012
AC		 2942*r3900:
2943// start-sanitize-tx19
2944*tx19:
2945// end-sanitize-tx19
2946{
ebcfd86a
FCE		 2947 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
2948}
2949
2950
2951
2952:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2953{
2954 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2955 address_word reverseendian = (ReverseEndian ? -1 : 0);
2956 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2957 unsigned int byte;
2958 address_word paddr;
2959 int uncached;
2960 unsigned64 memval;
2961 address_word vaddr;
2962
2963 vaddr = base + offset;
2964 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2965 paddr = (paddr ^ (reverseendian & mask));
2966 if (BigEndianMem == 0)
2967 paddr = paddr & ~access;
2968 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2969 if ((byte & ~access) == 0)
2970 memval = (rt >> (8 * (access - byte)));
2971 else
2972 memval = (rt << (8 * (mask - byte)));
2973 StoreMemory (uncached, byte & access, memval, NULL, paddr, vaddr, isREAL);
f2b30012
AC		 2974}
2975
2976
2977101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2978"swl r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 2979*mipsI,mipsII,mipsIII,mipsIV:
2980*vr5000:
15232df4
FCE		 2981// start-sanitize-vr4320
2982*vr4320:
2983// end-sanitize-vr4320
90ad43b2
AC		 2984// start-sanitize-vr5400
2985*vr5400:
2986// end-sanitize-vr5400
f2b30012
AC		 2987// start-sanitize-r5900
2988*r5900:
2989// end-sanitize-r5900
2990*r3900:
2991// start-sanitize-tx19
2992*tx19:
2993// end-sanitize-tx19
2994{
ebcfd86a 2995 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 2996}
2997
2998
ebcfd86a
FCE		 2999:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3000{
3001 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3002 address_word reverseendian = (ReverseEndian ? -1 : 0);
3003 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3004 unsigned int byte;
3005 address_word paddr;
3006 int uncached;
3007 unsigned64 memval;
3008 address_word vaddr;
3009
3010 vaddr = base + offset;
3011 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3012 paddr = (paddr ^ (reverseendian & mask));
3013 if (BigEndianMem != 0)
3014 paddr &= ~access;
3015 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3016 memval = (rt << (byte * 8));
3017 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3018}
3019
f2b30012
AC		 3020101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3021"swr r<RT>, <OFFSET>(r<BASE>)"
23850e92
JL		 3022*mipsI,mipsII,mipsIII,mipsIV:
3023*vr5000:
15232df4
FCE		 3024// start-sanitize-vr4320
3025*vr4320:
3026// end-sanitize-vr4320
90ad43b2
AC		 3027// start-sanitize-vr5400
3028*vr5400:
3029// end-sanitize-vr5400
f2b30012
AC		 3030// start-sanitize-r5900
3031*r5900:
3032// end-sanitize-r5900
3033*r3900:
3034// start-sanitize-tx19
3035*tx19:
3036// end-sanitize-tx19
3037{
ebcfd86a 3038 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
f2b30012
AC		 3039}
3040
3041
3042000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3043"sync":STYPE == 0
3044"sync <STYPE>"
3045*mipsII:
3046*mipsIII:
3047*mipsIV:
23850e92 3048*vr5000:
15232df4
FCE		 3049// start-sanitize-vr4320
3050*vr4320:
3051// end-sanitize-vr4320
90ad43b2
AC		 3052// start-sanitize-vr5400
3053*vr5400:
3054// end-sanitize-vr5400
f2b30012
AC		 3055// start-sanitize-r5900
3056*r5900:
3057// end-sanitize-r5900
3058*r3900:
3059// start-sanitize-tx19
3060*tx19:
3061// end-sanitize-tx19
3062{
085c1cb9 3063 SyncOperation (STYPE);
f2b30012
AC		 3064}
3065
3066
3067000000,20.CODE,001100:SPECIAL:32::SYSCALL
3068"syscall <CODE>"
23850e92
JL		 3069*mipsI,mipsII,mipsIII,mipsIV:
3070*vr5000:
15232df4
FCE		 3071// start-sanitize-vr4320
3072*vr4320:
3073// end-sanitize-vr4320
90ad43b2
AC		 3074// start-sanitize-vr5400
3075*vr5400:
3076// end-sanitize-vr5400
f2b30012
AC		 3077// start-sanitize-r5900
3078*r5900:
3079// end-sanitize-r5900
3080*r3900:
3081// start-sanitize-tx19
3082*tx19:
3083// end-sanitize-tx19
3084{
055ee297 3085 SignalException(SystemCall, instruction_0);
f2b30012
AC		 3086}
3087
3088
3089000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3090"teq r<RS>, r<RT>"
3091*mipsII:
3092*mipsIII:
3093*mipsIV:
23850e92 3094*vr5000:
15232df4
FCE		 3095// start-sanitize-vr4320
3096*vr4320:
3097// end-sanitize-vr4320
90ad43b2
AC		 3098// start-sanitize-vr5400
3099*vr5400:
3100// end-sanitize-vr5400
f2b30012
AC		 3101// start-sanitize-r5900
3102*r5900:
3103// end-sanitize-r5900
f2b30012
AC		 3104// start-sanitize-tx19
3105*tx19:
3106// end-sanitize-tx19
3107{
a94c5493 3108 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
055ee297 3109 SignalException(Trap, instruction_0);
f2b30012
AC		 3110}
3111
3112
3113000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3114"teqi r<RS>, <IMMEDIATE>"
3115*mipsII:
3116*mipsIII:
3117*mipsIV:
23850e92 3118*vr5000:
15232df4
FCE		 3119// start-sanitize-vr4320
3120*vr4320:
3121// end-sanitize-vr4320
90ad43b2
AC		 3122// start-sanitize-vr5400
3123*vr5400:
3124// end-sanitize-vr5400
f2b30012
AC		 3125// start-sanitize-r5900
3126*r5900:
3127// end-sanitize-r5900
f2b30012
AC		 3128// start-sanitize-tx19
3129*tx19:
3130// end-sanitize-tx19
3131{
a94c5493 3132 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
055ee297 3133 SignalException(Trap, instruction_0);
f2b30012
AC		 3134}
3135
3136
3137000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3138"tge r<RS>, r<RT>"
3139*mipsII:
3140*mipsIII:
3141*mipsIV:
23850e92 3142*vr5000:
15232df4
FCE		 3143// start-sanitize-vr4320
3144*vr4320:
3145// end-sanitize-vr4320
90ad43b2
AC		 3146// start-sanitize-vr5400
3147*vr5400:
3148// end-sanitize-vr5400
f2b30012
AC		 3149// start-sanitize-r5900
3150*r5900:
3151// end-sanitize-r5900
f2b30012
AC		 3152// start-sanitize-tx19
3153*tx19:
3154// end-sanitize-tx19
3155{
a94c5493 3156 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
055ee297 3157 SignalException(Trap, instruction_0);
f2b30012
AC		 3158}
3159
3160
3161000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3162"tgei r<RS>, <IMMEDIATE>"
3163*mipsII:
3164*mipsIII:
3165*mipsIV:
23850e92 3166*vr5000:
15232df4
FCE		 3167// start-sanitize-vr4320
3168*vr4320:
3169// end-sanitize-vr4320
90ad43b2
AC		 3170// start-sanitize-vr5400
3171*vr5400:
3172// end-sanitize-vr5400
f2b30012
AC		 3173// start-sanitize-r5900
3174*r5900:
3175// end-sanitize-r5900
f2b30012
AC		 3176// start-sanitize-tx19
3177*tx19:
3178// end-sanitize-tx19
3179{
a94c5493 3180 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
055ee297 3181 SignalException(Trap, instruction_0);
f2b30012
AC		 3182}
3183
3184
3185000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3186"tgeiu r<RS>, <IMMEDIATE>"
3187*mipsII:
3188*mipsIII:
3189*mipsIV:
23850e92 3190*vr5000:
15232df4
FCE		 3191// start-sanitize-vr4320
3192*vr4320:
3193// end-sanitize-vr4320
90ad43b2
AC		 3194// start-sanitize-vr5400
3195*vr5400:
3196// end-sanitize-vr5400
f2b30012
AC		 3197// start-sanitize-r5900
3198*r5900:
3199// end-sanitize-r5900
f2b30012
AC		 3200// start-sanitize-tx19
3201*tx19:
3202// end-sanitize-tx19
3203{
055ee297
AC		 3204 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3205 SignalException(Trap, instruction_0);
f2b30012
AC		 3206}
3207
3208
3209000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3210"tgeu r<RS>, r<RT>"
3211*mipsII:
3212*mipsIII:
3213*mipsIV:
23850e92 3214*vr5000:
15232df4
FCE		 3215// start-sanitize-vr4320
3216*vr4320:
3217// end-sanitize-vr4320
90ad43b2
AC		 3218// start-sanitize-vr5400
3219*vr5400:
3220// end-sanitize-vr5400
f2b30012
AC		 3221// start-sanitize-r5900
3222*r5900:
3223// end-sanitize-r5900
f2b30012
AC		 3224// start-sanitize-tx19
3225*tx19:
3226// end-sanitize-tx19
3227{
055ee297
AC		 3228 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3229 SignalException(Trap, instruction_0);
f2b30012
AC		 3230}
3231
3232
3233000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3234"tlt r<RS>, r<RT>"
3235*mipsII:
3236*mipsIII:
3237*mipsIV:
23850e92 3238*vr5000:
15232df4
FCE		 3239// start-sanitize-vr4320
3240*vr4320:
3241// end-sanitize-vr4320
90ad43b2
AC		 3242// start-sanitize-vr5400
3243*vr5400:
3244// end-sanitize-vr5400
f2b30012
AC		 3245// start-sanitize-r5900
3246*r5900:
3247// end-sanitize-r5900
f2b30012
AC		 3248// start-sanitize-tx19
3249*tx19:
3250// end-sanitize-tx19
3251{
a94c5493 3252 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
055ee297 3253 SignalException(Trap, instruction_0);
f2b30012
AC		 3254}
3255
3256
3257000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3258"tlti r<RS>, <IMMEDIATE>"
3259*mipsII:
3260*mipsIII:
3261*mipsIV:
23850e92 3262*vr5000:
15232df4
FCE		 3263// start-sanitize-vr4320
3264*vr4320:
3265// end-sanitize-vr4320
90ad43b2
AC		 3266// start-sanitize-vr5400
3267*vr5400:
3268// end-sanitize-vr5400
f2b30012
AC		 3269// start-sanitize-r5900
3270*r5900:
3271// end-sanitize-r5900
f2b30012
AC		 3272// start-sanitize-tx19
3273*tx19:
3274// end-sanitize-tx19
3275{
a94c5493 3276 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
055ee297 3277 SignalException(Trap, instruction_0);
f2b30012
AC		 3278}
3279
3280
3281000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3282"tltiu r<RS>, <IMMEDIATE>"
3283*mipsII:
3284*mipsIII:
3285*mipsIV:
23850e92 3286*vr5000:
15232df4
FCE		 3287// start-sanitize-vr4320
3288*vr4320:
3289// end-sanitize-vr4320
90ad43b2
AC		 3290// start-sanitize-vr5400
3291*vr5400:
3292// end-sanitize-vr5400
f2b30012
AC		 3293// start-sanitize-r5900
3294*r5900:
3295// end-sanitize-r5900
f2b30012
AC		 3296// start-sanitize-tx19
3297*tx19:
3298// end-sanitize-tx19
3299{
055ee297
AC		 3300 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3301 SignalException(Trap, instruction_0);
f2b30012
AC		 3302}
3303
3304
3305000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3306"tltu r<RS>, r<RT>"
3307*mipsII:
3308*mipsIII:
3309*mipsIV:
23850e92 3310*vr5000:
15232df4
FCE		 3311// start-sanitize-vr4320
3312*vr4320:
3313// end-sanitize-vr4320
90ad43b2
AC		 3314// start-sanitize-vr5400
3315*vr5400:
3316// end-sanitize-vr5400
f2b30012
AC		 3317// start-sanitize-r5900
3318*r5900:
3319// end-sanitize-r5900
f2b30012
AC		 3320// start-sanitize-tx19
3321*tx19:
3322// end-sanitize-tx19
3323{
055ee297
AC		 3324 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3325 SignalException(Trap, instruction_0);
f2b30012
AC		 3326}
3327
3328
3329000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3330"tne r<RS>, r<RT>"
3331*mipsII:
3332*mipsIII:
3333*mipsIV:
23850e92 3334*vr5000:
15232df4
FCE		 3335// start-sanitize-vr4320
3336*vr4320:
3337// end-sanitize-vr4320
90ad43b2
AC		 3338// start-sanitize-vr5400
3339*vr5400:
3340// end-sanitize-vr5400
f2b30012
AC		 3341// start-sanitize-r5900
3342*r5900:
3343// end-sanitize-r5900
f2b30012
AC		 3344// start-sanitize-tx19
3345*tx19:
3346// end-sanitize-tx19
3347{
a94c5493 3348 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
055ee297 3349 SignalException(Trap, instruction_0);
f2b30012
AC		 3350}
3351
3352
3353000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3354"tne r<RS>, <IMMEDIATE>"
3355*mipsII:
3356*mipsIII:
3357*mipsIV:
23850e92 3358*vr5000:
15232df4
FCE		 3359// start-sanitize-vr4320
3360*vr4320:
3361// end-sanitize-vr4320
90ad43b2
AC		 3362// start-sanitize-vr5400
3363*vr5400:
3364// end-sanitize-vr5400
f2b30012
AC		 3365// start-sanitize-r5900
3366*r5900:
3367// end-sanitize-r5900
f2b30012
AC		 3368// start-sanitize-tx19
3369*tx19:
3370// end-sanitize-tx19
3371{
a94c5493 3372 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
055ee297 3373 SignalException(Trap, instruction_0);
f2b30012
AC		 3374}
3375
3376
c0a4c3ba
AC		 3377:function:::void:do_xor:int rs, int rt, int rd
3378{
3379 GPR[rd] = GPR[rs] ^ GPR[rt];
3380}
3381
f2b30012
AC		 3382000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3383"xor r<RD>, r<RS>, r<RT>"
23850e92
JL		 3384*mipsI,mipsII,mipsIII,mipsIV:
3385*vr5000:
15232df4
FCE		 3386// start-sanitize-vr4320
3387*vr4320:
3388// end-sanitize-vr4320
90ad43b2
AC		 3389// start-sanitize-vr5400
3390*vr5400:
3391// end-sanitize-vr5400
f2b30012
AC		 3392// start-sanitize-r5900
3393*r5900:
3394// end-sanitize-r5900
3395*r3900:
3396// start-sanitize-tx19
3397*tx19:
3398// end-sanitize-tx19
3399{
c0a4c3ba 3400 do_xor (SD_, RS, RT, RD);
f2b30012
AC		 3401}
3402
3403
c0a4c3ba
AC		 3404:function:::void:do_xori:int rs, int rt, unsigned16 immediate
3405{
3406 GPR[rt] = GPR[rs] ^ immediate;
3407}
3408
f2b30012 3409001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
055ee297 3410"xori r<RT>, r<RS>, <IMMEDIATE>"
23850e92
JL		 3411*mipsI,mipsII,mipsIII,mipsIV:
3412*vr5000:
15232df4
FCE		 3413// start-sanitize-vr4320
3414*vr4320:
3415// end-sanitize-vr4320
90ad43b2
AC		 3416// start-sanitize-vr5400
3417*vr5400:
3418// end-sanitize-vr5400
f2b30012
AC		 3419// start-sanitize-r5900
3420*r5900:
3421// end-sanitize-r5900
3422*r3900:
3423// start-sanitize-tx19
3424*tx19:
3425// end-sanitize-tx19
3426{
c0a4c3ba 3427 do_xori (SD_, RS, RT, IMMEDIATE);
f2b30012
AC		 3428}
3429
3430\f
3431//
3432// MIPS Architecture:
3433//
3434// FPU Instruction Set (COP1 & COP1X)
3435//
3436
3437
89d09738 3438:%s::::FMT:int fmt
055ee297
AC		 3439{
3440 switch (fmt)
3441 {
3442 case fmt_single: return "s";
3443 case fmt_double: return "d";
3444 case fmt_word: return "w";
3445 case fmt_long: return "l";
3446 default: return "?";
3447 }
3448}
3449
030843d7
AC		 3450:%s::::X:int x
3451{
3452 switch (x)
3453 {
3454 case 0: return "f";
3455 case 1: return "t";
3456 default: return "?";
3457 }
3458}
3459
89d09738 3460:%s::::TF:int tf
055ee297
AC		 3461{
3462 if (tf)
3463 return "t";
3464 else
3465 return "f";
3466}
3467
89d09738 3468:%s::::ND:int nd
055ee297
AC		 3469{
3470 if (nd)
3471 return "l";
3472 else
3473 return "";
3474}
3475
89d09738 3476:%s::::COND:int cond
055ee297
AC		 3477{
3478 switch (cond)
3479 {
3480 case 00: return "f";
3481 case 01: return "un";
3482 case 02: return "eq";
3483 case 03: return "ueq";
3484 case 04: return "olt";
3485 case 05: return "ult";
3486 case 06: return "ole";
3487 case 07: return "ule";
3488 case 010: return "sf";
3489 case 011: return "ngle";
3490 case 012: return "seq";
3491 case 013: return "ngl";
3492 case 014: return "lt";
3493 case 015: return "nge";
3494 case 016: return "le";
3495 case 017: return "ngt";
3496 default: return "?";
3497 }
3498}
3499
3500
f2b30012
AC		 3501010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3502"abs.%s<FMT> f<FD>, f<FS>"
23850e92
JL		 3503*mipsI,mipsII,mipsIII,mipsIV:
3504*vr5000:
15232df4
FCE		 3505// start-sanitize-vr4320
3506*vr4320:
3507// end-sanitize-vr4320
90ad43b2
AC		 3508// start-sanitize-vr5400
3509*vr5400:
3510// end-sanitize-vr5400
f2b30012
AC		 3511*r3900:
3512// start-sanitize-tx19
3513*tx19:
3514// end-sanitize-tx19
3515{
3516 unsigned32 instruction = instruction_0;
055ee297
AC		 3517 int destreg = ((instruction >> 6) & 0x0000001F);
3518 int fs = ((instruction >> 11) & 0x0000001F);
3519 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3520 {
3521 if ((format != fmt_single) && (format != fmt_double))
3522 SignalException(ReservedInstruction,instruction);
3523 else
3524 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3525 }
3526}
3527
3528
055ee297 3529
a48e8c8d 3530010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
f2b30012 3531"add.%s<FMT> f<FD>, f<FS>, f<FT>"
23850e92
JL		 3532*mipsI,mipsII,mipsIII,mipsIV:
3533*vr5000:
15232df4
FCE		 3534// start-sanitize-vr4320
3535*vr4320:
3536// end-sanitize-vr4320
90ad43b2
AC		 3537// start-sanitize-vr5400
3538*vr5400:
3539// end-sanitize-vr5400
f2b30012
AC		 3540*r3900:
3541// start-sanitize-tx19
3542*tx19:
3543// end-sanitize-tx19
3544{
3545 unsigned32 instruction = instruction_0;
055ee297
AC		 3546 int destreg = ((instruction >> 6) & 0x0000001F);
3547 int fs = ((instruction >> 11) & 0x0000001F);
3548 int ft = ((instruction >> 16) & 0x0000001F);
3549 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3550 {
3551 if ((format != fmt_single) && (format != fmt_double))
055ee297 3552 SignalException(ReservedInstruction, instruction);
f2b30012
AC		 3553 else
3554 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3555 }
3556}
3557
3558
23850e92 3559
f2b30012
AC		 3560// BC1F
3561// BC1FL
3562// BC1T
3563// BC1TL
23850e92
JL		 3564
3565010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3566"bc1%s<TF>%s<ND> <OFFSET>"
3567*mipsI,mipsII,mipsIII:
3568// start-sanitize-r5900
3569*r5900:
3570// end-sanitize-r5900
3571{
a48e8c8d 3572 TRACE_BRANCH_INPUT (PREVCOC1());
23850e92
JL		 3573 if (PREVCOC1() == TF)
3574 {
a48e8c8d
AC		 3575 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3576 TRACE_BRANCH_RESULT (dest);
3577 DELAY_SLOT (dest);
23850e92
JL		 3578 }
3579 else if (ND)
3580 {
a48e8c8d 3581 TRACE_BRANCH_RESULT (0);
23850e92
JL		 3582 NULLIFY_NEXT_INSTRUCTION ();
3583 }
a48e8c8d
AC		 3584 else
3585 {
3586 TRACE_BRANCH_RESULT (NIA);
3587 }
23850e92
JL		 3588}
3589
055ee297
AC		 3590010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3591"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3592"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
f2b30012 3593*mipsIV:
23850e92 3594*vr5000:
15232df4
FCE		 3595// start-sanitize-vr4320
3596*vr4320:
3597// end-sanitize-vr4320
90ad43b2
AC		 3598// start-sanitize-vr5400
3599*vr5400:
3600// end-sanitize-vr5400
f2b30012
AC		 3601*r3900:
3602// start-sanitize-tx19
3603*tx19:
3604// end-sanitize-tx19
3605{
23850e92
JL		 3606 if (GETFCC(CC) == TF)
3607 {
3608 DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3609 }
3610 else if (ND)
3611 {
3612 NULLIFY_NEXT_INSTRUCTION ();
f2b30012 3613 }
f2b30012
AC		 3614}
3615
3616
23850e92
JL		 3617
3618// C.EQ.S
3619// C.EQ.D
3620// ...
3621
3622:function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3623{
3624 if ((fmt != fmt_single) && (fmt != fmt_double))
3625 SignalException (ReservedInstruction, insn);
3626 else
3627 {
3628 int less;
3629 int equal;
3630 int unordered;
3631 int condition;
3632 unsigned64 ofs = ValueFPR (fs, fmt);
3633 unsigned64 oft = ValueFPR (ft, fmt);
3634 if (NaN (ofs, fmt) || NaN (oft, fmt))
3635 {
3636 if (FCSR & FP_ENABLE (IO))
3637 {
3638 FCSR |= FP_CAUSE (IO);
3639 SignalExceptionFPE ();
3640 }
3641 less = 0;
3642 equal = 0;
3643 unordered = 1;
3644 }
3645 else
3646 {
3647 less = Less (ofs, oft, fmt);
3648 equal = Equal (ofs, oft, fmt);
3649 unordered = 0;
3650 }
3651 condition = (((cond & (1 << 2)) && less)
3652 || ((cond & (1 << 1)) && equal)
3653 || ((cond & (1 << 0)) && unordered));
3654 SETFCC (cc, condition);
3655 }
3656}
3657
3658010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
3659*mipsI,mipsII,mipsIII:
3660"c.%s<COND>.%s<FMT> f<FS>, f<FT>":
3661{
3662 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
3663}
3664
f2b30012
AC		 3665010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3666"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3667"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
f2b30012 3668*mipsIV:
23850e92 3669*vr5000:
15232df4
FCE		 3670// start-sanitize-vr4320
3671*vr4320:
3672// end-sanitize-vr4320
90ad43b2
AC		 3673// start-sanitize-vr5400
3674*vr5400:
3675// end-sanitize-vr5400
f2b30012
AC		 3676*r3900:
3677// start-sanitize-tx19
3678*tx19:
3679// end-sanitize-tx19
3680{
23850e92 3681 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
f2b30012
AC		 3682}
3683
3684
3685010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3686"ceil.l.%s<FMT> f<FD>, f<FS>"
3687*mipsIII:
3688*mipsIV:
23850e92 3689*vr5000:
15232df4
FCE		 3690// start-sanitize-vr4320
3691*vr4320:
3692// end-sanitize-vr4320
90ad43b2
AC		 3693// start-sanitize-vr5400
3694*vr5400:
3695// end-sanitize-vr5400
f2b30012
AC		 3696// start-sanitize-r5900
3697*r5900:
3698// end-sanitize-r5900
3699*r3900:
3700// start-sanitize-tx19
3701*tx19:
3702// end-sanitize-tx19
3703{
3704 unsigned32 instruction = instruction_0;
055ee297
AC		 3705 int destreg = ((instruction >> 6) & 0x0000001F);
3706 int fs = ((instruction >> 11) & 0x0000001F);
3707 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3708 {
3709 if ((format != fmt_single) && (format != fmt_double))
3710 SignalException(ReservedInstruction,instruction);
3711 else
3712 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3713 }
3714}
3715
3716
3717010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3718*mipsII:
3719*mipsIII:
3720*mipsIV:
23850e92 3721*vr5000:
15232df4
FCE		 3722// start-sanitize-vr4320
3723*vr4320:
3724// end-sanitize-vr4320
90ad43b2
AC		 3725// start-sanitize-vr5400
3726*vr5400:
3727// end-sanitize-vr5400
f2b30012
AC		 3728// start-sanitize-r5900
3729*r5900:
3730// end-sanitize-r5900
3731*r3900:
3732// start-sanitize-tx19
3733*tx19:
3734// end-sanitize-tx19
3735{
3736 unsigned32 instruction = instruction_0;
055ee297
AC		 3737 int destreg = ((instruction >> 6) & 0x0000001F);
3738 int fs = ((instruction >> 11) & 0x0000001F);
3739 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3740 {
3741 if ((format != fmt_single) && (format != fmt_double))
3742 SignalException(ReservedInstruction,instruction);
3743 else
3744 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3745 }
3746}
3747
3748
3749// CFC1
3750// CTC1
030843d7
AC		 3751010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3752"c%s<X>c1 r<RT>, f<FS>"
f2b30012
AC		 3753*mipsI:
3754*mipsII:
3755*mipsIII:
030843d7
AC		 3756{
3757 if (X)
3758 {
3759 if (FS == 0)
3760 PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
3761 else if (FS == 31)
3762 PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
3763 /* else NOP */
3764 PENDING_FILL(COCIDX,0); /* special case */
3765 }
3766 else
3767 { /* control from */
3768 if (FS == 0)
3769 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
3770 else if (FS == 31)
3771 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
3772 /* else NOP */
3773 }
3774}
3775010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3776"c%s<X>c1 r<RT>, f<FS>"
f2b30012 3777*mipsIV:
23850e92 3778*vr5000:
15232df4
FCE		 3779// start-sanitize-vr4320
3780*vr4320:
3781// end-sanitize-vr4320
90ad43b2
AC		 3782// start-sanitize-vr5400
3783*vr5400:
3784// end-sanitize-vr5400
f2b30012
AC		 3785// start-sanitize-r5900
3786*r5900:
3787// end-sanitize-r5900
3788*r3900:
3789// start-sanitize-tx19
3790*tx19:
3791// end-sanitize-tx19
3792{
030843d7
AC		 3793 if (X)
3794 {
f89c0689
AC		 3795 /* control to */
3796 TRACE_ALU_INPUT1 (GPR[RT]);
030843d7 3797 if (FS == 0)
f89c0689
AC		 3798 {
3799 FCR0 = VL4_8(GPR[RT]);
3800 TRACE_ALU_RESULT (FCR0);
3801 }
030843d7 3802 else if (FS == 31)
f89c0689
AC		 3803 {
3804 FCR31 = VL4_8(GPR[RT]);
3805 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3806 TRACE_ALU_RESULT (FCR31);
3807 }
3808 else
3809 {
3810 TRACE_ALU_RESULT0 ();
3811 }
030843d7 3812 /* else NOP */
030843d7
AC		 3813 }
3814 else
3815 { /* control from */
3816 if (FS == 0)
f89c0689
AC		 3817 {
3818 TRACE_ALU_INPUT1 (FCR0);
3819 GPR[RT] = SIGNEXTEND (FCR0, 32);
3820 }
030843d7 3821 else if (FS == 31)
f89c0689
AC		 3822 {
3823 TRACE_ALU_INPUT1 (FCR31);
3824 GPR[RT] = SIGNEXTEND (FCR31, 32);
3825 }
3826 TRACE_ALU_RESULT (GPR[RT]);
030843d7 3827 /* else NOP */
f2b30012 3828 }
f2b30012
AC		 3829}
3830
3831
3832//
3833// FIXME: Does not correctly differentiate between mips*
3834//
3835010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
3836"cvt.d.%s<FMT> f<FD>, f<FS>"
23850e92
JL		 3837*mipsI,mipsII,mipsIII,mipsIV:
3838*vr5000:
15232df4
FCE		 3839// start-sanitize-vr4320
3840*vr4320:
3841// end-sanitize-vr4320
90ad43b2
AC		 3842// start-sanitize-vr5400
3843*vr5400:
3844// end-sanitize-vr5400
f2b30012
AC		 3845*r3900:
3846// start-sanitize-tx19
3847*tx19:
3848// end-sanitize-tx19
3849{
3850 unsigned32 instruction = instruction_0;
055ee297
AC		 3851 int destreg = ((instruction >> 6) & 0x0000001F);
3852 int fs = ((instruction >> 11) & 0x0000001F);
3853 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3854 {
3855 if ((format == fmt_double) | 0)
3856 SignalException(ReservedInstruction,instruction);
3857 else
3858 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
3859 }
3860}
3861
3862
3863010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
3864"cvt.l.%s<FMT> f<FD>, f<FS>"
3865*mipsIII:
3866*mipsIV:
23850e92 3867*vr5000:
15232df4
FCE		 3868// start-sanitize-vr4320
3869*vr4320:
3870// end-sanitize-vr4320
90ad43b2
AC		 3871// start-sanitize-vr5400
3872*vr5400:
3873// end-sanitize-vr5400
f2b30012
AC		 3874*r3900:
3875// start-sanitize-tx19
3876*tx19:
3877// end-sanitize-tx19
3878{
3879 unsigned32 instruction = instruction_0;
055ee297
AC		 3880 int destreg = ((instruction >> 6) & 0x0000001F);
3881 int fs = ((instruction >> 11) & 0x0000001F);
3882 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3883 {
3884 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
3885 SignalException(ReservedInstruction,instruction);
3886 else
3887 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
3888 }
3889}
3890
3891
3892//
3893// FIXME: Does not correctly differentiate between mips*
3894//
3895010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
3896"cvt.s.%s<FMT> f<FD>, f<FS>"
23850e92
JL		 3897*mipsI,mipsII,mipsIII,mipsIV:
3898*vr5000:
15232df4
FCE		 3899// start-sanitize-vr4320
3900*vr4320:
3901// end-sanitize-vr4320
90ad43b2
AC		 3902// start-sanitize-vr5400
3903*vr5400:
3904// end-sanitize-vr5400
f2b30012
AC		 3905*r3900:
3906// start-sanitize-tx19
3907*tx19:
3908// end-sanitize-tx19
3909{
3910 unsigned32 instruction = instruction_0;
055ee297
AC		 3911 int destreg = ((instruction >> 6) & 0x0000001F);
3912 int fs = ((instruction >> 11) & 0x0000001F);
3913 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3914 {
3915 if ((format == fmt_single) | 0)
3916 SignalException(ReservedInstruction,instruction);
3917 else
3918 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
3919 }
3920}
3921
3922
3923010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
3924"cvt.w.%s<FMT> f<FD>, f<FS>"
23850e92
JL		 3925*mipsI,mipsII,mipsIII,mipsIV:
3926*vr5000:
15232df4
FCE		 3927// start-sanitize-vr4320
3928*vr4320:
3929// end-sanitize-vr4320
90ad43b2
AC		 3930// start-sanitize-vr5400
3931*vr5400:
3932// end-sanitize-vr5400
f2b30012
AC		 3933*r3900:
3934// start-sanitize-tx19
3935*tx19:
3936// end-sanitize-tx19
3937{
3938 unsigned32 instruction = instruction_0;
055ee297
AC		 3939 int destreg = ((instruction >> 6) & 0x0000001F);
3940 int fs = ((instruction >> 11) & 0x0000001F);
3941 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3942 {
3943 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
3944 SignalException(ReservedInstruction,instruction);
3945 else
3946 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
3947 }
3948}
3949
3950
3951010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
3952"div.%s<FMT> f<FD>, f<FS>, f<FT>"
23850e92
JL		 3953*mipsI,mipsII,mipsIII,mipsIV:
3954*vr5000:
15232df4
FCE		 3955// start-sanitize-vr4320
3956*vr4320:
3957// end-sanitize-vr4320
90ad43b2
AC		 3958// start-sanitize-vr5400
3959*vr5400:
3960// end-sanitize-vr5400
f2b30012
AC		 3961*r3900:
3962// start-sanitize-tx19
3963*tx19:
3964// end-sanitize-tx19
3965{
3966 unsigned32 instruction = instruction_0;
055ee297
AC		 3967 int destreg = ((instruction >> 6) & 0x0000001F);
3968 int fs = ((instruction >> 11) & 0x0000001F);
3969 int ft = ((instruction >> 16) & 0x0000001F);
3970 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 3971 {
3972 if ((format != fmt_single) && (format != fmt_double))
3973 SignalException(ReservedInstruction,instruction);
3974 else
3975 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3976 }
3977}
3978
3979
3980// DMFC1
3981// DMTC1
030843d7
AC		 3982010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
3983"dm%s<X>c1 r<RT>, f<FS>"
f2b30012 3984*mipsIII:
030843d7
AC		 3985{
3986 if (X)
3987 {
3988 if (SizeFGR() == 64)
3989 PENDING_FILL((FS + FGRIDX),GPR[RT]);
3990 else if ((FS & 0x1) == 0)
3991 {
3992 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
3993 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
3994 }
3995 }
3996 else
3997 {
3998 if (SizeFGR() == 64)
3999 PENDING_FILL(RT,FGR[FS]);
4000 else if ((FS & 0x1) == 0)
4001 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4002 else
4003 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4004 }
4005}
4006010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4007"dm%s<X>c1 r<RT>, f<FS>"
f2b30012 4008*mipsIV:
23850e92 4009*vr5000:
15232df4
FCE		 4010// start-sanitize-vr4320
4011*vr4320:
4012// end-sanitize-vr4320
90ad43b2
AC		 4013// start-sanitize-vr5400
4014*vr5400:
4015// end-sanitize-vr5400
f2b30012
AC		 4016// start-sanitize-r5900
4017*r5900:
4018// end-sanitize-r5900
4019*r3900:
4020// start-sanitize-tx19
4021*tx19:
4022// end-sanitize-tx19
4023{
030843d7
AC		 4024 if (X)
4025 {
4026 if (SizeFGR() == 64)
23850e92 4027 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
030843d7 4028 else if ((FS & 0x1) == 0)
23850e92 4029 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
f2b30012 4030 }
030843d7
AC		 4031 else
4032 {
4033 if (SizeFGR() == 64)
4034 GPR[RT] = FGR[FS];
4035 else if ((FS & 0x1) == 0)
4036 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4037 else
4038 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4039 }
f2b30012
AC		 4040}
4041
4042
4043010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4044"floor.l.%s<FMT> f<FD>, f<FS>"
4045*mipsIII:
4046*mipsIV:
23850e92 4047*vr5000:
15232df4
FCE		 4048// start-sanitize-vr4320
4049*vr4320:
4050// end-sanitize-vr4320
90ad43b2
AC		 4051// start-sanitize-vr5400
4052*vr5400:
4053// end-sanitize-vr5400
f2b30012
AC		 4054// start-sanitize-r5900
4055*r5900:
4056// end-sanitize-r5900
4057*r3900:
4058// start-sanitize-tx19
4059*tx19:
4060// end-sanitize-tx19
4061{
4062 unsigned32 instruction = instruction_0;
055ee297
AC		 4063 int destreg = ((instruction >> 6) & 0x0000001F);
4064 int fs = ((instruction >> 11) & 0x0000001F);
4065 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4066 {
4067 if ((format != fmt_single) && (format != fmt_double))
4068 SignalException(ReservedInstruction,instruction);
4069 else
4070 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4071 }
4072}
4073
4074
4075010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4076"floor.w.%s<FMT> f<FD>, f<FS>"
4077*mipsII:
4078*mipsIII:
4079*mipsIV:
23850e92 4080*vr5000:
15232df4
FCE		 4081// start-sanitize-vr4320
4082*vr4320:
4083// end-sanitize-vr4320
90ad43b2
AC		 4084// start-sanitize-vr5400
4085*vr5400:
4086// end-sanitize-vr5400
f2b30012
AC		 4087// start-sanitize-r5900
4088*r5900:
4089// end-sanitize-r5900
4090*r3900:
4091// start-sanitize-tx19
4092*tx19:
4093// end-sanitize-tx19
4094{
4095 unsigned32 instruction = instruction_0;
055ee297
AC		 4096 int destreg = ((instruction >> 6) & 0x0000001F);
4097 int fs = ((instruction >> 11) & 0x0000001F);
4098 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4099 {
4100 if ((format != fmt_single) && (format != fmt_double))
4101 SignalException(ReservedInstruction,instruction);
4102 else
4103 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4104 }
4105}
4106
4107
030843d7 4108110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
a94c5493 4109"ldc1 f<FT>, <OFFSET>(r<BASE>)"
030843d7
AC		 4110*mipsII:
4111*mipsIII:
4112*mipsIV:
23850e92 4113*vr5000:
15232df4
FCE		 4114// start-sanitize-vr4320
4115*vr4320:
4116// end-sanitize-vr4320
030843d7
AC		 4117// start-sanitize-vr5400
4118*vr5400:
4119// end-sanitize-vr5400
4120*r3900:
4121// start-sanitize-tx19
4122*tx19:
4123// end-sanitize-tx19
4124{
ebcfd86a 4125 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
030843d7 4126}
f2b30012
AC		 4127
4128
4129010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4130"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4131*mipsIV:
23850e92 4132*vr5000:
15232df4
FCE		 4133// start-sanitize-vr4320
4134*vr4320:
4135// end-sanitize-vr4320
90ad43b2
AC		 4136// start-sanitize-vr5400
4137*vr5400:
4138// end-sanitize-vr5400
f2b30012 4139{
ebcfd86a 4140 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
f2b30012
AC		 4141}
4142
4143
f2b30012 4144
030843d7 4145110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
23850e92
JL		 4146"lwc1 f<FT>, <OFFSET>(r<BASE>)"
4147*mipsI,mipsII,mipsIII,mipsIV:
4148*vr5000:
15232df4
FCE		 4149// start-sanitize-vr4320
4150*vr4320:
4151// end-sanitize-vr4320
90ad43b2
AC		 4152// start-sanitize-vr5400
4153*vr5400:
4154// end-sanitize-vr5400
f2b30012
AC		 4155// start-sanitize-r5900
4156*r5900:
4157// end-sanitize-r5900
030843d7
AC		 4158*r3900:
4159// start-sanitize-tx19
4160*tx19:
4161// end-sanitize-tx19
4162{
ebcfd86a 4163 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
030843d7
AC		 4164}
4165
4166
4167010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4168"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4169*mipsIV:
23850e92 4170*vr5000:
15232df4
FCE		 4171// start-sanitize-vr4320
4172*vr4320:
4173// end-sanitize-vr4320
030843d7
AC		 4174// start-sanitize-vr5400
4175*vr5400:
4176// end-sanitize-vr5400
f2b30012 4177{
ebcfd86a 4178 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
f2b30012
AC		 4179}
4180
4181
4182
4183//
4184// FIXME: Not correct for mips*
4185//
a48e8c8d 4186010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
f2b30012
AC		 4187"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4188*mipsIV:
23850e92 4189*vr5000:
15232df4
FCE		 4190// start-sanitize-vr4320
4191*vr4320:
4192// end-sanitize-vr4320
90ad43b2
AC		 4193// start-sanitize-vr5400
4194*vr5400:
4195// end-sanitize-vr5400
f2b30012
AC		 4196{
4197 unsigned32 instruction = instruction_0;
055ee297
AC		 4198 int destreg = ((instruction >> 6) & 0x0000001F);
4199 int fs = ((instruction >> 11) & 0x0000001F);
4200 int ft = ((instruction >> 16) & 0x0000001F);
4201 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4202 {
4203 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4204 }
4205}
4206
4207
a48e8c8d 4208010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
f2b30012
AC		 4209"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4210*mipsIV:
23850e92 4211*vr5000:
15232df4
FCE		 4212// start-sanitize-vr4320
4213*vr4320:
4214// end-sanitize-vr4320
90ad43b2
AC		 4215// start-sanitize-vr5400
4216*vr5400:
4217// end-sanitize-vr5400
f2b30012
AC		 4218{
4219 unsigned32 instruction = instruction_0;
055ee297
AC		 4220 int destreg = ((instruction >> 6) & 0x0000001F);
4221 int fs = ((instruction >> 11) & 0x0000001F);
4222 int ft = ((instruction >> 16) & 0x0000001F);
4223 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4224 {
4225 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4226 }
4227}
4228
4229
4230// MFC1
030843d7 4231// MTC1
f2b30012 4232010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
030843d7 4233"m%s<X>c1 r<RT>, f<FS>"
f2b30012
AC		 4234*mipsI:
4235*mipsII:
4236*mipsIII:
030843d7
AC		 4237{
4238 if (X)
4239 { /*MTC1*/
4240 if (SizeFGR() == 64)
4241 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4242 else
4243 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4244 }
4245 else /*MFC1*/
4246 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4247}
4248010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4249"m%s<X>c1 r<RT>, f<FS>"
f2b30012 4250*mipsIV:
23850e92 4251*vr5000:
15232df4
FCE		 4252// start-sanitize-vr4320
4253*vr4320:
4254// end-sanitize-vr4320
90ad43b2
AC		 4255// start-sanitize-vr5400
4256*vr5400:
4257// end-sanitize-vr5400
f2b30012
AC		 4258*r3900:
4259// start-sanitize-tx19
4260*tx19:
4261// end-sanitize-tx19
4262{
030843d7 4263 if (X)
23850e92
JL		 4264 /*MTC1*/
4265 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
030843d7
AC		 4266 else /*MFC1*/
4267 GPR[RT] = SIGNEXTEND(FGR[FS],32);
f2b30012
AC		 4268}
4269
4270
4271010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4272"mov.%s<FMT> f<FD>, f<FS>"
23850e92
JL		 4273*mipsI,mipsII,mipsIII,mipsIV:
4274*vr5000:
15232df4
FCE		 4275// start-sanitize-vr4320
4276*vr4320:
4277// end-sanitize-vr4320
90ad43b2
AC		 4278// start-sanitize-vr5400
4279*vr5400:
4280// end-sanitize-vr5400
f2b30012
AC		 4281*r3900:
4282// start-sanitize-tx19
4283*tx19:
4284// end-sanitize-tx19
4285{
4286 unsigned32 instruction = instruction_0;
055ee297
AC		 4287 int destreg = ((instruction >> 6) & 0x0000001F);
4288 int fs = ((instruction >> 11) & 0x0000001F);
4289 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4290 {
4291 StoreFPR(destreg,format,ValueFPR(fs,format));
4292 }
4293}
4294
4295
4296// MOVF
4297000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
055ee297 4298"mov%s<TF> r<RD>, r<RS>, <CC>"
f2b30012 4299*mipsIV:
23850e92 4300*vr5000:
15232df4
FCE		 4301// start-sanitize-vr4320
4302*vr4320:
4303// end-sanitize-vr4320
90ad43b2
AC		 4304// start-sanitize-vr5400
4305*vr5400:
4306// end-sanitize-vr5400
f2b30012
AC		 4307// start-sanitize-r5900
4308*r5900:
4309// end-sanitize-r5900
4310{
055ee297
AC		 4311 if (GETFCC(CC) == TF)
4312 GPR[RD] = GPR[RS];
f2b30012
AC		 4313}
4314
4315
4316// MOVF.fmt
4317010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
055ee297 4318"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
f2b30012 4319*mipsIV:
23850e92 4320*vr5000:
15232df4
FCE		 4321// start-sanitize-vr4320
4322*vr4320:
4323// end-sanitize-vr4320
90ad43b2
AC		 4324// start-sanitize-vr5400
4325*vr5400:
4326// end-sanitize-vr5400
f2b30012
AC		 4327// start-sanitize-r5900
4328*r5900:
4329// end-sanitize-r5900
4330{
4331 unsigned32 instruction = instruction_0;
055ee297 4332 int format = ((instruction >> 21) & 0x00000007);
f2b30012 4333 {
055ee297
AC		 4334 if (GETFCC(CC) == TF)
4335 StoreFPR (FD, format, ValueFPR (FS, format));
f2b30012 4336 else
055ee297 4337 StoreFPR (FD, format, ValueFPR (FD, format));
f2b30012
AC		 4338 }
4339}
4340
4341
4342010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4343*mipsIV:
23850e92 4344*vr5000:
15232df4
FCE		 4345// start-sanitize-vr4320
4346*vr4320:
4347// end-sanitize-vr4320
90ad43b2
AC		 4348// start-sanitize-vr5400
4349*vr5400:
4350// end-sanitize-vr5400
f2b30012
AC		 4351// start-sanitize-r5900
4352*r5900:
4353// end-sanitize-r5900
4354{
4355 unsigned32 instruction = instruction_0;
055ee297
AC		 4356 int destreg = ((instruction >> 6) & 0x0000001F);
4357 int fs = ((instruction >> 11) & 0x0000001F);
4358 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4359 {
4360 StoreFPR(destreg,format,ValueFPR(fs,format));
4361 }
4362}
4363
4364
4365// MOVT see MOVtf
4366
4367
4368// MOVT.fmt see MOVtf.fmt
4369
4370
4371
4372010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4373"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4374*mipsIV:
23850e92 4375*vr5000:
15232df4
FCE		 4376// start-sanitize-vr4320
4377*vr4320:
4378// end-sanitize-vr4320
90ad43b2
AC		 4379// start-sanitize-vr5400
4380*vr5400:
4381// end-sanitize-vr5400
f2b30012
AC		 4382// start-sanitize-r5900
4383*r5900:
4384// end-sanitize-r5900
4385{
4386 unsigned32 instruction = instruction_0;
055ee297
AC		 4387 int destreg = ((instruction >> 6) & 0x0000001F);
4388 int fs = ((instruction >> 11) & 0x0000001F);
4389 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4390 {
4391 StoreFPR(destreg,format,ValueFPR(fs,format));
4392 }
4393}
4394
4395
4396// MSUB.fmt
4397010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4398"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4399*mipsIV:
23850e92 4400*vr5000:
15232df4
FCE		 4401// start-sanitize-vr4320
4402*vr4320:
4403// end-sanitize-vr4320
90ad43b2
AC		 4404// start-sanitize-vr5400
4405*vr5400:
4406// end-sanitize-vr5400
f2b30012
AC		 4407// start-sanitize-r5900
4408*r5900:
4409// end-sanitize-r5900
4410{
4411 unsigned32 instruction = instruction_0;
055ee297
AC		 4412 int destreg = ((instruction >> 6) & 0x0000001F);
4413 int fs = ((instruction >> 11) & 0x0000001F);
4414 int ft = ((instruction >> 16) & 0x0000001F);
4415 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012 4416 {
23850e92 4417 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
f2b30012
AC		 4418 }
4419}
4420
4421
4422// MSUB.fmt
055ee297 4423010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
f2b30012
AC		 4424"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4425*mipsIV:
23850e92 4426*vr5000:
15232df4
FCE		 4427// start-sanitize-vr4320
4428*vr4320:
4429// end-sanitize-vr4320
90ad43b2
AC		 4430// start-sanitize-vr5400
4431*vr5400:
4432// end-sanitize-vr5400
f2b30012
AC		 4433// start-sanitize-r5900
4434*r5900:
4435// end-sanitize-r5900
4436{
4437 unsigned32 instruction = instruction_0;
055ee297
AC		 4438 int destreg = ((instruction >> 6) & 0x0000001F);
4439 int fs = ((instruction >> 11) & 0x0000001F);
4440 int ft = ((instruction >> 16) & 0x0000001F);
4441 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012 4442 {
23850e92 4443 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
f2b30012
AC		 4444 }
4445}
4446
4447
4448// MTC1 see MxC1
4449
4450
4451010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4452"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
23850e92
JL		 4453*mipsI,mipsII,mipsIII,mipsIV:
4454*vr5000:
15232df4
FCE		 4455// start-sanitize-vr4320
4456*vr4320:
4457// end-sanitize-vr4320
90ad43b2
AC		 4458// start-sanitize-vr5400
4459*vr5400:
4460// end-sanitize-vr5400
f2b30012
AC		 4461*r3900:
4462// start-sanitize-tx19
4463*tx19:
4464// end-sanitize-tx19
4465{
4466 unsigned32 instruction = instruction_0;
055ee297
AC		 4467 int destreg = ((instruction >> 6) & 0x0000001F);
4468 int fs = ((instruction >> 11) & 0x0000001F);
4469 int ft = ((instruction >> 16) & 0x0000001F);
4470 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4471 {
4472 if ((format != fmt_single) && (format != fmt_double))
4473 SignalException(ReservedInstruction,instruction);
4474 else
4475 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4476 }
4477}
4478
4479
4480010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4481"neg.%s<FMT> f<FD>, f<FS>"
23850e92
JL		 4482*mipsI,mipsII,mipsIII,mipsIV:
4483*vr5000:
15232df4
FCE		 4484// start-sanitize-vr4320
4485*vr4320:
4486// end-sanitize-vr4320
90ad43b2
AC		 4487// start-sanitize-vr5400
4488*vr5400:
4489// end-sanitize-vr5400
f2b30012
AC		 4490*r3900:
4491// start-sanitize-tx19
4492*tx19:
4493// end-sanitize-tx19
4494{
4495 unsigned32 instruction = instruction_0;
055ee297
AC		 4496 int destreg = ((instruction >> 6) & 0x0000001F);
4497 int fs = ((instruction >> 11) & 0x0000001F);
4498 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4499 {
4500 if ((format != fmt_single) && (format != fmt_double))
4501 SignalException(ReservedInstruction,instruction);
4502 else
4503 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4504 }
4505}
4506
4507
4508// NMADD.fmt
4509010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4510"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4511*mipsIV:
23850e92 4512*vr5000:
15232df4
FCE		 4513// start-sanitize-vr4320
4514*vr4320:
4515// end-sanitize-vr4320
90ad43b2
AC		 4516// start-sanitize-vr5400
4517*vr5400:
4518// end-sanitize-vr5400
f2b30012
AC		 4519{
4520 unsigned32 instruction = instruction_0;
055ee297
AC		 4521 int destreg = ((instruction >> 6) & 0x0000001F);
4522 int fs = ((instruction >> 11) & 0x0000001F);
4523 int ft = ((instruction >> 16) & 0x0000001F);
4524 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4525 {
4526 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4527 }
4528}
4529
4530
4531// NMADD.fmt
4532010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4533"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4534*mipsIV:
23850e92 4535*vr5000:
15232df4
FCE		 4536// start-sanitize-vr4320
4537*vr4320:
4538// end-sanitize-vr4320
90ad43b2
AC		 4539// start-sanitize-vr5400
4540*vr5400:
4541// end-sanitize-vr5400
f2b30012
AC		 4542{
4543 unsigned32 instruction = instruction_0;
055ee297
AC		 4544 int destreg = ((instruction >> 6) & 0x0000001F);
4545 int fs = ((instruction >> 11) & 0x0000001F);
4546 int ft = ((instruction >> 16) & 0x0000001F);
4547 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4548 {
4549 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4550 }
4551}
4552
4553
4554// NMSUB.fmt
055ee297 4555010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
f2b30012
AC		 4556"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4557*mipsIV:
23850e92 4558*vr5000:
15232df4
FCE		 4559// start-sanitize-vr4320
4560*vr4320:
4561// end-sanitize-vr4320
90ad43b2
AC		 4562// start-sanitize-vr5400
4563*vr5400:
4564// end-sanitize-vr5400
f2b30012
AC		 4565{
4566 unsigned32 instruction = instruction_0;
055ee297
AC		 4567 int destreg = ((instruction >> 6) & 0x0000001F);
4568 int fs = ((instruction >> 11) & 0x0000001F);
4569 int ft = ((instruction >> 16) & 0x0000001F);
4570 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4571 {
4572 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4573 }
4574}
4575
4576
4577// NMSUB.fmt
055ee297 4578010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
f2b30012
AC		 4579"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4580*mipsIV:
23850e92 4581*vr5000:
15232df4
FCE		 4582// start-sanitize-vr4320
4583*vr4320:
4584// end-sanitize-vr4320
90ad43b2
AC		 4585// start-sanitize-vr5400
4586*vr5400:
4587// end-sanitize-vr5400
f2b30012
AC		 4588{
4589 unsigned32 instruction = instruction_0;
055ee297
AC		 4590 int destreg = ((instruction >> 6) & 0x0000001F);
4591 int fs = ((instruction >> 11) & 0x0000001F);
4592 int ft = ((instruction >> 16) & 0x0000001F);
4593 int fr = ((instruction >> 21) & 0x0000001F);
f2b30012
AC		 4594 {
4595 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4596 }
4597}
4598
4599
4600010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
49a6eed5 4601"prefx <HINT>, r<INDEX>(r<BASE>)"
f2b30012 4602*mipsIV:
23850e92 4603*vr5000:
15232df4
FCE		 4604// start-sanitize-vr4320
4605*vr4320:
4606// end-sanitize-vr4320
90ad43b2
AC		 4607// start-sanitize-vr5400
4608*vr5400:
4609// end-sanitize-vr5400
f2b30012
AC		 4610{
4611 unsigned32 instruction = instruction_0;
055ee297
AC		 4612 int fs = ((instruction >> 11) & 0x0000001F);
4613 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4614 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 4615 {
49a76833
AC		 4616 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4617 address_word paddr;
f2b30012
AC		 4618 int uncached;
4619 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4620 Prefetch(uncached,paddr,vaddr,isDATA,fs);
4621 }
4622}
4623
4624010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4625*mipsIV:
4626"recip.%s<FMT> f<FD>, f<FS>"
23850e92 4627*vr5000:
15232df4
FCE		 4628// start-sanitize-vr4320
4629*vr4320:
4630// end-sanitize-vr4320
90ad43b2
AC		 4631// start-sanitize-vr5400
4632*vr5400:
4633// end-sanitize-vr5400
f2b30012
AC		 4634{
4635 unsigned32 instruction = instruction_0;
055ee297
AC		 4636 int destreg = ((instruction >> 6) & 0x0000001F);
4637 int fs = ((instruction >> 11) & 0x0000001F);
4638 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4639 {
4640 if ((format != fmt_single) && (format != fmt_double))
4641 SignalException(ReservedInstruction,instruction);
4642 else
4643 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4644 }
4645}
4646
4647
4648010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
49a6eed5 4649"round.l.%s<FMT> f<FD>, f<FS>"
f2b30012
AC		 4650*mipsIII:
4651*mipsIV:
23850e92 4652*vr5000:
15232df4
FCE		 4653// start-sanitize-vr4320
4654*vr4320:
4655// end-sanitize-vr4320
90ad43b2
AC		 4656// start-sanitize-vr5400
4657*vr5400:
4658// end-sanitize-vr5400
f2b30012
AC		 4659// start-sanitize-r5900
4660*r5900:
4661// end-sanitize-r5900
4662*r3900:
4663// start-sanitize-tx19
4664*tx19:
4665// end-sanitize-tx19
4666{
4667 unsigned32 instruction = instruction_0;
055ee297
AC		 4668 int destreg = ((instruction >> 6) & 0x0000001F);
4669 int fs = ((instruction >> 11) & 0x0000001F);
4670 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4671 {
4672 if ((format != fmt_single) && (format != fmt_double))
4673 SignalException(ReservedInstruction,instruction);
4674 else
4675 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4676 }
4677}
4678
4679
4680010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
49a6eed5 4681"round.w.%s<FMT> f<FD>, f<FS>"
f2b30012
AC		 4682*mipsII:
4683*mipsIII:
4684*mipsIV:
23850e92 4685*vr5000:
15232df4
FCE		 4686// start-sanitize-vr4320
4687*vr4320:
4688// end-sanitize-vr4320
90ad43b2
AC		 4689// start-sanitize-vr5400
4690*vr5400:
4691// end-sanitize-vr5400
f2b30012
AC		 4692// start-sanitize-r5900
4693*r5900:
4694// end-sanitize-r5900
4695*r3900:
4696// start-sanitize-tx19
4697*tx19:
4698// end-sanitize-tx19
4699{
4700 unsigned32 instruction = instruction_0;
055ee297
AC		 4701 int destreg = ((instruction >> 6) & 0x0000001F);
4702 int fs = ((instruction >> 11) & 0x0000001F);
4703 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4704 {
4705 if ((format != fmt_single) && (format != fmt_double))
4706 SignalException(ReservedInstruction,instruction);
4707 else
4708 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4709 }
4710}
4711
4712
4713010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4714*mipsIV:
4715"rsqrt.%s<FMT> f<FD>, f<FS>"
23850e92 4716*vr5000:
15232df4
FCE		 4717// start-sanitize-vr4320
4718*vr4320:
4719// end-sanitize-vr4320
90ad43b2
AC		 4720// start-sanitize-vr5400
4721*vr5400:
4722// end-sanitize-vr5400
f2b30012
AC		 4723{
4724 unsigned32 instruction = instruction_0;
055ee297
AC		 4725 int destreg = ((instruction >> 6) & 0x0000001F);
4726 int fs = ((instruction >> 11) & 0x0000001F);
4727 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4728 {
4729 if ((format != fmt_single) && (format != fmt_double))
4730 SignalException(ReservedInstruction,instruction);
4731 else
085c1cb9 4732 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
f2b30012
AC		 4733 }
4734}
4735
4736
030843d7
AC		 4737111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
4738"sdc1 f<FT>, <OFFSET>(r<BASE>)"
4739*mipsII:
4740*mipsIII:
4741*mipsIV:
23850e92 4742*vr5000:
15232df4
FCE		 4743// start-sanitize-vr4320
4744*vr4320:
4745// end-sanitize-vr4320
030843d7
AC		 4746// start-sanitize-vr5400
4747*vr5400:
4748// end-sanitize-vr5400
4749*r3900:
4750// start-sanitize-tx19
4751*tx19:
4752// end-sanitize-tx19
4753{
ebcfd86a 4754 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
030843d7 4755}
f2b30012
AC		 4756
4757
ebcfd86a
FCE		 4758010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
4759"ldxc1 f<FS>, r<INDEX>(r<BASE>)"
f2b30012 4760*mipsIV:
23850e92 4761*vr5000:
15232df4
FCE		 4762// start-sanitize-vr4320
4763*vr4320:
4764// end-sanitize-vr4320
90ad43b2
AC		 4765// start-sanitize-vr5400
4766*vr5400:
4767// end-sanitize-vr5400
f2b30012 4768{
ebcfd86a 4769 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
f2b30012
AC		 4770}
4771
4772
4773010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
4774"sqrt.%s<FMT> f<FD>, f<FS>"
4775*mipsII:
4776*mipsIII:
4777*mipsIV:
23850e92 4778*vr5000:
15232df4
FCE		 4779// start-sanitize-vr4320
4780*vr4320:
4781// end-sanitize-vr4320
90ad43b2
AC		 4782// start-sanitize-vr5400
4783*vr5400:
4784// end-sanitize-vr5400
f2b30012
AC		 4785*r3900:
4786// start-sanitize-tx19
4787*tx19:
4788// end-sanitize-tx19
4789{
4790 unsigned32 instruction = instruction_0;
055ee297
AC		 4791 int destreg = ((instruction >> 6) & 0x0000001F);
4792 int fs = ((instruction >> 11) & 0x0000001F);
4793 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4794 {
4795 if ((format != fmt_single) && (format != fmt_double))
4796 SignalException(ReservedInstruction,instruction);
4797 else
4798 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4799 }
4800}
4801
4802
4803010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
4804"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
23850e92
JL		 4805*mipsI,mipsII,mipsIII,mipsIV:
4806*vr5000:
15232df4
FCE		 4807// start-sanitize-vr4320
4808*vr4320:
4809// end-sanitize-vr4320
90ad43b2
AC		 4810// start-sanitize-vr5400
4811*vr5400:
4812// end-sanitize-vr5400
f2b30012
AC		 4813*r3900:
4814// start-sanitize-tx19
4815*tx19:
4816// end-sanitize-tx19
4817{
4818 unsigned32 instruction = instruction_0;
055ee297
AC		 4819 int destreg = ((instruction >> 6) & 0x0000001F);
4820 int fs = ((instruction >> 11) & 0x0000001F);
4821 int ft = ((instruction >> 16) & 0x0000001F);
4822 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4823 {
4824 if ((format != fmt_single) && (format != fmt_double))
4825 SignalException(ReservedInstruction,instruction);
4826 else
4827 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4828 }
4829}
4830
4831
f2b30012 4832
030843d7
AC		 4833111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
4834"swc1 f<FT>, <OFFSET>(r<BASE>)"
23850e92
JL		 4835*mipsI,mipsII,mipsIII,mipsIV:
4836*vr5000:
15232df4
FCE		 4837// start-sanitize-vr4320
4838*vr4320:
4839// end-sanitize-vr4320
90ad43b2
AC		 4840// start-sanitize-vr5400
4841*vr5400:
4842// end-sanitize-vr5400
f2b30012
AC		 4843// start-sanitize-r5900
4844*r5900:
4845// end-sanitize-r5900
030843d7
AC		 4846*r3900:
4847// start-sanitize-tx19
4848*tx19:
4849// end-sanitize-tx19
4850{
4851 unsigned32 instruction = instruction_0;
4852 signed_word offset = EXTEND16 (OFFSET);
4853 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
4854 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
4855 {
4856 address_word vaddr = ((uword64)op1 + offset);
4857 address_word paddr;
4858 int uncached;
4859 if ((vaddr & 3) != 0)
4860 SignalExceptionAddressStore();
4861 else
4862 {
4863 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4864 {
4865 uword64 memval = 0;
4866 uword64 memval1 = 0;
4867 uword64 mask = 0x7;
4868 unsigned int byte;
4869 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4870 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4871 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
4872 {
4873 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4874 }
4875 }
4876 }
4877 }
4878}
4879
4880
4881010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
4882"swxc1 f<FS>, r<INDEX>(r<BASE>)"
4883*mipsIV:
23850e92 4884*vr5000:
15232df4
FCE		 4885// start-sanitize-vr4320
4886*vr4320:
4887// end-sanitize-vr4320
030843d7
AC		 4888// start-sanitize-vr5400
4889*vr5400:
4890// end-sanitize-vr5400
f2b30012
AC		 4891{
4892 unsigned32 instruction = instruction_0;
055ee297
AC		 4893 int fs = ((instruction >> 11) & 0x0000001F);
4894 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4895 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 4896 {
49a76833
AC		 4897 address_word vaddr = ((unsigned64)op1 + op2);
4898 address_word paddr;
f2b30012
AC		 4899 int uncached;
4900 if ((vaddr & 3) != 0)
055ee297 4901 SignalExceptionAddressStore();
f2b30012
AC		 4902 else
4903 {
4904 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4905 {
4906 unsigned64 memval = 0;
4907 unsigned64 memval1 = 0;
4908 unsigned64 mask = 0x7;
4909 unsigned int byte;
4910 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4911 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4912 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
4913 {
4914 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4915 }
4916 }
4917 }
4918 }
4919}
4920
4921
4922010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
4923"trunc.l.%s<FMT> f<FD>, f<FS>"
4924*mipsIII:
4925*mipsIV:
23850e92 4926*vr5000:
15232df4
FCE		 4927// start-sanitize-vr4320
4928*vr4320:
4929// end-sanitize-vr4320
90ad43b2
AC		 4930// start-sanitize-vr5400
4931*vr5400:
4932// end-sanitize-vr5400
f2b30012
AC		 4933// start-sanitize-r5900
4934*r5900:
4935// end-sanitize-r5900
4936*r3900:
4937// start-sanitize-tx19
4938*tx19:
4939// end-sanitize-tx19
4940{
4941 unsigned32 instruction = instruction_0;
055ee297
AC		 4942 int destreg = ((instruction >> 6) & 0x0000001F);
4943 int fs = ((instruction >> 11) & 0x0000001F);
4944 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4945 {
4946 if ((format != fmt_single) && (format != fmt_double))
4947 SignalException(ReservedInstruction,instruction);
4948 else
4949 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
4950 }
4951}
4952
4953
4954010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
4955"trunc.w.%s<FMT> f<FD>, f<FS>"
4956*mipsII:
4957*mipsIII:
4958*mipsIV:
23850e92 4959*vr5000:
15232df4
FCE		 4960// start-sanitize-vr4320
4961*vr4320:
4962// end-sanitize-vr4320
90ad43b2
AC		 4963// start-sanitize-vr5400
4964*vr5400:
4965// end-sanitize-vr5400
f2b30012
AC		 4966// start-sanitize-r5900
4967*r5900:
4968// end-sanitize-r5900
4969*r3900:
4970// start-sanitize-tx19
4971*tx19:
4972// end-sanitize-tx19
4973{
4974 unsigned32 instruction = instruction_0;
055ee297
AC		 4975 int destreg = ((instruction >> 6) & 0x0000001F);
4976 int fs = ((instruction >> 11) & 0x0000001F);
4977 int format = ((instruction >> 21) & 0x00000007);
f2b30012
AC		 4978 {
4979 if ((format != fmt_single) && (format != fmt_double))
4980 SignalException(ReservedInstruction,instruction);
4981 else
4982 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
4983 }
4984}
4985
4986\f
4987//
4988// MIPS Architecture:
4989//
4990// System Control Instruction Set (COP0)
4991//
4992
4993
4994010000,01000,00000,16.OFFSET:COP0:32::BC0F
4995"bc0f <OFFSET>"
23850e92
JL		 4996*mipsI,mipsII,mipsIII,mipsIV:
4997*vr5000:
15232df4
FCE		 4998// start-sanitize-vr4320
4999*vr4320:
5000// end-sanitize-vr4320
90ad43b2
AC		 5001// start-sanitize-vr5400
5002*vr5400:
5003// end-sanitize-vr5400
f2b30012
AC		 5004// start-sanitize-r5900
5005*r5900:
5006// end-sanitize-r5900
5007
5008
5009010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5010"bc0fl <OFFSET>"
23850e92
JL		 5011*mipsI,mipsII,mipsIII,mipsIV:
5012*vr5000:
15232df4
FCE		 5013// start-sanitize-vr4320
5014*vr4320:
5015// end-sanitize-vr4320
90ad43b2
AC		 5016// start-sanitize-vr5400
5017*vr5400:
5018// end-sanitize-vr5400
f2b30012
AC		 5019// start-sanitize-r5900
5020*r5900:
5021// end-sanitize-r5900
5022
5023
5024010000,01000,00001,16.OFFSET:COP0:32::BC0T
5025"bc0t <OFFSET>"
23850e92 5026*mipsI,mipsII,mipsIII,mipsIV:
f2b30012
AC		 5027// start-sanitize-r5900
5028*r5900:
5029// end-sanitize-r5900
5030
5031
5032
49a6eed5 5033010000,01000,00011,16.OFFSET:COP0:32::BC0TL
f2b30012 5034"bc0tl <OFFSET>"
23850e92
JL		 5035*mipsI,mipsII,mipsIII,mipsIV:
5036*vr5000:
15232df4
FCE		 5037// start-sanitize-vr4320
5038*vr4320:
5039// end-sanitize-vr4320
90ad43b2
AC		 5040// start-sanitize-vr5400
5041*vr5400:
5042// end-sanitize-vr5400
f2b30012
AC		 5043// start-sanitize-r5900
5044*r5900:
5045// end-sanitize-r5900
5046
5047
5048101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5049*mipsIII:
5050*mipsIV:
23850e92 5051*vr5000:
15232df4
FCE		 5052// start-sanitize-vr4320
5053*vr4320:
5054// end-sanitize-vr4320
90ad43b2
AC		 5055// start-sanitize-vr5400
5056*vr5400:
5057// end-sanitize-vr5400
f2b30012
AC		 5058// start-sanitize-r5900
5059*r5900:
5060// end-sanitize-r5900
5061*r3900:
5062// start-sanitize-tx19
5063*tx19:
5064// end-sanitize-tx19
5065{
5066 unsigned32 instruction = instruction_0;
055ee297
AC		 5067 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5068 int hint = ((instruction >> 16) & 0x0000001F);
5069 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
f2b30012 5070 {
49a76833
AC		 5071 address_word vaddr = (op1 + offset);
5072 address_word paddr;
f2b30012
AC		 5073 int uncached;
5074 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5075 CacheOp(hint,vaddr,paddr,instruction);
5076 }
5077}
5078
5079
5080010000,10000,000000000000000,111001:COP0:32::DI
5081"di"
23850e92
JL		 5082*mipsI,mipsII,mipsIII,mipsIV:
5083*vr5000:
15232df4
FCE		 5084// start-sanitize-vr4320
5085*vr4320:
5086// end-sanitize-vr4320
90ad43b2
AC		 5087// start-sanitize-vr5400
5088*vr5400:
5089// end-sanitize-vr5400
f2b30012
AC		 5090// start-sanitize-r5900
5091*r5900:
5092// end-sanitize-r5900
5093
5094
5095010000,10000,000000000000000,111000:COP0:32::EI
5096"ei"
23850e92
JL		 5097*mipsI,mipsII,mipsIII,mipsIV:
5098*vr5000:
15232df4
FCE		 5099// start-sanitize-vr4320
5100*vr4320:
5101// end-sanitize-vr4320
90ad43b2
AC		 5102// start-sanitize-vr5400
5103*vr5400:
5104// end-sanitize-vr5400
f2b30012
AC		 5105// start-sanitize-r5900
5106*r5900:
5107// end-sanitize-r5900
5108
5109
5110010000,10000,000000000000000,011000:COP0:32::ERET
5111"eret"
5112*mipsIII:
5113*mipsIV:
23850e92 5114*vr5000:
15232df4
FCE		 5115// start-sanitize-vr4320
5116*vr4320:
5117// end-sanitize-vr4320
90ad43b2
AC		 5118// start-sanitize-vr5400
5119*vr5400:
5120// end-sanitize-vr5400
f2b30012
AC		 5121// start-sanitize-r5900
5122*r5900:
5123// end-sanitize-r5900
5124
5125
49a6eed5
AC		 5126010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5127"mfc0 r<RT>, r<RD> # <REGX>"
23850e92
JL		 5128*mipsI,mipsII,mipsIII,mipsIV:
5129*vr5000:
15232df4
FCE		 5130// start-sanitize-vr4320
5131*vr4320:
5132// end-sanitize-vr4320
90ad43b2
AC		 5133// start-sanitize-vr5400
5134*vr5400:
5135// end-sanitize-vr5400
f2b30012
AC		 5136// start-sanitize-r5900
5137*r5900:
5138// end-sanitize-r5900
030843d7
AC		 5139{
5140 DecodeCoproc (instruction_0);
5141}
f2b30012 5142
49a6eed5
AC		 5143010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5144"mtc0 r<RT>, r<RD> # <REGX>"
23850e92 5145*mipsI,mipsII,mipsIII,mipsIV:
ebcfd86a 5146*r3900:
15232df4
FCE		 5147// start-sanitize-vr4320
5148*vr4320:
5149// end-sanitize-vr4320
ebcfd86a 5150*vr5000:
90ad43b2
AC		 5151// start-sanitize-vr5400
5152*vr5400:
5153// end-sanitize-vr5400
f2b30012
AC		 5154// start-sanitize-r5900
5155*r5900:
5156// end-sanitize-r5900
030843d7
AC		 5157{
5158 DecodeCoproc (instruction_0);
5159}
f2b30012
AC		 5160
5161
5162010000,10000,000000000000000,001000:COP0:32::TLBP
5163"tlbp"
23850e92
JL		 5164*mipsI,mipsII,mipsIII,mipsIV:
5165*vr5000:
15232df4
FCE		 5166// start-sanitize-vr4320
5167*vr4320:
5168// end-sanitize-vr4320
90ad43b2
AC		 5169// start-sanitize-vr5400
5170*vr5400:
5171// end-sanitize-vr5400
f2b30012
AC		 5172// start-sanitize-r5900
5173*r5900:
5174// end-sanitize-r5900
5175
5176
5177010000,10000,000000000000000,000001:COP0:32::TLBR
5178"tlbr"
23850e92
JL		 5179*mipsI,mipsII,mipsIII,mipsIV:
5180*vr5000:
15232df4
FCE		 5181// start-sanitize-vr4320
5182*vr4320:
5183// end-sanitize-vr4320
90ad43b2
AC		 5184// start-sanitize-vr5400
5185*vr5400:
5186// end-sanitize-vr5400
f2b30012
AC		 5187// start-sanitize-r5900
5188*r5900:
5189// end-sanitize-r5900
5190
5191
5192010000,10000,000000000000000,000010:COP0:32::TLBWI
5193"tlbwi"
23850e92
JL		 5194*mipsI,mipsII,mipsIII,mipsIV:
5195*vr5000:
15232df4
FCE		 5196// start-sanitize-vr4320
5197*vr4320:
5198// end-sanitize-vr4320
90ad43b2
AC		 5199// start-sanitize-vr5400
5200*vr5400:
5201// end-sanitize-vr5400
f2b30012
AC		 5202// start-sanitize-r5900
5203*r5900:
5204// end-sanitize-r5900
5205
5206
5207010000,10000,000000000000000,000110:COP0:32::TLBWR
5208"tlbwr"
23850e92
JL		 5209*mipsI,mipsII,mipsIII,mipsIV:
5210*vr5000:
15232df4
FCE		 5211// start-sanitize-vr4320
5212*vr4320:
5213// end-sanitize-vr4320
90ad43b2
AC		 5214// start-sanitize-vr5400
5215*vr5400:
5216// end-sanitize-vr5400
f2b30012
AC		 5217// start-sanitize-r5900
5218*r5900:
5219// end-sanitize-r5900
5220
5221\f
a48e8c8d 5222:include:16::m16.igen
15232df4
FCE		 5223// start-sanitize-vr4320
5224:include::vr4320:vr4320.igen
5225// end-sanitize-vr4320
16bd5d6e 5226// start-sanitize-vr5400
89d09738 5227:include::vr5400:vr5400.igen
a48e8c8d 5228:include:64,f::mdmx.igen
16bd5d6e 5229// end-sanitize-vr5400
f2b30012 5230// start-sanitize-r5900
89d09738 5231:include::r5900:r5900.igen
f2b30012 5232// end-sanitize-r5900
ebcfd86a 5233:include:::tx.igen
f2b30012
AC		 5234\f
5235// start-sanitize-cygnus-never
5236
49a6eed5
AC		 5237// // FIXME FIXME FIXME What is this instruction?
5238// 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5239// *mipsI:
5240// *mipsII:
5241// *mipsIII:
5242// *mipsIV:
5243// // start-sanitize-r5900
5244// *r5900:
5245// // end-sanitize-r5900
5246// *r3900:
5247// // start-sanitize-tx19
5248// *tx19:
5249// // end-sanitize-tx19
5250// {
5251// unsigned32 instruction = instruction_0;
055ee297
AC		 5252// signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5253// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5254// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
49a6eed5
AC		 5255// {
5256// if (CoProcPresent(3))
5257// SignalException(CoProcessorUnusable);
5258// else
5259// SignalException(ReservedInstruction,instruction);
5260// }
5261// }
5262
5263// end-sanitize-cygnus-never
5264// start-sanitize-cygnus-never
5265
5266// // FIXME FIXME FIXME What is this?
5267// 11100,******,00001:RR:16::SDBBP
5268// *mips16:
5269// {
5270// unsigned32 instruction = instruction_0;
5271// if (have_extendval)
5272// SignalException (ReservedInstruction, instruction);
5273// {
5274// SignalException(DebugBreakPoint,instruction);
5275// }
5276// }
f2b30012
AC		 5277
5278// end-sanitize-cygnus-never
5279// start-sanitize-cygnus-never
5280
49a6eed5
AC		 5281// // FIXME FIXME FIXME What is this?
5282// 000000,********************,001110:SPECIAL:32::SDBBP
5283// *r3900:
5284// {
5285// unsigned32 instruction = instruction_0;
5286// {
5287// SignalException(DebugBreakPoint,instruction);
5288// }
5289// }
f2b30012
AC		 5290
5291// end-sanitize-cygnus-never
5292// start-sanitize-cygnus-never
5293
49a6eed5
AC		 5294// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5295// // isn't yet reconized by this simulator.
5296// 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5297// *vr4100:
5298// {
5299// unsigned32 instruction = instruction_0;
055ee297
AC		 5300// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5301// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
49a6eed5
AC		 5302// {
5303// CHECKHILO("Multiply-Add");
5304// {
5305// unsigned64 temp = (op1 * op2);
5306// temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5307// LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5308// HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5309// }
5310// }
5311// }
f2b30012
AC		 5312
5313// end-sanitize-cygnus-never
49a6eed5
AC		 5314// start-sanitize-cygnus-never
5315
5316// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5317// // isn't yet reconized by this simulator.
5318// 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5319// *vr4100:
5320// {
5321// unsigned32 instruction = instruction_0;
055ee297
AC		 5322// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5323// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
49a6eed5
AC		 5324// {
5325// CHECKHILO("Multiply-Add");
5326// {
5327// unsigned64 temp = (op1 * op2);
5328// LO = LO + temp;
5329// }
5330// }
5331// }
5332
a48e8c8d 5333// end-sanitize-cygnus-never
GDB Binutils - Deliverables
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