Commit | Line | Data |
---|---|---|
c906108c SS |
1 | // -*- C -*- |
2 | // | |
3 | // In mips.igen, the semantics for many of the instructions were created | |
4 | // using code generated by gencode. Those semantic segments could be | |
5 | // greatly simplified. | |
6 | // | |
7 | // <insn> ::= | |
8 | // <insn-word> { "+" <insn-word> } | |
9 | // ":" <format-name> | |
10 | // ":" <filter-flags> | |
11 | // ":" <options> | |
12 | // ":" <name> | |
13 | // <nl> | |
14 | // { <insn-model> } | |
15 | // { <insn-mnemonic> } | |
16 | // <code-block> | |
17 | // | |
18 | ||
19 | ||
20 | // IGEN config - mips16 | |
21 | // :option:16::insn-bit-size:16 | |
22 | // :option:16::hi-bit-nr:15 | |
23 | :option:16::insn-specifying-widths:true | |
24 | :option:16::gen-delayed-branch:false | |
25 | ||
26 | // IGEN config - mips32/64.. | |
27 | // :option:32::insn-bit-size:32 | |
28 | // :option:32::hi-bit-nr:31 | |
29 | :option:32::insn-specifying-widths:true | |
30 | :option:32::gen-delayed-branch:false | |
31 | ||
32 | ||
33 | // Generate separate simulators for each target | |
34 | // :option:::multi-sim:true | |
35 | ||
36 | ||
074e9cb8 | 37 | // Models known by this simulator are defined below. |
c5d00cc7 CD |
38 | // |
39 | // When placing models in the instruction descriptions, please place | |
40 | // them one per line, in the order given here. | |
074e9cb8 CD |
41 | |
42 | // MIPS ISAs: | |
43 | // | |
44 | // Instructions and related functions for these models are included in | |
45 | // this file. | |
c906108c SS |
46 | :model:::mipsI:mips3000: |
47 | :model:::mipsII:mips6000: | |
48 | :model:::mipsIII:mips4000: | |
49 | :model:::mipsIV:mips8000: | |
603a98e7 | 50 | :model:::mipsV:mipsisaV: |
074e9cb8 CD |
51 | |
52 | // Vendor ISAs: | |
53 | // | |
54 | // Standard MIPS ISA instructions used for these models are listed here, | |
55 | // as are functions needed by those standard instructions. Instructions | |
56 | // which are model-dependent and which are not in the standard MIPS ISAs | |
57 | // (or which pre-date or use different encodings than the standard | |
58 | // instructions) are (for the most part) in separate .igen files. | |
59 | :model:::vr4100:mips4100: // vr.igen | |
c906108c | 60 | :model:::vr5000:mips5000: |
074e9cb8 | 61 | :model:::r3900:mips3900: // tx.igen |
c906108c | 62 | |
074e9cb8 CD |
63 | // MIPS Application Specific Extensions (ASEs) |
64 | // | |
65 | // Instructions for the ASEs are in separate .igen files. | |
66 | :model:::mips16:mips16: // m16.igen (and m16.dc) | |
c906108c SS |
67 | |
68 | ||
69 | // Pseudo instructions known by IGEN | |
70 | :internal::::illegal: | |
71 | { | |
72 | SignalException (ReservedInstruction, 0); | |
73 | } | |
74 | ||
75 | ||
76 | // Pseudo instructions known by interp.c | |
77 | // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK | |
78 | 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD | |
79 | "rsvd <OP>" | |
80 | { | |
81 | SignalException (ReservedInstruction, instruction_0); | |
82 | } | |
83 | ||
84 | ||
85 | ||
86 | // Helper: | |
87 | // | |
88 | // Simulate a 32 bit delayslot instruction | |
89 | // | |
90 | ||
91 | :function:::address_word:delayslot32:address_word target | |
92 | { | |
93 | instruction_word delay_insn; | |
94 | sim_events_slip (SD, 1); | |
95 | DSPC = CIA; | |
96 | CIA = CIA + 4; /* NOTE not mips16 */ | |
97 | STATE |= simDELAYSLOT; | |
98 | delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ | |
d4f3574e | 99 | ENGINE_ISSUE_PREFIX_HOOK(); |
c906108c SS |
100 | idecode_issue (CPU_, delay_insn, (CIA)); |
101 | STATE &= ~simDELAYSLOT; | |
102 | return target; | |
103 | } | |
104 | ||
105 | :function:::address_word:nullify_next_insn32: | |
106 | { | |
107 | sim_events_slip (SD, 1); | |
108 | dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction"); | |
109 | return CIA + 8; | |
110 | } | |
111 | ||
09297648 CD |
112 | |
113 | // Helper: | |
114 | // | |
115 | // Calculate an effective address given a base and an offset. | |
116 | // | |
117 | ||
118 | :function:::address_word:loadstore_ea:address_word base, address_word offset | |
119 | *mipsI: | |
120 | *mipsII: | |
121 | *mipsIII: | |
122 | *mipsIV: | |
123 | *mipsV: | |
124 | *vr4100: | |
125 | *vr5000: | |
126 | *r3900: | |
127 | { | |
128 | return base + offset; | |
129 | } | |
130 | ||
131 | ||
c906108c | 132 | // Helper: |
4a0bd876 | 133 | // |
c906108c SS |
134 | // Check that an access to a HI/LO register meets timing requirements |
135 | // | |
136 | // The following requirements exist: | |
137 | // | |
138 | // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read | |
139 | // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read | |
140 | // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update | |
141 | // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}. | |
142 | // | |
143 | ||
144 | :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new | |
145 | { | |
146 | if (history->mf.timestamp + 3 > time) | |
147 | { | |
148 | sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n", | |
149 | itable[MY_INDEX].name, | |
150 | new, (long) CIA, | |
4a0bd876 | 151 | (long) history->mf.cia); |
c906108c SS |
152 | return 0; |
153 | } | |
154 | return 1; | |
155 | } | |
156 | ||
157 | :function:::int:check_mt_hilo:hilo_history *history | |
c5d00cc7 CD |
158 | *mipsI: |
159 | *mipsII: | |
160 | *mipsIII: | |
161 | *mipsIV: | |
603a98e7 | 162 | *mipsV: |
c906108c SS |
163 | *vr4100: |
164 | *vr5000: | |
165 | { | |
166 | signed64 time = sim_events_time (SD); | |
167 | int ok = check_mf_cycles (SD_, history, time, "MT"); | |
168 | history->mt.timestamp = time; | |
169 | history->mt.cia = CIA; | |
170 | return ok; | |
171 | } | |
172 | ||
173 | :function:::int:check_mt_hilo:hilo_history *history | |
174 | *r3900: | |
175 | { | |
176 | signed64 time = sim_events_time (SD); | |
177 | history->mt.timestamp = time; | |
178 | history->mt.cia = CIA; | |
179 | return 1; | |
180 | } | |
181 | ||
182 | ||
183 | :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer | |
c5d00cc7 CD |
184 | *mipsI: |
185 | *mipsII: | |
186 | *mipsIII: | |
187 | *mipsIV: | |
603a98e7 | 188 | *mipsV: |
c906108c SS |
189 | *vr4100: |
190 | *vr5000: | |
191 | *r3900: | |
192 | { | |
193 | signed64 time = sim_events_time (SD); | |
194 | int ok = 1; | |
195 | if (peer != NULL | |
196 | && peer->mt.timestamp > history->op.timestamp | |
197 | && history->mt.timestamp < history->op.timestamp | |
198 | && ! (history->mf.timestamp > history->op.timestamp | |
199 | && history->mf.timestamp < peer->mt.timestamp) | |
200 | && ! (peer->mf.timestamp > history->op.timestamp | |
201 | && peer->mf.timestamp < peer->mt.timestamp)) | |
202 | { | |
203 | /* The peer has been written to since the last OP yet we have | |
204 | not */ | |
205 | sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n", | |
206 | itable[MY_INDEX].name, | |
207 | (long) CIA, | |
208 | (long) history->op.cia, | |
4a0bd876 | 209 | (long) peer->mt.cia); |
c906108c SS |
210 | ok = 0; |
211 | } | |
212 | history->mf.timestamp = time; | |
213 | history->mf.cia = CIA; | |
214 | return ok; | |
215 | } | |
216 | ||
217 | ||
218 | ||
219 | :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo | |
c5d00cc7 CD |
220 | *mipsI: |
221 | *mipsII: | |
222 | *mipsIII: | |
223 | *mipsIV: | |
603a98e7 | 224 | *mipsV: |
c906108c SS |
225 | *vr4100: |
226 | *vr5000: | |
227 | { | |
228 | signed64 time = sim_events_time (SD); | |
229 | int ok = (check_mf_cycles (SD_, hi, time, "OP") | |
230 | && check_mf_cycles (SD_, lo, time, "OP")); | |
231 | hi->op.timestamp = time; | |
232 | lo->op.timestamp = time; | |
233 | hi->op.cia = CIA; | |
234 | lo->op.cia = CIA; | |
235 | return ok; | |
236 | } | |
237 | ||
238 | // The r3900 mult and multu insns _can_ be exectuted immediatly after | |
239 | // a mf{hi,lo} | |
240 | :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo | |
241 | *r3900: | |
242 | { | |
243 | /* FIXME: could record the fact that a stall occured if we want */ | |
244 | signed64 time = sim_events_time (SD); | |
245 | hi->op.timestamp = time; | |
246 | lo->op.timestamp = time; | |
247 | hi->op.cia = CIA; | |
248 | lo->op.cia = CIA; | |
249 | return 1; | |
250 | } | |
251 | ||
252 | ||
253 | :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo | |
c5d00cc7 CD |
254 | *mipsI: |
255 | *mipsII: | |
256 | *mipsIII: | |
257 | *mipsIV: | |
603a98e7 | 258 | *mipsV: |
c906108c SS |
259 | *vr4100: |
260 | *vr5000: | |
261 | *r3900: | |
262 | { | |
263 | signed64 time = sim_events_time (SD); | |
264 | int ok = (check_mf_cycles (SD_, hi, time, "OP") | |
265 | && check_mf_cycles (SD_, lo, time, "OP")); | |
266 | hi->op.timestamp = time; | |
267 | lo->op.timestamp = time; | |
268 | hi->op.cia = CIA; | |
269 | lo->op.cia = CIA; | |
270 | return ok; | |
271 | } | |
272 | ||
273 | ||
ca971540 | 274 | // Helper: |
4a0bd876 | 275 | // |
ca971540 CD |
276 | // Check that the 64-bit instruction can currently be used, and signal |
277 | // an ReservedInstruction exception if not. | |
278 | // | |
279 | ||
280 | :function:::void:check_u64:instruction_word insn | |
281 | *mipsIII: | |
282 | *mipsIV: | |
283 | *mipsV: | |
284 | *vr4100: | |
285 | *vr5000: | |
286 | { | |
287 | // On mips64, if UserMode check SR:PX & SR:UX bits. | |
288 | // The check should be similar to mips64 for any with PX/UX bit equivalents. | |
289 | } | |
c906108c SS |
290 | |
291 | ||
292 | ||
293 | // | |
074e9cb8 | 294 | // MIPS Architecture: |
c906108c | 295 | // |
603a98e7 | 296 | // CPU Instruction Set (mipsI - mipsV) |
c906108c SS |
297 | // |
298 | ||
299 | ||
300 | ||
301 | 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD | |
302 | "add r<RD>, r<RS>, r<RT>" | |
c5d00cc7 CD |
303 | *mipsI: |
304 | *mipsII: | |
305 | *mipsIII: | |
306 | *mipsIV: | |
603a98e7 | 307 | *mipsV: |
c906108c SS |
308 | *vr4100: |
309 | *vr5000: | |
310 | *r3900: | |
311 | { | |
312 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); | |
313 | { | |
314 | ALU32_BEGIN (GPR[RS]); | |
315 | ALU32_ADD (GPR[RT]); | |
9805e229 | 316 | ALU32_END (GPR[RD]); /* This checks for overflow. */ |
c906108c SS |
317 | } |
318 | TRACE_ALU_RESULT (GPR[RD]); | |
319 | } | |
320 | ||
321 | ||
322 | ||
323 | 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI | |
20ae0098 | 324 | "addi r<RT>, r<RS>, <IMMEDIATE>" |
c5d00cc7 CD |
325 | *mipsI: |
326 | *mipsII: | |
327 | *mipsIII: | |
328 | *mipsIV: | |
603a98e7 | 329 | *mipsV: |
c906108c SS |
330 | *vr4100: |
331 | *vr5000: | |
332 | *r3900: | |
333 | { | |
334 | TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE)); | |
335 | { | |
336 | ALU32_BEGIN (GPR[RS]); | |
337 | ALU32_ADD (EXTEND16 (IMMEDIATE)); | |
9805e229 | 338 | ALU32_END (GPR[RT]); /* This checks for overflow. */ |
c906108c SS |
339 | } |
340 | TRACE_ALU_RESULT (GPR[RT]); | |
341 | } | |
342 | ||
343 | ||
344 | ||
345 | :function:::void:do_addiu:int rs, int rt, unsigned16 immediate | |
346 | { | |
347 | TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); | |
348 | GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate)); | |
349 | TRACE_ALU_RESULT (GPR[rt]); | |
350 | } | |
351 | ||
352 | 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU | |
353 | "addiu r<RT>, r<RS>, <IMMEDIATE>" | |
c5d00cc7 CD |
354 | *mipsI: |
355 | *mipsII: | |
356 | *mipsIII: | |
357 | *mipsIV: | |
603a98e7 | 358 | *mipsV: |
c906108c SS |
359 | *vr4100: |
360 | *vr5000: | |
361 | *r3900: | |
362 | { | |
363 | do_addiu (SD_, RS, RT, IMMEDIATE); | |
364 | } | |
365 | ||
366 | ||
367 | ||
368 | :function:::void:do_addu:int rs, int rt, int rd | |
369 | { | |
370 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
371 | GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]); | |
372 | TRACE_ALU_RESULT (GPR[rd]); | |
373 | } | |
374 | ||
375 | 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU | |
376 | "addu r<RD>, r<RS>, r<RT>" | |
c5d00cc7 CD |
377 | *mipsI: |
378 | *mipsII: | |
379 | *mipsIII: | |
380 | *mipsIV: | |
603a98e7 | 381 | *mipsV: |
c906108c SS |
382 | *vr4100: |
383 | *vr5000: | |
384 | *r3900: | |
385 | { | |
386 | do_addu (SD_, RS, RT, RD); | |
387 | } | |
388 | ||
389 | ||
390 | ||
391 | :function:::void:do_and:int rs, int rt, int rd | |
392 | { | |
393 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
394 | GPR[rd] = GPR[rs] & GPR[rt]; | |
395 | TRACE_ALU_RESULT (GPR[rd]); | |
396 | } | |
397 | ||
398 | 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND | |
399 | "and r<RD>, r<RS>, r<RT>" | |
c5d00cc7 CD |
400 | *mipsI: |
401 | *mipsII: | |
402 | *mipsIII: | |
403 | *mipsIV: | |
603a98e7 | 404 | *mipsV: |
c906108c SS |
405 | *vr4100: |
406 | *vr5000: | |
407 | *r3900: | |
408 | { | |
409 | do_and (SD_, RS, RT, RD); | |
410 | } | |
411 | ||
412 | ||
413 | ||
414 | 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI | |
415 | "and r<RT>, r<RS>, <IMMEDIATE>" | |
c5d00cc7 CD |
416 | *mipsI: |
417 | *mipsII: | |
418 | *mipsIII: | |
419 | *mipsIV: | |
603a98e7 | 420 | *mipsV: |
c906108c SS |
421 | *vr4100: |
422 | *vr5000: | |
423 | *r3900: | |
424 | { | |
425 | TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE); | |
426 | GPR[RT] = GPR[RS] & IMMEDIATE; | |
427 | TRACE_ALU_RESULT (GPR[RT]); | |
428 | } | |
429 | ||
430 | ||
431 | ||
432 | 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ | |
433 | "beq r<RS>, r<RT>, <OFFSET>" | |
c5d00cc7 CD |
434 | *mipsI: |
435 | *mipsII: | |
436 | *mipsIII: | |
437 | *mipsIV: | |
603a98e7 | 438 | *mipsV: |
c906108c SS |
439 | *vr4100: |
440 | *vr5000: | |
441 | *r3900: | |
442 | { | |
443 | address_word offset = EXTEND16 (OFFSET) << 2; | |
444 | check_branch_bug (); | |
445 | if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) | |
446 | { | |
447 | mark_branch_bug (NIA+offset); | |
448 | DELAY_SLOT (NIA + offset); | |
449 | } | |
450 | } | |
451 | ||
452 | ||
453 | ||
454 | 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL | |
455 | "beql r<RS>, r<RT>, <OFFSET>" | |
456 | *mipsII: | |
457 | *mipsIII: | |
458 | *mipsIV: | |
603a98e7 | 459 | *mipsV: |
c906108c SS |
460 | *vr4100: |
461 | *vr5000: | |
462 | *r3900: | |
463 | { | |
464 | address_word offset = EXTEND16 (OFFSET) << 2; | |
465 | check_branch_bug (); | |
466 | if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) | |
467 | { | |
468 | mark_branch_bug (NIA+offset); | |
469 | DELAY_SLOT (NIA + offset); | |
470 | } | |
471 | else | |
472 | NULLIFY_NEXT_INSTRUCTION (); | |
473 | } | |
474 | ||
475 | ||
476 | ||
477 | 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ | |
478 | "bgez r<RS>, <OFFSET>" | |
c5d00cc7 CD |
479 | *mipsI: |
480 | *mipsII: | |
481 | *mipsIII: | |
482 | *mipsIV: | |
603a98e7 | 483 | *mipsV: |
c906108c SS |
484 | *vr4100: |
485 | *vr5000: | |
486 | *r3900: | |
487 | { | |
488 | address_word offset = EXTEND16 (OFFSET) << 2; | |
489 | check_branch_bug (); | |
490 | if ((signed_word) GPR[RS] >= 0) | |
491 | { | |
492 | mark_branch_bug (NIA+offset); | |
493 | DELAY_SLOT (NIA + offset); | |
494 | } | |
495 | } | |
496 | ||
497 | ||
498 | ||
499 | 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL | |
500 | "bgezal r<RS>, <OFFSET>" | |
c5d00cc7 CD |
501 | *mipsI: |
502 | *mipsII: | |
503 | *mipsIII: | |
504 | *mipsIV: | |
603a98e7 | 505 | *mipsV: |
c906108c SS |
506 | *vr4100: |
507 | *vr5000: | |
508 | *r3900: | |
509 | { | |
510 | address_word offset = EXTEND16 (OFFSET) << 2; | |
511 | check_branch_bug (); | |
512 | RA = (CIA + 8); | |
513 | if ((signed_word) GPR[RS] >= 0) | |
514 | { | |
515 | mark_branch_bug (NIA+offset); | |
516 | DELAY_SLOT (NIA + offset); | |
517 | } | |
518 | } | |
519 | ||
520 | ||
521 | ||
522 | 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL | |
523 | "bgezall r<RS>, <OFFSET>" | |
524 | *mipsII: | |
525 | *mipsIII: | |
526 | *mipsIV: | |
603a98e7 | 527 | *mipsV: |
c906108c SS |
528 | *vr4100: |
529 | *vr5000: | |
530 | *r3900: | |
531 | { | |
532 | address_word offset = EXTEND16 (OFFSET) << 2; | |
533 | check_branch_bug (); | |
534 | RA = (CIA + 8); | |
535 | /* NOTE: The branch occurs AFTER the next instruction has been | |
536 | executed */ | |
537 | if ((signed_word) GPR[RS] >= 0) | |
538 | { | |
539 | mark_branch_bug (NIA+offset); | |
540 | DELAY_SLOT (NIA + offset); | |
541 | } | |
542 | else | |
543 | NULLIFY_NEXT_INSTRUCTION (); | |
544 | } | |
545 | ||
546 | ||
547 | ||
548 | 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL | |
549 | "bgezl r<RS>, <OFFSET>" | |
550 | *mipsII: | |
551 | *mipsIII: | |
552 | *mipsIV: | |
603a98e7 | 553 | *mipsV: |
c906108c SS |
554 | *vr4100: |
555 | *vr5000: | |
556 | *r3900: | |
557 | { | |
558 | address_word offset = EXTEND16 (OFFSET) << 2; | |
559 | check_branch_bug (); | |
560 | if ((signed_word) GPR[RS] >= 0) | |
561 | { | |
562 | mark_branch_bug (NIA+offset); | |
563 | DELAY_SLOT (NIA + offset); | |
564 | } | |
565 | else | |
566 | NULLIFY_NEXT_INSTRUCTION (); | |
567 | } | |
568 | ||
569 | ||
570 | ||
571 | 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ | |
572 | "bgtz r<RS>, <OFFSET>" | |
c5d00cc7 CD |
573 | *mipsI: |
574 | *mipsII: | |
575 | *mipsIII: | |
576 | *mipsIV: | |
603a98e7 | 577 | *mipsV: |
c906108c SS |
578 | *vr4100: |
579 | *vr5000: | |
580 | *r3900: | |
581 | { | |
582 | address_word offset = EXTEND16 (OFFSET) << 2; | |
583 | check_branch_bug (); | |
584 | if ((signed_word) GPR[RS] > 0) | |
585 | { | |
586 | mark_branch_bug (NIA+offset); | |
587 | DELAY_SLOT (NIA + offset); | |
588 | } | |
589 | } | |
590 | ||
591 | ||
592 | ||
593 | 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL | |
594 | "bgtzl r<RS>, <OFFSET>" | |
595 | *mipsII: | |
596 | *mipsIII: | |
597 | *mipsIV: | |
603a98e7 | 598 | *mipsV: |
c906108c SS |
599 | *vr4100: |
600 | *vr5000: | |
601 | *r3900: | |
602 | { | |
603 | address_word offset = EXTEND16 (OFFSET) << 2; | |
604 | check_branch_bug (); | |
605 | /* NOTE: The branch occurs AFTER the next instruction has been | |
606 | executed */ | |
607 | if ((signed_word) GPR[RS] > 0) | |
608 | { | |
609 | mark_branch_bug (NIA+offset); | |
610 | DELAY_SLOT (NIA + offset); | |
611 | } | |
612 | else | |
613 | NULLIFY_NEXT_INSTRUCTION (); | |
614 | } | |
615 | ||
616 | ||
617 | ||
618 | 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ | |
619 | "blez r<RS>, <OFFSET>" | |
c5d00cc7 CD |
620 | *mipsI: |
621 | *mipsII: | |
622 | *mipsIII: | |
623 | *mipsIV: | |
603a98e7 | 624 | *mipsV: |
c906108c SS |
625 | *vr4100: |
626 | *vr5000: | |
627 | *r3900: | |
628 | { | |
629 | address_word offset = EXTEND16 (OFFSET) << 2; | |
630 | check_branch_bug (); | |
631 | /* NOTE: The branch occurs AFTER the next instruction has been | |
632 | executed */ | |
633 | if ((signed_word) GPR[RS] <= 0) | |
634 | { | |
635 | mark_branch_bug (NIA+offset); | |
636 | DELAY_SLOT (NIA + offset); | |
637 | } | |
638 | } | |
639 | ||
640 | ||
641 | ||
642 | 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL | |
643 | "bgezl r<RS>, <OFFSET>" | |
644 | *mipsII: | |
645 | *mipsIII: | |
646 | *mipsIV: | |
603a98e7 | 647 | *mipsV: |
c906108c SS |
648 | *vr4100: |
649 | *vr5000: | |
650 | *r3900: | |
651 | { | |
652 | address_word offset = EXTEND16 (OFFSET) << 2; | |
653 | check_branch_bug (); | |
654 | if ((signed_word) GPR[RS] <= 0) | |
655 | { | |
656 | mark_branch_bug (NIA+offset); | |
657 | DELAY_SLOT (NIA + offset); | |
658 | } | |
659 | else | |
660 | NULLIFY_NEXT_INSTRUCTION (); | |
661 | } | |
662 | ||
663 | ||
664 | ||
665 | 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ | |
666 | "bltz r<RS>, <OFFSET>" | |
c5d00cc7 CD |
667 | *mipsI: |
668 | *mipsII: | |
669 | *mipsIII: | |
670 | *mipsIV: | |
603a98e7 | 671 | *mipsV: |
c906108c SS |
672 | *vr4100: |
673 | *vr5000: | |
674 | *r3900: | |
675 | { | |
676 | address_word offset = EXTEND16 (OFFSET) << 2; | |
677 | check_branch_bug (); | |
678 | if ((signed_word) GPR[RS] < 0) | |
679 | { | |
680 | mark_branch_bug (NIA+offset); | |
681 | DELAY_SLOT (NIA + offset); | |
682 | } | |
683 | } | |
684 | ||
685 | ||
686 | ||
687 | 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL | |
688 | "bltzal r<RS>, <OFFSET>" | |
c5d00cc7 CD |
689 | *mipsI: |
690 | *mipsII: | |
691 | *mipsIII: | |
692 | *mipsIV: | |
603a98e7 | 693 | *mipsV: |
c906108c SS |
694 | *vr4100: |
695 | *vr5000: | |
696 | *r3900: | |
697 | { | |
698 | address_word offset = EXTEND16 (OFFSET) << 2; | |
699 | check_branch_bug (); | |
700 | RA = (CIA + 8); | |
701 | /* NOTE: The branch occurs AFTER the next instruction has been | |
702 | executed */ | |
703 | if ((signed_word) GPR[RS] < 0) | |
704 | { | |
705 | mark_branch_bug (NIA+offset); | |
706 | DELAY_SLOT (NIA + offset); | |
707 | } | |
708 | } | |
709 | ||
710 | ||
711 | ||
712 | 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL | |
713 | "bltzall r<RS>, <OFFSET>" | |
714 | *mipsII: | |
715 | *mipsIII: | |
716 | *mipsIV: | |
603a98e7 | 717 | *mipsV: |
c906108c SS |
718 | *vr4100: |
719 | *vr5000: | |
720 | *r3900: | |
721 | { | |
722 | address_word offset = EXTEND16 (OFFSET) << 2; | |
723 | check_branch_bug (); | |
724 | RA = (CIA + 8); | |
725 | if ((signed_word) GPR[RS] < 0) | |
726 | { | |
727 | mark_branch_bug (NIA+offset); | |
728 | DELAY_SLOT (NIA + offset); | |
729 | } | |
730 | else | |
731 | NULLIFY_NEXT_INSTRUCTION (); | |
732 | } | |
733 | ||
734 | ||
735 | ||
736 | 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL | |
737 | "bltzl r<RS>, <OFFSET>" | |
738 | *mipsII: | |
739 | *mipsIII: | |
740 | *mipsIV: | |
603a98e7 | 741 | *mipsV: |
c906108c SS |
742 | *vr4100: |
743 | *vr5000: | |
744 | *r3900: | |
745 | { | |
746 | address_word offset = EXTEND16 (OFFSET) << 2; | |
747 | check_branch_bug (); | |
748 | /* NOTE: The branch occurs AFTER the next instruction has been | |
749 | executed */ | |
750 | if ((signed_word) GPR[RS] < 0) | |
751 | { | |
752 | mark_branch_bug (NIA+offset); | |
753 | DELAY_SLOT (NIA + offset); | |
754 | } | |
755 | else | |
756 | NULLIFY_NEXT_INSTRUCTION (); | |
757 | } | |
758 | ||
759 | ||
760 | ||
761 | 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE | |
762 | "bne r<RS>, r<RT>, <OFFSET>" | |
c5d00cc7 CD |
763 | *mipsI: |
764 | *mipsII: | |
765 | *mipsIII: | |
766 | *mipsIV: | |
603a98e7 | 767 | *mipsV: |
c906108c SS |
768 | *vr4100: |
769 | *vr5000: | |
770 | *r3900: | |
771 | { | |
772 | address_word offset = EXTEND16 (OFFSET) << 2; | |
773 | check_branch_bug (); | |
774 | if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) | |
775 | { | |
776 | mark_branch_bug (NIA+offset); | |
777 | DELAY_SLOT (NIA + offset); | |
778 | } | |
779 | } | |
780 | ||
781 | ||
782 | ||
783 | 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL | |
784 | "bnel r<RS>, r<RT>, <OFFSET>" | |
785 | *mipsII: | |
786 | *mipsIII: | |
787 | *mipsIV: | |
603a98e7 | 788 | *mipsV: |
c906108c SS |
789 | *vr4100: |
790 | *vr5000: | |
791 | *r3900: | |
792 | { | |
793 | address_word offset = EXTEND16 (OFFSET) << 2; | |
794 | check_branch_bug (); | |
795 | if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) | |
796 | { | |
797 | mark_branch_bug (NIA+offset); | |
798 | DELAY_SLOT (NIA + offset); | |
799 | } | |
800 | else | |
801 | NULLIFY_NEXT_INSTRUCTION (); | |
802 | } | |
803 | ||
804 | ||
805 | ||
806 | 000000,20.CODE,001101:SPECIAL:32::BREAK | |
20ae0098 | 807 | "break <CODE>" |
c5d00cc7 CD |
808 | *mipsI: |
809 | *mipsII: | |
810 | *mipsIII: | |
811 | *mipsIV: | |
603a98e7 | 812 | *mipsV: |
c906108c SS |
813 | *vr4100: |
814 | *vr5000: | |
815 | *r3900: | |
816 | { | |
817 | /* Check for some break instruction which are reserved for use by the simulator. */ | |
818 | unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK; | |
819 | if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) || | |
820 | break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) | |
821 | { | |
822 | sim_engine_halt (SD, CPU, NULL, cia, | |
823 | sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); | |
824 | } | |
825 | else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) || | |
826 | break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) | |
827 | { | |
828 | if (STATE & simDELAYSLOT) | |
829 | PC = cia - 4; /* reference the branch instruction */ | |
830 | else | |
831 | PC = cia; | |
832 | SignalException(BreakPoint, instruction_0); | |
833 | } | |
834 | ||
835 | else | |
836 | { | |
4a0bd876 | 837 | /* If we get this far, we're not an instruction reserved by the sim. Raise |
c906108c SS |
838 | the exception. */ |
839 | SignalException(BreakPoint, instruction_0); | |
840 | } | |
841 | } | |
842 | ||
843 | ||
844 | ||
c906108c SS |
845 | 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD |
846 | "dadd r<RD>, r<RS>, r<RT>" | |
847 | *mipsIII: | |
848 | *mipsIV: | |
603a98e7 | 849 | *mipsV: |
c906108c SS |
850 | *vr4100: |
851 | *vr5000: | |
852 | { | |
ca971540 | 853 | check_u64 (SD_, instruction_0); |
c906108c SS |
854 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); |
855 | { | |
856 | ALU64_BEGIN (GPR[RS]); | |
857 | ALU64_ADD (GPR[RT]); | |
9805e229 | 858 | ALU64_END (GPR[RD]); /* This checks for overflow. */ |
c906108c SS |
859 | } |
860 | TRACE_ALU_RESULT (GPR[RD]); | |
861 | } | |
862 | ||
863 | ||
864 | ||
865 | 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI | |
866 | "daddi r<RT>, r<RS>, <IMMEDIATE>" | |
867 | *mipsIII: | |
868 | *mipsIV: | |
603a98e7 | 869 | *mipsV: |
c906108c SS |
870 | *vr4100: |
871 | *vr5000: | |
872 | { | |
ca971540 | 873 | check_u64 (SD_, instruction_0); |
c906108c SS |
874 | TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE)); |
875 | { | |
876 | ALU64_BEGIN (GPR[RS]); | |
877 | ALU64_ADD (EXTEND16 (IMMEDIATE)); | |
9805e229 | 878 | ALU64_END (GPR[RT]); /* This checks for overflow. */ |
c906108c SS |
879 | } |
880 | TRACE_ALU_RESULT (GPR[RT]); | |
881 | } | |
882 | ||
883 | ||
884 | ||
885 | :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate | |
886 | { | |
887 | TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); | |
888 | GPR[rt] = GPR[rs] + EXTEND16 (immediate); | |
889 | TRACE_ALU_RESULT (GPR[rt]); | |
890 | } | |
891 | ||
892 | 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU | |
20ae0098 | 893 | "daddiu r<RT>, r<RS>, <IMMEDIATE>" |
c906108c SS |
894 | *mipsIII: |
895 | *mipsIV: | |
603a98e7 | 896 | *mipsV: |
c906108c SS |
897 | *vr4100: |
898 | *vr5000: | |
899 | { | |
ca971540 | 900 | check_u64 (SD_, instruction_0); |
c906108c SS |
901 | do_daddiu (SD_, RS, RT, IMMEDIATE); |
902 | } | |
903 | ||
904 | ||
905 | ||
906 | :function:::void:do_daddu:int rs, int rt, int rd | |
907 | { | |
908 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
909 | GPR[rd] = GPR[rs] + GPR[rt]; | |
910 | TRACE_ALU_RESULT (GPR[rd]); | |
911 | } | |
912 | ||
913 | 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU | |
914 | "daddu r<RD>, r<RS>, r<RT>" | |
915 | *mipsIII: | |
916 | *mipsIV: | |
603a98e7 | 917 | *mipsV: |
c906108c SS |
918 | *vr4100: |
919 | *vr5000: | |
920 | { | |
ca971540 | 921 | check_u64 (SD_, instruction_0); |
c906108c SS |
922 | do_daddu (SD_, RS, RT, RD); |
923 | } | |
924 | ||
925 | ||
926 | ||
927 | :function:::void:do_ddiv:int rs, int rt | |
928 | { | |
929 | check_div_hilo (SD_, HIHISTORY, LOHISTORY); | |
930 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
931 | { | |
932 | signed64 n = GPR[rs]; | |
933 | signed64 d = GPR[rt]; | |
934 | signed64 hi; | |
935 | signed64 lo; | |
936 | if (d == 0) | |
937 | { | |
938 | lo = SIGNED64 (0x8000000000000000); | |
939 | hi = 0; | |
940 | } | |
941 | else if (d == -1 && n == SIGNED64 (0x8000000000000000)) | |
942 | { | |
943 | lo = SIGNED64 (0x8000000000000000); | |
944 | hi = 0; | |
945 | } | |
946 | else | |
947 | { | |
948 | lo = (n / d); | |
949 | hi = (n % d); | |
950 | } | |
951 | HI = hi; | |
952 | LO = lo; | |
953 | } | |
954 | TRACE_ALU_RESULT2 (HI, LO); | |
955 | } | |
956 | ||
f701dad2 | 957 | 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV |
c906108c SS |
958 | "ddiv r<RS>, r<RT>" |
959 | *mipsIII: | |
960 | *mipsIV: | |
603a98e7 | 961 | *mipsV: |
c906108c SS |
962 | *vr4100: |
963 | *vr5000: | |
964 | { | |
ca971540 | 965 | check_u64 (SD_, instruction_0); |
c906108c SS |
966 | do_ddiv (SD_, RS, RT); |
967 | } | |
968 | ||
969 | ||
970 | ||
971 | :function:::void:do_ddivu:int rs, int rt | |
972 | { | |
973 | check_div_hilo (SD_, HIHISTORY, LOHISTORY); | |
974 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
975 | { | |
976 | unsigned64 n = GPR[rs]; | |
977 | unsigned64 d = GPR[rt]; | |
978 | unsigned64 hi; | |
979 | unsigned64 lo; | |
980 | if (d == 0) | |
981 | { | |
982 | lo = SIGNED64 (0x8000000000000000); | |
983 | hi = 0; | |
984 | } | |
985 | else | |
986 | { | |
987 | lo = (n / d); | |
988 | hi = (n % d); | |
989 | } | |
990 | HI = hi; | |
991 | LO = lo; | |
992 | } | |
993 | TRACE_ALU_RESULT2 (HI, LO); | |
994 | } | |
995 | ||
996 | 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU | |
997 | "ddivu r<RS>, r<RT>" | |
998 | *mipsIII: | |
999 | *mipsIV: | |
603a98e7 | 1000 | *mipsV: |
c906108c SS |
1001 | *vr4100: |
1002 | *vr5000: | |
1003 | { | |
ca971540 | 1004 | check_u64 (SD_, instruction_0); |
c906108c SS |
1005 | do_ddivu (SD_, RS, RT); |
1006 | } | |
1007 | ||
1008 | ||
1009 | ||
1010 | :function:::void:do_div:int rs, int rt | |
1011 | { | |
1012 | check_div_hilo (SD_, HIHISTORY, LOHISTORY); | |
1013 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
1014 | { | |
1015 | signed32 n = GPR[rs]; | |
1016 | signed32 d = GPR[rt]; | |
1017 | if (d == 0) | |
1018 | { | |
1019 | LO = EXTEND32 (0x80000000); | |
1020 | HI = EXTEND32 (0); | |
1021 | } | |
1022 | else if (n == SIGNED32 (0x80000000) && d == -1) | |
1023 | { | |
1024 | LO = EXTEND32 (0x80000000); | |
1025 | HI = EXTEND32 (0); | |
1026 | } | |
1027 | else | |
1028 | { | |
1029 | LO = EXTEND32 (n / d); | |
1030 | HI = EXTEND32 (n % d); | |
1031 | } | |
1032 | } | |
1033 | TRACE_ALU_RESULT2 (HI, LO); | |
1034 | } | |
1035 | ||
f701dad2 | 1036 | 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV |
c906108c | 1037 | "div r<RS>, r<RT>" |
c5d00cc7 CD |
1038 | *mipsI: |
1039 | *mipsII: | |
1040 | *mipsIII: | |
1041 | *mipsIV: | |
603a98e7 | 1042 | *mipsV: |
c906108c SS |
1043 | *vr4100: |
1044 | *vr5000: | |
1045 | *r3900: | |
1046 | { | |
1047 | do_div (SD_, RS, RT); | |
1048 | } | |
1049 | ||
1050 | ||
1051 | ||
1052 | :function:::void:do_divu:int rs, int rt | |
1053 | { | |
1054 | check_div_hilo (SD_, HIHISTORY, LOHISTORY); | |
1055 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
1056 | { | |
1057 | unsigned32 n = GPR[rs]; | |
1058 | unsigned32 d = GPR[rt]; | |
1059 | if (d == 0) | |
1060 | { | |
1061 | LO = EXTEND32 (0x80000000); | |
1062 | HI = EXTEND32 (0); | |
1063 | } | |
3e1dca16 CD |
1064 | else |
1065 | { | |
1066 | LO = EXTEND32 (n / d); | |
1067 | HI = EXTEND32 (n % d); | |
1068 | } | |
c906108c SS |
1069 | } |
1070 | TRACE_ALU_RESULT2 (HI, LO); | |
1071 | } | |
1072 | ||
f701dad2 | 1073 | 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU |
c906108c | 1074 | "divu r<RS>, r<RT>" |
c5d00cc7 CD |
1075 | *mipsI: |
1076 | *mipsII: | |
1077 | *mipsIII: | |
1078 | *mipsIV: | |
603a98e7 | 1079 | *mipsV: |
c906108c SS |
1080 | *vr4100: |
1081 | *vr5000: | |
1082 | *r3900: | |
1083 | { | |
1084 | do_divu (SD_, RS, RT); | |
1085 | } | |
1086 | ||
1087 | ||
1088 | ||
1089 | :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p | |
1090 | { | |
1091 | unsigned64 lo; | |
1092 | unsigned64 hi; | |
1093 | unsigned64 m00; | |
1094 | unsigned64 m01; | |
1095 | unsigned64 m10; | |
1096 | unsigned64 m11; | |
1097 | unsigned64 mid; | |
1098 | int sign; | |
1099 | unsigned64 op1 = GPR[rs]; | |
1100 | unsigned64 op2 = GPR[rt]; | |
1101 | check_mult_hilo (SD_, HIHISTORY, LOHISTORY); | |
1102 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
4a0bd876 | 1103 | /* make signed multiply unsigned */ |
c906108c SS |
1104 | sign = 0; |
1105 | if (signed_p) | |
1106 | { | |
1107 | if (op1 < 0) | |
1108 | { | |
1109 | op1 = - op1; | |
1110 | ++sign; | |
1111 | } | |
1112 | if (op2 < 0) | |
1113 | { | |
1114 | op2 = - op2; | |
1115 | ++sign; | |
1116 | } | |
1117 | } | |
67f5c7ef | 1118 | /* multiply out the 4 sub products */ |
c906108c SS |
1119 | m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2)); |
1120 | m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2)); | |
1121 | m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2)); | |
1122 | m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2)); | |
1123 | /* add the products */ | |
1124 | mid = ((unsigned64) VH4_8 (m00) | |
1125 | + (unsigned64) VL4_8 (m10) | |
1126 | + (unsigned64) VL4_8 (m01)); | |
1127 | lo = U8_4 (mid, m00); | |
1128 | hi = (m11 | |
1129 | + (unsigned64) VH4_8 (mid) | |
1130 | + (unsigned64) VH4_8 (m01) | |
1131 | + (unsigned64) VH4_8 (m10)); | |
1132 | /* fix the sign */ | |
1133 | if (sign & 1) | |
1134 | { | |
1135 | lo = -lo; | |
1136 | if (lo == 0) | |
1137 | hi = -hi; | |
1138 | else | |
1139 | hi = -hi - 1; | |
1140 | } | |
1141 | /* save the result HI/LO (and a gpr) */ | |
1142 | LO = lo; | |
1143 | HI = hi; | |
1144 | if (rd != 0) | |
1145 | GPR[rd] = lo; | |
1146 | TRACE_ALU_RESULT2 (HI, LO); | |
1147 | } | |
1148 | ||
1149 | :function:::void:do_dmult:int rs, int rt, int rd | |
1150 | { | |
1151 | do_dmultx (SD_, rs, rt, rd, 1); | |
1152 | } | |
1153 | ||
f701dad2 | 1154 | 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT |
c906108c | 1155 | "dmult r<RS>, r<RT>" |
c5d00cc7 CD |
1156 | *mipsIII: |
1157 | *mipsIV: | |
603a98e7 | 1158 | *mipsV: |
c906108c SS |
1159 | *vr4100: |
1160 | { | |
ca971540 | 1161 | check_u64 (SD_, instruction_0); |
c906108c SS |
1162 | do_dmult (SD_, RS, RT, 0); |
1163 | } | |
1164 | ||
f701dad2 | 1165 | 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT |
c906108c SS |
1166 | "dmult r<RS>, r<RT>":RD == 0 |
1167 | "dmult r<RD>, r<RS>, r<RT>" | |
1168 | *vr5000: | |
1169 | { | |
ca971540 | 1170 | check_u64 (SD_, instruction_0); |
c906108c SS |
1171 | do_dmult (SD_, RS, RT, RD); |
1172 | } | |
1173 | ||
1174 | ||
1175 | ||
1176 | :function:::void:do_dmultu:int rs, int rt, int rd | |
1177 | { | |
1178 | do_dmultx (SD_, rs, rt, rd, 0); | |
1179 | } | |
1180 | ||
f701dad2 | 1181 | 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU |
c906108c | 1182 | "dmultu r<RS>, r<RT>" |
c5d00cc7 CD |
1183 | *mipsIII: |
1184 | *mipsIV: | |
603a98e7 | 1185 | *mipsV: |
c906108c SS |
1186 | *vr4100: |
1187 | { | |
ca971540 | 1188 | check_u64 (SD_, instruction_0); |
c906108c SS |
1189 | do_dmultu (SD_, RS, RT, 0); |
1190 | } | |
1191 | ||
f701dad2 | 1192 | 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU |
c906108c SS |
1193 | "dmultu r<RD>, r<RS>, r<RT>":RD == 0 |
1194 | "dmultu r<RS>, r<RT>" | |
1195 | *vr5000: | |
1196 | { | |
ca971540 | 1197 | check_u64 (SD_, instruction_0); |
c906108c SS |
1198 | do_dmultu (SD_, RS, RT, RD); |
1199 | } | |
1200 | ||
1201 | :function:::void:do_dsll:int rt, int rd, int shift | |
1202 | { | |
fff8d27d | 1203 | TRACE_ALU_INPUT2 (GPR[rt], shift); |
c906108c | 1204 | GPR[rd] = GPR[rt] << shift; |
fff8d27d | 1205 | TRACE_ALU_RESULT (GPR[rd]); |
c906108c SS |
1206 | } |
1207 | ||
f701dad2 | 1208 | 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL |
c906108c SS |
1209 | "dsll r<RD>, r<RT>, <SHIFT>" |
1210 | *mipsIII: | |
1211 | *mipsIV: | |
603a98e7 | 1212 | *mipsV: |
c906108c SS |
1213 | *vr4100: |
1214 | *vr5000: | |
1215 | { | |
ca971540 | 1216 | check_u64 (SD_, instruction_0); |
c906108c SS |
1217 | do_dsll (SD_, RT, RD, SHIFT); |
1218 | } | |
1219 | ||
1220 | ||
f701dad2 | 1221 | 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32 |
c906108c SS |
1222 | "dsll32 r<RD>, r<RT>, <SHIFT>" |
1223 | *mipsIII: | |
1224 | *mipsIV: | |
603a98e7 | 1225 | *mipsV: |
c906108c SS |
1226 | *vr4100: |
1227 | *vr5000: | |
1228 | { | |
1229 | int s = 32 + SHIFT; | |
ca971540 | 1230 | check_u64 (SD_, instruction_0); |
fff8d27d | 1231 | TRACE_ALU_INPUT2 (GPR[RT], s); |
c906108c | 1232 | GPR[RD] = GPR[RT] << s; |
fff8d27d | 1233 | TRACE_ALU_RESULT (GPR[RD]); |
c906108c SS |
1234 | } |
1235 | ||
3e1dca16 CD |
1236 | :function:::void:do_dsllv:int rs, int rt, int rd |
1237 | { | |
1238 | int s = MASKED64 (GPR[rs], 5, 0); | |
1239 | TRACE_ALU_INPUT2 (GPR[rt], s); | |
1240 | GPR[rd] = GPR[rt] << s; | |
1241 | TRACE_ALU_RESULT (GPR[rd]); | |
1242 | } | |
1243 | ||
f701dad2 | 1244 | 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV |
c906108c SS |
1245 | "dsllv r<RD>, r<RT>, r<RS>" |
1246 | *mipsIII: | |
1247 | *mipsIV: | |
603a98e7 | 1248 | *mipsV: |
c906108c SS |
1249 | *vr4100: |
1250 | *vr5000: | |
1251 | { | |
ca971540 | 1252 | check_u64 (SD_, instruction_0); |
c906108c SS |
1253 | do_dsllv (SD_, RS, RT, RD); |
1254 | } | |
1255 | ||
1256 | :function:::void:do_dsra:int rt, int rd, int shift | |
1257 | { | |
fff8d27d | 1258 | TRACE_ALU_INPUT2 (GPR[rt], shift); |
c906108c | 1259 | GPR[rd] = ((signed64) GPR[rt]) >> shift; |
fff8d27d | 1260 | TRACE_ALU_RESULT (GPR[rd]); |
c906108c SS |
1261 | } |
1262 | ||
1263 | ||
f701dad2 | 1264 | 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA |
c906108c SS |
1265 | "dsra r<RD>, r<RT>, <SHIFT>" |
1266 | *mipsIII: | |
1267 | *mipsIV: | |
603a98e7 | 1268 | *mipsV: |
c906108c SS |
1269 | *vr4100: |
1270 | *vr5000: | |
1271 | { | |
ca971540 | 1272 | check_u64 (SD_, instruction_0); |
c906108c SS |
1273 | do_dsra (SD_, RT, RD, SHIFT); |
1274 | } | |
1275 | ||
1276 | ||
f701dad2 | 1277 | 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32 |
bb22bd7d | 1278 | "dsra32 r<RD>, r<RT>, <SHIFT>" |
c906108c SS |
1279 | *mipsIII: |
1280 | *mipsIV: | |
603a98e7 | 1281 | *mipsV: |
c906108c SS |
1282 | *vr4100: |
1283 | *vr5000: | |
1284 | { | |
1285 | int s = 32 + SHIFT; | |
ca971540 | 1286 | check_u64 (SD_, instruction_0); |
fff8d27d | 1287 | TRACE_ALU_INPUT2 (GPR[RT], s); |
c906108c | 1288 | GPR[RD] = ((signed64) GPR[RT]) >> s; |
fff8d27d | 1289 | TRACE_ALU_RESULT (GPR[RD]); |
c906108c SS |
1290 | } |
1291 | ||
1292 | ||
1293 | :function:::void:do_dsrav:int rs, int rt, int rd | |
1294 | { | |
1295 | int s = MASKED64 (GPR[rs], 5, 0); | |
1296 | TRACE_ALU_INPUT2 (GPR[rt], s); | |
1297 | GPR[rd] = ((signed64) GPR[rt]) >> s; | |
1298 | TRACE_ALU_RESULT (GPR[rd]); | |
1299 | } | |
1300 | ||
f701dad2 | 1301 | 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV |
bb22bd7d | 1302 | "dsrav r<RD>, r<RT>, r<RS>" |
c906108c SS |
1303 | *mipsIII: |
1304 | *mipsIV: | |
603a98e7 | 1305 | *mipsV: |
c906108c SS |
1306 | *vr4100: |
1307 | *vr5000: | |
1308 | { | |
ca971540 | 1309 | check_u64 (SD_, instruction_0); |
c906108c SS |
1310 | do_dsrav (SD_, RS, RT, RD); |
1311 | } | |
1312 | ||
1313 | :function:::void:do_dsrl:int rt, int rd, int shift | |
1314 | { | |
fff8d27d | 1315 | TRACE_ALU_INPUT2 (GPR[rt], shift); |
c906108c | 1316 | GPR[rd] = (unsigned64) GPR[rt] >> shift; |
fff8d27d | 1317 | TRACE_ALU_RESULT (GPR[rd]); |
c906108c SS |
1318 | } |
1319 | ||
1320 | ||
f701dad2 | 1321 | 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL |
c906108c SS |
1322 | "dsrl r<RD>, r<RT>, <SHIFT>" |
1323 | *mipsIII: | |
1324 | *mipsIV: | |
603a98e7 | 1325 | *mipsV: |
c906108c SS |
1326 | *vr4100: |
1327 | *vr5000: | |
1328 | { | |
ca971540 | 1329 | check_u64 (SD_, instruction_0); |
c906108c SS |
1330 | do_dsrl (SD_, RT, RD, SHIFT); |
1331 | } | |
1332 | ||
1333 | ||
f701dad2 | 1334 | 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32 |
c906108c SS |
1335 | "dsrl32 r<RD>, r<RT>, <SHIFT>" |
1336 | *mipsIII: | |
1337 | *mipsIV: | |
603a98e7 | 1338 | *mipsV: |
c906108c SS |
1339 | *vr4100: |
1340 | *vr5000: | |
1341 | { | |
1342 | int s = 32 + SHIFT; | |
ca971540 | 1343 | check_u64 (SD_, instruction_0); |
fff8d27d | 1344 | TRACE_ALU_INPUT2 (GPR[RT], s); |
c906108c | 1345 | GPR[RD] = (unsigned64) GPR[RT] >> s; |
fff8d27d | 1346 | TRACE_ALU_RESULT (GPR[RD]); |
c906108c SS |
1347 | } |
1348 | ||
1349 | ||
1350 | :function:::void:do_dsrlv:int rs, int rt, int rd | |
1351 | { | |
1352 | int s = MASKED64 (GPR[rs], 5, 0); | |
fff8d27d | 1353 | TRACE_ALU_INPUT2 (GPR[rt], s); |
c906108c | 1354 | GPR[rd] = (unsigned64) GPR[rt] >> s; |
fff8d27d | 1355 | TRACE_ALU_RESULT (GPR[rd]); |
c906108c SS |
1356 | } |
1357 | ||
1358 | ||
1359 | ||
f701dad2 | 1360 | 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV |
20ae0098 | 1361 | "dsrlv r<RD>, r<RT>, r<RS>" |
c906108c SS |
1362 | *mipsIII: |
1363 | *mipsIV: | |
603a98e7 | 1364 | *mipsV: |
c906108c SS |
1365 | *vr4100: |
1366 | *vr5000: | |
1367 | { | |
ca971540 | 1368 | check_u64 (SD_, instruction_0); |
c906108c SS |
1369 | do_dsrlv (SD_, RS, RT, RD); |
1370 | } | |
1371 | ||
1372 | ||
f701dad2 | 1373 | 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB |
c906108c SS |
1374 | "dsub r<RD>, r<RS>, r<RT>" |
1375 | *mipsIII: | |
1376 | *mipsIV: | |
603a98e7 | 1377 | *mipsV: |
c906108c SS |
1378 | *vr4100: |
1379 | *vr5000: | |
1380 | { | |
ca971540 | 1381 | check_u64 (SD_, instruction_0); |
c906108c SS |
1382 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); |
1383 | { | |
1384 | ALU64_BEGIN (GPR[RS]); | |
1385 | ALU64_SUB (GPR[RT]); | |
9805e229 | 1386 | ALU64_END (GPR[RD]); /* This checks for overflow. */ |
c906108c SS |
1387 | } |
1388 | TRACE_ALU_RESULT (GPR[RD]); | |
1389 | } | |
1390 | ||
1391 | ||
1392 | :function:::void:do_dsubu:int rs, int rt, int rd | |
1393 | { | |
1394 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
1395 | GPR[rd] = GPR[rs] - GPR[rt]; | |
1396 | TRACE_ALU_RESULT (GPR[rd]); | |
1397 | } | |
1398 | ||
f701dad2 | 1399 | 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU |
c906108c SS |
1400 | "dsubu r<RD>, r<RS>, r<RT>" |
1401 | *mipsIII: | |
1402 | *mipsIV: | |
603a98e7 | 1403 | *mipsV: |
c906108c SS |
1404 | *vr4100: |
1405 | *vr5000: | |
1406 | { | |
ca971540 | 1407 | check_u64 (SD_, instruction_0); |
c906108c SS |
1408 | do_dsubu (SD_, RS, RT, RD); |
1409 | } | |
1410 | ||
1411 | ||
1412 | 000010,26.INSTR_INDEX:NORMAL:32::J | |
1413 | "j <INSTR_INDEX>" | |
c5d00cc7 CD |
1414 | *mipsI: |
1415 | *mipsII: | |
1416 | *mipsIII: | |
1417 | *mipsIV: | |
603a98e7 | 1418 | *mipsV: |
c906108c SS |
1419 | *vr4100: |
1420 | *vr5000: | |
1421 | *r3900: | |
1422 | { | |
1423 | /* NOTE: The region used is that of the delay slot NIA and NOT the | |
1424 | current instruction */ | |
1425 | address_word region = (NIA & MASK (63, 28)); | |
1426 | DELAY_SLOT (region | (INSTR_INDEX << 2)); | |
1427 | } | |
1428 | ||
1429 | ||
1430 | 000011,26.INSTR_INDEX:NORMAL:32::JAL | |
1431 | "jal <INSTR_INDEX>" | |
c5d00cc7 CD |
1432 | *mipsI: |
1433 | *mipsII: | |
1434 | *mipsIII: | |
1435 | *mipsIV: | |
603a98e7 | 1436 | *mipsV: |
c906108c SS |
1437 | *vr4100: |
1438 | *vr5000: | |
1439 | *r3900: | |
1440 | { | |
1441 | /* NOTE: The region used is that of the delay slot and NOT the | |
1442 | current instruction */ | |
1443 | address_word region = (NIA & MASK (63, 28)); | |
1444 | GPR[31] = CIA + 8; | |
1445 | DELAY_SLOT (region | (INSTR_INDEX << 2)); | |
1446 | } | |
1447 | ||
f701dad2 | 1448 | 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR |
c906108c SS |
1449 | "jalr r<RS>":RD == 31 |
1450 | "jalr r<RD>, r<RS>" | |
c5d00cc7 CD |
1451 | *mipsI: |
1452 | *mipsII: | |
1453 | *mipsIII: | |
1454 | *mipsIV: | |
603a98e7 | 1455 | *mipsV: |
c906108c SS |
1456 | *vr4100: |
1457 | *vr5000: | |
1458 | *r3900: | |
1459 | { | |
1460 | address_word temp = GPR[RS]; | |
1461 | GPR[RD] = CIA + 8; | |
1462 | DELAY_SLOT (temp); | |
1463 | } | |
1464 | ||
1465 | ||
f701dad2 | 1466 | 000000,5.RS,000000000000000,001000:SPECIAL:32::JR |
c906108c | 1467 | "jr r<RS>" |
c5d00cc7 CD |
1468 | *mipsI: |
1469 | *mipsII: | |
1470 | *mipsIII: | |
1471 | *mipsIV: | |
603a98e7 | 1472 | *mipsV: |
c906108c SS |
1473 | *vr4100: |
1474 | *vr5000: | |
1475 | *r3900: | |
1476 | { | |
1477 | DELAY_SLOT (GPR[RS]); | |
1478 | } | |
1479 | ||
1480 | ||
1481 | :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset | |
1482 | { | |
1483 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); | |
1484 | address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); | |
1485 | address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); | |
1486 | unsigned int byte; | |
1487 | address_word paddr; | |
1488 | int uncached; | |
1489 | unsigned64 memval; | |
1490 | address_word vaddr; | |
1491 | ||
09297648 | 1492 | vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
1493 | if ((vaddr & access) != 0) |
1494 | { | |
1495 | SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal); | |
1496 | } | |
1497 | AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); | |
1498 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); | |
1499 | LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL); | |
1500 | byte = ((vaddr & mask) ^ bigendiancpu); | |
1501 | return (memval >> (8 * byte)); | |
1502 | } | |
1503 | ||
1c47a468 CD |
1504 | :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt |
1505 | { | |
1506 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); | |
1507 | address_word reverseendian = (ReverseEndian ? -1 : 0); | |
1508 | address_word bigendiancpu = (BigEndianCPU ? -1 : 0); | |
1509 | unsigned int byte; | |
1510 | unsigned int word; | |
1511 | address_word paddr; | |
1512 | int uncached; | |
1513 | unsigned64 memval; | |
1514 | address_word vaddr; | |
1515 | int nr_lhs_bits; | |
1516 | int nr_rhs_bits; | |
1517 | unsigned_word lhs_mask; | |
1518 | unsigned_word temp; | |
1519 | ||
09297648 | 1520 | vaddr = loadstore_ea (SD_, base, offset); |
1c47a468 CD |
1521 | AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); |
1522 | paddr = (paddr ^ (reverseendian & mask)); | |
1523 | if (BigEndianMem == 0) | |
1524 | paddr = paddr & ~access; | |
1525 | ||
1526 | /* compute where within the word/mem we are */ | |
1527 | byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */ | |
1528 | word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */ | |
1529 | nr_lhs_bits = 8 * byte + 8; | |
1530 | nr_rhs_bits = 8 * access - 8 * byte; | |
1531 | /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ | |
1532 | ||
1533 | /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", | |
1534 | (long) ((unsigned64) vaddr >> 32), (long) vaddr, | |
1535 | (long) ((unsigned64) paddr >> 32), (long) paddr, | |
1536 | word, byte, nr_lhs_bits, nr_rhs_bits); */ | |
1537 | ||
1538 | LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL); | |
1539 | if (word == 0) | |
1540 | { | |
1541 | /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */ | |
1542 | temp = (memval << nr_rhs_bits); | |
1543 | } | |
1544 | else | |
1545 | { | |
1546 | /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */ | |
1547 | temp = (memval >> nr_lhs_bits); | |
1548 | } | |
1549 | lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits); | |
1550 | rt = (rt & ~lhs_mask) | (temp & lhs_mask); | |
1551 | ||
1552 | /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n", | |
1553 | (long) ((unsigned64) memval >> 32), (long) memval, | |
1554 | (long) ((unsigned64) temp >> 32), (long) temp, | |
1555 | (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask, | |
1556 | (long) (rt >> 32), (long) rt); */ | |
1557 | return rt; | |
1558 | } | |
1559 | ||
1560 | :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt | |
1561 | { | |
1562 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); | |
1563 | address_word reverseendian = (ReverseEndian ? -1 : 0); | |
1564 | address_word bigendiancpu = (BigEndianCPU ? -1 : 0); | |
1565 | unsigned int byte; | |
1566 | address_word paddr; | |
1567 | int uncached; | |
1568 | unsigned64 memval; | |
1569 | address_word vaddr; | |
1570 | ||
09297648 | 1571 | vaddr = loadstore_ea (SD_, base, offset); |
1c47a468 CD |
1572 | AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); |
1573 | /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */ | |
1574 | paddr = (paddr ^ (reverseendian & mask)); | |
1575 | if (BigEndianMem != 0) | |
1576 | paddr = paddr & ~access; | |
1577 | byte = ((vaddr & mask) ^ (bigendiancpu & mask)); | |
1578 | /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */ | |
1579 | LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL); | |
1580 | /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n", | |
1581 | (long) paddr, byte, (long) paddr, (long) memval); */ | |
1582 | { | |
1583 | unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0); | |
1584 | rt &= ~screen; | |
1585 | rt |= (memval >> (8 * byte)) & screen; | |
1586 | } | |
1587 | return rt; | |
1588 | } | |
1589 | ||
c906108c SS |
1590 | |
1591 | 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB | |
1592 | "lb r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
1593 | *mipsI: |
1594 | *mipsII: | |
1595 | *mipsIII: | |
1596 | *mipsIV: | |
603a98e7 | 1597 | *mipsV: |
c906108c SS |
1598 | *vr4100: |
1599 | *vr5000: | |
1600 | *r3900: | |
1601 | { | |
1602 | GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET))); | |
1603 | } | |
1604 | ||
1605 | ||
1606 | 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU | |
1607 | "lbu r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
1608 | *mipsI: |
1609 | *mipsII: | |
1610 | *mipsIII: | |
1611 | *mipsIV: | |
603a98e7 | 1612 | *mipsV: |
c906108c SS |
1613 | *vr4100: |
1614 | *vr5000: | |
1615 | *r3900: | |
1616 | { | |
1617 | GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)); | |
1618 | } | |
1619 | ||
1620 | ||
1621 | 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD | |
1622 | "ld r<RT>, <OFFSET>(r<BASE>)" | |
1623 | *mipsIII: | |
1624 | *mipsIV: | |
603a98e7 | 1625 | *mipsV: |
c906108c SS |
1626 | *vr4100: |
1627 | *vr5000: | |
1628 | { | |
ca971540 | 1629 | check_u64 (SD_, instruction_0); |
c906108c SS |
1630 | GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); |
1631 | } | |
1632 | ||
1633 | ||
1634 | 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz | |
1635 | "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)" | |
1636 | *mipsII: | |
1637 | *mipsIII: | |
1638 | *mipsIV: | |
603a98e7 | 1639 | *mipsV: |
c906108c SS |
1640 | *vr4100: |
1641 | *vr5000: | |
1642 | *r3900: | |
1643 | { | |
1644 | COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); | |
1645 | } | |
1646 | ||
1647 | ||
1648 | ||
1649 | ||
1650 | 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL | |
1651 | "ldl r<RT>, <OFFSET>(r<BASE>)" | |
1652 | *mipsIII: | |
1653 | *mipsIV: | |
603a98e7 | 1654 | *mipsV: |
c906108c SS |
1655 | *vr4100: |
1656 | *vr5000: | |
1657 | { | |
ca971540 | 1658 | check_u64 (SD_, instruction_0); |
c906108c SS |
1659 | GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
1660 | } | |
1661 | ||
1662 | ||
1663 | 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR | |
1664 | "ldr r<RT>, <OFFSET>(r<BASE>)" | |
1665 | *mipsIII: | |
1666 | *mipsIV: | |
603a98e7 | 1667 | *mipsV: |
c906108c SS |
1668 | *vr4100: |
1669 | *vr5000: | |
1670 | { | |
ca971540 | 1671 | check_u64 (SD_, instruction_0); |
c906108c SS |
1672 | GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
1673 | } | |
1674 | ||
1675 | ||
1676 | 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH | |
1677 | "lh r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
1678 | *mipsI: |
1679 | *mipsII: | |
1680 | *mipsIII: | |
1681 | *mipsIV: | |
603a98e7 | 1682 | *mipsV: |
c906108c SS |
1683 | *vr4100: |
1684 | *vr5000: | |
1685 | *r3900: | |
1686 | { | |
1687 | GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET))); | |
1688 | } | |
1689 | ||
1690 | ||
1691 | 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU | |
1692 | "lhu r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
1693 | *mipsI: |
1694 | *mipsII: | |
1695 | *mipsIII: | |
1696 | *mipsIV: | |
603a98e7 | 1697 | *mipsV: |
c906108c SS |
1698 | *vr4100: |
1699 | *vr5000: | |
1700 | *r3900: | |
1701 | { | |
1702 | GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)); | |
1703 | } | |
1704 | ||
1705 | ||
1706 | 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL | |
1707 | "ll r<RT>, <OFFSET>(r<BASE>)" | |
1708 | *mipsII: | |
1709 | *mipsIII: | |
1710 | *mipsIV: | |
603a98e7 | 1711 | *mipsV: |
c906108c SS |
1712 | *vr4100: |
1713 | *vr5000: | |
1714 | { | |
c1e8ada4 CD |
1715 | address_word base = GPR[BASE]; |
1716 | address_word offset = EXTEND16 (OFFSET); | |
c906108c | 1717 | { |
09297648 | 1718 | address_word vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
1719 | address_word paddr; |
1720 | int uncached; | |
1721 | if ((vaddr & 3) != 0) | |
1722 | { | |
1723 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal); | |
1724 | } | |
1725 | else | |
1726 | { | |
1727 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1728 | { | |
1729 | unsigned64 memval = 0; | |
1730 | unsigned64 memval1 = 0; | |
1731 | unsigned64 mask = 0x7; | |
1732 | unsigned int shift = 2; | |
1733 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
1734 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1735 | unsigned int byte; | |
1736 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
1737 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
1738 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
043b7057 | 1739 | GPR[RT] = EXTEND32 (memval >> (8 * byte)); |
c906108c SS |
1740 | LLBIT = 1; |
1741 | } | |
1742 | } | |
1743 | } | |
1744 | } | |
1745 | ||
1746 | ||
1747 | 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD | |
1748 | "lld r<RT>, <OFFSET>(r<BASE>)" | |
1749 | *mipsIII: | |
1750 | *mipsIV: | |
603a98e7 | 1751 | *mipsV: |
c906108c SS |
1752 | *vr4100: |
1753 | *vr5000: | |
1754 | { | |
c1e8ada4 CD |
1755 | address_word base = GPR[BASE]; |
1756 | address_word offset = EXTEND16 (OFFSET); | |
ca971540 | 1757 | check_u64 (SD_, instruction_0); |
c906108c | 1758 | { |
09297648 | 1759 | address_word vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
1760 | address_word paddr; |
1761 | int uncached; | |
1762 | if ((vaddr & 7) != 0) | |
1763 | { | |
1764 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal); | |
1765 | } | |
1766 | else | |
1767 | { | |
1768 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1769 | { | |
1770 | unsigned64 memval = 0; | |
1771 | unsigned64 memval1 = 0; | |
1772 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); | |
c1e8ada4 | 1773 | GPR[RT] = memval; |
c906108c SS |
1774 | LLBIT = 1; |
1775 | } | |
1776 | } | |
1777 | } | |
1778 | } | |
1779 | ||
1780 | ||
1781 | 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI | |
1782 | "lui r<RT>, <IMMEDIATE>" | |
c5d00cc7 CD |
1783 | *mipsI: |
1784 | *mipsII: | |
1785 | *mipsIII: | |
1786 | *mipsIV: | |
603a98e7 | 1787 | *mipsV: |
c906108c SS |
1788 | *vr4100: |
1789 | *vr5000: | |
1790 | *r3900: | |
1791 | { | |
1792 | TRACE_ALU_INPUT1 (IMMEDIATE); | |
1793 | GPR[RT] = EXTEND32 (IMMEDIATE << 16); | |
1794 | TRACE_ALU_RESULT (GPR[RT]); | |
1795 | } | |
1796 | ||
1797 | ||
1798 | 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW | |
1799 | "lw r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
1800 | *mipsI: |
1801 | *mipsII: | |
1802 | *mipsIII: | |
1803 | *mipsIV: | |
603a98e7 | 1804 | *mipsV: |
c906108c SS |
1805 | *vr4100: |
1806 | *vr5000: | |
1807 | *r3900: | |
1808 | { | |
1809 | GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); | |
1810 | } | |
1811 | ||
1812 | ||
1813 | 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz | |
1814 | "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
1815 | *mipsI: |
1816 | *mipsII: | |
1817 | *mipsIII: | |
1818 | *mipsIV: | |
603a98e7 | 1819 | *mipsV: |
c906108c SS |
1820 | *vr4100: |
1821 | *vr5000: | |
1822 | *r3900: | |
1823 | { | |
1824 | COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); | |
1825 | } | |
1826 | ||
1827 | ||
c906108c SS |
1828 | 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL |
1829 | "lwl r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
1830 | *mipsI: |
1831 | *mipsII: | |
1832 | *mipsIII: | |
1833 | *mipsIV: | |
603a98e7 | 1834 | *mipsV: |
c906108c SS |
1835 | *vr4100: |
1836 | *vr5000: | |
1837 | *r3900: | |
1838 | { | |
7a292a7a | 1839 | GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); |
c906108c SS |
1840 | } |
1841 | ||
1842 | ||
c906108c SS |
1843 | 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR |
1844 | "lwr r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
1845 | *mipsI: |
1846 | *mipsII: | |
1847 | *mipsIII: | |
1848 | *mipsIV: | |
603a98e7 | 1849 | *mipsV: |
c906108c SS |
1850 | *vr4100: |
1851 | *vr5000: | |
1852 | *r3900: | |
1853 | { | |
1854 | GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); | |
1855 | } | |
1856 | ||
1857 | ||
bb22bd7d | 1858 | 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU |
c906108c SS |
1859 | "lwu r<RT>, <OFFSET>(r<BASE>)" |
1860 | *mipsIII: | |
1861 | *mipsIV: | |
603a98e7 | 1862 | *mipsV: |
c906108c SS |
1863 | *vr4100: |
1864 | *vr5000: | |
1865 | { | |
ca971540 | 1866 | check_u64 (SD_, instruction_0); |
c906108c SS |
1867 | GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)); |
1868 | } | |
1869 | ||
1870 | ||
1871 | :function:::void:do_mfhi:int rd | |
1872 | { | |
1873 | check_mf_hilo (SD_, HIHISTORY, LOHISTORY); | |
1874 | TRACE_ALU_INPUT1 (HI); | |
1875 | GPR[rd] = HI; | |
1876 | TRACE_ALU_RESULT (GPR[rd]); | |
1877 | } | |
1878 | ||
1879 | 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI | |
1880 | "mfhi r<RD>" | |
c5d00cc7 CD |
1881 | *mipsI: |
1882 | *mipsII: | |
1883 | *mipsIII: | |
1884 | *mipsIV: | |
603a98e7 | 1885 | *mipsV: |
c906108c SS |
1886 | *vr4100: |
1887 | *vr5000: | |
1888 | *r3900: | |
1889 | { | |
1890 | do_mfhi (SD_, RD); | |
1891 | } | |
1892 | ||
1893 | ||
1894 | ||
1895 | :function:::void:do_mflo:int rd | |
1896 | { | |
1897 | check_mf_hilo (SD_, LOHISTORY, HIHISTORY); | |
1898 | TRACE_ALU_INPUT1 (LO); | |
1899 | GPR[rd] = LO; | |
1900 | TRACE_ALU_RESULT (GPR[rd]); | |
1901 | } | |
1902 | ||
1903 | 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO | |
1904 | "mflo r<RD>" | |
c5d00cc7 CD |
1905 | *mipsI: |
1906 | *mipsII: | |
1907 | *mipsIII: | |
1908 | *mipsIV: | |
603a98e7 | 1909 | *mipsV: |
c906108c SS |
1910 | *vr4100: |
1911 | *vr5000: | |
1912 | *r3900: | |
1913 | { | |
1914 | do_mflo (SD_, RD); | |
1915 | } | |
1916 | ||
1917 | ||
1918 | ||
f701dad2 | 1919 | 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN |
c906108c SS |
1920 | "movn r<RD>, r<RS>, r<RT>" |
1921 | *mipsIV: | |
603a98e7 | 1922 | *mipsV: |
c906108c SS |
1923 | *vr5000: |
1924 | { | |
1925 | if (GPR[RT] != 0) | |
1926 | GPR[RD] = GPR[RS]; | |
1927 | } | |
1928 | ||
1929 | ||
1930 | ||
f701dad2 | 1931 | 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ |
c906108c SS |
1932 | "movz r<RD>, r<RS>, r<RT>" |
1933 | *mipsIV: | |
603a98e7 | 1934 | *mipsV: |
c906108c SS |
1935 | *vr5000: |
1936 | { | |
1937 | if (GPR[RT] == 0) | |
1938 | GPR[RD] = GPR[RS]; | |
1939 | } | |
1940 | ||
1941 | ||
1942 | ||
1943 | 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI | |
1944 | "mthi r<RS>" | |
c5d00cc7 CD |
1945 | *mipsI: |
1946 | *mipsII: | |
1947 | *mipsIII: | |
1948 | *mipsIV: | |
603a98e7 | 1949 | *mipsV: |
c906108c SS |
1950 | *vr4100: |
1951 | *vr5000: | |
1952 | *r3900: | |
1953 | { | |
1954 | check_mt_hilo (SD_, HIHISTORY); | |
1955 | HI = GPR[RS]; | |
1956 | } | |
1957 | ||
1958 | ||
1959 | ||
f701dad2 | 1960 | 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO |
c906108c | 1961 | "mtlo r<RS>" |
c5d00cc7 CD |
1962 | *mipsI: |
1963 | *mipsII: | |
1964 | *mipsIII: | |
1965 | *mipsIV: | |
603a98e7 | 1966 | *mipsV: |
c906108c SS |
1967 | *vr4100: |
1968 | *vr5000: | |
1969 | *r3900: | |
1970 | { | |
1971 | check_mt_hilo (SD_, LOHISTORY); | |
1972 | LO = GPR[RS]; | |
1973 | } | |
1974 | ||
1975 | ||
1976 | ||
1977 | :function:::void:do_mult:int rs, int rt, int rd | |
1978 | { | |
1979 | signed64 prod; | |
1980 | check_mult_hilo (SD_, HIHISTORY, LOHISTORY); | |
1981 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
1982 | prod = (((signed64)(signed32) GPR[rs]) | |
1983 | * ((signed64)(signed32) GPR[rt])); | |
1984 | LO = EXTEND32 (VL4_8 (prod)); | |
1985 | HI = EXTEND32 (VH4_8 (prod)); | |
1986 | if (rd != 0) | |
1987 | GPR[rd] = LO; | |
1988 | TRACE_ALU_RESULT2 (HI, LO); | |
1989 | } | |
1990 | ||
f701dad2 | 1991 | 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT |
c906108c | 1992 | "mult r<RS>, r<RT>" |
c5d00cc7 CD |
1993 | *mipsI: |
1994 | *mipsII: | |
1995 | *mipsIII: | |
1996 | *mipsIV: | |
603a98e7 | 1997 | *mipsV: |
c906108c SS |
1998 | *vr4100: |
1999 | { | |
2000 | do_mult (SD_, RS, RT, 0); | |
2001 | } | |
2002 | ||
2003 | ||
f701dad2 | 2004 | 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT |
9846de1b | 2005 | "mult r<RS>, r<RT>":RD == 0 |
c906108c SS |
2006 | "mult r<RD>, r<RS>, r<RT>" |
2007 | *vr5000: | |
2008 | *r3900: | |
2009 | { | |
2010 | do_mult (SD_, RS, RT, RD); | |
2011 | } | |
2012 | ||
2013 | ||
2014 | :function:::void:do_multu:int rs, int rt, int rd | |
2015 | { | |
2016 | unsigned64 prod; | |
2017 | check_mult_hilo (SD_, HIHISTORY, LOHISTORY); | |
2018 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
2019 | prod = (((unsigned64)(unsigned32) GPR[rs]) | |
2020 | * ((unsigned64)(unsigned32) GPR[rt])); | |
2021 | LO = EXTEND32 (VL4_8 (prod)); | |
2022 | HI = EXTEND32 (VH4_8 (prod)); | |
2023 | if (rd != 0) | |
2024 | GPR[rd] = LO; | |
2025 | TRACE_ALU_RESULT2 (HI, LO); | |
2026 | } | |
2027 | ||
f701dad2 | 2028 | 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU |
c906108c | 2029 | "multu r<RS>, r<RT>" |
c5d00cc7 CD |
2030 | *mipsI: |
2031 | *mipsII: | |
2032 | *mipsIII: | |
2033 | *mipsIV: | |
603a98e7 | 2034 | *mipsV: |
c906108c SS |
2035 | *vr4100: |
2036 | { | |
cff3e48b | 2037 | do_multu (SD_, RS, RT, 0); |
c906108c SS |
2038 | } |
2039 | ||
f701dad2 | 2040 | 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU |
9846de1b | 2041 | "multu r<RS>, r<RT>":RD == 0 |
c906108c SS |
2042 | "multu r<RD>, r<RS>, r<RT>" |
2043 | *vr5000: | |
2044 | *r3900: | |
2045 | { | |
cff3e48b | 2046 | do_multu (SD_, RS, RT, RD); |
c906108c SS |
2047 | } |
2048 | ||
2049 | ||
2050 | :function:::void:do_nor:int rs, int rt, int rd | |
2051 | { | |
2052 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
2053 | GPR[rd] = ~ (GPR[rs] | GPR[rt]); | |
2054 | TRACE_ALU_RESULT (GPR[rd]); | |
2055 | } | |
2056 | ||
2057 | 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR | |
2058 | "nor r<RD>, r<RS>, r<RT>" | |
c5d00cc7 CD |
2059 | *mipsI: |
2060 | *mipsII: | |
2061 | *mipsIII: | |
2062 | *mipsIV: | |
603a98e7 | 2063 | *mipsV: |
c906108c SS |
2064 | *vr4100: |
2065 | *vr5000: | |
2066 | *r3900: | |
2067 | { | |
2068 | do_nor (SD_, RS, RT, RD); | |
2069 | } | |
2070 | ||
2071 | ||
2072 | :function:::void:do_or:int rs, int rt, int rd | |
2073 | { | |
2074 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
2075 | GPR[rd] = (GPR[rs] | GPR[rt]); | |
2076 | TRACE_ALU_RESULT (GPR[rd]); | |
2077 | } | |
2078 | ||
2079 | 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR | |
2080 | "or r<RD>, r<RS>, r<RT>" | |
c5d00cc7 CD |
2081 | *mipsI: |
2082 | *mipsII: | |
2083 | *mipsIII: | |
2084 | *mipsIV: | |
603a98e7 | 2085 | *mipsV: |
c906108c SS |
2086 | *vr4100: |
2087 | *vr5000: | |
2088 | *r3900: | |
2089 | { | |
2090 | do_or (SD_, RS, RT, RD); | |
2091 | } | |
2092 | ||
2093 | ||
2094 | ||
2095 | :function:::void:do_ori:int rs, int rt, unsigned immediate | |
2096 | { | |
2097 | TRACE_ALU_INPUT2 (GPR[rs], immediate); | |
2098 | GPR[rt] = (GPR[rs] | immediate); | |
2099 | TRACE_ALU_RESULT (GPR[rt]); | |
2100 | } | |
2101 | ||
2102 | 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI | |
2103 | "ori r<RT>, r<RS>, <IMMEDIATE>" | |
c5d00cc7 CD |
2104 | *mipsI: |
2105 | *mipsII: | |
2106 | *mipsIII: | |
2107 | *mipsIV: | |
603a98e7 | 2108 | *mipsV: |
c906108c SS |
2109 | *vr4100: |
2110 | *vr5000: | |
2111 | *r3900: | |
2112 | { | |
2113 | do_ori (SD_, RS, RT, IMMEDIATE); | |
2114 | } | |
2115 | ||
2116 | ||
af5107af CD |
2117 | 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF |
2118 | "pref <HINT>, <OFFSET>(r<BASE>)" | |
c906108c | 2119 | *mipsIV: |
603a98e7 | 2120 | *mipsV: |
c906108c SS |
2121 | *vr5000: |
2122 | { | |
c1e8ada4 CD |
2123 | address_word base = GPR[BASE]; |
2124 | address_word offset = EXTEND16 (OFFSET); | |
c906108c | 2125 | { |
09297648 | 2126 | address_word vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
2127 | address_word paddr; |
2128 | int uncached; | |
2129 | { | |
2130 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
c1e8ada4 | 2131 | Prefetch(uncached,paddr,vaddr,isDATA,HINT); |
c906108c SS |
2132 | } |
2133 | } | |
2134 | } | |
2135 | ||
1c47a468 | 2136 | |
c906108c SS |
2137 | :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word |
2138 | { | |
2139 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); | |
2140 | address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); | |
2141 | address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); | |
2142 | unsigned int byte; | |
2143 | address_word paddr; | |
2144 | int uncached; | |
2145 | unsigned64 memval; | |
2146 | address_word vaddr; | |
2147 | ||
09297648 | 2148 | vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
2149 | if ((vaddr & access) != 0) |
2150 | { | |
2151 | SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal); | |
2152 | } | |
2153 | AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); | |
2154 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); | |
2155 | byte = ((vaddr & mask) ^ bigendiancpu); | |
2156 | memval = (word << (8 * byte)); | |
2157 | StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL); | |
2158 | } | |
2159 | ||
1c47a468 CD |
2160 | :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt |
2161 | { | |
2162 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); | |
2163 | address_word reverseendian = (ReverseEndian ? -1 : 0); | |
2164 | address_word bigendiancpu = (BigEndianCPU ? -1 : 0); | |
2165 | unsigned int byte; | |
2166 | unsigned int word; | |
2167 | address_word paddr; | |
2168 | int uncached; | |
2169 | unsigned64 memval; | |
2170 | address_word vaddr; | |
2171 | int nr_lhs_bits; | |
2172 | int nr_rhs_bits; | |
2173 | ||
09297648 | 2174 | vaddr = loadstore_ea (SD_, base, offset); |
1c47a468 CD |
2175 | AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); |
2176 | paddr = (paddr ^ (reverseendian & mask)); | |
2177 | if (BigEndianMem == 0) | |
2178 | paddr = paddr & ~access; | |
2179 | ||
2180 | /* compute where within the word/mem we are */ | |
2181 | byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */ | |
2182 | word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */ | |
2183 | nr_lhs_bits = 8 * byte + 8; | |
2184 | nr_rhs_bits = 8 * access - 8 * byte; | |
2185 | /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ | |
2186 | /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", | |
2187 | (long) ((unsigned64) vaddr >> 32), (long) vaddr, | |
2188 | (long) ((unsigned64) paddr >> 32), (long) paddr, | |
2189 | word, byte, nr_lhs_bits, nr_rhs_bits); */ | |
2190 | ||
2191 | if (word == 0) | |
2192 | { | |
2193 | memval = (rt >> nr_rhs_bits); | |
2194 | } | |
2195 | else | |
2196 | { | |
2197 | memval = (rt << nr_lhs_bits); | |
2198 | } | |
2199 | /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n", | |
2200 | (long) ((unsigned64) rt >> 32), (long) rt, | |
2201 | (long) ((unsigned64) memval >> 32), (long) memval); */ | |
2202 | StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL); | |
2203 | } | |
2204 | ||
2205 | :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt | |
2206 | { | |
2207 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); | |
2208 | address_word reverseendian = (ReverseEndian ? -1 : 0); | |
2209 | address_word bigendiancpu = (BigEndianCPU ? -1 : 0); | |
2210 | unsigned int byte; | |
2211 | address_word paddr; | |
2212 | int uncached; | |
2213 | unsigned64 memval; | |
2214 | address_word vaddr; | |
2215 | ||
09297648 | 2216 | vaddr = loadstore_ea (SD_, base, offset); |
1c47a468 CD |
2217 | AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); |
2218 | paddr = (paddr ^ (reverseendian & mask)); | |
2219 | if (BigEndianMem != 0) | |
2220 | paddr &= ~access; | |
2221 | byte = ((vaddr & mask) ^ (bigendiancpu & mask)); | |
2222 | memval = (rt << (byte * 8)); | |
2223 | StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL); | |
2224 | } | |
2225 | ||
c906108c SS |
2226 | |
2227 | 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB | |
2228 | "sb r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
2229 | *mipsI: |
2230 | *mipsII: | |
2231 | *mipsIII: | |
2232 | *mipsIV: | |
603a98e7 | 2233 | *mipsV: |
c906108c SS |
2234 | *vr4100: |
2235 | *vr5000: | |
2236 | *r3900: | |
2237 | { | |
2238 | do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); | |
2239 | } | |
2240 | ||
2241 | ||
2242 | 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC | |
2243 | "sc r<RT>, <OFFSET>(r<BASE>)" | |
2244 | *mipsII: | |
2245 | *mipsIII: | |
2246 | *mipsIV: | |
603a98e7 | 2247 | *mipsV: |
c906108c SS |
2248 | *vr4100: |
2249 | *vr5000: | |
2250 | { | |
2251 | unsigned32 instruction = instruction_0; | |
c1e8ada4 CD |
2252 | address_word base = GPR[BASE]; |
2253 | address_word offset = EXTEND16 (OFFSET); | |
c906108c | 2254 | { |
09297648 | 2255 | address_word vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
2256 | address_word paddr; |
2257 | int uncached; | |
2258 | if ((vaddr & 3) != 0) | |
2259 | { | |
2260 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal); | |
2261 | } | |
2262 | else | |
2263 | { | |
2264 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2265 | { | |
2266 | unsigned64 memval = 0; | |
2267 | unsigned64 memval1 = 0; | |
2268 | unsigned64 mask = 0x7; | |
2269 | unsigned int byte; | |
2270 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
2271 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
c1e8ada4 | 2272 | memval = ((unsigned64) GPR[RT] << (8 * byte)); |
c906108c SS |
2273 | if (LLBIT) |
2274 | { | |
2275 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
2276 | } | |
c1e8ada4 | 2277 | GPR[RT] = LLBIT; |
c906108c SS |
2278 | } |
2279 | } | |
2280 | } | |
2281 | } | |
2282 | ||
2283 | ||
2284 | 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD | |
2285 | "scd r<RT>, <OFFSET>(r<BASE>)" | |
2286 | *mipsIII: | |
2287 | *mipsIV: | |
603a98e7 | 2288 | *mipsV: |
c906108c SS |
2289 | *vr4100: |
2290 | *vr5000: | |
2291 | { | |
c1e8ada4 CD |
2292 | address_word base = GPR[BASE]; |
2293 | address_word offset = EXTEND16 (OFFSET); | |
ca971540 | 2294 | check_u64 (SD_, instruction_0); |
c906108c | 2295 | { |
09297648 | 2296 | address_word vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
2297 | address_word paddr; |
2298 | int uncached; | |
2299 | if ((vaddr & 7) != 0) | |
2300 | { | |
2301 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal); | |
2302 | } | |
2303 | else | |
2304 | { | |
2305 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2306 | { | |
2307 | unsigned64 memval = 0; | |
2308 | unsigned64 memval1 = 0; | |
c1e8ada4 | 2309 | memval = GPR[RT]; |
c906108c SS |
2310 | if (LLBIT) |
2311 | { | |
2312 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
2313 | } | |
c1e8ada4 | 2314 | GPR[RT] = LLBIT; |
c906108c SS |
2315 | } |
2316 | } | |
2317 | } | |
2318 | } | |
2319 | ||
2320 | ||
2321 | 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD | |
2322 | "sd r<RT>, <OFFSET>(r<BASE>)" | |
2323 | *mipsIII: | |
2324 | *mipsIV: | |
603a98e7 | 2325 | *mipsV: |
c906108c SS |
2326 | *vr4100: |
2327 | *vr5000: | |
2328 | { | |
ca971540 | 2329 | check_u64 (SD_, instruction_0); |
c906108c SS |
2330 | do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
2331 | } | |
2332 | ||
2333 | ||
2334 | 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz | |
2335 | "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)" | |
2336 | *mipsII: | |
2337 | *mipsIII: | |
2338 | *mipsIV: | |
603a98e7 | 2339 | *mipsV: |
c906108c SS |
2340 | *vr4100: |
2341 | *vr5000: | |
2342 | { | |
2343 | do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT)); | |
2344 | } | |
2345 | ||
2346 | ||
2347 | 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL | |
2348 | "sdl r<RT>, <OFFSET>(r<BASE>)" | |
2349 | *mipsIII: | |
2350 | *mipsIV: | |
603a98e7 | 2351 | *mipsV: |
c906108c SS |
2352 | *vr4100: |
2353 | *vr5000: | |
2354 | { | |
ca971540 | 2355 | check_u64 (SD_, instruction_0); |
c906108c SS |
2356 | do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
2357 | } | |
2358 | ||
2359 | ||
2360 | 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR | |
2361 | "sdr r<RT>, <OFFSET>(r<BASE>)" | |
2362 | *mipsIII: | |
2363 | *mipsIV: | |
603a98e7 | 2364 | *mipsV: |
c906108c SS |
2365 | *vr4100: |
2366 | *vr5000: | |
2367 | { | |
ca971540 | 2368 | check_u64 (SD_, instruction_0); |
c906108c SS |
2369 | do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); |
2370 | } | |
2371 | ||
2372 | ||
2373 | 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH | |
2374 | "sh r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
2375 | *mipsI: |
2376 | *mipsII: | |
2377 | *mipsIII: | |
2378 | *mipsIV: | |
603a98e7 | 2379 | *mipsV: |
c906108c SS |
2380 | *vr4100: |
2381 | *vr5000: | |
2382 | *r3900: | |
2383 | { | |
2384 | do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); | |
2385 | } | |
2386 | ||
2387 | ||
2388 | :function:::void:do_sll:int rt, int rd, int shift | |
2389 | { | |
2390 | unsigned32 temp = (GPR[rt] << shift); | |
2391 | TRACE_ALU_INPUT2 (GPR[rt], shift); | |
2392 | GPR[rd] = EXTEND32 (temp); | |
2393 | TRACE_ALU_RESULT (GPR[rd]); | |
2394 | } | |
2395 | ||
f701dad2 | 2396 | 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL |
20ae0098 | 2397 | "nop":RD == 0 && RT == 0 && SHIFT == 0 |
c906108c | 2398 | "sll r<RD>, r<RT>, <SHIFT>" |
c5d00cc7 CD |
2399 | *mipsI: |
2400 | *mipsII: | |
2401 | *mipsIII: | |
2402 | *mipsIV: | |
603a98e7 | 2403 | *mipsV: |
c906108c SS |
2404 | *vr4100: |
2405 | *vr5000: | |
2406 | *r3900: | |
2407 | { | |
20ae0098 CD |
2408 | /* Skip shift for NOP, so that there won't be lots of extraneous |
2409 | trace output. */ | |
2410 | if (RD != 0 || RT != 0 || SHIFT != 0) | |
2411 | do_sll (SD_, RT, RD, SHIFT); | |
c906108c SS |
2412 | } |
2413 | ||
2414 | ||
2415 | :function:::void:do_sllv:int rs, int rt, int rd | |
2416 | { | |
2417 | int s = MASKED (GPR[rs], 4, 0); | |
2418 | unsigned32 temp = (GPR[rt] << s); | |
2419 | TRACE_ALU_INPUT2 (GPR[rt], s); | |
2420 | GPR[rd] = EXTEND32 (temp); | |
2421 | TRACE_ALU_RESULT (GPR[rd]); | |
2422 | } | |
2423 | ||
f701dad2 | 2424 | 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV |
c906108c | 2425 | "sllv r<RD>, r<RT>, r<RS>" |
c5d00cc7 CD |
2426 | *mipsI: |
2427 | *mipsII: | |
2428 | *mipsIII: | |
2429 | *mipsIV: | |
603a98e7 | 2430 | *mipsV: |
c906108c SS |
2431 | *vr4100: |
2432 | *vr5000: | |
2433 | *r3900: | |
2434 | { | |
2435 | do_sllv (SD_, RS, RT, RD); | |
2436 | } | |
2437 | ||
2438 | ||
2439 | :function:::void:do_slt:int rs, int rt, int rd | |
2440 | { | |
2441 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
2442 | GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]); | |
2443 | TRACE_ALU_RESULT (GPR[rd]); | |
2444 | } | |
2445 | ||
f701dad2 | 2446 | 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT |
c906108c | 2447 | "slt r<RD>, r<RS>, r<RT>" |
c5d00cc7 CD |
2448 | *mipsI: |
2449 | *mipsII: | |
2450 | *mipsIII: | |
2451 | *mipsIV: | |
603a98e7 | 2452 | *mipsV: |
c906108c SS |
2453 | *vr4100: |
2454 | *vr5000: | |
2455 | *r3900: | |
2456 | { | |
2457 | do_slt (SD_, RS, RT, RD); | |
2458 | } | |
2459 | ||
2460 | ||
2461 | :function:::void:do_slti:int rs, int rt, unsigned16 immediate | |
2462 | { | |
2463 | TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); | |
2464 | GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate)); | |
2465 | TRACE_ALU_RESULT (GPR[rt]); | |
2466 | } | |
2467 | ||
2468 | 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI | |
2469 | "slti r<RT>, r<RS>, <IMMEDIATE>" | |
c5d00cc7 CD |
2470 | *mipsI: |
2471 | *mipsII: | |
2472 | *mipsIII: | |
2473 | *mipsIV: | |
603a98e7 | 2474 | *mipsV: |
c906108c SS |
2475 | *vr4100: |
2476 | *vr5000: | |
2477 | *r3900: | |
2478 | { | |
2479 | do_slti (SD_, RS, RT, IMMEDIATE); | |
2480 | } | |
2481 | ||
2482 | ||
2483 | :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate | |
2484 | { | |
2485 | TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); | |
2486 | GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate)); | |
2487 | TRACE_ALU_RESULT (GPR[rt]); | |
2488 | } | |
2489 | ||
2490 | 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU | |
2491 | "sltiu r<RT>, r<RS>, <IMMEDIATE>" | |
c5d00cc7 CD |
2492 | *mipsI: |
2493 | *mipsII: | |
2494 | *mipsIII: | |
2495 | *mipsIV: | |
603a98e7 | 2496 | *mipsV: |
c906108c SS |
2497 | *vr4100: |
2498 | *vr5000: | |
2499 | *r3900: | |
2500 | { | |
2501 | do_sltiu (SD_, RS, RT, IMMEDIATE); | |
2502 | } | |
2503 | ||
2504 | ||
2505 | ||
2506 | :function:::void:do_sltu:int rs, int rt, int rd | |
2507 | { | |
2508 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
2509 | GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]); | |
2510 | TRACE_ALU_RESULT (GPR[rd]); | |
2511 | } | |
2512 | ||
f701dad2 | 2513 | 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU |
c906108c | 2514 | "sltu r<RD>, r<RS>, r<RT>" |
c5d00cc7 CD |
2515 | *mipsI: |
2516 | *mipsII: | |
2517 | *mipsIII: | |
2518 | *mipsIV: | |
603a98e7 | 2519 | *mipsV: |
c906108c SS |
2520 | *vr4100: |
2521 | *vr5000: | |
2522 | *r3900: | |
2523 | { | |
2524 | do_sltu (SD_, RS, RT, RD); | |
2525 | } | |
2526 | ||
2527 | ||
2528 | :function:::void:do_sra:int rt, int rd, int shift | |
2529 | { | |
2530 | signed32 temp = (signed32) GPR[rt] >> shift; | |
2531 | TRACE_ALU_INPUT2 (GPR[rt], shift); | |
2532 | GPR[rd] = EXTEND32 (temp); | |
2533 | TRACE_ALU_RESULT (GPR[rd]); | |
2534 | } | |
2535 | ||
2536 | 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA | |
2537 | "sra r<RD>, r<RT>, <SHIFT>" | |
c5d00cc7 CD |
2538 | *mipsI: |
2539 | *mipsII: | |
2540 | *mipsIII: | |
2541 | *mipsIV: | |
603a98e7 | 2542 | *mipsV: |
c906108c SS |
2543 | *vr4100: |
2544 | *vr5000: | |
2545 | *r3900: | |
2546 | { | |
2547 | do_sra (SD_, RT, RD, SHIFT); | |
2548 | } | |
2549 | ||
2550 | ||
2551 | ||
2552 | :function:::void:do_srav:int rs, int rt, int rd | |
2553 | { | |
2554 | int s = MASKED (GPR[rs], 4, 0); | |
2555 | signed32 temp = (signed32) GPR[rt] >> s; | |
2556 | TRACE_ALU_INPUT2 (GPR[rt], s); | |
2557 | GPR[rd] = EXTEND32 (temp); | |
2558 | TRACE_ALU_RESULT (GPR[rd]); | |
2559 | } | |
2560 | ||
f701dad2 | 2561 | 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV |
c906108c | 2562 | "srav r<RD>, r<RT>, r<RS>" |
c5d00cc7 CD |
2563 | *mipsI: |
2564 | *mipsII: | |
2565 | *mipsIII: | |
2566 | *mipsIV: | |
603a98e7 | 2567 | *mipsV: |
c906108c SS |
2568 | *vr4100: |
2569 | *vr5000: | |
2570 | *r3900: | |
2571 | { | |
2572 | do_srav (SD_, RS, RT, RD); | |
2573 | } | |
2574 | ||
2575 | ||
2576 | ||
2577 | :function:::void:do_srl:int rt, int rd, int shift | |
2578 | { | |
2579 | unsigned32 temp = (unsigned32) GPR[rt] >> shift; | |
2580 | TRACE_ALU_INPUT2 (GPR[rt], shift); | |
2581 | GPR[rd] = EXTEND32 (temp); | |
2582 | TRACE_ALU_RESULT (GPR[rd]); | |
2583 | } | |
2584 | ||
2585 | 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL | |
2586 | "srl r<RD>, r<RT>, <SHIFT>" | |
c5d00cc7 CD |
2587 | *mipsI: |
2588 | *mipsII: | |
2589 | *mipsIII: | |
2590 | *mipsIV: | |
603a98e7 | 2591 | *mipsV: |
c906108c SS |
2592 | *vr4100: |
2593 | *vr5000: | |
2594 | *r3900: | |
2595 | { | |
2596 | do_srl (SD_, RT, RD, SHIFT); | |
2597 | } | |
2598 | ||
2599 | ||
2600 | :function:::void:do_srlv:int rs, int rt, int rd | |
2601 | { | |
2602 | int s = MASKED (GPR[rs], 4, 0); | |
2603 | unsigned32 temp = (unsigned32) GPR[rt] >> s; | |
2604 | TRACE_ALU_INPUT2 (GPR[rt], s); | |
2605 | GPR[rd] = EXTEND32 (temp); | |
2606 | TRACE_ALU_RESULT (GPR[rd]); | |
2607 | } | |
2608 | ||
f701dad2 | 2609 | 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV |
c906108c | 2610 | "srlv r<RD>, r<RT>, r<RS>" |
c5d00cc7 CD |
2611 | *mipsI: |
2612 | *mipsII: | |
2613 | *mipsIII: | |
2614 | *mipsIV: | |
603a98e7 | 2615 | *mipsV: |
c906108c SS |
2616 | *vr4100: |
2617 | *vr5000: | |
2618 | *r3900: | |
2619 | { | |
2620 | do_srlv (SD_, RS, RT, RD); | |
2621 | } | |
2622 | ||
2623 | ||
f701dad2 | 2624 | 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB |
c906108c | 2625 | "sub r<RD>, r<RS>, r<RT>" |
c5d00cc7 CD |
2626 | *mipsI: |
2627 | *mipsII: | |
2628 | *mipsIII: | |
2629 | *mipsIV: | |
603a98e7 | 2630 | *mipsV: |
c906108c SS |
2631 | *vr4100: |
2632 | *vr5000: | |
2633 | *r3900: | |
2634 | { | |
2635 | TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); | |
2636 | { | |
2637 | ALU32_BEGIN (GPR[RS]); | |
2638 | ALU32_SUB (GPR[RT]); | |
9805e229 | 2639 | ALU32_END (GPR[RD]); /* This checks for overflow. */ |
c906108c SS |
2640 | } |
2641 | TRACE_ALU_RESULT (GPR[RD]); | |
2642 | } | |
2643 | ||
2644 | ||
2645 | :function:::void:do_subu:int rs, int rt, int rd | |
2646 | { | |
2647 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
2648 | GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]); | |
2649 | TRACE_ALU_RESULT (GPR[rd]); | |
2650 | } | |
2651 | ||
f701dad2 | 2652 | 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU |
c906108c | 2653 | "subu r<RD>, r<RS>, r<RT>" |
c5d00cc7 CD |
2654 | *mipsI: |
2655 | *mipsII: | |
2656 | *mipsIII: | |
2657 | *mipsIV: | |
603a98e7 | 2658 | *mipsV: |
c906108c SS |
2659 | *vr4100: |
2660 | *vr5000: | |
2661 | *r3900: | |
2662 | { | |
2663 | do_subu (SD_, RS, RT, RD); | |
2664 | } | |
2665 | ||
2666 | ||
2667 | 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW | |
2668 | "sw r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
2669 | *mipsI: |
2670 | *mipsII: | |
2671 | *mipsIII: | |
2672 | *mipsIV: | |
603a98e7 | 2673 | *mipsV: |
c906108c SS |
2674 | *vr4100: |
2675 | *r3900: | |
2676 | *vr5000: | |
2677 | { | |
2678 | do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); | |
2679 | } | |
2680 | ||
2681 | ||
2682 | 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz | |
2683 | "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
2684 | *mipsI: |
2685 | *mipsII: | |
2686 | *mipsIII: | |
2687 | *mipsIV: | |
603a98e7 | 2688 | *mipsV: |
c906108c SS |
2689 | *vr4100: |
2690 | *vr5000: | |
2691 | *r3900: | |
2692 | { | |
2693 | do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT)); | |
2694 | } | |
2695 | ||
2696 | ||
c906108c SS |
2697 | 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL |
2698 | "swl r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
2699 | *mipsI: |
2700 | *mipsII: | |
2701 | *mipsIII: | |
2702 | *mipsIV: | |
603a98e7 | 2703 | *mipsV: |
c906108c SS |
2704 | *vr4100: |
2705 | *vr5000: | |
2706 | *r3900: | |
2707 | { | |
2708 | do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); | |
2709 | } | |
2710 | ||
2711 | ||
c906108c SS |
2712 | 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR |
2713 | "swr r<RT>, <OFFSET>(r<BASE>)" | |
c5d00cc7 CD |
2714 | *mipsI: |
2715 | *mipsII: | |
2716 | *mipsIII: | |
2717 | *mipsIV: | |
603a98e7 | 2718 | *mipsV: |
c906108c SS |
2719 | *vr4100: |
2720 | *vr5000: | |
2721 | *r3900: | |
2722 | { | |
2723 | do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); | |
2724 | } | |
2725 | ||
2726 | ||
f701dad2 | 2727 | 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC |
c906108c SS |
2728 | "sync":STYPE == 0 |
2729 | "sync <STYPE>" | |
2730 | *mipsII: | |
2731 | *mipsIII: | |
2732 | *mipsIV: | |
603a98e7 | 2733 | *mipsV: |
c906108c SS |
2734 | *vr4100: |
2735 | *vr5000: | |
2736 | *r3900: | |
2737 | { | |
2738 | SyncOperation (STYPE); | |
2739 | } | |
2740 | ||
2741 | ||
2742 | 000000,20.CODE,001100:SPECIAL:32::SYSCALL | |
2743 | "syscall <CODE>" | |
c5d00cc7 CD |
2744 | *mipsI: |
2745 | *mipsII: | |
2746 | *mipsIII: | |
2747 | *mipsIV: | |
603a98e7 | 2748 | *mipsV: |
c906108c SS |
2749 | *vr4100: |
2750 | *vr5000: | |
2751 | *r3900: | |
2752 | { | |
2753 | SignalException(SystemCall, instruction_0); | |
2754 | } | |
2755 | ||
2756 | ||
2757 | 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ | |
2758 | "teq r<RS>, r<RT>" | |
2759 | *mipsII: | |
2760 | *mipsIII: | |
2761 | *mipsIV: | |
603a98e7 | 2762 | *mipsV: |
c906108c SS |
2763 | *vr4100: |
2764 | *vr5000: | |
2765 | { | |
2766 | if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) | |
2767 | SignalException(Trap, instruction_0); | |
2768 | } | |
2769 | ||
2770 | ||
2771 | 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI | |
2772 | "teqi r<RS>, <IMMEDIATE>" | |
2773 | *mipsII: | |
2774 | *mipsIII: | |
2775 | *mipsIV: | |
603a98e7 | 2776 | *mipsV: |
c906108c SS |
2777 | *vr4100: |
2778 | *vr5000: | |
2779 | { | |
2780 | if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE)) | |
2781 | SignalException(Trap, instruction_0); | |
2782 | } | |
2783 | ||
2784 | ||
2785 | 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE | |
2786 | "tge r<RS>, r<RT>" | |
2787 | *mipsII: | |
2788 | *mipsIII: | |
2789 | *mipsIV: | |
603a98e7 | 2790 | *mipsV: |
c906108c SS |
2791 | *vr4100: |
2792 | *vr5000: | |
2793 | { | |
2794 | if ((signed_word) GPR[RS] >= (signed_word) GPR[RT]) | |
2795 | SignalException(Trap, instruction_0); | |
2796 | } | |
2797 | ||
2798 | ||
2799 | 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI | |
2800 | "tgei r<RS>, <IMMEDIATE>" | |
2801 | *mipsII: | |
2802 | *mipsIII: | |
2803 | *mipsIV: | |
603a98e7 | 2804 | *mipsV: |
c906108c SS |
2805 | *vr4100: |
2806 | *vr5000: | |
2807 | { | |
2808 | if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE)) | |
2809 | SignalException(Trap, instruction_0); | |
2810 | } | |
2811 | ||
2812 | ||
2813 | 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU | |
2814 | "tgeiu r<RS>, <IMMEDIATE>" | |
2815 | *mipsII: | |
2816 | *mipsIII: | |
2817 | *mipsIV: | |
603a98e7 | 2818 | *mipsV: |
c906108c SS |
2819 | *vr4100: |
2820 | *vr5000: | |
2821 | { | |
2822 | if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE)) | |
2823 | SignalException(Trap, instruction_0); | |
2824 | } | |
2825 | ||
2826 | ||
2827 | 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU | |
2828 | "tgeu r<RS>, r<RT>" | |
2829 | *mipsII: | |
2830 | *mipsIII: | |
2831 | *mipsIV: | |
603a98e7 | 2832 | *mipsV: |
c906108c SS |
2833 | *vr4100: |
2834 | *vr5000: | |
2835 | { | |
2836 | if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT]) | |
2837 | SignalException(Trap, instruction_0); | |
2838 | } | |
2839 | ||
2840 | ||
2841 | 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT | |
2842 | "tlt r<RS>, r<RT>" | |
2843 | *mipsII: | |
2844 | *mipsIII: | |
2845 | *mipsIV: | |
603a98e7 | 2846 | *mipsV: |
c906108c SS |
2847 | *vr4100: |
2848 | *vr5000: | |
2849 | { | |
2850 | if ((signed_word) GPR[RS] < (signed_word) GPR[RT]) | |
2851 | SignalException(Trap, instruction_0); | |
2852 | } | |
2853 | ||
2854 | ||
2855 | 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI | |
2856 | "tlti r<RS>, <IMMEDIATE>" | |
2857 | *mipsII: | |
2858 | *mipsIII: | |
2859 | *mipsIV: | |
603a98e7 | 2860 | *mipsV: |
c906108c SS |
2861 | *vr4100: |
2862 | *vr5000: | |
2863 | { | |
2864 | if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE)) | |
2865 | SignalException(Trap, instruction_0); | |
2866 | } | |
2867 | ||
2868 | ||
2869 | 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU | |
2870 | "tltiu r<RS>, <IMMEDIATE>" | |
2871 | *mipsII: | |
2872 | *mipsIII: | |
2873 | *mipsIV: | |
603a98e7 | 2874 | *mipsV: |
c906108c SS |
2875 | *vr4100: |
2876 | *vr5000: | |
2877 | { | |
2878 | if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE)) | |
2879 | SignalException(Trap, instruction_0); | |
2880 | } | |
2881 | ||
2882 | ||
2883 | 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU | |
2884 | "tltu r<RS>, r<RT>" | |
2885 | *mipsII: | |
2886 | *mipsIII: | |
2887 | *mipsIV: | |
603a98e7 | 2888 | *mipsV: |
c906108c SS |
2889 | *vr4100: |
2890 | *vr5000: | |
2891 | { | |
2892 | if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]) | |
2893 | SignalException(Trap, instruction_0); | |
2894 | } | |
2895 | ||
2896 | ||
2897 | 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE | |
2898 | "tne r<RS>, r<RT>" | |
2899 | *mipsII: | |
2900 | *mipsIII: | |
2901 | *mipsIV: | |
603a98e7 | 2902 | *mipsV: |
c906108c SS |
2903 | *vr4100: |
2904 | *vr5000: | |
2905 | { | |
2906 | if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) | |
2907 | SignalException(Trap, instruction_0); | |
2908 | } | |
2909 | ||
2910 | ||
2911 | 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI | |
2912 | "tne r<RS>, <IMMEDIATE>" | |
2913 | *mipsII: | |
2914 | *mipsIII: | |
2915 | *mipsIV: | |
603a98e7 | 2916 | *mipsV: |
c906108c SS |
2917 | *vr4100: |
2918 | *vr5000: | |
2919 | { | |
2920 | if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE)) | |
2921 | SignalException(Trap, instruction_0); | |
2922 | } | |
2923 | ||
2924 | ||
2925 | :function:::void:do_xor:int rs, int rt, int rd | |
2926 | { | |
2927 | TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); | |
2928 | GPR[rd] = GPR[rs] ^ GPR[rt]; | |
2929 | TRACE_ALU_RESULT (GPR[rd]); | |
2930 | } | |
2931 | ||
f701dad2 | 2932 | 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR |
c906108c | 2933 | "xor r<RD>, r<RS>, r<RT>" |
c5d00cc7 CD |
2934 | *mipsI: |
2935 | *mipsII: | |
2936 | *mipsIII: | |
2937 | *mipsIV: | |
603a98e7 | 2938 | *mipsV: |
c906108c SS |
2939 | *vr4100: |
2940 | *vr5000: | |
2941 | *r3900: | |
2942 | { | |
2943 | do_xor (SD_, RS, RT, RD); | |
2944 | } | |
2945 | ||
2946 | ||
2947 | :function:::void:do_xori:int rs, int rt, unsigned16 immediate | |
2948 | { | |
2949 | TRACE_ALU_INPUT2 (GPR[rs], immediate); | |
2950 | GPR[rt] = GPR[rs] ^ immediate; | |
2951 | TRACE_ALU_RESULT (GPR[rt]); | |
2952 | } | |
2953 | ||
2954 | 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI | |
2955 | "xori r<RT>, r<RS>, <IMMEDIATE>" | |
c5d00cc7 CD |
2956 | *mipsI: |
2957 | *mipsII: | |
2958 | *mipsIII: | |
2959 | *mipsIV: | |
603a98e7 | 2960 | *mipsV: |
c906108c SS |
2961 | *vr4100: |
2962 | *vr5000: | |
2963 | *r3900: | |
2964 | { | |
2965 | do_xori (SD_, RS, RT, IMMEDIATE); | |
2966 | } | |
2967 | ||
2968 | \f | |
2969 | // | |
2970 | // MIPS Architecture: | |
2971 | // | |
2972 | // FPU Instruction Set (COP1 & COP1X) | |
2973 | // | |
2974 | ||
2975 | ||
2976 | :%s::::FMT:int fmt | |
2977 | { | |
2978 | switch (fmt) | |
2979 | { | |
2980 | case fmt_single: return "s"; | |
2981 | case fmt_double: return "d"; | |
2982 | case fmt_word: return "w"; | |
2983 | case fmt_long: return "l"; | |
2984 | default: return "?"; | |
2985 | } | |
2986 | } | |
2987 | ||
2988 | :%s::::X:int x | |
2989 | { | |
2990 | switch (x) | |
2991 | { | |
2992 | case 0: return "f"; | |
2993 | case 1: return "t"; | |
2994 | default: return "?"; | |
2995 | } | |
2996 | } | |
2997 | ||
2998 | :%s::::TF:int tf | |
2999 | { | |
3000 | if (tf) | |
3001 | return "t"; | |
3002 | else | |
3003 | return "f"; | |
3004 | } | |
3005 | ||
3006 | :%s::::ND:int nd | |
3007 | { | |
3008 | if (nd) | |
3009 | return "l"; | |
3010 | else | |
3011 | return ""; | |
3012 | } | |
3013 | ||
3014 | :%s::::COND:int cond | |
3015 | { | |
3016 | switch (cond) | |
3017 | { | |
3018 | case 00: return "f"; | |
3019 | case 01: return "un"; | |
3020 | case 02: return "eq"; | |
3021 | case 03: return "ueq"; | |
3022 | case 04: return "olt"; | |
3023 | case 05: return "ult"; | |
3024 | case 06: return "ole"; | |
3025 | case 07: return "ule"; | |
3026 | case 010: return "sf"; | |
3027 | case 011: return "ngle"; | |
3028 | case 012: return "seq"; | |
3029 | case 013: return "ngl"; | |
3030 | case 014: return "lt"; | |
3031 | case 015: return "nge"; | |
3032 | case 016: return "le"; | |
3033 | case 017: return "ngt"; | |
3034 | default: return "?"; | |
3035 | } | |
3036 | } | |
3037 | ||
ca971540 | 3038 | // Helper: |
4a0bd876 | 3039 | // |
ca971540 CD |
3040 | // Check that the FPU is currently usable, and signal a CoProcessorUnusable |
3041 | // exception if not. | |
3042 | // | |
3043 | ||
3044 | :function:::void:check_fpu: | |
4a0bd876 | 3045 | *mipsI: |
ca971540 CD |
3046 | *mipsII: |
3047 | *mipsIII: | |
3048 | *mipsIV: | |
3049 | *mipsV: | |
3050 | *vr4100: | |
3051 | *vr5000: | |
3052 | *r3900: | |
3053 | { | |
3054 | #if 0 /* XXX FIXME: For now, never treat the FPU as disabled. */ | |
3055 | if (! COP_Usable (1)) | |
3056 | SignalExceptionCoProcessorUnusable (1); | |
3057 | #endif | |
3058 | } | |
3059 | ||
c906108c SS |
3060 | |
3061 | 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt | |
3062 | "abs.%s<FMT> f<FD>, f<FS>" | |
c5d00cc7 CD |
3063 | *mipsI: |
3064 | *mipsII: | |
3065 | *mipsIII: | |
3066 | *mipsIV: | |
603a98e7 | 3067 | *mipsV: |
c906108c SS |
3068 | *vr4100: |
3069 | *vr5000: | |
3070 | *r3900: | |
3071 | { | |
c1e8ada4 | 3072 | int fmt = FMT; |
ca971540 | 3073 | check_fpu(SD_); |
c906108c | 3074 | { |
c1e8ada4 CD |
3075 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
3076 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3077 | else |
c1e8ada4 | 3078 | StoreFPR(FD,fmt,AbsoluteValue(ValueFPR(FS,fmt),fmt)); |
c906108c SS |
3079 | } |
3080 | } | |
3081 | ||
3082 | ||
3083 | ||
3084 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt | |
3085 | "add.%s<FMT> f<FD>, f<FS>, f<FT>" | |
c5d00cc7 CD |
3086 | *mipsI: |
3087 | *mipsII: | |
3088 | *mipsIII: | |
3089 | *mipsIV: | |
603a98e7 | 3090 | *mipsV: |
c906108c SS |
3091 | *vr4100: |
3092 | *vr5000: | |
3093 | *r3900: | |
3094 | { | |
c1e8ada4 | 3095 | int fmt = FMT; |
ca971540 | 3096 | check_fpu(SD_); |
c906108c | 3097 | { |
c1e8ada4 CD |
3098 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
3099 | SignalException(ReservedInstruction, instruction_0); | |
c906108c | 3100 | else |
c1e8ada4 | 3101 | StoreFPR(FD,fmt,Add(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt)); |
c906108c SS |
3102 | } |
3103 | } | |
3104 | ||
3105 | ||
3106 | ||
3107 | // BC1F | |
3108 | // BC1FL | |
3109 | // BC1T | |
3110 | // BC1TL | |
3111 | ||
3112 | 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a | |
3113 | "bc1%s<TF>%s<ND> <OFFSET>" | |
c5d00cc7 CD |
3114 | *mipsI: |
3115 | *mipsII: | |
3116 | *mipsIII: | |
c906108c | 3117 | { |
ca971540 | 3118 | check_fpu(SD_); |
c906108c SS |
3119 | check_branch_bug (); |
3120 | TRACE_BRANCH_INPUT (PREVCOC1()); | |
3121 | if (PREVCOC1() == TF) | |
3122 | { | |
3123 | address_word dest = NIA + (EXTEND16 (OFFSET) << 2); | |
3124 | TRACE_BRANCH_RESULT (dest); | |
3125 | mark_branch_bug (dest); | |
3126 | DELAY_SLOT (dest); | |
3127 | } | |
3128 | else if (ND) | |
3129 | { | |
3130 | TRACE_BRANCH_RESULT (0); | |
3131 | NULLIFY_NEXT_INSTRUCTION (); | |
3132 | } | |
3133 | else | |
3134 | { | |
3135 | TRACE_BRANCH_RESULT (NIA); | |
3136 | } | |
3137 | } | |
3138 | ||
3139 | 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b | |
3140 | "bc1%s<TF>%s<ND> <OFFSET>":CC == 0 | |
3141 | "bc1%s<TF>%s<ND> <CC>, <OFFSET>" | |
3142 | *mipsIV: | |
603a98e7 | 3143 | *mipsV: |
c906108c | 3144 | #*vr4100: |
074e9cb8 | 3145 | *vr5000: |
c906108c SS |
3146 | *r3900: |
3147 | { | |
ca971540 | 3148 | check_fpu(SD_); |
c906108c SS |
3149 | check_branch_bug (); |
3150 | if (GETFCC(CC) == TF) | |
3151 | { | |
3152 | address_word dest = NIA + (EXTEND16 (OFFSET) << 2); | |
3153 | mark_branch_bug (dest); | |
3154 | DELAY_SLOT (dest); | |
3155 | } | |
3156 | else if (ND) | |
3157 | { | |
3158 | NULLIFY_NEXT_INSTRUCTION (); | |
3159 | } | |
3160 | } | |
3161 | ||
3162 | ||
3163 | ||
3164 | ||
3165 | ||
3166 | ||
3167 | // C.EQ.S | |
3168 | // C.EQ.D | |
3169 | // ... | |
3170 | ||
3171 | :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn | |
3172 | { | |
3173 | if ((fmt != fmt_single) && (fmt != fmt_double)) | |
3174 | SignalException (ReservedInstruction, insn); | |
3175 | else | |
3176 | { | |
3177 | int less; | |
3178 | int equal; | |
3179 | int unordered; | |
3180 | int condition; | |
3181 | unsigned64 ofs = ValueFPR (fs, fmt); | |
3182 | unsigned64 oft = ValueFPR (ft, fmt); | |
3183 | if (NaN (ofs, fmt) || NaN (oft, fmt)) | |
3184 | { | |
3185 | if (FCSR & FP_ENABLE (IO)) | |
3186 | { | |
3187 | FCSR |= FP_CAUSE (IO); | |
3188 | SignalExceptionFPE (); | |
3189 | } | |
3190 | less = 0; | |
3191 | equal = 0; | |
3192 | unordered = 1; | |
3193 | } | |
3194 | else | |
3195 | { | |
3196 | less = Less (ofs, oft, fmt); | |
3197 | equal = Equal (ofs, oft, fmt); | |
3198 | unordered = 0; | |
3199 | } | |
3200 | condition = (((cond & (1 << 2)) && less) | |
3201 | || ((cond & (1 << 1)) && equal) | |
3202 | || ((cond & (1 << 0)) && unordered)); | |
3203 | SETFCC (cc, condition); | |
3204 | } | |
3205 | } | |
3206 | ||
eb5fcf93 | 3207 | 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta |
c906108c | 3208 | "c.%s<COND>.%s<FMT> f<FS>, f<FT>" |
c5d00cc7 CD |
3209 | *mipsI: |
3210 | *mipsII: | |
3211 | *mipsIII: | |
c906108c | 3212 | { |
ca971540 | 3213 | check_fpu(SD_); |
c906108c SS |
3214 | do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0); |
3215 | } | |
3216 | ||
eb5fcf93 | 3217 | 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb |
c906108c SS |
3218 | "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0 |
3219 | "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>" | |
3220 | *mipsIV: | |
603a98e7 | 3221 | *mipsV: |
c906108c SS |
3222 | *vr4100: |
3223 | *vr5000: | |
3224 | *r3900: | |
3225 | { | |
ca971540 | 3226 | check_fpu(SD_); |
c906108c SS |
3227 | do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0); |
3228 | } | |
3229 | ||
3230 | ||
eb5fcf93 | 3231 | 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt |
c906108c SS |
3232 | "ceil.l.%s<FMT> f<FD>, f<FS>" |
3233 | *mipsIII: | |
3234 | *mipsIV: | |
603a98e7 | 3235 | *mipsV: |
c906108c SS |
3236 | *vr4100: |
3237 | *vr5000: | |
3238 | *r3900: | |
3239 | { | |
c1e8ada4 | 3240 | int fmt = FMT; |
ca971540 | 3241 | check_fpu(SD_); |
c906108c | 3242 | { |
c1e8ada4 CD |
3243 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
3244 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3245 | else |
c1e8ada4 | 3246 | StoreFPR(FD,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_long)); |
c906108c SS |
3247 | } |
3248 | } | |
3249 | ||
3250 | ||
eb5fcf93 | 3251 | 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W |
c906108c SS |
3252 | *mipsII: |
3253 | *mipsIII: | |
3254 | *mipsIV: | |
603a98e7 | 3255 | *mipsV: |
c906108c SS |
3256 | *vr4100: |
3257 | *vr5000: | |
3258 | *r3900: | |
3259 | { | |
c1e8ada4 | 3260 | int fmt = FMT; |
ca971540 | 3261 | check_fpu(SD_); |
c906108c | 3262 | { |
c1e8ada4 CD |
3263 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
3264 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3265 | else |
c1e8ada4 | 3266 | StoreFPR(FD,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_word)); |
c906108c SS |
3267 | } |
3268 | } | |
3269 | ||
3270 | ||
3271 | // CFC1 | |
3272 | // CTC1 | |
eb5fcf93 | 3273 | 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32,f::CxC1 |
c906108c SS |
3274 | "c%s<X>c1 r<RT>, f<FS>" |
3275 | *mipsI: | |
3276 | *mipsII: | |
3277 | *mipsIII: | |
3278 | { | |
ca971540 | 3279 | check_fpu(SD_); |
c906108c SS |
3280 | if (X) |
3281 | { | |
3282 | if (FS == 0) | |
c0efbca4 | 3283 | PENDING_FILL(FCR0IDX,VL4_8(GPR[RT])); |
c906108c | 3284 | else if (FS == 31) |
c0efbca4 | 3285 | PENDING_FILL(FCR31IDX,VL4_8(GPR[RT])); |
c906108c | 3286 | /* else NOP */ |
c0efbca4 | 3287 | PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23); |
c906108c SS |
3288 | } |
3289 | else | |
3290 | { /* control from */ | |
3291 | if (FS == 0) | |
043b7057 | 3292 | PENDING_FILL(RT, EXTEND32 (FCR0)); |
c906108c | 3293 | else if (FS == 31) |
043b7057 | 3294 | PENDING_FILL(RT, EXTEND32 (FCR31)); |
c906108c SS |
3295 | /* else NOP */ |
3296 | } | |
3297 | } | |
eb5fcf93 | 3298 | 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32,f::CxC1 |
c906108c SS |
3299 | "c%s<X>c1 r<RT>, f<FS>" |
3300 | *mipsIV: | |
603a98e7 | 3301 | *mipsV: |
c906108c SS |
3302 | *vr4100: |
3303 | *vr5000: | |
3304 | *r3900: | |
3305 | { | |
ca971540 | 3306 | check_fpu(SD_); |
c906108c SS |
3307 | if (X) |
3308 | { | |
3309 | /* control to */ | |
3310 | TRACE_ALU_INPUT1 (GPR[RT]); | |
3311 | if (FS == 0) | |
3312 | { | |
3313 | FCR0 = VL4_8(GPR[RT]); | |
3314 | TRACE_ALU_RESULT (FCR0); | |
3315 | } | |
3316 | else if (FS == 31) | |
3317 | { | |
3318 | FCR31 = VL4_8(GPR[RT]); | |
3319 | SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0)); | |
3320 | TRACE_ALU_RESULT (FCR31); | |
3321 | } | |
3322 | else | |
3323 | { | |
3324 | TRACE_ALU_RESULT0 (); | |
3325 | } | |
3326 | /* else NOP */ | |
3327 | } | |
3328 | else | |
3329 | { /* control from */ | |
3330 | if (FS == 0) | |
3331 | { | |
3332 | TRACE_ALU_INPUT1 (FCR0); | |
043b7057 | 3333 | GPR[RT] = EXTEND32 (FCR0); |
c906108c SS |
3334 | } |
3335 | else if (FS == 31) | |
3336 | { | |
3337 | TRACE_ALU_INPUT1 (FCR31); | |
043b7057 | 3338 | GPR[RT] = EXTEND32 (FCR31); |
c906108c SS |
3339 | } |
3340 | TRACE_ALU_RESULT (GPR[RT]); | |
3341 | /* else NOP */ | |
3342 | } | |
3343 | } | |
3344 | ||
3345 | ||
3346 | // | |
3347 | // FIXME: Does not correctly differentiate between mips* | |
3348 | // | |
eb5fcf93 | 3349 | 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt |
c906108c | 3350 | "cvt.d.%s<FMT> f<FD>, f<FS>" |
c5d00cc7 CD |
3351 | *mipsI: |
3352 | *mipsII: | |
3353 | *mipsIII: | |
3354 | *mipsIV: | |
603a98e7 | 3355 | *mipsV: |
c906108c SS |
3356 | *vr4100: |
3357 | *vr5000: | |
3358 | *r3900: | |
3359 | { | |
c1e8ada4 | 3360 | int fmt = FMT; |
ca971540 | 3361 | check_fpu(SD_); |
c906108c | 3362 | { |
c1e8ada4 CD |
3363 | if ((fmt == fmt_double) | 0) |
3364 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3365 | else |
c1e8ada4 | 3366 | StoreFPR(FD,fmt_double,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_double)); |
c906108c SS |
3367 | } |
3368 | } | |
3369 | ||
3370 | ||
eb5fcf93 | 3371 | 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt |
c906108c SS |
3372 | "cvt.l.%s<FMT> f<FD>, f<FS>" |
3373 | *mipsIII: | |
3374 | *mipsIV: | |
603a98e7 | 3375 | *mipsV: |
c906108c SS |
3376 | *vr4100: |
3377 | *vr5000: | |
3378 | *r3900: | |
3379 | { | |
c1e8ada4 | 3380 | int fmt = FMT; |
ca971540 | 3381 | check_fpu(SD_); |
c906108c | 3382 | { |
c1e8ada4 CD |
3383 | if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word))) |
3384 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3385 | else |
c1e8ada4 | 3386 | StoreFPR(FD,fmt_long,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_long)); |
c906108c SS |
3387 | } |
3388 | } | |
3389 | ||
3390 | ||
3391 | // | |
3392 | // FIXME: Does not correctly differentiate between mips* | |
3393 | // | |
eb5fcf93 | 3394 | 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt |
c906108c | 3395 | "cvt.s.%s<FMT> f<FD>, f<FS>" |
c5d00cc7 CD |
3396 | *mipsI: |
3397 | *mipsII: | |
3398 | *mipsIII: | |
3399 | *mipsIV: | |
603a98e7 | 3400 | *mipsV: |
c906108c SS |
3401 | *vr4100: |
3402 | *vr5000: | |
3403 | *r3900: | |
3404 | { | |
c1e8ada4 | 3405 | int fmt = FMT; |
ca971540 | 3406 | check_fpu(SD_); |
c906108c | 3407 | { |
c1e8ada4 CD |
3408 | if ((fmt == fmt_single) | 0) |
3409 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3410 | else |
c1e8ada4 | 3411 | StoreFPR(FD,fmt_single,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_single)); |
c906108c SS |
3412 | } |
3413 | } | |
3414 | ||
3415 | ||
eb5fcf93 | 3416 | 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt |
c906108c | 3417 | "cvt.w.%s<FMT> f<FD>, f<FS>" |
c5d00cc7 CD |
3418 | *mipsI: |
3419 | *mipsII: | |
3420 | *mipsIII: | |
3421 | *mipsIV: | |
603a98e7 | 3422 | *mipsV: |
c906108c SS |
3423 | *vr4100: |
3424 | *vr5000: | |
3425 | *r3900: | |
3426 | { | |
c1e8ada4 | 3427 | int fmt = FMT; |
ca971540 | 3428 | check_fpu(SD_); |
c906108c | 3429 | { |
c1e8ada4 CD |
3430 | if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word))) |
3431 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3432 | else |
c1e8ada4 | 3433 | StoreFPR(FD,fmt_word,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_word)); |
c906108c SS |
3434 | } |
3435 | } | |
3436 | ||
3437 | ||
eb5fcf93 | 3438 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt |
c906108c | 3439 | "div.%s<FMT> f<FD>, f<FS>, f<FT>" |
c5d00cc7 CD |
3440 | *mipsI: |
3441 | *mipsII: | |
3442 | *mipsIII: | |
3443 | *mipsIV: | |
603a98e7 | 3444 | *mipsV: |
c906108c SS |
3445 | *vr4100: |
3446 | *vr5000: | |
3447 | *r3900: | |
3448 | { | |
c1e8ada4 | 3449 | int fmt = FMT; |
ca971540 | 3450 | check_fpu(SD_); |
c906108c | 3451 | { |
c1e8ada4 CD |
3452 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
3453 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3454 | else |
c1e8ada4 | 3455 | StoreFPR(FD,fmt,Divide(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt)); |
c906108c SS |
3456 | } |
3457 | } | |
3458 | ||
3459 | ||
3460 | // DMFC1 | |
3461 | // DMTC1 | |
eb5fcf93 | 3462 | 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64,f::DMxC1 |
c906108c SS |
3463 | "dm%s<X>c1 r<RT>, f<FS>" |
3464 | *mipsIII: | |
3465 | { | |
ca971540 CD |
3466 | check_fpu(SD_); |
3467 | check_u64 (SD_, instruction_0); | |
c906108c SS |
3468 | if (X) |
3469 | { | |
3470 | if (SizeFGR() == 64) | |
3471 | PENDING_FILL((FS + FGRIDX),GPR[RT]); | |
3472 | else if ((FS & 0x1) == 0) | |
3473 | { | |
3474 | PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT])); | |
3475 | PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT])); | |
3476 | } | |
3477 | } | |
3478 | else | |
3479 | { | |
3480 | if (SizeFGR() == 64) | |
3481 | PENDING_FILL(RT,FGR[FS]); | |
3482 | else if ((FS & 0x1) == 0) | |
3483 | PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS])); | |
3484 | else | |
a3027dd7 FCE |
3485 | { |
3486 | if (STATE_VERBOSE_P(SD)) | |
4a0bd876 | 3487 | sim_io_eprintf (SD, |
673388c0 AC |
3488 | "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n", |
3489 | (long) CIA); | |
a3027dd7 FCE |
3490 | PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0); |
3491 | } | |
c906108c SS |
3492 | } |
3493 | } | |
eb5fcf93 | 3494 | 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64,f::DMxC1 |
c906108c SS |
3495 | "dm%s<X>c1 r<RT>, f<FS>" |
3496 | *mipsIV: | |
603a98e7 | 3497 | *mipsV: |
c906108c SS |
3498 | *vr4100: |
3499 | *vr5000: | |
3500 | *r3900: | |
3501 | { | |
ca971540 CD |
3502 | check_fpu(SD_); |
3503 | check_u64 (SD_, instruction_0); | |
c906108c SS |
3504 | if (X) |
3505 | { | |
3506 | if (SizeFGR() == 64) | |
3507 | StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]); | |
3508 | else if ((FS & 0x1) == 0) | |
3509 | StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]); | |
3510 | } | |
3511 | else | |
3512 | { | |
3513 | if (SizeFGR() == 64) | |
3514 | GPR[RT] = FGR[FS]; | |
3515 | else if ((FS & 0x1) == 0) | |
3516 | GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS]; | |
3517 | else | |
a3027dd7 FCE |
3518 | { |
3519 | if (STATE_VERBOSE_P(SD)) | |
4a0bd876 | 3520 | sim_io_eprintf (SD, |
dd37a34b AC |
3521 | "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n", |
3522 | (long) CIA); | |
a3027dd7 FCE |
3523 | GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; |
3524 | } | |
c906108c SS |
3525 | } |
3526 | } | |
3527 | ||
3528 | ||
eb5fcf93 | 3529 | 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt |
c906108c SS |
3530 | "floor.l.%s<FMT> f<FD>, f<FS>" |
3531 | *mipsIII: | |
3532 | *mipsIV: | |
603a98e7 | 3533 | *mipsV: |
c906108c SS |
3534 | *vr4100: |
3535 | *vr5000: | |
3536 | *r3900: | |
3537 | { | |
c1e8ada4 | 3538 | int fmt = FMT; |
ca971540 | 3539 | check_fpu(SD_); |
c906108c | 3540 | { |
c1e8ada4 CD |
3541 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
3542 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3543 | else |
41774c9d | 3544 | StoreFPR(FD,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_long)); |
c906108c SS |
3545 | } |
3546 | } | |
3547 | ||
3548 | ||
eb5fcf93 | 3549 | 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt |
c906108c SS |
3550 | "floor.w.%s<FMT> f<FD>, f<FS>" |
3551 | *mipsII: | |
3552 | *mipsIII: | |
3553 | *mipsIV: | |
603a98e7 | 3554 | *mipsV: |
c906108c SS |
3555 | *vr4100: |
3556 | *vr5000: | |
3557 | *r3900: | |
3558 | { | |
c1e8ada4 | 3559 | int fmt = FMT; |
ca971540 | 3560 | check_fpu(SD_); |
c906108c | 3561 | { |
c1e8ada4 CD |
3562 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
3563 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3564 | else |
c1e8ada4 | 3565 | StoreFPR(FD,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_word)); |
c906108c SS |
3566 | } |
3567 | } | |
3568 | ||
3569 | ||
387f484a | 3570 | 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1 |
c906108c SS |
3571 | "ldc1 f<FT>, <OFFSET>(r<BASE>)" |
3572 | *mipsII: | |
3573 | *mipsIII: | |
3574 | *mipsIV: | |
603a98e7 | 3575 | *mipsV: |
c906108c SS |
3576 | *vr4100: |
3577 | *vr5000: | |
3578 | *r3900: | |
3579 | { | |
ca971540 | 3580 | check_fpu(SD_); |
c906108c SS |
3581 | COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); |
3582 | } | |
3583 | ||
3584 | ||
eb5fcf93 | 3585 | 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1 |
c906108c SS |
3586 | "ldxc1 f<FD>, r<INDEX>(r<BASE>)" |
3587 | *mipsIV: | |
603a98e7 | 3588 | *mipsV: |
c906108c SS |
3589 | *vr5000: |
3590 | { | |
ca971540 CD |
3591 | check_fpu(SD_); |
3592 | check_u64 (SD_, instruction_0); | |
c906108c SS |
3593 | COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX])); |
3594 | } | |
3595 | ||
3596 | ||
3597 | ||
4a0bd876 | 3598 | 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1 |
c906108c | 3599 | "lwc1 f<FT>, <OFFSET>(r<BASE>)" |
c5d00cc7 CD |
3600 | *mipsI: |
3601 | *mipsII: | |
3602 | *mipsIII: | |
3603 | *mipsIV: | |
603a98e7 | 3604 | *mipsV: |
c906108c SS |
3605 | *vr4100: |
3606 | *vr5000: | |
3607 | *r3900: | |
3608 | { | |
ca971540 | 3609 | check_fpu(SD_); |
c906108c SS |
3610 | COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); |
3611 | } | |
3612 | ||
3613 | ||
eb5fcf93 | 3614 | 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1 |
c906108c SS |
3615 | "lwxc1 f<FD>, r<INDEX>(r<BASE>)" |
3616 | *mipsIV: | |
603a98e7 | 3617 | *mipsV: |
c906108c SS |
3618 | *vr5000: |
3619 | { | |
ca971540 CD |
3620 | check_fpu(SD_); |
3621 | check_u64 (SD_, instruction_0); | |
c906108c SS |
3622 | COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX])); |
3623 | } | |
3624 | ||
3625 | ||
3626 | ||
3627 | // | |
3628 | // FIXME: Not correct for mips* | |
3629 | // | |
3630 | 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D | |
3631 | "madd.d f<FD>, f<FR>, f<FS>, f<FT>" | |
3632 | *mipsIV: | |
603a98e7 | 3633 | *mipsV: |
c906108c SS |
3634 | *vr5000: |
3635 | { | |
ca971540 | 3636 | check_fpu(SD_); |
c906108c | 3637 | { |
c1e8ada4 | 3638 | StoreFPR(FD,fmt_double,Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double)); |
c906108c SS |
3639 | } |
3640 | } | |
3641 | ||
3642 | ||
3643 | 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S | |
3644 | "madd.s f<FD>, f<FR>, f<FS>, f<FT>" | |
3645 | *mipsIV: | |
603a98e7 | 3646 | *mipsV: |
c906108c SS |
3647 | *vr5000: |
3648 | { | |
ca971540 | 3649 | check_fpu(SD_); |
c906108c | 3650 | { |
c1e8ada4 | 3651 | StoreFPR(FD,fmt_single,Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single)); |
c906108c SS |
3652 | } |
3653 | } | |
3654 | ||
3655 | ||
3656 | // MFC1 | |
3657 | // MTC1 | |
eb5fcf93 | 3658 | 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32,f::MxC1 |
c906108c SS |
3659 | "m%s<X>c1 r<RT>, f<FS>" |
3660 | *mipsI: | |
3661 | *mipsII: | |
3662 | *mipsIII: | |
3663 | { | |
ca971540 | 3664 | check_fpu(SD_); |
c906108c SS |
3665 | if (X) |
3666 | { /*MTC1*/ | |
3667 | if (SizeFGR() == 64) | |
a3027dd7 FCE |
3668 | { |
3669 | if (STATE_VERBOSE_P(SD)) | |
4a0bd876 | 3670 | sim_io_eprintf (SD, |
673388c0 AC |
3671 | "Warning: PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n", |
3672 | (long) CIA); | |
a3027dd7 FCE |
3673 | PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT]))); |
3674 | } | |
c906108c SS |
3675 | else |
3676 | PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT])); | |
3677 | } | |
3678 | else /*MFC1*/ | |
043b7057 | 3679 | PENDING_FILL (RT, EXTEND32 (FGR[FS])); |
c906108c | 3680 | } |
eb5fcf93 | 3681 | 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1 |
c906108c SS |
3682 | "m%s<X>c1 r<RT>, f<FS>" |
3683 | *mipsIV: | |
603a98e7 | 3684 | *mipsV: |
c906108c SS |
3685 | *vr4100: |
3686 | *vr5000: | |
3687 | *r3900: | |
3688 | { | |
3689 | int fs = FS; | |
ca971540 | 3690 | check_fpu(SD_); |
c906108c SS |
3691 | if (X) |
3692 | /*MTC1*/ | |
3693 | StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT])); | |
3694 | else /*MFC1*/ | |
043b7057 | 3695 | GPR[RT] = EXTEND32 (FGR[FS]); |
c906108c SS |
3696 | } |
3697 | ||
3698 | ||
eb5fcf93 | 3699 | 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt |
c906108c | 3700 | "mov.%s<FMT> f<FD>, f<FS>" |
c5d00cc7 CD |
3701 | *mipsI: |
3702 | *mipsII: | |
3703 | *mipsIII: | |
3704 | *mipsIV: | |
603a98e7 | 3705 | *mipsV: |
c906108c SS |
3706 | *vr4100: |
3707 | *vr5000: | |
3708 | *r3900: | |
3709 | { | |
c1e8ada4 | 3710 | int fmt = FMT; |
ca971540 | 3711 | check_fpu(SD_); |
c1e8ada4 | 3712 | StoreFPR(FD,fmt,ValueFPR(FS,fmt)); |
c906108c SS |
3713 | } |
3714 | ||
3715 | ||
3716 | // MOVF | |
c2d11a7d | 3717 | // MOVT |
eb5fcf93 | 3718 | 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf |
c906108c SS |
3719 | "mov%s<TF> r<RD>, r<RS>, <CC>" |
3720 | *mipsIV: | |
603a98e7 | 3721 | *mipsV: |
c906108c SS |
3722 | *vr5000: |
3723 | { | |
ca971540 | 3724 | check_fpu(SD_); |
c906108c SS |
3725 | if (GETFCC(CC) == TF) |
3726 | GPR[RD] = GPR[RS]; | |
3727 | } | |
3728 | ||
3729 | ||
3730 | // MOVF.fmt | |
c2d11a7d | 3731 | // MOVT.fmt |
eb5fcf93 | 3732 | 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt |
c906108c SS |
3733 | "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>" |
3734 | *mipsIV: | |
603a98e7 | 3735 | *mipsV: |
c906108c SS |
3736 | *vr5000: |
3737 | { | |
c1e8ada4 | 3738 | int fmt = FMT; |
ca971540 | 3739 | check_fpu(SD_); |
c906108c SS |
3740 | { |
3741 | if (GETFCC(CC) == TF) | |
c1e8ada4 | 3742 | StoreFPR (FD, fmt, ValueFPR (FS, fmt)); |
c906108c | 3743 | else |
c1e8ada4 | 3744 | StoreFPR (FD, fmt, ValueFPR (FD, fmt)); |
c906108c SS |
3745 | } |
3746 | } | |
3747 | ||
3748 | ||
eb5fcf93 | 3749 | 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt |
80ee11fa | 3750 | "movn.%s<FMT> f<FD>, f<FS>, r<RT>" |
c906108c | 3751 | *mipsIV: |
603a98e7 | 3752 | *mipsV: |
c906108c SS |
3753 | *vr5000: |
3754 | { | |
ca971540 | 3755 | check_fpu(SD_); |
80ee11fa AC |
3756 | if (GPR[RT] != 0) |
3757 | StoreFPR (FD, FMT, ValueFPR (FS, FMT)); | |
3758 | else | |
3759 | StoreFPR (FD, FMT, ValueFPR (FD, FMT)); | |
c906108c SS |
3760 | } |
3761 | ||
3762 | ||
3763 | // MOVT see MOVtf | |
3764 | ||
3765 | ||
3766 | // MOVT.fmt see MOVtf.fmt | |
3767 | ||
3768 | ||
3769 | ||
eb5fcf93 | 3770 | 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt |
c906108c SS |
3771 | "movz.%s<FMT> f<FD>, f<FS>, r<RT>" |
3772 | *mipsIV: | |
603a98e7 | 3773 | *mipsV: |
c906108c SS |
3774 | *vr5000: |
3775 | { | |
ca971540 | 3776 | check_fpu(SD_); |
80ee11fa AC |
3777 | if (GPR[RT] == 0) |
3778 | StoreFPR (FD, FMT, ValueFPR (FS, FMT)); | |
3779 | else | |
3780 | StoreFPR (FD, FMT, ValueFPR (FD, FMT)); | |
c906108c SS |
3781 | } |
3782 | ||
3783 | ||
3784 | // MSUB.fmt | |
eb5fcf93 | 3785 | 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32,f::MSUB.D |
c906108c SS |
3786 | "msub.d f<FD>, f<FR>, f<FS>, f<FT>" |
3787 | *mipsIV: | |
603a98e7 | 3788 | *mipsV: |
c906108c SS |
3789 | *vr5000: |
3790 | { | |
ca971540 | 3791 | check_fpu(SD_); |
c1e8ada4 | 3792 | StoreFPR(FD,fmt_double,Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double)); |
c906108c SS |
3793 | } |
3794 | ||
3795 | ||
3796 | // MSUB.fmt | |
eb5fcf93 | 3797 | 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32,f::MSUB.S |
c906108c SS |
3798 | "msub.s f<FD>, f<FR>, f<FS>, f<FT>" |
3799 | *mipsIV: | |
603a98e7 | 3800 | *mipsV: |
c906108c SS |
3801 | *vr5000: |
3802 | { | |
ca971540 | 3803 | check_fpu(SD_); |
c1e8ada4 | 3804 | StoreFPR(FD,fmt_single,Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single)); |
c906108c SS |
3805 | } |
3806 | ||
3807 | ||
3808 | // MTC1 see MxC1 | |
3809 | ||
3810 | ||
eb5fcf93 | 3811 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt |
c906108c | 3812 | "mul.%s<FMT> f<FD>, f<FS>, f<FT>" |
c5d00cc7 CD |
3813 | *mipsI: |
3814 | *mipsII: | |
3815 | *mipsIII: | |
3816 | *mipsIV: | |
603a98e7 | 3817 | *mipsV: |
c906108c SS |
3818 | *vr4100: |
3819 | *vr5000: | |
3820 | *r3900: | |
3821 | { | |
c1e8ada4 | 3822 | int fmt = FMT; |
ca971540 | 3823 | check_fpu(SD_); |
c906108c | 3824 | { |
c1e8ada4 CD |
3825 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
3826 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3827 | else |
c1e8ada4 | 3828 | StoreFPR(FD,fmt,Multiply(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt)); |
c906108c SS |
3829 | } |
3830 | } | |
3831 | ||
3832 | ||
eb5fcf93 | 3833 | 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt |
c906108c | 3834 | "neg.%s<FMT> f<FD>, f<FS>" |
c5d00cc7 CD |
3835 | *mipsI: |
3836 | *mipsII: | |
3837 | *mipsIII: | |
3838 | *mipsIV: | |
603a98e7 | 3839 | *mipsV: |
c906108c SS |
3840 | *vr4100: |
3841 | *vr5000: | |
3842 | *r3900: | |
3843 | { | |
c1e8ada4 | 3844 | int fmt = FMT; |
ca971540 | 3845 | check_fpu(SD_); |
c906108c | 3846 | { |
c1e8ada4 CD |
3847 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
3848 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3849 | else |
c1e8ada4 | 3850 | StoreFPR(FD,fmt,Negate(ValueFPR(FS,fmt),fmt)); |
c906108c SS |
3851 | } |
3852 | } | |
3853 | ||
3854 | ||
3855 | // NMADD.fmt | |
eb5fcf93 | 3856 | 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32,f::NMADD.D |
c906108c SS |
3857 | "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>" |
3858 | *mipsIV: | |
603a98e7 | 3859 | *mipsV: |
c906108c SS |
3860 | *vr5000: |
3861 | { | |
ca971540 | 3862 | check_fpu(SD_); |
c1e8ada4 | 3863 | StoreFPR(FD,fmt_double,Negate(Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double)); |
c906108c SS |
3864 | } |
3865 | ||
3866 | ||
3867 | // NMADD.fmt | |
eb5fcf93 | 3868 | 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32,f::NMADD.S |
c906108c SS |
3869 | "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>" |
3870 | *mipsIV: | |
603a98e7 | 3871 | *mipsV: |
c906108c SS |
3872 | *vr5000: |
3873 | { | |
ca971540 | 3874 | check_fpu(SD_); |
c1e8ada4 | 3875 | StoreFPR(FD,fmt_single,Negate(Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single)); |
c906108c SS |
3876 | } |
3877 | ||
3878 | ||
3879 | // NMSUB.fmt | |
eb5fcf93 | 3880 | 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32,f::NMSUB.D |
c906108c SS |
3881 | "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>" |
3882 | *mipsIV: | |
603a98e7 | 3883 | *mipsV: |
c906108c SS |
3884 | *vr5000: |
3885 | { | |
ca971540 | 3886 | check_fpu(SD_); |
c1e8ada4 | 3887 | StoreFPR(FD,fmt_double,Negate(Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double)); |
c906108c SS |
3888 | } |
3889 | ||
3890 | ||
3891 | // NMSUB.fmt | |
eb5fcf93 | 3892 | 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32,f::NMSUB.S |
c906108c SS |
3893 | "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>" |
3894 | *mipsIV: | |
603a98e7 | 3895 | *mipsV: |
c906108c SS |
3896 | *vr5000: |
3897 | { | |
ca971540 | 3898 | check_fpu(SD_); |
c1e8ada4 | 3899 | StoreFPR(FD,fmt_single,Negate(Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single)); |
c906108c SS |
3900 | } |
3901 | ||
3902 | ||
3d81f391 | 3903 | 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX |
c906108c SS |
3904 | "prefx <HINT>, r<INDEX>(r<BASE>)" |
3905 | *mipsIV: | |
603a98e7 | 3906 | *mipsV: |
c906108c SS |
3907 | *vr5000: |
3908 | { | |
c1e8ada4 CD |
3909 | address_word base = GPR[BASE]; |
3910 | address_word index = GPR[INDEX]; | |
c906108c | 3911 | { |
09297648 | 3912 | address_word vaddr = loadstore_ea (SD_, base, index); |
c906108c SS |
3913 | address_word paddr; |
3914 | int uncached; | |
3915 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
c1e8ada4 | 3916 | Prefetch(uncached,paddr,vaddr,isDATA,HINT); |
c906108c SS |
3917 | } |
3918 | } | |
3919 | ||
eb5fcf93 | 3920 | 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt |
c906108c | 3921 | "recip.%s<FMT> f<FD>, f<FS>" |
e514a9d6 | 3922 | *mipsIV: |
603a98e7 | 3923 | *mipsV: |
c906108c SS |
3924 | *vr5000: |
3925 | { | |
c1e8ada4 | 3926 | int fmt = FMT; |
ca971540 | 3927 | check_fpu(SD_); |
c906108c | 3928 | { |
c1e8ada4 CD |
3929 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
3930 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3931 | else |
c1e8ada4 | 3932 | StoreFPR(FD,fmt,Recip(ValueFPR(FS,fmt),fmt)); |
c906108c SS |
3933 | } |
3934 | } | |
3935 | ||
3936 | ||
eb5fcf93 | 3937 | 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt |
c906108c SS |
3938 | "round.l.%s<FMT> f<FD>, f<FS>" |
3939 | *mipsIII: | |
3940 | *mipsIV: | |
603a98e7 | 3941 | *mipsV: |
c906108c SS |
3942 | *vr4100: |
3943 | *vr5000: | |
3944 | *r3900: | |
3945 | { | |
c1e8ada4 | 3946 | int fmt = FMT; |
ca971540 | 3947 | check_fpu(SD_); |
c906108c | 3948 | { |
c1e8ada4 CD |
3949 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
3950 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3951 | else |
c1e8ada4 | 3952 | StoreFPR(FD,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_long)); |
c906108c SS |
3953 | } |
3954 | } | |
3955 | ||
3956 | ||
eb5fcf93 | 3957 | 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt |
c906108c SS |
3958 | "round.w.%s<FMT> f<FD>, f<FS>" |
3959 | *mipsII: | |
3960 | *mipsIII: | |
3961 | *mipsIV: | |
603a98e7 | 3962 | *mipsV: |
c906108c SS |
3963 | *vr4100: |
3964 | *vr5000: | |
3965 | *r3900: | |
3966 | { | |
c1e8ada4 | 3967 | int fmt = FMT; |
ca971540 | 3968 | check_fpu(SD_); |
c906108c | 3969 | { |
c1e8ada4 CD |
3970 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
3971 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3972 | else |
c1e8ada4 | 3973 | StoreFPR(FD,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_word)); |
c906108c SS |
3974 | } |
3975 | } | |
3976 | ||
3977 | ||
eb5fcf93 | 3978 | 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt |
c906108c | 3979 | *mipsIV: |
603a98e7 | 3980 | *mipsV: |
c906108c SS |
3981 | "rsqrt.%s<FMT> f<FD>, f<FS>" |
3982 | *vr5000: | |
3983 | { | |
c1e8ada4 | 3984 | int fmt = FMT; |
ca971540 | 3985 | check_fpu(SD_); |
c906108c | 3986 | { |
c1e8ada4 CD |
3987 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
3988 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 3989 | else |
c1e8ada4 | 3990 | StoreFPR(FD,fmt,Recip(SquareRoot(ValueFPR(FS,fmt),fmt),fmt)); |
c906108c SS |
3991 | } |
3992 | } | |
3993 | ||
3994 | ||
387f484a | 3995 | 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1 |
c906108c SS |
3996 | "sdc1 f<FT>, <OFFSET>(r<BASE>)" |
3997 | *mipsII: | |
3998 | *mipsIII: | |
3999 | *mipsIV: | |
603a98e7 | 4000 | *mipsV: |
c906108c SS |
4001 | *vr4100: |
4002 | *vr5000: | |
4003 | *r3900: | |
4004 | { | |
ca971540 | 4005 | check_fpu(SD_); |
c906108c SS |
4006 | do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT)); |
4007 | } | |
4008 | ||
4009 | ||
eb5fcf93 | 4010 | 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1 |
91a177cf | 4011 | "sdxc1 f<FS>, r<INDEX>(r<BASE>)" |
c906108c | 4012 | *mipsIV: |
603a98e7 | 4013 | *mipsV: |
c906108c SS |
4014 | *vr5000: |
4015 | { | |
ca971540 CD |
4016 | check_fpu(SD_); |
4017 | check_u64 (SD_, instruction_0); | |
c906108c SS |
4018 | do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS)); |
4019 | } | |
4020 | ||
4021 | ||
eb5fcf93 | 4022 | 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt |
c906108c SS |
4023 | "sqrt.%s<FMT> f<FD>, f<FS>" |
4024 | *mipsII: | |
4025 | *mipsIII: | |
4026 | *mipsIV: | |
603a98e7 | 4027 | *mipsV: |
c906108c SS |
4028 | *vr4100: |
4029 | *vr5000: | |
4030 | *r3900: | |
4031 | { | |
c1e8ada4 | 4032 | int fmt = FMT; |
ca971540 | 4033 | check_fpu(SD_); |
c906108c | 4034 | { |
c1e8ada4 CD |
4035 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
4036 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 4037 | else |
c1e8ada4 | 4038 | StoreFPR(FD,fmt,(SquareRoot(ValueFPR(FS,fmt),fmt))); |
c906108c SS |
4039 | } |
4040 | } | |
4041 | ||
4042 | ||
eb5fcf93 | 4043 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt |
c906108c | 4044 | "sub.%s<FMT> f<FD>, f<FS>, f<FT>" |
c5d00cc7 CD |
4045 | *mipsI: |
4046 | *mipsII: | |
4047 | *mipsIII: | |
4048 | *mipsIV: | |
603a98e7 | 4049 | *mipsV: |
c906108c SS |
4050 | *vr4100: |
4051 | *vr5000: | |
4052 | *r3900: | |
4053 | { | |
c1e8ada4 | 4054 | int fmt = FMT; |
ca971540 | 4055 | check_fpu(SD_); |
c906108c | 4056 | { |
c1e8ada4 CD |
4057 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
4058 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 4059 | else |
c1e8ada4 | 4060 | StoreFPR(FD,fmt,Sub(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt)); |
c906108c SS |
4061 | } |
4062 | } | |
4063 | ||
4064 | ||
4065 | ||
eb5fcf93 | 4066 | 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1 |
c906108c | 4067 | "swc1 f<FT>, <OFFSET>(r<BASE>)" |
c5d00cc7 CD |
4068 | *mipsI: |
4069 | *mipsII: | |
4070 | *mipsIII: | |
4071 | *mipsIV: | |
603a98e7 | 4072 | *mipsV: |
c906108c SS |
4073 | *vr4100: |
4074 | *vr5000: | |
4075 | *r3900: | |
4076 | { | |
09297648 CD |
4077 | address_word base = GPR[BASE]; |
4078 | address_word offset = EXTEND16 (OFFSET); | |
ca971540 | 4079 | check_fpu(SD_); |
c906108c | 4080 | { |
09297648 | 4081 | address_word vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
4082 | address_word paddr; |
4083 | int uncached; | |
4084 | if ((vaddr & 3) != 0) | |
4085 | { | |
4086 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal); | |
4087 | } | |
4088 | else | |
4089 | { | |
4090 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
4091 | { | |
4092 | uword64 memval = 0; | |
4093 | uword64 memval1 = 0; | |
4094 | uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); | |
4095 | address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0); | |
4096 | address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0); | |
4097 | unsigned int byte; | |
4098 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); | |
4099 | byte = ((vaddr & mask) ^ bigendiancpu); | |
c1e8ada4 | 4100 | memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte)); |
c906108c SS |
4101 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); |
4102 | } | |
4103 | } | |
4104 | } | |
4105 | } | |
4106 | ||
4107 | ||
eb5fcf93 | 4108 | 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1 |
c906108c SS |
4109 | "swxc1 f<FS>, r<INDEX>(r<BASE>)" |
4110 | *mipsIV: | |
603a98e7 | 4111 | *mipsV: |
c906108c SS |
4112 | *vr5000: |
4113 | { | |
c1e8ada4 CD |
4114 | |
4115 | address_word base = GPR[BASE]; | |
4116 | address_word index = GPR[INDEX]; | |
ca971540 CD |
4117 | check_fpu(SD_); |
4118 | check_u64 (SD_, instruction_0); | |
c906108c | 4119 | { |
09297648 | 4120 | address_word vaddr = loadstore_ea (SD_, base, index); |
c906108c SS |
4121 | address_word paddr; |
4122 | int uncached; | |
4123 | if ((vaddr & 3) != 0) | |
4124 | { | |
4125 | SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal); | |
4126 | } | |
4127 | else | |
4128 | { | |
4129 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
4130 | { | |
4131 | unsigned64 memval = 0; | |
4132 | unsigned64 memval1 = 0; | |
4133 | unsigned64 mask = 0x7; | |
4134 | unsigned int byte; | |
4135 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
4136 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
c1e8ada4 | 4137 | memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte)); |
c906108c SS |
4138 | { |
4139 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
4140 | } | |
4141 | } | |
4142 | } | |
4143 | } | |
4144 | } | |
4145 | ||
4146 | ||
eb5fcf93 | 4147 | 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt |
c906108c SS |
4148 | "trunc.l.%s<FMT> f<FD>, f<FS>" |
4149 | *mipsIII: | |
4150 | *mipsIV: | |
603a98e7 | 4151 | *mipsV: |
c906108c SS |
4152 | *vr4100: |
4153 | *vr5000: | |
4154 | *r3900: | |
4155 | { | |
c1e8ada4 | 4156 | int fmt = FMT; |
ca971540 | 4157 | check_fpu(SD_); |
c906108c | 4158 | { |
c1e8ada4 CD |
4159 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
4160 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 4161 | else |
c1e8ada4 | 4162 | StoreFPR(FD,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_long)); |
c906108c SS |
4163 | } |
4164 | } | |
4165 | ||
4166 | ||
eb5fcf93 | 4167 | 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W |
c906108c SS |
4168 | "trunc.w.%s<FMT> f<FD>, f<FS>" |
4169 | *mipsII: | |
4170 | *mipsIII: | |
4171 | *mipsIV: | |
603a98e7 | 4172 | *mipsV: |
c906108c SS |
4173 | *vr4100: |
4174 | *vr5000: | |
4175 | *r3900: | |
4176 | { | |
c1e8ada4 | 4177 | int fmt = FMT; |
ca971540 | 4178 | check_fpu(SD_); |
c906108c | 4179 | { |
c1e8ada4 CD |
4180 | if ((fmt != fmt_single) && (fmt != fmt_double)) |
4181 | SignalException(ReservedInstruction,instruction_0); | |
c906108c | 4182 | else |
c1e8ada4 | 4183 | StoreFPR(FD,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_word)); |
c906108c SS |
4184 | } |
4185 | } | |
4186 | ||
4187 | \f | |
4188 | // | |
4189 | // MIPS Architecture: | |
4190 | // | |
4191 | // System Control Instruction Set (COP0) | |
4192 | // | |
4193 | ||
4194 | ||
4195 | 010000,01000,00000,16.OFFSET:COP0:32::BC0F | |
4196 | "bc0f <OFFSET>" | |
c5d00cc7 CD |
4197 | *mipsI: |
4198 | *mipsII: | |
4199 | *mipsIII: | |
4200 | *mipsIV: | |
603a98e7 | 4201 | *mipsV: |
c906108c SS |
4202 | *vr4100: |
4203 | *vr5000: | |
4204 | ||
7a292a7a SS |
4205 | 010000,01000,00000,16.OFFSET:COP0:32::BC0F |
4206 | "bc0f <OFFSET>" | |
4207 | // stub needed for eCos as tx39 hardware bug workaround | |
4208 | *r3900: | |
4209 | { | |
4210 | /* do nothing */ | |
4211 | } | |
4212 | ||
c906108c SS |
4213 | |
4214 | 010000,01000,00010,16.OFFSET:COP0:32::BC0FL | |
4215 | "bc0fl <OFFSET>" | |
c5d00cc7 CD |
4216 | *mipsI: |
4217 | *mipsII: | |
4218 | *mipsIII: | |
4219 | *mipsIV: | |
603a98e7 | 4220 | *mipsV: |
c906108c SS |
4221 | *vr4100: |
4222 | *vr5000: | |
4223 | ||
4224 | ||
4225 | 010000,01000,00001,16.OFFSET:COP0:32::BC0T | |
4226 | "bc0t <OFFSET>" | |
c5d00cc7 CD |
4227 | *mipsI: |
4228 | *mipsII: | |
4229 | *mipsIII: | |
4230 | *mipsIV: | |
603a98e7 | 4231 | *mipsV: |
c906108c SS |
4232 | *vr4100: |
4233 | ||
4234 | ||
4235 | 010000,01000,00011,16.OFFSET:COP0:32::BC0TL | |
4236 | "bc0tl <OFFSET>" | |
c5d00cc7 CD |
4237 | *mipsI: |
4238 | *mipsII: | |
4239 | *mipsIII: | |
4240 | *mipsIV: | |
603a98e7 | 4241 | *mipsV: |
c906108c SS |
4242 | *vr4100: |
4243 | *vr5000: | |
4244 | ||
4245 | ||
4246 | 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE | |
0d3e762b | 4247 | "cache <OP>, <OFFSET>(r<BASE>)" |
c906108c SS |
4248 | *mipsIII: |
4249 | *mipsIV: | |
603a98e7 | 4250 | *mipsV: |
c906108c SS |
4251 | *vr4100: |
4252 | *vr5000: | |
4253 | *r3900: | |
4254 | { | |
c1e8ada4 CD |
4255 | address_word base = GPR[BASE]; |
4256 | address_word offset = EXTEND16 (OFFSET); | |
c906108c | 4257 | { |
09297648 | 4258 | address_word vaddr = loadstore_ea (SD_, base, offset); |
c906108c SS |
4259 | address_word paddr; |
4260 | int uncached; | |
4261 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
c1e8ada4 | 4262 | CacheOp(OP,vaddr,paddr,instruction_0); |
c906108c SS |
4263 | } |
4264 | } | |
4265 | ||
4266 | ||
f701dad2 | 4267 | 010000,1,0000000000000000000,111001:COP0:32::DI |
c906108c | 4268 | "di" |
c5d00cc7 CD |
4269 | *mipsI: |
4270 | *mipsII: | |
4271 | *mipsIII: | |
4272 | *mipsIV: | |
603a98e7 | 4273 | *mipsV: |
c906108c SS |
4274 | *vr4100: |
4275 | *vr5000: | |
4276 | ||
4277 | ||
f701dad2 | 4278 | 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0 |
9846de1b | 4279 | "dmfc0 r<RT>, r<RD>" |
c5d00cc7 CD |
4280 | *mipsIII: |
4281 | *mipsIV: | |
603a98e7 | 4282 | *mipsV: |
9846de1b | 4283 | { |
ca971540 | 4284 | check_u64 (SD_, instruction_0); |
9846de1b JM |
4285 | DecodeCoproc (instruction_0); |
4286 | } | |
4287 | ||
4288 | ||
f701dad2 | 4289 | 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0 |
9846de1b | 4290 | "dmtc0 r<RT>, r<RD>" |
c5d00cc7 CD |
4291 | *mipsIII: |
4292 | *mipsIV: | |
603a98e7 | 4293 | *mipsV: |
9846de1b | 4294 | { |
ca971540 | 4295 | check_u64 (SD_, instruction_0); |
9846de1b JM |
4296 | DecodeCoproc (instruction_0); |
4297 | } | |
4298 | ||
4299 | ||
f701dad2 | 4300 | 010000,1,0000000000000000000,111000:COP0:32::EI |
c906108c | 4301 | "ei" |
c5d00cc7 CD |
4302 | *mipsI: |
4303 | *mipsII: | |
4304 | *mipsIII: | |
4305 | *mipsIV: | |
603a98e7 | 4306 | *mipsV: |
c906108c SS |
4307 | *vr4100: |
4308 | *vr5000: | |
4309 | ||
4310 | ||
f701dad2 | 4311 | 010000,1,0000000000000000000,011000:COP0:32::ERET |
c906108c SS |
4312 | "eret" |
4313 | *mipsIII: | |
4314 | *mipsIV: | |
603a98e7 | 4315 | *mipsV: |
c906108c SS |
4316 | *vr4100: |
4317 | *vr5000: | |
4318 | { | |
4319 | if (SR & status_ERL) | |
4320 | { | |
4321 | /* Oops, not yet available */ | |
4322 | sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported"); | |
4323 | NIA = EPC; | |
4324 | SR &= ~status_ERL; | |
4325 | } | |
4326 | else | |
4327 | { | |
4328 | NIA = EPC; | |
4329 | SR &= ~status_EXL; | |
4330 | } | |
4331 | } | |
4332 | ||
4333 | ||
4334 | 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0 | |
4335 | "mfc0 r<RT>, r<RD> # <REGX>" | |
c5d00cc7 CD |
4336 | *mipsI: |
4337 | *mipsII: | |
4338 | *mipsIII: | |
4339 | *mipsIV: | |
603a98e7 | 4340 | *mipsV: |
c906108c SS |
4341 | *vr4100: |
4342 | *vr5000: | |
074e9cb8 | 4343 | *r3900: |
c906108c SS |
4344 | { |
4345 | TRACE_ALU_INPUT0 (); | |
4346 | DecodeCoproc (instruction_0); | |
4347 | TRACE_ALU_RESULT (GPR[RT]); | |
4348 | } | |
4349 | ||
4350 | 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0 | |
4351 | "mtc0 r<RT>, r<RD> # <REGX>" | |
c5d00cc7 CD |
4352 | *mipsI: |
4353 | *mipsII: | |
4354 | *mipsIII: | |
4355 | *mipsIV: | |
603a98e7 | 4356 | *mipsV: |
c906108c SS |
4357 | *vr4100: |
4358 | *vr5000: | |
074e9cb8 | 4359 | *r3900: |
c906108c SS |
4360 | { |
4361 | DecodeCoproc (instruction_0); | |
4362 | } | |
4363 | ||
4364 | ||
f701dad2 | 4365 | 010000,1,0000000000000000000,010000:COP0:32::RFE |
c906108c | 4366 | "rfe" |
c5d00cc7 CD |
4367 | *mipsI: |
4368 | *mipsII: | |
4369 | *mipsIII: | |
4370 | *mipsIV: | |
603a98e7 | 4371 | *mipsV: |
c906108c SS |
4372 | *vr4100: |
4373 | *vr5000: | |
074e9cb8 | 4374 | *r3900: |
c906108c SS |
4375 | { |
4376 | DecodeCoproc (instruction_0); | |
4377 | } | |
4378 | ||
4379 | ||
4380 | 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz | |
4381 | "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>" | |
c5d00cc7 CD |
4382 | *mipsI: |
4383 | *mipsII: | |
4384 | *mipsIII: | |
4385 | *mipsIV: | |
603a98e7 | 4386 | *mipsV: |
c906108c SS |
4387 | *vr4100: |
4388 | *r3900: | |
4389 | { | |
4390 | DecodeCoproc (instruction_0); | |
4391 | } | |
4392 | ||
4393 | ||
4394 | ||
f701dad2 | 4395 | 010000,1,0000000000000000000,001000:COP0:32::TLBP |
c906108c | 4396 | "tlbp" |
c5d00cc7 CD |
4397 | *mipsI: |
4398 | *mipsII: | |
4399 | *mipsIII: | |
4400 | *mipsIV: | |
603a98e7 | 4401 | *mipsV: |
c906108c SS |
4402 | *vr4100: |
4403 | *vr5000: | |
4404 | ||
4405 | ||
f701dad2 | 4406 | 010000,1,0000000000000000000,000001:COP0:32::TLBR |
c906108c | 4407 | "tlbr" |
c5d00cc7 CD |
4408 | *mipsI: |
4409 | *mipsII: | |
4410 | *mipsIII: | |
4411 | *mipsIV: | |
603a98e7 | 4412 | *mipsV: |
c906108c SS |
4413 | *vr4100: |
4414 | *vr5000: | |
4415 | ||
4416 | ||
f701dad2 | 4417 | 010000,1,0000000000000000000,000010:COP0:32::TLBWI |
c906108c | 4418 | "tlbwi" |
c5d00cc7 CD |
4419 | *mipsI: |
4420 | *mipsII: | |
4421 | *mipsIII: | |
4422 | *mipsIV: | |
603a98e7 | 4423 | *mipsV: |
c906108c SS |
4424 | *vr4100: |
4425 | *vr5000: | |
4426 | ||
4427 | ||
f701dad2 | 4428 | 010000,1,0000000000000000000,000110:COP0:32::TLBWR |
c906108c | 4429 | "tlbwr" |
c5d00cc7 CD |
4430 | *mipsI: |
4431 | *mipsII: | |
4432 | *mipsIII: | |
4433 | *mipsIV: | |
603a98e7 | 4434 | *mipsV: |
c906108c SS |
4435 | *vr4100: |
4436 | *vr5000: | |
4437 | ||
4438 | \f | |
4439 | :include:::m16.igen | |
4440 | :include:::tx.igen | |
4441 | :include:::vr.igen | |
4442 | \f |