Commit | Line | Data |
---|---|---|
f2b30012 AC |
1 | // <insn> ::= |
2 | // <insn-word> { "+" <insn-word> } | |
3 | // ":" <format-name> | |
4 | // ":" <filter-flags> | |
5 | // ":" <options> | |
6 | // ":" <name> | |
7 | // <nl> | |
8 | // { <insn-model> } | |
9 | // { <insn-mnemonic> } | |
10 | // <code-block> | |
11 | // | |
12 | ||
13 | ||
14 | // IGEN config - mips16 | |
a48e8c8d AC |
15 | // :option:16::insn-bit-size:16 |
16 | // :option:16::hi-bit-nr:15 | |
89d09738 AC |
17 | :option:16::insn-specifying-widths:true |
18 | :option:16::gen-delayed-branch:false | |
f2b30012 | 19 | |
90ad43b2 | 20 | // IGEN config - mips32/64.. |
a48e8c8d AC |
21 | // :option:32::insn-bit-size:32 |
22 | // :option:32::hi-bit-nr:31 | |
89d09738 AC |
23 | :option:32::insn-specifying-widths:true |
24 | :option:32::gen-delayed-branch:false | |
f2b30012 AC |
25 | |
26 | ||
49a6eed5 | 27 | // Generate separate simulators for each target |
89d09738 | 28 | // :option:::multi-sim:true |
49a6eed5 | 29 | |
f2b30012 AC |
30 | |
31 | // Models known by this simulator | |
89d09738 AC |
32 | :model:::mipsI:mipsI: |
33 | :model:::mipsII:mipsII: | |
34 | :model:::mipsIII:mipsIII: | |
35 | :model:::mipsIV:mipsIV: | |
36 | :model:::mips16:mips16: | |
f2b30012 | 37 | // start-sanitize-r5900 |
a48e8c8d | 38 | :model:::r5900:mips5900: |
f2b30012 | 39 | // end-sanitize-r5900 |
a48e8c8d | 40 | :model:::r3900:mips3900: |
f2b30012 | 41 | // start-sanitize-tx19 |
89d09738 | 42 | :model:::tx19:tx19: |
f2b30012 | 43 | // end-sanitize-tx19 |
90ad43b2 | 44 | // start-sanitize-vr5400 |
a48e8c8d | 45 | :model:::vr5400:mips5400: |
23850e92 | 46 | :model:::mdmx:mdmx: |
90ad43b2 | 47 | // end-sanitize-vr5400 |
a48e8c8d | 48 | :model:::vr5000:mips5000: |
f2b30012 AC |
49 | |
50 | ||
51 | ||
52 | // Pseudo instructions known by IGEN | |
89d09738 | 53 | :internal::::illegal: |
f2b30012 | 54 | { |
030843d7 | 55 | SignalException (ReservedInstruction, 0); |
f2b30012 AC |
56 | } |
57 | ||
58 | ||
030843d7 AC |
59 | // Pseudo instructions known by interp.c |
60 | // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK | |
61 | 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD | |
62 | "rsvd <OP>" | |
63 | { | |
64 | SignalException (ReservedInstruction, instruction_0); | |
65 | } | |
66 | ||
f2b30012 AC |
67 | |
68 | ||
69 | // | |
7ce8b917 | 70 | // Mips Architecture: |
f2b30012 AC |
71 | // |
72 | // CPU Instruction Set (mipsI - mipsIV) | |
73 | // | |
74 | ||
75 | ||
76 | 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD | |
77 | "add r<RD>, r<RS>, r<RT>" | |
23850e92 JL |
78 | *mipsI,mipsII,mipsIII,mipsIV: |
79 | *vr5000: | |
90ad43b2 AC |
80 | // start-sanitize-vr5400 |
81 | *vr5400: | |
82 | // end-sanitize-vr5400 | |
f2b30012 AC |
83 | // start-sanitize-r5900 |
84 | *r5900: | |
85 | // end-sanitize-r5900 | |
86 | *r3900: | |
87 | // start-sanitize-tx19 | |
88 | *tx19: | |
89 | // end-sanitize-tx19 | |
90 | { | |
055ee297 AC |
91 | ALU32_BEGIN (GPR[RS]); |
92 | ALU32_ADD (GPR[RT]); | |
93 | ALU32_END (GPR[RD]); | |
f2b30012 AC |
94 | } |
95 | ||
96 | ||
97 | 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI | |
98 | "addi r<RT>, r<RS>, IMMEDIATE" | |
23850e92 JL |
99 | *mipsI,mipsII,mipsIII,mipsIV: |
100 | *vr5000: | |
90ad43b2 AC |
101 | // start-sanitize-vr5400 |
102 | *vr5400: | |
103 | // end-sanitize-vr5400 | |
f2b30012 AC |
104 | // start-sanitize-r5900 |
105 | *r5900: | |
106 | // end-sanitize-r5900 | |
107 | *r3900: | |
108 | // start-sanitize-tx19 | |
109 | *tx19: | |
110 | // end-sanitize-tx19 | |
111 | { | |
055ee297 | 112 | ALU32_BEGIN (GPR[RS]); |
f2b30012 | 113 | ALU32_ADD (EXTEND16 (IMMEDIATE)); |
055ee297 | 114 | ALU32_END (GPR[RT]); |
f2b30012 AC |
115 | } |
116 | ||
117 | ||
118 | 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU | |
7ce8b917 | 119 | "add r<RT>, r<RS>, <IMMEDIATE>" |
23850e92 JL |
120 | *mipsI,mipsII,mipsIII,mipsIV: |
121 | *vr5000: | |
90ad43b2 AC |
122 | // start-sanitize-vr5400 |
123 | *vr5400: | |
124 | // end-sanitize-vr5400 | |
f2b30012 AC |
125 | // start-sanitize-r5900 |
126 | *r5900: | |
127 | // end-sanitize-r5900 | |
128 | *r3900: | |
129 | // start-sanitize-tx19 | |
130 | *tx19: | |
131 | // end-sanitize-tx19 | |
132 | { | |
055ee297 AC |
133 | signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE); |
134 | GPR[RT] = EXTEND32 (temp); | |
f2b30012 AC |
135 | } |
136 | ||
137 | ||
138 | 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU | |
23850e92 JL |
139 | *mipsI,mipsII,mipsIII,mipsIV: |
140 | *vr5000: | |
90ad43b2 AC |
141 | // start-sanitize-vr5400 |
142 | *vr5400: | |
143 | // end-sanitize-vr5400 | |
f2b30012 AC |
144 | // start-sanitize-r5900 |
145 | *r5900: | |
146 | // end-sanitize-r5900 | |
147 | *r3900: | |
148 | // start-sanitize-tx19 | |
149 | *tx19: | |
150 | // end-sanitize-tx19 | |
151 | { | |
055ee297 AC |
152 | signed32 temp = GPR[RS] + GPR[RT]; |
153 | GPR[RD] = EXTEND32 (temp); | |
f2b30012 AC |
154 | } |
155 | ||
156 | ||
157 | 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND | |
158 | "and r<RD>, r<RS>, r<RT>" | |
23850e92 JL |
159 | *mipsI,mipsII,mipsIII,mipsIV: |
160 | *vr5000: | |
90ad43b2 AC |
161 | // start-sanitize-vr5400 |
162 | *vr5400: | |
163 | // end-sanitize-vr5400 | |
f2b30012 AC |
164 | // start-sanitize-r5900 |
165 | *r5900: | |
166 | // end-sanitize-r5900 | |
167 | *r3900: | |
168 | // start-sanitize-tx19 | |
169 | *tx19: | |
170 | // end-sanitize-tx19 | |
171 | { | |
055ee297 | 172 | GPR[RD] = GPR[RS] & GPR[RT]; |
f2b30012 AC |
173 | } |
174 | ||
175 | ||
176 | 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI | |
23850e92 JL |
177 | "and r<RT>, r<RS>, <IMMEDIATE>" |
178 | *mipsI,mipsII,mipsIII,mipsIV: | |
179 | *vr5000: | |
90ad43b2 AC |
180 | // start-sanitize-vr5400 |
181 | *vr5400: | |
182 | // end-sanitize-vr5400 | |
f2b30012 AC |
183 | // start-sanitize-r5900 |
184 | *r5900: | |
185 | // end-sanitize-r5900 | |
186 | *r3900: | |
187 | // start-sanitize-tx19 | |
188 | *tx19: | |
189 | // end-sanitize-tx19 | |
190 | { | |
055ee297 | 191 | GPR[RT] = GPR[RS] & IMMEDIATE; |
f2b30012 AC |
192 | } |
193 | ||
194 | ||
195 | 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ | |
7ce8b917 | 196 | "beq r<RS>, r<RT>, <OFFSET>" |
23850e92 JL |
197 | *mipsI,mipsII,mipsIII,mipsIV: |
198 | *vr5000: | |
90ad43b2 AC |
199 | // start-sanitize-vr5400 |
200 | *vr5400: | |
201 | // end-sanitize-vr5400 | |
f2b30012 AC |
202 | // start-sanitize-r5900 |
203 | *r5900: | |
204 | // end-sanitize-r5900 | |
205 | *r3900: | |
206 | // start-sanitize-tx19 | |
207 | *tx19: | |
208 | // end-sanitize-tx19 | |
209 | { | |
055ee297 | 210 | address_word offset = EXTEND16 (OFFSET) << 2; |
030843d7 AC |
211 | if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) |
212 | DELAY_SLOT (NIA + offset); | |
f2b30012 AC |
213 | } |
214 | ||
215 | ||
216 | 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL | |
217 | "beql r<RS>, r<RT>, <OFFSET>" | |
218 | *mipsII: | |
219 | *mipsIII: | |
220 | *mipsIV: | |
23850e92 | 221 | *vr5000: |
90ad43b2 AC |
222 | // start-sanitize-vr5400 |
223 | *vr5400: | |
224 | // end-sanitize-vr5400 | |
f2b30012 AC |
225 | // start-sanitize-r5900 |
226 | *r5900: | |
227 | // end-sanitize-r5900 | |
228 | *r3900: | |
229 | // start-sanitize-tx19 | |
230 | *tx19: | |
231 | // end-sanitize-tx19 | |
232 | { | |
055ee297 | 233 | address_word offset = EXTEND16 (OFFSET) << 2; |
030843d7 AC |
234 | if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) |
235 | DELAY_SLOT (NIA + offset); | |
055ee297 | 236 | else |
49a76833 | 237 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
238 | } |
239 | ||
240 | ||
241 | 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ | |
242 | "bgez r<RS>, <OFFSET>" | |
23850e92 JL |
243 | *mipsI,mipsII,mipsIII,mipsIV: |
244 | *vr5000: | |
90ad43b2 AC |
245 | // start-sanitize-vr5400 |
246 | *vr5400: | |
247 | // end-sanitize-vr5400 | |
f2b30012 AC |
248 | // start-sanitize-r5900 |
249 | *r5900: | |
250 | // end-sanitize-r5900 | |
251 | *r3900: | |
252 | // start-sanitize-tx19 | |
253 | *tx19: | |
254 | // end-sanitize-tx19 | |
255 | { | |
055ee297 | 256 | address_word offset = EXTEND16 (OFFSET) << 2; |
030843d7 AC |
257 | if ((signed_word) GPR[RS] >= 0) |
258 | DELAY_SLOT (NIA + offset); | |
f2b30012 AC |
259 | } |
260 | ||
261 | ||
262 | 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL | |
263 | "bgezal r<RS>, <OFFSET>" | |
23850e92 JL |
264 | *mipsI,mipsII,mipsIII,mipsIV: |
265 | *vr5000: | |
90ad43b2 AC |
266 | // start-sanitize-vr5400 |
267 | *vr5400: | |
268 | // end-sanitize-vr5400 | |
f2b30012 AC |
269 | // start-sanitize-r5900 |
270 | *r5900: | |
271 | // end-sanitize-r5900 | |
272 | *r3900: | |
273 | // start-sanitize-tx19 | |
274 | *tx19: | |
275 | // end-sanitize-tx19 | |
276 | { | |
055ee297 AC |
277 | address_word offset = EXTEND16 (OFFSET) << 2; |
278 | RA = (CIA + 8); | |
030843d7 AC |
279 | if ((signed_word) GPR[RS] >= 0) |
280 | DELAY_SLOT (NIA + offset); | |
f2b30012 AC |
281 | } |
282 | ||
283 | ||
284 | 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL | |
285 | "bgezall r<RS>, <OFFSET>" | |
286 | *mipsII: | |
287 | *mipsIII: | |
288 | *mipsIV: | |
23850e92 | 289 | *vr5000: |
90ad43b2 AC |
290 | // start-sanitize-vr5400 |
291 | *vr5400: | |
292 | // end-sanitize-vr5400 | |
f2b30012 AC |
293 | // start-sanitize-r5900 |
294 | *r5900: | |
295 | // end-sanitize-r5900 | |
296 | *r3900: | |
297 | // start-sanitize-tx19 | |
298 | *tx19: | |
299 | // end-sanitize-tx19 | |
300 | { | |
055ee297 AC |
301 | address_word offset = EXTEND16 (OFFSET) << 2; |
302 | RA = (CIA + 8); | |
f2b30012 AC |
303 | /* NOTE: The branch occurs AFTER the next instruction has been |
304 | executed */ | |
030843d7 AC |
305 | if ((signed_word) GPR[RS] >= 0) |
306 | DELAY_SLOT (NIA + offset); | |
f2b30012 | 307 | else |
49a76833 | 308 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
309 | } |
310 | ||
311 | ||
312 | 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL | |
313 | "bgezl r<RS>, <OFFSET>" | |
314 | *mipsII: | |
315 | *mipsIII: | |
316 | *mipsIV: | |
23850e92 | 317 | *vr5000: |
90ad43b2 AC |
318 | // start-sanitize-vr5400 |
319 | *vr5400: | |
320 | // end-sanitize-vr5400 | |
f2b30012 AC |
321 | // start-sanitize-r5900 |
322 | *r5900: | |
323 | // end-sanitize-r5900 | |
324 | *r3900: | |
325 | // start-sanitize-tx19 | |
326 | *tx19: | |
327 | // end-sanitize-tx19 | |
328 | { | |
055ee297 | 329 | address_word offset = EXTEND16 (OFFSET) << 2; |
030843d7 AC |
330 | if ((signed_word) GPR[RS] >= 0) |
331 | DELAY_SLOT (NIA + offset); | |
f2b30012 | 332 | else |
49a76833 | 333 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
334 | } |
335 | ||
336 | ||
337 | 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ | |
338 | "bgtz r<RS>, <OFFSET>" | |
23850e92 JL |
339 | *mipsI,mipsII,mipsIII,mipsIV: |
340 | *vr5000: | |
90ad43b2 AC |
341 | // start-sanitize-vr5400 |
342 | *vr5400: | |
343 | // end-sanitize-vr5400 | |
f2b30012 AC |
344 | // start-sanitize-r5900 |
345 | *r5900: | |
346 | // end-sanitize-r5900 | |
347 | *r3900: | |
348 | // start-sanitize-tx19 | |
349 | *tx19: | |
350 | // end-sanitize-tx19 | |
351 | { | |
055ee297 | 352 | address_word offset = EXTEND16 (OFFSET) << 2; |
030843d7 AC |
353 | if ((signed_word) GPR[RS] > 0) |
354 | DELAY_SLOT (NIA + offset); | |
f2b30012 AC |
355 | } |
356 | ||
357 | ||
358 | 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL | |
359 | "bgtzl r<RS>, <OFFSET>" | |
360 | *mipsII: | |
361 | *mipsIII: | |
362 | *mipsIV: | |
23850e92 | 363 | *vr5000: |
90ad43b2 AC |
364 | // start-sanitize-vr5400 |
365 | *vr5400: | |
366 | // end-sanitize-vr5400 | |
f2b30012 AC |
367 | // start-sanitize-r5900 |
368 | *r5900: | |
369 | // end-sanitize-r5900 | |
370 | *r3900: | |
371 | // start-sanitize-tx19 | |
372 | *tx19: | |
373 | // end-sanitize-tx19 | |
374 | { | |
055ee297 | 375 | address_word offset = EXTEND16 (OFFSET) << 2; |
f2b30012 AC |
376 | /* NOTE: The branch occurs AFTER the next instruction has been |
377 | executed */ | |
030843d7 AC |
378 | if ((signed_word) GPR[RS] > 0) |
379 | DELAY_SLOT (NIA + offset); | |
f2b30012 | 380 | else |
49a76833 | 381 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
382 | } |
383 | ||
384 | ||
385 | 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ | |
386 | "blez r<RS>, <OFFSET>" | |
23850e92 JL |
387 | *mipsI,mipsII,mipsIII,mipsIV: |
388 | *vr5000: | |
90ad43b2 AC |
389 | // start-sanitize-vr5400 |
390 | *vr5400: | |
391 | // end-sanitize-vr5400 | |
f2b30012 AC |
392 | // start-sanitize-r5900 |
393 | *r5900: | |
394 | // end-sanitize-r5900 | |
395 | *r3900: | |
396 | // start-sanitize-tx19 | |
397 | *tx19: | |
398 | // end-sanitize-tx19 | |
399 | { | |
055ee297 | 400 | address_word offset = EXTEND16 (OFFSET) << 2; |
f2b30012 AC |
401 | /* NOTE: The branch occurs AFTER the next instruction has been |
402 | executed */ | |
030843d7 AC |
403 | if ((signed_word) GPR[RS] <= 0) |
404 | DELAY_SLOT (NIA + offset); | |
f2b30012 AC |
405 | } |
406 | ||
407 | ||
408 | 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL | |
409 | "bgezl r<RS>, <OFFSET>" | |
410 | *mipsII: | |
411 | *mipsIII: | |
412 | *mipsIV: | |
23850e92 | 413 | *vr5000: |
90ad43b2 AC |
414 | // start-sanitize-vr5400 |
415 | *vr5400: | |
416 | // end-sanitize-vr5400 | |
f2b30012 AC |
417 | // start-sanitize-r5900 |
418 | *r5900: | |
419 | // end-sanitize-r5900 | |
420 | *r3900: | |
421 | // start-sanitize-tx19 | |
422 | *tx19: | |
423 | // end-sanitize-tx19 | |
424 | { | |
055ee297 | 425 | address_word offset = EXTEND16 (OFFSET) << 2; |
030843d7 AC |
426 | if ((signed_word) GPR[RS] <= 0) |
427 | DELAY_SLOT (NIA + offset); | |
f2b30012 | 428 | else |
49a76833 | 429 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
430 | } |
431 | ||
432 | ||
433 | 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ | |
434 | "bltz r<RS>, <OFFSET>" | |
23850e92 JL |
435 | *mipsI,mipsII,mipsIII,mipsIV: |
436 | *vr5000: | |
90ad43b2 AC |
437 | // start-sanitize-vr5400 |
438 | *vr5400: | |
439 | // end-sanitize-vr5400 | |
f2b30012 AC |
440 | // start-sanitize-r5900 |
441 | *r5900: | |
442 | // end-sanitize-r5900 | |
443 | *r3900: | |
444 | // start-sanitize-tx19 | |
445 | *tx19: | |
446 | // end-sanitize-tx19 | |
447 | { | |
055ee297 | 448 | address_word offset = EXTEND16 (OFFSET) << 2; |
030843d7 AC |
449 | if ((signed_word) GPR[RS] < 0) |
450 | DELAY_SLOT (NIA + offset); | |
f2b30012 AC |
451 | } |
452 | ||
453 | ||
454 | 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL | |
455 | "bltzal r<RS>, <OFFSET>" | |
23850e92 JL |
456 | *mipsI,mipsII,mipsIII,mipsIV: |
457 | *vr5000: | |
90ad43b2 AC |
458 | // start-sanitize-vr5400 |
459 | *vr5400: | |
460 | // end-sanitize-vr5400 | |
f2b30012 AC |
461 | // start-sanitize-r5900 |
462 | *r5900: | |
463 | // end-sanitize-r5900 | |
464 | *r3900: | |
465 | // start-sanitize-tx19 | |
466 | *tx19: | |
467 | // end-sanitize-tx19 | |
468 | { | |
055ee297 AC |
469 | address_word offset = EXTEND16 (OFFSET) << 2; |
470 | RA = (CIA + 8); | |
f2b30012 AC |
471 | /* NOTE: The branch occurs AFTER the next instruction has been |
472 | executed */ | |
030843d7 AC |
473 | if ((signed_word) GPR[RS] < 0) |
474 | DELAY_SLOT (NIA + offset); | |
f2b30012 AC |
475 | } |
476 | ||
477 | ||
478 | 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL | |
479 | "bltzall r<RS>, <OFFSET>" | |
480 | *mipsII: | |
481 | *mipsIII: | |
482 | *mipsIV: | |
23850e92 | 483 | *vr5000: |
90ad43b2 AC |
484 | // start-sanitize-vr5400 |
485 | *vr5400: | |
486 | // end-sanitize-vr5400 | |
f2b30012 AC |
487 | // start-sanitize-r5900 |
488 | *r5900: | |
489 | // end-sanitize-r5900 | |
490 | *r3900: | |
491 | // start-sanitize-tx19 | |
492 | *tx19: | |
493 | // end-sanitize-tx19 | |
494 | { | |
055ee297 AC |
495 | address_word offset = EXTEND16 (OFFSET) << 2; |
496 | RA = (CIA + 8); | |
030843d7 AC |
497 | if ((signed_word) GPR[RS] < 0) |
498 | DELAY_SLOT (NIA + offset); | |
f2b30012 | 499 | else |
49a76833 | 500 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
501 | } |
502 | ||
503 | ||
504 | 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL | |
505 | "bltzl r<RS>, <OFFSET>" | |
506 | *mipsII: | |
507 | *mipsIII: | |
508 | *mipsIV: | |
23850e92 | 509 | *vr5000: |
90ad43b2 AC |
510 | // start-sanitize-vr5400 |
511 | *vr5400: | |
512 | // end-sanitize-vr5400 | |
f2b30012 AC |
513 | // start-sanitize-r5900 |
514 | *r5900: | |
515 | // end-sanitize-r5900 | |
516 | *r3900: | |
517 | // start-sanitize-tx19 | |
518 | *tx19: | |
519 | // end-sanitize-tx19 | |
520 | { | |
055ee297 | 521 | address_word offset = EXTEND16 (OFFSET) << 2; |
f2b30012 AC |
522 | /* NOTE: The branch occurs AFTER the next instruction has been |
523 | executed */ | |
030843d7 AC |
524 | if ((signed_word) GPR[RS] < 0) |
525 | DELAY_SLOT (NIA + offset); | |
f2b30012 | 526 | else |
49a76833 | 527 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
528 | } |
529 | ||
530 | ||
531 | 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE | |
532 | "bne r<RS>, r<RT>, <OFFSET>" | |
23850e92 JL |
533 | *mipsI,mipsII,mipsIII,mipsIV: |
534 | *vr5000: | |
90ad43b2 AC |
535 | // start-sanitize-vr5400 |
536 | *vr5400: | |
537 | // end-sanitize-vr5400 | |
f2b30012 AC |
538 | // start-sanitize-r5900 |
539 | *r5900: | |
540 | // end-sanitize-r5900 | |
541 | *r3900: | |
542 | // start-sanitize-tx19 | |
543 | *tx19: | |
544 | // end-sanitize-tx19 | |
545 | { | |
055ee297 | 546 | address_word offset = EXTEND16 (OFFSET) << 2; |
030843d7 AC |
547 | if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) |
548 | DELAY_SLOT (NIA + offset); | |
f2b30012 AC |
549 | } |
550 | ||
551 | ||
552 | 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL | |
553 | "bnel r<RS>, r<RT>, <OFFSET>" | |
554 | *mipsII: | |
555 | *mipsIII: | |
556 | *mipsIV: | |
23850e92 | 557 | *vr5000: |
90ad43b2 AC |
558 | // start-sanitize-vr5400 |
559 | *vr5400: | |
560 | // end-sanitize-vr5400 | |
f2b30012 AC |
561 | // start-sanitize-r5900 |
562 | *r5900: | |
563 | // end-sanitize-r5900 | |
564 | *r3900: | |
565 | // start-sanitize-tx19 | |
566 | *tx19: | |
567 | // end-sanitize-tx19 | |
568 | { | |
085c1cb9 | 569 | address_word offset = EXTEND16 (OFFSET) << 2; |
030843d7 AC |
570 | if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) |
571 | DELAY_SLOT (NIA + offset); | |
f2b30012 | 572 | else |
49a76833 | 573 | NULLIFY_NEXT_INSTRUCTION (); |
f2b30012 AC |
574 | } |
575 | ||
576 | ||
49a6eed5 | 577 | 000000,20.CODE,001101:SPECIAL:32::BREAK |
f2b30012 | 578 | "break" |
23850e92 JL |
579 | *mipsI,mipsII,mipsIII,mipsIV: |
580 | *vr5000: | |
90ad43b2 AC |
581 | // start-sanitize-vr5400 |
582 | *vr5400: | |
583 | // end-sanitize-vr5400 | |
f2b30012 AC |
584 | // start-sanitize-r5900 |
585 | *r5900: | |
586 | // end-sanitize-r5900 | |
587 | *r3900: | |
588 | // start-sanitize-tx19 | |
589 | *tx19: | |
590 | // end-sanitize-tx19 | |
591 | { | |
055ee297 | 592 | SignalException(BreakPoint, instruction_0); |
f2b30012 AC |
593 | } |
594 | ||
595 | ||
49a6eed5 | 596 | 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz |
f2b30012 | 597 | "cop<ZZ> <COP_FUN>" |
23850e92 | 598 | *mipsI,mipsII,mipsIII,mipsIV: |
f2b30012 AC |
599 | // start-sanitize-r5900 |
600 | *r5900: | |
601 | // end-sanitize-r5900 | |
602 | *r3900: | |
603 | // start-sanitize-tx19 | |
604 | *tx19: | |
605 | // end-sanitize-tx19 | |
606 | { | |
085c1cb9 | 607 | DecodeCoproc (instruction_0); |
f2b30012 AC |
608 | } |
609 | ||
610 | ||
611 | 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD | |
612 | "dadd r<RD>, r<RS>, r<RT>" | |
613 | *mipsIII: | |
614 | *mipsIV: | |
23850e92 | 615 | *vr5000: |
90ad43b2 AC |
616 | // start-sanitize-vr5400 |
617 | *vr5400: | |
618 | // end-sanitize-vr5400 | |
f2b30012 AC |
619 | // start-sanitize-r5900 |
620 | *r5900: | |
621 | // end-sanitize-r5900 | |
622 | *r3900: | |
623 | // start-sanitize-tx19 | |
624 | *tx19: | |
625 | // end-sanitize-tx19 | |
626 | { | |
055ee297 AC |
627 | ALU64_BEGIN (GPR[RS]); |
628 | ALU64_ADD (GPR[RT]); | |
629 | ALU64_END (GPR[RT]); | |
f2b30012 AC |
630 | } |
631 | ||
632 | ||
633 | 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI | |
634 | "daddi r<RT>, r<RS>, <IMMEDIATE>" | |
635 | *mipsIII: | |
636 | *mipsIV: | |
23850e92 | 637 | *vr5000: |
90ad43b2 AC |
638 | // start-sanitize-vr5400 |
639 | *vr5400: | |
640 | // end-sanitize-vr5400 | |
f2b30012 AC |
641 | // start-sanitize-r5900 |
642 | *r5900: | |
643 | // end-sanitize-r5900 | |
644 | *r3900: | |
645 | // start-sanitize-tx19 | |
646 | *tx19: | |
647 | // end-sanitize-tx19 | |
648 | { | |
055ee297 | 649 | ALU64_BEGIN (GPR[RS]); |
f2b30012 | 650 | ALU64_ADD (EXTEND16 (IMMEDIATE)); |
055ee297 | 651 | ALU64_END (GPR[RT]); |
f2b30012 AC |
652 | } |
653 | ||
654 | ||
655 | 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU | |
656 | "daddu r<RT>, r<RS>, <IMMEDIATE>" | |
657 | *mipsIII: | |
658 | *mipsIV: | |
23850e92 | 659 | *vr5000: |
90ad43b2 AC |
660 | // start-sanitize-vr5400 |
661 | *vr5400: | |
662 | // end-sanitize-vr5400 | |
f2b30012 AC |
663 | // start-sanitize-r5900 |
664 | *r5900: | |
665 | // end-sanitize-r5900 | |
666 | *r3900: | |
667 | // start-sanitize-tx19 | |
668 | *tx19: | |
669 | // end-sanitize-tx19 | |
670 | { | |
085c1cb9 | 671 | GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE); |
f2b30012 AC |
672 | } |
673 | ||
674 | ||
675 | 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU | |
676 | "daddu r<RD>, r<RS>, r<RT>" | |
677 | *mipsIII: | |
678 | *mipsIV: | |
23850e92 | 679 | *vr5000: |
90ad43b2 AC |
680 | // start-sanitize-vr5400 |
681 | *vr5400: | |
682 | // end-sanitize-vr5400 | |
f2b30012 AC |
683 | // start-sanitize-r5900 |
684 | *r5900: | |
685 | // end-sanitize-r5900 | |
686 | *r3900: | |
687 | // start-sanitize-tx19 | |
688 | *tx19: | |
689 | // end-sanitize-tx19 | |
690 | { | |
055ee297 | 691 | GPR[RD] = GPR[RS] + GPR[RT]; |
f2b30012 AC |
692 | } |
693 | ||
694 | ||
695 | 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV | |
696 | "ddiv r<RS>, r<RT>" | |
697 | *mipsIII: | |
698 | *mipsIV: | |
23850e92 | 699 | *vr5000: |
90ad43b2 AC |
700 | // start-sanitize-vr5400 |
701 | *vr5400: | |
702 | // end-sanitize-vr5400 | |
f2b30012 AC |
703 | // start-sanitize-r5900 |
704 | *r5900: | |
705 | // end-sanitize-r5900 | |
706 | *r3900: | |
707 | // start-sanitize-tx19 | |
708 | *tx19: | |
709 | // end-sanitize-tx19 | |
710 | { | |
711 | CHECKHILO ("Division"); | |
712 | { | |
055ee297 AC |
713 | signed64 n = GPR[RS]; |
714 | signed64 d = GPR[RT]; | |
f2b30012 AC |
715 | if (d == 0) |
716 | { | |
717 | LO = SIGNED64 (0x8000000000000000); | |
718 | HI = 0; | |
719 | } | |
720 | else if (d == -1 && n == SIGNED64 (0x8000000000000000)) | |
721 | { | |
722 | LO = SIGNED64 (0x8000000000000000); | |
723 | HI = 0; | |
724 | } | |
725 | else | |
726 | { | |
727 | LO = (n / d); | |
728 | HI = (n % d); | |
729 | } | |
730 | } | |
731 | } | |
732 | ||
733 | ||
734 | ||
735 | 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU | |
736 | "ddivu r<RS>, r<RT>" | |
737 | *mipsIII: | |
738 | *mipsIV: | |
739 | *r3900: | |
23850e92 | 740 | *vr5000: |
90ad43b2 AC |
741 | // start-sanitize-vr5400 |
742 | *vr5400: | |
743 | // end-sanitize-vr5400 | |
f2b30012 AC |
744 | // start-sanitize-tx19 |
745 | *tx19: | |
746 | // end-sanitize-tx19 | |
747 | { | |
748 | CHECKHILO ("Division"); | |
749 | { | |
055ee297 AC |
750 | unsigned64 n = GPR[RS]; |
751 | unsigned64 d = GPR[RT]; | |
f2b30012 AC |
752 | if (d == 0) |
753 | { | |
754 | LO = SIGNED64 (0x8000000000000000); | |
755 | HI = 0; | |
756 | } | |
757 | else | |
758 | { | |
759 | LO = (n / d); | |
760 | HI = (n % d); | |
761 | } | |
762 | } | |
763 | } | |
764 | ||
765 | ||
766 | 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV | |
767 | "div r<RS>, r<RT>" | |
23850e92 JL |
768 | *mipsI,mipsII,mipsIII,mipsIV: |
769 | *vr5000: | |
90ad43b2 AC |
770 | // start-sanitize-vr5400 |
771 | *vr5400: | |
772 | // end-sanitize-vr5400 | |
f2b30012 AC |
773 | // start-sanitize-r5900 |
774 | *r5900: | |
775 | // end-sanitize-r5900 | |
776 | *r3900: | |
777 | // start-sanitize-tx19 | |
778 | *tx19: | |
779 | // end-sanitize-tx19 | |
780 | { | |
781 | CHECKHILO("Division"); | |
782 | { | |
055ee297 AC |
783 | signed32 n = GPR[RS]; |
784 | signed32 d = GPR[RT]; | |
f2b30012 AC |
785 | if (d == 0) |
786 | { | |
787 | LO = EXTEND32 (0x80000000); | |
788 | HI = EXTEND32 (0); | |
789 | } | |
055ee297 | 790 | else if (d == -1 && d == 0x80000000) |
f2b30012 AC |
791 | { |
792 | LO = EXTEND32 (0x80000000); | |
793 | HI = EXTEND32 (0); | |
794 | } | |
795 | else | |
796 | { | |
797 | LO = EXTEND32 (n / d); | |
798 | HI = EXTEND32 (n % d); | |
799 | } | |
800 | } | |
801 | } | |
802 | ||
803 | ||
804 | 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU | |
805 | "divu r<RS>, r<RT>" | |
23850e92 JL |
806 | *mipsI,mipsII,mipsIII,mipsIV: |
807 | *vr5000: | |
90ad43b2 AC |
808 | // start-sanitize-vr5400 |
809 | *vr5400: | |
810 | // end-sanitize-vr5400 | |
f2b30012 AC |
811 | // start-sanitize-r5900 |
812 | *r5900: | |
813 | // end-sanitize-r5900 | |
814 | *r3900: | |
815 | // start-sanitize-tx19 | |
816 | *tx19: | |
817 | // end-sanitize-tx19 | |
818 | { | |
819 | CHECKHILO ("Division"); | |
820 | { | |
055ee297 AC |
821 | unsigned32 n = GPR[RS]; |
822 | unsigned32 d = GPR[RT]; | |
f2b30012 AC |
823 | if (d == 0) |
824 | { | |
825 | LO = EXTEND32 (0x80000000); | |
826 | HI = EXTEND32 (0); | |
827 | } | |
828 | else | |
829 | { | |
830 | LO = EXTEND32 (n / d); | |
831 | HI = EXTEND32 (n % d); | |
832 | } | |
833 | } | |
834 | } | |
835 | ||
836 | ||
23850e92 JL |
837 | :function:::void:do_dmult:int rs, int rt, int rd, int signed_p |
838 | { | |
839 | unsigned64 lo; | |
840 | unsigned64 hi; | |
841 | unsigned64 m00; | |
842 | unsigned64 m01; | |
843 | unsigned64 m10; | |
844 | unsigned64 m11; | |
845 | unsigned64 mid; | |
846 | int sign; | |
847 | unsigned64 op1 = GPR[rs]; | |
848 | unsigned64 op2 = GPR[rt]; | |
849 | CHECKHILO ("Multiplication"); | |
850 | /* make signed multiply unsigned */ | |
851 | sign = 0; | |
852 | if (signed_p) | |
853 | { | |
854 | if (op1 < 0) | |
855 | { | |
856 | op1 = - op1; | |
857 | ++sign; | |
858 | } | |
859 | if (op2 < 0) | |
860 | { | |
861 | op2 = - op2; | |
862 | ++sign; | |
863 | } | |
864 | } | |
865 | /* multuply out the 4 sub products */ | |
866 | m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2)); | |
867 | m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2)); | |
868 | m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2)); | |
869 | m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2)); | |
870 | /* add the products */ | |
871 | mid = ((unsigned64) VH4_8 (m00) | |
872 | + (unsigned64) VL4_8 (m10) | |
873 | + (unsigned64) VL4_8 (m01)); | |
874 | lo = U8_4 (mid, m00); | |
875 | hi = (m11 | |
876 | + (unsigned64) VH4_8 (mid) | |
877 | + (unsigned64) VH4_8 (m01) | |
878 | + (unsigned64) VH4_8 (m10)); | |
879 | /* fix the sign */ | |
880 | if (sign & 1) | |
881 | { | |
882 | lo = -lo; | |
883 | if (lo == 0) | |
884 | hi = -hi; | |
885 | else | |
886 | hi = -hi - 1; | |
887 | } | |
888 | /* save the result HI/LO (and a gpr) */ | |
889 | LO = lo; | |
890 | HI = hi; | |
891 | if (rd != 0) | |
892 | GPR[rd] = lo; | |
893 | } | |
894 | ||
895 | ||
f2b30012 AC |
896 | 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT |
897 | "dmult r<RS>, r<RT>" | |
23850e92 | 898 | *mipsIII,mipsIV: |
f2b30012 AC |
899 | *r3900: |
900 | // start-sanitize-tx19 | |
901 | *tx19: | |
902 | // end-sanitize-tx19 | |
903 | { | |
23850e92 | 904 | do_dmult (SD_, RS, RT, 0, 1); |
f2b30012 AC |
905 | } |
906 | ||
23850e92 JL |
907 | 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT |
908 | "dmult r<RS>, r<RT>":RD == 0 | |
909 | "dmult r<RD>, r<RS>, r<RT>" | |
910 | *vr5000: | |
90ad43b2 AC |
911 | // start-sanitize-vr5400 |
912 | *vr5400: | |
913 | // end-sanitize-vr5400 | |
23850e92 JL |
914 | { |
915 | do_dmult (SD_, RS, RT, RD, 1); | |
916 | } | |
917 | ||
918 | ||
919 | ||
920 | 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU | |
921 | "dmultu r<RS>, r<RT>" | |
922 | *mipsIII,mipsIV: | |
f2b30012 AC |
923 | *r3900: |
924 | // start-sanitize-tx19 | |
925 | *tx19: | |
926 | // end-sanitize-tx19 | |
927 | { | |
23850e92 JL |
928 | do_dmult (SD_, RS, RT, 0, 0); |
929 | } | |
930 | ||
931 | 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU | |
932 | "dmultu r<RD>, r<RS>, r<RT>":RD == 0 | |
933 | "dmultu r<RS>, r<RT>" | |
934 | *vr5000: | |
935 | // start-sanitize-vr5400 | |
936 | *vr5400: | |
937 | // end-sanitize-vr5400 | |
938 | { | |
939 | do_dmult (SD_, RS, RT, RD, 0); | |
f2b30012 AC |
940 | } |
941 | ||
942 | ||
23850e92 | 943 | |
055ee297 | 944 | 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL |
01b9cd49 | 945 | "dsll r<RD>, r<RT>, <SHIFT>" |
f2b30012 AC |
946 | *mipsIII: |
947 | *mipsIV: | |
23850e92 | 948 | *vr5000: |
90ad43b2 AC |
949 | // start-sanitize-vr5400 |
950 | *vr5400: | |
951 | // end-sanitize-vr5400 | |
f2b30012 AC |
952 | // start-sanitize-r5900 |
953 | *r5900: | |
954 | // end-sanitize-r5900 | |
955 | *r3900: | |
956 | // start-sanitize-tx19 | |
957 | *tx19: | |
958 | // end-sanitize-tx19 | |
959 | { | |
01b9cd49 | 960 | int s = SHIFT; |
055ee297 | 961 | GPR[RD] = GPR[RT] << s; |
f2b30012 AC |
962 | } |
963 | ||
964 | ||
055ee297 | 965 | 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32 |
01b9cd49 | 966 | "dsll32 r<RD>, r<RT>, <SHIFT>" |
f2b30012 AC |
967 | *mipsIII: |
968 | *mipsIV: | |
23850e92 | 969 | *vr5000: |
90ad43b2 AC |
970 | // start-sanitize-vr5400 |
971 | *vr5400: | |
972 | // end-sanitize-vr5400 | |
f2b30012 AC |
973 | // start-sanitize-r5900 |
974 | *r5900: | |
975 | // end-sanitize-r5900 | |
976 | *r3900: | |
977 | // start-sanitize-tx19 | |
978 | *tx19: | |
979 | // end-sanitize-tx19 | |
980 | { | |
01b9cd49 | 981 | int s = 32 + SHIFT; |
055ee297 | 982 | GPR[RD] = GPR[RT] << s; |
f2b30012 AC |
983 | } |
984 | ||
985 | ||
986 | 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV | |
987 | "dsllv r<RD>, r<RT>, r<RS>" | |
988 | *mipsIII: | |
989 | *mipsIV: | |
23850e92 | 990 | *vr5000: |
90ad43b2 AC |
991 | // start-sanitize-vr5400 |
992 | *vr5400: | |
993 | // end-sanitize-vr5400 | |
f2b30012 AC |
994 | // start-sanitize-r5900 |
995 | *r5900: | |
996 | // end-sanitize-r5900 | |
997 | *r3900: | |
998 | // start-sanitize-tx19 | |
999 | *tx19: | |
1000 | // end-sanitize-tx19 | |
1001 | { | |
055ee297 AC |
1002 | int s = MASKED64 (GPR[RS], 5, 0); |
1003 | GPR[RD] = GPR[RT] << s; | |
f2b30012 AC |
1004 | } |
1005 | ||
1006 | ||
055ee297 | 1007 | 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA |
01b9cd49 | 1008 | "dsra r<RD>, r<RT>, <SHIFT>" |
f2b30012 AC |
1009 | *mipsIII: |
1010 | *mipsIV: | |
23850e92 | 1011 | *vr5000: |
90ad43b2 AC |
1012 | // start-sanitize-vr5400 |
1013 | *vr5400: | |
1014 | // end-sanitize-vr5400 | |
f2b30012 AC |
1015 | // start-sanitize-r5900 |
1016 | *r5900: | |
1017 | // end-sanitize-r5900 | |
1018 | *r3900: | |
1019 | // start-sanitize-tx19 | |
1020 | *tx19: | |
1021 | // end-sanitize-tx19 | |
1022 | { | |
01b9cd49 | 1023 | int s = SHIFT; |
055ee297 | 1024 | GPR[RD] = ((signed64) GPR[RT]) >> s; |
f2b30012 AC |
1025 | } |
1026 | ||
1027 | ||
055ee297 | 1028 | 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32 |
01b9cd49 | 1029 | "dsra32 r<RT>, r<RD>, <SHIFT>" |
f2b30012 AC |
1030 | *mipsIII: |
1031 | *mipsIV: | |
23850e92 | 1032 | *vr5000: |
90ad43b2 AC |
1033 | // start-sanitize-vr5400 |
1034 | *vr5400: | |
1035 | // end-sanitize-vr5400 | |
f2b30012 AC |
1036 | // start-sanitize-r5900 |
1037 | *r5900: | |
1038 | // end-sanitize-r5900 | |
1039 | *r3900: | |
1040 | // start-sanitize-tx19 | |
1041 | *tx19: | |
1042 | // end-sanitize-tx19 | |
1043 | { | |
01b9cd49 | 1044 | int s = 32 + SHIFT; |
055ee297 | 1045 | GPR[RD] = ((signed64) GPR[RT]) >> s; |
f2b30012 AC |
1046 | } |
1047 | ||
1048 | ||
1049 | 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV | |
1050 | "dsra32 r<RT>, r<RD>, r<RS>" | |
1051 | *mipsIII: | |
1052 | *mipsIV: | |
23850e92 | 1053 | *vr5000: |
90ad43b2 AC |
1054 | // start-sanitize-vr5400 |
1055 | *vr5400: | |
1056 | // end-sanitize-vr5400 | |
f2b30012 AC |
1057 | // start-sanitize-r5900 |
1058 | *r5900: | |
1059 | // end-sanitize-r5900 | |
1060 | *r3900: | |
1061 | // start-sanitize-tx19 | |
1062 | *tx19: | |
1063 | // end-sanitize-tx19 | |
1064 | { | |
055ee297 AC |
1065 | int s = MASKED64 (GPR[RS], 5, 0); |
1066 | GPR[RD] = ((signed64) GPR[RT]) >> s; | |
f2b30012 AC |
1067 | } |
1068 | ||
1069 | ||
055ee297 | 1070 | 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL |
01b9cd49 | 1071 | "dsrav r<RD>, r<RT>, <SHIFT>" |
f2b30012 AC |
1072 | *mipsIII: |
1073 | *mipsIV: | |
23850e92 | 1074 | *vr5000: |
90ad43b2 AC |
1075 | // start-sanitize-vr5400 |
1076 | *vr5400: | |
1077 | // end-sanitize-vr5400 | |
f2b30012 AC |
1078 | // start-sanitize-r5900 |
1079 | *r5900: | |
1080 | // end-sanitize-r5900 | |
1081 | *r3900: | |
1082 | // start-sanitize-tx19 | |
1083 | *tx19: | |
1084 | // end-sanitize-tx19 | |
1085 | { | |
01b9cd49 | 1086 | int s = SHIFT; |
055ee297 | 1087 | GPR[RD] = (unsigned64) GPR[RT] >> s; |
f2b30012 AC |
1088 | } |
1089 | ||
1090 | ||
055ee297 | 1091 | 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32 |
01b9cd49 | 1092 | "dsrl32 r<RD>, r<RT>, <SHIFT>" |
f2b30012 AC |
1093 | *mipsIII: |
1094 | *mipsIV: | |
23850e92 | 1095 | *vr5000: |
90ad43b2 AC |
1096 | // start-sanitize-vr5400 |
1097 | *vr5400: | |
1098 | // end-sanitize-vr5400 | |
f2b30012 AC |
1099 | // start-sanitize-r5900 |
1100 | *r5900: | |
1101 | // end-sanitize-r5900 | |
1102 | *r3900: | |
1103 | // start-sanitize-tx19 | |
1104 | *tx19: | |
1105 | // end-sanitize-tx19 | |
1106 | { | |
01b9cd49 | 1107 | int s = 32 + SHIFT; |
055ee297 | 1108 | GPR[RD] = (unsigned64) GPR[RT] >> s; |
f2b30012 AC |
1109 | } |
1110 | ||
1111 | ||
1112 | 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV | |
1113 | "dsrl32 r<RD>, r<RT>, r<RS>" | |
1114 | *mipsIII: | |
1115 | *mipsIV: | |
23850e92 | 1116 | *vr5000: |
90ad43b2 AC |
1117 | // start-sanitize-vr5400 |
1118 | *vr5400: | |
1119 | // end-sanitize-vr5400 | |
f2b30012 AC |
1120 | // start-sanitize-r5900 |
1121 | *r5900: | |
1122 | // end-sanitize-r5900 | |
1123 | *r3900: | |
1124 | // start-sanitize-tx19 | |
1125 | *tx19: | |
1126 | // end-sanitize-tx19 | |
1127 | { | |
055ee297 AC |
1128 | int s = MASKED64 (GPR[RS], 5, 0); |
1129 | GPR[RD] = (unsigned64) GPR[RT] >> s; | |
f2b30012 AC |
1130 | } |
1131 | ||
1132 | ||
1133 | 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB | |
1134 | "dsub r<RD>, r<RS>, r<RT>" | |
1135 | *mipsIII: | |
1136 | *mipsIV: | |
23850e92 | 1137 | *vr5000: |
90ad43b2 AC |
1138 | // start-sanitize-vr5400 |
1139 | *vr5400: | |
1140 | // end-sanitize-vr5400 | |
f2b30012 AC |
1141 | // start-sanitize-r5900 |
1142 | *r5900: | |
1143 | // end-sanitize-r5900 | |
1144 | *r3900: | |
1145 | // start-sanitize-tx19 | |
1146 | *tx19: | |
1147 | // end-sanitize-tx19 | |
1148 | { | |
055ee297 AC |
1149 | ALU64_BEGIN (GPR[RS]); |
1150 | ALU64_SUB (GPR[RT]); | |
1151 | ALU64_END (GPR[RD]); | |
f2b30012 AC |
1152 | } |
1153 | ||
1154 | ||
1155 | 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU | |
1156 | "dsubu r<RD>, r<RS>, r<RT>" | |
1157 | *mipsIII: | |
1158 | *mipsIV: | |
23850e92 | 1159 | *vr5000: |
90ad43b2 AC |
1160 | // start-sanitize-vr5400 |
1161 | *vr5400: | |
1162 | // end-sanitize-vr5400 | |
f2b30012 AC |
1163 | // start-sanitize-r5900 |
1164 | *r5900: | |
1165 | // end-sanitize-r5900 | |
1166 | *r3900: | |
1167 | // start-sanitize-tx19 | |
1168 | *tx19: | |
1169 | // end-sanitize-tx19 | |
1170 | { | |
055ee297 | 1171 | GPR[RD] = GPR[RS] - GPR[RT]; |
f2b30012 AC |
1172 | } |
1173 | ||
1174 | ||
1175 | 000010,26.INSTR_INDEX:NORMAL:32::J | |
1176 | "j <INSTR_INDEX>" | |
23850e92 JL |
1177 | *mipsI,mipsII,mipsIII,mipsIV: |
1178 | *vr5000: | |
90ad43b2 AC |
1179 | // start-sanitize-vr5400 |
1180 | *vr5400: | |
1181 | // end-sanitize-vr5400 | |
f2b30012 AC |
1182 | // start-sanitize-r5900 |
1183 | *r5900: | |
1184 | // end-sanitize-r5900 | |
1185 | *r3900: | |
1186 | // start-sanitize-tx19 | |
1187 | *tx19: | |
1188 | // end-sanitize-tx19 | |
1189 | { | |
49a76833 | 1190 | /* NOTE: The region used is that of the delay slot NIA and NOT the |
f2b30012 | 1191 | current instruction */ |
49a76833 AC |
1192 | address_word region = (NIA & MASK (63, 28)); |
1193 | DELAY_SLOT (region | (INSTR_INDEX << 2)); | |
f2b30012 AC |
1194 | } |
1195 | ||
1196 | ||
1197 | 000011,26.INSTR_INDEX:NORMAL:32::JAL | |
1198 | "jal <INSTR_INDEX>" | |
23850e92 JL |
1199 | *mipsI,mipsII,mipsIII,mipsIV: |
1200 | *vr5000: | |
90ad43b2 AC |
1201 | // start-sanitize-vr5400 |
1202 | *vr5400: | |
1203 | // end-sanitize-vr5400 | |
f2b30012 AC |
1204 | // start-sanitize-r5900 |
1205 | *r5900: | |
1206 | // end-sanitize-r5900 | |
1207 | *r3900: | |
1208 | // start-sanitize-tx19 | |
1209 | *tx19: | |
1210 | // end-sanitize-tx19 | |
1211 | { | |
1212 | /* NOTE: The region used is that of the delay slot and NOT the | |
1213 | current instruction */ | |
49a76833 | 1214 | address_word region = (NIA & MASK (63, 28)); |
055ee297 | 1215 | GPR[31] = CIA + 8; |
49a76833 | 1216 | DELAY_SLOT (region | (INSTR_INDEX << 2)); |
f2b30012 AC |
1217 | } |
1218 | ||
1219 | ||
1220 | 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR | |
1221 | "jalr r<RS>":RD == 31 | |
1222 | "jalr r<RD>, r<RS>" | |
23850e92 JL |
1223 | *mipsI,mipsII,mipsIII,mipsIV: |
1224 | *vr5000: | |
90ad43b2 AC |
1225 | // start-sanitize-vr5400 |
1226 | *vr5400: | |
1227 | // end-sanitize-vr5400 | |
f2b30012 AC |
1228 | // start-sanitize-r5900 |
1229 | *r5900: | |
1230 | // end-sanitize-r5900 | |
1231 | *r3900: | |
1232 | // start-sanitize-tx19 | |
1233 | *tx19: | |
1234 | // end-sanitize-tx19 | |
1235 | { | |
055ee297 AC |
1236 | address_word temp = GPR[RS]; |
1237 | GPR[RD] = CIA + 8; | |
49a76833 | 1238 | DELAY_SLOT (temp); |
f2b30012 AC |
1239 | } |
1240 | ||
1241 | ||
1242 | 000000,5.RS,000000000000000001000:SPECIAL:32::JR | |
1243 | "jr r<RS>" | |
23850e92 JL |
1244 | *mipsI,mipsII,mipsIII,mipsIV: |
1245 | *vr5000: | |
90ad43b2 AC |
1246 | // start-sanitize-vr5400 |
1247 | *vr5400: | |
1248 | // end-sanitize-vr5400 | |
f2b30012 AC |
1249 | // start-sanitize-r5900 |
1250 | *r5900: | |
1251 | // end-sanitize-r5900 | |
1252 | *r3900: | |
1253 | // start-sanitize-tx19 | |
1254 | *tx19: | |
1255 | // end-sanitize-tx19 | |
1256 | { | |
49a76833 | 1257 | DELAY_SLOT (GPR[RS]); |
f2b30012 AC |
1258 | } |
1259 | ||
1260 | ||
a48e8c8d AC |
1261 | :function:::void:do_load_byte:address_word gpr_base, int rt, signed16 offset |
1262 | { | |
1263 | address_word vaddr = offset + gpr_base; | |
1264 | address_word paddr; | |
1265 | int uncached; | |
1266 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1267 | { | |
1268 | unsigned64 memval = 0; | |
1269 | address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); | |
1270 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
1271 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
1272 | unsigned int byte; | |
1273 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
1274 | LoadMemory (&memval, NULL, uncached, AccessLength_BYTE, paddr, vaddr, isDATA, isREAL); | |
1275 | byte = ((vaddr & mask) ^ bigend); | |
1276 | GPR[rt] = EXTEND8 ((memval >> (8 * byte))); | |
1277 | } | |
1278 | } | |
1279 | ||
f2b30012 AC |
1280 | 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB |
1281 | "lb r<RT>, <OFFSET>(r<BASE>)" | |
23850e92 JL |
1282 | *mipsI,mipsII,mipsIII,mipsIV: |
1283 | *vr5000: | |
90ad43b2 AC |
1284 | // start-sanitize-vr5400 |
1285 | *vr5400: | |
1286 | // end-sanitize-vr5400 | |
f2b30012 AC |
1287 | // start-sanitize-r5900 |
1288 | *r5900: | |
1289 | // end-sanitize-r5900 | |
1290 | *r3900: | |
1291 | // start-sanitize-tx19 | |
1292 | *tx19: | |
1293 | // end-sanitize-tx19 | |
1294 | { | |
a48e8c8d AC |
1295 | do_load_byte (SD_, GPR[BASE], RT, OFFSET); |
1296 | #if 0 | |
f2b30012 | 1297 | unsigned32 instruction = instruction_0; |
055ee297 AC |
1298 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1299 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1300 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1301 | { |
49a76833 AC |
1302 | address_word vaddr = ((uword64)op1 + offset); |
1303 | address_word paddr; | |
f2b30012 AC |
1304 | int uncached; |
1305 | { | |
1306 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1307 | { | |
1308 | uword64 memval = 0; | |
1309 | uword64 memval1 = 0; | |
1310 | uword64 mask = 0x7; | |
1311 | unsigned int shift = 0; | |
055ee297 AC |
1312 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1313 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1314 | unsigned int byte; | |
f2b30012 AC |
1315 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1316 | LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); | |
1317 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1318 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8)); | |
1319 | } | |
1320 | } | |
1321 | } | |
a48e8c8d | 1322 | #endif |
f2b30012 AC |
1323 | } |
1324 | ||
1325 | ||
1326 | 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU | |
1327 | "lbu r<RT>, <OFFSET>(r<BASE>)" | |
23850e92 JL |
1328 | *mipsI,mipsII,mipsIII,mipsIV: |
1329 | *vr5000: | |
90ad43b2 AC |
1330 | // start-sanitize-vr5400 |
1331 | *vr5400: | |
1332 | // end-sanitize-vr5400 | |
f2b30012 AC |
1333 | // start-sanitize-r5900 |
1334 | *r5900: | |
1335 | // end-sanitize-r5900 | |
1336 | *r3900: | |
1337 | // start-sanitize-tx19 | |
1338 | *tx19: | |
1339 | // end-sanitize-tx19 | |
1340 | { | |
1341 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1342 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1343 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1344 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1345 | { |
49a76833 AC |
1346 | address_word vaddr = ((unsigned64)op1 + offset); |
1347 | address_word paddr; | |
f2b30012 AC |
1348 | int uncached; |
1349 | { | |
1350 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1351 | { | |
1352 | unsigned64 memval = 0; | |
1353 | unsigned64 memval1 = 0; | |
1354 | unsigned64 mask = 0x7; | |
1355 | unsigned int shift = 0; | |
055ee297 AC |
1356 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1357 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1358 | unsigned int byte; | |
f2b30012 AC |
1359 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1360 | LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL); | |
1361 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1362 | GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF)); | |
1363 | } | |
1364 | } | |
1365 | } | |
1366 | } | |
1367 | ||
1368 | ||
1369 | 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD | |
1370 | "ld r<RT>, <OFFSET>(r<BASE>)" | |
1371 | *mipsIII: | |
1372 | *mipsIV: | |
23850e92 | 1373 | *vr5000: |
90ad43b2 AC |
1374 | // start-sanitize-vr5400 |
1375 | *vr5400: | |
1376 | // end-sanitize-vr5400 | |
f2b30012 AC |
1377 | // start-sanitize-r5900 |
1378 | *r5900: | |
1379 | // end-sanitize-r5900 | |
1380 | *r3900: | |
1381 | // start-sanitize-tx19 | |
1382 | *tx19: | |
1383 | // end-sanitize-tx19 | |
1384 | { | |
1385 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1386 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1387 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1388 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1389 | { |
49a76833 AC |
1390 | address_word vaddr = ((unsigned64)op1 + offset); |
1391 | address_word paddr; | |
f2b30012 AC |
1392 | int uncached; |
1393 | if ((vaddr & 7) != 0) | |
055ee297 | 1394 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1395 | else |
1396 | { | |
1397 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1398 | { | |
1399 | unsigned64 memval = 0; | |
1400 | unsigned64 memval1 = 0; | |
f2b30012 AC |
1401 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); |
1402 | GPR[destreg] = memval; | |
1403 | } | |
1404 | } | |
1405 | } | |
1406 | } | |
1407 | ||
1408 | ||
49a6eed5 | 1409 | 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz |
f2b30012 AC |
1410 | "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
1411 | *mipsII: | |
1412 | *mipsIII: | |
1413 | *mipsIV: | |
23850e92 | 1414 | *vr5000: |
90ad43b2 AC |
1415 | // start-sanitize-vr5400 |
1416 | *vr5400: | |
1417 | // end-sanitize-vr5400 | |
f2b30012 AC |
1418 | // start-sanitize-r5900 |
1419 | *r5900: | |
1420 | // end-sanitize-r5900 | |
1421 | *r3900: | |
1422 | // start-sanitize-tx19 | |
1423 | *tx19: | |
1424 | // end-sanitize-tx19 | |
1425 | { | |
1426 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1427 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1428 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1429 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1430 | { |
49a76833 AC |
1431 | address_word vaddr = ((unsigned64)op1 + offset); |
1432 | address_word paddr; | |
f2b30012 AC |
1433 | int uncached; |
1434 | if ((vaddr & 7) != 0) | |
055ee297 | 1435 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1436 | else |
1437 | { | |
1438 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1439 | { | |
1440 | unsigned64 memval = 0; | |
1441 | unsigned64 memval1 = 0; | |
f2b30012 AC |
1442 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); |
1443 | COP_LD(((instruction >> 26) & 0x3),destreg,memval);; | |
1444 | } | |
1445 | } | |
1446 | } | |
1447 | } | |
1448 | ||
1449 | ||
1450 | 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL | |
1451 | "ldl r<RT>, <OFFSET>(r<BASE>)" | |
1452 | *mipsIII: | |
1453 | *mipsIV: | |
23850e92 | 1454 | *vr5000: |
90ad43b2 AC |
1455 | // start-sanitize-vr5400 |
1456 | *vr5400: | |
1457 | // end-sanitize-vr5400 | |
f2b30012 AC |
1458 | // start-sanitize-r5900 |
1459 | *r5900: | |
1460 | // end-sanitize-r5900 | |
1461 | *r3900: | |
1462 | // start-sanitize-tx19 | |
1463 | *tx19: | |
1464 | // end-sanitize-tx19 | |
1465 | { | |
1466 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1467 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1468 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1469 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1470 | { |
49a76833 AC |
1471 | address_word vaddr = ((unsigned64)op1 + offset); |
1472 | address_word paddr; | |
f2b30012 AC |
1473 | int uncached; |
1474 | { | |
1475 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1476 | { | |
1477 | unsigned64 memval = 0; | |
1478 | unsigned64 memval1 = 0; | |
1479 | unsigned64 mask = 7; | |
1480 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
1481 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
1482 | int byte; | |
1483 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
1484 | byte = ((vaddr & mask) ^ bigend); | |
63be8feb | 1485 | if (!BigEndianMem) |
f2b30012 AC |
1486 | paddr &= ~mask; |
1487 | LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL); | |
1488 | GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1))); | |
1489 | } | |
1490 | } | |
1491 | } | |
1492 | } | |
1493 | ||
1494 | ||
1495 | 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR | |
1496 | "ldr r<RT>, <OFFSET>(r<BASE>)" | |
1497 | *mipsIII: | |
1498 | *mipsIV: | |
23850e92 | 1499 | *vr5000: |
90ad43b2 AC |
1500 | // start-sanitize-vr5400 |
1501 | *vr5400: | |
1502 | // end-sanitize-vr5400 | |
f2b30012 AC |
1503 | // start-sanitize-r5900 |
1504 | *r5900: | |
1505 | // end-sanitize-r5900 | |
1506 | *r3900: | |
1507 | // start-sanitize-tx19 | |
1508 | *tx19: | |
1509 | // end-sanitize-tx19 | |
1510 | { | |
1511 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1512 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1513 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1514 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1515 | { |
49a76833 AC |
1516 | address_word vaddr = ((unsigned64)op1 + offset); |
1517 | address_word paddr; | |
f2b30012 AC |
1518 | int uncached; |
1519 | { | |
1520 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1521 | { | |
1522 | unsigned64 memval = 0; | |
1523 | unsigned64 memval1 = 0; | |
1524 | unsigned64 mask = 7; | |
1525 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
1526 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
1527 | int byte; | |
1528 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
1529 | byte = ((vaddr & mask) ^ bigend); | |
63be8feb | 1530 | if (BigEndianMem) |
f2b30012 AC |
1531 | paddr &= ~mask; |
1532 | LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL); | |
1533 | { | |
1534 | unsigned64 srcmask; | |
1535 | if (byte == 0) | |
1536 | srcmask = 0; | |
1537 | else | |
1538 | srcmask = ((unsigned64)-1 << (8 * (8 - byte))); | |
1539 | GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte))); | |
1540 | } | |
1541 | } | |
1542 | } | |
1543 | } | |
1544 | } | |
1545 | ||
1546 | ||
1547 | 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH | |
1548 | "lh r<RT>, <OFFSET>(r<BASE>)" | |
23850e92 JL |
1549 | *mipsI,mipsII,mipsIII,mipsIV: |
1550 | *vr5000: | |
90ad43b2 AC |
1551 | // start-sanitize-vr5400 |
1552 | *vr5400: | |
1553 | // end-sanitize-vr5400 | |
f2b30012 AC |
1554 | // start-sanitize-r5900 |
1555 | *r5900: | |
1556 | // end-sanitize-r5900 | |
1557 | *r3900: | |
1558 | // start-sanitize-tx19 | |
1559 | *tx19: | |
1560 | // end-sanitize-tx19 | |
1561 | { | |
1562 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1563 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1564 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1565 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1566 | { |
49a76833 AC |
1567 | address_word vaddr = ((unsigned64)op1 + offset); |
1568 | address_word paddr; | |
f2b30012 AC |
1569 | int uncached; |
1570 | if ((vaddr & 1) != 0) | |
055ee297 | 1571 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1572 | else |
1573 | { | |
1574 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1575 | { | |
1576 | unsigned64 memval = 0; | |
1577 | unsigned64 memval1 = 0; | |
1578 | unsigned64 mask = 0x7; | |
1579 | unsigned int shift = 1; | |
055ee297 AC |
1580 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1581 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1582 | unsigned int byte; | |
f2b30012 AC |
1583 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1584 | LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); | |
1585 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1586 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16)); | |
1587 | } | |
1588 | } | |
1589 | } | |
1590 | } | |
1591 | ||
1592 | ||
1593 | 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU | |
1594 | "lhu r<RT>, <OFFSET>(r<BASE>)" | |
23850e92 JL |
1595 | *mipsI,mipsII,mipsIII,mipsIV: |
1596 | *vr5000: | |
90ad43b2 AC |
1597 | // start-sanitize-vr5400 |
1598 | *vr5400: | |
1599 | // end-sanitize-vr5400 | |
f2b30012 AC |
1600 | // start-sanitize-r5900 |
1601 | *r5900: | |
1602 | // end-sanitize-r5900 | |
1603 | *r3900: | |
1604 | // start-sanitize-tx19 | |
1605 | *tx19: | |
1606 | // end-sanitize-tx19 | |
1607 | { | |
1608 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1609 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1610 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1611 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1612 | { |
49a76833 AC |
1613 | address_word vaddr = ((unsigned64)op1 + offset); |
1614 | address_word paddr; | |
f2b30012 AC |
1615 | int uncached; |
1616 | if ((vaddr & 1) != 0) | |
055ee297 | 1617 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1618 | else |
1619 | { | |
1620 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1621 | { | |
1622 | unsigned64 memval = 0; | |
1623 | unsigned64 memval1 = 0; | |
1624 | unsigned64 mask = 0x7; | |
1625 | unsigned int shift = 1; | |
055ee297 AC |
1626 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1627 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1628 | unsigned int byte; | |
f2b30012 AC |
1629 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1630 | LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL); | |
1631 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1632 | GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF)); | |
1633 | } | |
1634 | } | |
1635 | } | |
1636 | } | |
1637 | ||
1638 | ||
1639 | 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL | |
1640 | "ll r<RT>, <OFFSET>(r<BASE>)" | |
1641 | *mipsII: | |
1642 | *mipsIII: | |
1643 | *mipsIV: | |
23850e92 | 1644 | *vr5000: |
90ad43b2 AC |
1645 | // start-sanitize-vr5400 |
1646 | *vr5400: | |
1647 | // end-sanitize-vr5400 | |
f2b30012 AC |
1648 | // start-sanitize-r5900 |
1649 | *r5900: | |
1650 | // end-sanitize-r5900 | |
1651 | *r3900: | |
1652 | // start-sanitize-tx19 | |
1653 | *tx19: | |
1654 | // end-sanitize-tx19 | |
1655 | { | |
1656 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1657 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1658 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1659 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1660 | { |
49a76833 AC |
1661 | address_word vaddr = ((unsigned64)op1 + offset); |
1662 | address_word paddr; | |
f2b30012 AC |
1663 | int uncached; |
1664 | if ((vaddr & 3) != 0) | |
055ee297 | 1665 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1666 | else |
1667 | { | |
1668 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1669 | { | |
1670 | unsigned64 memval = 0; | |
1671 | unsigned64 memval1 = 0; | |
1672 | unsigned64 mask = 0x7; | |
1673 | unsigned int shift = 2; | |
055ee297 AC |
1674 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1675 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1676 | unsigned int byte; | |
f2b30012 AC |
1677 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1678 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
1679 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1680 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); | |
1681 | LLBIT = 1; | |
1682 | } | |
1683 | } | |
1684 | } | |
1685 | } | |
1686 | ||
1687 | ||
1688 | 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD | |
1689 | "lld r<RT>, <OFFSET>(r<BASE>)" | |
1690 | *mipsIII: | |
1691 | *mipsIV: | |
23850e92 | 1692 | *vr5000: |
90ad43b2 AC |
1693 | // start-sanitize-vr5400 |
1694 | *vr5400: | |
1695 | // end-sanitize-vr5400 | |
f2b30012 AC |
1696 | // start-sanitize-r5900 |
1697 | *r5900: | |
1698 | // end-sanitize-r5900 | |
1699 | *r3900: | |
1700 | // start-sanitize-tx19 | |
1701 | *tx19: | |
1702 | // end-sanitize-tx19 | |
1703 | { | |
1704 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1705 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1706 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1707 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1708 | { |
49a76833 AC |
1709 | address_word vaddr = ((unsigned64)op1 + offset); |
1710 | address_word paddr; | |
f2b30012 AC |
1711 | int uncached; |
1712 | if ((vaddr & 7) != 0) | |
055ee297 | 1713 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1714 | else |
1715 | { | |
1716 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1717 | { | |
1718 | unsigned64 memval = 0; | |
1719 | unsigned64 memval1 = 0; | |
f2b30012 AC |
1720 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); |
1721 | GPR[destreg] = memval; | |
1722 | LLBIT = 1; | |
1723 | } | |
1724 | } | |
1725 | } | |
1726 | } | |
1727 | ||
1728 | ||
1729 | 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI | |
1730 | "lui r<RT>, <IMMEDIATE>" | |
23850e92 JL |
1731 | *mipsI,mipsII,mipsIII,mipsIV: |
1732 | *vr5000: | |
90ad43b2 AC |
1733 | // start-sanitize-vr5400 |
1734 | *vr5400: | |
1735 | // end-sanitize-vr5400 | |
f2b30012 AC |
1736 | // start-sanitize-r5900 |
1737 | *r5900: | |
1738 | // end-sanitize-r5900 | |
1739 | *r3900: | |
1740 | // start-sanitize-tx19 | |
1741 | *tx19: | |
1742 | // end-sanitize-tx19 | |
1743 | { | |
055ee297 | 1744 | GPR[RT] = EXTEND32 (IMMEDIATE << 16); |
f2b30012 AC |
1745 | } |
1746 | ||
1747 | ||
1748 | 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW | |
1749 | "lw r<RT>, <OFFSET>(r<BASE>)" | |
23850e92 JL |
1750 | *mipsI,mipsII,mipsIII,mipsIV: |
1751 | *vr5000: | |
90ad43b2 AC |
1752 | // start-sanitize-vr5400 |
1753 | *vr5400: | |
1754 | // end-sanitize-vr5400 | |
f2b30012 AC |
1755 | // start-sanitize-r5900 |
1756 | *r5900: | |
1757 | // end-sanitize-r5900 | |
1758 | *r3900: | |
1759 | // start-sanitize-tx19 | |
1760 | *tx19: | |
1761 | // end-sanitize-tx19 | |
1762 | { | |
1763 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1764 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1765 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1766 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1767 | { |
49a76833 AC |
1768 | address_word vaddr = ((unsigned64)op1 + offset); |
1769 | address_word paddr; | |
f2b30012 AC |
1770 | int uncached; |
1771 | if ((vaddr & 3) != 0) | |
055ee297 | 1772 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1773 | else |
1774 | { | |
1775 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1776 | { | |
1777 | unsigned64 memval = 0; | |
1778 | unsigned64 memval1 = 0; | |
1779 | unsigned64 mask = 0x7; | |
1780 | unsigned int shift = 2; | |
055ee297 AC |
1781 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1782 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1783 | unsigned int byte; | |
f2b30012 AC |
1784 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1785 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
1786 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1787 | GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); | |
1788 | } | |
1789 | } | |
1790 | } | |
1791 | } | |
1792 | ||
1793 | ||
49a6eed5 | 1794 | 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz |
f2b30012 | 1795 | "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
23850e92 JL |
1796 | *mipsI,mipsII,mipsIII,mipsIV: |
1797 | *vr5000: | |
90ad43b2 AC |
1798 | // start-sanitize-vr5400 |
1799 | *vr5400: | |
1800 | // end-sanitize-vr5400 | |
f2b30012 AC |
1801 | // start-sanitize-r5900 |
1802 | *r5900: | |
1803 | // end-sanitize-r5900 | |
1804 | *r3900: | |
1805 | // start-sanitize-tx19 | |
1806 | *tx19: | |
1807 | // end-sanitize-tx19 | |
1808 | { | |
1809 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1810 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1811 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1812 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1813 | { |
49a76833 AC |
1814 | address_word vaddr = ((unsigned64)op1 + offset); |
1815 | address_word paddr; | |
f2b30012 AC |
1816 | int uncached; |
1817 | if ((vaddr & 3) != 0) | |
055ee297 | 1818 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1819 | else |
1820 | { | |
1821 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1822 | { | |
1823 | unsigned64 memval = 0; | |
1824 | unsigned64 memval1 = 0; | |
1825 | unsigned64 mask = 0x7; | |
1826 | unsigned int shift = 2; | |
055ee297 AC |
1827 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1828 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1829 | unsigned int byte; | |
f2b30012 AC |
1830 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1831 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
1832 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1833 | COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF)); | |
1834 | } | |
1835 | } | |
1836 | } | |
1837 | } | |
1838 | ||
1839 | ||
1840 | 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL | |
1841 | "lwl r<RT>, <OFFSET>(r<BASE>)" | |
23850e92 JL |
1842 | *mipsI,mipsII,mipsIII,mipsIV: |
1843 | *vr5000: | |
90ad43b2 AC |
1844 | // start-sanitize-vr5400 |
1845 | *vr5400: | |
1846 | // end-sanitize-vr5400 | |
f2b30012 AC |
1847 | // start-sanitize-r5900 |
1848 | *r5900: | |
1849 | // end-sanitize-r5900 | |
1850 | *r3900: | |
1851 | // start-sanitize-tx19 | |
1852 | *tx19: | |
1853 | // end-sanitize-tx19 | |
1854 | { | |
1855 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1856 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1857 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1858 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1859 | { |
49a76833 AC |
1860 | address_word vaddr = ((unsigned64)op1 + offset); |
1861 | address_word paddr; | |
f2b30012 AC |
1862 | int uncached; |
1863 | { | |
1864 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1865 | { | |
1866 | unsigned64 memval = 0; | |
1867 | unsigned64 memval1 = 0; | |
1868 | unsigned64 mask = 3; | |
1869 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
1870 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
1871 | int byte; | |
1872 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
1873 | byte = ((vaddr & mask) ^ bigend); | |
63be8feb | 1874 | if (!BigEndianMem) |
f2b30012 AC |
1875 | paddr &= ~mask; |
1876 | LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL); | |
1877 | if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { | |
1878 | memval >>= 32; | |
1879 | } | |
1880 | GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1))); | |
1881 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
1882 | } | |
1883 | } | |
1884 | } | |
1885 | } | |
1886 | ||
1887 | ||
1888 | 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR | |
1889 | "lwr r<RT>, <OFFSET>(r<BASE>)" | |
23850e92 JL |
1890 | *mipsI,mipsII,mipsIII,mipsIV: |
1891 | *vr5000: | |
90ad43b2 AC |
1892 | // start-sanitize-vr5400 |
1893 | *vr5400: | |
1894 | // end-sanitize-vr5400 | |
f2b30012 AC |
1895 | // start-sanitize-r5900 |
1896 | *r5900: | |
1897 | // end-sanitize-r5900 | |
1898 | *r3900: | |
1899 | // start-sanitize-tx19 | |
1900 | *tx19: | |
1901 | // end-sanitize-tx19 | |
1902 | { | |
1903 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1904 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1905 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1906 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1907 | { |
49a76833 AC |
1908 | address_word vaddr = ((unsigned64)op1 + offset); |
1909 | address_word paddr; | |
f2b30012 AC |
1910 | int uncached; |
1911 | { | |
1912 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1913 | { | |
1914 | unsigned64 memval = 0; | |
1915 | unsigned64 memval1 = 0; | |
1916 | unsigned64 mask = 3; | |
1917 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
1918 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
1919 | int byte; | |
1920 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
1921 | byte = ((vaddr & mask) ^ bigend); | |
63be8feb | 1922 | if (BigEndianMem) |
f2b30012 AC |
1923 | paddr &= ~mask; |
1924 | LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL); | |
1925 | if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { | |
1926 | memval >>= 32; | |
1927 | } | |
1928 | { | |
1929 | unsigned64 srcmask; | |
1930 | if (byte == 0) | |
1931 | srcmask = 0; | |
1932 | else | |
1933 | srcmask = ((unsigned64)-1 << (8 * (4 - byte))); | |
1934 | GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte))); | |
1935 | } | |
1936 | GPR[destreg] = SIGNEXTEND(GPR[destreg],32); | |
1937 | } | |
1938 | } | |
1939 | } | |
1940 | } | |
1941 | ||
1942 | ||
1943 | 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU | |
1944 | "lwu r<RT>, <OFFSET>(r<BASE>)" | |
1945 | *mipsIII: | |
1946 | *mipsIV: | |
23850e92 | 1947 | *vr5000: |
90ad43b2 AC |
1948 | // start-sanitize-vr5400 |
1949 | *vr5400: | |
1950 | // end-sanitize-vr5400 | |
f2b30012 AC |
1951 | // start-sanitize-r5900 |
1952 | *r5900: | |
1953 | // end-sanitize-r5900 | |
1954 | *r3900: | |
1955 | // start-sanitize-tx19 | |
1956 | *tx19: | |
1957 | // end-sanitize-tx19 | |
1958 | { | |
1959 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
1960 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
1961 | int destreg = ((instruction >> 16) & 0x0000001F); | |
1962 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 1963 | { |
49a76833 AC |
1964 | address_word vaddr = ((unsigned64)op1 + offset); |
1965 | address_word paddr; | |
f2b30012 AC |
1966 | int uncached; |
1967 | if ((vaddr & 3) != 0) | |
055ee297 | 1968 | SignalExceptionAddressLoad(); |
f2b30012 AC |
1969 | else |
1970 | { | |
1971 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
1972 | { | |
1973 | unsigned64 memval = 0; | |
1974 | unsigned64 memval1 = 0; | |
1975 | unsigned64 mask = 0x7; | |
1976 | unsigned int shift = 2; | |
055ee297 AC |
1977 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
1978 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
1979 | unsigned int byte; | |
f2b30012 AC |
1980 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
1981 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
1982 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
1983 | GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF)); | |
1984 | } | |
1985 | } | |
1986 | } | |
1987 | } | |
1988 | ||
1989 | ||
1990 | 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI | |
1991 | "mfhi r<RD>" | |
23850e92 JL |
1992 | *mipsI,mipsII,mipsIII,mipsIV: |
1993 | *vr5000: | |
90ad43b2 AC |
1994 | // start-sanitize-vr5400 |
1995 | *vr5400: | |
1996 | // end-sanitize-vr5400 | |
f2b30012 AC |
1997 | // start-sanitize-r5900 |
1998 | *r5900: | |
1999 | // end-sanitize-r5900 | |
2000 | *r3900: | |
2001 | // start-sanitize-tx19 | |
2002 | *tx19: | |
2003 | // end-sanitize-tx19 | |
2004 | { | |
055ee297 | 2005 | GPR[RD] = HI; |
030843d7 | 2006 | #if 0 |
f2b30012 | 2007 | HIACCESS = 3; |
030843d7 | 2008 | #endif |
f2b30012 AC |
2009 | } |
2010 | ||
2011 | ||
2012 | 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO | |
2013 | "mflo r<RD>" | |
23850e92 JL |
2014 | *mipsI,mipsII,mipsIII,mipsIV: |
2015 | *vr5000: | |
90ad43b2 AC |
2016 | // start-sanitize-vr5400 |
2017 | *vr5400: | |
2018 | // end-sanitize-vr5400 | |
f2b30012 AC |
2019 | // start-sanitize-r5900 |
2020 | *r5900: | |
2021 | // end-sanitize-r5900 | |
2022 | *r3900: | |
2023 | // start-sanitize-tx19 | |
2024 | *tx19: | |
2025 | // end-sanitize-tx19 | |
2026 | { | |
055ee297 | 2027 | GPR[RD] = LO; |
030843d7 | 2028 | #if 0 |
f2b30012 | 2029 | LOACCESS = 3; /* 3rd instruction will be safe */ |
030843d7 | 2030 | #endif |
f2b30012 AC |
2031 | } |
2032 | ||
2033 | ||
2034 | 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN | |
2035 | "movn r<RD>, r<RS>, r<RT>" | |
2036 | *mipsIV: | |
23850e92 | 2037 | *vr5000: |
90ad43b2 AC |
2038 | // start-sanitize-vr5400 |
2039 | *vr5400: | |
2040 | // end-sanitize-vr5400 | |
f2b30012 AC |
2041 | // start-sanitize-r5900 |
2042 | *r5900: | |
2043 | // end-sanitize-r5900 | |
2044 | { | |
055ee297 AC |
2045 | if (GPR[RT] != 0) |
2046 | GPR[RD] = GPR[RS]; | |
f2b30012 AC |
2047 | } |
2048 | ||
2049 | ||
2050 | 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ | |
2051 | "movz r<RD>, r<RS>, r<RT>" | |
2052 | *mipsIV: | |
23850e92 | 2053 | *vr5000: |
90ad43b2 AC |
2054 | // start-sanitize-vr5400 |
2055 | *vr5400: | |
2056 | // end-sanitize-vr5400 | |
f2b30012 AC |
2057 | // start-sanitize-r5900 |
2058 | *r5900: | |
2059 | // end-sanitize-r5900 | |
2060 | { | |
055ee297 AC |
2061 | if (GPR[RT] == 0) |
2062 | GPR[RD] = GPR[RS]; | |
f2b30012 AC |
2063 | } |
2064 | ||
2065 | ||
2066 | 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI | |
2067 | "mthi r<RS>" | |
23850e92 JL |
2068 | *mipsI,mipsII,mipsIII,mipsIV: |
2069 | *vr5000: | |
90ad43b2 AC |
2070 | // start-sanitize-vr5400 |
2071 | *vr5400: | |
2072 | // end-sanitize-vr5400 | |
f2b30012 AC |
2073 | // start-sanitize-r5900 |
2074 | *r5900: | |
2075 | // end-sanitize-r5900 | |
2076 | *r3900: | |
2077 | // start-sanitize-tx19 | |
2078 | *tx19: | |
2079 | // end-sanitize-tx19 | |
2080 | { | |
030843d7 | 2081 | #if 0 |
f2b30012 | 2082 | if (HIACCESS != 0) |
055ee297 | 2083 | sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n"); |
030843d7 | 2084 | #endif |
055ee297 | 2085 | HI = GPR[RS]; |
030843d7 | 2086 | #if 0 |
f2b30012 | 2087 | HIACCESS = 3; /* 3rd instruction will be safe */ |
030843d7 | 2088 | #endif |
f2b30012 AC |
2089 | } |
2090 | ||
2091 | ||
2092 | 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO | |
2093 | "mtlo r<RS>" | |
23850e92 JL |
2094 | *mipsI,mipsII,mipsIII,mipsIV: |
2095 | *vr5000: | |
90ad43b2 AC |
2096 | // start-sanitize-vr5400 |
2097 | *vr5400: | |
2098 | // end-sanitize-vr5400 | |
f2b30012 AC |
2099 | // start-sanitize-r5900 |
2100 | *r5900: | |
2101 | // end-sanitize-r5900 | |
2102 | *r3900: | |
2103 | // start-sanitize-tx19 | |
2104 | *tx19: | |
2105 | // end-sanitize-tx19 | |
2106 | { | |
030843d7 | 2107 | #if 0 |
f2b30012 | 2108 | if (LOACCESS != 0) |
055ee297 | 2109 | sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n"); |
030843d7 | 2110 | #endif |
055ee297 | 2111 | LO = GPR[RS]; |
030843d7 | 2112 | #if 0 |
f2b30012 | 2113 | LOACCESS = 3; /* 3rd instruction will be safe */ |
030843d7 | 2114 | #endif |
f2b30012 AC |
2115 | } |
2116 | ||
2117 | ||
030843d7 | 2118 | 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT |
f2b30012 | 2119 | "mult r<RS>, r<RT>" |
23850e92 | 2120 | *mipsI,mipsII,mipsIII,mipsIV: |
030843d7 AC |
2121 | { |
2122 | signed64 prod; | |
2123 | CHECKHILO ("Multiplication"); | |
2124 | prod = (((signed64)(signed32) GPR[RS]) | |
2125 | * ((signed64)(signed32) GPR[RT])); | |
2126 | LO = EXTEND32 (VL4_8 (prod)); | |
2127 | HI = EXTEND32 (VH4_8 (prod)); | |
2128 | } | |
2129 | 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT | |
2130 | "mult r<RD>, r<RS>, r<RT>" | |
23850e92 | 2131 | *vr5000: |
90ad43b2 AC |
2132 | // start-sanitize-vr5400 |
2133 | *vr5400: | |
2134 | // end-sanitize-vr5400 | |
f2b30012 AC |
2135 | // start-sanitize-r5900 |
2136 | *r5900: | |
2137 | // end-sanitize-r5900 | |
2138 | *r3900: | |
2139 | // start-sanitize-tx19 | |
2140 | *tx19: | |
2141 | // end-sanitize-tx19 | |
2142 | { | |
2143 | signed64 prod; | |
2144 | CHECKHILO ("Multiplication"); | |
055ee297 AC |
2145 | prod = (((signed64)(signed32) GPR[RS]) |
2146 | * ((signed64)(signed32) GPR[RT])); | |
f2b30012 AC |
2147 | LO = EXTEND32 (VL4_8 (prod)); |
2148 | HI = EXTEND32 (VH4_8 (prod)); | |
030843d7 AC |
2149 | if (RD != 0) |
2150 | GPR[RD] = LO; | |
f2b30012 AC |
2151 | } |
2152 | ||
2153 | ||
030843d7 | 2154 | 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU |
f2b30012 | 2155 | "multu r<RS>, r<RT>" |
23850e92 | 2156 | *mipsI,mipsII,mipsIII,mipsIV: |
030843d7 AC |
2157 | { |
2158 | unsigned64 prod; | |
2159 | CHECKHILO ("Multiplication"); | |
2160 | prod = (((unsigned64)(unsigned32) GPR[RS]) | |
2161 | * ((unsigned64)(unsigned32) GPR[RT])); | |
2162 | LO = EXTEND32 (VL4_8 (prod)); | |
2163 | HI = EXTEND32 (VH4_8 (prod)); | |
2164 | } | |
2165 | 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU | |
2166 | "multu r<RD>, r<RS>, r<RT>" | |
23850e92 | 2167 | *vr5000: |
90ad43b2 AC |
2168 | // start-sanitize-vr5400 |
2169 | *vr5400: | |
2170 | // end-sanitize-vr5400 | |
f2b30012 AC |
2171 | // start-sanitize-r5900 |
2172 | *r5900: | |
2173 | // end-sanitize-r5900 | |
2174 | *r3900: | |
2175 | // start-sanitize-tx19 | |
2176 | *tx19: | |
2177 | // end-sanitize-tx19 | |
2178 | { | |
2179 | unsigned64 prod; | |
2180 | CHECKHILO ("Multiplication"); | |
055ee297 AC |
2181 | prod = (((unsigned64)(unsigned32) GPR[RS]) |
2182 | * ((unsigned64)(unsigned32) GPR[RT])); | |
f2b30012 AC |
2183 | LO = EXTEND32 (VL4_8 (prod)); |
2184 | HI = EXTEND32 (VH4_8 (prod)); | |
030843d7 AC |
2185 | if (RD != 0) |
2186 | GPR[RD] = LO; | |
f2b30012 AC |
2187 | } |
2188 | ||
2189 | ||
2190 | 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR | |
2191 | "nor r<RD>, r<RS>, r<RT>" | |
23850e92 JL |
2192 | *mipsI,mipsII,mipsIII,mipsIV: |
2193 | *vr5000: | |
90ad43b2 AC |
2194 | // start-sanitize-vr5400 |
2195 | *vr5400: | |
2196 | // end-sanitize-vr5400 | |
f2b30012 AC |
2197 | // start-sanitize-r5900 |
2198 | *r5900: | |
2199 | // end-sanitize-r5900 | |
2200 | *r3900: | |
2201 | // start-sanitize-tx19 | |
2202 | *tx19: | |
2203 | // end-sanitize-tx19 | |
2204 | { | |
055ee297 | 2205 | GPR[RD] = ~ (GPR[RS] | GPR[RT]); |
f2b30012 AC |
2206 | } |
2207 | ||
2208 | ||
2209 | 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR | |
2210 | "or r<RD>, r<RS>, r<RT>" | |
23850e92 JL |
2211 | *mipsI,mipsII,mipsIII,mipsIV: |
2212 | *vr5000: | |
90ad43b2 AC |
2213 | // start-sanitize-vr5400 |
2214 | *vr5400: | |
2215 | // end-sanitize-vr5400 | |
f2b30012 AC |
2216 | // start-sanitize-r5900 |
2217 | *r5900: | |
2218 | // end-sanitize-r5900 | |
2219 | *r3900: | |
2220 | // start-sanitize-tx19 | |
2221 | *tx19: | |
2222 | // end-sanitize-tx19 | |
2223 | { | |
055ee297 | 2224 | GPR[RD] = (GPR[RS] | GPR[RT]); |
f2b30012 AC |
2225 | } |
2226 | ||
2227 | ||
2228 | 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI | |
055ee297 | 2229 | "ori r<RT>, r<RS>, <IMMEDIATE>" |
23850e92 JL |
2230 | *mipsI,mipsII,mipsIII,mipsIV: |
2231 | *vr5000: | |
90ad43b2 AC |
2232 | // start-sanitize-vr5400 |
2233 | *vr5400: | |
2234 | // end-sanitize-vr5400 | |
f2b30012 AC |
2235 | // start-sanitize-r5900 |
2236 | *r5900: | |
2237 | // end-sanitize-r5900 | |
2238 | *r3900: | |
2239 | // start-sanitize-tx19 | |
2240 | *tx19: | |
2241 | // end-sanitize-tx19 | |
2242 | { | |
055ee297 | 2243 | GPR[RT] = (GPR[RS] | IMMEDIATE); |
f2b30012 AC |
2244 | } |
2245 | ||
2246 | ||
2247 | 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF | |
2248 | *mipsIV: | |
23850e92 | 2249 | *vr5000: |
90ad43b2 AC |
2250 | // start-sanitize-vr5400 |
2251 | *vr5400: | |
2252 | // end-sanitize-vr5400 | |
f2b30012 AC |
2253 | // start-sanitize-r5900 |
2254 | *r5900: | |
2255 | // end-sanitize-r5900 | |
2256 | { | |
2257 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2258 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2259 | int hint = ((instruction >> 16) & 0x0000001F); | |
2260 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2261 | { |
49a76833 AC |
2262 | address_word vaddr = ((unsigned64)op1 + offset); |
2263 | address_word paddr; | |
f2b30012 AC |
2264 | int uncached; |
2265 | { | |
2266 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
2267 | Prefetch(uncached,paddr,vaddr,isDATA,hint); | |
2268 | } | |
2269 | } | |
2270 | } | |
2271 | ||
2272 | 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB | |
2273 | "sb r<RT>, <OFFSET>(r<BASE>)" | |
23850e92 JL |
2274 | *mipsI,mipsII,mipsIII,mipsIV: |
2275 | *vr5000: | |
90ad43b2 AC |
2276 | // start-sanitize-vr5400 |
2277 | *vr5400: | |
2278 | // end-sanitize-vr5400 | |
f2b30012 AC |
2279 | // start-sanitize-r5900 |
2280 | *r5900: | |
2281 | // end-sanitize-r5900 | |
2282 | *r3900: | |
2283 | // start-sanitize-tx19 | |
2284 | *tx19: | |
2285 | // end-sanitize-tx19 | |
2286 | { | |
2287 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2288 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2289 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2290 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2291 | { |
49a76833 AC |
2292 | address_word vaddr = ((unsigned64)op1 + offset); |
2293 | address_word paddr; | |
f2b30012 AC |
2294 | int uncached; |
2295 | { | |
2296 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2297 | { | |
2298 | unsigned64 memval = 0; | |
2299 | unsigned64 memval1 = 0; | |
2300 | unsigned64 mask = 0x7; | |
2301 | unsigned int shift = 0; | |
2302 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
2303 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
2304 | unsigned int byte; | |
2305 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
2306 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
2307 | memval = ((unsigned64) op2 << (8 * byte)); | |
2308 | { | |
2309 | StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL); | |
2310 | } | |
2311 | } | |
2312 | } | |
2313 | } | |
2314 | } | |
2315 | ||
2316 | ||
2317 | 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC | |
2318 | "sc r<RT>, <OFFSET>(r<BASE>)" | |
2319 | *mipsII: | |
2320 | *mipsIII: | |
2321 | *mipsIV: | |
23850e92 | 2322 | *vr5000: |
90ad43b2 AC |
2323 | // start-sanitize-vr5400 |
2324 | *vr5400: | |
2325 | // end-sanitize-vr5400 | |
f2b30012 AC |
2326 | // start-sanitize-r5900 |
2327 | *r5900: | |
2328 | // end-sanitize-r5900 | |
2329 | *r3900: | |
2330 | // start-sanitize-tx19 | |
2331 | *tx19: | |
2332 | // end-sanitize-tx19 | |
2333 | { | |
2334 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2335 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2336 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2337 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2338 | { |
49a76833 AC |
2339 | address_word vaddr = ((unsigned64)op1 + offset); |
2340 | address_word paddr; | |
f2b30012 AC |
2341 | int uncached; |
2342 | if ((vaddr & 3) != 0) | |
055ee297 | 2343 | SignalExceptionAddressStore(); |
f2b30012 AC |
2344 | else |
2345 | { | |
2346 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2347 | { | |
2348 | unsigned64 memval = 0; | |
2349 | unsigned64 memval1 = 0; | |
2350 | unsigned64 mask = 0x7; | |
2351 | unsigned int byte; | |
2352 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
2353 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
2354 | memval = ((unsigned64) op2 << (8 * byte)); | |
2355 | if (LLBIT) | |
2356 | { | |
2357 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
2358 | } | |
2359 | GPR[(instruction >> 16) & 0x0000001F] = LLBIT; | |
2360 | } | |
2361 | } | |
2362 | } | |
2363 | } | |
2364 | ||
2365 | ||
2366 | 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD | |
2367 | "scd r<RT>, <OFFSET>(r<BASE>)" | |
2368 | *mipsIII: | |
2369 | *mipsIV: | |
23850e92 | 2370 | *vr5000: |
90ad43b2 AC |
2371 | // start-sanitize-vr5400 |
2372 | *vr5400: | |
2373 | // end-sanitize-vr5400 | |
f2b30012 AC |
2374 | // start-sanitize-r5900 |
2375 | *r5900: | |
2376 | // end-sanitize-r5900 | |
2377 | *r3900: | |
2378 | // start-sanitize-tx19 | |
2379 | *tx19: | |
2380 | // end-sanitize-tx19 | |
2381 | { | |
2382 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2383 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2384 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2385 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2386 | { |
49a76833 AC |
2387 | address_word vaddr = ((unsigned64)op1 + offset); |
2388 | address_word paddr; | |
f2b30012 AC |
2389 | int uncached; |
2390 | if ((vaddr & 7) != 0) | |
055ee297 | 2391 | SignalExceptionAddressStore(); |
f2b30012 AC |
2392 | else |
2393 | { | |
2394 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2395 | { | |
2396 | unsigned64 memval = 0; | |
2397 | unsigned64 memval1 = 0; | |
2398 | memval = op2; | |
2399 | if (LLBIT) | |
2400 | { | |
2401 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
2402 | } | |
2403 | GPR[(instruction >> 16) & 0x0000001F] = LLBIT; | |
2404 | } | |
2405 | } | |
2406 | } | |
2407 | } | |
2408 | ||
2409 | ||
2410 | 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD | |
2411 | "sd r<RT>, <OFFSET>(r<BASE>)" | |
2412 | *mipsIII: | |
2413 | *mipsIV: | |
23850e92 | 2414 | *vr5000: |
90ad43b2 AC |
2415 | // start-sanitize-vr5400 |
2416 | *vr5400: | |
2417 | // end-sanitize-vr5400 | |
f2b30012 AC |
2418 | // start-sanitize-r5900 |
2419 | *r5900: | |
2420 | // end-sanitize-r5900 | |
2421 | *r3900: | |
2422 | // start-sanitize-tx19 | |
2423 | *tx19: | |
2424 | // end-sanitize-tx19 | |
2425 | { | |
2426 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2427 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2428 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2429 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2430 | { |
49a76833 AC |
2431 | address_word vaddr = ((unsigned64)op1 + offset); |
2432 | address_word paddr; | |
f2b30012 AC |
2433 | int uncached; |
2434 | if ((vaddr & 7) != 0) | |
055ee297 | 2435 | SignalExceptionAddressStore(); |
f2b30012 AC |
2436 | else |
2437 | { | |
2438 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2439 | { | |
2440 | unsigned64 memval = 0; | |
2441 | unsigned64 memval1 = 0; | |
2442 | memval = op2; | |
2443 | { | |
2444 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
2445 | } | |
2446 | } | |
2447 | } | |
2448 | } | |
2449 | } | |
2450 | ||
2451 | ||
49a6eed5 | 2452 | 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz |
f2b30012 AC |
2453 | "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
2454 | *mipsII: | |
2455 | *mipsIII: | |
2456 | *mipsIV: | |
23850e92 | 2457 | *vr5000: |
90ad43b2 AC |
2458 | // start-sanitize-vr5400 |
2459 | *vr5400: | |
2460 | // end-sanitize-vr5400 | |
f2b30012 AC |
2461 | // start-sanitize-r5900 |
2462 | *r5900: | |
2463 | // end-sanitize-r5900 | |
2464 | *r3900: | |
2465 | // start-sanitize-tx19 | |
2466 | *tx19: | |
2467 | // end-sanitize-tx19 | |
2468 | { | |
2469 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2470 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2471 | int destreg = ((instruction >> 16) & 0x0000001F); | |
2472 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2473 | { |
49a76833 AC |
2474 | address_word vaddr = ((unsigned64)op1 + offset); |
2475 | address_word paddr; | |
f2b30012 AC |
2476 | int uncached; |
2477 | if ((vaddr & 7) != 0) | |
055ee297 | 2478 | SignalExceptionAddressStore(); |
f2b30012 AC |
2479 | else |
2480 | { | |
2481 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2482 | { | |
2483 | unsigned64 memval = 0; | |
2484 | unsigned64 memval1 = 0; | |
2485 | memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg); | |
2486 | { | |
2487 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
2488 | } | |
2489 | } | |
2490 | } | |
2491 | } | |
2492 | } | |
2493 | ||
2494 | ||
2495 | 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL | |
2496 | "sdl r<RT>, <OFFSET>(r<BASE>)" | |
2497 | *mipsIII: | |
2498 | *mipsIV: | |
23850e92 | 2499 | *vr5000: |
90ad43b2 AC |
2500 | // start-sanitize-vr5400 |
2501 | *vr5400: | |
2502 | // end-sanitize-vr5400 | |
f2b30012 AC |
2503 | // start-sanitize-r5900 |
2504 | *r5900: | |
2505 | // end-sanitize-r5900 | |
2506 | *r3900: | |
2507 | // start-sanitize-tx19 | |
2508 | *tx19: | |
2509 | // end-sanitize-tx19 | |
2510 | { | |
2511 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2512 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2513 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2514 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2515 | { |
49a76833 AC |
2516 | address_word vaddr = ((unsigned64)op1 + offset); |
2517 | address_word paddr; | |
f2b30012 AC |
2518 | int uncached; |
2519 | { | |
2520 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2521 | { | |
2522 | unsigned64 memval = 0; | |
2523 | unsigned64 memval1 = 0; | |
2524 | unsigned64 mask = 7; | |
2525 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
2526 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
2527 | int byte; | |
2528 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
2529 | byte = ((vaddr & mask) ^ bigend); | |
63be8feb | 2530 | if (!BigEndianMem) |
f2b30012 AC |
2531 | paddr &= ~mask; |
2532 | memval = (op2 >> (8 * (7 - byte))); | |
2533 | StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL); | |
2534 | } | |
2535 | } | |
2536 | } | |
2537 | } | |
2538 | ||
2539 | ||
2540 | 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR | |
2541 | "sdr r<RT>, <OFFSET>(r<BASE>)" | |
2542 | *mipsIII: | |
2543 | *mipsIV: | |
23850e92 | 2544 | *vr5000: |
90ad43b2 AC |
2545 | // start-sanitize-vr5400 |
2546 | *vr5400: | |
2547 | // end-sanitize-vr5400 | |
f2b30012 AC |
2548 | // start-sanitize-r5900 |
2549 | *r5900: | |
2550 | // end-sanitize-r5900 | |
2551 | *r3900: | |
2552 | // start-sanitize-tx19 | |
2553 | *tx19: | |
2554 | // end-sanitize-tx19 | |
2555 | { | |
23850e92 JL |
2556 | address_word paddr; |
2557 | int uncached; | |
2558 | unsigned64 memval; | |
2559 | unsigned64 mask = 7; | |
2560 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
2561 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
2562 | int byte; | |
2563 | address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET)); | |
2564 | AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL); | |
2565 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
2566 | if (BigEndianMem) | |
2567 | paddr &= ~mask; | |
2568 | byte = ((vaddr & mask) ^ bigend); | |
2569 | memval = (GPR[RT] << (byte * 8)); | |
2570 | StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,0,paddr,vaddr,isREAL); | |
f2b30012 AC |
2571 | } |
2572 | ||
2573 | ||
2574 | 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH | |
2575 | "sh r<RT>, <OFFSET>(r<BASE>)" | |
23850e92 JL |
2576 | *mipsI,mipsII,mipsIII,mipsIV: |
2577 | *vr5000: | |
90ad43b2 AC |
2578 | // start-sanitize-vr5400 |
2579 | *vr5400: | |
2580 | // end-sanitize-vr5400 | |
f2b30012 AC |
2581 | // start-sanitize-r5900 |
2582 | *r5900: | |
2583 | // end-sanitize-r5900 | |
2584 | *r3900: | |
2585 | // start-sanitize-tx19 | |
2586 | *tx19: | |
2587 | // end-sanitize-tx19 | |
2588 | { | |
2589 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2590 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2591 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2592 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2593 | { |
49a76833 AC |
2594 | address_word vaddr = ((unsigned64)op1 + offset); |
2595 | address_word paddr; | |
f2b30012 AC |
2596 | int uncached; |
2597 | if ((vaddr & 1) != 0) | |
055ee297 | 2598 | SignalExceptionAddressStore(); |
f2b30012 AC |
2599 | else |
2600 | { | |
2601 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2602 | { | |
2603 | unsigned64 memval = 0; | |
2604 | unsigned64 memval1 = 0; | |
2605 | unsigned64 mask = 0x7; | |
2606 | unsigned int shift = 1; | |
2607 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); | |
2608 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
2609 | unsigned int byte; | |
2610 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
2611 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
2612 | memval = ((unsigned64) op2 << (8 * byte)); | |
2613 | { | |
2614 | StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL); | |
2615 | } | |
2616 | } | |
2617 | } | |
2618 | } | |
2619 | } | |
2620 | ||
2621 | ||
055ee297 AC |
2622 | 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL |
2623 | "sll r<RD>, r<RT>, <SHIFT>" | |
23850e92 JL |
2624 | *mipsI,mipsII,mipsIII,mipsIV: |
2625 | *vr5000: | |
90ad43b2 AC |
2626 | // start-sanitize-vr5400 |
2627 | *vr5400: | |
2628 | // end-sanitize-vr5400 | |
f2b30012 AC |
2629 | // start-sanitize-r5900 |
2630 | *r5900: | |
2631 | // end-sanitize-r5900 | |
2632 | *r3900: | |
2633 | // start-sanitize-tx19 | |
2634 | *tx19: | |
2635 | // end-sanitize-tx19 | |
2636 | { | |
055ee297 AC |
2637 | int s = SHIFT; |
2638 | unsigned32 temp = (GPR[RT] << s); | |
2639 | GPR[RD] = EXTEND32 (temp); | |
f2b30012 AC |
2640 | } |
2641 | ||
2642 | ||
055ee297 | 2643 | 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV |
f2b30012 | 2644 | "sllv r<RD>, r<RT>, r<RS>" |
23850e92 JL |
2645 | *mipsI,mipsII,mipsIII,mipsIV: |
2646 | *vr5000: | |
90ad43b2 AC |
2647 | // start-sanitize-vr5400 |
2648 | *vr5400: | |
2649 | // end-sanitize-vr5400 | |
f2b30012 AC |
2650 | // start-sanitize-r5900 |
2651 | *r5900: | |
2652 | // end-sanitize-r5900 | |
2653 | *r3900: | |
2654 | // start-sanitize-tx19 | |
2655 | *tx19: | |
2656 | // end-sanitize-tx19 | |
2657 | { | |
055ee297 AC |
2658 | int s = MASKED (GPR[RS], 4, 0); |
2659 | unsigned32 temp = (GPR[RT] << s); | |
2660 | GPR[RD] = EXTEND32 (temp); | |
f2b30012 AC |
2661 | } |
2662 | ||
2663 | ||
2664 | 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT | |
2665 | "slt r<RD>, r<RS>, r<RT>" | |
23850e92 JL |
2666 | *mipsI,mipsII,mipsIII,mipsIV: |
2667 | *vr5000: | |
90ad43b2 AC |
2668 | // start-sanitize-vr5400 |
2669 | *vr5400: | |
2670 | // end-sanitize-vr5400 | |
f2b30012 AC |
2671 | // start-sanitize-r5900 |
2672 | *r5900: | |
2673 | // end-sanitize-r5900 | |
2674 | *r3900: | |
2675 | // start-sanitize-tx19 | |
2676 | *tx19: | |
2677 | // end-sanitize-tx19 | |
2678 | { | |
a94c5493 | 2679 | GPR[RD] = ((signed_word) GPR[RS] < (signed_word) GPR[RT]); |
f2b30012 AC |
2680 | } |
2681 | ||
2682 | ||
2683 | 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI | |
055ee297 | 2684 | "slti r<RT>, r<RS>, <IMMEDIATE>" |
23850e92 JL |
2685 | *mipsI,mipsII,mipsIII,mipsIV: |
2686 | *vr5000: | |
90ad43b2 AC |
2687 | // start-sanitize-vr5400 |
2688 | *vr5400: | |
2689 | // end-sanitize-vr5400 | |
f2b30012 AC |
2690 | // start-sanitize-r5900 |
2691 | *r5900: | |
2692 | // end-sanitize-r5900 | |
2693 | *r3900: | |
2694 | // start-sanitize-tx19 | |
2695 | *tx19: | |
2696 | // end-sanitize-tx19 | |
2697 | { | |
a94c5493 | 2698 | GPR[RT] = ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE)); |
f2b30012 AC |
2699 | } |
2700 | ||
2701 | ||
2702 | 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU | |
055ee297 | 2703 | "sltiu r<RT>, r<RS>, <IMMEDIATE>" |
23850e92 JL |
2704 | *mipsI,mipsII,mipsIII,mipsIV: |
2705 | *vr5000: | |
90ad43b2 AC |
2706 | // start-sanitize-vr5400 |
2707 | *vr5400: | |
2708 | // end-sanitize-vr5400 | |
f2b30012 AC |
2709 | // start-sanitize-r5900 |
2710 | *r5900: | |
2711 | // end-sanitize-r5900 | |
2712 | *r3900: | |
2713 | // start-sanitize-tx19 | |
2714 | *tx19: | |
2715 | // end-sanitize-tx19 | |
2716 | { | |
055ee297 | 2717 | GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE)); |
f2b30012 AC |
2718 | } |
2719 | ||
2720 | 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU | |
2721 | "sltu r<RD>, r<RS>, r<RT>" | |
23850e92 JL |
2722 | *mipsI,mipsII,mipsIII,mipsIV: |
2723 | *vr5000: | |
90ad43b2 AC |
2724 | // start-sanitize-vr5400 |
2725 | *vr5400: | |
2726 | // end-sanitize-vr5400 | |
f2b30012 AC |
2727 | // start-sanitize-r5900 |
2728 | *r5900: | |
2729 | // end-sanitize-r5900 | |
2730 | *r3900: | |
2731 | // start-sanitize-tx19 | |
2732 | *tx19: | |
2733 | // end-sanitize-tx19 | |
2734 | { | |
055ee297 | 2735 | GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]); |
f2b30012 AC |
2736 | } |
2737 | ||
2738 | ||
055ee297 AC |
2739 | 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA |
2740 | "sra r<RD>, r<RT>, <SHIFT>" | |
23850e92 JL |
2741 | *mipsI,mipsII,mipsIII,mipsIV: |
2742 | *vr5000: | |
90ad43b2 AC |
2743 | // start-sanitize-vr5400 |
2744 | *vr5400: | |
2745 | // end-sanitize-vr5400 | |
f2b30012 AC |
2746 | // start-sanitize-r5900 |
2747 | *r5900: | |
2748 | // end-sanitize-r5900 | |
2749 | *r3900: | |
2750 | // start-sanitize-tx19 | |
2751 | *tx19: | |
2752 | // end-sanitize-tx19 | |
2753 | { | |
055ee297 AC |
2754 | int s = SHIFT; |
2755 | signed32 temp = (signed32) GPR[RT] >> s; | |
2756 | GPR[RD] = EXTEND32 (temp); | |
f2b30012 AC |
2757 | } |
2758 | ||
2759 | ||
2760 | 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV | |
2761 | "srav r<RD>, r<RT>, r<RS>" | |
23850e92 JL |
2762 | *mipsI,mipsII,mipsIII,mipsIV: |
2763 | *vr5000: | |
90ad43b2 AC |
2764 | // start-sanitize-vr5400 |
2765 | *vr5400: | |
2766 | // end-sanitize-vr5400 | |
f2b30012 AC |
2767 | // start-sanitize-r5900 |
2768 | *r5900: | |
2769 | // end-sanitize-r5900 | |
2770 | *r3900: | |
2771 | // start-sanitize-tx19 | |
2772 | *tx19: | |
2773 | // end-sanitize-tx19 | |
2774 | { | |
055ee297 AC |
2775 | int s = MASKED (GPR[RS], 4, 0); |
2776 | signed32 temp = (signed32) GPR[RT] >> s; | |
2777 | GPR[RD] = EXTEND32 (temp); | |
f2b30012 AC |
2778 | } |
2779 | ||
2780 | ||
055ee297 AC |
2781 | 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL |
2782 | "srl r<RD>, r<RT>, <SHIFT>" | |
23850e92 JL |
2783 | *mipsI,mipsII,mipsIII,mipsIV: |
2784 | *vr5000: | |
90ad43b2 AC |
2785 | // start-sanitize-vr5400 |
2786 | *vr5400: | |
2787 | // end-sanitize-vr5400 | |
f2b30012 AC |
2788 | // start-sanitize-r5900 |
2789 | *r5900: | |
2790 | // end-sanitize-r5900 | |
2791 | *r3900: | |
2792 | // start-sanitize-tx19 | |
2793 | *tx19: | |
2794 | // end-sanitize-tx19 | |
2795 | { | |
055ee297 AC |
2796 | int s = SHIFT; |
2797 | unsigned32 temp = (unsigned32) GPR[RT] >> s; | |
2798 | GPR[RD] = EXTEND32 (temp); | |
f2b30012 AC |
2799 | } |
2800 | ||
2801 | ||
2802 | 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV | |
2803 | "srlv r<RD>, r<RT>, r<RS>" | |
23850e92 JL |
2804 | *mipsI,mipsII,mipsIII,mipsIV: |
2805 | *vr5000: | |
90ad43b2 AC |
2806 | // start-sanitize-vr5400 |
2807 | *vr5400: | |
2808 | // end-sanitize-vr5400 | |
f2b30012 AC |
2809 | // start-sanitize-r5900 |
2810 | *r5900: | |
2811 | // end-sanitize-r5900 | |
2812 | *r3900: | |
2813 | // start-sanitize-tx19 | |
2814 | *tx19: | |
2815 | // end-sanitize-tx19 | |
2816 | { | |
055ee297 AC |
2817 | int s = MASKED (GPR[RS], 4, 0); |
2818 | unsigned32 temp = (unsigned32) GPR[RT] >> s; | |
2819 | GPR[RD] = EXTEND32 (temp); | |
f2b30012 AC |
2820 | } |
2821 | ||
2822 | ||
2823 | 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB | |
2824 | "sub r<RD>, r<RS>, r<RT>" | |
23850e92 JL |
2825 | *mipsI,mipsII,mipsIII,mipsIV: |
2826 | *vr5000: | |
90ad43b2 AC |
2827 | // start-sanitize-vr5400 |
2828 | *vr5400: | |
2829 | // end-sanitize-vr5400 | |
f2b30012 AC |
2830 | // start-sanitize-r5900 |
2831 | *r5900: | |
2832 | // end-sanitize-r5900 | |
2833 | *r3900: | |
2834 | // start-sanitize-tx19 | |
2835 | *tx19: | |
2836 | // end-sanitize-tx19 | |
2837 | { | |
055ee297 AC |
2838 | ALU32_BEGIN (GPR[RS]); |
2839 | ALU32_SUB (GPR[RT]); | |
2840 | ALU32_END (GPR[RD]); | |
f2b30012 AC |
2841 | } |
2842 | ||
2843 | ||
2844 | 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU | |
2845 | "subu r<RD>, r<RS>, r<RT>" | |
23850e92 JL |
2846 | *mipsI,mipsII,mipsIII,mipsIV: |
2847 | *vr5000: | |
90ad43b2 AC |
2848 | // start-sanitize-vr5400 |
2849 | *vr5400: | |
2850 | // end-sanitize-vr5400 | |
f2b30012 AC |
2851 | // start-sanitize-r5900 |
2852 | *r5900: | |
2853 | // end-sanitize-r5900 | |
2854 | *r3900: | |
2855 | // start-sanitize-tx19 | |
2856 | *tx19: | |
2857 | // end-sanitize-tx19 | |
2858 | { | |
055ee297 | 2859 | GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]); |
f2b30012 AC |
2860 | } |
2861 | ||
2862 | ||
2863 | 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW | |
2864 | "sw r<RT>, <OFFSET>(r<BASE>)" | |
23850e92 JL |
2865 | *mipsI,mipsII,mipsIII,mipsIV: |
2866 | *vr5000: | |
90ad43b2 AC |
2867 | // start-sanitize-vr5400 |
2868 | *vr5400: | |
2869 | // end-sanitize-vr5400 | |
f2b30012 AC |
2870 | // start-sanitize-r5900 |
2871 | *r5900: | |
2872 | // end-sanitize-r5900 | |
2873 | *r3900: | |
2874 | // start-sanitize-tx19 | |
2875 | *tx19: | |
2876 | // end-sanitize-tx19 | |
2877 | { | |
2878 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2879 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2880 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2881 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2882 | { |
49a76833 AC |
2883 | address_word vaddr = ((unsigned64)op1 + offset); |
2884 | address_word paddr; | |
f2b30012 AC |
2885 | int uncached; |
2886 | if ((vaddr & 3) != 0) | |
055ee297 | 2887 | SignalExceptionAddressStore(); |
f2b30012 AC |
2888 | else |
2889 | { | |
2890 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2891 | { | |
2892 | unsigned64 memval = 0; | |
2893 | unsigned64 memval1 = 0; | |
2894 | unsigned64 mask = 0x7; | |
2895 | unsigned int byte; | |
2896 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
2897 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
2898 | memval = ((unsigned64) op2 << (8 * byte)); | |
2899 | { | |
2900 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
2901 | } | |
2902 | } | |
2903 | } | |
2904 | } | |
2905 | } | |
2906 | ||
2907 | ||
085c1cb9 | 2908 | 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz |
f2b30012 | 2909 | "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)" |
23850e92 JL |
2910 | *mipsI,mipsII,mipsIII,mipsIV: |
2911 | *vr5000: | |
90ad43b2 AC |
2912 | // start-sanitize-vr5400 |
2913 | *vr5400: | |
2914 | // end-sanitize-vr5400 | |
f2b30012 AC |
2915 | // start-sanitize-r5900 |
2916 | *r5900: | |
2917 | // end-sanitize-r5900 | |
2918 | *r3900: | |
2919 | // start-sanitize-tx19 | |
2920 | *tx19: | |
2921 | // end-sanitize-tx19 | |
2922 | { | |
2923 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2924 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2925 | int destreg = ((instruction >> 16) & 0x0000001F); | |
2926 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2927 | { |
49a76833 AC |
2928 | address_word vaddr = ((unsigned64)op1 + offset); |
2929 | address_word paddr; | |
f2b30012 AC |
2930 | int uncached; |
2931 | if ((vaddr & 3) != 0) | |
055ee297 | 2932 | SignalExceptionAddressStore(); |
f2b30012 AC |
2933 | else |
2934 | { | |
2935 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2936 | { | |
2937 | unsigned64 memval = 0; | |
2938 | unsigned64 memval1 = 0; | |
2939 | unsigned64 mask = 0x7; | |
2940 | unsigned int byte; | |
2941 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
2942 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
2943 | memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte)); | |
2944 | { | |
2945 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
2946 | } | |
2947 | } | |
2948 | } | |
2949 | } | |
2950 | } | |
2951 | ||
2952 | ||
2953 | 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL | |
2954 | "swl r<RT>, <OFFSET>(r<BASE>)" | |
23850e92 JL |
2955 | *mipsI,mipsII,mipsIII,mipsIV: |
2956 | *vr5000: | |
90ad43b2 AC |
2957 | // start-sanitize-vr5400 |
2958 | *vr5400: | |
2959 | // end-sanitize-vr5400 | |
f2b30012 AC |
2960 | // start-sanitize-r5900 |
2961 | *r5900: | |
2962 | // end-sanitize-r5900 | |
2963 | *r3900: | |
2964 | // start-sanitize-tx19 | |
2965 | *tx19: | |
2966 | // end-sanitize-tx19 | |
2967 | { | |
2968 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
2969 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
2970 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
2971 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 2972 | { |
49a76833 AC |
2973 | address_word vaddr = ((unsigned64)op1 + offset); |
2974 | address_word paddr; | |
f2b30012 AC |
2975 | int uncached; |
2976 | { | |
2977 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
2978 | { | |
2979 | unsigned64 memval = 0; | |
2980 | unsigned64 memval1 = 0; | |
2981 | unsigned64 mask = 3; | |
2982 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
2983 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
2984 | int byte; | |
2985 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
2986 | byte = ((vaddr & mask) ^ bigend); | |
63be8feb | 2987 | if (!BigEndianMem) |
f2b30012 AC |
2988 | paddr &= ~mask; |
2989 | memval = (op2 >> (8 * (3 - byte))); | |
2990 | if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { | |
2991 | memval <<= 32; | |
2992 | } | |
2993 | StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL); | |
2994 | } | |
2995 | } | |
2996 | } | |
2997 | } | |
2998 | ||
2999 | ||
3000 | 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR | |
3001 | "swr r<RT>, <OFFSET>(r<BASE>)" | |
23850e92 JL |
3002 | *mipsI,mipsII,mipsIII,mipsIV: |
3003 | *vr5000: | |
90ad43b2 AC |
3004 | // start-sanitize-vr5400 |
3005 | *vr5400: | |
3006 | // end-sanitize-vr5400 | |
f2b30012 AC |
3007 | // start-sanitize-r5900 |
3008 | *r5900: | |
3009 | // end-sanitize-r5900 | |
3010 | *r3900: | |
3011 | // start-sanitize-tx19 | |
3012 | *tx19: | |
3013 | // end-sanitize-tx19 | |
3014 | { | |
23850e92 JL |
3015 | unsigned64 memval = 0; |
3016 | unsigned64 mask = 3; | |
3017 | unsigned int reverse = (ReverseEndian ? mask : 0); | |
3018 | unsigned int bigend = (BigEndianCPU ? mask : 0); | |
3019 | int byte; | |
3020 | address_word paddr; | |
3021 | int uncached; | |
3022 | address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET)); | |
3023 | AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL); | |
3024 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); | |
3025 | if (BigEndianMem) | |
3026 | paddr &= ~mask; | |
3027 | byte = ((vaddr & mask) ^ bigend); | |
3028 | memval = (GPR[RT] << (byte * 8)); | |
3029 | if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) | |
3030 | memval <<= 32; | |
3031 | StoreMemory(uncached,(AccessLength_WORD - byte),memval,0,paddr,vaddr,isREAL); | |
f2b30012 AC |
3032 | } |
3033 | ||
3034 | ||
3035 | 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC | |
3036 | "sync":STYPE == 0 | |
3037 | "sync <STYPE>" | |
3038 | *mipsII: | |
3039 | *mipsIII: | |
3040 | *mipsIV: | |
23850e92 | 3041 | *vr5000: |
90ad43b2 AC |
3042 | // start-sanitize-vr5400 |
3043 | *vr5400: | |
3044 | // end-sanitize-vr5400 | |
f2b30012 AC |
3045 | // start-sanitize-r5900 |
3046 | *r5900: | |
3047 | // end-sanitize-r5900 | |
3048 | *r3900: | |
3049 | // start-sanitize-tx19 | |
3050 | *tx19: | |
3051 | // end-sanitize-tx19 | |
3052 | { | |
085c1cb9 | 3053 | SyncOperation (STYPE); |
f2b30012 AC |
3054 | } |
3055 | ||
3056 | ||
3057 | 000000,20.CODE,001100:SPECIAL:32::SYSCALL | |
3058 | "syscall <CODE>" | |
23850e92 JL |
3059 | *mipsI,mipsII,mipsIII,mipsIV: |
3060 | *vr5000: | |
90ad43b2 AC |
3061 | // start-sanitize-vr5400 |
3062 | *vr5400: | |
3063 | // end-sanitize-vr5400 | |
f2b30012 AC |
3064 | // start-sanitize-r5900 |
3065 | *r5900: | |
3066 | // end-sanitize-r5900 | |
3067 | *r3900: | |
3068 | // start-sanitize-tx19 | |
3069 | *tx19: | |
3070 | // end-sanitize-tx19 | |
3071 | { | |
055ee297 | 3072 | SignalException(SystemCall, instruction_0); |
f2b30012 AC |
3073 | } |
3074 | ||
3075 | ||
3076 | 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ | |
3077 | "teq r<RS>, r<RT>" | |
3078 | *mipsII: | |
3079 | *mipsIII: | |
3080 | *mipsIV: | |
23850e92 | 3081 | *vr5000: |
90ad43b2 AC |
3082 | // start-sanitize-vr5400 |
3083 | *vr5400: | |
3084 | // end-sanitize-vr5400 | |
f2b30012 AC |
3085 | // start-sanitize-r5900 |
3086 | *r5900: | |
3087 | // end-sanitize-r5900 | |
3088 | *r3900: | |
3089 | // start-sanitize-tx19 | |
3090 | *tx19: | |
3091 | // end-sanitize-tx19 | |
3092 | { | |
a94c5493 | 3093 | if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) |
055ee297 | 3094 | SignalException(Trap, instruction_0); |
f2b30012 AC |
3095 | } |
3096 | ||
3097 | ||
3098 | 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI | |
3099 | "teqi r<RS>, <IMMEDIATE>" | |
3100 | *mipsII: | |
3101 | *mipsIII: | |
3102 | *mipsIV: | |
23850e92 | 3103 | *vr5000: |
90ad43b2 AC |
3104 | // start-sanitize-vr5400 |
3105 | *vr5400: | |
3106 | // end-sanitize-vr5400 | |
f2b30012 AC |
3107 | // start-sanitize-r5900 |
3108 | *r5900: | |
3109 | // end-sanitize-r5900 | |
3110 | *r3900: | |
3111 | // start-sanitize-tx19 | |
3112 | *tx19: | |
3113 | // end-sanitize-tx19 | |
3114 | { | |
a94c5493 | 3115 | if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE)) |
055ee297 | 3116 | SignalException(Trap, instruction_0); |
f2b30012 AC |
3117 | } |
3118 | ||
3119 | ||
3120 | 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE | |
3121 | "tge r<RS>, r<RT>" | |
3122 | *mipsII: | |
3123 | *mipsIII: | |
3124 | *mipsIV: | |
23850e92 | 3125 | *vr5000: |
90ad43b2 AC |
3126 | // start-sanitize-vr5400 |
3127 | *vr5400: | |
3128 | // end-sanitize-vr5400 | |
f2b30012 AC |
3129 | // start-sanitize-r5900 |
3130 | *r5900: | |
3131 | // end-sanitize-r5900 | |
3132 | *r3900: | |
3133 | // start-sanitize-tx19 | |
3134 | *tx19: | |
3135 | // end-sanitize-tx19 | |
3136 | { | |
a94c5493 | 3137 | if ((signed_word) GPR[RS] >= (signed_word) GPR[RT]) |
055ee297 | 3138 | SignalException(Trap, instruction_0); |
f2b30012 AC |
3139 | } |
3140 | ||
3141 | ||
3142 | 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI | |
3143 | "tgei r<RS>, <IMMEDIATE>" | |
3144 | *mipsII: | |
3145 | *mipsIII: | |
3146 | *mipsIV: | |
23850e92 | 3147 | *vr5000: |
90ad43b2 AC |
3148 | // start-sanitize-vr5400 |
3149 | *vr5400: | |
3150 | // end-sanitize-vr5400 | |
f2b30012 AC |
3151 | // start-sanitize-r5900 |
3152 | *r5900: | |
3153 | // end-sanitize-r5900 | |
3154 | *r3900: | |
3155 | // start-sanitize-tx19 | |
3156 | *tx19: | |
3157 | // end-sanitize-tx19 | |
3158 | { | |
a94c5493 | 3159 | if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE)) |
055ee297 | 3160 | SignalException(Trap, instruction_0); |
f2b30012 AC |
3161 | } |
3162 | ||
3163 | ||
3164 | 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU | |
3165 | "tgeiu r<RS>, <IMMEDIATE>" | |
3166 | *mipsII: | |
3167 | *mipsIII: | |
3168 | *mipsIV: | |
23850e92 | 3169 | *vr5000: |
90ad43b2 AC |
3170 | // start-sanitize-vr5400 |
3171 | *vr5400: | |
3172 | // end-sanitize-vr5400 | |
f2b30012 AC |
3173 | // start-sanitize-r5900 |
3174 | *r5900: | |
3175 | // end-sanitize-r5900 | |
3176 | *r3900: | |
3177 | // start-sanitize-tx19 | |
3178 | *tx19: | |
3179 | // end-sanitize-tx19 | |
3180 | { | |
055ee297 AC |
3181 | if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE)) |
3182 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3183 | } |
3184 | ||
3185 | ||
3186 | 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU | |
3187 | "tgeu r<RS>, r<RT>" | |
3188 | *mipsII: | |
3189 | *mipsIII: | |
3190 | *mipsIV: | |
23850e92 | 3191 | *vr5000: |
90ad43b2 AC |
3192 | // start-sanitize-vr5400 |
3193 | *vr5400: | |
3194 | // end-sanitize-vr5400 | |
f2b30012 AC |
3195 | // start-sanitize-r5900 |
3196 | *r5900: | |
3197 | // end-sanitize-r5900 | |
3198 | *r3900: | |
3199 | // start-sanitize-tx19 | |
3200 | *tx19: | |
3201 | // end-sanitize-tx19 | |
3202 | { | |
055ee297 AC |
3203 | if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT]) |
3204 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3205 | } |
3206 | ||
3207 | ||
3208 | 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT | |
3209 | "tlt r<RS>, r<RT>" | |
3210 | *mipsII: | |
3211 | *mipsIII: | |
3212 | *mipsIV: | |
23850e92 | 3213 | *vr5000: |
90ad43b2 AC |
3214 | // start-sanitize-vr5400 |
3215 | *vr5400: | |
3216 | // end-sanitize-vr5400 | |
f2b30012 AC |
3217 | // start-sanitize-r5900 |
3218 | *r5900: | |
3219 | // end-sanitize-r5900 | |
3220 | *r3900: | |
3221 | // start-sanitize-tx19 | |
3222 | *tx19: | |
3223 | // end-sanitize-tx19 | |
3224 | { | |
a94c5493 | 3225 | if ((signed_word) GPR[RS] < (signed_word) GPR[RT]) |
055ee297 | 3226 | SignalException(Trap, instruction_0); |
f2b30012 AC |
3227 | } |
3228 | ||
3229 | ||
3230 | 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI | |
3231 | "tlti r<RS>, <IMMEDIATE>" | |
3232 | *mipsII: | |
3233 | *mipsIII: | |
3234 | *mipsIV: | |
23850e92 | 3235 | *vr5000: |
90ad43b2 AC |
3236 | // start-sanitize-vr5400 |
3237 | *vr5400: | |
3238 | // end-sanitize-vr5400 | |
f2b30012 AC |
3239 | // start-sanitize-r5900 |
3240 | *r5900: | |
3241 | // end-sanitize-r5900 | |
3242 | *r3900: | |
3243 | // start-sanitize-tx19 | |
3244 | *tx19: | |
3245 | // end-sanitize-tx19 | |
3246 | { | |
a94c5493 | 3247 | if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE)) |
055ee297 | 3248 | SignalException(Trap, instruction_0); |
f2b30012 AC |
3249 | } |
3250 | ||
3251 | ||
3252 | 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU | |
3253 | "tltiu r<RS>, <IMMEDIATE>" | |
3254 | *mipsII: | |
3255 | *mipsIII: | |
3256 | *mipsIV: | |
23850e92 | 3257 | *vr5000: |
90ad43b2 AC |
3258 | // start-sanitize-vr5400 |
3259 | *vr5400: | |
3260 | // end-sanitize-vr5400 | |
f2b30012 AC |
3261 | // start-sanitize-r5900 |
3262 | *r5900: | |
3263 | // end-sanitize-r5900 | |
3264 | *r3900: | |
3265 | // start-sanitize-tx19 | |
3266 | *tx19: | |
3267 | // end-sanitize-tx19 | |
3268 | { | |
055ee297 AC |
3269 | if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE)) |
3270 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3271 | } |
3272 | ||
3273 | ||
3274 | 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU | |
3275 | "tltu r<RS>, r<RT>" | |
3276 | *mipsII: | |
3277 | *mipsIII: | |
3278 | *mipsIV: | |
23850e92 | 3279 | *vr5000: |
90ad43b2 AC |
3280 | // start-sanitize-vr5400 |
3281 | *vr5400: | |
3282 | // end-sanitize-vr5400 | |
f2b30012 AC |
3283 | // start-sanitize-r5900 |
3284 | *r5900: | |
3285 | // end-sanitize-r5900 | |
3286 | *r3900: | |
3287 | // start-sanitize-tx19 | |
3288 | *tx19: | |
3289 | // end-sanitize-tx19 | |
3290 | { | |
055ee297 AC |
3291 | if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]) |
3292 | SignalException(Trap, instruction_0); | |
f2b30012 AC |
3293 | } |
3294 | ||
3295 | ||
3296 | 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE | |
3297 | "tne r<RS>, r<RT>" | |
3298 | *mipsII: | |
3299 | *mipsIII: | |
3300 | *mipsIV: | |
23850e92 | 3301 | *vr5000: |
90ad43b2 AC |
3302 | // start-sanitize-vr5400 |
3303 | *vr5400: | |
3304 | // end-sanitize-vr5400 | |
f2b30012 AC |
3305 | // start-sanitize-r5900 |
3306 | *r5900: | |
3307 | // end-sanitize-r5900 | |
3308 | *r3900: | |
3309 | // start-sanitize-tx19 | |
3310 | *tx19: | |
3311 | // end-sanitize-tx19 | |
3312 | { | |
a94c5493 | 3313 | if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) |
055ee297 | 3314 | SignalException(Trap, instruction_0); |
f2b30012 AC |
3315 | } |
3316 | ||
3317 | ||
3318 | 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI | |
3319 | "tne r<RS>, <IMMEDIATE>" | |
3320 | *mipsII: | |
3321 | *mipsIII: | |
3322 | *mipsIV: | |
23850e92 | 3323 | *vr5000: |
90ad43b2 AC |
3324 | // start-sanitize-vr5400 |
3325 | *vr5400: | |
3326 | // end-sanitize-vr5400 | |
f2b30012 AC |
3327 | // start-sanitize-r5900 |
3328 | *r5900: | |
3329 | // end-sanitize-r5900 | |
3330 | *r3900: | |
3331 | // start-sanitize-tx19 | |
3332 | *tx19: | |
3333 | // end-sanitize-tx19 | |
3334 | { | |
a94c5493 | 3335 | if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE)) |
055ee297 | 3336 | SignalException(Trap, instruction_0); |
f2b30012 AC |
3337 | } |
3338 | ||
3339 | ||
3340 | 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR | |
3341 | "xor r<RD>, r<RS>, r<RT>" | |
23850e92 JL |
3342 | *mipsI,mipsII,mipsIII,mipsIV: |
3343 | *vr5000: | |
90ad43b2 AC |
3344 | // start-sanitize-vr5400 |
3345 | *vr5400: | |
3346 | // end-sanitize-vr5400 | |
f2b30012 AC |
3347 | // start-sanitize-r5900 |
3348 | *r5900: | |
3349 | // end-sanitize-r5900 | |
3350 | *r3900: | |
3351 | // start-sanitize-tx19 | |
3352 | *tx19: | |
3353 | // end-sanitize-tx19 | |
3354 | { | |
055ee297 | 3355 | GPR[RD] = GPR[RS] ^ GPR[RT]; |
f2b30012 AC |
3356 | } |
3357 | ||
3358 | ||
3359 | 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI | |
055ee297 | 3360 | "xori r<RT>, r<RS>, <IMMEDIATE>" |
23850e92 JL |
3361 | *mipsI,mipsII,mipsIII,mipsIV: |
3362 | *vr5000: | |
90ad43b2 AC |
3363 | // start-sanitize-vr5400 |
3364 | *vr5400: | |
3365 | // end-sanitize-vr5400 | |
f2b30012 AC |
3366 | // start-sanitize-r5900 |
3367 | *r5900: | |
3368 | // end-sanitize-r5900 | |
3369 | *r3900: | |
3370 | // start-sanitize-tx19 | |
3371 | *tx19: | |
3372 | // end-sanitize-tx19 | |
3373 | { | |
055ee297 | 3374 | GPR[RT] = GPR[RS] ^ IMMEDIATE; |
f2b30012 AC |
3375 | } |
3376 | ||
3377 | \f | |
3378 | // | |
3379 | // MIPS Architecture: | |
3380 | // | |
3381 | // FPU Instruction Set (COP1 & COP1X) | |
3382 | // | |
3383 | ||
3384 | ||
89d09738 | 3385 | :%s::::FMT:int fmt |
055ee297 AC |
3386 | { |
3387 | switch (fmt) | |
3388 | { | |
3389 | case fmt_single: return "s"; | |
3390 | case fmt_double: return "d"; | |
3391 | case fmt_word: return "w"; | |
3392 | case fmt_long: return "l"; | |
3393 | default: return "?"; | |
3394 | } | |
3395 | } | |
3396 | ||
030843d7 AC |
3397 | :%s::::X:int x |
3398 | { | |
3399 | switch (x) | |
3400 | { | |
3401 | case 0: return "f"; | |
3402 | case 1: return "t"; | |
3403 | default: return "?"; | |
3404 | } | |
3405 | } | |
3406 | ||
89d09738 | 3407 | :%s::::TF:int tf |
055ee297 AC |
3408 | { |
3409 | if (tf) | |
3410 | return "t"; | |
3411 | else | |
3412 | return "f"; | |
3413 | } | |
3414 | ||
89d09738 | 3415 | :%s::::ND:int nd |
055ee297 AC |
3416 | { |
3417 | if (nd) | |
3418 | return "l"; | |
3419 | else | |
3420 | return ""; | |
3421 | } | |
3422 | ||
89d09738 | 3423 | :%s::::COND:int cond |
055ee297 AC |
3424 | { |
3425 | switch (cond) | |
3426 | { | |
3427 | case 00: return "f"; | |
3428 | case 01: return "un"; | |
3429 | case 02: return "eq"; | |
3430 | case 03: return "ueq"; | |
3431 | case 04: return "olt"; | |
3432 | case 05: return "ult"; | |
3433 | case 06: return "ole"; | |
3434 | case 07: return "ule"; | |
3435 | case 010: return "sf"; | |
3436 | case 011: return "ngle"; | |
3437 | case 012: return "seq"; | |
3438 | case 013: return "ngl"; | |
3439 | case 014: return "lt"; | |
3440 | case 015: return "nge"; | |
3441 | case 016: return "le"; | |
3442 | case 017: return "ngt"; | |
3443 | default: return "?"; | |
3444 | } | |
3445 | } | |
3446 | ||
3447 | ||
f2b30012 AC |
3448 | 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt |
3449 | "abs.%s<FMT> f<FD>, f<FS>" | |
23850e92 JL |
3450 | *mipsI,mipsII,mipsIII,mipsIV: |
3451 | *vr5000: | |
90ad43b2 AC |
3452 | // start-sanitize-vr5400 |
3453 | *vr5400: | |
3454 | // end-sanitize-vr5400 | |
f2b30012 AC |
3455 | *r3900: |
3456 | // start-sanitize-tx19 | |
3457 | *tx19: | |
3458 | // end-sanitize-tx19 | |
3459 | { | |
3460 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3461 | int destreg = ((instruction >> 6) & 0x0000001F); |
3462 | int fs = ((instruction >> 11) & 0x0000001F); | |
3463 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3464 | { |
3465 | if ((format != fmt_single) && (format != fmt_double)) | |
3466 | SignalException(ReservedInstruction,instruction); | |
3467 | else | |
3468 | StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format)); | |
3469 | } | |
3470 | } | |
3471 | ||
3472 | ||
055ee297 | 3473 | |
a48e8c8d | 3474 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt |
f2b30012 | 3475 | "add.%s<FMT> f<FD>, f<FS>, f<FT>" |
23850e92 JL |
3476 | *mipsI,mipsII,mipsIII,mipsIV: |
3477 | *vr5000: | |
90ad43b2 AC |
3478 | // start-sanitize-vr5400 |
3479 | *vr5400: | |
3480 | // end-sanitize-vr5400 | |
f2b30012 AC |
3481 | *r3900: |
3482 | // start-sanitize-tx19 | |
3483 | *tx19: | |
3484 | // end-sanitize-tx19 | |
3485 | { | |
3486 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3487 | int destreg = ((instruction >> 6) & 0x0000001F); |
3488 | int fs = ((instruction >> 11) & 0x0000001F); | |
3489 | int ft = ((instruction >> 16) & 0x0000001F); | |
3490 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3491 | { |
3492 | if ((format != fmt_single) && (format != fmt_double)) | |
055ee297 | 3493 | SignalException(ReservedInstruction, instruction); |
f2b30012 AC |
3494 | else |
3495 | StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format)); | |
3496 | } | |
3497 | } | |
3498 | ||
3499 | ||
23850e92 | 3500 | |
f2b30012 AC |
3501 | // BC1F |
3502 | // BC1FL | |
3503 | // BC1T | |
3504 | // BC1TL | |
23850e92 JL |
3505 | |
3506 | 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1 | |
3507 | "bc1%s<TF>%s<ND> <OFFSET>" | |
3508 | *mipsI,mipsII,mipsIII: | |
3509 | // start-sanitize-r5900 | |
3510 | *r5900: | |
3511 | // end-sanitize-r5900 | |
3512 | { | |
a48e8c8d | 3513 | TRACE_BRANCH_INPUT (PREVCOC1()); |
23850e92 JL |
3514 | if (PREVCOC1() == TF) |
3515 | { | |
a48e8c8d AC |
3516 | address_word dest = NIA + (EXTEND16 (OFFSET) << 2); |
3517 | TRACE_BRANCH_RESULT (dest); | |
3518 | DELAY_SLOT (dest); | |
23850e92 JL |
3519 | } |
3520 | else if (ND) | |
3521 | { | |
a48e8c8d | 3522 | TRACE_BRANCH_RESULT (0); |
23850e92 JL |
3523 | NULLIFY_NEXT_INSTRUCTION (); |
3524 | } | |
a48e8c8d AC |
3525 | else |
3526 | { | |
3527 | TRACE_BRANCH_RESULT (NIA); | |
3528 | } | |
23850e92 JL |
3529 | } |
3530 | ||
055ee297 AC |
3531 | 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1 |
3532 | "bc1%s<TF>%s<ND> <OFFSET>":CC == 0 | |
3533 | "bc1%s<TF>%s<ND> <CC>, <OFFSET>" | |
f2b30012 | 3534 | *mipsIV: |
23850e92 | 3535 | *vr5000: |
90ad43b2 AC |
3536 | // start-sanitize-vr5400 |
3537 | *vr5400: | |
3538 | // end-sanitize-vr5400 | |
f2b30012 AC |
3539 | *r3900: |
3540 | // start-sanitize-tx19 | |
3541 | *tx19: | |
3542 | // end-sanitize-tx19 | |
3543 | { | |
23850e92 JL |
3544 | if (GETFCC(CC) == TF) |
3545 | { | |
3546 | DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2)); | |
3547 | } | |
3548 | else if (ND) | |
3549 | { | |
3550 | NULLIFY_NEXT_INSTRUCTION (); | |
f2b30012 | 3551 | } |
f2b30012 AC |
3552 | } |
3553 | ||
3554 | ||
23850e92 JL |
3555 | |
3556 | // C.EQ.S | |
3557 | // C.EQ.D | |
3558 | // ... | |
3559 | ||
3560 | :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn | |
3561 | { | |
3562 | if ((fmt != fmt_single) && (fmt != fmt_double)) | |
3563 | SignalException (ReservedInstruction, insn); | |
3564 | else | |
3565 | { | |
3566 | int less; | |
3567 | int equal; | |
3568 | int unordered; | |
3569 | int condition; | |
3570 | unsigned64 ofs = ValueFPR (fs, fmt); | |
3571 | unsigned64 oft = ValueFPR (ft, fmt); | |
3572 | if (NaN (ofs, fmt) || NaN (oft, fmt)) | |
3573 | { | |
3574 | if (FCSR & FP_ENABLE (IO)) | |
3575 | { | |
3576 | FCSR |= FP_CAUSE (IO); | |
3577 | SignalExceptionFPE (); | |
3578 | } | |
3579 | less = 0; | |
3580 | equal = 0; | |
3581 | unordered = 1; | |
3582 | } | |
3583 | else | |
3584 | { | |
3585 | less = Less (ofs, oft, fmt); | |
3586 | equal = Equal (ofs, oft, fmt); | |
3587 | unordered = 0; | |
3588 | } | |
3589 | condition = (((cond & (1 << 2)) && less) | |
3590 | || ((cond & (1 << 1)) && equal) | |
3591 | || ((cond & (1 << 0)) && unordered)); | |
3592 | SETFCC (cc, condition); | |
3593 | } | |
3594 | } | |
3595 | ||
3596 | 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt | |
3597 | *mipsI,mipsII,mipsIII: | |
3598 | "c.%s<COND>.%s<FMT> f<FS>, f<FT>": | |
3599 | { | |
3600 | do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0); | |
3601 | } | |
3602 | ||
f2b30012 AC |
3603 | 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt |
3604 | "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0 | |
3605 | "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>" | |
f2b30012 | 3606 | *mipsIV: |
23850e92 | 3607 | *vr5000: |
90ad43b2 AC |
3608 | // start-sanitize-vr5400 |
3609 | *vr5400: | |
3610 | // end-sanitize-vr5400 | |
f2b30012 AC |
3611 | *r3900: |
3612 | // start-sanitize-tx19 | |
3613 | *tx19: | |
3614 | // end-sanitize-tx19 | |
3615 | { | |
23850e92 | 3616 | do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0); |
f2b30012 AC |
3617 | } |
3618 | ||
3619 | ||
3620 | 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt | |
3621 | "ceil.l.%s<FMT> f<FD>, f<FS>" | |
3622 | *mipsIII: | |
3623 | *mipsIV: | |
23850e92 | 3624 | *vr5000: |
90ad43b2 AC |
3625 | // start-sanitize-vr5400 |
3626 | *vr5400: | |
3627 | // end-sanitize-vr5400 | |
f2b30012 AC |
3628 | // start-sanitize-r5900 |
3629 | *r5900: | |
3630 | // end-sanitize-r5900 | |
3631 | *r3900: | |
3632 | // start-sanitize-tx19 | |
3633 | *tx19: | |
3634 | // end-sanitize-tx19 | |
3635 | { | |
3636 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3637 | int destreg = ((instruction >> 6) & 0x0000001F); |
3638 | int fs = ((instruction >> 11) & 0x0000001F); | |
3639 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3640 | { |
3641 | if ((format != fmt_single) && (format != fmt_double)) | |
3642 | SignalException(ReservedInstruction,instruction); | |
3643 | else | |
3644 | StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long)); | |
3645 | } | |
3646 | } | |
3647 | ||
3648 | ||
3649 | 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W | |
3650 | *mipsII: | |
3651 | *mipsIII: | |
3652 | *mipsIV: | |
23850e92 | 3653 | *vr5000: |
90ad43b2 AC |
3654 | // start-sanitize-vr5400 |
3655 | *vr5400: | |
3656 | // end-sanitize-vr5400 | |
f2b30012 AC |
3657 | // start-sanitize-r5900 |
3658 | *r5900: | |
3659 | // end-sanitize-r5900 | |
3660 | *r3900: | |
3661 | // start-sanitize-tx19 | |
3662 | *tx19: | |
3663 | // end-sanitize-tx19 | |
3664 | { | |
3665 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3666 | int destreg = ((instruction >> 6) & 0x0000001F); |
3667 | int fs = ((instruction >> 11) & 0x0000001F); | |
3668 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3669 | { |
3670 | if ((format != fmt_single) && (format != fmt_double)) | |
3671 | SignalException(ReservedInstruction,instruction); | |
3672 | else | |
3673 | StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word)); | |
3674 | } | |
3675 | } | |
3676 | ||
3677 | ||
3678 | // CFC1 | |
3679 | // CTC1 | |
030843d7 AC |
3680 | 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1 |
3681 | "c%s<X>c1 r<RT>, f<FS>" | |
f2b30012 AC |
3682 | *mipsI: |
3683 | *mipsII: | |
3684 | *mipsIII: | |
030843d7 AC |
3685 | { |
3686 | if (X) | |
3687 | { | |
3688 | if (FS == 0) | |
3689 | PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT])); | |
3690 | else if (FS == 31) | |
3691 | PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT])); | |
3692 | /* else NOP */ | |
3693 | PENDING_FILL(COCIDX,0); /* special case */ | |
3694 | } | |
3695 | else | |
3696 | { /* control from */ | |
3697 | if (FS == 0) | |
3698 | PENDING_FILL(RT,SIGNEXTEND(FCR0,32)); | |
3699 | else if (FS == 31) | |
3700 | PENDING_FILL(RT,SIGNEXTEND(FCR31,32)); | |
3701 | /* else NOP */ | |
3702 | } | |
3703 | } | |
3704 | 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1 | |
3705 | "c%s<X>c1 r<RT>, f<FS>" | |
f2b30012 | 3706 | *mipsIV: |
23850e92 | 3707 | *vr5000: |
90ad43b2 AC |
3708 | // start-sanitize-vr5400 |
3709 | *vr5400: | |
3710 | // end-sanitize-vr5400 | |
f2b30012 AC |
3711 | // start-sanitize-r5900 |
3712 | *r5900: | |
3713 | // end-sanitize-r5900 | |
3714 | *r3900: | |
3715 | // start-sanitize-tx19 | |
3716 | *tx19: | |
3717 | // end-sanitize-tx19 | |
3718 | { | |
030843d7 AC |
3719 | if (X) |
3720 | { | |
f89c0689 AC |
3721 | /* control to */ |
3722 | TRACE_ALU_INPUT1 (GPR[RT]); | |
030843d7 | 3723 | if (FS == 0) |
f89c0689 AC |
3724 | { |
3725 | FCR0 = VL4_8(GPR[RT]); | |
3726 | TRACE_ALU_RESULT (FCR0); | |
3727 | } | |
030843d7 | 3728 | else if (FS == 31) |
f89c0689 AC |
3729 | { |
3730 | FCR31 = VL4_8(GPR[RT]); | |
3731 | SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0)); | |
3732 | TRACE_ALU_RESULT (FCR31); | |
3733 | } | |
3734 | else | |
3735 | { | |
3736 | TRACE_ALU_RESULT0 (); | |
3737 | } | |
030843d7 | 3738 | /* else NOP */ |
030843d7 AC |
3739 | } |
3740 | else | |
3741 | { /* control from */ | |
3742 | if (FS == 0) | |
f89c0689 AC |
3743 | { |
3744 | TRACE_ALU_INPUT1 (FCR0); | |
3745 | GPR[RT] = SIGNEXTEND (FCR0, 32); | |
3746 | } | |
030843d7 | 3747 | else if (FS == 31) |
f89c0689 AC |
3748 | { |
3749 | TRACE_ALU_INPUT1 (FCR31); | |
3750 | GPR[RT] = SIGNEXTEND (FCR31, 32); | |
3751 | } | |
3752 | TRACE_ALU_RESULT (GPR[RT]); | |
030843d7 | 3753 | /* else NOP */ |
f2b30012 | 3754 | } |
f2b30012 AC |
3755 | } |
3756 | ||
3757 | ||
3758 | // | |
3759 | // FIXME: Does not correctly differentiate between mips* | |
3760 | // | |
3761 | 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt | |
3762 | "cvt.d.%s<FMT> f<FD>, f<FS>" | |
23850e92 JL |
3763 | *mipsI,mipsII,mipsIII,mipsIV: |
3764 | *vr5000: | |
90ad43b2 AC |
3765 | // start-sanitize-vr5400 |
3766 | *vr5400: | |
3767 | // end-sanitize-vr5400 | |
f2b30012 AC |
3768 | *r3900: |
3769 | // start-sanitize-tx19 | |
3770 | *tx19: | |
3771 | // end-sanitize-tx19 | |
3772 | { | |
3773 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3774 | int destreg = ((instruction >> 6) & 0x0000001F); |
3775 | int fs = ((instruction >> 11) & 0x0000001F); | |
3776 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3777 | { |
3778 | if ((format == fmt_double) | 0) | |
3779 | SignalException(ReservedInstruction,instruction); | |
3780 | else | |
3781 | StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double)); | |
3782 | } | |
3783 | } | |
3784 | ||
3785 | ||
3786 | 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt | |
3787 | "cvt.l.%s<FMT> f<FD>, f<FS>" | |
3788 | *mipsIII: | |
3789 | *mipsIV: | |
23850e92 | 3790 | *vr5000: |
90ad43b2 AC |
3791 | // start-sanitize-vr5400 |
3792 | *vr5400: | |
3793 | // end-sanitize-vr5400 | |
f2b30012 AC |
3794 | *r3900: |
3795 | // start-sanitize-tx19 | |
3796 | *tx19: | |
3797 | // end-sanitize-tx19 | |
3798 | { | |
3799 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3800 | int destreg = ((instruction >> 6) & 0x0000001F); |
3801 | int fs = ((instruction >> 11) & 0x0000001F); | |
3802 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3803 | { |
3804 | if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word))) | |
3805 | SignalException(ReservedInstruction,instruction); | |
3806 | else | |
3807 | StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long)); | |
3808 | } | |
3809 | } | |
3810 | ||
3811 | ||
3812 | // | |
3813 | // FIXME: Does not correctly differentiate between mips* | |
3814 | // | |
3815 | 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt | |
3816 | "cvt.s.%s<FMT> f<FD>, f<FS>" | |
23850e92 JL |
3817 | *mipsI,mipsII,mipsIII,mipsIV: |
3818 | *vr5000: | |
90ad43b2 AC |
3819 | // start-sanitize-vr5400 |
3820 | *vr5400: | |
3821 | // end-sanitize-vr5400 | |
f2b30012 AC |
3822 | *r3900: |
3823 | // start-sanitize-tx19 | |
3824 | *tx19: | |
3825 | // end-sanitize-tx19 | |
3826 | { | |
3827 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3828 | int destreg = ((instruction >> 6) & 0x0000001F); |
3829 | int fs = ((instruction >> 11) & 0x0000001F); | |
3830 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3831 | { |
3832 | if ((format == fmt_single) | 0) | |
3833 | SignalException(ReservedInstruction,instruction); | |
3834 | else | |
3835 | StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single)); | |
3836 | } | |
3837 | } | |
3838 | ||
3839 | ||
3840 | 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt | |
3841 | "cvt.w.%s<FMT> f<FD>, f<FS>" | |
23850e92 JL |
3842 | *mipsI,mipsII,mipsIII,mipsIV: |
3843 | *vr5000: | |
90ad43b2 AC |
3844 | // start-sanitize-vr5400 |
3845 | *vr5400: | |
3846 | // end-sanitize-vr5400 | |
f2b30012 AC |
3847 | *r3900: |
3848 | // start-sanitize-tx19 | |
3849 | *tx19: | |
3850 | // end-sanitize-tx19 | |
3851 | { | |
3852 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3853 | int destreg = ((instruction >> 6) & 0x0000001F); |
3854 | int fs = ((instruction >> 11) & 0x0000001F); | |
3855 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3856 | { |
3857 | if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word))) | |
3858 | SignalException(ReservedInstruction,instruction); | |
3859 | else | |
3860 | StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word)); | |
3861 | } | |
3862 | } | |
3863 | ||
3864 | ||
3865 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt | |
3866 | "div.%s<FMT> f<FD>, f<FS>, f<FT>" | |
23850e92 JL |
3867 | *mipsI,mipsII,mipsIII,mipsIV: |
3868 | *vr5000: | |
90ad43b2 AC |
3869 | // start-sanitize-vr5400 |
3870 | *vr5400: | |
3871 | // end-sanitize-vr5400 | |
f2b30012 AC |
3872 | *r3900: |
3873 | // start-sanitize-tx19 | |
3874 | *tx19: | |
3875 | // end-sanitize-tx19 | |
3876 | { | |
3877 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3878 | int destreg = ((instruction >> 6) & 0x0000001F); |
3879 | int fs = ((instruction >> 11) & 0x0000001F); | |
3880 | int ft = ((instruction >> 16) & 0x0000001F); | |
3881 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3882 | { |
3883 | if ((format != fmt_single) && (format != fmt_double)) | |
3884 | SignalException(ReservedInstruction,instruction); | |
3885 | else | |
3886 | StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format)); | |
3887 | } | |
3888 | } | |
3889 | ||
3890 | ||
3891 | // DMFC1 | |
3892 | // DMTC1 | |
030843d7 AC |
3893 | 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1 |
3894 | "dm%s<X>c1 r<RT>, f<FS>" | |
f2b30012 | 3895 | *mipsIII: |
030843d7 AC |
3896 | { |
3897 | if (X) | |
3898 | { | |
3899 | if (SizeFGR() == 64) | |
3900 | PENDING_FILL((FS + FGRIDX),GPR[RT]); | |
3901 | else if ((FS & 0x1) == 0) | |
3902 | { | |
3903 | PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT])); | |
3904 | PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT])); | |
3905 | } | |
3906 | } | |
3907 | else | |
3908 | { | |
3909 | if (SizeFGR() == 64) | |
3910 | PENDING_FILL(RT,FGR[FS]); | |
3911 | else if ((FS & 0x1) == 0) | |
3912 | PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS])); | |
3913 | else | |
3914 | PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0); | |
3915 | } | |
3916 | } | |
3917 | 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1 | |
3918 | "dm%s<X>c1 r<RT>, f<FS>" | |
f2b30012 | 3919 | *mipsIV: |
23850e92 | 3920 | *vr5000: |
90ad43b2 AC |
3921 | // start-sanitize-vr5400 |
3922 | *vr5400: | |
3923 | // end-sanitize-vr5400 | |
f2b30012 AC |
3924 | // start-sanitize-r5900 |
3925 | *r5900: | |
3926 | // end-sanitize-r5900 | |
3927 | *r3900: | |
3928 | // start-sanitize-tx19 | |
3929 | *tx19: | |
3930 | // end-sanitize-tx19 | |
3931 | { | |
030843d7 AC |
3932 | if (X) |
3933 | { | |
3934 | if (SizeFGR() == 64) | |
23850e92 | 3935 | StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]); |
030843d7 | 3936 | else if ((FS & 0x1) == 0) |
23850e92 | 3937 | StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]); |
f2b30012 | 3938 | } |
030843d7 AC |
3939 | else |
3940 | { | |
3941 | if (SizeFGR() == 64) | |
3942 | GPR[RT] = FGR[FS]; | |
3943 | else if ((FS & 0x1) == 0) | |
3944 | GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS]; | |
3945 | else | |
3946 | GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; | |
3947 | } | |
f2b30012 AC |
3948 | } |
3949 | ||
3950 | ||
3951 | 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt | |
3952 | "floor.l.%s<FMT> f<FD>, f<FS>" | |
3953 | *mipsIII: | |
3954 | *mipsIV: | |
23850e92 | 3955 | *vr5000: |
90ad43b2 AC |
3956 | // start-sanitize-vr5400 |
3957 | *vr5400: | |
3958 | // end-sanitize-vr5400 | |
f2b30012 AC |
3959 | // start-sanitize-r5900 |
3960 | *r5900: | |
3961 | // end-sanitize-r5900 | |
3962 | *r3900: | |
3963 | // start-sanitize-tx19 | |
3964 | *tx19: | |
3965 | // end-sanitize-tx19 | |
3966 | { | |
3967 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3968 | int destreg = ((instruction >> 6) & 0x0000001F); |
3969 | int fs = ((instruction >> 11) & 0x0000001F); | |
3970 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
3971 | { |
3972 | if ((format != fmt_single) && (format != fmt_double)) | |
3973 | SignalException(ReservedInstruction,instruction); | |
3974 | else | |
3975 | StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long)); | |
3976 | } | |
3977 | } | |
3978 | ||
3979 | ||
3980 | 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt | |
3981 | "floor.w.%s<FMT> f<FD>, f<FS>" | |
3982 | *mipsII: | |
3983 | *mipsIII: | |
3984 | *mipsIV: | |
23850e92 | 3985 | *vr5000: |
90ad43b2 AC |
3986 | // start-sanitize-vr5400 |
3987 | *vr5400: | |
3988 | // end-sanitize-vr5400 | |
f2b30012 AC |
3989 | // start-sanitize-r5900 |
3990 | *r5900: | |
3991 | // end-sanitize-r5900 | |
3992 | *r3900: | |
3993 | // start-sanitize-tx19 | |
3994 | *tx19: | |
3995 | // end-sanitize-tx19 | |
3996 | { | |
3997 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
3998 | int destreg = ((instruction >> 6) & 0x0000001F); |
3999 | int fs = ((instruction >> 11) & 0x0000001F); | |
4000 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4001 | { |
4002 | if ((format != fmt_single) && (format != fmt_double)) | |
4003 | SignalException(ReservedInstruction,instruction); | |
4004 | else | |
4005 | StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word)); | |
4006 | } | |
4007 | } | |
4008 | ||
4009 | ||
030843d7 | 4010 | 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1 |
a94c5493 | 4011 | "ldc1 f<FT>, <OFFSET>(r<BASE>)" |
030843d7 AC |
4012 | *mipsII: |
4013 | *mipsIII: | |
4014 | *mipsIV: | |
23850e92 | 4015 | *vr5000: |
030843d7 AC |
4016 | // start-sanitize-vr5400 |
4017 | *vr5400: | |
4018 | // end-sanitize-vr5400 | |
4019 | *r3900: | |
4020 | // start-sanitize-tx19 | |
4021 | *tx19: | |
4022 | // end-sanitize-tx19 | |
4023 | { | |
a94c5493 AC |
4024 | address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET); |
4025 | address_word paddr; | |
4026 | int uncached; | |
4027 | if ((vaddr & 7) != 0) | |
4028 | SignalExceptionAddressLoad(); | |
4029 | else | |
4030 | { | |
4031 | unsigned64 memval; | |
4032 | AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL); | |
4033 | LoadMemory(&memval,0,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); | |
4034 | COP_LD(((instruction_0 >> 26) & 0x3),FT,memval);; | |
4035 | } | |
030843d7 | 4036 | } |
f2b30012 AC |
4037 | |
4038 | ||
4039 | 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1 | |
4040 | "ldxc1 f<FD>, r<INDEX>(r<BASE>)" | |
4041 | *mipsIV: | |
23850e92 | 4042 | *vr5000: |
90ad43b2 AC |
4043 | // start-sanitize-vr5400 |
4044 | *vr5400: | |
4045 | // end-sanitize-vr5400 | |
f2b30012 AC |
4046 | { |
4047 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4048 | int destreg = ((instruction >> 6) & 0x0000001F); |
4049 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
4050 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 4051 | { |
49a76833 AC |
4052 | address_word vaddr = ((unsigned64)op1 + op2); |
4053 | address_word paddr; | |
f2b30012 AC |
4054 | int uncached; |
4055 | if ((vaddr & 7) != 0) | |
055ee297 | 4056 | SignalExceptionAddressLoad(); |
f2b30012 AC |
4057 | else |
4058 | { | |
4059 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4060 | { | |
4061 | unsigned64 memval = 0; | |
4062 | unsigned64 memval1 = 0; | |
f2b30012 AC |
4063 | LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); |
4064 | COP_LD(1,destreg,memval);; | |
4065 | } | |
4066 | } | |
4067 | } | |
4068 | } | |
4069 | ||
4070 | ||
f2b30012 | 4071 | |
030843d7 | 4072 | 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1 |
23850e92 JL |
4073 | "lwc1 f<FT>, <OFFSET>(r<BASE>)" |
4074 | *mipsI,mipsII,mipsIII,mipsIV: | |
4075 | *vr5000: | |
90ad43b2 AC |
4076 | // start-sanitize-vr5400 |
4077 | *vr5400: | |
4078 | // end-sanitize-vr5400 | |
f2b30012 AC |
4079 | // start-sanitize-r5900 |
4080 | *r5900: | |
4081 | // end-sanitize-r5900 | |
030843d7 AC |
4082 | *r3900: |
4083 | // start-sanitize-tx19 | |
4084 | *tx19: | |
4085 | // end-sanitize-tx19 | |
4086 | { | |
4087 | unsigned32 instruction = instruction_0; | |
4088 | signed_word offset = EXTEND16 (OFFSET); | |
4089 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
4090 | signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
4091 | { | |
4092 | address_word vaddr = ((uword64)op1 + offset); | |
4093 | address_word paddr; | |
4094 | int uncached; | |
4095 | if ((vaddr & 3) != 0) | |
4096 | SignalExceptionAddressLoad(); | |
4097 | else | |
4098 | { | |
4099 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4100 | { | |
4101 | uword64 memval = 0; | |
4102 | uword64 memval1 = 0; | |
4103 | uword64 mask = 0x7; | |
4104 | unsigned int shift = 2; | |
4105 | unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0); | |
4106 | unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0); | |
4107 | unsigned int byte UNUSED; | |
4108 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); | |
4109 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
4110 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
4111 | COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF)); | |
4112 | } | |
4113 | } | |
4114 | } | |
4115 | } | |
4116 | ||
4117 | ||
4118 | 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1 | |
4119 | "lwxc1 f<FD>, r<INDEX>(r<BASE>)" | |
4120 | *mipsIV: | |
23850e92 | 4121 | *vr5000: |
030843d7 AC |
4122 | // start-sanitize-vr5400 |
4123 | *vr5400: | |
4124 | // end-sanitize-vr5400 | |
f2b30012 AC |
4125 | { |
4126 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4127 | int destreg = ((instruction >> 6) & 0x0000001F); |
4128 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
4129 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 4130 | { |
49a76833 AC |
4131 | address_word vaddr = ((unsigned64)op1 + op2); |
4132 | address_word paddr; | |
f2b30012 AC |
4133 | int uncached; |
4134 | if ((vaddr & 3) != 0) | |
055ee297 | 4135 | SignalExceptionAddressLoad(); |
f2b30012 AC |
4136 | else |
4137 | { | |
4138 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4139 | { | |
4140 | unsigned64 memval = 0; | |
4141 | unsigned64 memval1 = 0; | |
4142 | unsigned64 mask = 0x7; | |
4143 | unsigned int shift = 2; | |
055ee297 AC |
4144 | unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); |
4145 | unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); | |
4146 | unsigned int byte; | |
f2b30012 AC |
4147 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); |
4148 | LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); | |
4149 | byte = ((vaddr & mask) ^ (bigend << shift)); | |
4150 | COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF)); | |
4151 | } | |
4152 | } | |
4153 | } | |
4154 | } | |
4155 | ||
4156 | ||
4157 | ||
4158 | // | |
4159 | // FIXME: Not correct for mips* | |
4160 | // | |
a48e8c8d | 4161 | 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D |
f2b30012 AC |
4162 | "madd.d f<FD>, f<FR>, f<FS>, f<FT>" |
4163 | *mipsIV: | |
23850e92 | 4164 | *vr5000: |
90ad43b2 AC |
4165 | // start-sanitize-vr5400 |
4166 | *vr5400: | |
4167 | // end-sanitize-vr5400 | |
f2b30012 AC |
4168 | { |
4169 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4170 | int destreg = ((instruction >> 6) & 0x0000001F); |
4171 | int fs = ((instruction >> 11) & 0x0000001F); | |
4172 | int ft = ((instruction >> 16) & 0x0000001F); | |
4173 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 AC |
4174 | { |
4175 | StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double)); | |
4176 | } | |
4177 | } | |
4178 | ||
4179 | ||
a48e8c8d | 4180 | 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S |
f2b30012 AC |
4181 | "madd.s f<FD>, f<FR>, f<FS>, f<FT>" |
4182 | *mipsIV: | |
23850e92 | 4183 | *vr5000: |
90ad43b2 AC |
4184 | // start-sanitize-vr5400 |
4185 | *vr5400: | |
4186 | // end-sanitize-vr5400 | |
f2b30012 AC |
4187 | { |
4188 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4189 | int destreg = ((instruction >> 6) & 0x0000001F); |
4190 | int fs = ((instruction >> 11) & 0x0000001F); | |
4191 | int ft = ((instruction >> 16) & 0x0000001F); | |
4192 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 AC |
4193 | { |
4194 | StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single)); | |
4195 | } | |
4196 | } | |
4197 | ||
4198 | ||
4199 | // MFC1 | |
030843d7 | 4200 | // MTC1 |
f2b30012 | 4201 | 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1 |
030843d7 | 4202 | "m%s<X>c1 r<RT>, f<FS>" |
f2b30012 AC |
4203 | *mipsI: |
4204 | *mipsII: | |
4205 | *mipsIII: | |
030843d7 AC |
4206 | { |
4207 | if (X) | |
4208 | { /*MTC1*/ | |
4209 | if (SizeFGR() == 64) | |
4210 | PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT]))); | |
4211 | else | |
4212 | PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT])); | |
4213 | } | |
4214 | else /*MFC1*/ | |
4215 | PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32)); | |
4216 | } | |
4217 | 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1 | |
4218 | "m%s<X>c1 r<RT>, f<FS>" | |
f2b30012 | 4219 | *mipsIV: |
23850e92 | 4220 | *vr5000: |
90ad43b2 AC |
4221 | // start-sanitize-vr5400 |
4222 | *vr5400: | |
4223 | // end-sanitize-vr5400 | |
f2b30012 AC |
4224 | *r3900: |
4225 | // start-sanitize-tx19 | |
4226 | *tx19: | |
4227 | // end-sanitize-tx19 | |
4228 | { | |
030843d7 | 4229 | if (X) |
23850e92 JL |
4230 | /*MTC1*/ |
4231 | StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT])); | |
030843d7 AC |
4232 | else /*MFC1*/ |
4233 | GPR[RT] = SIGNEXTEND(FGR[FS],32); | |
f2b30012 AC |
4234 | } |
4235 | ||
4236 | ||
4237 | 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt | |
4238 | "mov.%s<FMT> f<FD>, f<FS>" | |
23850e92 JL |
4239 | *mipsI,mipsII,mipsIII,mipsIV: |
4240 | *vr5000: | |
90ad43b2 AC |
4241 | // start-sanitize-vr5400 |
4242 | *vr5400: | |
4243 | // end-sanitize-vr5400 | |
f2b30012 AC |
4244 | *r3900: |
4245 | // start-sanitize-tx19 | |
4246 | *tx19: | |
4247 | // end-sanitize-tx19 | |
4248 | { | |
4249 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4250 | int destreg = ((instruction >> 6) & 0x0000001F); |
4251 | int fs = ((instruction >> 11) & 0x0000001F); | |
4252 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4253 | { |
4254 | StoreFPR(destreg,format,ValueFPR(fs,format)); | |
4255 | } | |
4256 | } | |
4257 | ||
4258 | ||
4259 | // MOVF | |
4260 | 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf | |
055ee297 | 4261 | "mov%s<TF> r<RD>, r<RS>, <CC>" |
f2b30012 | 4262 | *mipsIV: |
23850e92 | 4263 | *vr5000: |
90ad43b2 AC |
4264 | // start-sanitize-vr5400 |
4265 | *vr5400: | |
4266 | // end-sanitize-vr5400 | |
f2b30012 AC |
4267 | // start-sanitize-r5900 |
4268 | *r5900: | |
4269 | // end-sanitize-r5900 | |
4270 | { | |
055ee297 AC |
4271 | if (GETFCC(CC) == TF) |
4272 | GPR[RD] = GPR[RS]; | |
f2b30012 AC |
4273 | } |
4274 | ||
4275 | ||
4276 | // MOVF.fmt | |
4277 | 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt | |
055ee297 | 4278 | "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>" |
f2b30012 | 4279 | *mipsIV: |
23850e92 | 4280 | *vr5000: |
90ad43b2 AC |
4281 | // start-sanitize-vr5400 |
4282 | *vr5400: | |
4283 | // end-sanitize-vr5400 | |
f2b30012 AC |
4284 | // start-sanitize-r5900 |
4285 | *r5900: | |
4286 | // end-sanitize-r5900 | |
4287 | { | |
4288 | unsigned32 instruction = instruction_0; | |
055ee297 | 4289 | int format = ((instruction >> 21) & 0x00000007); |
f2b30012 | 4290 | { |
055ee297 AC |
4291 | if (GETFCC(CC) == TF) |
4292 | StoreFPR (FD, format, ValueFPR (FS, format)); | |
f2b30012 | 4293 | else |
055ee297 | 4294 | StoreFPR (FD, format, ValueFPR (FD, format)); |
f2b30012 AC |
4295 | } |
4296 | } | |
4297 | ||
4298 | ||
4299 | 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt | |
4300 | *mipsIV: | |
23850e92 | 4301 | *vr5000: |
90ad43b2 AC |
4302 | // start-sanitize-vr5400 |
4303 | *vr5400: | |
4304 | // end-sanitize-vr5400 | |
f2b30012 AC |
4305 | // start-sanitize-r5900 |
4306 | *r5900: | |
4307 | // end-sanitize-r5900 | |
4308 | { | |
4309 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4310 | int destreg = ((instruction >> 6) & 0x0000001F); |
4311 | int fs = ((instruction >> 11) & 0x0000001F); | |
4312 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4313 | { |
4314 | StoreFPR(destreg,format,ValueFPR(fs,format)); | |
4315 | } | |
4316 | } | |
4317 | ||
4318 | ||
4319 | // MOVT see MOVtf | |
4320 | ||
4321 | ||
4322 | // MOVT.fmt see MOVtf.fmt | |
4323 | ||
4324 | ||
4325 | ||
4326 | 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt | |
4327 | "movz.%s<FMT> f<FD>, f<FS>, r<RT>" | |
4328 | *mipsIV: | |
23850e92 | 4329 | *vr5000: |
90ad43b2 AC |
4330 | // start-sanitize-vr5400 |
4331 | *vr5400: | |
4332 | // end-sanitize-vr5400 | |
f2b30012 AC |
4333 | // start-sanitize-r5900 |
4334 | *r5900: | |
4335 | // end-sanitize-r5900 | |
4336 | { | |
4337 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4338 | int destreg = ((instruction >> 6) & 0x0000001F); |
4339 | int fs = ((instruction >> 11) & 0x0000001F); | |
4340 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4341 | { |
4342 | StoreFPR(destreg,format,ValueFPR(fs,format)); | |
4343 | } | |
4344 | } | |
4345 | ||
4346 | ||
4347 | // MSUB.fmt | |
4348 | 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D | |
4349 | "msub.d f<FD>, f<FR>, f<FS>, f<FT>" | |
4350 | *mipsIV: | |
23850e92 | 4351 | *vr5000: |
90ad43b2 AC |
4352 | // start-sanitize-vr5400 |
4353 | *vr5400: | |
4354 | // end-sanitize-vr5400 | |
f2b30012 AC |
4355 | // start-sanitize-r5900 |
4356 | *r5900: | |
4357 | // end-sanitize-r5900 | |
4358 | { | |
4359 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4360 | int destreg = ((instruction >> 6) & 0x0000001F); |
4361 | int fs = ((instruction >> 11) & 0x0000001F); | |
4362 | int ft = ((instruction >> 16) & 0x0000001F); | |
4363 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 | 4364 | { |
23850e92 | 4365 | StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double)); |
f2b30012 AC |
4366 | } |
4367 | } | |
4368 | ||
4369 | ||
4370 | // MSUB.fmt | |
055ee297 | 4371 | 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S |
f2b30012 AC |
4372 | "msub.s f<FD>, f<FR>, f<FS>, f<FT>" |
4373 | *mipsIV: | |
23850e92 | 4374 | *vr5000: |
90ad43b2 AC |
4375 | // start-sanitize-vr5400 |
4376 | *vr5400: | |
4377 | // end-sanitize-vr5400 | |
f2b30012 AC |
4378 | // start-sanitize-r5900 |
4379 | *r5900: | |
4380 | // end-sanitize-r5900 | |
4381 | { | |
4382 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4383 | int destreg = ((instruction >> 6) & 0x0000001F); |
4384 | int fs = ((instruction >> 11) & 0x0000001F); | |
4385 | int ft = ((instruction >> 16) & 0x0000001F); | |
4386 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 | 4387 | { |
23850e92 | 4388 | StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single)); |
f2b30012 AC |
4389 | } |
4390 | } | |
4391 | ||
4392 | ||
4393 | // MTC1 see MxC1 | |
4394 | ||
4395 | ||
4396 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt | |
4397 | "mul.%s<FMT> f<FD>, f<FS>, f<FT>" | |
23850e92 JL |
4398 | *mipsI,mipsII,mipsIII,mipsIV: |
4399 | *vr5000: | |
90ad43b2 AC |
4400 | // start-sanitize-vr5400 |
4401 | *vr5400: | |
4402 | // end-sanitize-vr5400 | |
f2b30012 AC |
4403 | *r3900: |
4404 | // start-sanitize-tx19 | |
4405 | *tx19: | |
4406 | // end-sanitize-tx19 | |
4407 | { | |
4408 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4409 | int destreg = ((instruction >> 6) & 0x0000001F); |
4410 | int fs = ((instruction >> 11) & 0x0000001F); | |
4411 | int ft = ((instruction >> 16) & 0x0000001F); | |
4412 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4413 | { |
4414 | if ((format != fmt_single) && (format != fmt_double)) | |
4415 | SignalException(ReservedInstruction,instruction); | |
4416 | else | |
4417 | StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format)); | |
4418 | } | |
4419 | } | |
4420 | ||
4421 | ||
4422 | 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt | |
4423 | "neg.%s<FMT> f<FD>, f<FS>" | |
23850e92 JL |
4424 | *mipsI,mipsII,mipsIII,mipsIV: |
4425 | *vr5000: | |
90ad43b2 AC |
4426 | // start-sanitize-vr5400 |
4427 | *vr5400: | |
4428 | // end-sanitize-vr5400 | |
f2b30012 AC |
4429 | *r3900: |
4430 | // start-sanitize-tx19 | |
4431 | *tx19: | |
4432 | // end-sanitize-tx19 | |
4433 | { | |
4434 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4435 | int destreg = ((instruction >> 6) & 0x0000001F); |
4436 | int fs = ((instruction >> 11) & 0x0000001F); | |
4437 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4438 | { |
4439 | if ((format != fmt_single) && (format != fmt_double)) | |
4440 | SignalException(ReservedInstruction,instruction); | |
4441 | else | |
4442 | StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format)); | |
4443 | } | |
4444 | } | |
4445 | ||
4446 | ||
4447 | // NMADD.fmt | |
4448 | 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D | |
4449 | "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>" | |
4450 | *mipsIV: | |
23850e92 | 4451 | *vr5000: |
90ad43b2 AC |
4452 | // start-sanitize-vr5400 |
4453 | *vr5400: | |
4454 | // end-sanitize-vr5400 | |
f2b30012 AC |
4455 | { |
4456 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4457 | int destreg = ((instruction >> 6) & 0x0000001F); |
4458 | int fs = ((instruction >> 11) & 0x0000001F); | |
4459 | int ft = ((instruction >> 16) & 0x0000001F); | |
4460 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 AC |
4461 | { |
4462 | StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double)); | |
4463 | } | |
4464 | } | |
4465 | ||
4466 | ||
4467 | // NMADD.fmt | |
4468 | 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S | |
4469 | "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>" | |
4470 | *mipsIV: | |
23850e92 | 4471 | *vr5000: |
90ad43b2 AC |
4472 | // start-sanitize-vr5400 |
4473 | *vr5400: | |
4474 | // end-sanitize-vr5400 | |
f2b30012 AC |
4475 | { |
4476 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4477 | int destreg = ((instruction >> 6) & 0x0000001F); |
4478 | int fs = ((instruction >> 11) & 0x0000001F); | |
4479 | int ft = ((instruction >> 16) & 0x0000001F); | |
4480 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 AC |
4481 | { |
4482 | StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single)); | |
4483 | } | |
4484 | } | |
4485 | ||
4486 | ||
4487 | // NMSUB.fmt | |
055ee297 | 4488 | 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D |
f2b30012 AC |
4489 | "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>" |
4490 | *mipsIV: | |
23850e92 | 4491 | *vr5000: |
90ad43b2 AC |
4492 | // start-sanitize-vr5400 |
4493 | *vr5400: | |
4494 | // end-sanitize-vr5400 | |
f2b30012 AC |
4495 | { |
4496 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4497 | int destreg = ((instruction >> 6) & 0x0000001F); |
4498 | int fs = ((instruction >> 11) & 0x0000001F); | |
4499 | int ft = ((instruction >> 16) & 0x0000001F); | |
4500 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 AC |
4501 | { |
4502 | StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double)); | |
4503 | } | |
4504 | } | |
4505 | ||
4506 | ||
4507 | // NMSUB.fmt | |
055ee297 | 4508 | 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S |
f2b30012 AC |
4509 | "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>" |
4510 | *mipsIV: | |
23850e92 | 4511 | *vr5000: |
90ad43b2 AC |
4512 | // start-sanitize-vr5400 |
4513 | *vr5400: | |
4514 | // end-sanitize-vr5400 | |
f2b30012 AC |
4515 | { |
4516 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4517 | int destreg = ((instruction >> 6) & 0x0000001F); |
4518 | int fs = ((instruction >> 11) & 0x0000001F); | |
4519 | int ft = ((instruction >> 16) & 0x0000001F); | |
4520 | int fr = ((instruction >> 21) & 0x0000001F); | |
f2b30012 AC |
4521 | { |
4522 | StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single)); | |
4523 | } | |
4524 | } | |
4525 | ||
4526 | ||
4527 | 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX | |
49a6eed5 | 4528 | "prefx <HINT>, r<INDEX>(r<BASE>)" |
f2b30012 | 4529 | *mipsIV: |
23850e92 | 4530 | *vr5000: |
90ad43b2 AC |
4531 | // start-sanitize-vr5400 |
4532 | *vr5400: | |
4533 | // end-sanitize-vr5400 | |
f2b30012 AC |
4534 | { |
4535 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4536 | int fs = ((instruction >> 11) & 0x0000001F); |
4537 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
4538 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 4539 | { |
49a76833 AC |
4540 | address_word vaddr = ((unsigned64)op1 + (unsigned64)op2); |
4541 | address_word paddr; | |
f2b30012 AC |
4542 | int uncached; |
4543 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4544 | Prefetch(uncached,paddr,vaddr,isDATA,fs); | |
4545 | } | |
4546 | } | |
4547 | ||
4548 | 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt | |
4549 | *mipsIV: | |
4550 | "recip.%s<FMT> f<FD>, f<FS>" | |
23850e92 | 4551 | *vr5000: |
90ad43b2 AC |
4552 | // start-sanitize-vr5400 |
4553 | *vr5400: | |
4554 | // end-sanitize-vr5400 | |
f2b30012 AC |
4555 | { |
4556 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4557 | int destreg = ((instruction >> 6) & 0x0000001F); |
4558 | int fs = ((instruction >> 11) & 0x0000001F); | |
4559 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4560 | { |
4561 | if ((format != fmt_single) && (format != fmt_double)) | |
4562 | SignalException(ReservedInstruction,instruction); | |
4563 | else | |
4564 | StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format)); | |
4565 | } | |
4566 | } | |
4567 | ||
4568 | ||
4569 | 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt | |
49a6eed5 | 4570 | "round.l.%s<FMT> f<FD>, f<FS>" |
f2b30012 AC |
4571 | *mipsIII: |
4572 | *mipsIV: | |
23850e92 | 4573 | *vr5000: |
90ad43b2 AC |
4574 | // start-sanitize-vr5400 |
4575 | *vr5400: | |
4576 | // end-sanitize-vr5400 | |
f2b30012 AC |
4577 | // start-sanitize-r5900 |
4578 | *r5900: | |
4579 | // end-sanitize-r5900 | |
4580 | *r3900: | |
4581 | // start-sanitize-tx19 | |
4582 | *tx19: | |
4583 | // end-sanitize-tx19 | |
4584 | { | |
4585 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4586 | int destreg = ((instruction >> 6) & 0x0000001F); |
4587 | int fs = ((instruction >> 11) & 0x0000001F); | |
4588 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4589 | { |
4590 | if ((format != fmt_single) && (format != fmt_double)) | |
4591 | SignalException(ReservedInstruction,instruction); | |
4592 | else | |
4593 | StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long)); | |
4594 | } | |
4595 | } | |
4596 | ||
4597 | ||
4598 | 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt | |
49a6eed5 | 4599 | "round.w.%s<FMT> f<FD>, f<FS>" |
f2b30012 AC |
4600 | *mipsII: |
4601 | *mipsIII: | |
4602 | *mipsIV: | |
23850e92 | 4603 | *vr5000: |
90ad43b2 AC |
4604 | // start-sanitize-vr5400 |
4605 | *vr5400: | |
4606 | // end-sanitize-vr5400 | |
f2b30012 AC |
4607 | // start-sanitize-r5900 |
4608 | *r5900: | |
4609 | // end-sanitize-r5900 | |
4610 | *r3900: | |
4611 | // start-sanitize-tx19 | |
4612 | *tx19: | |
4613 | // end-sanitize-tx19 | |
4614 | { | |
4615 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4616 | int destreg = ((instruction >> 6) & 0x0000001F); |
4617 | int fs = ((instruction >> 11) & 0x0000001F); | |
4618 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4619 | { |
4620 | if ((format != fmt_single) && (format != fmt_double)) | |
4621 | SignalException(ReservedInstruction,instruction); | |
4622 | else | |
4623 | StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word)); | |
4624 | } | |
4625 | } | |
4626 | ||
4627 | ||
4628 | 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt | |
4629 | *mipsIV: | |
4630 | "rsqrt.%s<FMT> f<FD>, f<FS>" | |
23850e92 | 4631 | *vr5000: |
90ad43b2 AC |
4632 | // start-sanitize-vr5400 |
4633 | *vr5400: | |
4634 | // end-sanitize-vr5400 | |
f2b30012 AC |
4635 | { |
4636 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4637 | int destreg = ((instruction >> 6) & 0x0000001F); |
4638 | int fs = ((instruction >> 11) & 0x0000001F); | |
4639 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4640 | { |
4641 | if ((format != fmt_single) && (format != fmt_double)) | |
4642 | SignalException(ReservedInstruction,instruction); | |
4643 | else | |
085c1cb9 | 4644 | StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format)); |
f2b30012 AC |
4645 | } |
4646 | } | |
4647 | ||
4648 | ||
030843d7 AC |
4649 | 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1 |
4650 | "sdc1 f<FT>, <OFFSET>(r<BASE>)" | |
4651 | *mipsII: | |
4652 | *mipsIII: | |
4653 | *mipsIV: | |
23850e92 | 4654 | *vr5000: |
030843d7 AC |
4655 | // start-sanitize-vr5400 |
4656 | *vr5400: | |
4657 | // end-sanitize-vr5400 | |
4658 | *r3900: | |
4659 | // start-sanitize-tx19 | |
4660 | *tx19: | |
4661 | // end-sanitize-tx19 | |
4662 | { | |
a94c5493 AC |
4663 | address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET); |
4664 | int uncached; | |
4665 | if ((vaddr & 7) != 0) | |
4666 | SignalExceptionAddressStore(); | |
4667 | else | |
4668 | { | |
4669 | address_word paddr; | |
4670 | unsigned64 memval; | |
4671 | AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL); | |
4672 | memval = (unsigned64) COP_SD(((instruction_0 >> 26) & 0x3),FT); | |
4673 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,0,paddr,vaddr,isREAL); | |
4674 | } | |
030843d7 | 4675 | } |
f2b30012 AC |
4676 | |
4677 | ||
a94c5493 | 4678 | |
f2b30012 AC |
4679 | 010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1 |
4680 | *mipsIV: | |
23850e92 | 4681 | *vr5000: |
90ad43b2 AC |
4682 | // start-sanitize-vr5400 |
4683 | *vr5400: | |
4684 | // end-sanitize-vr5400 | |
f2b30012 AC |
4685 | { |
4686 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4687 | int fs = ((instruction >> 11) & 0x0000001F); |
4688 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
4689 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 4690 | { |
49a76833 AC |
4691 | address_word vaddr = ((unsigned64)op1 + op2); |
4692 | address_word paddr; | |
f2b30012 AC |
4693 | int uncached; |
4694 | if ((vaddr & 7) != 0) | |
055ee297 | 4695 | SignalExceptionAddressStore(); |
f2b30012 AC |
4696 | else |
4697 | { | |
4698 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
4699 | { | |
4700 | unsigned64 memval = 0; | |
4701 | unsigned64 memval1 = 0; | |
4702 | memval = (unsigned64)COP_SD(1,fs); | |
4703 | { | |
4704 | StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); | |
4705 | } | |
4706 | } | |
4707 | } | |
4708 | } | |
4709 | } | |
4710 | ||
4711 | ||
4712 | 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt | |
4713 | "sqrt.%s<FMT> f<FD>, f<FS>" | |
4714 | *mipsII: | |
4715 | *mipsIII: | |
4716 | *mipsIV: | |
23850e92 | 4717 | *vr5000: |
90ad43b2 AC |
4718 | // start-sanitize-vr5400 |
4719 | *vr5400: | |
4720 | // end-sanitize-vr5400 | |
f2b30012 AC |
4721 | *r3900: |
4722 | // start-sanitize-tx19 | |
4723 | *tx19: | |
4724 | // end-sanitize-tx19 | |
4725 | { | |
4726 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4727 | int destreg = ((instruction >> 6) & 0x0000001F); |
4728 | int fs = ((instruction >> 11) & 0x0000001F); | |
4729 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4730 | { |
4731 | if ((format != fmt_single) && (format != fmt_double)) | |
4732 | SignalException(ReservedInstruction,instruction); | |
4733 | else | |
4734 | StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format))); | |
4735 | } | |
4736 | } | |
4737 | ||
4738 | ||
4739 | 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt | |
4740 | "sub.%s<FMT> f<FD>, f<FS>, f<FT>" | |
23850e92 JL |
4741 | *mipsI,mipsII,mipsIII,mipsIV: |
4742 | *vr5000: | |
90ad43b2 AC |
4743 | // start-sanitize-vr5400 |
4744 | *vr5400: | |
4745 | // end-sanitize-vr5400 | |
f2b30012 AC |
4746 | *r3900: |
4747 | // start-sanitize-tx19 | |
4748 | *tx19: | |
4749 | // end-sanitize-tx19 | |
4750 | { | |
4751 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4752 | int destreg = ((instruction >> 6) & 0x0000001F); |
4753 | int fs = ((instruction >> 11) & 0x0000001F); | |
4754 | int ft = ((instruction >> 16) & 0x0000001F); | |
4755 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4756 | { |
4757 | if ((format != fmt_single) && (format != fmt_double)) | |
4758 | SignalException(ReservedInstruction,instruction); | |
4759 | else | |
4760 | StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format)); | |
4761 | } | |
4762 | } | |
4763 | ||
4764 | ||
f2b30012 | 4765 | |
030843d7 AC |
4766 | 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1 |
4767 | "swc1 f<FT>, <OFFSET>(r<BASE>)" | |
23850e92 JL |
4768 | *mipsI,mipsII,mipsIII,mipsIV: |
4769 | *vr5000: | |
90ad43b2 AC |
4770 | // start-sanitize-vr5400 |
4771 | *vr5400: | |
4772 | // end-sanitize-vr5400 | |
f2b30012 AC |
4773 | // start-sanitize-r5900 |
4774 | *r5900: | |
4775 | // end-sanitize-r5900 | |
030843d7 AC |
4776 | *r3900: |
4777 | // start-sanitize-tx19 | |
4778 | *tx19: | |
4779 | // end-sanitize-tx19 | |
4780 | { | |
4781 | unsigned32 instruction = instruction_0; | |
4782 | signed_word offset = EXTEND16 (OFFSET); | |
4783 | int destreg UNUSED = ((instruction >> 16) & 0x0000001F); | |
4784 | signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)]; | |
4785 | { | |
4786 | address_word vaddr = ((uword64)op1 + offset); | |
4787 | address_word paddr; | |
4788 | int uncached; | |
4789 | if ((vaddr & 3) != 0) | |
4790 | SignalExceptionAddressStore(); | |
4791 | else | |
4792 | { | |
4793 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
4794 | { | |
4795 | uword64 memval = 0; | |
4796 | uword64 memval1 = 0; | |
4797 | uword64 mask = 0x7; | |
4798 | unsigned int byte; | |
4799 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
4800 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
4801 | memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte)); | |
4802 | { | |
4803 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
4804 | } | |
4805 | } | |
4806 | } | |
4807 | } | |
4808 | } | |
4809 | ||
4810 | ||
4811 | 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1 | |
4812 | "swxc1 f<FS>, r<INDEX>(r<BASE>)" | |
4813 | *mipsIV: | |
23850e92 | 4814 | *vr5000: |
030843d7 AC |
4815 | // start-sanitize-vr5400 |
4816 | *vr5400: | |
4817 | // end-sanitize-vr5400 | |
f2b30012 AC |
4818 | { |
4819 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4820 | int fs = ((instruction >> 11) & 0x0000001F); |
4821 | signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
4822 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 4823 | { |
49a76833 AC |
4824 | address_word vaddr = ((unsigned64)op1 + op2); |
4825 | address_word paddr; | |
f2b30012 AC |
4826 | int uncached; |
4827 | if ((vaddr & 3) != 0) | |
055ee297 | 4828 | SignalExceptionAddressStore(); |
f2b30012 AC |
4829 | else |
4830 | { | |
4831 | if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) | |
4832 | { | |
4833 | unsigned64 memval = 0; | |
4834 | unsigned64 memval1 = 0; | |
4835 | unsigned64 mask = 0x7; | |
4836 | unsigned int byte; | |
4837 | paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); | |
4838 | byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); | |
4839 | memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte)); | |
4840 | { | |
4841 | StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); | |
4842 | } | |
4843 | } | |
4844 | } | |
4845 | } | |
4846 | } | |
4847 | ||
4848 | ||
4849 | 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt | |
4850 | "trunc.l.%s<FMT> f<FD>, f<FS>" | |
4851 | *mipsIII: | |
4852 | *mipsIV: | |
23850e92 | 4853 | *vr5000: |
90ad43b2 AC |
4854 | // start-sanitize-vr5400 |
4855 | *vr5400: | |
4856 | // end-sanitize-vr5400 | |
f2b30012 AC |
4857 | // start-sanitize-r5900 |
4858 | *r5900: | |
4859 | // end-sanitize-r5900 | |
4860 | *r3900: | |
4861 | // start-sanitize-tx19 | |
4862 | *tx19: | |
4863 | // end-sanitize-tx19 | |
4864 | { | |
4865 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4866 | int destreg = ((instruction >> 6) & 0x0000001F); |
4867 | int fs = ((instruction >> 11) & 0x0000001F); | |
4868 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4869 | { |
4870 | if ((format != fmt_single) && (format != fmt_double)) | |
4871 | SignalException(ReservedInstruction,instruction); | |
4872 | else | |
4873 | StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long)); | |
4874 | } | |
4875 | } | |
4876 | ||
4877 | ||
4878 | 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W | |
4879 | "trunc.w.%s<FMT> f<FD>, f<FS>" | |
4880 | *mipsII: | |
4881 | *mipsIII: | |
4882 | *mipsIV: | |
23850e92 | 4883 | *vr5000: |
90ad43b2 AC |
4884 | // start-sanitize-vr5400 |
4885 | *vr5400: | |
4886 | // end-sanitize-vr5400 | |
f2b30012 AC |
4887 | // start-sanitize-r5900 |
4888 | *r5900: | |
4889 | // end-sanitize-r5900 | |
4890 | *r3900: | |
4891 | // start-sanitize-tx19 | |
4892 | *tx19: | |
4893 | // end-sanitize-tx19 | |
4894 | { | |
4895 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4896 | int destreg = ((instruction >> 6) & 0x0000001F); |
4897 | int fs = ((instruction >> 11) & 0x0000001F); | |
4898 | int format = ((instruction >> 21) & 0x00000007); | |
f2b30012 AC |
4899 | { |
4900 | if ((format != fmt_single) && (format != fmt_double)) | |
4901 | SignalException(ReservedInstruction,instruction); | |
4902 | else | |
4903 | StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word)); | |
4904 | } | |
4905 | } | |
4906 | ||
4907 | \f | |
4908 | // | |
4909 | // MIPS Architecture: | |
4910 | // | |
4911 | // System Control Instruction Set (COP0) | |
4912 | // | |
4913 | ||
4914 | ||
4915 | 010000,01000,00000,16.OFFSET:COP0:32::BC0F | |
4916 | "bc0f <OFFSET>" | |
23850e92 JL |
4917 | *mipsI,mipsII,mipsIII,mipsIV: |
4918 | *vr5000: | |
90ad43b2 AC |
4919 | // start-sanitize-vr5400 |
4920 | *vr5400: | |
4921 | // end-sanitize-vr5400 | |
f2b30012 AC |
4922 | // start-sanitize-r5900 |
4923 | *r5900: | |
4924 | // end-sanitize-r5900 | |
4925 | ||
4926 | ||
4927 | 010000,01000,00010,16.OFFSET:COP0:32::BC0FL | |
4928 | "bc0fl <OFFSET>" | |
23850e92 JL |
4929 | *mipsI,mipsII,mipsIII,mipsIV: |
4930 | *vr5000: | |
90ad43b2 AC |
4931 | // start-sanitize-vr5400 |
4932 | *vr5400: | |
4933 | // end-sanitize-vr5400 | |
f2b30012 AC |
4934 | // start-sanitize-r5900 |
4935 | *r5900: | |
4936 | // end-sanitize-r5900 | |
4937 | ||
4938 | ||
4939 | 010000,01000,00001,16.OFFSET:COP0:32::BC0T | |
4940 | "bc0t <OFFSET>" | |
23850e92 | 4941 | *mipsI,mipsII,mipsIII,mipsIV: |
f2b30012 AC |
4942 | // start-sanitize-r5900 |
4943 | *r5900: | |
4944 | // end-sanitize-r5900 | |
4945 | ||
4946 | ||
4947 | ||
49a6eed5 | 4948 | 010000,01000,00011,16.OFFSET:COP0:32::BC0TL |
f2b30012 | 4949 | "bc0tl <OFFSET>" |
23850e92 JL |
4950 | *mipsI,mipsII,mipsIII,mipsIV: |
4951 | *vr5000: | |
90ad43b2 AC |
4952 | // start-sanitize-vr5400 |
4953 | *vr5400: | |
4954 | // end-sanitize-vr5400 | |
f2b30012 AC |
4955 | // start-sanitize-r5900 |
4956 | *r5900: | |
4957 | // end-sanitize-r5900 | |
4958 | ||
4959 | ||
4960 | 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE | |
4961 | *mipsIII: | |
4962 | *mipsIV: | |
23850e92 | 4963 | *vr5000: |
90ad43b2 AC |
4964 | // start-sanitize-vr5400 |
4965 | *vr5400: | |
4966 | // end-sanitize-vr5400 | |
f2b30012 AC |
4967 | // start-sanitize-r5900 |
4968 | *r5900: | |
4969 | // end-sanitize-r5900 | |
4970 | *r3900: | |
4971 | // start-sanitize-tx19 | |
4972 | *tx19: | |
4973 | // end-sanitize-tx19 | |
4974 | { | |
4975 | unsigned32 instruction = instruction_0; | |
055ee297 AC |
4976 | signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
4977 | int hint = ((instruction >> 16) & 0x0000001F); | |
4978 | signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
f2b30012 | 4979 | { |
49a76833 AC |
4980 | address_word vaddr = (op1 + offset); |
4981 | address_word paddr; | |
f2b30012 AC |
4982 | int uncached; |
4983 | if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) | |
4984 | CacheOp(hint,vaddr,paddr,instruction); | |
4985 | } | |
4986 | } | |
4987 | ||
4988 | ||
4989 | 010000,10000,000000000000000,111001:COP0:32::DI | |
4990 | "di" | |
23850e92 JL |
4991 | *mipsI,mipsII,mipsIII,mipsIV: |
4992 | *vr5000: | |
90ad43b2 AC |
4993 | // start-sanitize-vr5400 |
4994 | *vr5400: | |
4995 | // end-sanitize-vr5400 | |
f2b30012 AC |
4996 | // start-sanitize-r5900 |
4997 | *r5900: | |
4998 | // end-sanitize-r5900 | |
4999 | ||
5000 | ||
5001 | 010000,10000,000000000000000,111000:COP0:32::EI | |
5002 | "ei" | |
23850e92 JL |
5003 | *mipsI,mipsII,mipsIII,mipsIV: |
5004 | *vr5000: | |
90ad43b2 AC |
5005 | // start-sanitize-vr5400 |
5006 | *vr5400: | |
5007 | // end-sanitize-vr5400 | |
f2b30012 AC |
5008 | // start-sanitize-r5900 |
5009 | *r5900: | |
5010 | // end-sanitize-r5900 | |
5011 | ||
5012 | ||
5013 | 010000,10000,000000000000000,011000:COP0:32::ERET | |
5014 | "eret" | |
5015 | *mipsIII: | |
5016 | *mipsIV: | |
23850e92 | 5017 | *vr5000: |
90ad43b2 AC |
5018 | // start-sanitize-vr5400 |
5019 | *vr5400: | |
5020 | // end-sanitize-vr5400 | |
f2b30012 AC |
5021 | // start-sanitize-r5900 |
5022 | *r5900: | |
5023 | // end-sanitize-r5900 | |
5024 | ||
5025 | ||
49a6eed5 AC |
5026 | 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0 |
5027 | "mfc0 r<RT>, r<RD> # <REGX>" | |
23850e92 JL |
5028 | *mipsI,mipsII,mipsIII,mipsIV: |
5029 | *vr5000: | |
90ad43b2 AC |
5030 | // start-sanitize-vr5400 |
5031 | *vr5400: | |
5032 | // end-sanitize-vr5400 | |
f2b30012 AC |
5033 | // start-sanitize-r5900 |
5034 | *r5900: | |
5035 | // end-sanitize-r5900 | |
030843d7 AC |
5036 | { |
5037 | DecodeCoproc (instruction_0); | |
5038 | } | |
f2b30012 | 5039 | |
49a6eed5 AC |
5040 | 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0 |
5041 | "mtc0 r<RT>, r<RD> # <REGX>" | |
23850e92 JL |
5042 | *mipsI,mipsII,mipsIII,mipsIV: |
5043 | *vr5000: | |
90ad43b2 AC |
5044 | // start-sanitize-vr5400 |
5045 | *vr5400: | |
5046 | // end-sanitize-vr5400 | |
f2b30012 AC |
5047 | // start-sanitize-r5900 |
5048 | *r5900: | |
5049 | // end-sanitize-r5900 | |
030843d7 AC |
5050 | { |
5051 | DecodeCoproc (instruction_0); | |
5052 | } | |
f2b30012 AC |
5053 | |
5054 | ||
5055 | 010000,10000,000000000000000,001000:COP0:32::TLBP | |
5056 | "tlbp" | |
23850e92 JL |
5057 | *mipsI,mipsII,mipsIII,mipsIV: |
5058 | *vr5000: | |
90ad43b2 AC |
5059 | // start-sanitize-vr5400 |
5060 | *vr5400: | |
5061 | // end-sanitize-vr5400 | |
f2b30012 AC |
5062 | // start-sanitize-r5900 |
5063 | *r5900: | |
5064 | // end-sanitize-r5900 | |
5065 | ||
5066 | ||
5067 | 010000,10000,000000000000000,000001:COP0:32::TLBR | |
5068 | "tlbr" | |
23850e92 JL |
5069 | *mipsI,mipsII,mipsIII,mipsIV: |
5070 | *vr5000: | |
90ad43b2 AC |
5071 | // start-sanitize-vr5400 |
5072 | *vr5400: | |
5073 | // end-sanitize-vr5400 | |
f2b30012 AC |
5074 | // start-sanitize-r5900 |
5075 | *r5900: | |
5076 | // end-sanitize-r5900 | |
5077 | ||
5078 | ||
5079 | 010000,10000,000000000000000,000010:COP0:32::TLBWI | |
5080 | "tlbwi" | |
23850e92 JL |
5081 | *mipsI,mipsII,mipsIII,mipsIV: |
5082 | *vr5000: | |
90ad43b2 AC |
5083 | // start-sanitize-vr5400 |
5084 | *vr5400: | |
5085 | // end-sanitize-vr5400 | |
f2b30012 AC |
5086 | // start-sanitize-r5900 |
5087 | *r5900: | |
5088 | // end-sanitize-r5900 | |
5089 | ||
5090 | ||
5091 | 010000,10000,000000000000000,000110:COP0:32::TLBWR | |
5092 | "tlbwr" | |
23850e92 JL |
5093 | *mipsI,mipsII,mipsIII,mipsIV: |
5094 | *vr5000: | |
90ad43b2 AC |
5095 | // start-sanitize-vr5400 |
5096 | *vr5400: | |
5097 | // end-sanitize-vr5400 | |
f2b30012 AC |
5098 | // start-sanitize-r5900 |
5099 | *r5900: | |
5100 | // end-sanitize-r5900 | |
5101 | ||
5102 | \f | |
a48e8c8d | 5103 | :include:16::m16.igen |
16bd5d6e | 5104 | // start-sanitize-vr5400 |
89d09738 | 5105 | :include::vr5400:vr5400.igen |
a48e8c8d | 5106 | :include:64,f::mdmx.igen |
16bd5d6e | 5107 | // end-sanitize-vr5400 |
f2b30012 | 5108 | // start-sanitize-r5900 |
89d09738 | 5109 | :include::r5900:r5900.igen |
f2b30012 AC |
5110 | // end-sanitize-r5900 |
5111 | \f | |
5112 | // start-sanitize-cygnus-never | |
5113 | ||
49a6eed5 AC |
5114 | // // FIXME FIXME FIXME What is this instruction? |
5115 | // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT> | |
5116 | // *mipsI: | |
5117 | // *mipsII: | |
5118 | // *mipsIII: | |
5119 | // *mipsIV: | |
5120 | // // start-sanitize-r5900 | |
5121 | // *r5900: | |
5122 | // // end-sanitize-r5900 | |
5123 | // *r3900: | |
5124 | // // start-sanitize-tx19 | |
5125 | // *tx19: | |
5126 | // // end-sanitize-tx19 | |
5127 | // { | |
5128 | // unsigned32 instruction = instruction_0; | |
055ee297 AC |
5129 | // signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16); |
5130 | // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; | |
5131 | // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
49a6eed5 AC |
5132 | // { |
5133 | // if (CoProcPresent(3)) | |
5134 | // SignalException(CoProcessorUnusable); | |
5135 | // else | |
5136 | // SignalException(ReservedInstruction,instruction); | |
5137 | // } | |
5138 | // } | |
5139 | ||
5140 | // end-sanitize-cygnus-never | |
5141 | // start-sanitize-cygnus-never | |
5142 | ||
5143 | // // FIXME FIXME FIXME What is this? | |
5144 | // 11100,******,00001:RR:16::SDBBP | |
5145 | // *mips16: | |
5146 | // { | |
5147 | // unsigned32 instruction = instruction_0; | |
5148 | // if (have_extendval) | |
5149 | // SignalException (ReservedInstruction, instruction); | |
5150 | // { | |
5151 | // SignalException(DebugBreakPoint,instruction); | |
5152 | // } | |
5153 | // } | |
f2b30012 AC |
5154 | |
5155 | // end-sanitize-cygnus-never | |
5156 | // start-sanitize-cygnus-never | |
5157 | ||
49a6eed5 AC |
5158 | // // FIXME FIXME FIXME What is this? |
5159 | // 000000,********************,001110:SPECIAL:32::SDBBP | |
5160 | // *r3900: | |
5161 | // { | |
5162 | // unsigned32 instruction = instruction_0; | |
5163 | // { | |
5164 | // SignalException(DebugBreakPoint,instruction); | |
5165 | // } | |
5166 | // } | |
f2b30012 AC |
5167 | |
5168 | // end-sanitize-cygnus-never | |
5169 | // start-sanitize-cygnus-never | |
5170 | ||
49a6eed5 AC |
5171 | // // FIXME FIXME FIXME This apparently belongs to the vr4100 which |
5172 | // // isn't yet reconized by this simulator. | |
5173 | // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16 | |
5174 | // *vr4100: | |
5175 | // { | |
5176 | // unsigned32 instruction = instruction_0; | |
055ee297 AC |
5177 | // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; |
5178 | // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
49a6eed5 AC |
5179 | // { |
5180 | // CHECKHILO("Multiply-Add"); | |
5181 | // { | |
5182 | // unsigned64 temp = (op1 * op2); | |
5183 | // temp += (SET64HI(VL4_8(HI)) | VL4_8(LO)); | |
5184 | // LO = SIGNEXTEND((unsigned64)VL4_8(temp),32); | |
5185 | // HI = SIGNEXTEND((unsigned64)VH4_8(temp),32); | |
5186 | // } | |
5187 | // } | |
5188 | // } | |
f2b30012 AC |
5189 | |
5190 | // end-sanitize-cygnus-never | |
49a6eed5 AC |
5191 | // start-sanitize-cygnus-never |
5192 | ||
5193 | // // FIXME FIXME FIXME This apparently belongs to the vr4100 which | |
5194 | // // isn't yet reconized by this simulator. | |
5195 | // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16 | |
5196 | // *vr4100: | |
5197 | // { | |
5198 | // unsigned32 instruction = instruction_0; | |
055ee297 AC |
5199 | // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)]; |
5200 | // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)]; | |
49a6eed5 AC |
5201 | // { |
5202 | // CHECKHILO("Multiply-Add"); | |
5203 | // { | |
5204 | // unsigned64 temp = (op1 * op2); | |
5205 | // LO = LO + temp; | |
5206 | // } | |
5207 | // } | |
5208 | // } | |
5209 | ||
a48e8c8d | 5210 | // end-sanitize-cygnus-never |