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2002-03-01 Chris Demetriou <cgd@broadcom.com>
[deliverable/binutils-gdb.git] / sim / mips / mips.igen
CommitLineData
c906108c
SS		 1// -*- C -*-
2//
3// In mips.igen, the semantics for many of the instructions were created
4// using code generated by gencode. Those semantic segments could be
5// greatly simplified.
6//
7// <insn> ::=
8// <insn-word> { "+" <insn-word> }
9// ":" <format-name>
10// ":" <filter-flags>
11// ":" <options>
12// ":" <name>
13// <nl>
14// { <insn-model> }
15// { <insn-mnemonic> }
16// <code-block>
17//
18
19
20// IGEN config - mips16
21// :option:16::insn-bit-size:16
22// :option:16::hi-bit-nr:15
23:option:16::insn-specifying-widths:true
24:option:16::gen-delayed-branch:false
25
26// IGEN config - mips32/64..
27// :option:32::insn-bit-size:32
28// :option:32::hi-bit-nr:31
29:option:32::insn-specifying-widths:true
30:option:32::gen-delayed-branch:false
31
32
33// Generate separate simulators for each target
34// :option:::multi-sim:true
35
36
074e9cb8 37// Models known by this simulator are defined below.
c5d00cc7
CD		 38//
39// When placing models in the instruction descriptions, please place
40// them one per line, in the order given here.
074e9cb8
CD		 41
42// MIPS ISAs:
43//
44// Instructions and related functions for these models are included in
45// this file.
c906108c
SS		 46:model:::mipsI:mips3000:
47:model:::mipsII:mips6000:
48:model:::mipsIII:mips4000:
49:model:::mipsIV:mips8000:
603a98e7 50:model:::mipsV:mipsisaV:
074e9cb8
CD		 51
52// Vendor ISAs:
53//
54// Standard MIPS ISA instructions used for these models are listed here,
55// as are functions needed by those standard instructions. Instructions
56// which are model-dependent and which are not in the standard MIPS ISAs
57// (or which pre-date or use different encodings than the standard
58// instructions) are (for the most part) in separate .igen files.
59:model:::vr4100:mips4100: // vr.igen
c906108c 60:model:::vr5000:mips5000:
074e9cb8 61:model:::r3900:mips3900: // tx.igen
c906108c 62
074e9cb8
CD		 63// MIPS Application Specific Extensions (ASEs)
64//
65// Instructions for the ASEs are in separate .igen files.
66:model:::mips16:mips16: // m16.igen (and m16.dc)
c906108c
SS		 67
68
69// Pseudo instructions known by IGEN
70:internal::::illegal:
71{
72 SignalException (ReservedInstruction, 0);
73}
74
75
76// Pseudo instructions known by interp.c
77// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
78000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
79"rsvd <OP>"
80{
81 SignalException (ReservedInstruction, instruction_0);
82}
83
84
85
86// Helper:
87//
88// Simulate a 32 bit delayslot instruction
89//
90
91:function:::address_word:delayslot32:address_word target
92{
93 instruction_word delay_insn;
94 sim_events_slip (SD, 1);
95 DSPC = CIA;
96 CIA = CIA + 4; /* NOTE not mips16 */
97 STATE |= simDELAYSLOT;
98 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
d4f3574e 99 ENGINE_ISSUE_PREFIX_HOOK();
c906108c
SS		 100 idecode_issue (CPU_, delay_insn, (CIA));
101 STATE &= ~simDELAYSLOT;
102 return target;
103}
104
105:function:::address_word:nullify_next_insn32:
106{
107 sim_events_slip (SD, 1);
108 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
109 return CIA + 8;
110}
111
112// Helper:
113//
114// Check that an access to a HI/LO register meets timing requirements
115//
116// The following requirements exist:
117//
118// - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
119// - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
120// - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
121// corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
122//
123
124:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
125{
126 if (history->mf.timestamp + 3 > time)
127 {
128 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
129 itable[MY_INDEX].name,
130 new, (long) CIA,
131 (long) history->mf.cia);
132 return 0;
133 }
134 return 1;
135}
136
137:function:::int:check_mt_hilo:hilo_history *history
c5d00cc7
CD		 138*mipsI:
139*mipsII:
140*mipsIII:
141*mipsIV:
603a98e7 142*mipsV:
c906108c
SS		 143*vr4100:
144*vr5000:
145{
146 signed64 time = sim_events_time (SD);
147 int ok = check_mf_cycles (SD_, history, time, "MT");
148 history->mt.timestamp = time;
149 history->mt.cia = CIA;
150 return ok;
151}
152
153:function:::int:check_mt_hilo:hilo_history *history
154*r3900:
155{
156 signed64 time = sim_events_time (SD);
157 history->mt.timestamp = time;
158 history->mt.cia = CIA;
159 return 1;
160}
161
162
163:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
c5d00cc7
CD		 164*mipsI:
165*mipsII:
166*mipsIII:
167*mipsIV:
603a98e7 168*mipsV:
c906108c
SS		 169*vr4100:
170*vr5000:
171*r3900:
172{
173 signed64 time = sim_events_time (SD);
174 int ok = 1;
175 if (peer != NULL
176 && peer->mt.timestamp > history->op.timestamp
177 && history->mt.timestamp < history->op.timestamp
178 && ! (history->mf.timestamp > history->op.timestamp
179 && history->mf.timestamp < peer->mt.timestamp)
180 && ! (peer->mf.timestamp > history->op.timestamp
181 && peer->mf.timestamp < peer->mt.timestamp))
182 {
183 /* The peer has been written to since the last OP yet we have
184 not */
185 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
186 itable[MY_INDEX].name,
187 (long) CIA,
188 (long) history->op.cia,
189 (long) peer->mt.cia);
190 ok = 0;
191 }
192 history->mf.timestamp = time;
193 history->mf.cia = CIA;
194 return ok;
195}
196
197
198
199:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
c5d00cc7
CD		 200*mipsI:
201*mipsII:
202*mipsIII:
203*mipsIV:
603a98e7 204*mipsV:
c906108c
SS		 205*vr4100:
206*vr5000:
207{
208 signed64 time = sim_events_time (SD);
209 int ok = (check_mf_cycles (SD_, hi, time, "OP")
210 && check_mf_cycles (SD_, lo, time, "OP"));
211 hi->op.timestamp = time;
212 lo->op.timestamp = time;
213 hi->op.cia = CIA;
214 lo->op.cia = CIA;
215 return ok;
216}
217
218// The r3900 mult and multu insns _can_ be exectuted immediatly after
219// a mf{hi,lo}
220:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
221*r3900:
222{
223 /* FIXME: could record the fact that a stall occured if we want */
224 signed64 time = sim_events_time (SD);
225 hi->op.timestamp = time;
226 lo->op.timestamp = time;
227 hi->op.cia = CIA;
228 lo->op.cia = CIA;
229 return 1;
230}
231
232
233:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
c5d00cc7
CD		 234*mipsI:
235*mipsII:
236*mipsIII:
237*mipsIV:
603a98e7 238*mipsV:
c906108c
SS		 239*vr4100:
240*vr5000:
241*r3900:
242{
243 signed64 time = sim_events_time (SD);
244 int ok = (check_mf_cycles (SD_, hi, time, "OP")
245 && check_mf_cycles (SD_, lo, time, "OP"));
246 hi->op.timestamp = time;
247 lo->op.timestamp = time;
248 hi->op.cia = CIA;
249 lo->op.cia = CIA;
250 return ok;
251}
252
253
ca971540
CD		 254// Helper:
255//
256// Check that the 64-bit instruction can currently be used, and signal
257// an ReservedInstruction exception if not.
258//
259
260:function:::void:check_u64:instruction_word insn
261*mipsIII:
262*mipsIV:
263*mipsV:
264*vr4100:
265*vr5000:
266{
267 // On mips64, if UserMode check SR:PX & SR:UX bits.
268 // The check should be similar to mips64 for any with PX/UX bit equivalents.
269}
c906108c
SS		 270
271
272
273//
074e9cb8 274// MIPS Architecture:
c906108c 275//
603a98e7 276// CPU Instruction Set (mipsI - mipsV)
c906108c
SS		 277//
278
279
280
281000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
282"add r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 283*mipsI:
284*mipsII:
285*mipsIII:
286*mipsIV:
603a98e7 287*mipsV:
c906108c
SS		 288*vr4100:
289*vr5000:
290*r3900:
291{
292 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
293 {
294 ALU32_BEGIN (GPR[RS]);
295 ALU32_ADD (GPR[RT]);
9805e229 296 ALU32_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 297 }
298 TRACE_ALU_RESULT (GPR[RD]);
299}
300
301
302
303001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
20ae0098 304"addi r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 305*mipsI:
306*mipsII:
307*mipsIII:
308*mipsIV:
603a98e7 309*mipsV:
c906108c
SS		 310*vr4100:
311*vr5000:
312*r3900:
313{
314 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
315 {
316 ALU32_BEGIN (GPR[RS]);
317 ALU32_ADD (EXTEND16 (IMMEDIATE));
9805e229 318 ALU32_END (GPR[RT]); /* This checks for overflow. */
c906108c
SS		 319 }
320 TRACE_ALU_RESULT (GPR[RT]);
321}
322
323
324
325:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
326{
327 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
328 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
329 TRACE_ALU_RESULT (GPR[rt]);
330}
331
332001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
333"addiu r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 334*mipsI:
335*mipsII:
336*mipsIII:
337*mipsIV:
603a98e7 338*mipsV:
c906108c
SS		 339*vr4100:
340*vr5000:
341*r3900:
342{
343 do_addiu (SD_, RS, RT, IMMEDIATE);
344}
345
346
347
348:function:::void:do_addu:int rs, int rt, int rd
349{
350 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
351 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
352 TRACE_ALU_RESULT (GPR[rd]);
353}
354
355000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
356"addu r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 357*mipsI:
358*mipsII:
359*mipsIII:
360*mipsIV:
603a98e7 361*mipsV:
c906108c
SS		 362*vr4100:
363*vr5000:
364*r3900:
365{
366 do_addu (SD_, RS, RT, RD);
367}
368
369
370
371:function:::void:do_and:int rs, int rt, int rd
372{
373 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
374 GPR[rd] = GPR[rs] & GPR[rt];
375 TRACE_ALU_RESULT (GPR[rd]);
376}
377
378000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
379"and r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 380*mipsI:
381*mipsII:
382*mipsIII:
383*mipsIV:
603a98e7 384*mipsV:
c906108c
SS		 385*vr4100:
386*vr5000:
387*r3900:
388{
389 do_and (SD_, RS, RT, RD);
390}
391
392
393
394001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
395"and r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 396*mipsI:
397*mipsII:
398*mipsIII:
399*mipsIV:
603a98e7 400*mipsV:
c906108c
SS		 401*vr4100:
402*vr5000:
403*r3900:
404{
405 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
406 GPR[RT] = GPR[RS] & IMMEDIATE;
407 TRACE_ALU_RESULT (GPR[RT]);
408}
409
410
411
412000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
413"beq r<RS>, r<RT>, <OFFSET>"
c5d00cc7
CD		 414*mipsI:
415*mipsII:
416*mipsIII:
417*mipsIV:
603a98e7 418*mipsV:
c906108c
SS		 419*vr4100:
420*vr5000:
421*r3900:
422{
423 address_word offset = EXTEND16 (OFFSET) << 2;
424 check_branch_bug ();
425 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
426 {
427 mark_branch_bug (NIA+offset);
428 DELAY_SLOT (NIA + offset);
429 }
430}
431
432
433
434010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
435"beql r<RS>, r<RT>, <OFFSET>"
436*mipsII:
437*mipsIII:
438*mipsIV:
603a98e7 439*mipsV:
c906108c
SS		 440*vr4100:
441*vr5000:
442*r3900:
443{
444 address_word offset = EXTEND16 (OFFSET) << 2;
445 check_branch_bug ();
446 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
447 {
448 mark_branch_bug (NIA+offset);
449 DELAY_SLOT (NIA + offset);
450 }
451 else
452 NULLIFY_NEXT_INSTRUCTION ();
453}
454
455
456
457000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
458"bgez r<RS>, <OFFSET>"
c5d00cc7
CD		 459*mipsI:
460*mipsII:
461*mipsIII:
462*mipsIV:
603a98e7 463*mipsV:
c906108c
SS		 464*vr4100:
465*vr5000:
466*r3900:
467{
468 address_word offset = EXTEND16 (OFFSET) << 2;
469 check_branch_bug ();
470 if ((signed_word) GPR[RS] >= 0)
471 {
472 mark_branch_bug (NIA+offset);
473 DELAY_SLOT (NIA + offset);
474 }
475}
476
477
478
479000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
480"bgezal r<RS>, <OFFSET>"
c5d00cc7
CD		 481*mipsI:
482*mipsII:
483*mipsIII:
484*mipsIV:
603a98e7 485*mipsV:
c906108c
SS		 486*vr4100:
487*vr5000:
488*r3900:
489{
490 address_word offset = EXTEND16 (OFFSET) << 2;
491 check_branch_bug ();
492 RA = (CIA + 8);
493 if ((signed_word) GPR[RS] >= 0)
494 {
495 mark_branch_bug (NIA+offset);
496 DELAY_SLOT (NIA + offset);
497 }
498}
499
500
501
502000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
503"bgezall r<RS>, <OFFSET>"
504*mipsII:
505*mipsIII:
506*mipsIV:
603a98e7 507*mipsV:
c906108c
SS		 508*vr4100:
509*vr5000:
510*r3900:
511{
512 address_word offset = EXTEND16 (OFFSET) << 2;
513 check_branch_bug ();
514 RA = (CIA + 8);
515 /* NOTE: The branch occurs AFTER the next instruction has been
516 executed */
517 if ((signed_word) GPR[RS] >= 0)
518 {
519 mark_branch_bug (NIA+offset);
520 DELAY_SLOT (NIA + offset);
521 }
522 else
523 NULLIFY_NEXT_INSTRUCTION ();
524}
525
526
527
528000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
529"bgezl r<RS>, <OFFSET>"
530*mipsII:
531*mipsIII:
532*mipsIV:
603a98e7 533*mipsV:
c906108c
SS		 534*vr4100:
535*vr5000:
536*r3900:
537{
538 address_word offset = EXTEND16 (OFFSET) << 2;
539 check_branch_bug ();
540 if ((signed_word) GPR[RS] >= 0)
541 {
542 mark_branch_bug (NIA+offset);
543 DELAY_SLOT (NIA + offset);
544 }
545 else
546 NULLIFY_NEXT_INSTRUCTION ();
547}
548
549
550
551000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
552"bgtz r<RS>, <OFFSET>"
c5d00cc7
CD		 553*mipsI:
554*mipsII:
555*mipsIII:
556*mipsIV:
603a98e7 557*mipsV:
c906108c
SS		 558*vr4100:
559*vr5000:
560*r3900:
561{
562 address_word offset = EXTEND16 (OFFSET) << 2;
563 check_branch_bug ();
564 if ((signed_word) GPR[RS] > 0)
565 {
566 mark_branch_bug (NIA+offset);
567 DELAY_SLOT (NIA + offset);
568 }
569}
570
571
572
573010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
574"bgtzl r<RS>, <OFFSET>"
575*mipsII:
576*mipsIII:
577*mipsIV:
603a98e7 578*mipsV:
c906108c
SS		 579*vr4100:
580*vr5000:
581*r3900:
582{
583 address_word offset = EXTEND16 (OFFSET) << 2;
584 check_branch_bug ();
585 /* NOTE: The branch occurs AFTER the next instruction has been
586 executed */
587 if ((signed_word) GPR[RS] > 0)
588 {
589 mark_branch_bug (NIA+offset);
590 DELAY_SLOT (NIA + offset);
591 }
592 else
593 NULLIFY_NEXT_INSTRUCTION ();
594}
595
596
597
598000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
599"blez r<RS>, <OFFSET>"
c5d00cc7
CD		 600*mipsI:
601*mipsII:
602*mipsIII:
603*mipsIV:
603a98e7 604*mipsV:
c906108c
SS		 605*vr4100:
606*vr5000:
607*r3900:
608{
609 address_word offset = EXTEND16 (OFFSET) << 2;
610 check_branch_bug ();
611 /* NOTE: The branch occurs AFTER the next instruction has been
612 executed */
613 if ((signed_word) GPR[RS] <= 0)
614 {
615 mark_branch_bug (NIA+offset);
616 DELAY_SLOT (NIA + offset);
617 }
618}
619
620
621
622010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
623"bgezl r<RS>, <OFFSET>"
624*mipsII:
625*mipsIII:
626*mipsIV:
603a98e7 627*mipsV:
c906108c
SS		 628*vr4100:
629*vr5000:
630*r3900:
631{
632 address_word offset = EXTEND16 (OFFSET) << 2;
633 check_branch_bug ();
634 if ((signed_word) GPR[RS] <= 0)
635 {
636 mark_branch_bug (NIA+offset);
637 DELAY_SLOT (NIA + offset);
638 }
639 else
640 NULLIFY_NEXT_INSTRUCTION ();
641}
642
643
644
645000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
646"bltz r<RS>, <OFFSET>"
c5d00cc7
CD		 647*mipsI:
648*mipsII:
649*mipsIII:
650*mipsIV:
603a98e7 651*mipsV:
c906108c
SS		 652*vr4100:
653*vr5000:
654*r3900:
655{
656 address_word offset = EXTEND16 (OFFSET) << 2;
657 check_branch_bug ();
658 if ((signed_word) GPR[RS] < 0)
659 {
660 mark_branch_bug (NIA+offset);
661 DELAY_SLOT (NIA + offset);
662 }
663}
664
665
666
667000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
668"bltzal r<RS>, <OFFSET>"
c5d00cc7
CD		 669*mipsI:
670*mipsII:
671*mipsIII:
672*mipsIV:
603a98e7 673*mipsV:
c906108c
SS		 674*vr4100:
675*vr5000:
676*r3900:
677{
678 address_word offset = EXTEND16 (OFFSET) << 2;
679 check_branch_bug ();
680 RA = (CIA + 8);
681 /* NOTE: The branch occurs AFTER the next instruction has been
682 executed */
683 if ((signed_word) GPR[RS] < 0)
684 {
685 mark_branch_bug (NIA+offset);
686 DELAY_SLOT (NIA + offset);
687 }
688}
689
690
691
692000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
693"bltzall r<RS>, <OFFSET>"
694*mipsII:
695*mipsIII:
696*mipsIV:
603a98e7 697*mipsV:
c906108c
SS		 698*vr4100:
699*vr5000:
700*r3900:
701{
702 address_word offset = EXTEND16 (OFFSET) << 2;
703 check_branch_bug ();
704 RA = (CIA + 8);
705 if ((signed_word) GPR[RS] < 0)
706 {
707 mark_branch_bug (NIA+offset);
708 DELAY_SLOT (NIA + offset);
709 }
710 else
711 NULLIFY_NEXT_INSTRUCTION ();
712}
713
714
715
716000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
717"bltzl r<RS>, <OFFSET>"
718*mipsII:
719*mipsIII:
720*mipsIV:
603a98e7 721*mipsV:
c906108c
SS		 722*vr4100:
723*vr5000:
724*r3900:
725{
726 address_word offset = EXTEND16 (OFFSET) << 2;
727 check_branch_bug ();
728 /* NOTE: The branch occurs AFTER the next instruction has been
729 executed */
730 if ((signed_word) GPR[RS] < 0)
731 {
732 mark_branch_bug (NIA+offset);
733 DELAY_SLOT (NIA + offset);
734 }
735 else
736 NULLIFY_NEXT_INSTRUCTION ();
737}
738
739
740
741000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
742"bne r<RS>, r<RT>, <OFFSET>"
c5d00cc7
CD		 743*mipsI:
744*mipsII:
745*mipsIII:
746*mipsIV:
603a98e7 747*mipsV:
c906108c
SS		 748*vr4100:
749*vr5000:
750*r3900:
751{
752 address_word offset = EXTEND16 (OFFSET) << 2;
753 check_branch_bug ();
754 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
755 {
756 mark_branch_bug (NIA+offset);
757 DELAY_SLOT (NIA + offset);
758 }
759}
760
761
762
763010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
764"bnel r<RS>, r<RT>, <OFFSET>"
765*mipsII:
766*mipsIII:
767*mipsIV:
603a98e7 768*mipsV:
c906108c
SS		 769*vr4100:
770*vr5000:
771*r3900:
772{
773 address_word offset = EXTEND16 (OFFSET) << 2;
774 check_branch_bug ();
775 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
776 {
777 mark_branch_bug (NIA+offset);
778 DELAY_SLOT (NIA + offset);
779 }
780 else
781 NULLIFY_NEXT_INSTRUCTION ();
782}
783
784
785
786000000,20.CODE,001101:SPECIAL:32::BREAK
20ae0098 787"break <CODE>"
c5d00cc7
CD		 788*mipsI:
789*mipsII:
790*mipsIII:
791*mipsIV:
603a98e7 792*mipsV:
c906108c
SS		 793*vr4100:
794*vr5000:
795*r3900:
796{
797 /* Check for some break instruction which are reserved for use by the simulator. */
798 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
799 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
800 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
801 {
802 sim_engine_halt (SD, CPU, NULL, cia,
803 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
804 }
805 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
806 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
807 {
808 if (STATE & simDELAYSLOT)
809 PC = cia - 4; /* reference the branch instruction */
810 else
811 PC = cia;
812 SignalException(BreakPoint, instruction_0);
813 }
814
815 else
816 {
817 /* If we get this far, we're not an instruction reserved by the sim. Raise
818 the exception. */
819 SignalException(BreakPoint, instruction_0);
820 }
821}
822
823
824
c906108c
SS		 825000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
826"dadd r<RD>, r<RS>, r<RT>"
827*mipsIII:
828*mipsIV:
603a98e7 829*mipsV:
c906108c
SS		 830*vr4100:
831*vr5000:
832{
ca971540 833 check_u64 (SD_, instruction_0);
c906108c
SS		 834 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
835 {
836 ALU64_BEGIN (GPR[RS]);
837 ALU64_ADD (GPR[RT]);
9805e229 838 ALU64_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 839 }
840 TRACE_ALU_RESULT (GPR[RD]);
841}
842
843
844
845011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
846"daddi r<RT>, r<RS>, <IMMEDIATE>"
847*mipsIII:
848*mipsIV:
603a98e7 849*mipsV:
c906108c
SS		 850*vr4100:
851*vr5000:
852{
ca971540 853 check_u64 (SD_, instruction_0);
c906108c
SS		 854 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
855 {
856 ALU64_BEGIN (GPR[RS]);
857 ALU64_ADD (EXTEND16 (IMMEDIATE));
9805e229 858 ALU64_END (GPR[RT]); /* This checks for overflow. */
c906108c
SS		 859 }
860 TRACE_ALU_RESULT (GPR[RT]);
861}
862
863
864
865:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
866{
867 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
868 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
869 TRACE_ALU_RESULT (GPR[rt]);
870}
871
872011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
20ae0098 873"daddiu r<RT>, r<RS>, <IMMEDIATE>"
c906108c
SS		 874*mipsIII:
875*mipsIV:
603a98e7 876*mipsV:
c906108c
SS		 877*vr4100:
878*vr5000:
879{
ca971540 880 check_u64 (SD_, instruction_0);
c906108c
SS		 881 do_daddiu (SD_, RS, RT, IMMEDIATE);
882}
883
884
885
886:function:::void:do_daddu:int rs, int rt, int rd
887{
888 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
889 GPR[rd] = GPR[rs] + GPR[rt];
890 TRACE_ALU_RESULT (GPR[rd]);
891}
892
893000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
894"daddu r<RD>, r<RS>, r<RT>"
895*mipsIII:
896*mipsIV:
603a98e7 897*mipsV:
c906108c
SS		 898*vr4100:
899*vr5000:
900{
ca971540 901 check_u64 (SD_, instruction_0);
c906108c
SS		 902 do_daddu (SD_, RS, RT, RD);
903}
904
905
906
907:function:::void:do_ddiv:int rs, int rt
908{
909 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
910 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
911 {
912 signed64 n = GPR[rs];
913 signed64 d = GPR[rt];
914 signed64 hi;
915 signed64 lo;
916 if (d == 0)
917 {
918 lo = SIGNED64 (0x8000000000000000);
919 hi = 0;
920 }
921 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
922 {
923 lo = SIGNED64 (0x8000000000000000);
924 hi = 0;
925 }
926 else
927 {
928 lo = (n / d);
929 hi = (n % d);
930 }
931 HI = hi;
932 LO = lo;
933 }
934 TRACE_ALU_RESULT2 (HI, LO);
935}
936
f701dad2 937000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
c906108c
SS		 938"ddiv r<RS>, r<RT>"
939*mipsIII:
940*mipsIV:
603a98e7 941*mipsV:
c906108c
SS		 942*vr4100:
943*vr5000:
944{
ca971540 945 check_u64 (SD_, instruction_0);
c906108c
SS		 946 do_ddiv (SD_, RS, RT);
947}
948
949
950
951:function:::void:do_ddivu:int rs, int rt
952{
953 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
954 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
955 {
956 unsigned64 n = GPR[rs];
957 unsigned64 d = GPR[rt];
958 unsigned64 hi;
959 unsigned64 lo;
960 if (d == 0)
961 {
962 lo = SIGNED64 (0x8000000000000000);
963 hi = 0;
964 }
965 else
966 {
967 lo = (n / d);
968 hi = (n % d);
969 }
970 HI = hi;
971 LO = lo;
972 }
973 TRACE_ALU_RESULT2 (HI, LO);
974}
975
976000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
977"ddivu r<RS>, r<RT>"
978*mipsIII:
979*mipsIV:
603a98e7 980*mipsV:
c906108c
SS		 981*vr4100:
982*vr5000:
983{
ca971540 984 check_u64 (SD_, instruction_0);
c906108c
SS		 985 do_ddivu (SD_, RS, RT);
986}
987
988
989
990:function:::void:do_div:int rs, int rt
991{
992 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
993 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
994 {
995 signed32 n = GPR[rs];
996 signed32 d = GPR[rt];
997 if (d == 0)
998 {
999 LO = EXTEND32 (0x80000000);
1000 HI = EXTEND32 (0);
1001 }
1002 else if (n == SIGNED32 (0x80000000) && d == -1)
1003 {
1004 LO = EXTEND32 (0x80000000);
1005 HI = EXTEND32 (0);
1006 }
1007 else
1008 {
1009 LO = EXTEND32 (n / d);
1010 HI = EXTEND32 (n % d);
1011 }
1012 }
1013 TRACE_ALU_RESULT2 (HI, LO);
1014}
1015
f701dad2 1016000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
c906108c 1017"div r<RS>, r<RT>"
c5d00cc7
CD		 1018*mipsI:
1019*mipsII:
1020*mipsIII:
1021*mipsIV:
603a98e7 1022*mipsV:
c906108c
SS		 1023*vr4100:
1024*vr5000:
1025*r3900:
1026{
1027 do_div (SD_, RS, RT);
1028}
1029
1030
1031
1032:function:::void:do_divu:int rs, int rt
1033{
1034 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1035 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1036 {
1037 unsigned32 n = GPR[rs];
1038 unsigned32 d = GPR[rt];
1039 if (d == 0)
1040 {
1041 LO = EXTEND32 (0x80000000);
1042 HI = EXTEND32 (0);
1043 }
1044 else
1045 {
1046 LO = EXTEND32 (n / d);
1047 HI = EXTEND32 (n % d);
1048 }
1049 }
1050 TRACE_ALU_RESULT2 (HI, LO);
1051}
1052
f701dad2 1053000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
c906108c 1054"divu r<RS>, r<RT>"
c5d00cc7
CD		 1055*mipsI:
1056*mipsII:
1057*mipsIII:
1058*mipsIV:
603a98e7 1059*mipsV:
c906108c
SS		 1060*vr4100:
1061*vr5000:
1062*r3900:
1063{
1064 do_divu (SD_, RS, RT);
1065}
1066
1067
1068
1069:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1070{
1071 unsigned64 lo;
1072 unsigned64 hi;
1073 unsigned64 m00;
1074 unsigned64 m01;
1075 unsigned64 m10;
1076 unsigned64 m11;
1077 unsigned64 mid;
1078 int sign;
1079 unsigned64 op1 = GPR[rs];
1080 unsigned64 op2 = GPR[rt];
1081 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1082 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1083 /* make signed multiply unsigned */
1084 sign = 0;
1085 if (signed_p)
1086 {
1087 if (op1 < 0)
1088 {
1089 op1 = - op1;
1090 ++sign;
1091 }
1092 if (op2 < 0)
1093 {
1094 op2 = - op2;
1095 ++sign;
1096 }
1097 }
67f5c7ef 1098 /* multiply out the 4 sub products */
c906108c
SS		 1099 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1100 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1101 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1102 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1103 /* add the products */
1104 mid = ((unsigned64) VH4_8 (m00)
1105 + (unsigned64) VL4_8 (m10)
1106 + (unsigned64) VL4_8 (m01));
1107 lo = U8_4 (mid, m00);
1108 hi = (m11
1109 + (unsigned64) VH4_8 (mid)
1110 + (unsigned64) VH4_8 (m01)
1111 + (unsigned64) VH4_8 (m10));
1112 /* fix the sign */
1113 if (sign & 1)
1114 {
1115 lo = -lo;
1116 if (lo == 0)
1117 hi = -hi;
1118 else
1119 hi = -hi - 1;
1120 }
1121 /* save the result HI/LO (and a gpr) */
1122 LO = lo;
1123 HI = hi;
1124 if (rd != 0)
1125 GPR[rd] = lo;
1126 TRACE_ALU_RESULT2 (HI, LO);
1127}
1128
1129:function:::void:do_dmult:int rs, int rt, int rd
1130{
1131 do_dmultx (SD_, rs, rt, rd, 1);
1132}
1133
f701dad2 1134000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
c906108c 1135"dmult r<RS>, r<RT>"
c5d00cc7
CD		 1136*mipsIII:
1137*mipsIV:
603a98e7 1138*mipsV:
c906108c
SS		 1139*vr4100:
1140{
ca971540 1141 check_u64 (SD_, instruction_0);
c906108c
SS		 1142 do_dmult (SD_, RS, RT, 0);
1143}
1144
f701dad2 1145000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
c906108c
SS		 1146"dmult r<RS>, r<RT>":RD == 0
1147"dmult r<RD>, r<RS>, r<RT>"
1148*vr5000:
1149{
ca971540 1150 check_u64 (SD_, instruction_0);
c906108c
SS		 1151 do_dmult (SD_, RS, RT, RD);
1152}
1153
1154
1155
1156:function:::void:do_dmultu:int rs, int rt, int rd
1157{
1158 do_dmultx (SD_, rs, rt, rd, 0);
1159}
1160
f701dad2 1161000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
c906108c 1162"dmultu r<RS>, r<RT>"
c5d00cc7
CD		 1163*mipsIII:
1164*mipsIV:
603a98e7 1165*mipsV:
c906108c
SS		 1166*vr4100:
1167{
ca971540 1168 check_u64 (SD_, instruction_0);
c906108c
SS		 1169 do_dmultu (SD_, RS, RT, 0);
1170}
1171
f701dad2 1172000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
c906108c
SS		 1173"dmultu r<RD>, r<RS>, r<RT>":RD == 0
1174"dmultu r<RS>, r<RT>"
1175*vr5000:
1176{
ca971540 1177 check_u64 (SD_, instruction_0);
c906108c
SS		 1178 do_dmultu (SD_, RS, RT, RD);
1179}
1180
1181:function:::void:do_dsll:int rt, int rd, int shift
1182{
fff8d27d 1183 TRACE_ALU_INPUT2 (GPR[rt], shift);
c906108c 1184 GPR[rd] = GPR[rt] << shift;
fff8d27d 1185 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 1186}
1187
1188:function:::void:do_dsllv:int rs, int rt, int rd
1189{
1190 int s = MASKED64 (GPR[rs], 5, 0);
fff8d27d 1191 TRACE_ALU_INPUT2 (GPR[rt], s);
c906108c 1192 GPR[rd] = GPR[rt] << s;
fff8d27d 1193 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 1194}
1195
1196
f701dad2 1197000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
c906108c
SS		 1198"dsll r<RD>, r<RT>, <SHIFT>"
1199*mipsIII:
1200*mipsIV:
603a98e7 1201*mipsV:
c906108c
SS		 1202*vr4100:
1203*vr5000:
1204{
ca971540 1205 check_u64 (SD_, instruction_0);
c906108c
SS		 1206 do_dsll (SD_, RT, RD, SHIFT);
1207}
1208
1209
f701dad2 1210000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
c906108c
SS		 1211"dsll32 r<RD>, r<RT>, <SHIFT>"
1212*mipsIII:
1213*mipsIV:
603a98e7 1214*mipsV:
c906108c
SS		 1215*vr4100:
1216*vr5000:
1217{
1218 int s = 32 + SHIFT;
ca971540 1219 check_u64 (SD_, instruction_0);
fff8d27d 1220 TRACE_ALU_INPUT2 (GPR[RT], s);
c906108c 1221 GPR[RD] = GPR[RT] << s;
fff8d27d 1222 TRACE_ALU_RESULT (GPR[RD]);
c906108c
SS		 1223}
1224
f701dad2 1225000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
c906108c
SS		 1226"dsllv r<RD>, r<RT>, r<RS>"
1227*mipsIII:
1228*mipsIV:
603a98e7 1229*mipsV:
c906108c
SS		 1230*vr4100:
1231*vr5000:
1232{
ca971540 1233 check_u64 (SD_, instruction_0);
c906108c
SS		 1234 do_dsllv (SD_, RS, RT, RD);
1235}
1236
1237:function:::void:do_dsra:int rt, int rd, int shift
1238{
fff8d27d 1239 TRACE_ALU_INPUT2 (GPR[rt], shift);
c906108c 1240 GPR[rd] = ((signed64) GPR[rt]) >> shift;
fff8d27d 1241 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 1242}
1243
1244
f701dad2 1245000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
c906108c
SS		 1246"dsra r<RD>, r<RT>, <SHIFT>"
1247*mipsIII:
1248*mipsIV:
603a98e7 1249*mipsV:
c906108c
SS		 1250*vr4100:
1251*vr5000:
1252{
ca971540 1253 check_u64 (SD_, instruction_0);
c906108c
SS		 1254 do_dsra (SD_, RT, RD, SHIFT);
1255}
1256
1257
f701dad2 1258000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
bb22bd7d 1259"dsra32 r<RD>, r<RT>, <SHIFT>"
c906108c
SS		 1260*mipsIII:
1261*mipsIV:
603a98e7 1262*mipsV:
c906108c
SS		 1263*vr4100:
1264*vr5000:
1265{
1266 int s = 32 + SHIFT;
ca971540 1267 check_u64 (SD_, instruction_0);
fff8d27d 1268 TRACE_ALU_INPUT2 (GPR[RT], s);
c906108c 1269 GPR[RD] = ((signed64) GPR[RT]) >> s;
fff8d27d 1270 TRACE_ALU_RESULT (GPR[RD]);
c906108c
SS		 1271}
1272
1273
1274:function:::void:do_dsrav:int rs, int rt, int rd
1275{
1276 int s = MASKED64 (GPR[rs], 5, 0);
1277 TRACE_ALU_INPUT2 (GPR[rt], s);
1278 GPR[rd] = ((signed64) GPR[rt]) >> s;
1279 TRACE_ALU_RESULT (GPR[rd]);
1280}
1281
f701dad2 1282000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
bb22bd7d 1283"dsrav r<RD>, r<RT>, r<RS>"
c906108c
SS		 1284*mipsIII:
1285*mipsIV:
603a98e7 1286*mipsV:
c906108c
SS		 1287*vr4100:
1288*vr5000:
1289{
ca971540 1290 check_u64 (SD_, instruction_0);
c906108c
SS		 1291 do_dsrav (SD_, RS, RT, RD);
1292}
1293
1294:function:::void:do_dsrl:int rt, int rd, int shift
1295{
fff8d27d 1296 TRACE_ALU_INPUT2 (GPR[rt], shift);
c906108c 1297 GPR[rd] = (unsigned64) GPR[rt] >> shift;
fff8d27d 1298 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 1299}
1300
1301
f701dad2 1302000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
c906108c
SS		 1303"dsrl r<RD>, r<RT>, <SHIFT>"
1304*mipsIII:
1305*mipsIV:
603a98e7 1306*mipsV:
c906108c
SS		 1307*vr4100:
1308*vr5000:
1309{
ca971540 1310 check_u64 (SD_, instruction_0);
c906108c
SS		 1311 do_dsrl (SD_, RT, RD, SHIFT);
1312}
1313
1314
f701dad2 1315000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
c906108c
SS		 1316"dsrl32 r<RD>, r<RT>, <SHIFT>"
1317*mipsIII:
1318*mipsIV:
603a98e7 1319*mipsV:
c906108c
SS		 1320*vr4100:
1321*vr5000:
1322{
1323 int s = 32 + SHIFT;
ca971540 1324 check_u64 (SD_, instruction_0);
fff8d27d 1325 TRACE_ALU_INPUT2 (GPR[RT], s);
c906108c 1326 GPR[RD] = (unsigned64) GPR[RT] >> s;
fff8d27d 1327 TRACE_ALU_RESULT (GPR[RD]);
c906108c
SS		 1328}
1329
1330
1331:function:::void:do_dsrlv:int rs, int rt, int rd
1332{
1333 int s = MASKED64 (GPR[rs], 5, 0);
fff8d27d 1334 TRACE_ALU_INPUT2 (GPR[rt], s);
c906108c 1335 GPR[rd] = (unsigned64) GPR[rt] >> s;
fff8d27d 1336 TRACE_ALU_RESULT (GPR[rd]);
c906108c
SS		 1337}
1338
1339
1340
f701dad2 1341000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
20ae0098 1342"dsrlv r<RD>, r<RT>, r<RS>"
c906108c
SS		 1343*mipsIII:
1344*mipsIV:
603a98e7 1345*mipsV:
c906108c
SS		 1346*vr4100:
1347*vr5000:
1348{
ca971540 1349 check_u64 (SD_, instruction_0);
c906108c
SS		 1350 do_dsrlv (SD_, RS, RT, RD);
1351}
1352
1353
f701dad2 1354000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
c906108c
SS		 1355"dsub r<RD>, r<RS>, r<RT>"
1356*mipsIII:
1357*mipsIV:
603a98e7 1358*mipsV:
c906108c
SS		 1359*vr4100:
1360*vr5000:
1361{
ca971540 1362 check_u64 (SD_, instruction_0);
c906108c
SS		 1363 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1364 {
1365 ALU64_BEGIN (GPR[RS]);
1366 ALU64_SUB (GPR[RT]);
9805e229 1367 ALU64_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 1368 }
1369 TRACE_ALU_RESULT (GPR[RD]);
1370}
1371
1372
1373:function:::void:do_dsubu:int rs, int rt, int rd
1374{
1375 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1376 GPR[rd] = GPR[rs] - GPR[rt];
1377 TRACE_ALU_RESULT (GPR[rd]);
1378}
1379
f701dad2 1380000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
c906108c
SS		 1381"dsubu r<RD>, r<RS>, r<RT>"
1382*mipsIII:
1383*mipsIV:
603a98e7 1384*mipsV:
c906108c
SS		 1385*vr4100:
1386*vr5000:
1387{
ca971540 1388 check_u64 (SD_, instruction_0);
c906108c
SS		 1389 do_dsubu (SD_, RS, RT, RD);
1390}
1391
1392
1393000010,26.INSTR_INDEX:NORMAL:32::J
1394"j <INSTR_INDEX>"
c5d00cc7
CD		 1395*mipsI:
1396*mipsII:
1397*mipsIII:
1398*mipsIV:
603a98e7 1399*mipsV:
c906108c
SS		 1400*vr4100:
1401*vr5000:
1402*r3900:
1403{
1404 /* NOTE: The region used is that of the delay slot NIA and NOT the
1405 current instruction */
1406 address_word region = (NIA & MASK (63, 28));
1407 DELAY_SLOT (region | (INSTR_INDEX << 2));
1408}
1409
1410
1411000011,26.INSTR_INDEX:NORMAL:32::JAL
1412"jal <INSTR_INDEX>"
c5d00cc7
CD		 1413*mipsI:
1414*mipsII:
1415*mipsIII:
1416*mipsIV:
603a98e7 1417*mipsV:
c906108c
SS		 1418*vr4100:
1419*vr5000:
1420*r3900:
1421{
1422 /* NOTE: The region used is that of the delay slot and NOT the
1423 current instruction */
1424 address_word region = (NIA & MASK (63, 28));
1425 GPR[31] = CIA + 8;
1426 DELAY_SLOT (region | (INSTR_INDEX << 2));
1427}
1428
f701dad2 1429000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
c906108c
SS		 1430"jalr r<RS>":RD == 31
1431"jalr r<RD>, r<RS>"
c5d00cc7
CD		 1432*mipsI:
1433*mipsII:
1434*mipsIII:
1435*mipsIV:
603a98e7 1436*mipsV:
c906108c
SS		 1437*vr4100:
1438*vr5000:
1439*r3900:
1440{
1441 address_word temp = GPR[RS];
1442 GPR[RD] = CIA + 8;
1443 DELAY_SLOT (temp);
1444}
1445
1446
f701dad2 1447000000,5.RS,000000000000000,001000:SPECIAL:32::JR
c906108c 1448"jr r<RS>"
c5d00cc7
CD		 1449*mipsI:
1450*mipsII:
1451*mipsIII:
1452*mipsIV:
603a98e7 1453*mipsV:
c906108c
SS		 1454*vr4100:
1455*vr5000:
1456*r3900:
1457{
1458 DELAY_SLOT (GPR[RS]);
1459}
1460
1461
1462:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1463{
1464 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1465 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1466 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1467 unsigned int byte;
1468 address_word paddr;
1469 int uncached;
1470 unsigned64 memval;
1471 address_word vaddr;
1472
1473 vaddr = base + offset;
1474 if ((vaddr & access) != 0)
1475 {
1476 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1477 }
1478 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1479 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1480 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1481 byte = ((vaddr & mask) ^ bigendiancpu);
1482 return (memval >> (8 * byte));
1483}
1484
1c47a468
CD		 1485:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1486{
1487 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1488 address_word reverseendian = (ReverseEndian ? -1 : 0);
1489 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1490 unsigned int byte;
1491 unsigned int word;
1492 address_word paddr;
1493 int uncached;
1494 unsigned64 memval;
1495 address_word vaddr;
1496 int nr_lhs_bits;
1497 int nr_rhs_bits;
1498 unsigned_word lhs_mask;
1499 unsigned_word temp;
1500
1501 vaddr = base + offset;
1502 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1503 paddr = (paddr ^ (reverseendian & mask));
1504 if (BigEndianMem == 0)
1505 paddr = paddr & ~access;
1506
1507 /* compute where within the word/mem we are */
1508 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1509 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1510 nr_lhs_bits = 8 * byte + 8;
1511 nr_rhs_bits = 8 * access - 8 * byte;
1512 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1513
1514 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1515 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1516 (long) ((unsigned64) paddr >> 32), (long) paddr,
1517 word, byte, nr_lhs_bits, nr_rhs_bits); */
1518
1519 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1520 if (word == 0)
1521 {
1522 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1523 temp = (memval << nr_rhs_bits);
1524 }
1525 else
1526 {
1527 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1528 temp = (memval >> nr_lhs_bits);
1529 }
1530 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1531 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1532
1533 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1534 (long) ((unsigned64) memval >> 32), (long) memval,
1535 (long) ((unsigned64) temp >> 32), (long) temp,
1536 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1537 (long) (rt >> 32), (long) rt); */
1538 return rt;
1539}
1540
1541:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1542{
1543 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1544 address_word reverseendian = (ReverseEndian ? -1 : 0);
1545 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1546 unsigned int byte;
1547 address_word paddr;
1548 int uncached;
1549 unsigned64 memval;
1550 address_word vaddr;
1551
1552 vaddr = base + offset;
1553 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1554 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1555 paddr = (paddr ^ (reverseendian & mask));
1556 if (BigEndianMem != 0)
1557 paddr = paddr & ~access;
1558 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1559 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
1560 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1561 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1562 (long) paddr, byte, (long) paddr, (long) memval); */
1563 {
1564 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1565 rt &= ~screen;
1566 rt |= (memval >> (8 * byte)) & screen;
1567 }
1568 return rt;
1569}
1570
c906108c
SS		 1571
1572100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1573"lb r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 1574*mipsI:
1575*mipsII:
1576*mipsIII:
1577*mipsIV:
603a98e7 1578*mipsV:
c906108c
SS		 1579*vr4100:
1580*vr5000:
1581*r3900:
1582{
1583 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1584}
1585
1586
1587100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1588"lbu r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 1589*mipsI:
1590*mipsII:
1591*mipsIII:
1592*mipsIV:
603a98e7 1593*mipsV:
c906108c
SS		 1594*vr4100:
1595*vr5000:
1596*r3900:
1597{
1598 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1599}
1600
1601
1602110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1603"ld r<RT>, <OFFSET>(r<BASE>)"
1604*mipsIII:
1605*mipsIV:
603a98e7 1606*mipsV:
c906108c
SS		 1607*vr4100:
1608*vr5000:
1609{
ca971540 1610 check_u64 (SD_, instruction_0);
c906108c
SS		 1611 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1612}
1613
1614
16151101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1616"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1617*mipsII:
1618*mipsIII:
1619*mipsIV:
603a98e7 1620*mipsV:
c906108c
SS		 1621*vr4100:
1622*vr5000:
1623*r3900:
1624{
1625 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1626}
1627
1628
1629
1630
1631011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1632"ldl r<RT>, <OFFSET>(r<BASE>)"
1633*mipsIII:
1634*mipsIV:
603a98e7 1635*mipsV:
c906108c
SS		 1636*vr4100:
1637*vr5000:
1638{
ca971540 1639 check_u64 (SD_, instruction_0);
c906108c
SS		 1640 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1641}
1642
1643
1644011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1645"ldr r<RT>, <OFFSET>(r<BASE>)"
1646*mipsIII:
1647*mipsIV:
603a98e7 1648*mipsV:
c906108c
SS		 1649*vr4100:
1650*vr5000:
1651{
ca971540 1652 check_u64 (SD_, instruction_0);
c906108c
SS		 1653 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1654}
1655
1656
1657100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1658"lh r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 1659*mipsI:
1660*mipsII:
1661*mipsIII:
1662*mipsIV:
603a98e7 1663*mipsV:
c906108c
SS		 1664*vr4100:
1665*vr5000:
1666*r3900:
1667{
1668 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1669}
1670
1671
1672100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1673"lhu r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 1674*mipsI:
1675*mipsII:
1676*mipsIII:
1677*mipsIV:
603a98e7 1678*mipsV:
c906108c
SS		 1679*vr4100:
1680*vr5000:
1681*r3900:
1682{
1683 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1684}
1685
1686
1687110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1688"ll r<RT>, <OFFSET>(r<BASE>)"
1689*mipsII:
1690*mipsIII:
1691*mipsIV:
603a98e7 1692*mipsV:
c906108c
SS		 1693*vr4100:
1694*vr5000:
1695{
1696 unsigned32 instruction = instruction_0;
1697 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1698 int destreg = ((instruction >> 16) & 0x0000001F);
1699 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1700 {
1701 address_word vaddr = ((unsigned64)op1 + offset);
1702 address_word paddr;
1703 int uncached;
1704 if ((vaddr & 3) != 0)
1705 {
1706 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
1707 }
1708 else
1709 {
1710 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1711 {
1712 unsigned64 memval = 0;
1713 unsigned64 memval1 = 0;
1714 unsigned64 mask = 0x7;
1715 unsigned int shift = 2;
1716 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1717 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1718 unsigned int byte;
1719 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1720 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1721 byte = ((vaddr & mask) ^ (bigend << shift));
1722 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1723 LLBIT = 1;
1724 }
1725 }
1726 }
1727}
1728
1729
1730110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1731"lld r<RT>, <OFFSET>(r<BASE>)"
1732*mipsIII:
1733*mipsIV:
603a98e7 1734*mipsV:
c906108c
SS		 1735*vr4100:
1736*vr5000:
1737{
1738 unsigned32 instruction = instruction_0;
1739 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1740 int destreg = ((instruction >> 16) & 0x0000001F);
1741 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
ca971540 1742 check_u64 (SD_, instruction_0);
c906108c
SS		 1743 {
1744 address_word vaddr = ((unsigned64)op1 + offset);
1745 address_word paddr;
1746 int uncached;
1747 if ((vaddr & 7) != 0)
1748 {
1749 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
1750 }
1751 else
1752 {
1753 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1754 {
1755 unsigned64 memval = 0;
1756 unsigned64 memval1 = 0;
1757 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1758 GPR[destreg] = memval;
1759 LLBIT = 1;
1760 }
1761 }
1762 }
1763}
1764
1765
1766001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1767"lui r<RT>, <IMMEDIATE>"
c5d00cc7
CD		 1768*mipsI:
1769*mipsII:
1770*mipsIII:
1771*mipsIV:
603a98e7 1772*mipsV:
c906108c
SS		 1773*vr4100:
1774*vr5000:
1775*r3900:
1776{
1777 TRACE_ALU_INPUT1 (IMMEDIATE);
1778 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1779 TRACE_ALU_RESULT (GPR[RT]);
1780}
1781
1782
1783100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1784"lw r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 1785*mipsI:
1786*mipsII:
1787*mipsIII:
1788*mipsIV:
603a98e7 1789*mipsV:
c906108c
SS		 1790*vr4100:
1791*vr5000:
1792*r3900:
1793{
1794 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1795}
1796
1797
17981100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1799"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 1800*mipsI:
1801*mipsII:
1802*mipsIII:
1803*mipsIV:
603a98e7 1804*mipsV:
c906108c
SS		 1805*vr4100:
1806*vr5000:
1807*r3900:
1808{
1809 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1810}
1811
1812
c906108c
SS		 1813100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1814"lwl r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 1815*mipsI:
1816*mipsII:
1817*mipsIII:
1818*mipsIV:
603a98e7 1819*mipsV:
c906108c
SS		 1820*vr4100:
1821*vr5000:
1822*r3900:
1823{
7a292a7a 1824 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
c906108c
SS		 1825}
1826
1827
c906108c
SS		 1828100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1829"lwr r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 1830*mipsI:
1831*mipsII:
1832*mipsIII:
1833*mipsIV:
603a98e7 1834*mipsV:
c906108c
SS		 1835*vr4100:
1836*vr5000:
1837*r3900:
1838{
1839 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1840}
1841
1842
bb22bd7d 1843100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
c906108c
SS		 1844"lwu r<RT>, <OFFSET>(r<BASE>)"
1845*mipsIII:
1846*mipsIV:
603a98e7 1847*mipsV:
c906108c
SS		 1848*vr4100:
1849*vr5000:
1850{
ca971540 1851 check_u64 (SD_, instruction_0);
c906108c
SS		 1852 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
1853}
1854
1855
1856:function:::void:do_mfhi:int rd
1857{
1858 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
1859 TRACE_ALU_INPUT1 (HI);
1860 GPR[rd] = HI;
1861 TRACE_ALU_RESULT (GPR[rd]);
1862}
1863
1864000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1865"mfhi r<RD>"
c5d00cc7
CD		 1866*mipsI:
1867*mipsII:
1868*mipsIII:
1869*mipsIV:
603a98e7 1870*mipsV:
c906108c
SS		 1871*vr4100:
1872*vr5000:
1873*r3900:
1874{
1875 do_mfhi (SD_, RD);
1876}
1877
1878
1879
1880:function:::void:do_mflo:int rd
1881{
1882 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
1883 TRACE_ALU_INPUT1 (LO);
1884 GPR[rd] = LO;
1885 TRACE_ALU_RESULT (GPR[rd]);
1886}
1887
1888000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
1889"mflo r<RD>"
c5d00cc7
CD		 1890*mipsI:
1891*mipsII:
1892*mipsIII:
1893*mipsIV:
603a98e7 1894*mipsV:
c906108c
SS		 1895*vr4100:
1896*vr5000:
1897*r3900:
1898{
1899 do_mflo (SD_, RD);
1900}
1901
1902
1903
f701dad2 1904000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
c906108c
SS		 1905"movn r<RD>, r<RS>, r<RT>"
1906*mipsIV:
603a98e7 1907*mipsV:
c906108c
SS		 1908*vr5000:
1909{
1910 if (GPR[RT] != 0)
1911 GPR[RD] = GPR[RS];
1912}
1913
1914
1915
f701dad2 1916000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
c906108c
SS		 1917"movz r<RD>, r<RS>, r<RT>"
1918*mipsIV:
603a98e7 1919*mipsV:
c906108c
SS		 1920*vr5000:
1921{
1922 if (GPR[RT] == 0)
1923 GPR[RD] = GPR[RS];
1924}
1925
1926
1927
1928000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
1929"mthi r<RS>"
c5d00cc7
CD		 1930*mipsI:
1931*mipsII:
1932*mipsIII:
1933*mipsIV:
603a98e7 1934*mipsV:
c906108c
SS		 1935*vr4100:
1936*vr5000:
1937*r3900:
1938{
1939 check_mt_hilo (SD_, HIHISTORY);
1940 HI = GPR[RS];
1941}
1942
1943
1944
f701dad2 1945000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
c906108c 1946"mtlo r<RS>"
c5d00cc7
CD		 1947*mipsI:
1948*mipsII:
1949*mipsIII:
1950*mipsIV:
603a98e7 1951*mipsV:
c906108c
SS		 1952*vr4100:
1953*vr5000:
1954*r3900:
1955{
1956 check_mt_hilo (SD_, LOHISTORY);
1957 LO = GPR[RS];
1958}
1959
1960
1961
1962:function:::void:do_mult:int rs, int rt, int rd
1963{
1964 signed64 prod;
1965 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1966 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1967 prod = (((signed64)(signed32) GPR[rs])
1968 * ((signed64)(signed32) GPR[rt]));
1969 LO = EXTEND32 (VL4_8 (prod));
1970 HI = EXTEND32 (VH4_8 (prod));
1971 if (rd != 0)
1972 GPR[rd] = LO;
1973 TRACE_ALU_RESULT2 (HI, LO);
1974}
1975
f701dad2 1976000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
c906108c 1977"mult r<RS>, r<RT>"
c5d00cc7
CD		 1978*mipsI:
1979*mipsII:
1980*mipsIII:
1981*mipsIV:
603a98e7 1982*mipsV:
c906108c
SS		 1983*vr4100:
1984{
1985 do_mult (SD_, RS, RT, 0);
1986}
1987
1988
f701dad2 1989000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
9846de1b 1990"mult r<RS>, r<RT>":RD == 0
c906108c
SS		 1991"mult r<RD>, r<RS>, r<RT>"
1992*vr5000:
1993*r3900:
1994{
1995 do_mult (SD_, RS, RT, RD);
1996}
1997
1998
1999:function:::void:do_multu:int rs, int rt, int rd
2000{
2001 unsigned64 prod;
2002 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2003 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2004 prod = (((unsigned64)(unsigned32) GPR[rs])
2005 * ((unsigned64)(unsigned32) GPR[rt]));
2006 LO = EXTEND32 (VL4_8 (prod));
2007 HI = EXTEND32 (VH4_8 (prod));
2008 if (rd != 0)
2009 GPR[rd] = LO;
2010 TRACE_ALU_RESULT2 (HI, LO);
2011}
2012
f701dad2 2013000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
c906108c 2014"multu r<RS>, r<RT>"
c5d00cc7
CD		 2015*mipsI:
2016*mipsII:
2017*mipsIII:
2018*mipsIV:
603a98e7 2019*mipsV:
c906108c
SS		 2020*vr4100:
2021{
cff3e48b 2022 do_multu (SD_, RS, RT, 0);
c906108c
SS		 2023}
2024
f701dad2 2025000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
9846de1b 2026"multu r<RS>, r<RT>":RD == 0
c906108c
SS		 2027"multu r<RD>, r<RS>, r<RT>"
2028*vr5000:
2029*r3900:
2030{
cff3e48b 2031 do_multu (SD_, RS, RT, RD);
c906108c
SS		 2032}
2033
2034
2035:function:::void:do_nor:int rs, int rt, int rd
2036{
2037 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2038 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2039 TRACE_ALU_RESULT (GPR[rd]);
2040}
2041
2042000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2043"nor r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 2044*mipsI:
2045*mipsII:
2046*mipsIII:
2047*mipsIV:
603a98e7 2048*mipsV:
c906108c
SS		 2049*vr4100:
2050*vr5000:
2051*r3900:
2052{
2053 do_nor (SD_, RS, RT, RD);
2054}
2055
2056
2057:function:::void:do_or:int rs, int rt, int rd
2058{
2059 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2060 GPR[rd] = (GPR[rs] | GPR[rt]);
2061 TRACE_ALU_RESULT (GPR[rd]);
2062}
2063
2064000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2065"or r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 2066*mipsI:
2067*mipsII:
2068*mipsIII:
2069*mipsIV:
603a98e7 2070*mipsV:
c906108c
SS		 2071*vr4100:
2072*vr5000:
2073*r3900:
2074{
2075 do_or (SD_, RS, RT, RD);
2076}
2077
2078
2079
2080:function:::void:do_ori:int rs, int rt, unsigned immediate
2081{
2082 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2083 GPR[rt] = (GPR[rs] | immediate);
2084 TRACE_ALU_RESULT (GPR[rt]);
2085}
2086
2087001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2088"ori r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 2089*mipsI:
2090*mipsII:
2091*mipsIII:
2092*mipsIV:
603a98e7 2093*mipsV:
c906108c
SS		 2094*vr4100:
2095*vr5000:
2096*r3900:
2097{
2098 do_ori (SD_, RS, RT, IMMEDIATE);
2099}
2100
2101
af5107af
CD		 2102110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2103"pref <HINT>, <OFFSET>(r<BASE>)"
c906108c 2104*mipsIV:
603a98e7 2105*mipsV:
c906108c
SS		 2106*vr5000:
2107{
2108 unsigned32 instruction = instruction_0;
2109 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2110 int hint = ((instruction >> 16) & 0x0000001F);
2111 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2112 {
2113 address_word vaddr = ((unsigned64)op1 + offset);
2114 address_word paddr;
2115 int uncached;
2116 {
2117 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2118 Prefetch(uncached,paddr,vaddr,isDATA,hint);
2119 }
2120 }
2121}
2122
1c47a468 2123
c906108c
SS		 2124:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2125{
2126 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2127 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2128 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2129 unsigned int byte;
2130 address_word paddr;
2131 int uncached;
2132 unsigned64 memval;
2133 address_word vaddr;
2134
2135 vaddr = base + offset;
2136 if ((vaddr & access) != 0)
2137 {
2138 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2139 }
2140 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2141 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2142 byte = ((vaddr & mask) ^ bigendiancpu);
2143 memval = (word << (8 * byte));
2144 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2145}
2146
1c47a468
CD		 2147:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2148{
2149 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2150 address_word reverseendian = (ReverseEndian ? -1 : 0);
2151 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2152 unsigned int byte;
2153 unsigned int word;
2154 address_word paddr;
2155 int uncached;
2156 unsigned64 memval;
2157 address_word vaddr;
2158 int nr_lhs_bits;
2159 int nr_rhs_bits;
2160
2161 vaddr = base + offset;
2162 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2163 paddr = (paddr ^ (reverseendian & mask));
2164 if (BigEndianMem == 0)
2165 paddr = paddr & ~access;
2166
2167 /* compute where within the word/mem we are */
2168 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2169 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2170 nr_lhs_bits = 8 * byte + 8;
2171 nr_rhs_bits = 8 * access - 8 * byte;
2172 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2173 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2174 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2175 (long) ((unsigned64) paddr >> 32), (long) paddr,
2176 word, byte, nr_lhs_bits, nr_rhs_bits); */
2177
2178 if (word == 0)
2179 {
2180 memval = (rt >> nr_rhs_bits);
2181 }
2182 else
2183 {
2184 memval = (rt << nr_lhs_bits);
2185 }
2186 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2187 (long) ((unsigned64) rt >> 32), (long) rt,
2188 (long) ((unsigned64) memval >> 32), (long) memval); */
2189 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2190}
2191
2192:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2193{
2194 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2195 address_word reverseendian = (ReverseEndian ? -1 : 0);
2196 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2197 unsigned int byte;
2198 address_word paddr;
2199 int uncached;
2200 unsigned64 memval;
2201 address_word vaddr;
2202
2203 vaddr = base + offset;
2204 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2205 paddr = (paddr ^ (reverseendian & mask));
2206 if (BigEndianMem != 0)
2207 paddr &= ~access;
2208 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2209 memval = (rt << (byte * 8));
2210 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2211}
2212
c906108c
SS		 2213
2214101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2215"sb r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2216*mipsI:
2217*mipsII:
2218*mipsIII:
2219*mipsIV:
603a98e7 2220*mipsV:
c906108c
SS		 2221*vr4100:
2222*vr5000:
2223*r3900:
2224{
2225 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2226}
2227
2228
2229111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2230"sc r<RT>, <OFFSET>(r<BASE>)"
2231*mipsII:
2232*mipsIII:
2233*mipsIV:
603a98e7 2234*mipsV:
c906108c
SS		 2235*vr4100:
2236*vr5000:
2237{
2238 unsigned32 instruction = instruction_0;
2239 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2240 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2241 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2242 {
2243 address_word vaddr = ((unsigned64)op1 + offset);
2244 address_word paddr;
2245 int uncached;
2246 if ((vaddr & 3) != 0)
2247 {
2248 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2249 }
2250 else
2251 {
2252 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2253 {
2254 unsigned64 memval = 0;
2255 unsigned64 memval1 = 0;
2256 unsigned64 mask = 0x7;
2257 unsigned int byte;
2258 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2259 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2260 memval = ((unsigned64) op2 << (8 * byte));
2261 if (LLBIT)
2262 {
2263 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2264 }
2265 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2266 }
2267 }
2268 }
2269}
2270
2271
2272111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2273"scd r<RT>, <OFFSET>(r<BASE>)"
2274*mipsIII:
2275*mipsIV:
603a98e7 2276*mipsV:
c906108c
SS		 2277*vr4100:
2278*vr5000:
2279{
2280 unsigned32 instruction = instruction_0;
2281 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2282 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2283 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
ca971540 2284 check_u64 (SD_, instruction_0);
c906108c
SS		 2285 {
2286 address_word vaddr = ((unsigned64)op1 + offset);
2287 address_word paddr;
2288 int uncached;
2289 if ((vaddr & 7) != 0)
2290 {
2291 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2292 }
2293 else
2294 {
2295 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2296 {
2297 unsigned64 memval = 0;
2298 unsigned64 memval1 = 0;
2299 memval = op2;
2300 if (LLBIT)
2301 {
2302 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2303 }
2304 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2305 }
2306 }
2307 }
2308}
2309
2310
2311111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2312"sd r<RT>, <OFFSET>(r<BASE>)"
2313*mipsIII:
2314*mipsIV:
603a98e7 2315*mipsV:
c906108c
SS		 2316*vr4100:
2317*vr5000:
2318{
ca971540 2319 check_u64 (SD_, instruction_0);
c906108c
SS		 2320 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2321}
2322
2323
23241111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2325"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2326*mipsII:
2327*mipsIII:
2328*mipsIV:
603a98e7 2329*mipsV:
c906108c
SS		 2330*vr4100:
2331*vr5000:
2332{
2333 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2334}
2335
2336
2337101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2338"sdl r<RT>, <OFFSET>(r<BASE>)"
2339*mipsIII:
2340*mipsIV:
603a98e7 2341*mipsV:
c906108c
SS		 2342*vr4100:
2343*vr5000:
2344{
ca971540 2345 check_u64 (SD_, instruction_0);
c906108c
SS		 2346 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2347}
2348
2349
2350101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2351"sdr r<RT>, <OFFSET>(r<BASE>)"
2352*mipsIII:
2353*mipsIV:
603a98e7 2354*mipsV:
c906108c
SS		 2355*vr4100:
2356*vr5000:
2357{
ca971540 2358 check_u64 (SD_, instruction_0);
c906108c
SS		 2359 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2360}
2361
2362
2363101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2364"sh r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2365*mipsI:
2366*mipsII:
2367*mipsIII:
2368*mipsIV:
603a98e7 2369*mipsV:
c906108c
SS		 2370*vr4100:
2371*vr5000:
2372*r3900:
2373{
2374 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2375}
2376
2377
2378:function:::void:do_sll:int rt, int rd, int shift
2379{
2380 unsigned32 temp = (GPR[rt] << shift);
2381 TRACE_ALU_INPUT2 (GPR[rt], shift);
2382 GPR[rd] = EXTEND32 (temp);
2383 TRACE_ALU_RESULT (GPR[rd]);
2384}
2385
f701dad2 2386000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
20ae0098 2387"nop":RD == 0 && RT == 0 && SHIFT == 0
c906108c 2388"sll r<RD>, r<RT>, <SHIFT>"
c5d00cc7
CD		 2389*mipsI:
2390*mipsII:
2391*mipsIII:
2392*mipsIV:
603a98e7 2393*mipsV:
c906108c
SS		 2394*vr4100:
2395*vr5000:
2396*r3900:
2397{
20ae0098
CD		 2398 /* Skip shift for NOP, so that there won't be lots of extraneous
2399 trace output. */
2400 if (RD != 0 || RT != 0 || SHIFT != 0)
2401 do_sll (SD_, RT, RD, SHIFT);
c906108c
SS		 2402}
2403
2404
2405:function:::void:do_sllv:int rs, int rt, int rd
2406{
2407 int s = MASKED (GPR[rs], 4, 0);
2408 unsigned32 temp = (GPR[rt] << s);
2409 TRACE_ALU_INPUT2 (GPR[rt], s);
2410 GPR[rd] = EXTEND32 (temp);
2411 TRACE_ALU_RESULT (GPR[rd]);
2412}
2413
f701dad2 2414000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
c906108c 2415"sllv r<RD>, r<RT>, r<RS>"
c5d00cc7
CD		 2416*mipsI:
2417*mipsII:
2418*mipsIII:
2419*mipsIV:
603a98e7 2420*mipsV:
c906108c
SS		 2421*vr4100:
2422*vr5000:
2423*r3900:
2424{
2425 do_sllv (SD_, RS, RT, RD);
2426}
2427
2428
2429:function:::void:do_slt:int rs, int rt, int rd
2430{
2431 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2432 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2433 TRACE_ALU_RESULT (GPR[rd]);
2434}
2435
f701dad2 2436000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
c906108c 2437"slt r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 2438*mipsI:
2439*mipsII:
2440*mipsIII:
2441*mipsIV:
603a98e7 2442*mipsV:
c906108c
SS		 2443*vr4100:
2444*vr5000:
2445*r3900:
2446{
2447 do_slt (SD_, RS, RT, RD);
2448}
2449
2450
2451:function:::void:do_slti:int rs, int rt, unsigned16 immediate
2452{
2453 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2454 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2455 TRACE_ALU_RESULT (GPR[rt]);
2456}
2457
2458001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2459"slti r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 2460*mipsI:
2461*mipsII:
2462*mipsIII:
2463*mipsIV:
603a98e7 2464*mipsV:
c906108c
SS		 2465*vr4100:
2466*vr5000:
2467*r3900:
2468{
2469 do_slti (SD_, RS, RT, IMMEDIATE);
2470}
2471
2472
2473:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2474{
2475 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2476 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2477 TRACE_ALU_RESULT (GPR[rt]);
2478}
2479
2480001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2481"sltiu r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 2482*mipsI:
2483*mipsII:
2484*mipsIII:
2485*mipsIV:
603a98e7 2486*mipsV:
c906108c
SS		 2487*vr4100:
2488*vr5000:
2489*r3900:
2490{
2491 do_sltiu (SD_, RS, RT, IMMEDIATE);
2492}
2493
2494
2495
2496:function:::void:do_sltu:int rs, int rt, int rd
2497{
2498 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2499 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2500 TRACE_ALU_RESULT (GPR[rd]);
2501}
2502
f701dad2 2503000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
c906108c 2504"sltu r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 2505*mipsI:
2506*mipsII:
2507*mipsIII:
2508*mipsIV:
603a98e7 2509*mipsV:
c906108c
SS		 2510*vr4100:
2511*vr5000:
2512*r3900:
2513{
2514 do_sltu (SD_, RS, RT, RD);
2515}
2516
2517
2518:function:::void:do_sra:int rt, int rd, int shift
2519{
2520 signed32 temp = (signed32) GPR[rt] >> shift;
2521 TRACE_ALU_INPUT2 (GPR[rt], shift);
2522 GPR[rd] = EXTEND32 (temp);
2523 TRACE_ALU_RESULT (GPR[rd]);
2524}
2525
2526000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2527"sra r<RD>, r<RT>, <SHIFT>"
c5d00cc7
CD		 2528*mipsI:
2529*mipsII:
2530*mipsIII:
2531*mipsIV:
603a98e7 2532*mipsV:
c906108c
SS		 2533*vr4100:
2534*vr5000:
2535*r3900:
2536{
2537 do_sra (SD_, RT, RD, SHIFT);
2538}
2539
2540
2541
2542:function:::void:do_srav:int rs, int rt, int rd
2543{
2544 int s = MASKED (GPR[rs], 4, 0);
2545 signed32 temp = (signed32) GPR[rt] >> s;
2546 TRACE_ALU_INPUT2 (GPR[rt], s);
2547 GPR[rd] = EXTEND32 (temp);
2548 TRACE_ALU_RESULT (GPR[rd]);
2549}
2550
f701dad2 2551000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
c906108c 2552"srav r<RD>, r<RT>, r<RS>"
c5d00cc7
CD		 2553*mipsI:
2554*mipsII:
2555*mipsIII:
2556*mipsIV:
603a98e7 2557*mipsV:
c906108c
SS		 2558*vr4100:
2559*vr5000:
2560*r3900:
2561{
2562 do_srav (SD_, RS, RT, RD);
2563}
2564
2565
2566
2567:function:::void:do_srl:int rt, int rd, int shift
2568{
2569 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2570 TRACE_ALU_INPUT2 (GPR[rt], shift);
2571 GPR[rd] = EXTEND32 (temp);
2572 TRACE_ALU_RESULT (GPR[rd]);
2573}
2574
2575000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2576"srl r<RD>, r<RT>, <SHIFT>"
c5d00cc7
CD		 2577*mipsI:
2578*mipsII:
2579*mipsIII:
2580*mipsIV:
603a98e7 2581*mipsV:
c906108c
SS		 2582*vr4100:
2583*vr5000:
2584*r3900:
2585{
2586 do_srl (SD_, RT, RD, SHIFT);
2587}
2588
2589
2590:function:::void:do_srlv:int rs, int rt, int rd
2591{
2592 int s = MASKED (GPR[rs], 4, 0);
2593 unsigned32 temp = (unsigned32) GPR[rt] >> s;
2594 TRACE_ALU_INPUT2 (GPR[rt], s);
2595 GPR[rd] = EXTEND32 (temp);
2596 TRACE_ALU_RESULT (GPR[rd]);
2597}
2598
f701dad2 2599000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
c906108c 2600"srlv r<RD>, r<RT>, r<RS>"
c5d00cc7
CD		 2601*mipsI:
2602*mipsII:
2603*mipsIII:
2604*mipsIV:
603a98e7 2605*mipsV:
c906108c
SS		 2606*vr4100:
2607*vr5000:
2608*r3900:
2609{
2610 do_srlv (SD_, RS, RT, RD);
2611}
2612
2613
f701dad2 2614000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
c906108c 2615"sub r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 2616*mipsI:
2617*mipsII:
2618*mipsIII:
2619*mipsIV:
603a98e7 2620*mipsV:
c906108c
SS		 2621*vr4100:
2622*vr5000:
2623*r3900:
2624{
2625 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2626 {
2627 ALU32_BEGIN (GPR[RS]);
2628 ALU32_SUB (GPR[RT]);
9805e229 2629 ALU32_END (GPR[RD]); /* This checks for overflow. */
c906108c
SS		 2630 }
2631 TRACE_ALU_RESULT (GPR[RD]);
2632}
2633
2634
2635:function:::void:do_subu:int rs, int rt, int rd
2636{
2637 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2638 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
2639 TRACE_ALU_RESULT (GPR[rd]);
2640}
2641
f701dad2 2642000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
c906108c 2643"subu r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 2644*mipsI:
2645*mipsII:
2646*mipsIII:
2647*mipsIV:
603a98e7 2648*mipsV:
c906108c
SS		 2649*vr4100:
2650*vr5000:
2651*r3900:
2652{
2653 do_subu (SD_, RS, RT, RD);
2654}
2655
2656
2657101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2658"sw r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2659*mipsI:
2660*mipsII:
2661*mipsIII:
2662*mipsIV:
603a98e7 2663*mipsV:
c906108c
SS		 2664*vr4100:
2665*r3900:
2666*vr5000:
2667{
2668 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2669}
2670
2671
26721110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2673"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2674*mipsI:
2675*mipsII:
2676*mipsIII:
2677*mipsIV:
603a98e7 2678*mipsV:
c906108c
SS		 2679*vr4100:
2680*vr5000:
2681*r3900:
2682{
2683 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
2684}
2685
2686
c906108c
SS		 2687101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2688"swl r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2689*mipsI:
2690*mipsII:
2691*mipsIII:
2692*mipsIV:
603a98e7 2693*mipsV:
c906108c
SS		 2694*vr4100:
2695*vr5000:
2696*r3900:
2697{
2698 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2699}
2700
2701
c906108c
SS		 2702101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
2703"swr r<RT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 2704*mipsI:
2705*mipsII:
2706*mipsIII:
2707*mipsIV:
603a98e7 2708*mipsV:
c906108c
SS		 2709*vr4100:
2710*vr5000:
2711*r3900:
2712{
2713 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2714}
2715
2716
f701dad2 2717000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
c906108c
SS		 2718"sync":STYPE == 0
2719"sync <STYPE>"
2720*mipsII:
2721*mipsIII:
2722*mipsIV:
603a98e7 2723*mipsV:
c906108c
SS		 2724*vr4100:
2725*vr5000:
2726*r3900:
2727{
2728 SyncOperation (STYPE);
2729}
2730
2731
2732000000,20.CODE,001100:SPECIAL:32::SYSCALL
2733"syscall <CODE>"
c5d00cc7
CD		 2734*mipsI:
2735*mipsII:
2736*mipsIII:
2737*mipsIV:
603a98e7 2738*mipsV:
c906108c
SS		 2739*vr4100:
2740*vr5000:
2741*r3900:
2742{
2743 SignalException(SystemCall, instruction_0);
2744}
2745
2746
2747000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
2748"teq r<RS>, r<RT>"
2749*mipsII:
2750*mipsIII:
2751*mipsIV:
603a98e7 2752*mipsV:
c906108c
SS		 2753*vr4100:
2754*vr5000:
2755{
2756 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
2757 SignalException(Trap, instruction_0);
2758}
2759
2760
2761000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
2762"teqi r<RS>, <IMMEDIATE>"
2763*mipsII:
2764*mipsIII:
2765*mipsIV:
603a98e7 2766*mipsV:
c906108c
SS		 2767*vr4100:
2768*vr5000:
2769{
2770 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
2771 SignalException(Trap, instruction_0);
2772}
2773
2774
2775000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
2776"tge r<RS>, r<RT>"
2777*mipsII:
2778*mipsIII:
2779*mipsIV:
603a98e7 2780*mipsV:
c906108c
SS		 2781*vr4100:
2782*vr5000:
2783{
2784 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
2785 SignalException(Trap, instruction_0);
2786}
2787
2788
2789000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
2790"tgei r<RS>, <IMMEDIATE>"
2791*mipsII:
2792*mipsIII:
2793*mipsIV:
603a98e7 2794*mipsV:
c906108c
SS		 2795*vr4100:
2796*vr5000:
2797{
2798 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
2799 SignalException(Trap, instruction_0);
2800}
2801
2802
2803000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
2804"tgeiu r<RS>, <IMMEDIATE>"
2805*mipsII:
2806*mipsIII:
2807*mipsIV:
603a98e7 2808*mipsV:
c906108c
SS		 2809*vr4100:
2810*vr5000:
2811{
2812 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
2813 SignalException(Trap, instruction_0);
2814}
2815
2816
2817000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
2818"tgeu r<RS>, r<RT>"
2819*mipsII:
2820*mipsIII:
2821*mipsIV:
603a98e7 2822*mipsV:
c906108c
SS		 2823*vr4100:
2824*vr5000:
2825{
2826 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
2827 SignalException(Trap, instruction_0);
2828}
2829
2830
2831000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
2832"tlt r<RS>, r<RT>"
2833*mipsII:
2834*mipsIII:
2835*mipsIV:
603a98e7 2836*mipsV:
c906108c
SS		 2837*vr4100:
2838*vr5000:
2839{
2840 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
2841 SignalException(Trap, instruction_0);
2842}
2843
2844
2845000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
2846"tlti r<RS>, <IMMEDIATE>"
2847*mipsII:
2848*mipsIII:
2849*mipsIV:
603a98e7 2850*mipsV:
c906108c
SS		 2851*vr4100:
2852*vr5000:
2853{
2854 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
2855 SignalException(Trap, instruction_0);
2856}
2857
2858
2859000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
2860"tltiu r<RS>, <IMMEDIATE>"
2861*mipsII:
2862*mipsIII:
2863*mipsIV:
603a98e7 2864*mipsV:
c906108c
SS		 2865*vr4100:
2866*vr5000:
2867{
2868 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
2869 SignalException(Trap, instruction_0);
2870}
2871
2872
2873000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
2874"tltu r<RS>, r<RT>"
2875*mipsII:
2876*mipsIII:
2877*mipsIV:
603a98e7 2878*mipsV:
c906108c
SS		 2879*vr4100:
2880*vr5000:
2881{
2882 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
2883 SignalException(Trap, instruction_0);
2884}
2885
2886
2887000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
2888"tne r<RS>, r<RT>"
2889*mipsII:
2890*mipsIII:
2891*mipsIV:
603a98e7 2892*mipsV:
c906108c
SS		 2893*vr4100:
2894*vr5000:
2895{
2896 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2897 SignalException(Trap, instruction_0);
2898}
2899
2900
2901000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
2902"tne r<RS>, <IMMEDIATE>"
2903*mipsII:
2904*mipsIII:
2905*mipsIV:
603a98e7 2906*mipsV:
c906108c
SS		 2907*vr4100:
2908*vr5000:
2909{
2910 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
2911 SignalException(Trap, instruction_0);
2912}
2913
2914
2915:function:::void:do_xor:int rs, int rt, int rd
2916{
2917 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2918 GPR[rd] = GPR[rs] ^ GPR[rt];
2919 TRACE_ALU_RESULT (GPR[rd]);
2920}
2921
f701dad2 2922000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
c906108c 2923"xor r<RD>, r<RS>, r<RT>"
c5d00cc7
CD		 2924*mipsI:
2925*mipsII:
2926*mipsIII:
2927*mipsIV:
603a98e7 2928*mipsV:
c906108c
SS		 2929*vr4100:
2930*vr5000:
2931*r3900:
2932{
2933 do_xor (SD_, RS, RT, RD);
2934}
2935
2936
2937:function:::void:do_xori:int rs, int rt, unsigned16 immediate
2938{
2939 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2940 GPR[rt] = GPR[rs] ^ immediate;
2941 TRACE_ALU_RESULT (GPR[rt]);
2942}
2943
2944001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
2945"xori r<RT>, r<RS>, <IMMEDIATE>"
c5d00cc7
CD		 2946*mipsI:
2947*mipsII:
2948*mipsIII:
2949*mipsIV:
603a98e7 2950*mipsV:
c906108c
SS		 2951*vr4100:
2952*vr5000:
2953*r3900:
2954{
2955 do_xori (SD_, RS, RT, IMMEDIATE);
2956}
2957
2958\f
2959//
2960// MIPS Architecture:
2961//
2962// FPU Instruction Set (COP1 & COP1X)
2963//
2964
2965
2966:%s::::FMT:int fmt
2967{
2968 switch (fmt)
2969 {
2970 case fmt_single: return "s";
2971 case fmt_double: return "d";
2972 case fmt_word: return "w";
2973 case fmt_long: return "l";
2974 default: return "?";
2975 }
2976}
2977
2978:%s::::X:int x
2979{
2980 switch (x)
2981 {
2982 case 0: return "f";
2983 case 1: return "t";
2984 default: return "?";
2985 }
2986}
2987
2988:%s::::TF:int tf
2989{
2990 if (tf)
2991 return "t";
2992 else
2993 return "f";
2994}
2995
2996:%s::::ND:int nd
2997{
2998 if (nd)
2999 return "l";
3000 else
3001 return "";
3002}
3003
3004:%s::::COND:int cond
3005{
3006 switch (cond)
3007 {
3008 case 00: return "f";
3009 case 01: return "un";
3010 case 02: return "eq";
3011 case 03: return "ueq";
3012 case 04: return "olt";
3013 case 05: return "ult";
3014 case 06: return "ole";
3015 case 07: return "ule";
3016 case 010: return "sf";
3017 case 011: return "ngle";
3018 case 012: return "seq";
3019 case 013: return "ngl";
3020 case 014: return "lt";
3021 case 015: return "nge";
3022 case 016: return "le";
3023 case 017: return "ngt";
3024 default: return "?";
3025 }
3026}
3027
ca971540
CD		 3028// Helper:
3029//
3030// Check that the FPU is currently usable, and signal a CoProcessorUnusable
3031// exception if not.
3032//
3033
3034:function:::void:check_fpu:
3035*mipsI:
3036*mipsII:
3037*mipsIII:
3038*mipsIV:
3039*mipsV:
3040*vr4100:
3041*vr5000:
3042*r3900:
3043{
3044#if 0 /* XXX FIXME: For now, never treat the FPU as disabled. */
3045 if (! COP_Usable (1))
3046 SignalExceptionCoProcessorUnusable (1);
3047#endif
3048}
3049
c906108c
SS		 3050
3051010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3052"abs.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 3053*mipsI:
3054*mipsII:
3055*mipsIII:
3056*mipsIV:
603a98e7 3057*mipsV:
c906108c
SS		 3058*vr4100:
3059*vr5000:
3060*r3900:
3061{
3062 unsigned32 instruction = instruction_0;
3063 int destreg = ((instruction >> 6) & 0x0000001F);
3064 int fs = ((instruction >> 11) & 0x0000001F);
3065 int format = ((instruction >> 21) & 0x00000007);
ca971540 3066 check_fpu(SD_);
c906108c
SS		 3067 {
3068 if ((format != fmt_single) && (format != fmt_double))
3069 SignalException(ReservedInstruction,instruction);
3070 else
3071 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3072 }
3073}
3074
3075
3076
3077010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3078"add.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 3079*mipsI:
3080*mipsII:
3081*mipsIII:
3082*mipsIV:
603a98e7 3083*mipsV:
c906108c
SS		 3084*vr4100:
3085*vr5000:
3086*r3900:
3087{
3088 unsigned32 instruction = instruction_0;
3089 int destreg = ((instruction >> 6) & 0x0000001F);
3090 int fs = ((instruction >> 11) & 0x0000001F);
3091 int ft = ((instruction >> 16) & 0x0000001F);
3092 int format = ((instruction >> 21) & 0x00000007);
ca971540 3093 check_fpu(SD_);
c906108c
SS		 3094 {
3095 if ((format != fmt_single) && (format != fmt_double))
3096 SignalException(ReservedInstruction, instruction);
3097 else
3098 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3099 }
3100}
3101
3102
3103
3104// BC1F
3105// BC1FL
3106// BC1T
3107// BC1TL
3108
3109010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3110"bc1%s<TF>%s<ND> <OFFSET>"
c5d00cc7
CD		 3111*mipsI:
3112*mipsII:
3113*mipsIII:
c906108c 3114{
ca971540 3115 check_fpu(SD_);
c906108c
SS		 3116 check_branch_bug ();
3117 TRACE_BRANCH_INPUT (PREVCOC1());
3118 if (PREVCOC1() == TF)
3119 {
3120 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3121 TRACE_BRANCH_RESULT (dest);
3122 mark_branch_bug (dest);
3123 DELAY_SLOT (dest);
3124 }
3125 else if (ND)
3126 {
3127 TRACE_BRANCH_RESULT (0);
3128 NULLIFY_NEXT_INSTRUCTION ();
3129 }
3130 else
3131 {
3132 TRACE_BRANCH_RESULT (NIA);
3133 }
3134}
3135
3136010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3137"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3138"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3139*mipsIV:
603a98e7 3140*mipsV:
c906108c 3141#*vr4100:
074e9cb8 3142*vr5000:
c906108c
SS		 3143*r3900:
3144{
ca971540 3145 check_fpu(SD_);
c906108c
SS		 3146 check_branch_bug ();
3147 if (GETFCC(CC) == TF)
3148 {
3149 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3150 mark_branch_bug (dest);
3151 DELAY_SLOT (dest);
3152 }
3153 else if (ND)
3154 {
3155 NULLIFY_NEXT_INSTRUCTION ();
3156 }
3157}
3158
3159
3160
3161
3162
3163
3164// C.EQ.S
3165// C.EQ.D
3166// ...
3167
3168:function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3169{
3170 if ((fmt != fmt_single) && (fmt != fmt_double))
3171 SignalException (ReservedInstruction, insn);
3172 else
3173 {
3174 int less;
3175 int equal;
3176 int unordered;
3177 int condition;
3178 unsigned64 ofs = ValueFPR (fs, fmt);
3179 unsigned64 oft = ValueFPR (ft, fmt);
3180 if (NaN (ofs, fmt) || NaN (oft, fmt))
3181 {
3182 if (FCSR & FP_ENABLE (IO))
3183 {
3184 FCSR |= FP_CAUSE (IO);
3185 SignalExceptionFPE ();
3186 }
3187 less = 0;
3188 equal = 0;
3189 unordered = 1;
3190 }
3191 else
3192 {
3193 less = Less (ofs, oft, fmt);
3194 equal = Equal (ofs, oft, fmt);
3195 unordered = 0;
3196 }
3197 condition = (((cond & (1 << 2)) && less)
3198 || ((cond & (1 << 1)) && equal)
3199 || ((cond & (1 << 0)) && unordered));
3200 SETFCC (cc, condition);
3201 }
3202}
3203
eb5fcf93 3204010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
c906108c 3205"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
c5d00cc7
CD		 3206*mipsI:
3207*mipsII:
3208*mipsIII:
c906108c 3209{
ca971540 3210 check_fpu(SD_);
c906108c
SS		 3211 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
3212}
3213
eb5fcf93 3214010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
c906108c
SS		 3215"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3216"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3217*mipsIV:
603a98e7 3218*mipsV:
c906108c
SS		 3219*vr4100:
3220*vr5000:
3221*r3900:
3222{
ca971540 3223 check_fpu(SD_);
c906108c
SS		 3224 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
3225}
3226
3227
eb5fcf93 3228010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
c906108c
SS		 3229"ceil.l.%s<FMT> f<FD>, f<FS>"
3230*mipsIII:
3231*mipsIV:
603a98e7 3232*mipsV:
c906108c
SS		 3233*vr4100:
3234*vr5000:
3235*r3900:
3236{
3237 unsigned32 instruction = instruction_0;
3238 int destreg = ((instruction >> 6) & 0x0000001F);
3239 int fs = ((instruction >> 11) & 0x0000001F);
3240 int format = ((instruction >> 21) & 0x00000007);
ca971540 3241 check_fpu(SD_);
c906108c
SS		 3242 {
3243 if ((format != fmt_single) && (format != fmt_double))
3244 SignalException(ReservedInstruction,instruction);
3245 else
3246 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3247 }
3248}
3249
3250
eb5fcf93 3251010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
c906108c
SS		 3252*mipsII:
3253*mipsIII:
3254*mipsIV:
603a98e7 3255*mipsV:
c906108c
SS		 3256*vr4100:
3257*vr5000:
3258*r3900:
3259{
3260 unsigned32 instruction = instruction_0;
3261 int destreg = ((instruction >> 6) & 0x0000001F);
3262 int fs = ((instruction >> 11) & 0x0000001F);
3263 int format = ((instruction >> 21) & 0x00000007);
ca971540 3264 check_fpu(SD_);
c906108c
SS		 3265 {
3266 if ((format != fmt_single) && (format != fmt_double))
3267 SignalException(ReservedInstruction,instruction);
3268 else
3269 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3270 }
3271}
3272
3273
3274// CFC1
3275// CTC1
eb5fcf93 3276010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32,f::CxC1
c906108c
SS		 3277"c%s<X>c1 r<RT>, f<FS>"
3278*mipsI:
3279*mipsII:
3280*mipsIII:
3281{
ca971540 3282 check_fpu(SD_);
c906108c
SS		 3283 if (X)
3284 {
3285 if (FS == 0)
c0efbca4 3286 PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
c906108c 3287 else if (FS == 31)
c0efbca4 3288 PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
c906108c 3289 /* else NOP */
c0efbca4 3290 PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
c906108c
SS		 3291 }
3292 else
3293 { /* control from */
3294 if (FS == 0)
3295 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
3296 else if (FS == 31)
3297 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
3298 /* else NOP */
3299 }
3300}
eb5fcf93 3301010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32,f::CxC1
c906108c
SS		 3302"c%s<X>c1 r<RT>, f<FS>"
3303*mipsIV:
603a98e7 3304*mipsV:
c906108c
SS		 3305*vr4100:
3306*vr5000:
3307*r3900:
3308{
ca971540 3309 check_fpu(SD_);
c906108c
SS		 3310 if (X)
3311 {
3312 /* control to */
3313 TRACE_ALU_INPUT1 (GPR[RT]);
3314 if (FS == 0)
3315 {
3316 FCR0 = VL4_8(GPR[RT]);
3317 TRACE_ALU_RESULT (FCR0);
3318 }
3319 else if (FS == 31)
3320 {
3321 FCR31 = VL4_8(GPR[RT]);
3322 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3323 TRACE_ALU_RESULT (FCR31);
3324 }
3325 else
3326 {
3327 TRACE_ALU_RESULT0 ();
3328 }
3329 /* else NOP */
3330 }
3331 else
3332 { /* control from */
3333 if (FS == 0)
3334 {
3335 TRACE_ALU_INPUT1 (FCR0);
3336 GPR[RT] = SIGNEXTEND (FCR0, 32);
3337 }
3338 else if (FS == 31)
3339 {
3340 TRACE_ALU_INPUT1 (FCR31);
3341 GPR[RT] = SIGNEXTEND (FCR31, 32);
3342 }
3343 TRACE_ALU_RESULT (GPR[RT]);
3344 /* else NOP */
3345 }
3346}
3347
3348
3349//
3350// FIXME: Does not correctly differentiate between mips*
3351//
eb5fcf93 3352010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
c906108c 3353"cvt.d.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 3354*mipsI:
3355*mipsII:
3356*mipsIII:
3357*mipsIV:
603a98e7 3358*mipsV:
c906108c
SS		 3359*vr4100:
3360*vr5000:
3361*r3900:
3362{
3363 unsigned32 instruction = instruction_0;
3364 int destreg = ((instruction >> 6) & 0x0000001F);
3365 int fs = ((instruction >> 11) & 0x0000001F);
3366 int format = ((instruction >> 21) & 0x00000007);
ca971540 3367 check_fpu(SD_);
c906108c
SS		 3368 {
3369 if ((format == fmt_double) | 0)
3370 SignalException(ReservedInstruction,instruction);
3371 else
3372 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
3373 }
3374}
3375
3376
eb5fcf93 3377010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
c906108c
SS		 3378"cvt.l.%s<FMT> f<FD>, f<FS>"
3379*mipsIII:
3380*mipsIV:
603a98e7 3381*mipsV:
c906108c
SS		 3382*vr4100:
3383*vr5000:
3384*r3900:
3385{
3386 unsigned32 instruction = instruction_0;
3387 int destreg = ((instruction >> 6) & 0x0000001F);
3388 int fs = ((instruction >> 11) & 0x0000001F);
3389 int format = ((instruction >> 21) & 0x00000007);
ca971540 3390 check_fpu(SD_);
c906108c
SS		 3391 {
3392 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
3393 SignalException(ReservedInstruction,instruction);
3394 else
3395 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
3396 }
3397}
3398
3399
3400//
3401// FIXME: Does not correctly differentiate between mips*
3402//
eb5fcf93 3403010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
c906108c 3404"cvt.s.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 3405*mipsI:
3406*mipsII:
3407*mipsIII:
3408*mipsIV:
603a98e7 3409*mipsV:
c906108c
SS		 3410*vr4100:
3411*vr5000:
3412*r3900:
3413{
3414 unsigned32 instruction = instruction_0;
3415 int destreg = ((instruction >> 6) & 0x0000001F);
3416 int fs = ((instruction >> 11) & 0x0000001F);
3417 int format = ((instruction >> 21) & 0x00000007);
ca971540 3418 check_fpu(SD_);
c906108c
SS		 3419 {
3420 if ((format == fmt_single) | 0)
3421 SignalException(ReservedInstruction,instruction);
3422 else
3423 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
3424 }
3425}
3426
3427
eb5fcf93 3428010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
c906108c 3429"cvt.w.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 3430*mipsI:
3431*mipsII:
3432*mipsIII:
3433*mipsIV:
603a98e7 3434*mipsV:
c906108c
SS		 3435*vr4100:
3436*vr5000:
3437*r3900:
3438{
3439 unsigned32 instruction = instruction_0;
3440 int destreg = ((instruction >> 6) & 0x0000001F);
3441 int fs = ((instruction >> 11) & 0x0000001F);
3442 int format = ((instruction >> 21) & 0x00000007);
ca971540 3443 check_fpu(SD_);
c906108c
SS		 3444 {
3445 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
3446 SignalException(ReservedInstruction,instruction);
3447 else
3448 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
3449 }
3450}
3451
3452
eb5fcf93 3453010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
c906108c 3454"div.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 3455*mipsI:
3456*mipsII:
3457*mipsIII:
3458*mipsIV:
603a98e7 3459*mipsV:
c906108c
SS		 3460*vr4100:
3461*vr5000:
3462*r3900:
3463{
3464 unsigned32 instruction = instruction_0;
3465 int destreg = ((instruction >> 6) & 0x0000001F);
3466 int fs = ((instruction >> 11) & 0x0000001F);
3467 int ft = ((instruction >> 16) & 0x0000001F);
3468 int format = ((instruction >> 21) & 0x00000007);
ca971540 3469 check_fpu(SD_);
c906108c
SS		 3470 {
3471 if ((format != fmt_single) && (format != fmt_double))
3472 SignalException(ReservedInstruction,instruction);
3473 else
3474 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3475 }
3476}
3477
3478
3479// DMFC1
3480// DMTC1
eb5fcf93 3481010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64,f::DMxC1
c906108c
SS		 3482"dm%s<X>c1 r<RT>, f<FS>"
3483*mipsIII:
3484{
ca971540
CD		 3485 check_fpu(SD_);
3486 check_u64 (SD_, instruction_0);
c906108c
SS		 3487 if (X)
3488 {
3489 if (SizeFGR() == 64)
3490 PENDING_FILL((FS + FGRIDX),GPR[RT]);
3491 else if ((FS & 0x1) == 0)
3492 {
3493 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
3494 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
3495 }
3496 }
3497 else
3498 {
3499 if (SizeFGR() == 64)
3500 PENDING_FILL(RT,FGR[FS]);
3501 else if ((FS & 0x1) == 0)
3502 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
3503 else
a3027dd7
FCE		 3504 {
3505 if (STATE_VERBOSE_P(SD))
3506 sim_io_eprintf (SD,
673388c0
AC		 3507 "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
3508 (long) CIA);
a3027dd7
FCE		 3509 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3510 }
c906108c
SS		 3511 }
3512}
eb5fcf93 3513010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64,f::DMxC1
c906108c
SS		 3514"dm%s<X>c1 r<RT>, f<FS>"
3515*mipsIV:
603a98e7 3516*mipsV:
c906108c
SS		 3517*vr4100:
3518*vr5000:
3519*r3900:
3520{
ca971540
CD		 3521 check_fpu(SD_);
3522 check_u64 (SD_, instruction_0);
c906108c
SS		 3523 if (X)
3524 {
3525 if (SizeFGR() == 64)
3526 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
3527 else if ((FS & 0x1) == 0)
3528 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
3529 }
3530 else
3531 {
3532 if (SizeFGR() == 64)
3533 GPR[RT] = FGR[FS];
3534 else if ((FS & 0x1) == 0)
3535 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
3536 else
a3027dd7
FCE		 3537 {
3538 if (STATE_VERBOSE_P(SD))
3539 sim_io_eprintf (SD,
dd37a34b
AC		 3540 "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
3541 (long) CIA);
a3027dd7
FCE		 3542 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
3543 }
c906108c
SS		 3544 }
3545}
3546
3547
eb5fcf93 3548010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
c906108c
SS		 3549"floor.l.%s<FMT> f<FD>, f<FS>"
3550*mipsIII:
3551*mipsIV:
603a98e7 3552*mipsV:
c906108c
SS		 3553*vr4100:
3554*vr5000:
3555*r3900:
3556{
3557 unsigned32 instruction = instruction_0;
3558 int destreg = ((instruction >> 6) & 0x0000001F);
3559 int fs = ((instruction >> 11) & 0x0000001F);
3560 int format = ((instruction >> 21) & 0x00000007);
ca971540 3561 check_fpu(SD_);
c906108c
SS		 3562 {
3563 if ((format != fmt_single) && (format != fmt_double))
3564 SignalException(ReservedInstruction,instruction);
3565 else
3566 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
3567 }
3568}
3569
3570
eb5fcf93 3571010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
c906108c
SS		 3572"floor.w.%s<FMT> f<FD>, f<FS>"
3573*mipsII:
3574*mipsIII:
3575*mipsIV:
603a98e7 3576*mipsV:
c906108c
SS		 3577*vr4100:
3578*vr5000:
3579*r3900:
3580{
3581 unsigned32 instruction = instruction_0;
3582 int destreg = ((instruction >> 6) & 0x0000001F);
3583 int fs = ((instruction >> 11) & 0x0000001F);
3584 int format = ((instruction >> 21) & 0x00000007);
ca971540 3585 check_fpu(SD_);
c906108c
SS		 3586 {
3587 if ((format != fmt_single) && (format != fmt_double))
3588 SignalException(ReservedInstruction,instruction);
3589 else
3590 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
3591 }
3592}
3593
3594
387f484a 3595110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
c906108c
SS		 3596"ldc1 f<FT>, <OFFSET>(r<BASE>)"
3597*mipsII:
3598*mipsIII:
3599*mipsIV:
603a98e7 3600*mipsV:
c906108c
SS		 3601*vr4100:
3602*vr5000:
3603*r3900:
3604{
ca971540 3605 check_fpu(SD_);
c906108c
SS		 3606 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
3607}
3608
3609
eb5fcf93 3610010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
c906108c
SS		 3611"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3612*mipsIV:
603a98e7 3613*mipsV:
c906108c
SS		 3614*vr5000:
3615{
ca971540
CD		 3616 check_fpu(SD_);
3617 check_u64 (SD_, instruction_0);
c906108c
SS		 3618 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3619}
3620
3621
3622
eb5fcf93 3623110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
c906108c 3624"lwc1 f<FT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 3625*mipsI:
3626*mipsII:
3627*mipsIII:
3628*mipsIV:
603a98e7 3629*mipsV:
c906108c
SS		 3630*vr4100:
3631*vr5000:
3632*r3900:
3633{
ca971540 3634 check_fpu(SD_);
c906108c
SS		 3635 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
3636}
3637
3638
eb5fcf93 3639010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
c906108c
SS		 3640"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
3641*mipsIV:
603a98e7 3642*mipsV:
c906108c
SS		 3643*vr5000:
3644{
ca971540
CD		 3645 check_fpu(SD_);
3646 check_u64 (SD_, instruction_0);
c906108c
SS		 3647 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
3648}
3649
3650
3651
3652//
3653// FIXME: Not correct for mips*
3654//
3655010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
3656"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
3657*mipsIV:
603a98e7 3658*mipsV:
c906108c
SS		 3659*vr5000:
3660{
3661 unsigned32 instruction = instruction_0;
3662 int destreg = ((instruction >> 6) & 0x0000001F);
3663 int fs = ((instruction >> 11) & 0x0000001F);
3664 int ft = ((instruction >> 16) & 0x0000001F);
3665 int fr = ((instruction >> 21) & 0x0000001F);
ca971540 3666 check_fpu(SD_);
c906108c
SS		 3667 {
3668 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3669 }
3670}
3671
3672
3673010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
3674"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
3675*mipsIV:
603a98e7 3676*mipsV:
c906108c
SS		 3677*vr5000:
3678{
3679 unsigned32 instruction = instruction_0;
3680 int destreg = ((instruction >> 6) & 0x0000001F);
3681 int fs = ((instruction >> 11) & 0x0000001F);
3682 int ft = ((instruction >> 16) & 0x0000001F);
3683 int fr = ((instruction >> 21) & 0x0000001F);
ca971540 3684 check_fpu(SD_);
c906108c
SS		 3685 {
3686 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3687 }
3688}
3689
3690
3691// MFC1
3692// MTC1
eb5fcf93 3693010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32,f::MxC1
c906108c
SS		 3694"m%s<X>c1 r<RT>, f<FS>"
3695*mipsI:
3696*mipsII:
3697*mipsIII:
3698{
ca971540 3699 check_fpu(SD_);
c906108c
SS		 3700 if (X)
3701 { /*MTC1*/
3702 if (SizeFGR() == 64)
a3027dd7
FCE		 3703 {
3704 if (STATE_VERBOSE_P(SD))
3705 sim_io_eprintf (SD,
673388c0
AC		 3706 "Warning: PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
3707 (long) CIA);
a3027dd7
FCE		 3708 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
3709 }
c906108c
SS		 3710 else
3711 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
3712 }
3713 else /*MFC1*/
3714 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
3715}
eb5fcf93 3716010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1
c906108c
SS		 3717"m%s<X>c1 r<RT>, f<FS>"
3718*mipsIV:
603a98e7 3719*mipsV:
c906108c
SS		 3720*vr4100:
3721*vr5000:
3722*r3900:
3723{
3724 int fs = FS;
ca971540 3725 check_fpu(SD_);
c906108c
SS		 3726 if (X)
3727 /*MTC1*/
3728 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
3729 else /*MFC1*/
3730 GPR[RT] = SIGNEXTEND(FGR[FS],32);
3731}
3732
3733
eb5fcf93 3734010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
c906108c 3735"mov.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 3736*mipsI:
3737*mipsII:
3738*mipsIII:
3739*mipsIV:
603a98e7 3740*mipsV:
c906108c
SS		 3741*vr4100:
3742*vr5000:
3743*r3900:
3744{
3745 unsigned32 instruction = instruction_0;
3746 int destreg = ((instruction >> 6) & 0x0000001F);
3747 int fs = ((instruction >> 11) & 0x0000001F);
3748 int format = ((instruction >> 21) & 0x00000007);
ca971540 3749 check_fpu(SD_);
c906108c
SS		 3750 {
3751 StoreFPR(destreg,format,ValueFPR(fs,format));
3752 }
3753}
3754
3755
3756// MOVF
c2d11a7d 3757// MOVT
eb5fcf93 3758000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
c906108c
SS		 3759"mov%s<TF> r<RD>, r<RS>, <CC>"
3760*mipsIV:
603a98e7 3761*mipsV:
c906108c
SS		 3762*vr5000:
3763{
ca971540 3764 check_fpu(SD_);
c906108c
SS		 3765 if (GETFCC(CC) == TF)
3766 GPR[RD] = GPR[RS];
3767}
3768
3769
3770// MOVF.fmt
c2d11a7d 3771// MOVT.fmt
eb5fcf93 3772010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
c906108c
SS		 3773"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
3774*mipsIV:
603a98e7 3775*mipsV:
c906108c
SS		 3776*vr5000:
3777{
3778 unsigned32 instruction = instruction_0;
3779 int format = ((instruction >> 21) & 0x00000007);
ca971540 3780 check_fpu(SD_);
c906108c
SS		 3781 {
3782 if (GETFCC(CC) == TF)
3783 StoreFPR (FD, format, ValueFPR (FS, format));
3784 else
3785 StoreFPR (FD, format, ValueFPR (FD, format));
3786 }
3787}
3788
3789
eb5fcf93 3790010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
80ee11fa 3791"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
c906108c 3792*mipsIV:
603a98e7 3793*mipsV:
c906108c
SS		 3794*vr5000:
3795{
ca971540 3796 check_fpu(SD_);
80ee11fa
AC		 3797 if (GPR[RT] != 0)
3798 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3799 else
3800 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
c906108c
SS		 3801}
3802
3803
3804// MOVT see MOVtf
3805
3806
3807// MOVT.fmt see MOVtf.fmt
3808
3809
3810
eb5fcf93 3811010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
c906108c
SS		 3812"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
3813*mipsIV:
603a98e7 3814*mipsV:
c906108c
SS		 3815*vr5000:
3816{
ca971540 3817 check_fpu(SD_);
80ee11fa
AC		 3818 if (GPR[RT] == 0)
3819 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3820 else
3821 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
c906108c
SS		 3822}
3823
3824
3825// MSUB.fmt
eb5fcf93 3826010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32,f::MSUB.D
c906108c
SS		 3827"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
3828*mipsIV:
603a98e7 3829*mipsV:
c906108c
SS		 3830*vr5000:
3831{
3832 unsigned32 instruction = instruction_0;
3833 int destreg = ((instruction >> 6) & 0x0000001F);
3834 int fs = ((instruction >> 11) & 0x0000001F);
3835 int ft = ((instruction >> 16) & 0x0000001F);
3836 int fr = ((instruction >> 21) & 0x0000001F);
ca971540 3837 check_fpu(SD_);
c906108c
SS		 3838 {
3839 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3840 }
3841}
3842
3843
3844// MSUB.fmt
eb5fcf93 3845010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32,f::MSUB.S
c906108c
SS		 3846"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
3847*mipsIV:
603a98e7 3848*mipsV:
c906108c
SS		 3849*vr5000:
3850{
3851 unsigned32 instruction = instruction_0;
3852 int destreg = ((instruction >> 6) & 0x0000001F);
3853 int fs = ((instruction >> 11) & 0x0000001F);
3854 int ft = ((instruction >> 16) & 0x0000001F);
3855 int fr = ((instruction >> 21) & 0x0000001F);
ca971540 3856 check_fpu(SD_);
c906108c
SS		 3857 {
3858 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3859 }
3860}
3861
3862
3863// MTC1 see MxC1
3864
3865
eb5fcf93 3866010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
c906108c 3867"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 3868*mipsI:
3869*mipsII:
3870*mipsIII:
3871*mipsIV:
603a98e7 3872*mipsV:
c906108c
SS		 3873*vr4100:
3874*vr5000:
3875*r3900:
3876{
3877 unsigned32 instruction = instruction_0;
3878 int destreg = ((instruction >> 6) & 0x0000001F);
3879 int fs = ((instruction >> 11) & 0x0000001F);
3880 int ft = ((instruction >> 16) & 0x0000001F);
3881 int format = ((instruction >> 21) & 0x00000007);
ca971540 3882 check_fpu(SD_);
c906108c
SS		 3883 {
3884 if ((format != fmt_single) && (format != fmt_double))
3885 SignalException(ReservedInstruction,instruction);
3886 else
3887 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
3888 }
3889}
3890
3891
eb5fcf93 3892010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
c906108c 3893"neg.%s<FMT> f<FD>, f<FS>"
c5d00cc7
CD		 3894*mipsI:
3895*mipsII:
3896*mipsIII:
3897*mipsIV:
603a98e7 3898*mipsV:
c906108c
SS		 3899*vr4100:
3900*vr5000:
3901*r3900:
3902{
3903 unsigned32 instruction = instruction_0;
3904 int destreg = ((instruction >> 6) & 0x0000001F);
3905 int fs = ((instruction >> 11) & 0x0000001F);
3906 int format = ((instruction >> 21) & 0x00000007);
ca971540 3907 check_fpu(SD_);
c906108c
SS		 3908 {
3909 if ((format != fmt_single) && (format != fmt_double))
3910 SignalException(ReservedInstruction,instruction);
3911 else
3912 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
3913 }
3914}
3915
3916
3917// NMADD.fmt
eb5fcf93 3918010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32,f::NMADD.D
c906108c
SS		 3919"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
3920*mipsIV:
603a98e7 3921*mipsV:
c906108c
SS		 3922*vr5000:
3923{
3924 unsigned32 instruction = instruction_0;
3925 int destreg = ((instruction >> 6) & 0x0000001F);
3926 int fs = ((instruction >> 11) & 0x0000001F);
3927 int ft = ((instruction >> 16) & 0x0000001F);
3928 int fr = ((instruction >> 21) & 0x0000001F);
ca971540 3929 check_fpu(SD_);
c906108c
SS		 3930 {
3931 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3932 }
3933}
3934
3935
3936// NMADD.fmt
eb5fcf93 3937010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32,f::NMADD.S
c906108c
SS		 3938"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
3939*mipsIV:
603a98e7 3940*mipsV:
c906108c
SS		 3941*vr5000:
3942{
3943 unsigned32 instruction = instruction_0;
3944 int destreg = ((instruction >> 6) & 0x0000001F);
3945 int fs = ((instruction >> 11) & 0x0000001F);
3946 int ft = ((instruction >> 16) & 0x0000001F);
3947 int fr = ((instruction >> 21) & 0x0000001F);
ca971540 3948 check_fpu(SD_);
c906108c
SS		 3949 {
3950 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3951 }
3952}
3953
3954
3955// NMSUB.fmt
eb5fcf93 3956010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32,f::NMSUB.D
c906108c
SS		 3957"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
3958*mipsIV:
603a98e7 3959*mipsV:
c906108c
SS		 3960*vr5000:
3961{
3962 unsigned32 instruction = instruction_0;
3963 int destreg = ((instruction >> 6) & 0x0000001F);
3964 int fs = ((instruction >> 11) & 0x0000001F);
3965 int ft = ((instruction >> 16) & 0x0000001F);
3966 int fr = ((instruction >> 21) & 0x0000001F);
ca971540 3967 check_fpu(SD_);
c906108c
SS		 3968 {
3969 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3970 }
3971}
3972
3973
3974// NMSUB.fmt
eb5fcf93 3975010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32,f::NMSUB.S
c906108c
SS		 3976"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
3977*mipsIV:
603a98e7 3978*mipsV:
c906108c
SS		 3979*vr5000:
3980{
3981 unsigned32 instruction = instruction_0;
3982 int destreg = ((instruction >> 6) & 0x0000001F);
3983 int fs = ((instruction >> 11) & 0x0000001F);
3984 int ft = ((instruction >> 16) & 0x0000001F);
3985 int fr = ((instruction >> 21) & 0x0000001F);
ca971540 3986 check_fpu(SD_);
c906108c
SS		 3987 {
3988 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3989 }
3990}
3991
3992
3d81f391 3993010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
c906108c
SS		 3994"prefx <HINT>, r<INDEX>(r<BASE>)"
3995*mipsIV:
603a98e7 3996*mipsV:
c906108c
SS		 3997*vr5000:
3998{
3999 unsigned32 instruction = instruction_0;
4000 int fs = ((instruction >> 11) & 0x0000001F);
4001 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4002 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4003 {
4004 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4005 address_word paddr;
4006 int uncached;
4007 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4008 Prefetch(uncached,paddr,vaddr,isDATA,fs);
4009 }
4010}
4011
eb5fcf93 4012010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
c906108c 4013"recip.%s<FMT> f<FD>, f<FS>"
e514a9d6 4014*mipsIV:
603a98e7 4015*mipsV:
c906108c
SS		 4016*vr5000:
4017{
4018 unsigned32 instruction = instruction_0;
4019 int destreg = ((instruction >> 6) & 0x0000001F);
4020 int fs = ((instruction >> 11) & 0x0000001F);
4021 int format = ((instruction >> 21) & 0x00000007);
ca971540 4022 check_fpu(SD_);
c906108c
SS		 4023 {
4024 if ((format != fmt_single) && (format != fmt_double))
4025 SignalException(ReservedInstruction,instruction);
4026 else
4027 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4028 }
4029}
4030
4031
eb5fcf93 4032010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
c906108c
SS		 4033"round.l.%s<FMT> f<FD>, f<FS>"
4034*mipsIII:
4035*mipsIV:
603a98e7 4036*mipsV:
c906108c
SS		 4037*vr4100:
4038*vr5000:
4039*r3900:
4040{
4041 unsigned32 instruction = instruction_0;
4042 int destreg = ((instruction >> 6) & 0x0000001F);
4043 int fs = ((instruction >> 11) & 0x0000001F);
4044 int format = ((instruction >> 21) & 0x00000007);
ca971540 4045 check_fpu(SD_);
c906108c
SS		 4046 {
4047 if ((format != fmt_single) && (format != fmt_double))
4048 SignalException(ReservedInstruction,instruction);
4049 else
4050 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4051 }
4052}
4053
4054
eb5fcf93 4055010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
c906108c
SS		 4056"round.w.%s<FMT> f<FD>, f<FS>"
4057*mipsII:
4058*mipsIII:
4059*mipsIV:
603a98e7 4060*mipsV:
c906108c
SS		 4061*vr4100:
4062*vr5000:
4063*r3900:
4064{
4065 unsigned32 instruction = instruction_0;
4066 int destreg = ((instruction >> 6) & 0x0000001F);
4067 int fs = ((instruction >> 11) & 0x0000001F);
4068 int format = ((instruction >> 21) & 0x00000007);
ca971540 4069 check_fpu(SD_);
c906108c
SS		 4070 {
4071 if ((format != fmt_single) && (format != fmt_double))
4072 SignalException(ReservedInstruction,instruction);
4073 else
4074 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4075 }
4076}
4077
4078
eb5fcf93 4079010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
c906108c 4080*mipsIV:
603a98e7 4081*mipsV:
c906108c
SS		 4082"rsqrt.%s<FMT> f<FD>, f<FS>"
4083*vr5000:
4084{
4085 unsigned32 instruction = instruction_0;
4086 int destreg = ((instruction >> 6) & 0x0000001F);
4087 int fs = ((instruction >> 11) & 0x0000001F);
4088 int format = ((instruction >> 21) & 0x00000007);
ca971540 4089 check_fpu(SD_);
c906108c
SS		 4090 {
4091 if ((format != fmt_single) && (format != fmt_double))
4092 SignalException(ReservedInstruction,instruction);
4093 else
4094 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
4095 }
4096}
4097
4098
387f484a 4099111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
c906108c
SS		 4100"sdc1 f<FT>, <OFFSET>(r<BASE>)"
4101*mipsII:
4102*mipsIII:
4103*mipsIV:
603a98e7 4104*mipsV:
c906108c
SS		 4105*vr4100:
4106*vr5000:
4107*r3900:
4108{
ca971540 4109 check_fpu(SD_);
c906108c
SS		 4110 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4111}
4112
4113
eb5fcf93 4114010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
91a177cf 4115"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
c906108c 4116*mipsIV:
603a98e7 4117*mipsV:
c906108c
SS		 4118*vr5000:
4119{
ca971540
CD		 4120 check_fpu(SD_);
4121 check_u64 (SD_, instruction_0);
c906108c
SS		 4122 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4123}
4124
4125
eb5fcf93 4126010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
c906108c
SS		 4127"sqrt.%s<FMT> f<FD>, f<FS>"
4128*mipsII:
4129*mipsIII:
4130*mipsIV:
603a98e7 4131*mipsV:
c906108c
SS		 4132*vr4100:
4133*vr5000:
4134*r3900:
4135{
4136 unsigned32 instruction = instruction_0;
4137 int destreg = ((instruction >> 6) & 0x0000001F);
4138 int fs = ((instruction >> 11) & 0x0000001F);
4139 int format = ((instruction >> 21) & 0x00000007);
ca971540 4140 check_fpu(SD_);
c906108c
SS		 4141 {
4142 if ((format != fmt_single) && (format != fmt_double))
4143 SignalException(ReservedInstruction,instruction);
4144 else
4145 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4146 }
4147}
4148
4149
eb5fcf93 4150010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
c906108c 4151"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
c5d00cc7
CD		 4152*mipsI:
4153*mipsII:
4154*mipsIII:
4155*mipsIV:
603a98e7 4156*mipsV:
c906108c
SS		 4157*vr4100:
4158*vr5000:
4159*r3900:
4160{
4161 unsigned32 instruction = instruction_0;
4162 int destreg = ((instruction >> 6) & 0x0000001F);
4163 int fs = ((instruction >> 11) & 0x0000001F);
4164 int ft = ((instruction >> 16) & 0x0000001F);
4165 int format = ((instruction >> 21) & 0x00000007);
ca971540 4166 check_fpu(SD_);
c906108c
SS		 4167 {
4168 if ((format != fmt_single) && (format != fmt_double))
4169 SignalException(ReservedInstruction,instruction);
4170 else
4171 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4172 }
4173}
4174
4175
4176
eb5fcf93 4177111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
c906108c 4178"swc1 f<FT>, <OFFSET>(r<BASE>)"
c5d00cc7
CD		 4179*mipsI:
4180*mipsII:
4181*mipsIII:
4182*mipsIV:
603a98e7 4183*mipsV:
c906108c
SS		 4184*vr4100:
4185*vr5000:
4186*r3900:
4187{
4188 unsigned32 instruction = instruction_0;
4189 signed_word offset = EXTEND16 (OFFSET);
4190 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
4191 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
ca971540 4192 check_fpu(SD_);
c906108c
SS		 4193 {
4194 address_word vaddr = ((uword64)op1 + offset);
4195 address_word paddr;
4196 int uncached;
4197 if ((vaddr & 3) != 0)
4198 {
4199 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4200 }
4201 else
4202 {
4203 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4204 {
4205 uword64 memval = 0;
4206 uword64 memval1 = 0;
4207 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4208 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4209 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4210 unsigned int byte;
4211 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4212 byte = ((vaddr & mask) ^ bigendiancpu);
4213 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
4214 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4215 }
4216 }
4217 }
4218}
4219
4220
eb5fcf93 4221010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
c906108c
SS		 4222"swxc1 f<FS>, r<INDEX>(r<BASE>)"
4223*mipsIV:
603a98e7 4224*mipsV:
c906108c
SS		 4225*vr5000:
4226{
4227 unsigned32 instruction = instruction_0;
4228 int fs = ((instruction >> 11) & 0x0000001F);
4229 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4230 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
ca971540
CD		 4231 check_fpu(SD_);
4232 check_u64 (SD_, instruction_0);
c906108c
SS		 4233 {
4234 address_word vaddr = ((unsigned64)op1 + op2);
4235 address_word paddr;
4236 int uncached;
4237 if ((vaddr & 3) != 0)
4238 {
4239 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4240 }
4241 else
4242 {
4243 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4244 {
4245 unsigned64 memval = 0;
4246 unsigned64 memval1 = 0;
4247 unsigned64 mask = 0x7;
4248 unsigned int byte;
4249 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4250 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4251 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
4252 {
4253 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4254 }
4255 }
4256 }
4257 }
4258}
4259
4260
eb5fcf93 4261010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
c906108c
SS		 4262"trunc.l.%s<FMT> f<FD>, f<FS>"
4263*mipsIII:
4264*mipsIV:
603a98e7 4265*mipsV:
c906108c
SS		 4266*vr4100:
4267*vr5000:
4268*r3900:
4269{
4270 unsigned32 instruction = instruction_0;
4271 int destreg = ((instruction >> 6) & 0x0000001F);
4272 int fs = ((instruction >> 11) & 0x0000001F);
4273 int format = ((instruction >> 21) & 0x00000007);
ca971540 4274 check_fpu(SD_);
c906108c
SS		 4275 {
4276 if ((format != fmt_single) && (format != fmt_double))
4277 SignalException(ReservedInstruction,instruction);
4278 else
4279 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
4280 }
4281}
4282
4283
eb5fcf93 4284010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
c906108c
SS		 4285"trunc.w.%s<FMT> f<FD>, f<FS>"
4286*mipsII:
4287*mipsIII:
4288*mipsIV:
603a98e7 4289*mipsV:
c906108c
SS		 4290*vr4100:
4291*vr5000:
4292*r3900:
4293{
4294 unsigned32 instruction = instruction_0;
4295 int destreg = ((instruction >> 6) & 0x0000001F);
4296 int fs = ((instruction >> 11) & 0x0000001F);
4297 int format = ((instruction >> 21) & 0x00000007);
ca971540 4298 check_fpu(SD_);
c906108c
SS		 4299 {
4300 if ((format != fmt_single) && (format != fmt_double))
4301 SignalException(ReservedInstruction,instruction);
4302 else
4303 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
4304 }
4305}
4306
4307\f
4308//
4309// MIPS Architecture:
4310//
4311// System Control Instruction Set (COP0)
4312//
4313
4314
4315010000,01000,00000,16.OFFSET:COP0:32::BC0F
4316"bc0f <OFFSET>"
c5d00cc7
CD		 4317*mipsI:
4318*mipsII:
4319*mipsIII:
4320*mipsIV:
603a98e7 4321*mipsV:
c906108c
SS		 4322*vr4100:
4323*vr5000:
4324
7a292a7a
SS		 4325010000,01000,00000,16.OFFSET:COP0:32::BC0F
4326"bc0f <OFFSET>"
4327// stub needed for eCos as tx39 hardware bug workaround
4328*r3900:
4329{
4330 /* do nothing */
4331}
4332
c906108c
SS		 4333
4334010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4335"bc0fl <OFFSET>"
c5d00cc7
CD		 4336*mipsI:
4337*mipsII:
4338*mipsIII:
4339*mipsIV:
603a98e7 4340*mipsV:
c906108c
SS		 4341*vr4100:
4342*vr5000:
4343
4344
4345010000,01000,00001,16.OFFSET:COP0:32::BC0T
4346"bc0t <OFFSET>"
c5d00cc7
CD		 4347*mipsI:
4348*mipsII:
4349*mipsIII:
4350*mipsIV:
603a98e7 4351*mipsV:
c906108c
SS		 4352*vr4100:
4353
4354
4355010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4356"bc0tl <OFFSET>"
c5d00cc7
CD		 4357*mipsI:
4358*mipsII:
4359*mipsIII:
4360*mipsIV:
603a98e7 4361*mipsV:
c906108c
SS		 4362*vr4100:
4363*vr5000:
4364
4365
4366101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
0d3e762b 4367"cache <OP>, <OFFSET>(r<BASE>)"
c906108c
SS		 4368*mipsIII:
4369*mipsIV:
603a98e7 4370*mipsV:
c906108c
SS		 4371*vr4100:
4372*vr5000:
4373*r3900:
4374{
4375 unsigned32 instruction = instruction_0;
4376 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
4377 int hint = ((instruction >> 16) & 0x0000001F);
4378 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4379 {
4380 address_word vaddr = (op1 + offset);
4381 address_word paddr;
4382 int uncached;
4383 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4384 CacheOp(hint,vaddr,paddr,instruction);
4385 }
4386}
4387
4388
f701dad2 4389010000,1,0000000000000000000,111001:COP0:32::DI
c906108c 4390"di"
c5d00cc7
CD		 4391*mipsI:
4392*mipsII:
4393*mipsIII:
4394*mipsIV:
603a98e7 4395*mipsV:
c906108c
SS		 4396*vr4100:
4397*vr5000:
4398
4399
f701dad2 4400010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
9846de1b 4401"dmfc0 r<RT>, r<RD>"
c5d00cc7
CD		 4402*mipsIII:
4403*mipsIV:
603a98e7 4404*mipsV:
9846de1b 4405{
ca971540 4406 check_u64 (SD_, instruction_0);
9846de1b
JM		 4407 DecodeCoproc (instruction_0);
4408}
4409
4410
f701dad2 4411010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
9846de1b 4412"dmtc0 r<RT>, r<RD>"
c5d00cc7
CD		 4413*mipsIII:
4414*mipsIV:
603a98e7 4415*mipsV:
9846de1b 4416{
ca971540 4417 check_u64 (SD_, instruction_0);
9846de1b
JM		 4418 DecodeCoproc (instruction_0);
4419}
4420
4421
f701dad2 4422010000,1,0000000000000000000,111000:COP0:32::EI
c906108c 4423"ei"
c5d00cc7
CD		 4424*mipsI:
4425*mipsII:
4426*mipsIII:
4427*mipsIV:
603a98e7 4428*mipsV:
c906108c
SS		 4429*vr4100:
4430*vr5000:
4431
4432
f701dad2 4433010000,1,0000000000000000000,011000:COP0:32::ERET
c906108c
SS		 4434"eret"
4435*mipsIII:
4436*mipsIV:
603a98e7 4437*mipsV:
c906108c
SS		 4438*vr4100:
4439*vr5000:
4440{
4441 if (SR & status_ERL)
4442 {
4443 /* Oops, not yet available */
4444 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
4445 NIA = EPC;
4446 SR &= ~status_ERL;
4447 }
4448 else
4449 {
4450 NIA = EPC;
4451 SR &= ~status_EXL;
4452 }
4453}
4454
4455
4456010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4457"mfc0 r<RT>, r<RD> # <REGX>"
c5d00cc7
CD		 4458*mipsI:
4459*mipsII:
4460*mipsIII:
4461*mipsIV:
603a98e7 4462*mipsV:
c906108c
SS		 4463*vr4100:
4464*vr5000:
074e9cb8 4465*r3900:
c906108c
SS		 4466{
4467 TRACE_ALU_INPUT0 ();
4468 DecodeCoproc (instruction_0);
4469 TRACE_ALU_RESULT (GPR[RT]);
4470}
4471
4472010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4473"mtc0 r<RT>, r<RD> # <REGX>"
c5d00cc7
CD		 4474*mipsI:
4475*mipsII:
4476*mipsIII:
4477*mipsIV:
603a98e7 4478*mipsV:
c906108c
SS		 4479*vr4100:
4480*vr5000:
074e9cb8 4481*r3900:
c906108c
SS		 4482{
4483 DecodeCoproc (instruction_0);
4484}
4485
4486
f701dad2 4487010000,1,0000000000000000000,010000:COP0:32::RFE
c906108c 4488"rfe"
c5d00cc7
CD		 4489*mipsI:
4490*mipsII:
4491*mipsIII:
4492*mipsIV:
603a98e7 4493*mipsV:
c906108c
SS		 4494*vr4100:
4495*vr5000:
074e9cb8 4496*r3900:
c906108c
SS		 4497{
4498 DecodeCoproc (instruction_0);
4499}
4500
4501
45020100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
4503"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
c5d00cc7
CD		 4504*mipsI:
4505*mipsII:
4506*mipsIII:
4507*mipsIV:
603a98e7 4508*mipsV:
c906108c
SS		 4509*vr4100:
4510*r3900:
4511{
4512 DecodeCoproc (instruction_0);
4513}
4514
4515
4516
f701dad2 4517010000,1,0000000000000000000,001000:COP0:32::TLBP
c906108c 4518"tlbp"
c5d00cc7
CD		 4519*mipsI:
4520*mipsII:
4521*mipsIII:
4522*mipsIV:
603a98e7 4523*mipsV:
c906108c
SS		 4524*vr4100:
4525*vr5000:
4526
4527
f701dad2 4528010000,1,0000000000000000000,000001:COP0:32::TLBR
c906108c 4529"tlbr"
c5d00cc7
CD		 4530*mipsI:
4531*mipsII:
4532*mipsIII:
4533*mipsIV:
603a98e7 4534*mipsV:
c906108c
SS		 4535*vr4100:
4536*vr5000:
4537
4538
f701dad2 4539010000,1,0000000000000000000,000010:COP0:32::TLBWI
c906108c 4540"tlbwi"
c5d00cc7
CD		 4541*mipsI:
4542*mipsII:
4543*mipsIII:
4544*mipsIV:
603a98e7 4545*mipsV:
c906108c
SS		 4546*vr4100:
4547*vr5000:
4548
4549
f701dad2 4550010000,1,0000000000000000000,000110:COP0:32::TLBWR
c906108c 4551"tlbwr"
c5d00cc7
CD		 4552*mipsI:
4553*mipsII:
4554*mipsIII:
4555*mipsIV:
603a98e7 4556*mipsV:
c906108c
SS		 4557*vr4100:
4558*vr5000:
4559
4560\f
4561:include:::m16.igen
4562:include:::tx.igen
4563:include:::vr.igen
4564\f
GDB Binutils - Deliverables
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