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1 | // -*- C -*- |
2 | ||
3 | // Simulator definition for the MIPS 32/64 revision 2 instructions. | |
4 | // Copyright (C) 2004 Free Software Foundation, Inc. | |
5 | // Contributed by David Ung, of MIPS Technologies. | |
6 | // | |
7 | // This file is part of GDB, the GNU debugger. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; either version 2, or (at your option) | |
12 | // any later version. | |
13 | // | |
14 | // This program is distributed in the hope that it will be useful, | |
15 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | // GNU General Public License for more details. | |
18 | // | |
19 | // You should have received a copy of the GNU General Public License along | |
20 | // with this program; if not, write to the Free Software Foundation, Inc., | |
21 | // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | ||
24 | 011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT | |
25 | "dext r<RT>, r<RS>, <LSB>, <SIZE+1>" | |
26 | *mips64r2: | |
27 | { | |
28 | check_u64 (SD_, instruction_0); | |
29 | TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); | |
30 | GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE, LSB); | |
31 | TRACE_ALU_RESULT1 (GPR[RT]); | |
32 | } | |
33 | ||
34 | 011111,5.RS,5.RT,5.SIZE,5.LSB,000001::64::DEXTM | |
35 | "dextm r<RT>, r<RS>, <LSB>, <SIZE+33>" | |
36 | *mips64r2: | |
37 | { | |
38 | check_u64 (SD_, instruction_0); | |
39 | TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); | |
40 | GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE + 32, LSB); | |
41 | TRACE_ALU_RESULT1 (GPR[RT]); | |
42 | } | |
43 | ||
44 | 011111,5.RS,5.RT,5.SIZE,5.LSB,000010::64::DEXTU | |
45 | "dextu r<RT>, r<RS>, <LSB+32>, <SIZE+1>" | |
46 | *mips64r2: | |
47 | { | |
48 | check_u64 (SD_, instruction_0); | |
49 | TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); | |
50 | GPR[RT] = EXTRACTED64 (GPR[RS], LSB + 32 + SIZE, LSB + 32); | |
51 | TRACE_ALU_RESULT1 (GPR[RT]); | |
52 | } | |
53 | ||
54 | ||
55 | 010000,01011,5.RT,01100,00000,0,00,000::32::DI | |
56 | "di":RT == 0 | |
57 | "di r<RT>" | |
58 | *mips32r2: | |
59 | *mips64r2: | |
60 | { | |
61 | TRACE_ALU_INPUT0 (); | |
62 | GPR[RT] = EXTEND32 (SR); | |
63 | SR &= ~status_IE; | |
64 | TRACE_ALU_RESULT1 (GPR[RT]); | |
65 | } | |
66 | ||
67 | ||
68 | 011111,5.RS,5.RT,5.MSB,5.LSB,000111::64::DINS | |
69 | "dins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>" | |
70 | *mips64r2: | |
71 | { | |
72 | check_u64 (SD_, instruction_0); | |
73 | TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); | |
74 | if (LSB <= MSB) | |
75 | GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB, LSB); | |
76 | TRACE_ALU_RESULT1 (GPR[RT]); | |
77 | } | |
78 | ||
79 | 011111,5.RS,5.RT,5.MSB,5.LSB,000101::64::DINSM | |
80 | "dinsm r<RT>, r<RS>, <LSB>, <MSB+32-LSB+1>" | |
81 | *mips64r2: | |
82 | { | |
83 | check_u64 (SD_, instruction_0); | |
84 | TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); | |
85 | if (LSB <= MSB + 32) | |
86 | GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB + 32, LSB); | |
87 | TRACE_ALU_RESULT1 (GPR[RT]); | |
88 | } | |
89 | ||
90 | 011111,5.RS,5.RT,5.MSB,5.LSB,000110::64::DINSU | |
91 | "dinsu r<RT>, r<RS>, <LSB+32>, <MSB-LSB+1>" | |
92 | *mips64r2: | |
93 | { | |
94 | check_u64 (SD_, instruction_0); | |
95 | TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); | |
96 | if (LSB <= MSB) | |
97 | GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << (LSB + 32))) | |
98 | & MASK64 (MSB + 32, LSB + 32); | |
99 | TRACE_ALU_RESULT1 (GPR[RT]); | |
100 | } | |
101 | ||
102 | ||
103 | 011111,00000,5.RT,5.RD,00010,100100::64::DSBH | |
104 | "dsbh r<RD>, r<RT>" | |
105 | *mips64r2: | |
106 | { | |
107 | union { unsigned64 d; unsigned16 h[4]; } u; | |
108 | check_u64 (SD_, instruction_0); | |
109 | TRACE_ALU_INPUT1 (GPR[RT]); | |
110 | u.d = GPR[RT]; | |
111 | u.h[0] = SWAP_2 (u.h[0]); | |
112 | u.h[1] = SWAP_2 (u.h[1]); | |
113 | u.h[2] = SWAP_2 (u.h[2]); | |
114 | u.h[3] = SWAP_2 (u.h[3]); | |
115 | GPR[RD] = u.d; | |
116 | TRACE_ALU_RESULT1 (GPR[RD]); | |
117 | } | |
118 | ||
119 | 011111,00000,5.RT,5.RD,00101,100100::64::DSHD | |
120 | "dshd r<RD>, r<RT>" | |
121 | *mips64r2: | |
122 | { | |
123 | unsigned64 d; | |
124 | check_u64 (SD_, instruction_0); | |
125 | TRACE_ALU_INPUT1 (GPR[RT]); | |
126 | d = GPR[RT]; | |
127 | GPR[RD] = ((d >> 48) | |
128 | | (d << 48) | |
129 | | ((d & 0x0000ffff00000000) >> 16) | |
130 | | ((d & 0x00000000ffff0000) << 16)); | |
131 | TRACE_ALU_RESULT1 (GPR[RD]); | |
132 | } | |
133 | ||
134 | ||
135 | 010000,01011,5.RT,01100,00000,1,00,000::32::EI | |
136 | "ei":RT == 0 | |
137 | "ei r<RT>" | |
138 | *mips32r2: | |
139 | *mips64r2: | |
140 | { | |
141 | TRACE_ALU_INPUT0 (); | |
142 | GPR[RT] = EXTEND32 (SR); | |
143 | SR |= status_IE; | |
144 | TRACE_ALU_RESULT1 (GPR[RT]); | |
145 | } | |
146 | ||
147 | ||
148 | 011111,5.RS,5.RT,5.SIZE,5.LSB,000000::32::EXT | |
149 | "ext r<RT>, r<RS>, <LSB>, <SIZE+1>" | |
150 | *mips32r2: | |
151 | *mips64r2: | |
152 | { | |
153 | TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); | |
154 | GPR[RT] = EXTEND32 (EXTRACTED32 (GPR[RS], LSB + SIZE, LSB)); | |
155 | TRACE_ALU_RESULT1 (GPR[RT]); | |
156 | } | |
157 | ||
158 | ||
159 | 010001,00011,5.RT,5.FS,00000000000:COP1Sa:32,f::MFHC1 | |
160 | "mfhc1 r<RT>, f<FS>" | |
161 | *mips32r2: | |
162 | *mips64r2: | |
163 | { | |
164 | check_fpu (SD_); | |
165 | if (SizeFGR() == 64) | |
166 | GPR[RT] = EXTEND32 (WORD64HI (FGR[FS])); | |
167 | else if ((FS & 0x1) == 0) | |
168 | GPR[RT] = EXTEND32 (FGR[FS + 1]); | |
169 | else | |
170 | { | |
171 | if (STATE_VERBOSE_P(SD)) | |
172 | sim_io_eprintf (SD, | |
173 | "Warning: PC 0x%lx: MFHC1 32-bit use of odd FPR number\n", | |
174 | (long) CIA); | |
175 | GPR[RT] = EXTEND32 (0xBADF00D); | |
176 | } | |
177 | TRACE_ALU_RESULT (GPR[RT]); | |
178 | } | |
179 | ||
180 | 010001,00111,5.RT,5.FS,00000000000:COP1Sa:32,f::MTHC1 | |
181 | "mthc1 r<RT>, f<FS>" | |
182 | *mips32r2: | |
183 | *mips64r2: | |
184 | { | |
185 | check_fpu (SD_); | |
186 | if (SizeFGR() == 64) | |
187 | StoreFPR (FS, fmt_uninterpreted_64, SET64HI (GPR[RT]) | VL4_8 (FGR[FS])); | |
188 | else if ((FS & 0x1) == 0) | |
189 | StoreFPR (FS + 1, fmt_uninterpreted_32, VL4_8 (GPR[RT])); | |
190 | else | |
191 | { | |
192 | if (STATE_VERBOSE_P(SD)) | |
193 | sim_io_eprintf (SD, | |
194 | "Warning: PC 0x%lx: MTHC1 32-bit use of odd FPR number\n", | |
195 | (long) CIA); | |
196 | StoreFPR (FS, fmt_uninterpreted_32, 0xDEADC0DE); | |
197 | } | |
198 | TRACE_FP_RESULT (GPR[RT]); | |
199 | } | |
200 | ||
201 | ||
202 | 011111,5.RS,5.RT,5.MSB,5.LSB,000100::32::INS | |
203 | "ins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>" | |
204 | *mips32r2: | |
205 | *mips64r2: | |
206 | { | |
207 | TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); | |
208 | if (LSB <= MSB) | |
209 | GPR[RT] = EXTEND32 (GPR[RT] ^ | |
210 | ((GPR[RT] ^ (GPR[RS] << LSB)) & MASK32 (MSB, LSB))); | |
211 | TRACE_ALU_RESULT1 (GPR[RT]); | |
212 | } | |
213 | ||
214 | ||
215 | 011111,00000,5.RT,5.RD,10000,100000::32::SEB | |
216 | "seb r<RD>, r<RT>" | |
217 | *mips32r2: | |
218 | *mips64r2: | |
219 | { | |
220 | TRACE_ALU_INPUT1 (GPR[RT]); | |
221 | GPR[RD] = EXTEND8 (GPR[RT]); | |
222 | TRACE_ALU_RESULT1 (GPR[RD]); | |
223 | } | |
224 | ||
225 | 011111,00000,5.RT,5.RD,11000,100000::32::SEH | |
226 | "seh r<RD>, r<RT>" | |
227 | *mips32r2: | |
228 | *mips64r2: | |
229 | { | |
230 | TRACE_ALU_INPUT1 (GPR[RT]); | |
231 | GPR[RD] = EXTEND16 (GPR[RT]); | |
232 | TRACE_ALU_RESULT1 (GPR[RD]); | |
233 | } | |
234 | ||
235 | ||
236 | 000001,5.BASE,11111,16.OFFSET::32::SYNCI | |
237 | "synci <OFFSET>(r<BASE>)" | |
238 | *mips32r2: | |
239 | *mips64r2: | |
240 | { | |
241 | // sync i-cache - nothing to do currently | |
242 | } | |
243 | ||
244 | ||
245 | 011111,00000,5.RT,5.RD,00010,100000::32::WSBH | |
246 | "wsbh r<RD>, r<RT>" | |
247 | *mips32r2: | |
248 | *mips64r2: | |
249 | { | |
250 | union { unsigned32 w; unsigned16 h[2]; } u; | |
251 | TRACE_ALU_INPUT1 (GPR[RT]); | |
252 | u.w = GPR[RT]; | |
253 | u.h[0] = SWAP_2 (u.h[0]); | |
254 | u.h[1] = SWAP_2 (u.h[1]); | |
255 | GPR[RD] = EXTEND32 (u.w); | |
256 | TRACE_ALU_RESULT1 (GPR[RD]); | |
257 | } | |
258 | ||
259 | ||
260 |