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sim: make LMA loading the default for all targets
[deliverable/binutils-gdb.git] / sim / mips / sim-main.h
CommitLineData
c906108c 1/* MIPS Simulator definition.
32d0add0 2 Copyright (C) 1997-2015 Free Software Foundation, Inc.
c906108c
SS		 3 Contributed by Cygnus Support.
4
8e394ffc 5This file is part of the MIPS sim.
c906108c
SS		 6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
4744ac1b
JB		 9the Free Software Foundation; either version 3 of the License, or
10(at your option) any later version.
c906108c
SS		 11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
4744ac1b
JB		 17You should have received a copy of the GNU General Public License
18along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c
SS		 19
20#ifndef SIM_MAIN_H
21#define SIM_MAIN_H
22
c906108c
SS		 23#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
24mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
25
26#include "sim-basics.h"
c906108c 27#include "sim-base.h"
4c54fc26 28#include "bfd.h"
c906108c 29
5accf1ff 30/* Deprecated macros and types for manipulating 64bit values. Use
c906108c
SS		 31 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
32
33typedef signed64 word64;
34typedef unsigned64 uword64;
35
36#define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
37#define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
38#define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
39#define SET64HI(t) (((uword64)(t))<<32)
40#define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
41#define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
42
c906108c
SS		 43/* Check if a value will fit within a halfword: */
44#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
45
46
8e394ffc
AB		 47typedef enum {
48 cp0_dmfc0,
49 cp0_dmtc0,
50 cp0_mfc0,
51 cp0_mtc0,
52 cp0_tlbr,
53 cp0_tlbwi,
54 cp0_tlbwr,
55 cp0_tlbp,
56 cp0_cache,
57 cp0_eret,
58 cp0_deret,
59 cp0_rfe
60} CP0_operation;
c906108c
SS		 61
62/* Floating-point operations: */
63
64#include "sim-fpu.h"
cfe9ea23 65#include "cp1.h"
c906108c
SS		 66
67/* FPU registers must be one of the following types. All other values
68 are reserved (and undefined). */
69typedef enum {
70 fmt_single = 0,
71 fmt_double = 1,
72 fmt_word = 4,
73 fmt_long = 5,
3a2b820e 74 fmt_ps = 6,
c906108c
SS		 75 /* The following are well outside the normal acceptable format
76 range, and are used in the register status vector. */
77 fmt_unknown = 0x10000000,
78 fmt_uninterpreted = 0x20000000,
79 fmt_uninterpreted_32 = 0x40000000,
80 fmt_uninterpreted_64 = 0x80000000U,
81} FP_formats;
82
e7e81181
CD		 83/* For paired word (pw) operations, the opcode representation is fmt_word,
84 but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long. */
85#define fmt_pw fmt_long
86
c906108c
SS		 87/* This should be the COC1 value at the start of the preceding
88 instruction: */
89#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
90
91#ifdef TARGET_ENABLE_FR
92/* FIXME: this should be enabled for all targets, but needs testing first. */
93#define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
94 ? ((SR & status_FR) ? 64 : 32) \
95 : (WITH_TARGET_FLOATING_POINT_BITSIZE))
96#else
97#define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
98#endif
99
c906108c
SS		 100
101
102
103
104/* HI/LO register accesses */
105
106/* For some MIPS targets, the HI/LO registers have certain timing
107 restrictions in that, for instance, a read of a HI register must be
108 separated by at least three instructions from a preceeding read.
109
110 The struct below is used to record the last access by each of A MT,
111 MF or other OP instruction to a HI/LO register. See mips.igen for
112 more details. */
113
114typedef struct _hilo_access {
115 signed64 timestamp;
116 address_word cia;
117} hilo_access;
118
119typedef struct _hilo_history {
120 hilo_access mt;
121 hilo_access mf;
122 hilo_access op;
123} hilo_history;
124
125
126
127
128/* Integer ALU operations: */
129
130#include "sim-alu.h"
131
132#define ALU32_END(ANS) \
133 if (ALU32_HAD_OVERFLOW) \
134 SignalExceptionIntegerOverflow (); \
135 (ANS) = (signed32) ALU32_OVERFLOW_RESULT
136
137
138#define ALU64_END(ANS) \
139 if (ALU64_HAD_OVERFLOW) \
140 SignalExceptionIntegerOverflow (); \
141 (ANS) = ALU64_OVERFLOW_RESULT;
142
143
144
145
146
147/* The following is probably not used for MIPS IV onwards: */
148/* Slots for delayed register updates. For the moment we just have a
149 fixed number of slots (rather than a more generic, dynamic
150 system). This keeps the simulator fast. However, we only allow
151 for the register update to be delayed for a single instruction
152 cycle. */
153#define PSLOTS (8) /* Maximum number of instruction cycles */
154
155typedef struct _pending_write_queue {
156 int in;
157 int out;
158 int total;
159 int slot_delay[PSLOTS];
160 int slot_size[PSLOTS];
161 int slot_bit[PSLOTS];
162 void *slot_dest[PSLOTS];
163 unsigned64 slot_value[PSLOTS];
164} pending_write_queue;
165
166#ifndef PENDING_TRACE
167#define PENDING_TRACE 0
168#endif
169#define PENDING_IN ((CPU)->pending.in)
170#define PENDING_OUT ((CPU)->pending.out)
171#define PENDING_TOTAL ((CPU)->pending.total)
172#define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
173#define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
174#define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
175#define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
176#define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
177
178/* Invalidate the pending write queue, all pending writes are
179 discarded. */
180
181#define PENDING_INVALIDATE() \
182memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
183
184/* Schedule a write to DEST for N cycles time. For 64 bit
185 destinations, schedule two writes. For floating point registers,
186 the caller should schedule a write to both the dest register and
187 the FPR_STATE register. When BIT is non-negative, only BIT of DEST
188 is updated. */
189
190#define PENDING_SCHED(DEST,VAL,DELAY,BIT) \
191 do { \
192 if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \
193 sim_engine_abort (SD, CPU, cia, \
194 "PENDING_SCHED - buffer overflow\n"); \
195 if (PENDING_TRACE) \
196 sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \
197 (unsigned long) cia, (unsigned long) &(DEST), \
198 (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
199 PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
200 PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \
201 PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \
202 PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \
203 PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \
204 PENDING_SLOT_BIT[PENDING_IN] = (BIT); \
205 PENDING_IN = (PENDING_IN + 1) % PSLOTS; \
206 PENDING_TOTAL += 1; \
207 } while (0)
208
209#define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
210#define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
211
212#define PENDING_TICK() pending_tick (SD, CPU, cia)
213
214#define PENDING_FLUSH() abort () /* think about this one */
215#define PENDING_FP() abort () /* think about this one */
216
217/* For backward compatibility */
218#define PENDING_FILL(R,VAL) \
219do { \
ee7254b0 220 if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \
c906108c 221 { \
ee7254b0
CD		 222 PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \
223 PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
c906108c
SS		 224 } \
225 else \
226 PENDING_SCHED(GPR[(R)], VAL, 1, -1); \
227} while (0)
228
229
9e52972e
FF		 230enum float_operation
231 {
232 FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD,
233 FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS,
234 FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
235 };
236
c906108c 237
f4f1b9f1
CD		 238/* The internal representation of an MDMX accumulator.
239 Note that 24 and 48 bit accumulator elements are represented in
240 32 or 64 bits. Since the accumulators are 2's complement with
241 overflow suppressed, high-order bits can be ignored in most contexts. */
242
243typedef signed32 signed24;
244typedef signed64 signed48;
245
246typedef union {
247 signed24 ob[8];
248 signed48 qh[4];
249} MDMX_accumulator;
250
251
252/* Conventional system arguments. */
253#define SIM_STATE sim_cpu *cpu, address_word cia
254#define SIM_ARGS CPU, cia
255
c906108c
SS		 256struct _sim_cpu {
257
258
259 /* The following are internal simulator state variables: */
c906108c
SS		 260 address_word dspc; /* delay-slot PC */
261#define DSPC ((CPU)->dspc)
262
263#define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
264#define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
265
266
267 /* State of the simulator */
268 unsigned int state;
269 unsigned int dsstate;
270#define STATE ((CPU)->state)
271#define DSSTATE ((CPU)->dsstate)
272
273/* Flags in the "state" variable: */
274#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
275#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
276#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
277#define simPCOC0 (1 << 17) /* COC[1] from current */
278#define simPCOC1 (1 << 18) /* COC[1] from previous */
279#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
280#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
281#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
282#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
283
fb891446 284#ifndef ENGINE_ISSUE_PREFIX_HOOK
c906108c
SS		 285#define ENGINE_ISSUE_PREFIX_HOOK() \
286 { \
287 /* Perform any pending writes */ \
288 PENDING_TICK(); \
289 /* Set previous flag, depending on current: */ \
290 if (STATE & simPCOC0) \
291 STATE |= simPCOC1; \
292 else \
293 STATE &= ~simPCOC1; \
294 /* and update the current value: */ \
295 if (GETFCC(0)) \
296 STATE |= simPCOC0; \
297 else \
298 STATE &= ~simPCOC0; \
299 }
fb891446 300#endif /* ENGINE_ISSUE_PREFIX_HOOK */
c906108c
SS		 301
302
303/* This is nasty, since we have to rely on matching the register
304 numbers used by GDB. Unfortunately, depending on the MIPS target
305 GDB uses different register numbers. We cannot just include the
306 relevant "gdb/tm.h" link, since GDB may not be configured before
307 the sim world, and also the GDB header file requires too much other
308 state. */
309
310#ifndef TM_MIPS_H
40a5538e 311#define LAST_EMBED_REGNUM (96)
c906108c
SS		 312#define NUM_REGS (LAST_EMBED_REGNUM + 1)
313
ee7254b0
CD		 314#define FP0_REGNUM 38 /* Floating point register 0 (single float) */
315#define FCRCS_REGNUM 70 /* FP control/status */
316#define FCRIR_REGNUM 71 /* FP implementation/revision */
c906108c
SS		 317#endif
318
319
c906108c
SS		 320/* To keep this default simulator simple, and fast, we use a direct
321 vector of registers. The internal simulator engine then uses
322 manifests to access the correct slot. */
323
324 unsigned_word registers[LAST_EMBED_REGNUM + 1];
325
326 int register_widths[NUM_REGS];
327#define REGISTERS ((CPU)->registers)
328
329#define GPR (&REGISTERS[0])
330#define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
331
c906108c
SS		 332#define LO (REGISTERS[33])
333#define HI (REGISTERS[34])
334#define PCIDX 37
335#define PC (REGISTERS[PCIDX])
336#define CAUSE (REGISTERS[36])
337#define SRIDX (32)
338#define SR (REGISTERS[SRIDX]) /* CPU status register */
339#define FCR0IDX (71)
340#define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
341#define FCR31IDX (70)
342#define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
343#define FCSR (FCR31)
344#define Debug (REGISTERS[86])
345#define DEPC (REGISTERS[87])
346#define EPC (REGISTERS[88])
2d2733fc 347#define ACX (REGISTERS[89])
c906108c 348
40a5538e
CF		 349#define AC0LOIDX (33) /* Must be the same register as LO */
350#define AC0HIIDX (34) /* Must be the same register as HI */
351#define AC1LOIDX (90)
352#define AC1HIIDX (91)
353#define AC2LOIDX (92)
354#define AC2HIIDX (93)
355#define AC3LOIDX (94)
356#define AC3HIIDX (95)
357
358#define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]])
359#define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]])
360
361#define DSPCRIDX (96) /* DSP control register */
362#define DSPCR (REGISTERS[DSPCRIDX])
363
364#define DSPCR_POS_SHIFT (0)
365#define DSPCR_POS_MASK (0x3f)
366#define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT)
367
368#define DSPCR_SCOUNT_SHIFT (7)
369#define DSPCR_SCOUNT_MASK (0x3f)
370#define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
371
372#define DSPCR_CARRY_SHIFT (13)
373#define DSPCR_CARRY_MASK (1)
374#define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
375#define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT)
376
377#define DSPCR_EFI_SHIFT (14)
378#define DSPCR_EFI_MASK (1)
379#define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
380#define DSPCR_EFI (1 << DSPCR_EFI_MASK)
381
382#define DSPCR_OUFLAG_SHIFT (16)
383#define DSPCR_OUFLAG_MASK (0xff)
384#define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
385#define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4))
386#define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5))
387#define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6))
388#define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7))
389
390#define DSPCR_CCOND_SHIFT (24)
391#define DSPCR_CCOND_MASK (0xf)
392#define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
393
c906108c
SS		 394 /* All internal state modified by signal_exception() that may need to be
395 rolled back for passing moment-of-exception image back to gdb. */
396 unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
397 unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
398 int exc_suspended;
399
400#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
401#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
402#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
403
404 unsigned_word c0_config_reg;
405#define C0_CONFIG ((CPU)->c0_config_reg)
406
407/* The following are pseudonyms for standard registers */
408#define ZERO (REGISTERS[0])
409#define V0 (REGISTERS[2])
410#define A0 (REGISTERS[4])
411#define A1 (REGISTERS[5])
412#define A2 (REGISTERS[6])
413#define A3 (REGISTERS[7])
414#define T8IDX 24
415#define T8 (REGISTERS[T8IDX])
416#define SPIDX 29
417#define SP (REGISTERS[SPIDX])
418#define RAIDX 31
419#define RA (REGISTERS[RAIDX])
420
421 /* While space is allocated in the main registers arrray for some of
422 the COP0 registers, that space isn't sufficient. Unknown COP0
423 registers overflow into the array below */
424
425#define NR_COP0_GPR 32
426 unsigned_word cop0_gpr[NR_COP0_GPR];
427#define COP0_GPR ((CPU)->cop0_gpr)
1a27f959 428#define COP0_BADVADDR (COP0_GPR[8])
c906108c 429
ee7254b0
CD		 430 /* While space is allocated for the floating point registers in the
431 main registers array, they are stored separatly. This is because
432 their size may not necessarily match the size of either the
433 general-purpose or system specific registers. */
434#define NR_FGR (32)
435#define FGR_BASE FP0_REGNUM
436 fp_word fgr[NR_FGR];
437#define FGR ((CPU)->fgr)
438
c906108c
SS		 439 /* Keep the current format state for each register: */
440 FP_formats fpr_state[32];
441#define FPR_STATE ((CPU)->fpr_state)
442
443 pending_write_queue pending;
444
f4f1b9f1
CD		 445 /* The MDMX accumulator (used only for MDMX ASE). */
446 MDMX_accumulator acc;
447#define ACC ((CPU)->acc)
448
c906108c
SS		 449 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
450 read-write instructions. It is set when a linked load occurs. It
451 is tested and cleared by the conditional store. It is cleared
452 (during other CPU operations) when a store to the location would
453 no longer be atomic. In particular, it is cleared by exception
454 return instructions. */
455 int llbit;
456#define LLBIT ((CPU)->llbit)
457
458
459/* The HIHISTORY and LOHISTORY timestamps are used to ensure that
460 corruptions caused by using the HI or LO register too close to a
461 following operation is spotted. See mips.igen for more details. */
462
463 hilo_history hi_history;
464#define HIHISTORY (&(CPU)->hi_history)
465 hilo_history lo_history;
466#define LOHISTORY (&(CPU)->lo_history)
467
c906108c
SS		 468
469 sim_cpu_base base;
470};
471
6e4f085c
MF		 472extern void mips_sim_close (SIM_DESC sd, int quitting);
473#define SIM_CLOSE_HOOK(...) mips_sim_close (__VA_ARGS__)
c906108c
SS		 474
475/* MIPS specific simulator watch config */
476
bdca5ee4 477void watch_options_install (SIM_DESC sd);
c906108c
SS		 478
479struct swatch {
480 sim_event *pc;
481 sim_event *clock;
482 sim_event *cycles;
483};
484
485
486/* FIXME: At present much of the simulator is still static */
487struct sim_state {
488
489 struct swatch watch;
490
7bebb329 491 sim_cpu *cpu[MAX_NR_PROCESSORS];
c906108c 492
8e394ffc
AB		 493 /* microMIPS ISA mode. */
494 int isa_mode;
495
c906108c
SS		 496 sim_state_base base;
497};
498
499
500
501/* Status information: */
502
503/* TODO : these should be the bitmasks for these bits within the
504 status register. At the moment the following are VR4300
505 bit-positions: */
506#define status_KSU_mask (0x18) /* mask for KSU bits */
507#define status_KSU_shift (3) /* shift for field */
508#define ksu_kernel (0x0)
509#define ksu_supervisor (0x1)
510#define ksu_user (0x2)
511#define ksu_unknown (0x3)
512
513#define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift)
514
515#define status_IE (1 << 0) /* Interrupt enable */
516#define status_EIE (1 << 16) /* Enable Interrupt Enable */
517#define status_EXL (1 << 1) /* Exception level */
518#define status_RE (1 << 25) /* Reverse Endian in user mode */
519#define status_FR (1 << 26) /* enables MIPS III additional FP registers */
520#define status_SR (1 << 20) /* soft reset or NMI */
521#define status_BEV (1 << 22) /* Location of general exception vectors */
522#define status_TS (1 << 21) /* TLB shutdown has occurred */
523#define status_ERL (1 << 2) /* Error level */
524#define status_IM7 (1 << 15) /* Timer Interrupt Mask */
525#define status_RP (1 << 27) /* Reduced Power mode */
526
527/* Specializations for TX39 family */
528#define status_IEc (1 << 0) /* Interrupt enable (current) */
529#define status_KUc (1 << 1) /* Kernel/User mode */
530#define status_IEp (1 << 2) /* Interrupt enable (previous) */
531#define status_KUp (1 << 3) /* Kernel/User mode */
532#define status_IEo (1 << 4) /* Interrupt enable (old) */
533#define status_KUo (1 << 5) /* Kernel/User mode */
534#define status_IM_mask (0xff) /* Interrupt mask */
535#define status_IM_shift (8)
536#define status_NMI (1 << 20) /* NMI */
537#define status_NMI (1 << 20) /* NMI */
538
d35d4f70
CD		 539/* Status bits used by MIPS32/MIPS64. */
540#define status_UX (1 << 5) /* 64-bit user addrs */
541#define status_SX (1 << 6) /* 64-bit supervisor addrs */
542#define status_KX (1 << 7) /* 64-bit kernel addrs */
543#define status_TS (1 << 21) /* TLB shutdown has occurred */
544#define status_PX (1 << 23) /* Enable 64 bit operations */
545#define status_MX (1 << 24) /* Enable MDMX resources */
546#define status_CU0 (1 << 28) /* Coprocessor 0 usable */
547#define status_CU1 (1 << 29) /* Coprocessor 1 usable */
548#define status_CU2 (1 << 30) /* Coprocessor 2 usable */
549#define status_CU3 (1 << 31) /* Coprocessor 3 usable */
7cbea089
CD		 550/* Bits reserved for implementations: */
551#define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */
d35d4f70 552
c906108c
SS		 553#define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */
554#define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */
555#define cause_CE_mask 0x30000000 /* Coprocessor exception */
556#define cause_CE_shift 28
557#define cause_EXC2_mask 0x00070000
558#define cause_EXC2_shift 16
559#define cause_IP7 (1 << 15) /* Interrupt pending */
560#define cause_SIOP (1 << 12) /* SIO pending */
561#define cause_IP3 (1 << 11) /* Int 0 pending */
562#define cause_IP2 (1 << 10) /* Int 1 pending */
563
564#define cause_EXC_mask (0x1c) /* Exception code */
565#define cause_EXC_shift (2)
566
567#define cause_SW0 (1 << 8) /* Software interrupt 0 */
568#define cause_SW1 (1 << 9) /* Software interrupt 1 */
569#define cause_IP_mask (0x3f) /* Interrupt pending field */
570#define cause_IP_shift (10)
571
572#define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask)
573#define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
574
575
576/* NOTE: We keep the following status flags as bit values (1 for true,
577 0 for false). This allows them to be used in binary boolean
578 operations without worrying about what exactly the non-zero true
579 value is. */
580
581/* UserMode */
582#ifdef SUBTARGET_R3900
583#define UserMode ((SR & status_KUc) ? 1 : 0)
584#else
585#define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
586#endif /* SUBTARGET_R3900 */
587
588/* BigEndianMem */
589/* Hardware configuration. Affects endianness of LoadMemory and
590 StoreMemory and the endianness of Kernel and Supervisor mode
591 execution. The value is 0 for little-endian; 1 for big-endian. */
592#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
593/*(state & simBE) ? 1 : 0)*/
594
595/* ReverseEndian */
596/* This mode is selected if in User mode with the RE bit being set in
597 SR (Status Register). It reverses the endianness of load and store
598 instructions. */
599#define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
600
601/* BigEndianCPU */
602/* The endianness for load and store instructions (0=little;1=big). In
603 User mode this endianness may be switched by setting the state_RE
604 bit in the SR register. Thus, BigEndianCPU may be computed as
605 (BigEndianMem EOR ReverseEndian). */
606#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
607
608
609
610/* Exceptions: */
611
612/* NOTE: These numbers depend on the processor architecture being
613 simulated: */
614enum ExceptionCause {
615 Interrupt = 0,
616 TLBModification = 1,
617 TLBLoad = 2,
618 TLBStore = 3,
619 AddressLoad = 4,
620 AddressStore = 5,
621 InstructionFetch = 6,
622 DataReference = 7,
623 SystemCall = 8,
624 BreakPoint = 9,
625 ReservedInstruction = 10,
626 CoProcessorUnusable = 11,
627 IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */
628 Trap = 13,
629 FPE = 15,
d35d4f70
CD		 630 DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */
631 MDMX = 22,
c906108c 632 Watch = 23,
d35d4f70
CD		 633 MCheck = 24,
634 CacheErr = 30,
635 NMIReset = 31, /* Reserved in MIPS32/MIPS64. */
c906108c
SS		 636
637
638/* The following exception code is actually private to the simulator
639 world. It is *NOT* a processor feature, and is used to signal
640 run-time errors in the simulator. */
641 SimulatorFault = 0xFFFFFFFF
642};
643
644#define TLB_REFILL (0)
645#define TLB_INVALID (1)
646
647
648/* The following break instructions are reserved for use by the
649 simulator. The first is used to halt the simulation. The second
650 is used by gdb for break-points. NOTE: Care must be taken, since
651 this value may be used in later revisions of the MIPS ISA. */
652#define HALT_INSTRUCTION_MASK (0x03FFFFC0)
653
654#define HALT_INSTRUCTION (0x03ff000d)
655#define HALT_INSTRUCTION2 (0x0000ffcd)
656
657
658#define BREAKPOINT_INSTRUCTION (0x0005000d)
659#define BREAKPOINT_INSTRUCTION2 (0x0000014d)
660
661
662
663void interrupt_event (SIM_DESC sd, void *data);
664
665void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
666#define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction))
667#define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level)
668#define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
669#define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
670#define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
671#define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference)
672#define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
673#define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
674#define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
3ad6f714 675#define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
c906108c
SS		 676#define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset)
677#define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
678#define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
679#define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
680#define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
681#define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification)
d35d4f70
CD		 682#define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX)
683#define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch)
684#define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck)
685#define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr)
c906108c
SS		 686
687/* Co-processor accesses */
688
3ad6f714
CD		 689/* XXX FIXME: For now, assume that FPU (cp1) is always usable. */
690#define COP_Usable(coproc_num) (coproc_num == 1)
691
bdca5ee4
TT		 692void cop_lw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword);
693void cop_ld (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword);
694unsigned int cop_sw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
695uword64 cop_sd (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
c906108c
SS		 696
697#define COP_LW(coproc_num,coproc_reg,memword) \
698cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
699#define COP_LD(coproc_num,coproc_reg,memword) \
700cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
701#define COP_SW(coproc_num,coproc_reg) \
702cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
703#define COP_SD(coproc_num,coproc_reg) \
704cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
705
706
8e394ffc
AB		 707void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia,
708 unsigned int instruction, int coprocnum, CP0_operation op,
709 int rt, int rd, int sel);
710#define DecodeCoproc(instruction,coprocnum,op,rt,rd,sel) \
711 decode_coproc (SD, CPU, cia, (instruction), (coprocnum), (op), \
712 (rt), (rd), (sel))
c906108c 713
8030f857 714int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
c906108c
SS		 715
716
18d8a52d
CD		 717/* FPR access. */
718unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
719#define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
720void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
721#define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
3a2b820e
CD		 722unsigned64 ps_lower (SIM_STATE, unsigned64 op);
723#define PSLower(op) ps_lower (SIM_ARGS, op)
724unsigned64 ps_upper (SIM_STATE, unsigned64 op);
725#define PSUpper(op) ps_upper (SIM_ARGS, op)
726unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
727#define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
18d8a52d
CD		 728
729
cfe9ea23
CD		 730/* FCR access. */
731unsigned_word value_fcr (SIM_STATE, int fcr);
732#define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
733void store_fcr (SIM_STATE, int fcr, unsigned_word value);
734#define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
735void test_fcsr (SIM_STATE);
736#define TestFCSR() test_fcsr (SIM_ARGS)
737
738
18d8a52d 739/* FPU operations. */
cfe9ea23
CD		 740void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
741#define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
ba46ddd0
CD		 742unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
743#define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
744unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
745#define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
746unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
747#define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
748unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
749#define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
750unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
751#define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
752unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
753#define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
754unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
755#define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
756unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
757#define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
f3c08b7e
CD		 758unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
759#define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
760unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
761 unsigned64 op3, FP_formats fmt);
762#define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
763unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
764 unsigned64 op3, FP_formats fmt);
765#define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
766unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
767 unsigned64 op3, FP_formats fmt);
768#define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
769unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
770 unsigned64 op3, FP_formats fmt);
771#define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
18d8a52d
CD		 772unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
773#define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
3a2b820e
CD		 774unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
775 FP_formats to);
776#define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
18d8a52d
CD		 777
778
e7e81181
CD		 779/* MIPS-3D ASE operations. */
780#define CompareAbs(op1,op2,fmt,cond,cc) \
781fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
782unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
783#define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
784unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
785#define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
786unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt);
787#define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
788unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
789#define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
790unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt);
791#define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
792unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
793#define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)
794
795
f4f1b9f1
CD		 796/* MDMX access. */
797
798typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */
799#define ob_fmtsel(sel) (((sel)<<1)|0x0)
800#define qh_fmtsel(sel) (((sel)<<2)|0x1)
801
802#define fmt_mdmx fmt_uninterpreted
803
804#define MX_VECT_AND (0)
805#define MX_VECT_NOR (1)
806#define MX_VECT_OR (2)
807#define MX_VECT_XOR (3)
808#define MX_VECT_SLL (4)
809#define MX_VECT_SRL (5)
f4f1b9f1
CD		 810#define MX_VECT_ADD (6)
811#define MX_VECT_SUB (7)
812#define MX_VECT_MIN (8)
813#define MX_VECT_MAX (9)
814#define MX_VECT_MUL (10)
815#define MX_VECT_MSGN (11)
816#define MX_VECT_SRA (12)
7cbea089
CD		 817#define MX_VECT_ABSD (13) /* SB-1 only. */
818#define MX_VECT_AVG (14) /* SB-1 only. */
f4f1b9f1
CD		 819
820unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
821#define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
822#define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
823#define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
824#define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
825#define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
826#define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
827#define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
828#define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel)
829#define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
830#define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
831#define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
832#define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
833#define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
7cbea089
CD		 834#define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
835#define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
f4f1b9f1
CD		 836
837#define MX_C_EQ 0x1
838#define MX_C_LT 0x4
839
840void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
841#define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
842
843unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
844#define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
845
846#define MX_VECT_ADDA (0)
847#define MX_VECT_ADDL (1)
848#define MX_VECT_MULA (2)
849#define MX_VECT_MULL (3)
850#define MX_VECT_MULS (4)
851#define MX_VECT_MULSL (5)
852#define MX_VECT_SUBA (6)
853#define MX_VECT_SUBL (7)
7cbea089 854#define MX_VECT_ABSDA (8) /* SB-1 only. */
f4f1b9f1
CD		 855
856void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
857#define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
858#define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
859#define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
860#define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
861#define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
862#define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
863#define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
864#define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
7cbea089 865#define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
f4f1b9f1
CD		 866
867#define MX_FMT_OB (0)
868#define MX_FMT_QH (1)
869
870/* The following codes chosen to indicate the units of shift. */
871#define MX_RAC_L (0)
872#define MX_RAC_M (1)
873#define MX_RAC_H (2)
874
875unsigned64 mdmx_rac_op (SIM_STATE, int, int);
876#define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
877
878void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
879#define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
880void mdmx_wach (SIM_STATE, int, unsigned64);
881#define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
882
883#define MX_RND_AS (0)
884#define MX_RND_AU (1)
885#define MX_RND_ES (2)
886#define MX_RND_EU (3)
887#define MX_RND_ZS (4)
888#define MX_RND_ZU (5)
889
890unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
891#define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
892#define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
893#define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
894#define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
895#define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
896#define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
897
898unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
899#define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
900
901
c906108c
SS		 902
903/* Memory accesses */
904
905/* The following are generic to all versions of the MIPS architecture
906 to date: */
907
908/* Memory Access Types (for CCA): */
909#define Uncached (0)
910#define CachedNoncoherent (1)
911#define CachedCoherent (2)
912#define Cached (3)
913
914#define isINSTRUCTION (1 == 0) /* FALSE */
915#define isDATA (1 == 1) /* TRUE */
916#define isLOAD (1 == 0) /* FALSE */
917#define isSTORE (1 == 1) /* TRUE */
918#define isREAL (1 == 0) /* FALSE */
919#define isRAW (1 == 1) /* TRUE */
920/* The parameter HOST (isTARGET / isHOST) is ignored */
921#define isTARGET (1 == 0) /* FALSE */
922/* #define isHOST (1 == 1) TRUE */
923
924/* The "AccessLength" specifications for Loads and Stores. NOTE: This
925 is the number of bytes minus 1. */
926#define AccessLength_BYTE (0)
927#define AccessLength_HALFWORD (1)
928#define AccessLength_TRIPLEBYTE (2)
929#define AccessLength_WORD (3)
930#define AccessLength_QUINTIBYTE (4)
931#define AccessLength_SEXTIBYTE (5)
932#define AccessLength_SEPTIBYTE (6)
933#define AccessLength_DOUBLEWORD (7)
934#define AccessLength_QUADWORD (15)
935
936#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
937 ? AccessLength_DOUBLEWORD /*7*/ \
938 : AccessLength_WORD /*3*/)
939#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
940
941
bdca5ee4 942INLINE_SIM_MAIN (int) address_translation (SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw);
c906108c
SS		 943#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
944address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
945
bdca5ee4 946INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD);
c906108c
SS		 947#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
948load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
949
bdca5ee4 950INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr);
c906108c
SS		 951#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
952store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
953
bdca5ee4 954INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction);
c906108c
SS		 955#define CacheOp(op,pAddr,vAddr,instruction) \
956cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
957
bdca5ee4 958INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype);
c906108c
SS		 959#define SyncOperation(stype) \
960sync_operation (SD, CPU, cia, (stype))
961
bdca5ee4 962INLINE_SIM_MAIN (void) prefetch (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint);
c906108c
SS		 963#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
964prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
965
402586aa
CD		 966void unpredictable_action (sim_cpu *cpu, address_word cia);
967#define NotWordValue(val) not_word_value (SD_, (val))
968#define Unpredictable() unpredictable (SD_)
f4f1b9f1 969#define UnpredictableResult() /* For now, do nothing. */
b96e7ef1 970
bdca5ee4 971INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
c906108c 972#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
bdca5ee4 973INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
c906108c
SS		 974#define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
975#define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
8e394ffc
AB		 976#define IMEM32_MICROMIPS(CIA) \
977 (ifetch16 (SD, CPU, (CIA), (CIA)) << 16 | ifetch16 (SD, CPU, (CIA + 2), \
978 (CIA + 2)))
979#define IMEM16_MICROMIPS(CIA) ifetch16 (SD, CPU, (CIA), ((CIA)))
980
981#define MICROMIPS_MINOR_OPCODE(INSN) ((INSN & 0x1C00) >> 10)
982
983#define MICROMIPS_DELAYSLOT_SIZE_ANY 0
984#define MICROMIPS_DELAYSLOT_SIZE_16 2
985#define MICROMIPS_DELAYSLOT_SIZE_32 4
986
987extern int isa_mode;
988
989#define ISA_MODE_MIPS32 0
990#define ISA_MODE_MICROMIPS 1
991
992address_word micromips_instruction_decode (SIM_DESC sd, sim_cpu * cpu,
993 address_word cia,
994 int instruction_size);
c906108c 995
29bc024d 996#if WITH_TRACE_ANY_P
bdca5ee4 997void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...);
c906108c 998extern FILE *tracefh;
29bc024d
MF		 999#else
1000#define dotrace(sd, cpu, tracefh, type, address, width, comment, ...)
1001#endif
c906108c 1002
40a5538e
CF		 1003extern int DSPLO_REGNUM[4];
1004extern int DSPHI_REGNUM[4];
1005
bdca5ee4 1006INLINE_SIM_MAIN (void) pending_tick (SIM_DESC sd, sim_cpu *cpu, address_word cia);
c906108c
SS		 1007extern SIM_CORE_SIGNAL_FN mips_core_signal;
1008
bdca5ee4
TT		 1009char* pr_addr (SIM_ADDR addr);
1010char* pr_uword64 (uword64 addr);
c906108c
SS		 1011
1012
4c0deff4 1013#define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
4c0deff4 1014
c906108c
SS		 1015void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
1016void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
1017void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
1018
4c54fc26
CD		 1019#ifdef MIPS_MACH_MULTI
1020extern int mips_mach_multi(SIM_DESC sd);
1021#define MIPS_MACH(SD) mips_mach_multi(SD)
1022#else
1023#define MIPS_MACH(SD) MIPS_MACH_DEFAULT
1024#endif
c906108c 1025
0e1b7197
RS		 1026/* Macros for determining whether a MIPS IV or MIPS V part is subject
1027 to the hi/lo restrictions described in mips.igen. */
1028
1029#define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \
1030 (MIPS_MACH (SD) != bfd_mach_mips5500)
1031
1032#define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \
1033 (MIPS_MACH (SD) != bfd_mach_mips5500)
1034
1035#define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \
1036 (MIPS_MACH (SD) != bfd_mach_mips5500)
1037
c906108c
SS		 1038#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
1039#include "sim-main.c"
1040#endif
1041
1042#endif
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