[deliverable/binutils-gdb.git] / sim / mips / sky-pke.h

/* Copyright (C) 1998, Cygnus Solutions */

#ifndef H_PKE_H
#define H_PKE_H

#include "sim-main.h"
#include "sky-device.h"


/* External functions */

void pke0_attach(SIM_DESC sd);
void pke0_issue(SIM_DESC sd);
void pke1_attach(SIM_DESC sd);
void pke1_issue(SIM_DESC sd);


/* Quadword data type */

typedef unsigned_4 quadword[4];

/* truncate address to quadword */
#define ADDR_TRUNC_QW(addr) ((addr) & ~0x0f)
/* extract offset in quadword */
#define ADDR_OFFSET_QW(addr) ((addr) & 0x0f)


/* SCEI memory mapping information */

#define PKE0_REGISTER_WINDOW_START 0x10003800
#define PKE1_REGISTER_WINDOW_START 0x10003C00
#define PKE0_FIFO_ADDR             0x10004000
#define PKE1_FIFO_ADDR             0x10005000


/* and now a few definitions that rightfully belong elsewhere */ 
#ifdef PKE_DEBUG


/* VU source-addr tracking tables */ /* changed from 1998-01-22 e-mail plans */
#define VU0_MEM0_SRCADDR_START 0x21000000
#define VU0_MEM1_SRCADDR_START 0x21004000
#define VU1_MEM0_SRCADDR_START 0x21008000
#define VU1_MEM1_SRCADDR_START 0x2100C000

/* GPUIF STAT register */
#define GPUIF_REG_STAT_APATH_E 11
#define GPUIF_REG_STAT_APATH_B 10

/* COP2 STAT register */
#define COP2_REG_STAT_ADDR VPU_STAT
#define COP2_REG_STAT_VBS1_E 8
#define COP2_REG_STAT_VBS1_B 8
#define COP2_REG_STAT_VBS0_E 0
#define COP2_REG_STAT_VBS0_B 0

#endif /* PKE_DEBUG */


/* Quadword indices of PKE registers.  Actual registers sit at bottom
   32 bits of each quadword. */
#define PKE_REG_STAT    0x00
#define PKE_REG_FBRST   0x01
#define PKE_REG_ERR     0x02
#define PKE_REG_MARK    0x03
#define PKE_REG_CYCLE   0x04
#define PKE_REG_MODE    0x05
#define PKE_REG_NUM     0x06
#define PKE_REG_MASK    0x07
#define PKE_REG_CODE    0x08
#define PKE_REG_ITOPS   0x09
#define PKE_REG_BASE    0x0a /* pke1 only */
#define PKE_REG_OFST    0x0b /* pke1 only */
#define PKE_REG_TOPS    0x0c /* pke1 only */
#define PKE_REG_ITOP    0x0d
#define PKE_REG_TOP     0x0e /* pke1 only */
#define PKE_REG_DBF     0x0f /* pke1 only */
#define PKE_REG_R0      0x10 /* R0 .. R3 must be contiguous */
#define PKE_REG_R1      0x11
#define PKE_REG_R2      0x12
#define PKE_REG_R3      0x13
#define PKE_REG_C0      0x14 /* C0 .. C3 must be contiguous */
#define PKE_REG_C1      0x15
#define PKE_REG_C2      0x16
#define PKE_REG_C3      0x17
/* one plus last index */
#define PKE_NUM_REGS    0x18

#define PKE_REGISTER_WINDOW_SIZE  (sizeof(quadword) * PKE_NUM_REGS)


/* PKE commands */

#define PKE_CMD_PKENOP_MASK 0x7F
#define PKE_CMD_PKENOP_BITS 0x00
#define PKE_CMD_STCYCL_MASK 0x7F
#define PKE_CMD_STCYCL_BITS 0x01
#define PKE_CMD_OFFSET_MASK 0x7F
#define PKE_CMD_OFFSET_BITS 0x02
#define PKE_CMD_BASE_MASK 0x7F
#define PKE_CMD_BASE_BITS 0x03
#define PKE_CMD_ITOP_MASK 0x7F
#define PKE_CMD_ITOP_BITS 0x04
#define PKE_CMD_STMOD_MASK 0x7F
#define PKE_CMD_STMOD_BITS 0x05
#define PKE_CMD_MSKPATH3_MASK 0x7F
#define PKE_CMD_MSKPATH3_BITS 0x06
#define PKE_CMD_PKEMARK_MASK 0x7F
#define PKE_CMD_PKEMARK_BITS 0x07
#define PKE_CMD_FLUSHE_MASK 0x7F
#define PKE_CMD_FLUSHE_BITS 0x10
#define PKE_CMD_FLUSH_MASK 0x7F
#define PKE_CMD_FLUSH_BITS 0x11
#define PKE_CMD_FLUSHA_MASK 0x7F
#define PKE_CMD_FLUSHA_BITS 0x13
#define PKE_CMD_PKEMSCAL_MASK 0x7F  /* CAL == "call" */
#define PKE_CMD_PKEMSCAL_BITS 0x14
#define PKE_CMD_PKEMSCNT_MASK 0x7F  /* CNT == "continue" */
#define PKE_CMD_PKEMSCNT_BITS 0x17
#define PKE_CMD_PKEMSCALF_MASK 0x7F /* CALF == "call after flush" */
#define PKE_CMD_PKEMSCALF_BITS 0x15
#define PKE_CMD_STMASK_MASK 0x7F
#define PKE_CMD_STMASK_BITS 0x20
#define PKE_CMD_STROW_MASK 0x7F
#define PKE_CMD_STROW_BITS 0x30
#define PKE_CMD_STCOL_MASK 0x7F
#define PKE_CMD_STCOL_BITS 0x31
#define PKE_CMD_MPG_MASK 0x7F
#define PKE_CMD_MPG_BITS 0x4A
#define PKE_CMD_DIRECT_MASK 0x7F
#define PKE_CMD_DIRECT_BITS 0x50
#define PKE_CMD_DIRECTHL_MASK 0x7F
#define PKE_CMD_DIRECTHL_BITS 0x51
#define PKE_CMD_UNPACK_MASK 0x60
#define PKE_CMD_UNPACK_BITS 0x60

/* test given word for particular PKE command bit pattern */
#define IS_PKE_CMD(word,cmd) (((word) & PKE_CMD_##cmd##_MASK) == PKE_CMD_##cmd##_BITS)


/* register bitmasks: bit numbers for end and beginning of fields */

/* PKE opcode */
#define PKE_OPCODE_I_E 31
#define PKE_OPCODE_I_B 31
#define PKE_OPCODE_CMD_E 30
#define PKE_OPCODE_CMD_B 24
#define PKE_OPCODE_NUM_E 23
#define PKE_OPCODE_NUM_B 16
#define PKE_OPCODE_IMM_E 15
#define PKE_OPCODE_IMM_B 0

/* STAT register */
#define PKE_REG_STAT_FQC_E 28
#define PKE_REG_STAT_FQC_B 24
#define PKE_REG_STAT_FDR_E 23
#define PKE_REG_STAT_FDR_B 23
#define PKE_REG_STAT_ER1_E 13
#define PKE_REG_STAT_ER1_B 13
#define PKE_REG_STAT_ER0_E 12
#define PKE_REG_STAT_ER0_B 12
#define PKE_REG_STAT_INT_E 11
#define PKE_REG_STAT_INT_B 11
#define PKE_REG_STAT_PIS_E 10
#define PKE_REG_STAT_PIS_B 10
#define PKE_REG_STAT_PFS_E 9
#define PKE_REG_STAT_PFS_B 9
#define PKE_REG_STAT_PSS_E 8
#define PKE_REG_STAT_PSS_B 8
#define PKE_REG_STAT_DBF_E 7
#define PKE_REG_STAT_DBF_B 7
#define PKE_REG_STAT_MRK_E 6
#define PKE_REG_STAT_MRK_B 6
#define PKE_REG_STAT_PGW_E 3
#define PKE_REG_STAT_PGW_B 3
#define PKE_REG_STAT_PEW_E 2
#define PKE_REG_STAT_PEW_B 2
#define PKE_REG_STAT_PPS_E 1
#define PKE_REG_STAT_PPS_B 0

#define PKE_REG_STAT_PPS_IDLE 0x00 /* ready to execute next instruction */
#define PKE_REG_STAT_PPS_WAIT 0x01 /* not enough words in FIFO */
#define PKE_REG_STAT_PPS_DECODE 0x02 /* decoding instruction */
#define PKE_REG_STAT_PPS_STALL 0x02 /* alias state for FLUSHE stall */
#define PKE_REG_STAT_PPS_XFER 0x03 /* transferring instruction operands */

/* DBF register */
#define PKE_REG_DBF_DF_E 0
#define PKE_REG_DBF_DF_B 0

/* OFST register */
#define PKE_REG_OFST_OFFSET_E 9
#define PKE_REG_OFST_OFFSET_B 0

/* OFST register */
#define PKE_REG_TOPS_TOPS_E 9
#define PKE_REG_TOPS_TOPS_B 0

/* BASE register */
#define PKE_REG_BASE_BASE_E 9
#define PKE_REG_BASE_BASE_B 0

/* ITOPS register */
#define PKE_REG_ITOPS_ITOPS_E 9
#define PKE_REG_ITOPS_ITOPS_B 0

/* MODE register */
#define PKE_REG_MODE_MDE_E 1
#define PKE_REG_MODE_MDE_B 0

/* NUM register */
#define PKE_REG_NUM_NUM_E 9
#define PKE_REG_NUM_NUM_B 0

/* MARK register */
#define PKE_REG_MARK_MARK_E 15
#define PKE_REG_MARK_MARK_B 0

/* ITOP register */
#define PKE_REG_ITOP_ITOP_E 9
#define PKE_REG_ITOP_ITOP_B 0

/* TOP register */
#define PKE_REG_TOP_TOP_E 9
#define PKE_REG_TOP_TOP_B 0

/* MASK register */
#define PKE_REG_MASK_MASK_E 31
#define PKE_REG_MASK_MASK_B 0

/* CYCLE register */
#define PKE_REG_CYCLE_WL_E 15
#define PKE_REG_CYCLE_WL_B 8
#define PKE_REG_CYCLE_CL_E 7
#define PKE_REG_CYCLE_CL_B 0

/* ERR register */
#define PKE_REG_ERR_ME1_E 2
#define PKE_REG_ERR_ME1_B 2
#define PKE_REG_ERR_ME0_E 1
#define PKE_REG_ERR_ME0_B 1
#define PKE_REG_ERR_MII_E 0
#define PKE_REG_ERR_MII_B 0


/* UNPACK opcodes */
#define PKE_UNPACK(vn,vl) ((vn) << 2 | (vl))
#define PKE_UNPACK_S_32  PKE_UNPACK(0, 0)
#define PKE_UNPACK_S_16  PKE_UNPACK(0, 1)
#define PKE_UNPACK_S_8   PKE_UNPACK(0, 2)
#define PKE_UNPACK_V2_32 PKE_UNPACK(1, 0)
#define PKE_UNPACK_V2_16 PKE_UNPACK(1, 1)
#define PKE_UNPACK_V2_8  PKE_UNPACK(1, 2)
#define PKE_UNPACK_V3_32 PKE_UNPACK(2, 0)
#define PKE_UNPACK_V3_16 PKE_UNPACK(2, 1)
#define PKE_UNPACK_V3_8  PKE_UNPACK(2, 2)
#define PKE_UNPACK_V4_32 PKE_UNPACK(3, 0)
#define PKE_UNPACK_V4_16 PKE_UNPACK(3, 1)
#define PKE_UNPACK_V4_8  PKE_UNPACK(3, 2)
#define PKE_UNPACK_V4_5  PKE_UNPACK(3, 3)


/* MASK register sub-field definitions */
#define PKE_MASKREG_INPUT 0
#define PKE_MASKREG_ROW 1
#define PKE_MASKREG_COLUMN 2
#define PKE_MASKREG_NOTHING 3


/* STMOD register field definitions */
#define PKE_MODE_INPUT 0
#define PKE_MODE_ADDROW 1
#define PKE_MODE_ACCROW 2


/* extract a MASK register sub-field for row [0..3] and column [0..3] */
/* MASK register is laid out of 2-bit values in this r-c order */
/* m33 m32 m31 m30 m23 m22 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00 */
#define PKE_MASKREG_GET(me,row,col) \
((((me)->regs[PKE_REG_MASK][0]) >> (8*(row) + 2*(col))) & 0x03)


/* operations - replace with those in sim-bits.h when convenient */

/* unsigned 32-bit mask of given width */
#define BIT_MASK(width) ((width) == 31 ? 0xffffffff : (((unsigned_4)1) << (width+1)) - 1)
/* e.g.: BIT_MASK(4) = 00011111 */

/* mask between given given bits numbers (MSB) */
#define BIT_MASK_BTW(begin,end) ((BIT_MASK(end) & ~((begin) == 0 ? 0 : BIT_MASK((begin)-1))))
/* e.g.: BIT_MASK_BTW(4,11) = 0000111111110000 */

/* set bitfield value */
#define BIT_MASK_SET(lvalue,begin,end,value) \
do { \
  ASSERT((begin) <= (end)); \
  (lvalue) &= ~BIT_MASK_BTW((begin),(end)); \
  (lvalue) |= ((value) << (begin)) & BIT_MASK_BTW((begin),(end)); \
} while(0)

/* get bitfield value */
#define BIT_MASK_GET(rvalue,begin,end) \
  (((rvalue) & BIT_MASK_BTW(begin,end)) >> (begin))
/* e.g., BIT_MASK_GET(0000111100001111, 2, 8) = 0000000100001100 */

/* These ugly macro hacks allow succinct bitfield accesses */
/* set a bitfield in a register by "name" */
#define PKE_REG_MASK_SET(me,reg,flag,value) \
     do { \
       unsigned_4 old = BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
		    PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E); \
       BIT_MASK_SET(((me)->regs[PKE_REG_##reg][0]), \
		    PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E, \
		    (value)); \
       if((me)->fifo_trace_file != NULL) \
	 { \
	   if(old != (value)) \
	     fprintf((me)->fifo_trace_file, "# Reg %s:%s = 0x%x\n", #reg, #flag, (unsigned)(value)); \
	 } \
     } while(0)

/* get a bitfield from a register by "name" */
#define PKE_REG_MASK_GET(me,reg,flag) \
     BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
                  PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E)


#define PKE_LIMIT(value,max) ((value) > (max) ? (max) : (value))


/* Classify words in a FIFO quadword */
enum wordclass
{
  wc_dma = 'D',
  wc_pkecode = 'P',
  wc_unknown = '?',
  wc_pkedata = '.'
};


/* One row in the FIFO */
struct fifo_quadword
{
  /* 128 bits of data */
  quadword data;
  /* source main memory address (or 0: unknown) */
  unsigned_4 source_address;
  /* classification of words in quadword; wc_dma set on DMA tags at FIFO write */
  enum wordclass word_class[4];
};


/* PKE internal state: FIFOs, registers, handle to VU friend */
struct pke_device
{
  /* common device info */
  device dev;

  /* identity: 0=PKE0, 1=PKE1 */
  int pke_number;
  int flags;

  /* quadword registers: data in [0] word only */
  quadword regs[PKE_NUM_REGS];

  /* write buffer for FIFO address */
  quadword fifo_qw_in_progress;
  int fifo_qw_done; /* bitfield */

  /* FIFO */
  struct fifo_quadword* fifo;
  int fifo_num_elements; /* no. of quadwords occupied in FIFO */
  int fifo_buffer_size;  /* no. of quadwords of space in FIFO */
  FILE* fifo_trace_file; /* or 0 for no trace */

  /* PC */
  int fifo_pc;  /* 0 .. (fifo_num_elements-1): quadword index of next instruction */
  int qw_pc;    /* 0 .. 3:                     word index of next instruction */
};


/* Flags for PKE.flags */

#define PKE_FLAG_NONE        0x00
#define PKE_FLAG_PENDING_PSS 0x01 /* PSS bit written-to; set STAT:PSS after current instruction */


/* Kludge alert */

#define PKE_MEM_READ(me,addr,data,size) \
    do { \
      sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
      unsigned_##size value = \
	sim_core_read_aligned_##size(cpu, CIA_GET(cpu), sim_core_read_map, \
				     (SIM_ADDR)(addr)); \
      memcpy((unsigned_##size*) (data), (void*) & value, size); \
      if(me->fifo_trace_file != NULL) \
	{ \
	  int i; \
	  fprintf((me)->fifo_trace_file, "# Read  %2d bytes from ", size); \
	  fprintf((me)->fifo_trace_file, "0x%08lx: ", (unsigned long)(addr)); \
	  for(i=0; i<size; i++) \
	    fprintf((me)->fifo_trace_file, " %02x", ((unsigned_1*)(& value))[i]); \
	  fprintf((me)->fifo_trace_file, "\n"); \
	} \
     } while(0)

#define PKE_MEM_WRITE(me,addr,data,size) \
    do { sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
         unsigned_##size value; \
         memcpy((void*) & value, (unsigned_##size*)(data), size); \
         sim_core_write_aligned_##size(cpu, CIA_GET(cpu), sim_core_write_map, \
				       (SIM_ADDR)(addr), value); \
         if((me)->fifo_trace_file != NULL) \
	   { \
	     int i; \
	     fprintf((me)->fifo_trace_file, "# Write %2d bytes  to  ", size); \
	     fprintf((me)->fifo_trace_file, "0x%08lx: ", (unsigned long)(addr)); \
	     for(i=0; i<size; i++) \
	       fprintf((me)->fifo_trace_file, " %02x", ((unsigned_1*)(& value))[i]); \
 	     fprintf((me)->fifo_trace_file, "\n"); \
	   } \
        } while(0)      


#endif /* H_PKE_H */
Commit	Line	Data
aea481da DE	1	/* Copyright (C) 1998, Cygnus Solutions */
	2
	3	#ifndef H_PKE_H
	4	#define H_PKE_H
	5
	6	#include "sim-main.h"
803f52b9	7	#include "sky-device.h"
aea481da DE	8
aea481da DE	9
fba9bfed	10
aea481da DE	11	/* External functions */
	12
	13	void pke0_attach(SIM_DESC sd);
e2306992	14	void pke0_issue(SIM_DESC sd);
aea481da	15	void pke1_attach(SIM_DESC sd);
e2306992 FCE	16	void pke1_issue(SIM_DESC sd);
e2306992 FCE	17
aea481da DE	18
	19	/* Quadword data type */
	20
fba9bfed	21	typedef unsigned_4 quadword[4];
aea481da DE	22
	23	/* truncate address to quadword */
	24	#define ADDR_TRUNC_QW(addr) ((addr) & ~0x0f)
	25	/* extract offset in quadword */
	26	#define ADDR_OFFSET_QW(addr) ((addr) & 0x0f)
	27
	28
	29	/* SCEI memory mapping information */
	30
db6dac32 FCE	31	#define PKE0_REGISTER_WINDOW_START 0x10003800
	32	#define PKE1_REGISTER_WINDOW_START 0x10003C00
	33	#define PKE0_FIFO_ADDR 0x10004000
	34	#define PKE1_FIFO_ADDR 0x10005000
	35
	36
	37	/* and now a few definitions that rightfully belong elsewhere */
	38	#ifdef PKE_DEBUG
	39
db6dac32 FCE	40
	41	/* VU source-addr tracking tables / / changed from 1998-01-22 e-mail plans */
	42	#define VU0_MEM0_SRCADDR_START 0x21000000
	43	#define VU0_MEM1_SRCADDR_START 0x21004000
	44	#define VU1_MEM0_SRCADDR_START 0x21008000
	45	#define VU1_MEM1_SRCADDR_START 0x2100C000
	46
	47	/* GPUIF STAT register */
	48	#define GPUIF_REG_STAT_APATH_E 11
	49	#define GPUIF_REG_STAT_APATH_B 10
	50
e2306992 FCE	51	/* COP2 STAT register */
	52	#define COP2_REG_STAT_ADDR VPU_STAT
	53	#define COP2_REG_STAT_VBS1_E 8
	54	#define COP2_REG_STAT_VBS1_B 8
	55	#define COP2_REG_STAT_VBS0_E 0
	56	#define COP2_REG_STAT_VBS0_B 0
	57
db6dac32	58	#endif /* PKE_DEBUG */
aea481da DE	59
	60
	61	/* Quadword indices of PKE registers. Actual registers sit at bottom
	62	32 bits of each quadword. */
	63	#define PKE_REG_STAT 0x00
	64	#define PKE_REG_FBRST 0x01
	65	#define PKE_REG_ERR 0x02
	66	#define PKE_REG_MARK 0x03
	67	#define PKE_REG_CYCLE 0x04
	68	#define PKE_REG_MODE 0x05
	69	#define PKE_REG_NUM 0x06
	70	#define PKE_REG_MASK 0x07
	71	#define PKE_REG_CODE 0x08
	72	#define PKE_REG_ITOPS 0x09
	73	#define PKE_REG_BASE 0x0a /* pke1 only */
	74	#define PKE_REG_OFST 0x0b /* pke1 only */
	75	#define PKE_REG_TOPS 0x0c /* pke1 only */
	76	#define PKE_REG_ITOP 0x0d
	77	#define PKE_REG_TOP 0x0e /* pke1 only */
	78	#define PKE_REG_DBF 0x0f /* pke1 only */
fba9bfed	79	#define PKE_REG_R0 0x10 /* R0 .. R3 must be contiguous */
aea481da DE	80	#define PKE_REG_R1 0x11
	81	#define PKE_REG_R2 0x12
	82	#define PKE_REG_R3 0x13
fba9bfed	83	#define PKE_REG_C0 0x14 /* C0 .. C3 must be contiguous */
aea481da DE	84	#define PKE_REG_C1 0x15
	85	#define PKE_REG_C2 0x16
	86	#define PKE_REG_C3 0x17
	87	/* one plus last index */
	88	#define PKE_NUM_REGS 0x18
	89
	90	#define PKE_REGISTER_WINDOW_SIZE (sizeof(quadword) * PKE_NUM_REGS)
	91
fba9bfed	92
aea481da	93
fba9bfed FCE	94	/* PKE commands */
	95
	96	#define PKE_CMD_PKENOP_MASK 0x7F
	97	#define PKE_CMD_PKENOP_BITS 0x00
	98	#define PKE_CMD_STCYCL_MASK 0x7F
	99	#define PKE_CMD_STCYCL_BITS 0x01
	100	#define PKE_CMD_OFFSET_MASK 0x7F
	101	#define PKE_CMD_OFFSET_BITS 0x02
	102	#define PKE_CMD_BASE_MASK 0x7F
	103	#define PKE_CMD_BASE_BITS 0x03
	104	#define PKE_CMD_ITOP_MASK 0x7F
	105	#define PKE_CMD_ITOP_BITS 0x04
	106	#define PKE_CMD_STMOD_MASK 0x7F
	107	#define PKE_CMD_STMOD_BITS 0x05
	108	#define PKE_CMD_MSKPATH3_MASK 0x7F
	109	#define PKE_CMD_MSKPATH3_BITS 0x06
	110	#define PKE_CMD_PKEMARK_MASK 0x7F
	111	#define PKE_CMD_PKEMARK_BITS 0x07
	112	#define PKE_CMD_FLUSHE_MASK 0x7F
	113	#define PKE_CMD_FLUSHE_BITS 0x10
	114	#define PKE_CMD_FLUSH_MASK 0x7F
	115	#define PKE_CMD_FLUSH_BITS 0x11
	116	#define PKE_CMD_FLUSHA_MASK 0x7F
	117	#define PKE_CMD_FLUSHA_BITS 0x13
	118	#define PKE_CMD_PKEMSCAL_MASK 0x7F /* CAL == "call" */
	119	#define PKE_CMD_PKEMSCAL_BITS 0x14
	120	#define PKE_CMD_PKEMSCNT_MASK 0x7F /* CNT == "continue" */
	121	#define PKE_CMD_PKEMSCNT_BITS 0x17
	122	#define PKE_CMD_PKEMSCALF_MASK 0x7F /* CALF == "call after flush" */
	123	#define PKE_CMD_PKEMSCALF_BITS 0x15
	124	#define PKE_CMD_STMASK_MASK 0x7F
	125	#define PKE_CMD_STMASK_BITS 0x20
	126	#define PKE_CMD_STROW_MASK 0x7F
	127	#define PKE_CMD_STROW_BITS 0x30
	128	#define PKE_CMD_STCOL_MASK 0x7F
	129	#define PKE_CMD_STCOL_BITS 0x31
	130	#define PKE_CMD_MPG_MASK 0x7F
	131	#define PKE_CMD_MPG_BITS 0x4A
	132	#define PKE_CMD_DIRECT_MASK 0x7F
	133	#define PKE_CMD_DIRECT_BITS 0x50
	134	#define PKE_CMD_DIRECTHL_MASK 0x7F
	135	#define PKE_CMD_DIRECTHL_BITS 0x51
	136	#define PKE_CMD_UNPACK_MASK 0x60
	137	#define PKE_CMD_UNPACK_BITS 0x60
	138
	139	/* test given word for particular PKE command bit pattern */
	140	#define IS_PKE_CMD(word,cmd) (((word) & PKE_CMD_##cmd##_MASK) == PKE_CMD_##cmd##_BITS)
	141
	142
	143	/* register bitmasks: bit numbers for end and beginning of fields */
	144
	145	/* PKE opcode */
	146	#define PKE_OPCODE_I_E 31
	147	#define PKE_OPCODE_I_B 31
	148	#define PKE_OPCODE_CMD_E 30
	149	#define PKE_OPCODE_CMD_B 24
	150	#define PKE_OPCODE_NUM_E 23
	151	#define PKE_OPCODE_NUM_B 16
	152	#define PKE_OPCODE_IMM_E 15
	153	#define PKE_OPCODE_IMM_B 0
	154
	155	/* STAT register */
	156	#define PKE_REG_STAT_FQC_E 28
	157	#define PKE_REG_STAT_FQC_B 24
158	#define PKE_REG_STAT_FDR_E 23
159	#define PKE_REG_STAT_FDR_B 23
160	#define PKE_REG_STAT_ER1_E 13
161	#define PKE_REG_STAT_ER1_B 13
162	#define PKE_REG_STAT_ER0_E 12
163	#define PKE_REG_STAT_ER0_B 12
164	#define PKE_REG_STAT_INT_E 11
165	#define PKE_REG_STAT_INT_B 11
166	#define PKE_REG_STAT_PIS_E 10
167	#define PKE_REG_STAT_PIS_B 10
168	#define PKE_REG_STAT_PFS_E 9
169	#define PKE_REG_STAT_PFS_B 9
170	#define PKE_REG_STAT_PSS_E 8
171	#define PKE_REG_STAT_PSS_B 8
172	#define PKE_REG_STAT_DBF_E 7
173	#define PKE_REG_STAT_DBF_B 7
174	#define PKE_REG_STAT_MRK_E 6
175	#define PKE_REG_STAT_MRK_B 6
176	#define PKE_REG_STAT_PGW_E 3
177	#define PKE_REG_STAT_PGW_B 3
178	#define PKE_REG_STAT_PEW_E 2
179	#define PKE_REG_STAT_PEW_B 2
180	#define PKE_REG_STAT_PPS_E 1
181	#define PKE_REG_STAT_PPS_B 0
182
43a6998b FCE	183	#define PKE_REG_STAT_PPS_IDLE 0x00 /* ready to execute next instruction */
	184	#define PKE_REG_STAT_PPS_WAIT 0x01 /* not enough words in FIFO */
	185	#define PKE_REG_STAT_PPS_DECODE 0x02 /* decoding instruction */
	186	#define PKE_REG_STAT_PPS_STALL 0x02 /* alias state for FLUSHE stall */
	187	#define PKE_REG_STAT_PPS_XFER 0x03 /* transferring instruction operands */
fba9bfed FCE	188
	189	/* DBF register */
	190	#define PKE_REG_DBF_DF_E 0
	191	#define PKE_REG_DBF_DF_B 0
	192
	193	/* OFST register */
	194	#define PKE_REG_OFST_OFFSET_E 9
	195	#define PKE_REG_OFST_OFFSET_B 0
	196
	197	/* OFST register */
	198	#define PKE_REG_TOPS_TOPS_E 9
	199	#define PKE_REG_TOPS_TOPS_B 0
	200
	201	/* BASE register */
	202	#define PKE_REG_BASE_BASE_E 9
	203	#define PKE_REG_BASE_BASE_B 0
	204
	205	/* ITOPS register */
	206	#define PKE_REG_ITOPS_ITOPS_E 9
	207	#define PKE_REG_ITOPS_ITOPS_B 0
	208
	209	/* MODE register */
	210	#define PKE_REG_MODE_MDE_E 1
	211	#define PKE_REG_MODE_MDE_B 0
	212
db6dac32 FCE	213	/* NUM register */
	214	#define PKE_REG_NUM_NUM_E 9
	215	#define PKE_REG_NUM_NUM_B 0
	216
fba9bfed FCE	217	/* MARK register */
	218	#define PKE_REG_MARK_MARK_E 15
	219	#define PKE_REG_MARK_MARK_B 0
	220
	221	/* ITOP register */
	222	#define PKE_REG_ITOP_ITOP_E 9
	223	#define PKE_REG_ITOP_ITOP_B 0
	224
	225	/* TOP register */
	226	#define PKE_REG_TOP_TOP_E 9
	227	#define PKE_REG_TOP_TOP_B 0
	228
	229	/* MASK register */
	230	#define PKE_REG_MASK_MASK_E 31
	231	#define PKE_REG_MASK_MASK_B 0
	232
	233	/* CYCLE register */
	234	#define PKE_REG_CYCLE_WL_E 15
	235	#define PKE_REG_CYCLE_WL_B 8
	236	#define PKE_REG_CYCLE_CL_E 7
	237	#define PKE_REG_CYCLE_CL_B 0
	238
	239	/* ERR register */
	240	#define PKE_REG_ERR_ME1_E 2
	241	#define PKE_REG_ERR_ME1_B 2
	242	#define PKE_REG_ERR_ME0_E 1
	243	#define PKE_REG_ERR_ME0_B 1
	244	#define PKE_REG_ERR_MII_E 0
	245	#define PKE_REG_ERR_MII_B 0
	246
	247
fba9bfed FCE	248	/* UNPACK opcodes */
	249	#define PKE_UNPACK(vn,vl) ((vn) << 2 \| (vl))
	250	#define PKE_UNPACK_S_32 PKE_UNPACK(0, 0)
	251	#define PKE_UNPACK_S_16 PKE_UNPACK(0, 1)
	252	#define PKE_UNPACK_S_8 PKE_UNPACK(0, 2)
	253	#define PKE_UNPACK_V2_32 PKE_UNPACK(1, 0)
	254	#define PKE_UNPACK_V2_16 PKE_UNPACK(1, 1)
	255	#define PKE_UNPACK_V2_8 PKE_UNPACK(1, 2)
	256	#define PKE_UNPACK_V3_32 PKE_UNPACK(2, 0)
	257	#define PKE_UNPACK_V3_16 PKE_UNPACK(2, 1)
	258	#define PKE_UNPACK_V3_8 PKE_UNPACK(2, 2)
	259	#define PKE_UNPACK_V4_32 PKE_UNPACK(3, 0)
	260	#define PKE_UNPACK_V4_16 PKE_UNPACK(3, 1)
	261	#define PKE_UNPACK_V4_8 PKE_UNPACK(3, 2)
	262	#define PKE_UNPACK_V4_5 PKE_UNPACK(3, 3)
	263
	264
	265	/* MASK register sub-field definitions */
	266	#define PKE_MASKREG_INPUT 0
	267	#define PKE_MASKREG_ROW 1
	268	#define PKE_MASKREG_COLUMN 2
	269	#define PKE_MASKREG_NOTHING 3
	270
	271
	272	/* STMOD register field definitions */
	273	#define PKE_MODE_INPUT 0
	274	#define PKE_MODE_ADDROW 1
	275	#define PKE_MODE_ACCROW 2
	276
	277
	278	/* extract a MASK register sub-field for row [0..3] and column [0..3] */
	279	/* MASK register is laid out of 2-bit values in this r-c order */
	280	/* m33 m32 m31 m30 m23 m22 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00 */
	281	#define PKE_MASKREG_GET(me,row,col) \
	282	((((me)->regs[PKE_REG_MASK][0]) >> (8(row) + 2(col))) & 0x03)
	283
	284
db6dac32	285	/* operations - replace with those in sim-bits.h when convenient */
fba9bfed	286
fba9bfed	287	/* unsigned 32-bit mask of given width */
e2306992	288	#define BIT_MASK(width) ((width) == 31 ? 0xffffffff : (((unsigned_4)1) << (width+1)) - 1)
52793fab	289	/* e.g.: BIT_MASK(4) = 00011111 */
fba9bfed FCE	290
fba9bfed FCE	291	/* mask between given given bits numbers (MSB) */
e2306992	292	#define BIT_MASK_BTW(begin,end) ((BIT_MASK(end) & ~((begin) == 0 ? 0 : BIT_MASK((begin)-1))))
fba9bfed FCE	293	/* e.g.: BIT_MASK_BTW(4,11) = 0000111111110000 */
	294
	295	/* set bitfield value */
	296	#define BIT_MASK_SET(lvalue,begin,end,value) \
	297	do { \
534a3d5c FCE	298	ASSERT((begin) <= (end)); \
	299	(lvalue) &= ~BIT_MASK_BTW((begin),(end)); \
	300	(lvalue) \|= ((value) << (begin)) & BIT_MASK_BTW((begin),(end)); \
fba9bfed FCE	301	} while(0)
	302
	303	/* get bitfield value */
	304	#define BIT_MASK_GET(rvalue,begin,end) \
	305	(((rvalue) & BIT_MASK_BTW(begin,end)) >> (begin))
	306	/* e.g., BIT_MASK_GET(0000111100001111, 2, 8) = 0000000100001100 */
	307
fba9bfed FCE	308	/* These ugly macro hacks allow succinct bitfield accesses */
	309	/* set a bitfield in a register by "name" */
	310	#define PKE_REG_MASK_SET(me,reg,flag,value) \
534a3d5c FCE	311	do { \
	312	unsigned_4 old = BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
	313	PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E); \
	314	BIT_MASK_SET(((me)->regs[PKE_REG_##reg][0]), \
	315	PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E, \
	316	(value)); \
	317	if((me)->fifo_trace_file != NULL) \
	318	{ \
	319	if(old != (value)) \
	320	fprintf((me)->fifo_trace_file, "# Reg %s:%s = 0x%x\n", #reg, #flag, (unsigned)(value)); \
	321	} \
	322	} while(0)
fba9bfed FCE	323
	324	/* get a bitfield from a register by "name" */
	325	#define PKE_REG_MASK_GET(me,reg,flag) \
	326	BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
	327	PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E)
	328
	329
	330	#define PKE_LIMIT(value,max) ((value) > (max) ? (max) : (value))
	331
	332
e2306992 FCE	333	/* Classify words in a FIFO quadword */
	334	enum wordclass
	335	{
	336	wc_dma = 'D',
	337	wc_pkecode = 'P',
	338	wc_unknown = '?',
	339	wc_pkedata = '.'
	340	};
	341
	342
aea481da DE	343	/* One row in the FIFO */
	344	struct fifo_quadword
	345	{
	346	/* 128 bits of data */
	347	quadword data;
	348	/* source main memory address (or 0: unknown) */
e2306992 FCE	349	unsigned_4 source_address;
	350	/* classification of words in quadword; wc_dma set on DMA tags at FIFO write */
	351	enum wordclass word_class[4];
aea481da DE	352	};
	353
	354
	355	/* PKE internal state: FIFOs, registers, handle to VU friend */
	356	struct pke_device
	357	{
	358	/* common device info */
	359	device dev;
	360
	361	/* identity: 0=PKE0, 1=PKE1 */
	362	int pke_number;
	363	int flags;
	364
db6dac32	365	/* quadword registers: data in [0] word only */
aea481da DE	366	quadword regs[PKE_NUM_REGS];
aea481da DE	367
db6dac32 FCE	368	/* write buffer for FIFO address */
	369	quadword fifo_qw_in_progress;
	370	int fifo_qw_done; /* bitfield */
	371
aea481da DE	372	/* FIFO */
	373	struct fifo_quadword* fifo;
	374	int fifo_num_elements; /* no. of quadwords occupied in FIFO */
	375	int fifo_buffer_size; /* no. of quadwords of space in FIFO */
e2306992	376	FILE* fifo_trace_file; /* or 0 for no trace */
aea481da	377
fba9bfed FCE	378	/* PC */
	379	int fifo_pc; /* 0 .. (fifo_num_elements-1): quadword index of next instruction */
	380	int qw_pc; /* 0 .. 3: word index of next instruction */
aea481da DE	381	};
	382
	383
	384	/* Flags for PKE.flags */
	385
db6dac32 FCE	386	#define PKE_FLAG_NONE 0x00
db6dac32 FCE	387	#define PKE_FLAG_PENDING_PSS 0x01 /* PSS bit written-to; set STAT:PSS after current instruction */
aea481da DE	388
aea481da DE	389
e2306992 FCE	390	/* Kludge alert */
e2306992 FCE	391
534a3d5c FCE	392	#define PKE_MEM_READ(me,addr,data,size) \
	393	do { \
	394	sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
	395	unsigned_##size value = \
	396	sim_core_read_aligned_##size(cpu, CIA_GET(cpu), sim_core_read_map, \
	397	(SIM_ADDR)(addr)); \
	398	memcpy((unsigned_##size) (data), (void) & value, size); \
	399	if(me->fifo_trace_file != NULL) \
	400	{ \
	401	int i; \
	402	fprintf((me)->fifo_trace_file, "# Read %2d bytes from ", size); \
	403	fprintf((me)->fifo_trace_file, "0x%08lx: ", (unsigned long)(addr)); \
	404	for(i=0; i<size; i++) \
	405	fprintf((me)->fifo_trace_file, " %02x", ((unsigned_1*)(& value))[i]); \
	406	fprintf((me)->fifo_trace_file, "\n"); \
	407	} \
	408	} while(0)
	409
	410	#define PKE_MEM_WRITE(me,addr,data,size) \
	411	do { sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
e2306992	412	unsigned_##size value; \
534a3d5c	413	memcpy((void) & value, (unsigned_##size)(data), size); \
e2306992	414	sim_core_write_aligned_##size(cpu, CIA_GET(cpu), sim_core_write_map, \
534a3d5c FCE	415	(SIM_ADDR)(addr), value); \
	416	if((me)->fifo_trace_file != NULL) \
	417	{ \
	418	int i; \
	419	fprintf((me)->fifo_trace_file, "# Write %2d bytes to ", size); \
	420	fprintf((me)->fifo_trace_file, "0x%08lx: ", (unsigned long)(addr)); \
	421	for(i=0; i<size; i++) \
	422	fprintf((me)->fifo_trace_file, " %02x", ((unsigned_1*)(& value))[i]); \
	423	fprintf((me)->fifo_trace_file, "\n"); \
	424	} \
	425	} while(0)
e2306992 FCE	426
	427
	428
aea481da	429	#endif /* H_PKE_H */