projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| aea481da DE |
1 | /* Copyright (C) 1998, Cygnus Solutions */ |
| 2 | ||
| 3 | #ifndef H_PKE_H | |
| 4 | #define H_PKE_H | |
| 5 | ||
| 6 | #include "sim-main.h" | |
| 7 | #include "device.h" | |
| 8 | ||
| 9 | ||
| 10 | /* External functions */ | |
| 11 | ||
| 12 | void pke0_attach(SIM_DESC sd); | |
| 13 | void pke0_issue(); | |
| 14 | void pke1_attach(SIM_DESC sd); | |
| 15 | void pke1_issue(); | |
| 16 | ||
| 17 | ||
| 18 | /* Quadword data type */ | |
| 19 | ||
| 20 | typedef unsigned int quadword[4]; | |
| 21 | ||
| 22 | /* truncate address to quadword */ | |
| 23 | #define ADDR_TRUNC_QW(addr) ((addr) & ~0x0f) | |
| 24 | /* extract offset in quadword */ | |
| 25 | #define ADDR_OFFSET_QW(addr) ((addr) & 0x0f) | |
| 26 | ||
| 27 | ||
| 28 | /* SCEI memory mapping information */ | |
| 29 | ||
| 30 | #define PKE0_REGISTER_WINDOW_START 0x10000800 | |
| 31 | #define PKE1_REGISTER_WINDOW_START 0x10000A00 | |
| 32 | #define PKE0_FIFO_START 0x10008000 | |
| 33 | #define PKE1_FIFO_START 0x10008010 | |
| 34 | ||
| 35 | ||
| 36 | /* Quadword indices of PKE registers. Actual registers sit at bottom | |
| 37 | 32 bits of each quadword. */ | |
| 38 | #define PKE_REG_STAT 0x00 | |
| 39 | #define PKE_REG_FBRST 0x01 | |
| 40 | #define PKE_REG_ERR 0x02 | |
| 41 | #define PKE_REG_MARK 0x03 | |
| 42 | #define PKE_REG_CYCLE 0x04 | |
| 43 | #define PKE_REG_MODE 0x05 | |
| 44 | #define PKE_REG_NUM 0x06 | |
| 45 | #define PKE_REG_MASK 0x07 | |
| 46 | #define PKE_REG_CODE 0x08 | |
| 47 | #define PKE_REG_ITOPS 0x09 | |
| 48 | #define PKE_REG_BASE 0x0a /* pke1 only */ | |
| 49 | #define PKE_REG_OFST 0x0b /* pke1 only */ | |
| 50 | #define PKE_REG_TOPS 0x0c /* pke1 only */ | |
| 51 | #define PKE_REG_ITOP 0x0d | |
| 52 | #define PKE_REG_TOP 0x0e /* pke1 only */ | |
| 53 | #define PKE_REG_DBF 0x0f /* pke1 only */ | |
| 54 | #define PKE_REG_R0 0x10 | |
| 55 | #define PKE_REG_R1 0x11 | |
| 56 | #define PKE_REG_R2 0x12 | |
| 57 | #define PKE_REG_R3 0x13 | |
| 58 | #define PKE_REG_C0 0x14 | |
| 59 | #define PKE_REG_C1 0x15 | |
| 60 | #define PKE_REG_C2 0x16 | |
| 61 | #define PKE_REG_C3 0x17 | |
| 62 | /* one plus last index */ | |
| 63 | #define PKE_NUM_REGS 0x18 | |
| 64 | ||
| 65 | #define PKE_REGISTER_WINDOW_SIZE (sizeof(quadword) * PKE_NUM_REGS) | |
| 66 | ||
| 67 | /* virtual addresses for source-addr tracking */ | |
| 68 | #define PKE0_SRCADDR 0x20000020 | |
| 69 | #define PKE1_SRCADDR 0x20000024 | |
| 70 | ||
| 71 | ||
| 72 | /* One row in the FIFO */ | |
| 73 | struct fifo_quadword | |
| 74 | { | |
| 75 | /* 128 bits of data */ | |
| 76 | quadword data; | |
| 77 | /* source main memory address (or 0: unknown) */ | |
| 78 | address_word source_address; | |
| 79 | }; | |
| 80 | ||
| 81 | ||
| 82 | /* PKE internal state: FIFOs, registers, handle to VU friend */ | |
| 83 | struct pke_device | |
| 84 | { | |
| 85 | /* common device info */ | |
| 86 | device dev; | |
| 87 | ||
| 88 | /* identity: 0=PKE0, 1=PKE1 */ | |
| 89 | int pke_number; | |
| 90 | int flags; | |
| 91 | ||
| 92 | address_word register_memory_addr; | |
| 93 | address_word fifo_memory_addr; | |
| 94 | ||
| 95 | /* quadword registers */ | |
| 96 | quadword regs[PKE_NUM_REGS]; | |
| 97 | ||
| 98 | /* FIFO */ | |
| 99 | struct fifo_quadword* fifo; | |
| 100 | int fifo_num_elements; /* no. of quadwords occupied in FIFO */ | |
| 101 | int fifo_buffer_size; /* no. of quadwords of space in FIFO */ | |
| 102 | FILE* fifo_trace_file; /* or 0 for no trace */ | |
| 103 | ||
| 104 | /* index into FIFO of current instruction */ | |
| 105 | int program_counter; | |
| 106 | ||
| 107 | }; | |
| 108 | ||
| 109 | ||
| 110 | /* Flags for PKE.flags */ | |
| 111 | ||
| 112 | #define PKE_FLAG_NONE 0 | |
| 113 | /* none at present */ | |
| 114 | ||
| 115 | ||
| 116 | ||
| 117 | #endif /* H_PKE_H */ |