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1 | /* Copyright (C) 1998, Cygnus Solutions */ |
2 | ||
3 | #ifndef H_PKE_H | |
4 | #define H_PKE_H | |
5 | ||
6 | #include "sim-main.h" | |
803f52b9 | 7 | #include "sky-device.h" |
aea481da DE |
8 | |
9 | ||
fba9bfed FCE |
10 | /* Debugguing PKE? */ |
11 | ||
12 | #define PKE_DEBUG | |
13 | ||
14 | ||
aea481da DE |
15 | /* External functions */ |
16 | ||
17 | void pke0_attach(SIM_DESC sd); | |
18 | void pke0_issue(); | |
19 | void pke1_attach(SIM_DESC sd); | |
20 | void pke1_issue(); | |
21 | ||
22 | ||
23 | /* Quadword data type */ | |
24 | ||
fba9bfed | 25 | typedef unsigned_4 quadword[4]; |
aea481da DE |
26 | |
27 | /* truncate address to quadword */ | |
28 | #define ADDR_TRUNC_QW(addr) ((addr) & ~0x0f) | |
29 | /* extract offset in quadword */ | |
30 | #define ADDR_OFFSET_QW(addr) ((addr) & 0x0f) | |
31 | ||
32 | ||
33 | /* SCEI memory mapping information */ | |
34 | ||
35 | #define PKE0_REGISTER_WINDOW_START 0x10000800 | |
36 | #define PKE1_REGISTER_WINDOW_START 0x10000A00 | |
fba9bfed FCE |
37 | #define PKE0_FIFO_ADDR 0x10008000 |
38 | #define PKE1_FIFO_ADDR 0x10008010 | |
aea481da DE |
39 | |
40 | ||
41 | /* Quadword indices of PKE registers. Actual registers sit at bottom | |
42 | 32 bits of each quadword. */ | |
43 | #define PKE_REG_STAT 0x00 | |
44 | #define PKE_REG_FBRST 0x01 | |
45 | #define PKE_REG_ERR 0x02 | |
46 | #define PKE_REG_MARK 0x03 | |
47 | #define PKE_REG_CYCLE 0x04 | |
48 | #define PKE_REG_MODE 0x05 | |
49 | #define PKE_REG_NUM 0x06 | |
50 | #define PKE_REG_MASK 0x07 | |
51 | #define PKE_REG_CODE 0x08 | |
52 | #define PKE_REG_ITOPS 0x09 | |
53 | #define PKE_REG_BASE 0x0a /* pke1 only */ | |
54 | #define PKE_REG_OFST 0x0b /* pke1 only */ | |
55 | #define PKE_REG_TOPS 0x0c /* pke1 only */ | |
56 | #define PKE_REG_ITOP 0x0d | |
57 | #define PKE_REG_TOP 0x0e /* pke1 only */ | |
58 | #define PKE_REG_DBF 0x0f /* pke1 only */ | |
fba9bfed | 59 | #define PKE_REG_R0 0x10 /* R0 .. R3 must be contiguous */ |
aea481da DE |
60 | #define PKE_REG_R1 0x11 |
61 | #define PKE_REG_R2 0x12 | |
62 | #define PKE_REG_R3 0x13 | |
fba9bfed | 63 | #define PKE_REG_C0 0x14 /* C0 .. C3 must be contiguous */ |
aea481da DE |
64 | #define PKE_REG_C1 0x15 |
65 | #define PKE_REG_C2 0x16 | |
66 | #define PKE_REG_C3 0x17 | |
67 | /* one plus last index */ | |
68 | #define PKE_NUM_REGS 0x18 | |
69 | ||
70 | #define PKE_REGISTER_WINDOW_SIZE (sizeof(quadword) * PKE_NUM_REGS) | |
71 | ||
fba9bfed | 72 | |
aea481da DE |
73 | /* virtual addresses for source-addr tracking */ |
74 | #define PKE0_SRCADDR 0x20000020 | |
75 | #define PKE1_SRCADDR 0x20000024 | |
76 | ||
77 | ||
fba9bfed FCE |
78 | /* PKE commands */ |
79 | ||
80 | #define PKE_CMD_PKENOP_MASK 0x7F | |
81 | #define PKE_CMD_PKENOP_BITS 0x00 | |
82 | #define PKE_CMD_STCYCL_MASK 0x7F | |
83 | #define PKE_CMD_STCYCL_BITS 0x01 | |
84 | #define PKE_CMD_OFFSET_MASK 0x7F | |
85 | #define PKE_CMD_OFFSET_BITS 0x02 | |
86 | #define PKE_CMD_BASE_MASK 0x7F | |
87 | #define PKE_CMD_BASE_BITS 0x03 | |
88 | #define PKE_CMD_ITOP_MASK 0x7F | |
89 | #define PKE_CMD_ITOP_BITS 0x04 | |
90 | #define PKE_CMD_STMOD_MASK 0x7F | |
91 | #define PKE_CMD_STMOD_BITS 0x05 | |
92 | #define PKE_CMD_MSKPATH3_MASK 0x7F | |
93 | #define PKE_CMD_MSKPATH3_BITS 0x06 | |
94 | #define PKE_CMD_PKEMARK_MASK 0x7F | |
95 | #define PKE_CMD_PKEMARK_BITS 0x07 | |
96 | #define PKE_CMD_FLUSHE_MASK 0x7F | |
97 | #define PKE_CMD_FLUSHE_BITS 0x10 | |
98 | #define PKE_CMD_FLUSH_MASK 0x7F | |
99 | #define PKE_CMD_FLUSH_BITS 0x11 | |
100 | #define PKE_CMD_FLUSHA_MASK 0x7F | |
101 | #define PKE_CMD_FLUSHA_BITS 0x13 | |
102 | #define PKE_CMD_PKEMSCAL_MASK 0x7F /* CAL == "call" */ | |
103 | #define PKE_CMD_PKEMSCAL_BITS 0x14 | |
104 | #define PKE_CMD_PKEMSCNT_MASK 0x7F /* CNT == "continue" */ | |
105 | #define PKE_CMD_PKEMSCNT_BITS 0x17 | |
106 | #define PKE_CMD_PKEMSCALF_MASK 0x7F /* CALF == "call after flush" */ | |
107 | #define PKE_CMD_PKEMSCALF_BITS 0x15 | |
108 | #define PKE_CMD_STMASK_MASK 0x7F | |
109 | #define PKE_CMD_STMASK_BITS 0x20 | |
110 | #define PKE_CMD_STROW_MASK 0x7F | |
111 | #define PKE_CMD_STROW_BITS 0x30 | |
112 | #define PKE_CMD_STCOL_MASK 0x7F | |
113 | #define PKE_CMD_STCOL_BITS 0x31 | |
114 | #define PKE_CMD_MPG_MASK 0x7F | |
115 | #define PKE_CMD_MPG_BITS 0x4A | |
116 | #define PKE_CMD_DIRECT_MASK 0x7F | |
117 | #define PKE_CMD_DIRECT_BITS 0x50 | |
118 | #define PKE_CMD_DIRECTHL_MASK 0x7F | |
119 | #define PKE_CMD_DIRECTHL_BITS 0x51 | |
120 | #define PKE_CMD_UNPACK_MASK 0x60 | |
121 | #define PKE_CMD_UNPACK_BITS 0x60 | |
122 | ||
123 | /* test given word for particular PKE command bit pattern */ | |
124 | #define IS_PKE_CMD(word,cmd) (((word) & PKE_CMD_##cmd##_MASK) == PKE_CMD_##cmd##_BITS) | |
125 | ||
126 | ||
127 | /* register bitmasks: bit numbers for end and beginning of fields */ | |
128 | ||
129 | /* PKE opcode */ | |
130 | #define PKE_OPCODE_I_E 31 | |
131 | #define PKE_OPCODE_I_B 31 | |
132 | #define PKE_OPCODE_CMD_E 30 | |
133 | #define PKE_OPCODE_CMD_B 24 | |
134 | #define PKE_OPCODE_NUM_E 23 | |
135 | #define PKE_OPCODE_NUM_B 16 | |
136 | #define PKE_OPCODE_IMM_E 15 | |
137 | #define PKE_OPCODE_IMM_B 0 | |
138 | ||
139 | /* STAT register */ | |
140 | #define PKE_REG_STAT_FQC_E 28 | |
141 | #define PKE_REG_STAT_FQC_B 24 | |
142 | #define PKE_REG_STAT_FDR_E 23 | |
143 | #define PKE_REG_STAT_FDR_B 23 | |
144 | #define PKE_REG_STAT_ER1_E 13 | |
145 | #define PKE_REG_STAT_ER1_B 13 | |
146 | #define PKE_REG_STAT_ER0_E 12 | |
147 | #define PKE_REG_STAT_ER0_B 12 | |
148 | #define PKE_REG_STAT_INT_E 11 | |
149 | #define PKE_REG_STAT_INT_B 11 | |
150 | #define PKE_REG_STAT_PIS_E 10 | |
151 | #define PKE_REG_STAT_PIS_B 10 | |
152 | #define PKE_REG_STAT_PFS_E 9 | |
153 | #define PKE_REG_STAT_PFS_B 9 | |
154 | #define PKE_REG_STAT_PSS_E 8 | |
155 | #define PKE_REG_STAT_PSS_B 8 | |
156 | #define PKE_REG_STAT_DBF_E 7 | |
157 | #define PKE_REG_STAT_DBF_B 7 | |
158 | #define PKE_REG_STAT_MRK_E 6 | |
159 | #define PKE_REG_STAT_MRK_B 6 | |
160 | #define PKE_REG_STAT_PGW_E 3 | |
161 | #define PKE_REG_STAT_PGW_B 3 | |
162 | #define PKE_REG_STAT_PEW_E 2 | |
163 | #define PKE_REG_STAT_PEW_B 2 | |
164 | #define PKE_REG_STAT_PPS_E 1 | |
165 | #define PKE_REG_STAT_PPS_B 0 | |
166 | ||
167 | #define PKE_REG_STAT_PPS_IDLE 0x00 | |
168 | #define PKE_REG_STAT_PPS_WAIT 0x01 | |
169 | #define PKE_REG_STAT_PPS_DECODE 0x02 | |
170 | #define PKE_REG_STAT_PPS_XFER 0x03 | |
171 | ||
172 | /* DBF register */ | |
173 | #define PKE_REG_DBF_DF_E 0 | |
174 | #define PKE_REG_DBF_DF_B 0 | |
175 | ||
176 | /* OFST register */ | |
177 | #define PKE_REG_OFST_OFFSET_E 9 | |
178 | #define PKE_REG_OFST_OFFSET_B 0 | |
179 | ||
180 | /* OFST register */ | |
181 | #define PKE_REG_TOPS_TOPS_E 9 | |
182 | #define PKE_REG_TOPS_TOPS_B 0 | |
183 | ||
184 | /* BASE register */ | |
185 | #define PKE_REG_BASE_BASE_E 9 | |
186 | #define PKE_REG_BASE_BASE_B 0 | |
187 | ||
188 | /* ITOPS register */ | |
189 | #define PKE_REG_ITOPS_ITOPS_E 9 | |
190 | #define PKE_REG_ITOPS_ITOPS_B 0 | |
191 | ||
192 | /* MODE register */ | |
193 | #define PKE_REG_MODE_MDE_E 1 | |
194 | #define PKE_REG_MODE_MDE_B 0 | |
195 | ||
196 | /* MARK register */ | |
197 | #define PKE_REG_MARK_MARK_E 15 | |
198 | #define PKE_REG_MARK_MARK_B 0 | |
199 | ||
200 | /* ITOP register */ | |
201 | #define PKE_REG_ITOP_ITOP_E 9 | |
202 | #define PKE_REG_ITOP_ITOP_B 0 | |
203 | ||
204 | /* TOP register */ | |
205 | #define PKE_REG_TOP_TOP_E 9 | |
206 | #define PKE_REG_TOP_TOP_B 0 | |
207 | ||
208 | /* MASK register */ | |
209 | #define PKE_REG_MASK_MASK_E 31 | |
210 | #define PKE_REG_MASK_MASK_B 0 | |
211 | ||
212 | /* CYCLE register */ | |
213 | #define PKE_REG_CYCLE_WL_E 15 | |
214 | #define PKE_REG_CYCLE_WL_B 8 | |
215 | #define PKE_REG_CYCLE_CL_E 7 | |
216 | #define PKE_REG_CYCLE_CL_B 0 | |
217 | ||
218 | /* ERR register */ | |
219 | #define PKE_REG_ERR_ME1_E 2 | |
220 | #define PKE_REG_ERR_ME1_B 2 | |
221 | #define PKE_REG_ERR_ME0_E 1 | |
222 | #define PKE_REG_ERR_ME0_B 1 | |
223 | #define PKE_REG_ERR_MII_E 0 | |
224 | #define PKE_REG_ERR_MII_B 0 | |
225 | ||
226 | ||
227 | /* source-addr for words written to VU/GPUIF ports */ | |
228 | #define PKE0_SRCADDR 0x20000020 /* from 1998-01-22 e-mail plans */ | |
229 | #define PKE1_SRCADDR 0x20000024 /* from 1998-01-22 e-mail plans */ | |
230 | ||
231 | ||
232 | /* UNPACK opcodes */ | |
233 | #define PKE_UNPACK(vn,vl) ((vn) << 2 | (vl)) | |
234 | #define PKE_UNPACK_S_32 PKE_UNPACK(0, 0) | |
235 | #define PKE_UNPACK_S_16 PKE_UNPACK(0, 1) | |
236 | #define PKE_UNPACK_S_8 PKE_UNPACK(0, 2) | |
237 | #define PKE_UNPACK_V2_32 PKE_UNPACK(1, 0) | |
238 | #define PKE_UNPACK_V2_16 PKE_UNPACK(1, 1) | |
239 | #define PKE_UNPACK_V2_8 PKE_UNPACK(1, 2) | |
240 | #define PKE_UNPACK_V3_32 PKE_UNPACK(2, 0) | |
241 | #define PKE_UNPACK_V3_16 PKE_UNPACK(2, 1) | |
242 | #define PKE_UNPACK_V3_8 PKE_UNPACK(2, 2) | |
243 | #define PKE_UNPACK_V4_32 PKE_UNPACK(3, 0) | |
244 | #define PKE_UNPACK_V4_16 PKE_UNPACK(3, 1) | |
245 | #define PKE_UNPACK_V4_8 PKE_UNPACK(3, 2) | |
246 | #define PKE_UNPACK_V4_5 PKE_UNPACK(3, 3) | |
247 | ||
248 | ||
249 | /* MASK register sub-field definitions */ | |
250 | #define PKE_MASKREG_INPUT 0 | |
251 | #define PKE_MASKREG_ROW 1 | |
252 | #define PKE_MASKREG_COLUMN 2 | |
253 | #define PKE_MASKREG_NOTHING 3 | |
254 | ||
255 | ||
256 | /* STMOD register field definitions */ | |
257 | #define PKE_MODE_INPUT 0 | |
258 | #define PKE_MODE_ADDROW 1 | |
259 | #define PKE_MODE_ACCROW 2 | |
260 | ||
261 | ||
262 | /* extract a MASK register sub-field for row [0..3] and column [0..3] */ | |
263 | /* MASK register is laid out of 2-bit values in this r-c order */ | |
264 | /* m33 m32 m31 m30 m23 m22 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00 */ | |
265 | #define PKE_MASKREG_GET(me,row,col) \ | |
266 | ((((me)->regs[PKE_REG_MASK][0]) >> (8*(row) + 2*(col))) & 0x03) | |
267 | ||
268 | ||
269 | /* and now a few definitions that rightfully belong elsewhere */ | |
270 | #ifdef PKE_DEBUG | |
271 | ||
272 | /* GPUIF addresses */ | |
273 | #define GPUIF_PATH3_FIFO_ADDR 0x10008020 /* data from CORE */ | |
274 | #define GPUIF_PATH1_FIFO_ADDR 0x10008030 /* data from VU1 */ | |
275 | #define GPUIF_PATH2_FIFO_ADDR 0x10008040 /* data from PKE1 */ | |
276 | ||
277 | /* VU STAT register */ | |
278 | #define VU_REG_STAT_VGW_E 4 | |
279 | #define VU_REG_STAT_VGW_B 4 | |
280 | #define VU_REG_STAT_VBS_E 0 | |
281 | #define VU_REG_STAT_VBS_B 0 | |
282 | ||
283 | /* VU PC pseudo-registers */ /* omitted from 1998-01-22 e-mail plans */ | |
284 | #define VU0_PC_START 0x20025000 | |
285 | #define VU1_PC_START 0x20026000 | |
286 | ||
287 | /* VU source-addr tracking tables */ /* changed from 1998-01-22 e-mail plans */ | |
288 | #define VU0_MEM0_SRCADDR_START 0x21000000 | |
289 | #define VU0_MEM1_SRCADDR_START 0x21004000 | |
290 | #define VU1_MEM0_SRCADDR_START 0x21008000 | |
291 | #define VU1_MEM1_SRCADDR_START 0x2100C000 | |
292 | ||
293 | #endif /* PKE_DEBUG */ | |
294 | ||
295 | ||
296 | /* operations */ | |
297 | /* unsigned 32-bit mask of given width */ | |
298 | #define BIT_MASK(width) ((((unsigned_4)1) << (width+1)) - 1) | |
299 | /* e.g.: BIT_MASK(5) = 00011111 */ | |
300 | ||
301 | /* mask between given given bits numbers (MSB) */ | |
302 | #define BIT_MASK_BTW(begin,end) (BIT_MASK(end) & ~BIT_MASK(begin)) | |
303 | /* e.g.: BIT_MASK_BTW(4,11) = 0000111111110000 */ | |
304 | ||
305 | /* set bitfield value */ | |
306 | #define BIT_MASK_SET(lvalue,begin,end,value) \ | |
307 | do { \ | |
308 | lvalue &= ~BIT_MASK_BTW(begin,end); \ | |
309 | lvalue |= (((value) << (begin)) & BIT_MASK_BTW(begin,end)); \ | |
310 | } while(0) | |
311 | ||
312 | /* get bitfield value */ | |
313 | #define BIT_MASK_GET(rvalue,begin,end) \ | |
314 | (((rvalue) & BIT_MASK_BTW(begin,end)) >> (begin)) | |
315 | /* e.g., BIT_MASK_GET(0000111100001111, 2, 8) = 0000000100001100 */ | |
316 | ||
317 | /* get bitfield value, sign-extended to given bit number */ | |
318 | #define BIT_MASK_GET_SX(rvalue,begin,end,sx) \ | |
319 | (BIT_MASK_GET(rvalue,begin,end) | ((BIT_MASK_GET(rvalue,begin,end) & BIT_MASK_BTW(end,end)) ? BIT_MASK_BTW(end,sx) : 0)) | |
320 | /* e.g., BIT_MASK_GET_SX(0000111100001111, 2, 8, 15) = 1111111100001100 */ | |
321 | ||
322 | ||
323 | /* These ugly macro hacks allow succinct bitfield accesses */ | |
324 | /* set a bitfield in a register by "name" */ | |
325 | #define PKE_REG_MASK_SET(me,reg,flag,value) \ | |
326 | BIT_MASK_SET(((me)->regs[PKE_REG_##reg][0]), \ | |
327 | PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E, \ | |
328 | (value)) | |
329 | ||
330 | /* get a bitfield from a register by "name" */ | |
331 | #define PKE_REG_MASK_GET(me,reg,flag) \ | |
332 | BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \ | |
333 | PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E) | |
334 | ||
335 | ||
336 | #define PKE_LIMIT(value,max) ((value) > (max) ? (max) : (value)) | |
337 | ||
338 | ||
aea481da DE |
339 | /* One row in the FIFO */ |
340 | struct fifo_quadword | |
341 | { | |
342 | /* 128 bits of data */ | |
343 | quadword data; | |
344 | /* source main memory address (or 0: unknown) */ | |
345 | address_word source_address; | |
fba9bfed FCE |
346 | /* DMA tag present in lower 64 bits */ |
347 | unsigned_4 dma_tag_present; | |
aea481da DE |
348 | }; |
349 | ||
350 | ||
351 | /* PKE internal state: FIFOs, registers, handle to VU friend */ | |
352 | struct pke_device | |
353 | { | |
354 | /* common device info */ | |
355 | device dev; | |
356 | ||
357 | /* identity: 0=PKE0, 1=PKE1 */ | |
358 | int pke_number; | |
359 | int flags; | |
360 | ||
aea481da DE |
361 | /* quadword registers */ |
362 | quadword regs[PKE_NUM_REGS]; | |
363 | ||
364 | /* FIFO */ | |
365 | struct fifo_quadword* fifo; | |
366 | int fifo_num_elements; /* no. of quadwords occupied in FIFO */ | |
367 | int fifo_buffer_size; /* no. of quadwords of space in FIFO */ | |
368 | FILE* fifo_trace_file; /* or 0 for no trace */ | |
fba9bfed | 369 | /* XXX: assumes FIFOs grow indefinately */ |
aea481da | 370 | |
fba9bfed FCE |
371 | /* PC */ |
372 | int fifo_pc; /* 0 .. (fifo_num_elements-1): quadword index of next instruction */ | |
373 | int qw_pc; /* 0 .. 3: word index of next instruction */ | |
aea481da DE |
374 | }; |
375 | ||
376 | ||
377 | /* Flags for PKE.flags */ | |
378 | ||
379 | #define PKE_FLAG_NONE 0 | |
380 | /* none at present */ | |
381 | ||
382 | ||
aea481da | 383 | #endif /* H_PKE_H */ |