Commit | Line | Data |
---|---|---|
e1b20d30 AC |
1 | // -*- C -*- |
2 | // | |
3 | // NEC specific instructions | |
4 | // | |
5 | ||
6 | // Integer Instructions | |
7 | // -------------------- | |
8 | // | |
9 | // MulAcc is the Multiply Accumulator. | |
10 | // This register is mapped on the the HI and LO registers. | |
11 | // Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register. | |
12 | // Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register. | |
13 | ||
14 | ||
15 | :function:::unsigned64:MulAcc: | |
aeeb756d KR |
16 | *vr4100: |
17 | // start-sanitize-vr4320 | |
18 | *vr4320: | |
19 | // end-sanitize-vr4320 | |
20 | // start-sanitize-cygnus | |
21 | *vr5400: | |
22 | // end-sanitize-cygnus | |
e1b20d30 AC |
23 | { |
24 | unsigned64 result = U8_4 (HI, LO); | |
25 | return result; | |
26 | } | |
27 | ||
28 | :function:::void:SET_MulAcc:unsigned64 value | |
aeeb756d KR |
29 | *vr4100: |
30 | // start-sanitize-vr4320 | |
31 | *vr4320: | |
32 | // end-sanitize-vr4320 | |
33 | // start-sanitize-cygnus | |
34 | *vr5400: | |
35 | // end-sanitize-cygnus | |
e1b20d30 | 36 | { |
aeeb756d | 37 | /* 64 bit specific */ |
e1b20d30 AC |
38 | *AL4_8 (&HI) = VH4_8 (value); |
39 | *AL4_8 (&LO) = VL4_8 (value); | |
40 | } | |
41 | ||
42 | :function:::signed64:SignedMultiply:signed32 l, signed32 r | |
aeeb756d KR |
43 | *vr4100: |
44 | // start-sanitize-vr4320 | |
45 | *vr4320: | |
46 | // end-sanitize-vr4320 | |
47 | // start-sanitize-cygnus | |
48 | *vr5400: | |
49 | // end-sanitize-cygnus | |
e1b20d30 AC |
50 | { |
51 | signed64 result = (signed64) l * (signed64) r; | |
52 | return result; | |
53 | } | |
54 | ||
55 | :function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r | |
aeeb756d KR |
56 | *vr4100: |
57 | // start-sanitize-vr4320 | |
58 | *vr4320: | |
59 | // end-sanitize-vr4320 | |
60 | // start-sanitize-cygnus | |
61 | *vr5400: | |
62 | // end-sanitize-cygnus | |
e1b20d30 AC |
63 | { |
64 | unsigned64 result = (unsigned64) l * (unsigned64) r; | |
65 | return result; | |
66 | } | |
67 | ||
68 | :function:::unsigned64:Low32Bits:unsigned64 value | |
aeeb756d KR |
69 | *vr4100: |
70 | // start-sanitize-vr4320 | |
71 | *vr4320: | |
72 | // end-sanitize-vr4320 | |
73 | // start-sanitize-cygnus | |
74 | *vr5400: | |
75 | // end-sanitize-cygnus | |
e1b20d30 AC |
76 | { |
77 | unsigned64 result = (signed64) (signed32) VL4_8 (value); | |
78 | return result; | |
79 | } | |
80 | ||
81 | :function:::unsigned64:High32Bits:unsigned64 value | |
aeeb756d KR |
82 | *vr4100: |
83 | // start-sanitize-vr4320 | |
84 | *vr4320: | |
85 | // end-sanitize-vr4320 | |
86 | // start-sanitize-cygnus | |
87 | *vr5400: | |
88 | // end-sanitize-cygnus | |
e1b20d30 AC |
89 | { |
90 | unsigned64 result = (signed64) (signed32) VH4_8 (value); | |
91 | return result; | |
92 | } | |
93 | ||
94 | ||
95 | ||
96 | // Multiply, Accumulate | |
97 | 000000,5.RS,5.RT,00000,00000,101000::::MAC | |
98 | "mac r<RS>, r<RT>" | |
99 | *vr4100: | |
100 | // start-sanitize-vr4320 | |
101 | *vr4320: | |
102 | // end-sanitize-vr4320 | |
103 | { | |
104 | SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
105 | } | |
106 | ||
107 | ||
108 | // D-Multiply, Accumulate | |
109 | 000000,5.RS,5.RT,00000,00000,101001::::DMAC | |
110 | "dmac r<RS>, r<RT>" | |
111 | *vr4100: | |
112 | // start-sanitize-vr4320 | |
113 | *vr4320: | |
114 | // end-sanitize-vr4320 | |
115 | { | |
116 | LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]); | |
117 | } | |
118 | ||
119 | ||
120 | // start-sanitize-vr4320 | |
121 | // Count Leading Zeros | |
122 | 000000,5.RS,00000,5.RD,00000,110101::::CLZ | |
123 | "clz r<RD>, r<RS>" | |
124 | // end-sanitize-vr4320 | |
125 | // start-sanitize-vr4320 | |
126 | *vr4320: | |
127 | // end-sanitize-vr4320 | |
128 | // start-sanitize-vr4320 | |
129 | { | |
130 | unsigned32 t = Low32Bits (SD_, GPR[RS]); | |
131 | signed64 c = 0; | |
132 | ||
133 | while (! (t & ( 1 << 31)) | |
134 | && c < 32) | |
135 | { | |
136 | c++; | |
137 | t <<= 1; | |
138 | } | |
139 | ||
140 | GPR[RD] = c; | |
141 | } | |
142 | ||
143 | ||
144 | // end-sanitize-vr4320 | |
145 | // start-sanitize-vr4320 | |
146 | // D-Count Leading Zeros | |
147 | 000000,5.RS,00000,5.RD,00000,111101::::DCLZ | |
148 | "dclz r<RD>, r<RS>" | |
149 | // end-sanitize-vr4320 | |
150 | // start-sanitize-vr4320 | |
151 | *vr4320: | |
152 | // end-sanitize-vr4320 | |
153 | // start-sanitize-vr4320 | |
154 | { | |
155 | unsigned64 t = GPR[RS]; | |
156 | signed64 c = 0; | |
157 | ||
158 | while (! (t & ( (unsigned64)1 << 63)) | |
159 | && c < 64) | |
160 | { | |
161 | c++; | |
162 | t <<= 1; | |
163 | } | |
164 | ||
165 | printf("lo %d\n", (int) c); | |
166 | GPR[RD] = c; | |
167 | } | |
168 | ||
169 | ||
170 | ||
171 | ||
172 | ||
173 | ||
174 | ||
175 | // end-sanitize-vr4320 | |
176 | // start-sanitize-vrXXXX | |
177 | // Multiply and Move LO. | |
178 | 000000,5.RS,5.RT,5.RD,00100,101000::::MUL | |
179 | "mul r<RD>, r<RS>, r<RT>" | |
180 | // end-sanitize-vrXXXX | |
181 | // start-sanitize-vr4320 | |
182 | *vr4320: | |
183 | // end-sanitize-vr4320 | |
aeeb756d | 184 | // start-sanitize-cygnus |
e1b20d30 | 185 | *vr5400: |
aeeb756d | 186 | // end-sanitize-cygnus |
e1b20d30 AC |
187 | // start-sanitize-vrXXXX |
188 | { | |
189 | SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
190 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
191 | } | |
192 | ||
193 | ||
194 | // end-sanitize-vrXXXX | |
195 | // start-sanitize-vrXXXX | |
196 | // Unsigned Multiply and Move LO. | |
197 | 000000,5.RS,5.RT,5.RD,00101,101000::::MULU | |
198 | "mulu r<RD>, r<RS>, r<RT>" | |
199 | // end-sanitize-vrXXXX | |
200 | // start-sanitize-vr4320 | |
201 | *vr4320: | |
202 | // end-sanitize-vr4320 | |
aeeb756d | 203 | // start-sanitize-cygnus |
e1b20d30 | 204 | *vr5400: |
aeeb756d | 205 | // end-sanitize-cygnus |
e1b20d30 AC |
206 | // start-sanitize-vrXXXX |
207 | { | |
208 | SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
209 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
210 | } | |
211 | ||
212 | ||
213 | // end-sanitize-vrXXXX | |
214 | // start-sanitize-vrXXXX | |
215 | // Multiply and Move HI. | |
216 | 000000,5.RS,5.RT,5.RD,01100,101000::::MULHI | |
217 | "mulhi r<RD>, r<RS>, r<RT>" | |
218 | // end-sanitize-vrXXXX | |
219 | // start-sanitize-vr4320 | |
220 | *vr4320: | |
221 | // end-sanitize-vr4320 | |
aeeb756d | 222 | // start-sanitize-cygnus |
e1b20d30 | 223 | *vr5400: |
aeeb756d | 224 | // end-sanitize-cygnus |
e1b20d30 AC |
225 | // start-sanitize-vrXXXX |
226 | { | |
227 | SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
228 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
229 | } | |
230 | ||
231 | ||
232 | // end-sanitize-vrXXXX | |
233 | // start-sanitize-vrXXXX | |
234 | // Unsigned Multiply and Move HI. | |
235 | 000000,5.RS,5.RT,5.RD,01101,101000::::MULHIU | |
236 | "mulhiu r<RD>, r<RS>, r<RT>" | |
237 | // end-sanitize-vrXXXX | |
238 | // start-sanitize-vr4320 | |
239 | *vr4320: | |
240 | // end-sanitize-vr4320 | |
aeeb756d | 241 | // start-sanitize-cygnus |
e1b20d30 | 242 | *vr5400: |
aeeb756d | 243 | // end-sanitize-cygnus |
e1b20d30 AC |
244 | // start-sanitize-vrXXXX |
245 | { | |
246 | SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
247 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
248 | } | |
249 | ||
250 | ||
251 | // end-sanitize-vrXXXX | |
aeeb756d | 252 | // start-sanitize-cygnus |
e1b20d30 AC |
253 | // Multiply, Negate and Move LO. |
254 | 000000,5.RS,5.RT,5.RD,00011,011000::::MULS | |
255 | "muls r<RD>, r<RS>, r<RT>" | |
aeeb756d KR |
256 | // end-sanitize-cygnus |
257 | // start-sanitize-cygnus | |
e1b20d30 | 258 | *vr5400: |
aeeb756d KR |
259 | // end-sanitize-cygnus |
260 | // start-sanitize-cygnus | |
e1b20d30 AC |
261 | { |
262 | SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
263 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
264 | } | |
265 | ||
266 | ||
aeeb756d KR |
267 | // end-sanitize-cygnus |
268 | // start-sanitize-cygnus | |
e1b20d30 AC |
269 | // Unsigned Multiply, Negate and Move LO. |
270 | 000000,5.RS,5.RT,5.RD,00011,011001::::MULSU | |
271 | "mulsu r<RD>, r<RS>, r<RT>" | |
aeeb756d KR |
272 | // end-sanitize-cygnus |
273 | // start-sanitize-cygnus | |
e1b20d30 | 274 | *vr5400: |
aeeb756d KR |
275 | // end-sanitize-cygnus |
276 | // start-sanitize-cygnus | |
e1b20d30 AC |
277 | { |
278 | SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
279 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
280 | } | |
281 | ||
282 | ||
aeeb756d KR |
283 | // end-sanitize-cygnus |
284 | // start-sanitize-cygnus | |
e1b20d30 AC |
285 | // Multiply, Negate and Move HI. |
286 | 000000,5.RS,5.RT,5.RD,01011,011000::::MULSHI | |
287 | "mulshi r<RD>, r<RS>, r<RT>" | |
aeeb756d KR |
288 | // end-sanitize-cygnus |
289 | // start-sanitize-cygnus | |
e1b20d30 | 290 | *vr5400: |
aeeb756d KR |
291 | // end-sanitize-cygnus |
292 | // start-sanitize-cygnus | |
e1b20d30 AC |
293 | { |
294 | SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
295 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
296 | } | |
297 | ||
298 | ||
aeeb756d KR |
299 | // end-sanitize-cygnus |
300 | // start-sanitize-cygnus | |
e1b20d30 AC |
301 | // Unsigned Multiply, Negate and Move HI. |
302 | 000000,5.RS,5.RT,5.RD,01011,011001::::MULSHIU | |
303 | "mulshiu r<RD>, r<RS>, r<RT>" | |
aeeb756d KR |
304 | // end-sanitize-cygnus |
305 | // start-sanitize-cygnus | |
e1b20d30 | 306 | *vr5400: |
aeeb756d KR |
307 | // end-sanitize-cygnus |
308 | // start-sanitize-cygnus | |
e1b20d30 AC |
309 | { |
310 | SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
311 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
312 | } | |
313 | ||
314 | ||
315 | ||
316 | ||
317 | ||
aeeb756d | 318 | // end-sanitize-cygnus |
e1b20d30 AC |
319 | // Multiply, Accumulate and Move LO. |
320 | 000000,5.RS,5.RT,5.RD,00010,101000::::MACC | |
321 | "macc r<RD>, r<RS>, r<RT>" | |
322 | // start-sanitize-vr4320 | |
323 | *vr4320: | |
324 | // end-sanitize-vr4320 | |
aeeb756d | 325 | // start-sanitize-cygnus |
e1b20d30 | 326 | *vr5400: |
aeeb756d | 327 | // end-sanitize-cygnus |
e1b20d30 AC |
328 | { |
329 | SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
330 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
331 | } | |
332 | ||
333 | ||
e1b20d30 AC |
334 | // start-sanitize-vrXXXX |
335 | // Unsigned Multiply, Accumulate and Move LO. | |
336 | 000000,5.RS,5.RT,5.RD,00011,101000::::MACCU | |
337 | "maccu r<RD>, r<RS>, r<RT>" | |
338 | // end-sanitize-vrXXXX | |
339 | // start-sanitize-vr4320 | |
340 | *vr4320: | |
341 | // end-sanitize-vr4320 | |
aeeb756d | 342 | // start-sanitize-cygnus |
e1b20d30 | 343 | *vr5400: |
aeeb756d | 344 | // end-sanitize-cygnus |
e1b20d30 AC |
345 | // start-sanitize-vrXXXX |
346 | { | |
347 | SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
348 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
349 | } | |
350 | ||
351 | ||
352 | // end-sanitize-vrXXXX | |
353 | // start-sanitize-vrXXXX | |
354 | // Multiply, Accumulate and Move HI. | |
355 | 000000,5.RS,5.RT,5.RD,01010,101000::::MACCHI | |
356 | "macchi r<RD>, r<RS>, r<RT>" | |
357 | // end-sanitize-vrXXXX | |
358 | // start-sanitize-vr4320 | |
359 | *vr4320: | |
360 | // end-sanitize-vr4320 | |
aeeb756d | 361 | // start-sanitize-cygnus |
e1b20d30 | 362 | *vr5400: |
aeeb756d | 363 | // end-sanitize-cygnus |
e1b20d30 AC |
364 | // start-sanitize-vrXXXX |
365 | { | |
366 | SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
367 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
368 | } | |
369 | ||
370 | ||
371 | // end-sanitize-vrXXXX | |
372 | // start-sanitize-vrXXXX | |
373 | // Unsigned Multiply, Accumulate and Move HI. | |
374 | 000000,5.RS,5.RT,5.RD,01011,101000::::MACCHIU | |
375 | "macchiu r<RD>, r<RS>, r<RT>" | |
acf38b4e | 376 | // end-sanitize-vrXXXX |
e1b20d30 AC |
377 | // start-sanitize-vr4320 |
378 | *vr4320: | |
379 | // end-sanitize-vr4320 | |
aeeb756d | 380 | // start-sanitize-cygnus |
e1b20d30 | 381 | *vr5400: |
aeeb756d | 382 | // end-sanitize-cygnus |
60f9cd07 | 383 | // start-sanitize-vrXXXX |
e1b20d30 AC |
384 | { |
385 | SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
386 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
387 | ||
388 | } | |
389 | ||
390 | ||
391 | ||
392 | // end-sanitize-vrXXXX | |
aeeb756d | 393 | // start-sanitize-cygnus |
e1b20d30 AC |
394 | // Multiply, Negate, Accumulate and Move LO. |
395 | 000000,5.RS,5.RT,5.RD,00111,011000::::MSAC | |
396 | "msac r<RD>, r<RS>, r<RT>" | |
aeeb756d KR |
397 | // end-sanitize-cygnus |
398 | // start-sanitize-cygnus | |
e1b20d30 | 399 | *vr5400: |
aeeb756d KR |
400 | // end-sanitize-cygnus |
401 | // start-sanitize-cygnus | |
e1b20d30 AC |
402 | { |
403 | SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
404 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
405 | } | |
406 | ||
407 | ||
aeeb756d KR |
408 | // end-sanitize-cygnus |
409 | // start-sanitize-cygnus | |
e1b20d30 AC |
410 | // Unsigned Multiply, Negate, Accumulate and Move LO. |
411 | 000000,5.RS,5.RT,5.RD,00111,011001::::MSACU | |
412 | "msacu r<RD>, r<RS>, r<RT>" | |
aeeb756d KR |
413 | // end-sanitize-cygnus |
414 | // start-sanitize-cygnus | |
e1b20d30 | 415 | *vr5400: |
aeeb756d KR |
416 | // end-sanitize-cygnus |
417 | // start-sanitize-cygnus | |
e1b20d30 AC |
418 | { |
419 | SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
420 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
421 | } | |
422 | ||
423 | ||
aeeb756d KR |
424 | // end-sanitize-cygnus |
425 | // start-sanitize-cygnus | |
e1b20d30 AC |
426 | // Multiply, Negate, Accumulate and Move HI. |
427 | 000000,5.RS,5.RT,5.RD,01111,011000::::MSACHI | |
428 | "msachi r<RD>, r<RS>, r<RT>" | |
aeeb756d KR |
429 | // end-sanitize-cygnus |
430 | // start-sanitize-cygnus | |
e1b20d30 | 431 | *vr5400: |
aeeb756d KR |
432 | // end-sanitize-cygnus |
433 | // start-sanitize-cygnus | |
e1b20d30 AC |
434 | { |
435 | SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
436 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
437 | } | |
438 | ||
aeeb756d KR |
439 | // end-sanitize-cygnus |
440 | // start-sanitize-cygnus | |
e1b20d30 AC |
441 | // Unsigned Multiply, Negate, Accumulate and Move HI. |
442 | 000000,5.RS,5.RT,5.RD,01111,011001::::MSACHIU | |
443 | "msachiu r<RD>, r<RS>, r<RT>" | |
aeeb756d KR |
444 | // end-sanitize-cygnus |
445 | // start-sanitize-cygnus | |
e1b20d30 | 446 | *vr5400: |
aeeb756d KR |
447 | // end-sanitize-cygnus |
448 | // start-sanitize-cygnus | |
e1b20d30 AC |
449 | { |
450 | SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
451 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
452 | } | |
453 | ||
454 | ||
aeeb756d KR |
455 | // end-sanitize-cygnus |
456 | // start-sanitize-cygnus | |
e1b20d30 AC |
457 | // Rotate Right. |
458 | 000000,00001,5.RT,5.RD,5.SHIFT,000010::::ROR | |
459 | "ror r<RD>, r<RT>, <SHIFT>" | |
aeeb756d KR |
460 | // end-sanitize-cygnus |
461 | // start-sanitize-cygnus | |
e1b20d30 | 462 | *vr5400: |
aeeb756d KR |
463 | // end-sanitize-cygnus |
464 | // start-sanitize-cygnus | |
e1b20d30 AC |
465 | { |
466 | int s = SHIFT; | |
467 | GPR[RD] = ROTR32 (GPR[RT], s); | |
468 | } | |
469 | ||
470 | ||
aeeb756d KR |
471 | // end-sanitize-cygnus |
472 | // start-sanitize-cygnus | |
e1b20d30 AC |
473 | // Rotate Right Variable. |
474 | 000000,5.RS,5.RT,5.RD,00001,000110::::RORV | |
475 | "rorv r<RD>, r<RT>, <RS>" | |
aeeb756d KR |
476 | // end-sanitize-cygnus |
477 | // start-sanitize-cygnus | |
e1b20d30 | 478 | *vr5400: |
aeeb756d KR |
479 | // end-sanitize-cygnus |
480 | // start-sanitize-cygnus | |
e1b20d30 AC |
481 | { |
482 | int s = MASKED (GPR[RS], 4, 0); | |
483 | GPR[RD] = ROTR32 (GPR[RT], s); | |
484 | } | |
485 | ||
486 | ||
aeeb756d KR |
487 | // end-sanitize-cygnus |
488 | // start-sanitize-cygnus | |
e1b20d30 AC |
489 | // Double Rotate Right. |
490 | 000000,00001,5.RT,5.RD,5.SHIFT,111010::::DROR | |
491 | "dror r<RD>, r<RT>, <SHIFT>" | |
aeeb756d KR |
492 | // end-sanitize-cygnus |
493 | // start-sanitize-cygnus | |
e1b20d30 | 494 | *vr5400: |
aeeb756d KR |
495 | // end-sanitize-cygnus |
496 | // start-sanitize-cygnus | |
e1b20d30 AC |
497 | { |
498 | int s = SHIFT; | |
499 | GPR[RD] = ROTR64 (GPR[RT], s); | |
500 | } | |
501 | ||
502 | ||
aeeb756d KR |
503 | // end-sanitize-cygnus |
504 | // start-sanitize-cygnus | |
e1b20d30 AC |
505 | // Double Rotate Right Plus 32. |
506 | 000000,00001,5.RT,5.RD,5.SHIFT,111110::::DROR32 | |
507 | "dror32 r<RD>, r<RT>, <SHIFT>" | |
aeeb756d KR |
508 | // end-sanitize-cygnus |
509 | // start-sanitize-cygnus | |
e1b20d30 | 510 | *vr5400: |
aeeb756d KR |
511 | // end-sanitize-cygnus |
512 | // start-sanitize-cygnus | |
e1b20d30 AC |
513 | { |
514 | int s = SHIFT + 32; | |
515 | GPR[RD] = ROTR64 (GPR[RT], s); | |
516 | } | |
517 | ||
518 | ||
aeeb756d KR |
519 | // end-sanitize-cygnus |
520 | // start-sanitize-cygnus | |
e1b20d30 AC |
521 | // Double Rotate Right Variable. |
522 | 000000,5.RS,5.RT,5.RD,00001,010110::::DRORV | |
523 | "drorv r<RD>, r<RT>, <RS>" | |
aeeb756d KR |
524 | // end-sanitize-cygnus |
525 | // start-sanitize-cygnus | |
e1b20d30 | 526 | *vr5400: |
aeeb756d KR |
527 | // end-sanitize-cygnus |
528 | // start-sanitize-cygnus | |
e1b20d30 AC |
529 | { |
530 | int s = MASKED (GPR[RS], 5, 0); | |
531 | GPR[RD] = ROTR64 (GPR[RT], s); | |
532 | } | |
533 | ||
534 | ||
aeeb756d | 535 | // end-sanitize-cygnus |