Commit | Line | Data |
---|---|---|
e1b20d30 AC |
1 | // -*- C -*- |
2 | // | |
3 | // NEC specific instructions | |
4 | // | |
5 | ||
6 | // Integer Instructions | |
7 | // -------------------- | |
8 | // | |
9 | // MulAcc is the Multiply Accumulator. | |
10 | // This register is mapped on the the HI and LO registers. | |
11 | // Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register. | |
12 | // Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register. | |
13 | ||
14 | ||
15 | :function:::unsigned64:MulAcc: | |
aeeb756d | 16 | *vr4100: |
f14397f0 GRK |
17 | // start-sanitize-vr4xxx |
18 | *vr4121: | |
19 | // end-sanitize-vr4xxx | |
aeeb756d KR |
20 | // start-sanitize-vr4320 |
21 | *vr4320: | |
22 | // end-sanitize-vr4320 | |
23 | // start-sanitize-cygnus | |
24 | *vr5400: | |
25 | // end-sanitize-cygnus | |
e1b20d30 AC |
26 | { |
27 | unsigned64 result = U8_4 (HI, LO); | |
28 | return result; | |
29 | } | |
30 | ||
31 | :function:::void:SET_MulAcc:unsigned64 value | |
aeeb756d | 32 | *vr4100: |
f14397f0 GRK |
33 | // start-sanitize-vr4xxx |
34 | *vr4121: | |
35 | // end-sanitize-vr4xxx | |
aeeb756d KR |
36 | // start-sanitize-vr4320 |
37 | *vr4320: | |
38 | // end-sanitize-vr4320 | |
39 | // start-sanitize-cygnus | |
40 | *vr5400: | |
41 | // end-sanitize-cygnus | |
e1b20d30 | 42 | { |
aeeb756d | 43 | /* 64 bit specific */ |
e1b20d30 AC |
44 | *AL4_8 (&HI) = VH4_8 (value); |
45 | *AL4_8 (&LO) = VL4_8 (value); | |
46 | } | |
47 | ||
48 | :function:::signed64:SignedMultiply:signed32 l, signed32 r | |
aeeb756d | 49 | *vr4100: |
f14397f0 GRK |
50 | // start-sanitize-vr4xxx |
51 | *vr4121: | |
52 | // end-sanitize-vr4xxx | |
aeeb756d KR |
53 | // start-sanitize-vr4320 |
54 | *vr4320: | |
55 | // end-sanitize-vr4320 | |
56 | // start-sanitize-cygnus | |
57 | *vr5400: | |
58 | // end-sanitize-cygnus | |
e1b20d30 AC |
59 | { |
60 | signed64 result = (signed64) l * (signed64) r; | |
61 | return result; | |
62 | } | |
63 | ||
64 | :function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r | |
aeeb756d | 65 | *vr4100: |
f14397f0 GRK |
66 | // start-sanitize-vr4xxx |
67 | *vr4121: | |
68 | // end-sanitize-vr4xxx | |
aeeb756d KR |
69 | // start-sanitize-vr4320 |
70 | *vr4320: | |
71 | // end-sanitize-vr4320 | |
72 | // start-sanitize-cygnus | |
73 | *vr5400: | |
74 | // end-sanitize-cygnus | |
e1b20d30 AC |
75 | { |
76 | unsigned64 result = (unsigned64) l * (unsigned64) r; | |
77 | return result; | |
78 | } | |
79 | ||
f14397f0 GRK |
80 | // start-sanitize-vr4xxx |
81 | :function:::signed64:SaturatedAdd:signed32 l, signed32 r | |
82 | *vr4121: | |
83 | { | |
84 | signed64 result = (signed64) l + (signed64) r; | |
85 | if (result < 0) | |
86 | result = 0xFFFFFFFF8000000LL; | |
87 | else if (result > 0x000000007FFFFFFFLL) | |
88 | result = 0x000000007FFFFFFFLL; | |
89 | return result; | |
90 | } | |
91 | ||
92 | :function:::unsigned64:SaturatedUnsignedAdd:unsigned32 l, unsigned32 r | |
93 | *vr4121: | |
94 | { | |
95 | unsigned64 result = (unsigned64) l + (unsigned64) r; | |
96 | if (result > 0x000000007FFFFFFFLL) | |
97 | result = 0xFFFFFFFFFFFFFFFFLL; | |
98 | return result; | |
99 | } | |
100 | ||
101 | ||
102 | // end-sanitize-vr4xxx | |
e1b20d30 | 103 | :function:::unsigned64:Low32Bits:unsigned64 value |
aeeb756d | 104 | *vr4100: |
f14397f0 GRK |
105 | // start-sanitize-vr4xxx |
106 | *vr4121: | |
107 | // end-sanitize-vr4xxx | |
7d2ec607 GRK |
108 | // start-sanitize-vr4320 |
109 | *vr4320: | |
110 | // end-sanitize-vr4320 | |
aeeb756d KR |
111 | // start-sanitize-cygnus |
112 | *vr5400: | |
113 | // end-sanitize-cygnus | |
e1b20d30 AC |
114 | { |
115 | unsigned64 result = (signed64) (signed32) VL4_8 (value); | |
116 | return result; | |
117 | } | |
118 | ||
119 | :function:::unsigned64:High32Bits:unsigned64 value | |
aeeb756d | 120 | *vr4100: |
f14397f0 GRK |
121 | // start-sanitize-vr4xxx |
122 | *vr4121: | |
123 | // end-sanitize-vr4xxx | |
aeeb756d KR |
124 | // start-sanitize-vr4320 |
125 | *vr4320: | |
126 | // end-sanitize-vr4320 | |
127 | // start-sanitize-cygnus | |
128 | *vr5400: | |
129 | // end-sanitize-cygnus | |
e1b20d30 AC |
130 | { |
131 | unsigned64 result = (signed64) (signed32) VH4_8 (value); | |
132 | return result; | |
133 | } | |
134 | ||
135 | ||
136 | ||
137 | // Multiply, Accumulate | |
f14397f0 | 138 | 000000,5.RS,5.RT,00000,00000,101000::64::MAC |
e1b20d30 AC |
139 | "mac r<RS>, r<RT>" |
140 | *vr4100: | |
141 | // start-sanitize-vr4320 | |
142 | *vr4320: | |
143 | // end-sanitize-vr4320 | |
144 | { | |
145 | SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
146 | } | |
147 | ||
148 | ||
149 | // D-Multiply, Accumulate | |
f14397f0 | 150 | 000000,5.RS,5.RT,00000,00000,101001::64::DMAC |
e1b20d30 AC |
151 | "dmac r<RS>, r<RT>" |
152 | *vr4100: | |
153 | // start-sanitize-vr4320 | |
154 | *vr4320: | |
155 | // end-sanitize-vr4320 | |
156 | { | |
157 | LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]); | |
158 | } | |
159 | ||
160 | ||
161 | // start-sanitize-vr4320 | |
162 | // Count Leading Zeros | |
f14397f0 | 163 | 000000,5.RS,00000,5.RD,00000,110101::64::CLZ |
e1b20d30 AC |
164 | "clz r<RD>, r<RS>" |
165 | // end-sanitize-vr4320 | |
166 | // start-sanitize-vr4320 | |
167 | *vr4320: | |
168 | // end-sanitize-vr4320 | |
169 | // start-sanitize-vr4320 | |
170 | { | |
171 | unsigned32 t = Low32Bits (SD_, GPR[RS]); | |
172 | signed64 c = 0; | |
173 | ||
174 | while (! (t & ( 1 << 31)) | |
175 | && c < 32) | |
176 | { | |
177 | c++; | |
178 | t <<= 1; | |
179 | } | |
180 | ||
181 | GPR[RD] = c; | |
182 | } | |
183 | ||
184 | ||
185 | // end-sanitize-vr4320 | |
186 | // start-sanitize-vr4320 | |
187 | // D-Count Leading Zeros | |
f14397f0 | 188 | 000000,5.RS,00000,5.RD,00000,111101::64::DCLZ |
e1b20d30 AC |
189 | "dclz r<RD>, r<RS>" |
190 | // end-sanitize-vr4320 | |
191 | // start-sanitize-vr4320 | |
192 | *vr4320: | |
193 | // end-sanitize-vr4320 | |
194 | // start-sanitize-vr4320 | |
195 | { | |
196 | unsigned64 t = GPR[RS]; | |
197 | signed64 c = 0; | |
198 | ||
199 | while (! (t & ( (unsigned64)1 << 63)) | |
200 | && c < 64) | |
201 | { | |
202 | c++; | |
203 | t <<= 1; | |
204 | } | |
205 | ||
206 | printf("lo %d\n", (int) c); | |
207 | GPR[RD] = c; | |
208 | } | |
209 | ||
210 | ||
211 | ||
212 | ||
213 | ||
214 | ||
215 | ||
216 | // end-sanitize-vr4320 | |
f14397f0 | 217 | // start-sanitize-cygnus |
e1b20d30 | 218 | // Multiply and Move LO. |
f14397f0 | 219 | 000000,5.RS,5.RT,5.RD,00100,101000::64::MUL |
e1b20d30 | 220 | "mul r<RD>, r<RS>, r<RT>" |
f14397f0 | 221 | // end-sanitize-cygnus |
e1b20d30 AC |
222 | // start-sanitize-vr4320 |
223 | *vr4320: | |
224 | // end-sanitize-vr4320 | |
aeeb756d | 225 | // start-sanitize-cygnus |
e1b20d30 | 226 | *vr5400: |
aeeb756d | 227 | // end-sanitize-cygnus |
f14397f0 | 228 | // start-sanitize-cygnus |
e1b20d30 AC |
229 | { |
230 | SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
231 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
232 | } | |
233 | ||
234 | ||
f14397f0 GRK |
235 | // end-sanitize-cygnus |
236 | // start-sanitize-cygnus | |
e1b20d30 | 237 | // Unsigned Multiply and Move LO. |
f14397f0 | 238 | 000000,5.RS,5.RT,5.RD,00101,101000::64::MULU |
e1b20d30 | 239 | "mulu r<RD>, r<RS>, r<RT>" |
f14397f0 | 240 | // end-sanitize-cygnus |
e1b20d30 AC |
241 | // start-sanitize-vr4320 |
242 | *vr4320: | |
243 | // end-sanitize-vr4320 | |
aeeb756d | 244 | // start-sanitize-cygnus |
e1b20d30 | 245 | *vr5400: |
aeeb756d | 246 | // end-sanitize-cygnus |
f14397f0 | 247 | // start-sanitize-cygnus |
e1b20d30 AC |
248 | { |
249 | SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
250 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
251 | } | |
252 | ||
253 | ||
f14397f0 GRK |
254 | // end-sanitize-cygnus |
255 | // start-sanitize-cygnus | |
e1b20d30 | 256 | // Multiply and Move HI. |
f14397f0 | 257 | 000000,5.RS,5.RT,5.RD,01100,101000::64::MULHI |
e1b20d30 | 258 | "mulhi r<RD>, r<RS>, r<RT>" |
f14397f0 | 259 | // end-sanitize-cygnus |
e1b20d30 AC |
260 | // start-sanitize-vr4320 |
261 | *vr4320: | |
262 | // end-sanitize-vr4320 | |
aeeb756d | 263 | // start-sanitize-cygnus |
e1b20d30 | 264 | *vr5400: |
aeeb756d | 265 | // end-sanitize-cygnus |
f14397f0 | 266 | // start-sanitize-cygnus |
e1b20d30 AC |
267 | { |
268 | SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
269 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
270 | } | |
271 | ||
272 | ||
f14397f0 GRK |
273 | // end-sanitize-cygnus |
274 | // start-sanitize-cygnus | |
e1b20d30 | 275 | // Unsigned Multiply and Move HI. |
f14397f0 | 276 | 000000,5.RS,5.RT,5.RD,01101,101000::64::MULHIU |
e1b20d30 | 277 | "mulhiu r<RD>, r<RS>, r<RT>" |
f14397f0 | 278 | // end-sanitize-cygnus |
e1b20d30 AC |
279 | // start-sanitize-vr4320 |
280 | *vr4320: | |
281 | // end-sanitize-vr4320 | |
aeeb756d | 282 | // start-sanitize-cygnus |
e1b20d30 | 283 | *vr5400: |
aeeb756d | 284 | // end-sanitize-cygnus |
f14397f0 | 285 | // start-sanitize-cygnus |
e1b20d30 AC |
286 | { |
287 | SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
288 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
289 | } | |
290 | ||
291 | ||
f14397f0 | 292 | // end-sanitize-cygnus |
aeeb756d | 293 | // start-sanitize-cygnus |
e1b20d30 | 294 | // Multiply, Negate and Move LO. |
f14397f0 | 295 | 000000,5.RS,5.RT,5.RD,00011,011000::64::MULS |
e1b20d30 | 296 | "muls r<RD>, r<RS>, r<RT>" |
aeeb756d KR |
297 | // end-sanitize-cygnus |
298 | // start-sanitize-cygnus | |
e1b20d30 | 299 | *vr5400: |
aeeb756d KR |
300 | // end-sanitize-cygnus |
301 | // start-sanitize-cygnus | |
e1b20d30 AC |
302 | { |
303 | SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
304 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
305 | } | |
306 | ||
307 | ||
aeeb756d KR |
308 | // end-sanitize-cygnus |
309 | // start-sanitize-cygnus | |
e1b20d30 | 310 | // Unsigned Multiply, Negate and Move LO. |
f14397f0 | 311 | 000000,5.RS,5.RT,5.RD,00011,011001::64::MULSU |
e1b20d30 | 312 | "mulsu r<RD>, r<RS>, r<RT>" |
aeeb756d KR |
313 | // end-sanitize-cygnus |
314 | // start-sanitize-cygnus | |
e1b20d30 | 315 | *vr5400: |
aeeb756d KR |
316 | // end-sanitize-cygnus |
317 | // start-sanitize-cygnus | |
e1b20d30 AC |
318 | { |
319 | SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
320 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
321 | } | |
322 | ||
323 | ||
aeeb756d KR |
324 | // end-sanitize-cygnus |
325 | // start-sanitize-cygnus | |
e1b20d30 | 326 | // Multiply, Negate and Move HI. |
f14397f0 | 327 | 000000,5.RS,5.RT,5.RD,01011,011000::64::MULSHI |
e1b20d30 | 328 | "mulshi r<RD>, r<RS>, r<RT>" |
aeeb756d KR |
329 | // end-sanitize-cygnus |
330 | // start-sanitize-cygnus | |
e1b20d30 | 331 | *vr5400: |
aeeb756d KR |
332 | // end-sanitize-cygnus |
333 | // start-sanitize-cygnus | |
e1b20d30 AC |
334 | { |
335 | SET_MulAcc (SD_, 0 - SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
336 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
337 | } | |
338 | ||
339 | ||
aeeb756d KR |
340 | // end-sanitize-cygnus |
341 | // start-sanitize-cygnus | |
e1b20d30 | 342 | // Unsigned Multiply, Negate and Move HI. |
f14397f0 | 343 | 000000,5.RS,5.RT,5.RD,01011,011001::64::MULSHIU |
e1b20d30 | 344 | "mulshiu r<RD>, r<RS>, r<RT>" |
aeeb756d KR |
345 | // end-sanitize-cygnus |
346 | // start-sanitize-cygnus | |
e1b20d30 | 347 | *vr5400: |
aeeb756d KR |
348 | // end-sanitize-cygnus |
349 | // start-sanitize-cygnus | |
e1b20d30 AC |
350 | { |
351 | SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
352 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
353 | } | |
354 | ||
355 | ||
aeeb756d | 356 | // end-sanitize-cygnus |
f14397f0 GRK |
357 | // start-sanitize-cygnus |
358 | // | |
e1b20d30 | 359 | // Multiply, Accumulate and Move LO. |
f14397f0 GRK |
360 | // |
361 | 000000,5.RS,5.RT,5.RD,00010,101000::64::MACC | |
e1b20d30 | 362 | "macc r<RD>, r<RS>, r<RT>" |
f14397f0 | 363 | // end-sanitize-cygnus |
e1b20d30 AC |
364 | // start-sanitize-vr4320 |
365 | *vr4320: | |
366 | // end-sanitize-vr4320 | |
aeeb756d | 367 | // start-sanitize-cygnus |
e1b20d30 | 368 | *vr5400: |
aeeb756d | 369 | // end-sanitize-cygnus |
f14397f0 | 370 | // start-sanitize-cygnus |
e1b20d30 AC |
371 | { |
372 | SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
373 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
374 | } | |
f14397f0 GRK |
375 | // end-sanitize-cygnus |
376 | ||
377 | // start-sanitize-vr4xxx | |
378 | 000000,5.RS,5.RT,5.RD,00000,101000::::MACC | |
379 | "macc r<RD>, r<RS>, r<RT>" | |
380 | *vr4121: | |
381 | { | |
382 | SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
383 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
384 | } | |
385 | ||
386 | 000000,5.RS,5.RT,5.RD,00000,101001::::DMACC | |
387 | "dmacc r<RD>, r<RS>, r<RT>" | |
388 | *vr4121: | |
389 | { | |
390 | LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]); | |
391 | GPR[RD] = LO; | |
392 | } | |
393 | ||
394 | 000000,5.RS,5.RT,5.RD,10000,101000::::MACCS | |
395 | "maccs r<RD>, r<RS>, r<RT>" | |
396 | *vr4121: | |
397 | { | |
398 | SET_MulAcc (SD_, SaturatedAdd (SD_, MulAcc (SD_), | |
399 | SignedMultiply (SD_, GPR[RS], GPR[RT]))); | |
400 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
401 | } | |
402 | ||
403 | 000000,5.RS,5.RT,5.RD,10000,101001::::DMACCS | |
404 | "dmaccs r<RD>, r<RS>, r<RT>" | |
405 | *vr4121: | |
406 | { | |
407 | LO = SaturatedAdd (SD_, LO, SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
408 | GPR[RD] = LO; | |
409 | } | |
e1b20d30 AC |
410 | |
411 | ||
f14397f0 GRK |
412 | |
413 | ||
414 | ||
415 | // end-sanitize-vr4xxx | |
416 | // start-sanitize-cygnus | |
417 | // | |
e1b20d30 | 418 | // Unsigned Multiply, Accumulate and Move LO. |
f14397f0 GRK |
419 | // |
420 | 000000,5.RS,5.RT,5.RD,00011,101000::64::MACCU | |
e1b20d30 | 421 | "maccu r<RD>, r<RS>, r<RT>" |
f14397f0 | 422 | // end-sanitize-cygnus |
e1b20d30 AC |
423 | // start-sanitize-vr4320 |
424 | *vr4320: | |
425 | // end-sanitize-vr4320 | |
aeeb756d | 426 | // start-sanitize-cygnus |
e1b20d30 | 427 | *vr5400: |
aeeb756d | 428 | // end-sanitize-cygnus |
f14397f0 GRK |
429 | // start-sanitize-cygnus |
430 | { | |
431 | SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
432 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
433 | } | |
434 | ||
435 | // end-sanitize-cygnus | |
436 | // start-sanitize-vr4xxx | |
437 | 000000,5.RS,5.RT,5.RD,00001,101000::64::MACCU | |
438 | "maccu r<RD>, r<RS>, r<RT>" | |
439 | *vr4121: | |
e1b20d30 AC |
440 | { |
441 | SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
442 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
443 | } | |
444 | ||
f14397f0 GRK |
445 | 000000,5.RS,5.RT,5.RD,00001,101001::64::DMACCU |
446 | "dmaccu r<RD>, r<RS>, r<RT>" | |
447 | *vr4121: | |
448 | { | |
449 | LO = LO + UnsignedMultiply (SD_, GPR[RS], GPR[RT]); | |
450 | GPR[RD] = LO; | |
451 | } | |
452 | ||
453 | 000000,5.RS,5.RT,5.RD,10001,101000::64::MACCUS | |
454 | "maccus r<RD>, r<RS>, r<RT>" | |
455 | *vr4121: | |
456 | { | |
457 | SET_MulAcc (SD_, | |
458 | SaturatedUnsignedAdd (SD_, MulAcc (SD_), | |
459 | UnsignedMultiply (SD_, GPR[RS], GPR[RT]))); | |
460 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
461 | } | |
462 | ||
463 | 000000,5.RS,5.RT,5.RD,10001,101001::64::DMACCUS | |
464 | "dmaccus r<RD>, r<RS>, r<RT>" | |
465 | *vr4121: | |
466 | { | |
467 | LO = SaturatedUnsignedAdd (SD_, LO, | |
468 | UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
469 | GPR[RD] = LO; | |
470 | } | |
471 | ||
472 | ||
e1b20d30 | 473 | |
f14397f0 GRK |
474 | // end-sanitize-vr4xxx |
475 | // start-sanitize-cygnus | |
476 | // | |
e1b20d30 | 477 | // Multiply, Accumulate and Move HI. |
f14397f0 GRK |
478 | // |
479 | 000000,5.RS,5.RT,5.RD,01010,101000::64::MACCHI | |
e1b20d30 | 480 | "macchi r<RD>, r<RS>, r<RT>" |
f14397f0 | 481 | // end-sanitize-cygnus |
e1b20d30 AC |
482 | // start-sanitize-vr4320 |
483 | *vr4320: | |
484 | // end-sanitize-vr4320 | |
aeeb756d | 485 | // start-sanitize-cygnus |
e1b20d30 | 486 | *vr5400: |
aeeb756d | 487 | // end-sanitize-cygnus |
f14397f0 | 488 | // start-sanitize-cygnus |
e1b20d30 AC |
489 | { |
490 | SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
491 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
492 | } | |
493 | ||
f14397f0 GRK |
494 | // end-sanitize-cygnus |
495 | // start-sanitize-vr4xxx | |
496 | 000000,5.RS,5.RT,5.RD,01000,101000::64::MACCHI | |
497 | "macchi r<RD>, r<RS>, r<RT>" | |
498 | *vr4121: | |
499 | { | |
500 | SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
501 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
502 | } | |
e1b20d30 | 503 | |
f14397f0 GRK |
504 | 000000,5.RS,5.RT,5.RD,11000,101000::64::MACCHIS |
505 | "macchis r<RD>, r<RS>, r<RT>" | |
506 | *vr4121: | |
507 | { | |
508 | SET_MulAcc (SD_, SaturatedAdd (SD_, MulAcc (SD_), | |
509 | SignedMultiply (SD_, GPR[RS], GPR[RT]))); | |
510 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
511 | } | |
512 | ||
513 | ||
514 | ||
515 | // end-sanitize-vr4xxx | |
516 | // start-sanitize-cygnus | |
517 | // | |
e1b20d30 | 518 | // Unsigned Multiply, Accumulate and Move HI. |
f14397f0 GRK |
519 | // |
520 | 000000,5.RS,5.RT,5.RD,01011,101000::64::MACCHIU | |
e1b20d30 | 521 | "macchiu r<RD>, r<RS>, r<RT>" |
f14397f0 | 522 | // end-sanitize-cygnus |
e1b20d30 AC |
523 | // start-sanitize-vr4320 |
524 | *vr4320: | |
525 | // end-sanitize-vr4320 | |
aeeb756d | 526 | // start-sanitize-cygnus |
e1b20d30 | 527 | *vr5400: |
aeeb756d | 528 | // end-sanitize-cygnus |
f14397f0 | 529 | // start-sanitize-cygnus |
e1b20d30 AC |
530 | { |
531 | SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
532 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
533 | ||
534 | } | |
535 | ||
f14397f0 GRK |
536 | // end-sanitize-cygnus |
537 | // start-sanitize-vr4xxx | |
538 | 000000,5.RS,5.RT,5.RD,01001,101000::64::MACCHIU | |
539 | "macchiu r<RD>, r<RS>, r<RT>" | |
540 | *vr4121: | |
541 | { | |
542 | SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
543 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
e1b20d30 | 544 | |
f14397f0 | 545 | } |
e1b20d30 | 546 | |
f14397f0 GRK |
547 | 000000,5.RS,5.RT,5.RD,11001,101000::64::MACCHIUS |
548 | "macchius r<RD>, r<RS>, r<RT>" | |
549 | *vr4121: | |
e1b20d30 | 550 | { |
f14397f0 GRK |
551 | SET_MulAcc (SD_, |
552 | SaturatedUnsignedAdd (SD_, MulAcc (SD_), | |
553 | UnsignedMultiply (SD_, GPR[RS], GPR[RT]))); | |
554 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
555 | ||
e1b20d30 AC |
556 | } |
557 | ||
558 | ||
f14397f0 GRK |
559 | |
560 | // end-sanitize-vr4xxx | |
aeeb756d | 561 | // start-sanitize-cygnus |
e1b20d30 | 562 | // Unsigned Multiply, Negate, Accumulate and Move LO. |
f14397f0 | 563 | 000000,5.RS,5.RT,5.RD,00111,011001::64::MSACU |
e1b20d30 | 564 | "msacu r<RD>, r<RS>, r<RT>" |
aeeb756d KR |
565 | // end-sanitize-cygnus |
566 | // start-sanitize-cygnus | |
e1b20d30 | 567 | *vr5400: |
aeeb756d KR |
568 | // end-sanitize-cygnus |
569 | // start-sanitize-cygnus | |
e1b20d30 AC |
570 | { |
571 | SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
572 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
573 | } | |
574 | ||
575 | ||
aeeb756d KR |
576 | // end-sanitize-cygnus |
577 | // start-sanitize-cygnus | |
e1b20d30 AC |
578 | // Multiply, Negate, Accumulate and Move HI. |
579 | 000000,5.RS,5.RT,5.RD,01111,011000::::MSACHI | |
580 | "msachi r<RD>, r<RS>, r<RT>" | |
aeeb756d KR |
581 | // end-sanitize-cygnus |
582 | // start-sanitize-cygnus | |
e1b20d30 | 583 | *vr5400: |
aeeb756d KR |
584 | // end-sanitize-cygnus |
585 | // start-sanitize-cygnus | |
e1b20d30 AC |
586 | { |
587 | SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
588 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
589 | } | |
590 | ||
aeeb756d KR |
591 | // end-sanitize-cygnus |
592 | // start-sanitize-cygnus | |
e1b20d30 | 593 | // Unsigned Multiply, Negate, Accumulate and Move HI. |
f14397f0 | 594 | 000000,5.RS,5.RT,5.RD,01111,011001::64::MSACHIU |
e1b20d30 | 595 | "msachiu r<RD>, r<RS>, r<RT>" |
aeeb756d KR |
596 | // end-sanitize-cygnus |
597 | // start-sanitize-cygnus | |
e1b20d30 | 598 | *vr5400: |
aeeb756d KR |
599 | // end-sanitize-cygnus |
600 | // start-sanitize-cygnus | |
e1b20d30 AC |
601 | { |
602 | SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
603 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
604 | } | |
605 | ||
606 | ||
aeeb756d KR |
607 | // end-sanitize-cygnus |
608 | // start-sanitize-cygnus | |
e1b20d30 | 609 | // Rotate Right. |
f14397f0 | 610 | 000000,00001,5.RT,5.RD,5.SHIFT,000010::64::ROR |
e1b20d30 | 611 | "ror r<RD>, r<RT>, <SHIFT>" |
aeeb756d KR |
612 | // end-sanitize-cygnus |
613 | // start-sanitize-cygnus | |
e1b20d30 | 614 | *vr5400: |
aeeb756d KR |
615 | // end-sanitize-cygnus |
616 | // start-sanitize-cygnus | |
e1b20d30 AC |
617 | { |
618 | int s = SHIFT; | |
619 | GPR[RD] = ROTR32 (GPR[RT], s); | |
620 | } | |
621 | ||
622 | ||
aeeb756d KR |
623 | // end-sanitize-cygnus |
624 | // start-sanitize-cygnus | |
e1b20d30 | 625 | // Rotate Right Variable. |
f14397f0 | 626 | 000000,5.RS,5.RT,5.RD,00001,000110::64::RORV |
e1b20d30 | 627 | "rorv r<RD>, r<RT>, <RS>" |
aeeb756d KR |
628 | // end-sanitize-cygnus |
629 | // start-sanitize-cygnus | |
e1b20d30 | 630 | *vr5400: |
aeeb756d KR |
631 | // end-sanitize-cygnus |
632 | // start-sanitize-cygnus | |
e1b20d30 AC |
633 | { |
634 | int s = MASKED (GPR[RS], 4, 0); | |
635 | GPR[RD] = ROTR32 (GPR[RT], s); | |
636 | } | |
637 | ||
638 | ||
aeeb756d KR |
639 | // end-sanitize-cygnus |
640 | // start-sanitize-cygnus | |
e1b20d30 | 641 | // Double Rotate Right. |
f14397f0 | 642 | 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR |
e1b20d30 | 643 | "dror r<RD>, r<RT>, <SHIFT>" |
aeeb756d KR |
644 | // end-sanitize-cygnus |
645 | // start-sanitize-cygnus | |
e1b20d30 | 646 | *vr5400: |
aeeb756d KR |
647 | // end-sanitize-cygnus |
648 | // start-sanitize-cygnus | |
e1b20d30 AC |
649 | { |
650 | int s = SHIFT; | |
651 | GPR[RD] = ROTR64 (GPR[RT], s); | |
652 | } | |
653 | ||
654 | ||
aeeb756d KR |
655 | // end-sanitize-cygnus |
656 | // start-sanitize-cygnus | |
e1b20d30 | 657 | // Double Rotate Right Plus 32. |
f14397f0 | 658 | 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32 |
e1b20d30 | 659 | "dror32 r<RD>, r<RT>, <SHIFT>" |
aeeb756d KR |
660 | // end-sanitize-cygnus |
661 | // start-sanitize-cygnus | |
e1b20d30 | 662 | *vr5400: |
aeeb756d KR |
663 | // end-sanitize-cygnus |
664 | // start-sanitize-cygnus | |
e1b20d30 AC |
665 | { |
666 | int s = SHIFT + 32; | |
667 | GPR[RD] = ROTR64 (GPR[RT], s); | |
668 | } | |
669 | ||
670 | ||
aeeb756d KR |
671 | // end-sanitize-cygnus |
672 | // start-sanitize-cygnus | |
e1b20d30 | 673 | // Double Rotate Right Variable. |
f14397f0 | 674 | 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV |
e1b20d30 | 675 | "drorv r<RD>, r<RT>, <RS>" |
aeeb756d KR |
676 | // end-sanitize-cygnus |
677 | // start-sanitize-cygnus | |
e1b20d30 | 678 | *vr5400: |
aeeb756d KR |
679 | // end-sanitize-cygnus |
680 | // start-sanitize-cygnus | |
e1b20d30 AC |
681 | { |
682 | int s = MASKED (GPR[RS], 5, 0); | |
683 | GPR[RD] = ROTR64 (GPR[RT], s); | |
684 | } | |
685 | ||
686 | ||
aeeb756d | 687 | // end-sanitize-cygnus |