Commit | Line | Data |
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dd15abd5 GRK |
1 | |
2 | ||
3 | // Integer Instructions | |
4 | // -------------------- | |
5 | // | |
6 | // MulAcc is the Multiply Accumulator. | |
7 | // This register is mapped on the the HI and LO registers. | |
8 | // Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register. | |
9 | // Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register. | |
10 | ||
11 | ||
12 | :function:::unsigned64:MulAcc: | |
13 | { | |
14 | unsigned64 result = U8_4 (HI, LO); | |
15 | return result; | |
16 | } | |
17 | ||
18 | :function:::void:SET_MulAcc:unsigned64 value | |
19 | { | |
20 | *AL4_8 (&HI) = VH4_8 (value); | |
21 | *AL4_8 (&LO) = VL4_8 (value); | |
22 | } | |
23 | ||
24 | :function:::signed64:SignedMultiply:signed32 l, signed32 r | |
25 | { | |
26 | signed64 result = (signed64) l * (signed64) r; | |
27 | return result; | |
28 | } | |
29 | ||
30 | :function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r | |
31 | { | |
32 | unsigned64 result = (unsigned64) l * (unsigned64) r; | |
33 | return result; | |
34 | } | |
35 | ||
36 | :function:::unsigned64:Low32Bits:unsigned64 value | |
37 | { | |
38 | unsigned64 result = (signed64) (signed32) VL4_8 (value); | |
39 | return result; | |
40 | } | |
41 | ||
42 | :function:::unsigned64:High32Bits:unsigned64 value | |
43 | { | |
44 | unsigned64 result = (signed64) (signed32) VH4_8 (value); | |
45 | return result; | |
46 | } | |
47 | ||
48 | ||
49 | ||
50 | // Multiply and Move LO. | |
51 | 000000,5.RS,5.RT,5.RD,00100,101000::::MUL | |
52 | "mul r<RD>, r<RS>, r<RT>" | |
53 | *mipsI,mipsII,mipsIII,mipsIV: | |
54 | { | |
55 | SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
56 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
57 | } | |
58 | ||
59 | // Unsigned Multiply and Move LO. | |
60 | 000000,5.RS,5.RT,5.RD,00101,101000::::MULU | |
61 | "mulu r<RD>, r<RS>, r<RT>" | |
62 | *mipsI,mipsII,mipsIII,mipsIV: | |
63 | { | |
64 | SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
65 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
66 | } | |
67 | ||
68 | // Multiply and Move HI. | |
69 | 000000,5.RS,5.RT,5.RD,01100,101000::::MULHI | |
70 | "mulhi r<RD>, r<RS>, r<RT>" | |
71 | *mipsI,mipsII,mipsIII,mipsIV: | |
72 | { | |
73 | SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
74 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
75 | } | |
76 | ||
77 | // Unsigned Multiply and Move HI. | |
78 | 000000,5.RS,5.RT,5.RD,01101,101000::::MULHIU | |
79 | "mulhiu r<RD>, r<RS>, r<RT>" | |
80 | *mipsI,mipsII,mipsIII,mipsIV: | |
81 | { | |
82 | SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
83 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
84 | } | |
85 | ||
86 | ||
87 | // Multiply, Accumulate | |
88 | 000000,5.RS,5.RT,00000,00000,101000::::MAC | |
89 | "mac r<RS>, r<RT>" | |
90 | *vr4320: | |
91 | { | |
92 | SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
93 | } | |
94 | ||
95 | // D-Multiply, Accumulate | |
96 | 000000,5.RS,5.RT,00000,00000,101001::::DMAC | |
97 | "dmac r<RS>, r<RT>" | |
98 | *mipsI,mipsII,mipsIII,mipsIV: | |
99 | { | |
100 | LO = MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]); | |
101 | } | |
102 | ||
103 | // Multiply, Accumulate and Move LO. | |
104 | 000000,5.RS,5.RT,5.RD,00010,101000::::MACC | |
105 | "macc r<RD>, r<RS>, r<RT>" | |
106 | *mipsI,mipsII,mipsIII,mipsIV: | |
107 | { | |
108 | SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
109 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
110 | } | |
111 | ||
112 | // Unsigned Multiply, Accumulate and Move LO. | |
113 | 000000,5.RS,5.RT,5.RD,00011,101000::::MACCU | |
114 | "maccu r<RD>, r<RS>, r<RT>" | |
115 | *mipsI,mipsII,mipsIII,mipsIV: | |
116 | { | |
117 | SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
118 | GPR[RD] = Low32Bits (SD_, MulAcc (SD_)); | |
119 | } | |
120 | ||
121 | // Multiply, Accumulate and Move HI. | |
122 | 000000,5.RS,5.RT,5.RD,01010,101000::::MACCHI | |
123 | "macchi r<RD>, r<RS>, r<RT>" | |
124 | *mipsI,mipsII,mipsIII,mipsIV: | |
125 | { | |
126 | SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT])); | |
127 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
128 | } | |
129 | ||
130 | // Unsigned Multiply, Accumulate and Move HI. | |
131 | 000000,5.RS,5.RT,5.RD,01011,101000::::MACCHIU | |
132 | "macchiu r<RD>, r<RS>, r<RT>" | |
133 | *mipsI,mipsII,mipsIII,mipsIV: | |
134 | { | |
135 | SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT])); | |
136 | GPR[RD] = High32Bits (SD_, MulAcc (SD_)); | |
137 | ||
138 | } | |
139 |