Implement 32 bit MIPS16 instructions listed in m16.igen.

[deliverable/binutils-gdb.git] / sim / mips / vr5400.igen

// Integer Instructions
// --------------------
//
// MulAcc is the Multiply Accumulator.
//     This register is mapped on the the HI and LO registers.
//     Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
//     Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.


:function:::unsigned64:MulAcc:
{
  unsigned64 result = U8_4 (HI, LO);
  return result;
}

:function:::void:SET_MulAcc:unsigned64 value
{
  *AL4_8 (&HI) = VH4_8 (value);
  *AL4_8 (&LO) = VL4_8 (value);
}

:function:::signed64:SignedMultiply:signed32 l, signed32 r
{
  signed64 result = (signed64) l * (signed64) r;
  return result;
}

:function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
{
  unsigned64 result = (unsigned64) l * (unsigned64) r;
  return result;
}

:function:::unsigned64:Low32Bits:unsigned64 value
{
  unsigned64 result = (signed64) (signed32) VL4_8 (value);
  return result;
}

:function:::unsigned64:High32Bits:unsigned64 value
{
  unsigned64 result = (signed64) (signed32) VH4_8 (value);
  return result;
}



// Multiply and Move LO.
000000,5.RS,5.RT,5.RD,00001,011000::::MUL
"mul r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}

// Unsigned Multiply and Move LO.
000000,5.RS,5.RT,5.RD,00001,011001::::MULU
"mulu r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}

// Multiply and Move HI.
000000,5.RS,5.RT,5.RD,01001,011000::::MULHI
"mulhi r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, 0 + SignedMultiply   (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}

// Unsigned Multiply and Move HI.
000000,5.RS,5.RT,5.RD,01001,011001::::MULHIU
"mulhiu r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}


// Multiply, Negate and Move LO.
000000,5.RS,5.RT,5.RD,00011,011000::::MULS
"muls r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, 0 - SignedMultiply   (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}

// Unsigned Multiply, Negate and Move LO.
000000,5.RS,5.RT,5.RD,00011,011001::::MULSU
"mulsu r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}

// Multiply, Negate and Move HI.
000000,5.RS,5.RT,5.RD,01011,011000::::MULSHI
"mulshi r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, 0 - SignedMultiply   (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}

// Unsigned Multiply, Negate and Move HI.
000000,5.RS,5.RT,5.RD,01011,011001::::MULSHIU
"mulshiu r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}


// Multiply, Accumulate and Move LO.
000000,5.RS,5.RT,5.RD,00101,011000::::MACC
"macc r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}

// Unsigned Multiply, Accumulate and Move LO.
000000,5.RS,5.RT,5.RD,00101,011001::::MACCU
"maccu r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}

// Multiply, Accumulate and Move HI.
000000,5.RS,5.RT,5.RD,01101,011000::::MACCHI
"macchi r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}

// Unsigned Multiply, Accumulate and Move HI.
000000,5.RS,5.RT,5.RD,01101,011001::::MACCHIU
"macchiu r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));

}

// Multiply, Negate, Accumulate and Move LO.
000000,5.RS,5.RT,5.RD,00111,011000::::MSAC
"msac r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}

// Unsigned Multiply, Negate, Accumulate and Move LO.
000000,5.RS,5.RT,5.RD,00111,011001::::MSACU
"msacu r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}

// Multiply, Negate, Accumulate and Move HI.
000000,5.RS,5.RT,5.RD,01111,011000::::MSACHI
"msachi r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}

// Unsigned Multiply, Negate, Accumulate and Move HI.
000000,5.RS,5.RT,5.RD,01111,011001::::MSACHIU
"msachiu r<RD>, r<RS>, r<RT>"
*vr5400:
{
  SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}


// Rotate Right.
000000,00001,5.RT,5.RD,5.SHIFT,000010::::ROR
"ror r<RD>, r<RT>, <SHIFT>"
*vr5400:
{
  int s = SHIFT;
  GPR[RD] = ROTR32 (GPR[RT], s);
}

// Rotate Right Variable.
000000,5.RS,5.RT,5.RD,00001,000110::::RORV
"rorv r<RD>, r<RT>, <RS>"
*vr5400:
{
  int s = MASKED (GPR[RS], 4, 0);
  GPR[RD] = ROTR32 (GPR[RT], s);
}

// Double Rotate Right.
000000,00001,5.RT,5.RD,5.SHIFT,111010::::DROR
"dror r<RD>, r<RT>, <SHIFT>"
*vr5400:
{
  int s = SHIFT;
  GPR[RD] = ROTR64 (GPR[RT], s);
}

// Double Rotate Right Plus 32.
000000,00001,5.RT,5.RD,5.SHIFT,111110::::DROR32
"dror32 r<RD>, r<RT>, <SHIFT>"
*vr5400:
{
  int s = SHIFT + 32;
  GPR[RD] = ROTR64 (GPR[RT], s);
}

// Double Rotate Right Variable.
000000,5.RS,5.RT,5.RD,00001,010110::::DRORV
"drorv r<RD>, r<RT>, <RS>"
*vr5400:
{
  int s = MASKED (GPR[RS], 5, 0);
  GPR[RD] = ROTR64 (GPR[RT], s);
}