projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 2e8f4133 JL |
1 | Sat Dec 7 09:50:28 1996 Jeffrey A Law (law@cygnus.com) |
| 2 | ||
| 3 | * simops.c (REG0_16): Fix typo. | |
| 4 | ||
| d2523010 JL |
5 | Fri Dec 6 14:13:34 1996 Jeffrey A Law (law@cygnus.com) |
| 6 | ||
| b2f7a7e5 JL |
7 | * simops.c: Call abort for any instruction that's not currently |
| 8 | simulated. | |
| 9 | ||
| 9f4a551e JL |
10 | * simops.c: Define accessor macros to extract register |
| 11 | values from instructions. Use them consistently. | |
| 12 | ||
| 7c52bf32 JL |
13 | * interp.c: Delete unused global variable "OP". |
| 14 | (sim_resume): Remove unused variable "opcode". | |
| 15 | * simops.c: Fix some uninitialized variable problems, add | |
| 16 | parens to fix various -Wall warnings. | |
| 17 | ||
| d2523010 JL |
18 | * gencode.c (write_header): Add "insn" and "extension" arguments |
| 19 | to the OP_* declarations. | |
| 20 | (write_template): Similarly for function templates. | |
| 21 | * interp.c (insn, extension): Remove global variables. Instead | |
| 22 | pass them as arguments to the OP_* functions. | |
| 23 | * mn10300_sim.h: Remove decls for "insn" and "extension". | |
| 24 | * simops.c (OP_*): Accept "insn" and "extension" as arguments | |
| 25 | instead of using globals. | |
| 26 | ||
| 4d8ced6c JL |
27 | Thu Dec 5 22:26:31 1996 Jeffrey A Law (law@cygnus.com) |
| 28 | ||
| e5a7a537 JL |
29 | * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)" |
| 30 | ||
| 4d8ced6c JL |
31 | * simops.c: Fix thinkos in last change to "inc dn". |
| 32 | ||
| 61ecca95 JL |
33 | Wed Dec 4 10:57:53 1996 Jeffrey A Law (law@cygnus.com) |
| 34 | ||
| 35 | * simops.c: "add imm,sp" does not effect the condition codes. | |
| 36 | "inc dn" does effect the condition codes. | |
| 37 | ||
| e4e13022 JL |
38 | Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com) |
| 39 | ||
| 40 | * simops.c: Treat both operands as signed values for | |
| 41 | "div" instruction. | |
| 42 | ||
| 43 | * simops.c: Fix simulation of division instructions. | |
| 44 | Fix typos/thinkos in several "cmp" and "sub" instructions. | |
| 45 | ||
| fcfaf40d JL |
46 | Mon Dec 2 12:31:40 1996 Jeffrey A Law (law@cygnus.com) |
| 47 | ||
| e4e13022 JL |
48 | * simops.c: Fix carry bit handling in "sub" and "cmp" |
| 49 | instructions. | |
| 50 | ||
| fcfaf40d JL |
51 | * simops.c: Fix "mov imm8,an" and "mov imm16,dn". |
| 52 | ||
| 6db7fc49 JL |
53 | Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com) |
| 54 | ||
| b7b89deb JL |
55 | * simops.c: Fix overflow computation for many instructions. |
| 56 | ||
| e5a7a537 | 57 | * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)". |
| af388638 | 58 | |
| c8f0171f JL |
59 | * simops.c: Fix "mov am, dn". |
| 60 | ||
| 6db7fc49 JL |
61 | * simops.c: Fix more bugs in "add imm,an" and |
| 62 | "add imm,dn". | |
| 63 | ||
| f5f13c1d JL |
64 | Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com) |
| 65 | ||
| 6e7a01c1 JL |
66 | * simops.c: Fix bugs in "movm" and "add imm,an". |
| 67 | ||
| 3bb3fe44 JL |
68 | * simops.c: Don't lose the upper 24 bits of the return |
| 69 | pointer in "call" and "calls" instructions. Rough cut | |
| 70 | at emulated system calls. | |
| 71 | ||
| de0dce7c JL |
72 | * simops.c: Implement the remaining 5, 6 and 7 byte instructions. |
| 73 | ||
| ecb4b5a3 JL |
74 | * simops.c: Implement remaining 4 byte instructions. |
| 75 | ||
| 76 | * simops.c: Implement remaining 3 byte instructions. | |
| 2e35551c | 77 | |
| f5f13c1d JL |
78 | * simops.c: Implement remaining 2 byte instructions. Call |
| 79 | abort for instructions we're not implementing now. | |
| 80 | ||
| 73e65298 JL |
81 | Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com) |
| 82 | ||
| 707641f6 JL |
83 | * simops.c: Implement lots of random instructions. |
| 84 | ||
| 1f3bea21 JL |
85 | * simops.c: Implement "movm" and "bCC" insns. |
| 86 | ||
| 92284aaa JL |
87 | * mn10300_sim.h (_state): Add another register (MDR). |
| 88 | (REG_MDR): Define. | |
| 89 | * simops.c: Implement "cmp", "calls", "rets", "jmp" and | |
| 90 | a few additional random insns. | |
| 91 | ||
| 73e65298 JL |
92 | * mn10300_sim.h (PSW_*): Define for CC status tracking. |
| 93 | (REG_D0, REG_A0, REG_SP): Define. | |
| 94 | * simops.c: Implement "add", "addc" and a few other random | |
| 95 | instructions. | |
| b5f831ac JL |
96 | |
| 97 | * gencode.c, interp.c: Snapshot current simulator code. | |
| 98 | ||
| 05ccbdfd JL |
99 | Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com) |
| 100 | ||
| 101 | * Makefile.in, config.in, configure, configure.in: New files. | |
| 102 | * gencode.c, interp.c, mn10300_sim.h, simops.c: New files. | |
| 103 |