Commit | Line | Data |
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f5f13c1d JL |
1 | Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com) |
2 | ||
3bb3fe44 JL |
3 | * simops.c: Don't lose the upper 24 bits of the return |
4 | pointer in "call" and "calls" instructions. Rough cut | |
5 | at emulated system calls. | |
6 | ||
de0dce7c JL |
7 | * simops.c: Implement the remaining 5, 6 and 7 byte instructions. |
8 | ||
ecb4b5a3 JL |
9 | * simops.c: Implement remaining 4 byte instructions. |
10 | ||
11 | * simops.c: Implement remaining 3 byte instructions. | |
2e35551c | 12 | |
f5f13c1d JL |
13 | * simops.c: Implement remaining 2 byte instructions. Call |
14 | abort for instructions we're not implementing now. | |
15 | ||
73e65298 JL |
16 | Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com) |
17 | ||
707641f6 JL |
18 | * simops.c: Implement lots of random instructions. |
19 | ||
1f3bea21 JL |
20 | * simops.c: Implement "movm" and "bCC" insns. |
21 | ||
92284aaa JL |
22 | * mn10300_sim.h (_state): Add another register (MDR). |
23 | (REG_MDR): Define. | |
24 | * simops.c: Implement "cmp", "calls", "rets", "jmp" and | |
25 | a few additional random insns. | |
26 | ||
73e65298 JL |
27 | * mn10300_sim.h (PSW_*): Define for CC status tracking. |
28 | (REG_D0, REG_A0, REG_SP): Define. | |
29 | * simops.c: Implement "add", "addc" and a few other random | |
30 | instructions. | |
b5f831ac JL |
31 | |
32 | * gencode.c, interp.c: Snapshot current simulator code. | |
33 | ||
05ccbdfd JL |
34 | Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com) |
35 | ||
36 | * Makefile.in, config.in, configure, configure.in: New files. | |
37 | * gencode.c, interp.c, mn10300_sim.h, simops.c: New files. | |
38 |