Commit | Line | Data |
---|---|---|
a77aa7ec AC |
1 | Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com> |
2 | ||
3 | * configure: Re-generate. | |
4 | ||
601fb8ae MM |
5 | Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com> |
6 | ||
7 | * configure: Regenerate to track ../common/aclocal.m4 changes. | |
8 | ||
53b9417e DE |
9 | Thu Mar 13 12:54:45 1997 Doug Evans <dje@canuck.cygnus.com> |
10 | ||
11 | * interp.c (sim_open): New SIM_DESC result. Argument is now | |
12 | in argv form. | |
13 | (other sim_*): New SIM_DESC argument. | |
14 | ||
09eef8af JL |
15 | Wed Mar 12 15:04:00 1997 Jeffrey A Law (law@cygnus.com) |
16 | ||
0ade484f JL |
17 | * simops.c: Fix carry bit computation for "add" instructions. |
18 | ||
09eef8af JL |
19 | * simops.c: Fix typos in bset insns. Fix arguments to store_mem |
20 | for bset imm8,(d8,an) and bclr imm8,(d8,an). | |
21 | ||
22 | Wed Mar 5 15:00:10 1997 Jeffrey A Law (law@cygnus.com) | |
23 | ||
24 | * simops.c: Fix register references when computing Z and N bits | |
25 | for lsr imm8,dn. | |
26 | ||
27 | Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com> | |
28 | ||
29 | * Makefile.in (@COMMON_MAKEFILE_FRAG): Use | |
30 | COMMON_{PRE,POST}_CONFIG_FRAG instead. | |
31 | * configure.in: sinclude ../common/aclocal.m4. | |
32 | * configure: Regenerated. | |
33 | ||
018f9eb4 JL |
34 | Fri Jan 24 10:47:25 1997 Jeffrey A Law (law@cygnus.com) |
35 | ||
36 | * interp.c (init_system): Allocate 2^19 bytes of space for the | |
37 | simulator. | |
38 | ||
295dbbe4 SG |
39 | Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com) |
40 | ||
41 | * configure configure.in Makefile.in: Update to new configure | |
42 | scheme which is more compatible with WinGDB builds. | |
43 | * configure.in: Improve comment on how to run autoconf. | |
44 | * configure: Re-run autoconf to get new ../common/aclocal.m4. | |
45 | * Makefile.in: Use autoconf substitution to install common | |
46 | makefile fragment. | |
47 | ||
f95251f0 JL |
48 | Tue Jan 21 15:03:04 1997 Jeffrey A Law (law@cygnus.com) |
49 | ||
50 | * simops.c: Undo last change to "rol" and "ror", original code | |
51 | was correct! | |
52 | ||
b4b290a0 JL |
53 | Thu Jan 16 11:28:14 1997 Jeffrey A Law (law@cygnus.com) |
54 | ||
55 | * simops.c: Fix "rol" and "ror". | |
56 | ||
57 | Wed Jan 15 06:45:58 1997 Jeffrey A Law (law@cygnus.com) | |
58 | ||
59 | * simops.c: Fix typo in last change. | |
60 | ||
2da0bc1b JL |
61 | Mon Jan 13 13:22:35 1997 Jeffrey A Law (law@cygnus.com) |
62 | ||
63 | * simops.c: Use REG macros in few places not using them yet. | |
64 | ||
bbd17062 JL |
65 | Mon Jan 6 16:21:19 1997 Jeffrey A Law (law@cygnus.com) |
66 | ||
67 | * mn10300_sim.h (struct _state): Fix number of registers! | |
68 | ||
b774c0e4 JL |
69 | Tue Dec 31 16:20:41 1996 Jeffrey A Law (law@cygnus.com) |
70 | ||
71 | * mn10300_sim.h (struct _state): Put all registers into a single | |
72 | array to make gdb implementation easier. | |
73 | (REG_*): Add definitions for all registers in the state array. | |
74 | (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros. | |
75 | * simops.c: Related changes. | |
76 | ||
d657034d JL |
77 | Wed Dec 18 10:10:45 1996 Jeffrey A Law (law@cygnus.com) |
78 | ||
79 | * interp.c (sim_resume): Handle 0xff as a single byte insn. | |
80 | ||
81 | * simops.c: Fix overflow computation for "add" and "inc" | |
82 | instructions. | |
83 | ||
16d2e2b6 JL |
84 | Mon Dec 16 10:03:52 1996 Jeffrey A Law (law@cygnus.com) |
85 | ||
093e9a32 JL |
86 | * simops.c: Handle "break" instruction. |
87 | ||
16d2e2b6 JL |
88 | * simops.c: Fix restoring the PC for "ret" and "retf" instructions. |
89 | ||
90 | Wed Dec 11 09:53:10 1996 Jeffrey A Law (law@cygnus.com) | |
91 | ||
92 | * gencode.c (write_opcodes): Also write out the format of the | |
93 | opcode. | |
94 | * mn10300_sim.h (simops): Add "format" field. | |
95 | * interp.c (sim_resume): Deal with endianness issues here. | |
96 | ||
95d18eb7 JL |
97 | Tue Dec 10 15:05:37 1996 Jeffrey A Law (law@cygnus.com) |
98 | ||
99 | * simops.c (REG0_4): Define. | |
100 | Use REG0_4 for indexed loads/stores. | |
101 | ||
2e8f4133 JL |
102 | Sat Dec 7 09:50:28 1996 Jeffrey A Law (law@cygnus.com) |
103 | ||
104 | * simops.c (REG0_16): Fix typo. | |
105 | ||
d2523010 JL |
106 | Fri Dec 6 14:13:34 1996 Jeffrey A Law (law@cygnus.com) |
107 | ||
b2f7a7e5 JL |
108 | * simops.c: Call abort for any instruction that's not currently |
109 | simulated. | |
110 | ||
9f4a551e JL |
111 | * simops.c: Define accessor macros to extract register |
112 | values from instructions. Use them consistently. | |
113 | ||
7c52bf32 JL |
114 | * interp.c: Delete unused global variable "OP". |
115 | (sim_resume): Remove unused variable "opcode". | |
116 | * simops.c: Fix some uninitialized variable problems, add | |
117 | parens to fix various -Wall warnings. | |
118 | ||
d2523010 JL |
119 | * gencode.c (write_header): Add "insn" and "extension" arguments |
120 | to the OP_* declarations. | |
121 | (write_template): Similarly for function templates. | |
122 | * interp.c (insn, extension): Remove global variables. Instead | |
123 | pass them as arguments to the OP_* functions. | |
124 | * mn10300_sim.h: Remove decls for "insn" and "extension". | |
125 | * simops.c (OP_*): Accept "insn" and "extension" as arguments | |
126 | instead of using globals. | |
127 | ||
4d8ced6c JL |
128 | Thu Dec 5 22:26:31 1996 Jeffrey A Law (law@cygnus.com) |
129 | ||
e5a7a537 JL |
130 | * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)" |
131 | ||
4d8ced6c JL |
132 | * simops.c: Fix thinkos in last change to "inc dn". |
133 | ||
61ecca95 JL |
134 | Wed Dec 4 10:57:53 1996 Jeffrey A Law (law@cygnus.com) |
135 | ||
136 | * simops.c: "add imm,sp" does not effect the condition codes. | |
137 | "inc dn" does effect the condition codes. | |
138 | ||
e4e13022 JL |
139 | Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com) |
140 | ||
141 | * simops.c: Treat both operands as signed values for | |
142 | "div" instruction. | |
143 | ||
144 | * simops.c: Fix simulation of division instructions. | |
145 | Fix typos/thinkos in several "cmp" and "sub" instructions. | |
146 | ||
fcfaf40d JL |
147 | Mon Dec 2 12:31:40 1996 Jeffrey A Law (law@cygnus.com) |
148 | ||
e4e13022 JL |
149 | * simops.c: Fix carry bit handling in "sub" and "cmp" |
150 | instructions. | |
151 | ||
fcfaf40d JL |
152 | * simops.c: Fix "mov imm8,an" and "mov imm16,dn". |
153 | ||
6db7fc49 JL |
154 | Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com) |
155 | ||
b7b89deb JL |
156 | * simops.c: Fix overflow computation for many instructions. |
157 | ||
e5a7a537 | 158 | * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)". |
af388638 | 159 | |
c8f0171f JL |
160 | * simops.c: Fix "mov am, dn". |
161 | ||
6db7fc49 JL |
162 | * simops.c: Fix more bugs in "add imm,an" and |
163 | "add imm,dn". | |
164 | ||
f5f13c1d JL |
165 | Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com) |
166 | ||
6e7a01c1 JL |
167 | * simops.c: Fix bugs in "movm" and "add imm,an". |
168 | ||
3bb3fe44 JL |
169 | * simops.c: Don't lose the upper 24 bits of the return |
170 | pointer in "call" and "calls" instructions. Rough cut | |
171 | at emulated system calls. | |
172 | ||
de0dce7c JL |
173 | * simops.c: Implement the remaining 5, 6 and 7 byte instructions. |
174 | ||
ecb4b5a3 JL |
175 | * simops.c: Implement remaining 4 byte instructions. |
176 | ||
177 | * simops.c: Implement remaining 3 byte instructions. | |
2e35551c | 178 | |
f5f13c1d JL |
179 | * simops.c: Implement remaining 2 byte instructions. Call |
180 | abort for instructions we're not implementing now. | |
181 | ||
73e65298 JL |
182 | Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com) |
183 | ||
707641f6 JL |
184 | * simops.c: Implement lots of random instructions. |
185 | ||
1f3bea21 JL |
186 | * simops.c: Implement "movm" and "bCC" insns. |
187 | ||
92284aaa JL |
188 | * mn10300_sim.h (_state): Add another register (MDR). |
189 | (REG_MDR): Define. | |
190 | * simops.c: Implement "cmp", "calls", "rets", "jmp" and | |
191 | a few additional random insns. | |
192 | ||
73e65298 JL |
193 | * mn10300_sim.h (PSW_*): Define for CC status tracking. |
194 | (REG_D0, REG_A0, REG_SP): Define. | |
195 | * simops.c: Implement "add", "addc" and a few other random | |
196 | instructions. | |
b5f831ac JL |
197 | |
198 | * gencode.c, interp.c: Snapshot current simulator code. | |
199 | ||
05ccbdfd JL |
200 | Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com) |
201 | ||
202 | * Makefile.in, config.in, configure, configure.in: New files. | |
203 | * gencode.c, interp.c, mn10300_sim.h, simops.c: New files. | |
204 |