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Fri Jul 24 18:15:21 1998 Joyce Janczyn <janczyn@cygnus.com>
[deliverable/binutils-gdb.git] / sim / mn10300 / am33.igen
CommitLineData
9c55817e
JL		 1// Helper:
2//
3// Given an extended register number, translate it into an index into the
4// register array. This is necessary as the upper 8 extended registers are
5// actually synonyms for the d0-d3/a0-a3 registers.
6//
7//
8
9:function:::int:translate_rreg:int rreg
10{
11
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
18 else
19 return REG_E0 + rreg;
20}
21
6d254a2d
JL		 22:function:::int:translate_xreg:int xreg
23{
24 switch (xreg)
25 {
26 case 0:
27 return REG_SP;
28 case 1:
29 return REG_MDRQ;
30 case 2:
31 return REG_MCRH;
32 case 3:
33 return REG_MCRL;
34 case 4:
35 return REG_MCVF;
36 default:
37 abort ();
38 }
39}
40
0f7d7385
JL		 41// 1111 0000 0010 00An; mov USP,An
428.0xf0+4.0x2,00,2.AN0:D0m:::mov
43"mov"
44*am33
45{
46 PC = cia;
47 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
48}
49
50
51// 1111 0000 0010 01An; mov SSP,An
528.0xf0+4.0x2,01,2.AN0:D0n:::mov
53"mov"
54*am33
55{
56 PC = cia;
57 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
58}
59
60
61// 1111 0000 0010 10An; mov MSP,An
628.0xf0+4.0x2,10,2.AN0:D0o:::mov
63"mov"
64*am33
65{
66 PC = cia;
67 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
68}
69
70
71// 1111 0000 0010 11An; mov PC,An
728.0xf0+4.0x2,11,2.AN0:D0p:::mov
73"mov"
74*am33
75{
76 PC = cia;
77 State.regs[REG_A0 + AN0] = PC;
78}
79
80
81// 1111 0000 0011 Am00; mov Am,USP
828.0xf0+4.0x3,2.AM1,00:D0q:::mov
83"mov"
3e75ff7e 84*am33
0f7d7385
JL		 85{
86 PC = cia;
87 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
88}
89
90// 1111 0000 0011 Am01; mov Am,SSP
918.0xf0+4.0x3,2.AM1,01:D0r:::mov
92"mov"
3e75ff7e 93*am33
0f7d7385
JL		 94{
95 PC = cia;
96 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
97}
98
99// 1111 0000 0011 Am10; mov Am,MSP
1008.0xf0+4.0x3,2.AM1,10:D0s:::mov
101"mov"
3e75ff7e 102*am33
0f7d7385
JL		 103{
104 PC = cia;
105 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
106}
107
108
109// 1111 0000 1110 imm4; syscall
1108.0xf0+4.0xe,IMM4:D0t:::syscall
111"syscall"
112*am33
113{
114 unsigned int sp, next_pc;
115
116 PC = cia;
117 sp = State.regs[REG_SP];
118 next_pc = State.regs[REG_PC] + 2;
119 store_word (sp - 4, next_pc);
120 store_word (sp - 8, PSW);
121 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
122 nia = PC;
123}
124
125
126// 1111 0010 1110 11Dn; mov EPSW,Dn
1278.0xf2+4.0xe,11,2.DN0:D0u:::mov
128"mov"
129*am33
130{
131 PC = cia;
132 State.regs[REG_D0 + DN0] = PSW;
133}
134
135
136// 1111 0010 1111 Dm01; mov Dm,EPSW
1378.0xf2+4.0xf,2.DM1,01:D0v:::mov
138"mov"
139*am33
140{
141 PC = cia;
142 PSW = State.regs[REG_D0 + DM1];
143}
144
145// 1111 0101 00Am Rn; mov Am,Rn
1468.0xf5+00,2.AM1,4.RN0:D0w:::mov
147"mov"
148*am33
149{
9c55817e
JL		 150 int destreg = translate_rreg (SD_, RN0);
151
0f7d7385 152 PC = cia;
9c55817e 153 State.regs[destreg] = State.regs[REG_A0 + AM1];
0f7d7385
JL		 154}
155
156// 1111 0101 01Dm Rn; mov Dm,Rn
1578.0xf5+01,2.DM1,4.RN0:D0x:::mov
158"mov"
159*am33
160{
9c55817e
JL		 161 int destreg = translate_rreg (SD_, RN0);
162
0f7d7385 163 PC = cia;
9c55817e 164 State.regs[destreg] = State.regs[REG_D0 + DM1];
0f7d7385
JL		 165}
166
167// 1111 0101 10Rm An; mov Rm,An
1688.0xf5+10,4.RM1,2.AN0:D0y:::mov
169"mov"
170*am33
171{
9c55817e
JL		 172 int destreg = translate_rreg (SD_, RM1);
173
0f7d7385 174 PC = cia;
9c55817e 175 State.regs[REG_A0 + AN0] = State.regs[destreg];
0f7d7385
JL		 176}
177
178// 1111 0101 11Rm Dn; mov Rm,Dn
1798.0xf5+11,4.RM1,2.DN0:D0z:::mov
180"mov"
181*am33
182{
9c55817e
JL		 183 int destreg = translate_rreg (SD_, RM1);
184
0f7d7385 185 PC = cia;
9c55817e 186 State.regs[REG_D0 + DN0] = State.regs[destreg];
0f7d7385
JL		 187}
188
189
190// 1111 1000 1100 1110 regs....; movm (USP),regs
1918.0xf8+8.0xce+8.REGS:D1a:::movm
192"movm"
3e75ff7e 193*am33
0f7d7385
JL		 194{
195 unsigned long usp = State.regs[REG_USP];
196 unsigned long mask;
197
198 PC = cia;
199 mask = REGS;
200
201 if (mask & 0x8)
202 {
203 usp += 4;
204 State.regs[REG_LAR] = load_word (usp);
205 usp += 4;
206 State.regs[REG_LIR] = load_word (usp);
207 usp += 4;
208 State.regs[REG_MDR] = load_word (usp);
209 usp += 4;
210 State.regs[REG_A0 + 1] = load_word (usp);
211 usp += 4;
212 State.regs[REG_A0] = load_word (usp);
213 usp += 4;
214 State.regs[REG_D0 + 1] = load_word (usp);
215 usp += 4;
216 State.regs[REG_D0] = load_word (usp);
217 usp += 4;
218 }
219
220 if (mask & 0x10)
221 {
222 State.regs[REG_A0 + 3] = load_word (usp);
223 usp += 4;
224 }
225
226 if (mask & 0x20)
227 {
228 State.regs[REG_A0 + 2] = load_word (usp);
229 usp += 4;
230 }
231
232 if (mask & 0x40)
233 {
234 State.regs[REG_D0 + 3] = load_word (usp);
235 usp += 4;
236 }
237
238 if (mask & 0x80)
239 {
240 State.regs[REG_D0 + 2] = load_word (usp);
241 usp += 4;
242 }
243
244 /* start-sanitize-am33 */
245 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
246 {
247 if (mask & 0x1)
248 {
249 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
250 usp += 16;
251 State.regs[REG_E0 + 1] = load_word (usp);
252 usp += 4;
253 State.regs[REG_E0 + 0] = load_word (usp);
254 usp += 4;
255 }
256
257 if (mask & 0x2)
258 {
259 State.regs[REG_E0 + 7] = load_word (usp);
260 usp += 4;
261 State.regs[REG_E0 + 6] = load_word (usp);
262 usp += 4;
263 State.regs[REG_E0 + 5] = load_word (usp);
264 usp += 4;
265 State.regs[REG_E0 + 4] = load_word (usp);
266 usp += 4;
267 }
268
269 if (mask & 0x4)
270 {
271 State.regs[REG_E0 + 3] = load_word (usp);
272 usp += 4;
273 State.regs[REG_E0 + 2] = load_word (usp);
274 usp += 4;
275 }
276 }
277 /* end-sanitize-am33 */
278
279 /* And make sure to update the stack pointer. */
280 State.regs[REG_USP] = usp;
281}
282
283// 1111 1000 1100 1111 regs....; movm (USP),regs
2848.0xf8+8.0xcf+8.REGS:D1b:::movm
285"movm"
3e75ff7e 286*am33
0f7d7385
JL		 287{
288 unsigned long usp = State.regs[REG_USP];
289 unsigned long mask;
290
291 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
292 {
293 if (mask & 0x4)
294 {
295 usp -= 4;
296 store_word (usp, State.regs[REG_E0 + 2]);
297 usp -= 4;
298 store_word (usp, State.regs[REG_E0 + 3]);
299 }
300
301 if (mask & 0x2)
302 {
303 usp -= 4;
304 store_word (usp, State.regs[REG_E0 + 4]);
305 usp -= 4;
306 store_word (usp, State.regs[REG_E0 + 5]);
307 usp -= 4;
308 store_word (usp, State.regs[REG_E0 + 6]);
309 usp -= 4;
310 store_word (usp, State.regs[REG_E0 + 7]);
311 }
312
313 if (mask & 0x1)
314 {
315 usp -= 4;
316 store_word (usp, State.regs[REG_E0 + 0]);
317 usp -= 4;
318 store_word (usp, State.regs[REG_E0 + 1]);
319 usp -= 16;
320 /* Need to save MDQR, MCRH, MCRL, and MCVF */
321 }
322 }
323 /* end-sanitize-am33 */
324
325 if (mask & 0x80)
326 {
327 usp -= 4;
328 store_word (usp, State.regs[REG_D0 + 2]);
329 }
330
331 if (mask & 0x40)
332 {
333 usp -= 4;
334 store_word (usp, State.regs[REG_D0 + 3]);
335 }
336
337 if (mask & 0x20)
338 {
339 usp -= 4;
340 store_word (usp, State.regs[REG_A0 + 2]);
341 }
342
343 if (mask & 0x10)
344 {
345 usp -= 4;
346 store_word (usp, State.regs[REG_A0 + 3]);
347 }
348
349 if (mask & 0x8)
350 {
351 usp -= 4;
352 store_word (usp, State.regs[REG_D0]);
353 usp -= 4;
354 store_word (usp, State.regs[REG_D0 + 1]);
355 usp -= 4;
356 store_word (usp, State.regs[REG_A0]);
357 usp -= 4;
358 store_word (usp, State.regs[REG_A0 + 1]);
359 usp -= 4;
360 store_word (usp, State.regs[REG_MDR]);
361 usp -= 4;
362 store_word (usp, State.regs[REG_LIR]);
363 usp -= 4;
364 store_word (usp, State.regs[REG_LAR]);
365 usp -= 4;
366 }
367
368 /* And make sure to update the stack pointer. */
369 State.regs[REG_USP] = usp;
370}
371
372// 1111 1100 1111 1100 imm32...; and imm32,EPSW
3738.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
374"and"
375*am33
376{
377 PC = cia;
378 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
379}
380
381// 1111 1100 1111 1101 imm32...; or imm32,EPSW
3828.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
383"or"
384*am33
385{
386 PC = cia;
387 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
388}
389
390// 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
3918.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
392"mov"
393*am33
394{
395 int srcreg, dstreg;
396
397 PC = cia;
398
9c55817e
JL		 399 srcreg = translate_rreg (SD_, RM2);
400 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 401 State.regs[dstreg] = State.regs[srcreg];
402}
403
404// 1111 1001 0001 1000 Rn Rn; ext Rn
4058.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
406"mov"
407*am33
408{
9c55817e 409 int srcreg;
0f7d7385
JL		 410
411 PC = cia;
9c55817e 412 srcreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 413 if (State.regs[srcreg] & 0x80000000)
414 State.regs[REG_MDR] = -1;
415 else
416 State.regs[REG_MDR] = 0;
417}
418
419// 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
4208.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
421"extb"
422*am33
423{
424 int srcreg, dstreg;
425
426 PC = cia;
9c55817e
JL		 427 srcreg = translate_rreg (SD_, RM2);
428 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 429 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
430}
431
432// 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
4338.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
434"extbu"
435*am33
436{
437 int srcreg, dstreg;
438
439 PC = cia;
9c55817e
JL		 440 srcreg = translate_rreg (SD_, RM2);
441 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 442 State.regs[dstreg] = State.regs[srcreg] & 0xff;
443}
444
445// 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
4468.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
447"exth"
448*am33
449{
450 int srcreg, dstreg;
451
452 PC = cia;
9c55817e
JL		 453 srcreg = translate_rreg (SD_, RM2);
454 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 455 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
456}
457
458// 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
4598.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
460"exthu"
461*am33
462{
463 int srcreg, dstreg;
464
465 PC = cia;
9c55817e
JL		 466 srcreg = translate_rreg (SD_, RM2);
467 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 468 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
469}
470
471// 1111 1001 0110 1000 Rn Rn; clr Rn
4728.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
473"clr"
474*am33
475{
9c55817e 476 int dstreg;
0f7d7385
JL		 477
478 PC = cia;
9c55817e 479 dstreg = translate_rreg (SD_, RN0);
0f7d7385 480 State.regs[dstreg] = 0;
0f7d7385
JL		 481 PSW |= PSW_Z;
482 PSW &= ~(PSW_V | PSW_C | PSW_N);
483}
484
485// 1111 1001 0111 1000 Rm Rn; add Rm,Rn
4868.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
487"add"
488*am33
489{
490 int srcreg, dstreg;
491
492 PC = cia;
9c55817e
JL		 493 srcreg = translate_rreg (SD_, RM2);
494 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 495 genericAdd (State.regs[srcreg], dstreg);
496}
497
498// 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
4998.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
500"addc"
501*am33
502{
503 int srcreg, dstreg;
504 int z, c, n, v;
505 unsigned long reg1, reg2, sum;
506
507 PC = cia;
9c55817e
JL		 508 srcreg = translate_rreg (SD_, RM2);
509 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 510
511 reg1 = State.regs[srcreg];
512 reg2 = State.regs[dstreg];
513 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
514 State.regs[dstreg] = sum;
515
4e86afb8 516 z = ((PSW & PSW_Z) != 0) && (sum == 0);
0f7d7385
JL		 517 n = (sum & 0x80000000);
518 c = (sum < reg1) || (sum < reg2);
519 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
520 && (reg2 & 0x80000000) != (sum & 0x80000000));
521
522 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
523 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
524 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
525}
526
527// 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
5288.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
529"sub"
530*am33
531{
532 int srcreg, dstreg;
533
534 PC = cia;
9c55817e
JL		 535 srcreg = translate_rreg (SD_, RM2);
536 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 537 genericSub (State.regs[srcreg], dstreg);
538}
539
540// 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
5418.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
542"subc"
543*am33
544{
545 int srcreg, dstreg;
546 int z, c, n, v;
547 unsigned long reg1, reg2, difference;
548
549 PC = cia;
9c55817e
JL		 550 srcreg = translate_rreg (SD_, RM2);
551 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 552
553 reg1 = State.regs[srcreg];
554 reg2 = State.regs[dstreg];
555 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
556 State.regs[dstreg] = difference;
557
4e86afb8 558 z = ((PSW & PSW_Z) != 0) && (difference == 0);
0f7d7385
JL		 559 n = (difference & 0x80000000);
560 c = (reg1 > reg2);
561 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
562 && (reg2 & 0x80000000) != (difference & 0x80000000));
563
564 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
565 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
566 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
567}
568
569// 1111 1001 1011 1000 Rn Rn; inc Rn
5708.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
571"inc"
572*am33
573{
574 int dstreg;
575
576 PC = cia;
9c55817e 577 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 578 genericAdd (1, dstreg);
579}
580
581// 1111 1001 1101 1000 Rn Rn; inc Rn
5828.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
583"inc4"
584*am33
585{
586 int dstreg;
587
588 PC = cia;
9c55817e 589 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 590 State.regs[dstreg] += 4;
591}
592
593// 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
5948.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
595"cmp"
596*am33
597{
598 int srcreg1, srcreg2;
599
600 PC = cia;
9c55817e
JL		 601 srcreg1 = translate_rreg (SD_, RN0);
602 srcreg2 = translate_rreg (SD_, RM2);
0f7d7385
JL		 603 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
604}
605
606// 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
6078.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
608"mov"
609*am33
610{
6d254a2d 611 int dstreg, srcreg;
0f7d7385
JL		 612
613 PC = cia;
9c55817e 614 dstreg = translate_rreg (SD_, RN0);
6d254a2d 615 srcreg = translate_xreg (SD_, XRM2);
0f7d7385 616
6d254a2d 617 State.regs[dstreg] = State.regs[srcreg];
0f7d7385
JL		 618}
619
620// 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
6218.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
622"mov"
623*am33
624{
6d254a2d 625 int srcreg, dstreg;
0f7d7385
JL		 626
627 PC = cia;
9c55817e 628 srcreg = translate_rreg (SD_, RM2);
6d254a2d 629 dstreg = translate_xreg (SD_, XRN0);
0f7d7385 630
6d254a2d 631 State.regs[dstreg] = State.regs[srcreg];
0f7d7385
JL		 632}
633
634// 1111 1001 0000 1001 Rm Rn; and Rm,Rn
6358.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
636"and"
637*am33
638{
639 int srcreg, dstreg;
640 int z, n;
641
642 PC = cia;
643
9c55817e
JL		 644 srcreg = translate_rreg (SD_, RM2);
645 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 646
647 State.regs[dstreg] &= State.regs[srcreg];
648 z = (State.regs[dstreg] == 0);
649 n = (State.regs[dstreg] & 0x80000000) != 0;
650 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
651 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
652}
653
654// 1111 1001 0001 1001 Rm Rn; or Rm,Rn
6558.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
656"or"
657*am33
658{
659 int srcreg, dstreg;
660 int z, n;
661
662 PC = cia;
9c55817e
JL		 663 srcreg = translate_rreg (SD_, RM2);
664 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 665
666 State.regs[dstreg] |= State.regs[srcreg];
667 z = (State.regs[dstreg] == 0);
668 n = (State.regs[dstreg] & 0x80000000) != 0;
669 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
670 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
671}
672
673// 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
6748.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
675"xor"
676*am33
677{
678 int srcreg, dstreg;
679 int z, n;
680
681 PC = cia;
9c55817e
JL		 682 srcreg = translate_rreg (SD_, RM2);
683 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 684
685 State.regs[dstreg] ^= State.regs[srcreg];
686 z = (State.regs[dstreg] == 0);
687 n = (State.regs[dstreg] & 0x80000000) != 0;
688 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
689 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
690}
691
692// 1111 1001 0011 1001 Rn Rn; not Rn
6938.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
694"not"
695*am33
696{
697 int dstreg;
698 int z, n;
699
700 PC = cia;
9c55817e 701 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 702
703 State.regs[dstreg] = ~State.regs[dstreg];
704 z = (State.regs[dstreg] == 0);
705 n = (State.regs[dstreg] & 0x80000000) != 0;
706 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
707 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
708}
709
710// 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
7118.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
712"asr"
713*am33
714{
715 int srcreg, dstreg;
716 long temp;
717 int c, z, n;
718
719 PC = cia;
9c55817e
JL		 720 srcreg = translate_rreg (SD_, RM2);
721 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 722
723 temp = State.regs[dstreg];
724 c = temp & 1;
725 temp >>= State.regs[srcreg];
726 State.regs[dstreg] = temp;
727 z = (State.regs[dstreg] == 0);
728 n = (State.regs[dstreg] & 0x80000000) != 0;
729 PSW &= ~(PSW_Z | PSW_N | PSW_C);
730 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
731}
732
733// 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
7348.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
735"lsr"
736*am33
737{
738 int srcreg, dstreg;
739 int z, n, c;
740
741 PC = cia;
742
9c55817e
JL		 743 srcreg = translate_rreg (SD_, RM2);
744 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 745
746 c = State.regs[dstreg] & 1;
747 State.regs[dstreg] >>= State.regs[srcreg];
748 z = (State.regs[dstreg] == 0);
749 n = (State.regs[dstreg] & 0x80000000) != 0;
750 PSW &= ~(PSW_Z | PSW_N | PSW_C);
751 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
752}
753
754// 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
7558.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
756"asl"
757*am33
758{
759 int srcreg, dstreg;
760 int z, n;
761
762 PC = cia;
9c55817e
JL		 763 srcreg = translate_rreg (SD_, RM2);
764 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 765
766 State.regs[dstreg] <<= State.regs[srcreg];
767 z = (State.regs[dstreg] == 0);
768 n = (State.regs[dstreg] & 0x80000000) != 0;
769 PSW &= ~(PSW_Z | PSW_N);
770 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
771}
772
773// 1111 1001 0111 1001 Rn Rn; asl2 Rn
7748.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
775"asl2"
776*am33
777{
778 int dstreg;
779 int n, z;
780
781 PC = cia;
9c55817e 782 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 783
784 State.regs[dstreg] <<= 2;
785 z = (State.regs[dstreg] == 0);
786 n = (State.regs[dstreg] & 0x80000000) != 0;
787 PSW &= ~(PSW_Z | PSW_N);
788 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
789}
790
791// 1111 1001 1000 1001 Rn Rn; ror Rn
7928.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
793"ror"
794*am33
795{
796 int dstreg;
797 int c, n, z;
798 unsigned long value;
799
800 PC = cia;
9c55817e 801 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 802
803 value = State.regs[dstreg];
804 c = (value & 0x1);
805
806 value >>= 1;
807 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
808 State.regs[dstreg] = value;
809 z = (value == 0);
810 n = (value & 0x80000000) != 0;
811 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
812 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
813}
814
815// 1111 1001 1001 1001 Rn Rn; rol Rn
8168.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
817"rol"
818*am33
819{
820 int dstreg;
821 int c, n, z;
822 unsigned long value;
823
824 PC = cia;
9c55817e 825 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 826
827 value = State.regs[dstreg];
828 c = (value & 0x80000000) ? 1 : 0;
829
830 value <<= 1;
831 value |= ((PSW & PSW_C) != 0);
832 State.regs[dstreg] = value;
833 z = (value == 0);
834 n = (value & 0x80000000) != 0;
835 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
836 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
837}
838
839// 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
8408.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
841"mul"
842*am33
843{
844 int srcreg, dstreg;
845 unsigned long long temp;
846 int n, z;
847
848 PC = cia;
9c55817e
JL		 849 srcreg = translate_rreg (SD_, RM2);
850 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 851
852 temp = ((signed64)(signed32)State.regs[dstreg]
853 * (signed64)(signed32)State.regs[srcreg]);
854 State.regs[dstreg] = temp & 0xffffffff;
855 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
856 z = (State.regs[dstreg] == 0);
857 n = (State.regs[dstreg] & 0x80000000) != 0;
858 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
859 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
860}
861
862// 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
8638.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
864"mulu"
865*am33
866{
867 int srcreg, dstreg;
868 unsigned long long temp;
869 int n, z;
870
871 PC = cia;
9c55817e
JL		 872 srcreg = translate_rreg (SD_, RM2);
873 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 874
875 temp = ((unsigned64)State.regs[dstreg]
876 * (unsigned64)State.regs[srcreg]);
877 State.regs[dstreg] = temp & 0xffffffff;
878 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
879 z = (State.regs[dstreg] == 0);
880 n = (State.regs[dstreg] & 0x80000000) != 0;
881 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
882 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
883}
884
885// 1111 1001 1100 1001 Rm Rn; div Rm,Rn
8868.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
887"div"
888*am33
889{
890 int srcreg, dstreg;
377e53bb 891 long long temp;
0f7d7385
JL		 892 int n, z;
893
894 PC = cia;
9c55817e
JL		 895 srcreg = translate_rreg (SD_, RM2);
896 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 897
898 temp = State.regs[REG_MDR];
899 temp <<= 32;
900 temp |= State.regs[dstreg];
377e53bb 901 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
4e86afb8 902 temp /= (signed32)State.regs[srcreg];
0f7d7385
JL		 903 State.regs[dstreg] = temp & 0xffffffff;
904 z = (State.regs[dstreg] == 0);
905 n = (State.regs[dstreg] & 0x80000000) != 0;
906 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
907 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
908}
909
910// 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
9118.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
912"divu"
913*am33
914{
915 int srcreg, dstreg;
916 unsigned long long temp;
917 int n, z;
918
919 PC = cia;
9c55817e
JL		 920 srcreg = translate_rreg (SD_, RM2);
921 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 922
923 temp = State.regs[REG_MDR];
924 temp <<= 32;
925 temp |= State.regs[dstreg];
926 State.regs[REG_MDR] = temp % State.regs[srcreg];
927 temp /= State.regs[srcreg];
928 State.regs[dstreg] = temp & 0xffffffff;
929 z = (State.regs[dstreg] == 0);
930 n = (State.regs[dstreg] & 0x80000000) != 0;
931 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
932 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
933}
934
935
936// 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
3e75ff7e 9378.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
0f7d7385
JL		 938"mov"
939*am33
940{
941 int srcreg, dstreg;
942
943 PC = cia;
9c55817e
JL		 944 srcreg = translate_rreg (SD_, RM0);
945 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 946 State.regs[dstreg] = load_word (State.regs[srcreg]);
947}
948
949// 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
9508.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
951"mov"
952*am33
953{
954 int srcreg, dstreg;
955
956 PC = cia;
9c55817e
JL		 957 srcreg = translate_rreg (SD_, RM2);
958 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 959 store_word (State.regs[dstreg], State.regs[srcreg]);
960}
961
962// 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
3e75ff7e 9638.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
0f7d7385
JL		 964"movbu"
965*am33
966{
967 int srcreg, dstreg;
968
969 PC = cia;
9c55817e
JL		 970 srcreg = translate_rreg (SD_, RM0);
971 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 972 State.regs[dstreg] = load_byte (State.regs[srcreg]);
973}
974
975// 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
9768.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
977"movbu"
978*am33
979{
980 int srcreg, dstreg;
981
982 PC = cia;
9c55817e
JL		 983 srcreg = translate_rreg (SD_, RM2);
984 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 985 store_byte (State.regs[dstreg], State.regs[srcreg]);
986}
987
988// 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
3e75ff7e 9898.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
0f7d7385
JL		 990"movhu"
991*am33
992{
993 int srcreg, dstreg;
994
995 PC = cia;
9c55817e
JL		 996 srcreg = translate_rreg (SD_, RM0);
997 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 998 State.regs[dstreg] = load_half (State.regs[srcreg]);
999}
1000
1001// 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
10028.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
1003"movhu"
1004*am33
1005{
1006 int srcreg, dstreg;
1007
1008 PC = cia;
9c55817e
JL		 1009 srcreg = translate_rreg (SD_, RM2);
1010 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 1011 store_half (State.regs[dstreg], State.regs[srcreg]);
1012}
1013
377e53bb
JL		 1014// 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
10158.0xf9+8.0x6a+4.RN2,4.RM0:D1y:::mov
1016"mov"
1017*am33
1018{
1019 int srcreg, dstreg;
1020
1021 PC = cia;
9c55817e
JL		 1022 srcreg = translate_rreg (SD_, RM0);
1023 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1024 State.regs[dstreg] = load_word (State.regs[srcreg]);
1025 State.regs[srcreg] += 4;
1026}
1027
1028// 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
10298.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1030"mov"
1031*am33
1032{
1033 int srcreg, dstreg;
1034
1035 PC = cia;
9c55817e
JL		 1036 srcreg = translate_rreg (SD_, RM2);
1037 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1038 store_word (State.regs[dstreg], State.regs[srcreg]);
1039 State.regs[dstreg] += 4;
1040}
0f7d7385
JL		 1041
1042// 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
10438.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1044"mov"
1045*am33
1046{
9c55817e 1047 int dstreg;
0f7d7385
JL		 1048
1049 PC = cia;
9c55817e 1050 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 1051 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1052}
1053
1054// 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
10558.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1056"mov"
1057*am33
1058{
9c55817e 1059 int srcreg;
0f7d7385
JL		 1060
1061 PC = cia;
9c55817e
JL		 1062 srcreg = translate_rreg (SD_, RM2);
1063 store_word (State.regs[REG_SP], State.regs[srcreg]);
0f7d7385
JL		 1064}
1065
1066// 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
10678.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1068"movbu"
1069*am33
1070{
9c55817e 1071 int dstreg;
0f7d7385
JL		 1072
1073 PC = cia;
9c55817e 1074 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 1075 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1076}
1077
1078// 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
10798.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1080"movbu"
1081*am33
1082{
9c55817e 1083 int srcreg;
0f7d7385
JL		 1084
1085 PC = cia;
9c55817e
JL		 1086 srcreg = translate_rreg (SD_, RM2);
1087 store_byte (State.regs[REG_SP], State.regs[srcreg]);
0f7d7385
JL		 1088}
1089
1090// 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
10918.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1092"movhu"
1093*am33
1094{
9c55817e 1095 int dstreg;
0f7d7385
JL		 1096
1097 PC = cia;
9c55817e 1098 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 1099 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1100}
1101
1102// 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
11038.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1104"movhu"
1105*am33
1106{
9c55817e 1107 int srcreg;
0f7d7385
JL		 1108
1109 PC = cia;
9c55817e
JL		 1110 srcreg = translate_rreg (SD_, RM2);
1111 store_half (State.regs[REG_SP], State.regs[srcreg]);
0f7d7385
JL		 1112}
1113
377e53bb
JL		 1114// 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
11158.0xf9+8.0xea+4.RN2,4.RM0:D1y:::movhu
1116"movhu"
0f7d7385
JL		 1117*am33
1118{
377e53bb 1119 int srcreg, dstreg;
0f7d7385
JL		 1120
1121 PC = cia;
9c55817e
JL		 1122 srcreg = translate_rreg (SD_, RM0);
1123 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1124 State.regs[dstreg] = load_half (State.regs[srcreg]);
1125 State.regs[srcreg] += 2;
0f7d7385
JL		 1126}
1127
377e53bb
JL		 1128// 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
11298.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1130"movhu"
0f7d7385
JL		 1131*am33
1132{
377e53bb 1133 int srcreg, dstreg;
0f7d7385
JL		 1134
1135 PC = cia;
9c55817e
JL		 1136 srcreg = translate_rreg (SD_, RM2);
1137 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1138 store_half (State.regs[dstreg], State.regs[srcreg]);
1139 State.regs[dstreg] += 2;
0f7d7385
JL		 1140}
1141
377e53bb
JL		 1142
1143// 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
11448.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1145"mac"
0f7d7385
JL		 1146*am33
1147{
377e53bb
JL		 1148 int srcreg1, srcreg2;
1149 long long temp, sum;
1150 int c, v;
0f7d7385
JL		 1151
1152 PC = cia;
9c55817e
JL		 1153 srcreg1 = translate_rreg (SD_, RM2);
1154 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1155
4e86afb8
JL		 1156 temp = ((signed64)(signed32)State.regs[srcreg2]
1157 * (signed64)(signed32)State.regs[srcreg1]);
377e53bb
JL		 1158 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1159 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1160 State.regs[REG_MCRL] = sum;
1161 temp >>= 32;
1162 temp &= 0xffffffff;
1163 sum = State.regs[REG_MCRH] + temp + c;
1164 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1165 && (temp & 0x80000000) != (sum & 0x80000000));
1166 State.regs[REG_MCRH] = sum;
1167 if (v)
1168 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1169}
1170
377e53bb
JL		 1171// 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
11728.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1173"macu"
0f7d7385
JL		 1174*am33
1175{
377e53bb
JL		 1176 int srcreg1, srcreg2;
1177 unsigned long long temp, sum;
1178 int c, v;
0f7d7385
JL		 1179
1180 PC = cia;
9c55817e
JL		 1181 srcreg1 = translate_rreg (SD_, RM2);
1182 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1183
377e53bb
JL		 1184 temp = ((unsigned64)State.regs[srcreg2]
1185 * (unsigned64)State.regs[srcreg1]);
1186 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1187 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1188 State.regs[REG_MCRL] = sum;
1189 temp >>= 32;
1190 temp &= 0xffffffff;
1191 sum = State.regs[REG_MCRH] + temp + c;
1192 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1193 && (temp & 0x80000000) != (sum & 0x80000000));
1194 State.regs[REG_MCRH] = sum;
1195 if (v)
1196 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1197}
1198
377e53bb
JL		 1199// 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
12008.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1201"macb"
0f7d7385
JL		 1202*am33
1203{
377e53bb
JL		 1204 int srcreg1, srcreg2;
1205 long temp, sum;
1206 int v;
0f7d7385
JL		 1207
1208 PC = cia;
9c55817e
JL		 1209 srcreg1 = translate_rreg (SD_, RM2);
1210 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1211
4e86afb8
JL		 1212 temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
1213 * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
377e53bb
JL		 1214 sum = State.regs[REG_MCRL] + temp;
1215 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1216 && (temp & 0x80000000) != (sum & 0x80000000));
1217 State.regs[REG_MCRL] = sum;
1218 if (v)
1219 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1220}
1221
377e53bb
JL		 1222// 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
12238.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1224"macbu"
0f7d7385
JL		 1225*am33
1226{
377e53bb
JL		 1227 int srcreg1, srcreg2;
1228 long long temp, sum;
1229 int v;
0f7d7385
JL		 1230
1231 PC = cia;
9c55817e
JL		 1232 srcreg1 = translate_rreg (SD_, RM2);
1233 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1234
377e53bb
JL		 1235 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1236 * (unsigned32)(State.regs[srcreg1] & 0xff));
1237 sum = State.regs[REG_MCRL] + temp;
1238 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1239 && (temp & 0x80000000) != (sum & 0x80000000));
1240 State.regs[REG_MCRL] = sum;
1241 if (v)
1242 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1243}
1244
377e53bb
JL		 1245// 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
12468.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1247"mach"
0f7d7385
JL		 1248*am33
1249{
377e53bb
JL		 1250 int srcreg1, srcreg2;
1251 long long temp, sum;
1252 int c, v;
0f7d7385
JL		 1253
1254 PC = cia;
9c55817e
JL		 1255 srcreg1 = translate_rreg (SD_, RM2);
1256 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1257
4e86afb8
JL		 1258 temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
1259 * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
377e53bb
JL		 1260 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1261 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1262 State.regs[REG_MCRL] = sum;
1263 temp >>= 32;
1264 temp &= 0xffffffff;
1265 sum = State.regs[REG_MCRH] + temp + c;
1266 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1267 && (temp & 0x80000000) != (sum & 0x80000000));
1268 State.regs[REG_MCRH] = sum;
1269 if (v)
1270 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1271}
1272
377e53bb
JL		 1273// 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
12748.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1275"machu"
0f7d7385
JL		 1276*am33
1277{
377e53bb
JL		 1278 int srcreg1, srcreg2;
1279 long long temp, sum;
1280 int c, v;
0f7d7385
JL		 1281
1282 PC = cia;
9c55817e
JL		 1283 srcreg1 = translate_rreg (SD_, RM2);
1284 srcreg2 = translate_rreg (SD_, RN0);
377e53bb
JL		 1285
1286 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1287 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1288 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1289 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1290 State.regs[REG_MCRL] = sum;
1291 temp >>= 32;
1292 temp &= 0xffffffff;
1293 sum = State.regs[REG_MCRH] + temp + c;
1294 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1295 && (temp & 0x80000000) != (sum & 0x80000000));
1296 State.regs[REG_MCRH] = sum;
1297 if (v)
1298 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1299}
1300
377e53bb
JL		 1301// 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
13028.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1303"dmach"
0f7d7385
JL		 1304*am33
1305{
377e53bb
JL		 1306 int srcreg1, srcreg2;
1307 long temp, temp2, sum;
1308 int v;
0f7d7385
JL		 1309
1310 PC = cia;
9c55817e
JL		 1311 srcreg1 = translate_rreg (SD_, RM2);
1312 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1313
4e86afb8
JL		 1314 temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
1315 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
1316 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
1317 * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
377e53bb
JL		 1318 sum = temp + temp2 + State.regs[REG_MCRL];
1319 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1320 && (temp & 0x80000000) != (sum & 0x80000000));
1321 State.regs[REG_MCRL] = sum;
1322 if (v)
1323 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1324}
1325
377e53bb
JL		 1326// 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
13278.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1328"dmachu"
0f7d7385
JL		 1329*am33
1330{
377e53bb
JL		 1331 int srcreg1, srcreg2;
1332 unsigned long temp, temp2, sum;
1333 int v;
0f7d7385
JL		 1334
1335 PC = cia;
9c55817e
JL		 1336 srcreg1 = translate_rreg (SD_, RM2);
1337 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1338
377e53bb
JL		 1339 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1340 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1341 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1342 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1343 sum = temp + temp2 + State.regs[REG_MCRL];
1344 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1345 && (temp & 0x80000000) != (sum & 0x80000000));
1346 State.regs[REG_MCRL] = sum;
1347 if (v)
1348 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1349}
1350
377e53bb
JL		 1351// 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
13528.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1353"dmulh"
0f7d7385
JL		 1354*am33
1355{
377e53bb
JL		 1356 int srcreg, dstreg;
1357 long temp;
0f7d7385
JL		 1358
1359 PC = cia;
9c55817e
JL		 1360 srcreg = translate_rreg (SD_, RM2);
1361 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1362
4e86afb8
JL		 1363 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
1364 * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
377e53bb 1365 State.regs[REG_MDRQ] = temp;
4e86afb8
JL		 1366 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
1367 * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
377e53bb 1368 State.regs[dstreg] = temp;
0f7d7385
JL		 1369}
1370
377e53bb
JL		 1371// 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
13728.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1373"dmachu"
0f7d7385
JL		 1374*am33
1375{
377e53bb
JL		 1376 int srcreg, dstreg;
1377 unsigned long temp;
0f7d7385
JL		 1378
1379 PC = cia;
9c55817e
JL		 1380 srcreg = translate_rreg (SD_, RM2);
1381 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1382
377e53bb
JL		 1383 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1384 * (unsigned32)(State.regs[srcreg] & 0xffff));
1385 State.regs[REG_MDRQ] = temp;
1386 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1387 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
0f7d7385 1388 State.regs[dstreg] = temp;
0f7d7385
JL		 1389}
1390
377e53bb
JL		 1391// 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
13928.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1393"sat16"
0f7d7385
JL		 1394*am33
1395{
377e53bb 1396 int srcreg, dstreg;
4e86afb8 1397 int value, z, n;
0f7d7385
JL		 1398
1399 PC = cia;
9c55817e
JL		 1400 srcreg = translate_rreg (SD_, RM2);
1401 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1402
377e53bb
JL		 1403 value = State.regs[srcreg];
1404
1405 if (value >= 0x7fff)
1406 State.regs[dstreg] = 0x7fff;
1407 else if (value <= 0xffff8000)
1408 State.regs[dstreg] = 0xffff8000;
1409 else
1410 State.regs[dstreg] = value;
4e86afb8
JL		 1411
1412 n = (State.regs[dstreg] & 0x8000) != 0;
1413 z = (State.regs[dstreg] == 0);
1414 PSW &= ~(PSW_Z | PSW_N);
1415 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1416}
1417
1f0ba346
JL		 1418// 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
14198.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1420"mcste"
1421*am33
1422{
1423 int srcreg, dstreg;
1424
1425 PC = cia;
1426 srcreg = translate_rreg (SD_, RM2);
1427 dstreg = translate_rreg (SD_, RN0);
1428
1429 PSW &= ~(PSW_V | PSW_C);
1430 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1431
1432 /* 32bit saturation. */
1433 if (State.regs[srcreg] == 0x20)
1434 {
1435 long long tmp;
1436
1437 tmp = State.regs[REG_MCRH];
1438 tmp <<= 32;
1439 tmp += State.regs[REG_MCRL];
1440
1441 if (tmp > 0x7fffffff)
1442 State.regs[dstreg] = 0x7fffffff;
1443 else if (tmp < 0xffffffff80000000LL)
1444 State.regs[dstreg] = 0x80000000;
1445 else
1446 State.regs[dstreg] = tmp;
1447 }
1448 /* 16bit saturation */
1449 else if (State.regs[srcreg] == 0x10)
1450 {
1451 long long tmp;
1452
1453 tmp = State.regs[REG_MCRH];
1454 tmp <<= 32;
1455 tmp += State.regs[REG_MCRL];
1456
1457 if (tmp > 0x7fff)
1458 State.regs[dstreg] = 0x7fff;
1459 else if (tmp < 0xffffffffffff8000LL)
1460 State.regs[dstreg] = 0x8000;
1461 else
1462 State.regs[dstreg] = tmp;
1463 }
1464 /* 8 bit saturation */
1465 else if (State.regs[srcreg] == 0x8)
1466 {
1467 long long tmp;
1468
1469 tmp = State.regs[REG_MCRH];
1470 tmp <<= 32;
1471 tmp += State.regs[REG_MCRL];
1472
1473 if (tmp > 0x7f)
1474 State.regs[dstreg] = 0x7f;
1475 else if (tmp < 0xffffffffffffff80LL)
1476 State.regs[dstreg] = 0x80;
1477 else
1478 State.regs[dstreg] = tmp;
1479 }
1480 /* 9 bit saturation */
1481 else if (State.regs[srcreg] == 0x9)
1482 {
1483 long long tmp;
1484
1485 tmp = State.regs[REG_MCRH];
1486 tmp <<= 32;
1487 tmp += State.regs[REG_MCRL];
1488
1489 if (tmp > 0x80)
1490 State.regs[dstreg] = 0x80;
1491 else if (tmp < 0xffffffffffffff81LL)
1492 State.regs[dstreg] = 0x81;
1493 else
1494 State.regs[dstreg] = tmp;
1495 }
1496 /* 9 bit saturation */
1497 else if (State.regs[srcreg] == 0x30)
1498 {
1499 long long tmp;
1500
1501 tmp = State.regs[REG_MCRH];
1502 tmp <<= 32;
1503 tmp += State.regs[REG_MCRL];
1504
1505 if (tmp > 0x7fffffffffffLL)
1506 tmp = 0x7fffffffffffLL;
1507 else if (tmp < 0xffff800000000000LL)
1508 tmp = 0xffff800000000000LL;
1509
1510 tmp >>= 16;
1511 State.regs[dstreg] = tmp;
1512 }
1513}
377e53bb
JL		 1514
1515// 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
15168.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1517"swap"
0f7d7385
JL		 1518*am33
1519{
1520 int srcreg, dstreg;
0f7d7385 1521
9c55817e
JL		 1522 PC = cia;
1523 srcreg = translate_rreg (SD_, RM2);
1524 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1525
377e53bb
JL		 1526 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1527 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1528 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1529 | ((State.regs[srcreg] >> 24) & 0xff));
0f7d7385
JL		 1530}
1531
377e53bb
JL		 1532// 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
15338.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1534"swaph"
0f7d7385
JL		 1535*am33
1536{
377e53bb 1537 int srcreg, dstreg;
0f7d7385 1538
9c55817e
JL		 1539 PC = cia;
1540 srcreg = translate_rreg (SD_, RM2);
1541 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1542
377e53bb
JL		 1543 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1544 | ((State.regs[srcreg] >> 8) & 0xff)
1545 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1546 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
0f7d7385
JL		 1547}
1548
377e53bb
JL		 1549// 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
15508.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1551"swhw"
0f7d7385
JL		 1552*am33
1553{
377e53bb 1554 int srcreg, dstreg;
0f7d7385 1555
9c55817e
JL		 1556 PC = cia;
1557 srcreg = translate_rreg (SD_, RM2);
1558 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1559
377e53bb
JL		 1560 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1561 | ((State.regs[srcreg] >> 16) & 0xffff));
0f7d7385
JL		 1562}
1563
377e53bb
JL		 1564// 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
15658.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1566"bsch"
3e75ff7e
JL		 1567*am33
1568{
377e53bb
JL		 1569 int temp, c, i;
1570 int srcreg, dstreg;
1571 int start;
3e75ff7e
JL		 1572
1573 PC = cia;
9c55817e
JL		 1574 srcreg = translate_rreg (SD_, RM2);
1575 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1576
1577 temp = State.regs[srcreg];
1578 start = (State.regs[dstreg] & 0x1f) - 1;
1579 if (start == -1)
1580 start = 31;
1581
1582 for (i = start; i >= 0; i--)
1583 {
1584 if (temp & (1 << i))
1585 {
1586 c = 1;
1587 State.regs[dstreg] = i;
1588 break;
1589 }
1590 }
3e75ff7e 1591
377e53bb
JL		 1592 if (i < 0)
1593 {
1594 c = 0;
1595 State.regs[dstreg] = 0;
1596 }
1597 PSW &= ~(PSW_C);
1598 PSW |= (c ? PSW_C : 0);
3e75ff7e
JL		 1599}
1600
0f7d7385 1601
377e53bb
JL		 1602// 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
16038.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
0f7d7385 1604"mov"
3e75ff7e 1605*am33
0f7d7385 1606{
377e53bb 1607 int dstreg;
0f7d7385
JL		 1608
1609 PC = cia;
9c55817e 1610 dstreg = translate_rreg (SD_, RN0);
377e53bb 1611 State.regs[dstreg] = EXTEND8 (IMM8);
0f7d7385
JL		 1612}
1613
377e53bb
JL		 1614// 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
16158.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1616"movu"
1617*am33
0f7d7385 1618{
377e53bb 1619 int dstreg;
0f7d7385
JL		 1620
1621 PC = cia;
9c55817e 1622 dstreg = translate_rreg (SD_, RN0);
377e53bb 1623 State.regs[dstreg] = IMM8 & 0xff;
0f7d7385
JL		 1624}
1625
377e53bb
JL		 1626// 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
16278.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1628"add"
1629*am33
0f7d7385 1630{
377e53bb 1631 int dstreg;
0f7d7385
JL		 1632
1633 PC = cia;
9c55817e 1634 dstreg = translate_rreg (SD_, RN0);
377e53bb 1635 genericAdd (EXTEND8 (IMM8), dstreg);
0f7d7385
JL		 1636}
1637
377e53bb
JL		 1638// 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
16398.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1640"addc"
1641*am33
0f7d7385 1642{
377e53bb
JL		 1643 int dstreg, imm;
1644 int z, c, n, v;
1645 unsigned long reg1, reg2, sum;
0f7d7385
JL		 1646
1647 PC = cia;
9c55817e 1648 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1649
377e53bb
JL		 1650 imm = EXTEND8 (IMM8);
1651 reg2 = State.regs[dstreg];
1652 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1653 State.regs[dstreg] = sum;
1654
080ee2ba 1655 z = ((PSW & PSW_Z) != 0) && (sum == 0);
377e53bb
JL		 1656 n = (sum & 0x80000000);
1657 c = (sum < imm) || (sum < reg2);
1658 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1659 && (reg2 & 0x80000000) != (sum & 0x80000000));
1660
1661 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1662 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1663 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
0f7d7385
JL		 1664}
1665
377e53bb
JL		 1666// 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
16678.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1668"sub"
1669*am33
0f7d7385 1670{
377e53bb 1671 int dstreg;
0f7d7385
JL		 1672
1673 PC = cia;
9c55817e 1674 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1675
377e53bb 1676 genericSub (EXTEND8 (IMM8), dstreg);
0f7d7385
JL		 1677}
1678
377e53bb
JL		 1679// 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
16808.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1681"subc"
1682*am33
0f7d7385 1683{
377e53bb
JL		 1684 int imm, dstreg;
1685 int z, c, n, v;
1686 unsigned long reg1, reg2, difference;
0f7d7385
JL		 1687
1688 PC = cia;
9c55817e 1689 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1690
377e53bb
JL		 1691 imm = EXTEND8 (IMM8);
1692 reg2 = State.regs[dstreg];
1693 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1694 State.regs[dstreg] = difference;
0f7d7385 1695
080ee2ba 1696 z = ((PSW & PSW_Z) != 0) && (difference == 0);
377e53bb
JL		 1697 n = (difference & 0x80000000);
1698 c = (imm > reg2);
1699 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1700 && (reg2 & 0x80000000) != (difference & 0x80000000));
0f7d7385 1701
377e53bb
JL		 1702 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1703 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1704 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1705}
1706
1707// 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
17088.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1709"cmp"
1710*am33
0f7d7385 1711{
377e53bb 1712 int srcreg;
0f7d7385
JL		 1713
1714 PC = cia;
9c55817e 1715 srcreg = translate_rreg (SD_, RN0);
377e53bb 1716 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
0f7d7385
JL		 1717}
1718
377e53bb
JL		 1719// 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
17208.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
0f7d7385 1721"mov"
377e53bb 1722*am33
0f7d7385 1723{
377e53bb 1724 int dstreg;
0f7d7385
JL		 1725
1726 PC = cia;
6d254a2d 1727 dstreg = translate_xreg (SD_, XRN0);
0f7d7385 1728
6d254a2d 1729 State.regs[dstreg] = IMM8;
0f7d7385
JL		 1730}
1731
377e53bb
JL		 1732// 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
17338.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1734"and"
1735*am33
0f7d7385
JL		 1736{
1737 int dstreg;
377e53bb 1738 int z, n;
0f7d7385
JL		 1739
1740 PC = cia;
9c55817e 1741 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1742
377e53bb
JL		 1743 State.regs[dstreg] &= (IMM8 & 0xff);
1744 z = (State.regs[dstreg] == 0);
1745 n = (State.regs[dstreg] & 0x80000000) != 0;
1746 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1747 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1748}
1749
377e53bb
JL		 1750// 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
17518.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1752"or"
1753*am33
0f7d7385 1754{
377e53bb
JL		 1755 int dstreg;
1756 int z, n;
0f7d7385
JL		 1757
1758 PC = cia;
9c55817e 1759 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1760
377e53bb
JL		 1761 State.regs[dstreg] |= (IMM8 & 0xff);
1762 z = (State.regs[dstreg] == 0);
1763 n = (State.regs[dstreg] & 0x80000000) != 0;
1764 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1765 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1766}
1767
377e53bb
JL		 1768// 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
17698.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1770"xor"
1771*am33
0f7d7385
JL		 1772{
1773 int dstreg;
377e53bb 1774 int z, n;
0f7d7385
JL		 1775
1776 PC = cia;
9c55817e 1777 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1778
377e53bb
JL		 1779 State.regs[dstreg] ^= (IMM8 & 0xff);
1780 z = (State.regs[dstreg] == 0);
1781 n = (State.regs[dstreg] & 0x80000000) != 0;
1782 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1783 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1784}
1785
377e53bb
JL		 1786// 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
17878.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1788"asr"
1789*am33
0f7d7385 1790{
377e53bb
JL		 1791 int dstreg;
1792 long temp;
1793 int c, z, n;
0f7d7385
JL		 1794
1795 PC = cia;
9c55817e 1796 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1797
377e53bb
JL		 1798 temp = State.regs[dstreg];
1799 c = temp & 1;
1800 temp >>= (IMM8 & 0xff);
1801 State.regs[dstreg] = temp;
1802 z = (State.regs[dstreg] == 0);
1803 n = (State.regs[dstreg] & 0x80000000) != 0;
1804 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1805 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
0f7d7385
JL		 1806}
1807
377e53bb
JL		 1808// 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
18098.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1810"lsr"
1811*am33
1812{
1813 int dstreg;
1814 int z, n, c;
1815
1816 PC = cia;
9c55817e 1817 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1818
1819 c = State.regs[dstreg] & 1;
1820 State.regs[dstreg] >>= (IMM8 & 0xff);
1821 z = (State.regs[dstreg] == 0);
1822 n = (State.regs[dstreg] & 0x80000000) != 0;
1823 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1824 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1825}
1826
1827// 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
18288.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1829"asl"
1830*am33
1831{
1832 int srcreg, dstreg;
1833 int z, n;
1834
1835 PC = cia;
9c55817e 1836 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1837
1838 State.regs[dstreg] <<= (IMM8 & 0xff);
1839 z = (State.regs[dstreg] == 0);
1840 n = (State.regs[dstreg] & 0x80000000) != 0;
1841 PSW &= ~(PSW_Z | PSW_N);
1842 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1843}
1844
1845// 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
18468.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1847"mul"
1848*am33
1849{
1850 int dstreg;
1851 unsigned long long temp;
1852 int z, n;
1853
1854 PC = cia;
9c55817e 1855 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1856
1857 temp = ((signed64)(signed32)State.regs[dstreg]
1858 * (signed64)(signed32)EXTEND8 (IMM8));
1859 State.regs[dstreg] = temp & 0xffffffff;
1860 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1861 z = (State.regs[dstreg] == 0);
1862 n = (State.regs[dstreg] & 0x80000000) != 0;
1863 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1864 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1865}
1866
1867// 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
18688.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1869"mulu"
1870*am33
1871{
1872 int dstreg;
1873 unsigned long long temp;
1874 int z, n;
1875
1876 PC = cia;
9c55817e 1877 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1878
1879 temp = ((unsigned64)State.regs[dstreg]
1880 * (unsigned64)(IMM8 & 0xff));
1881 State.regs[dstreg] = temp & 0xffffffff;
1882 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1883 z = (State.regs[dstreg] == 0);
1884 n = (State.regs[dstreg] & 0x80000000) != 0;
1885 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1886 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1887}
1888
1889// 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
18908.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1891"btst"
1892*am33
1893{
1894 int srcreg;
1895
1896 PC = cia;
9c55817e 1897 srcreg = translate_rreg (SD_, RM0);
377e53bb 1898 genericBtst(IMM8, State.regs[srcreg]);
377e53bb
JL		 1899}
1900
377e53bb
JL		 1901// 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
19028.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1903"mov"
1904*am33
1905{
1906 int srcreg, dstreg;
1907
1908 PC = cia;
9c55817e
JL		 1909 srcreg = translate_rreg (SD_, RM0);
1910 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1911 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1912}
1913
1914// 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
19158.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1916"mov"
1917{
1918 int srcreg, dstreg;
1919
1920 PC = cia;
9c55817e
JL		 1921 srcreg = translate_rreg (SD_, RM2);
1922 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1923 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1924}
1925
1926// 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
19278.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1928"movbu"
1929{
1930 int srcreg, dstreg;
1931
1932 PC = cia;
9c55817e
JL		 1933 srcreg = translate_rreg (SD_, RM0);
1934 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1935 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1936}
1937
1938// 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
19398.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1940"movbu"
1941{
1942 int srcreg, dstreg;
1943
1944 PC = cia;
9c55817e
JL		 1945 srcreg = translate_rreg (SD_, RM2);
1946 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1947 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1948}
1949
1950// 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
19518.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1952"movhu"
1953{
1954 int srcreg, dstreg;
1955
1956 PC = cia;
9c55817e
JL		 1957 srcreg = translate_rreg (SD_, RM0);
1958 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1959 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1960}
1961
1962// 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
19638.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1964"movhu"
1965{
1966 int srcreg, dstreg;
1967
1968 PC = cia;
9c55817e
JL		 1969 srcreg = translate_rreg (SD_, RM2);
1970 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1971 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1972}
1973
1974// 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
19758.0xfb+8.0x6a+4.RN2,4.RM0+8.IMM8:D2y:::mov
1976"mov"
1977*am33
1978{
1979 int srcreg, dstreg;
1980
1981 PC = cia;
9c55817e
JL		 1982 srcreg = translate_rreg (SD_, RM0);
1983 dstreg = translate_rreg (SD_, RN2);
6ae1456e
JL		 1984 State.regs[dstreg] = load_word (State.regs[srcreg]);
1985 State.regs[srcreg] += EXTEND8 (IMM8);
377e53bb
JL		 1986}
1987
1988// 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
19898.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
1990"mov"
1991{
1992 int srcreg, dstreg;
1993
1994 PC = cia;
9c55817e
JL		 1995 srcreg = translate_rreg (SD_, RM2);
1996 dstreg = translate_rreg (SD_, RN0);
6ae1456e
JL		 1997 store_word (State.regs[dstreg], State.regs[srcreg]);
1998 State.regs[dstreg] += EXTEND8 (IMM8);
377e53bb
JL		 1999}
2000
2001
2002// 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
20038.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2004"mov"
2005{
2006 int dstreg;
2007
2008 PC = cia;
9c55817e 2009 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2010 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2011}
2012
2013// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
20148.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2015"mov"
2016{
2017 int srcreg;
2018
2019 PC = cia;
9c55817e 2020 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2021 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2022}
2023
2024// 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
20258.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2026"movbu"
2027{
2028 int dstreg;
2029
2030 PC = cia;
9c55817e 2031 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2032 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2033}
2034
2035// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
20368.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2037"movbu"
2038{
2039 int srcreg;
2040
2041 PC = cia;
9c55817e 2042 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2043 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2044}
2045
2046// 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
20478.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2048"movhu"
2049{
2050 int dstreg;
2051
2052 PC = cia;
9c55817e 2053 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2054 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2055}
2056
2057// 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
20588.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2059"movhu"
2060{
2061 int srcreg;
2062
2063 PC = cia;
9c55817e 2064 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2065 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2066}
2067
2068// 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
20698.0xfb+8.0xea+4.RN2,4.RM0+8.IMM8:D2y:::movhu
2070"movhu"
2071*am33
2072{
2073 int srcreg, dstreg;
2074
2075 PC = cia;
9c55817e
JL		 2076 srcreg = translate_rreg (SD_, RM0);
2077 dstreg = translate_rreg (SD_, RN2);
6ae1456e
JL		 2078 State.regs[dstreg] = load_half (State.regs[srcreg]);
2079 State.regs[srcreg] += EXTEND8 (IMM8);
377e53bb
JL		 2080}
2081
2082// 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
20838.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2084"movhu"
2085{
2086 int srcreg, dstreg;
2087
2088 PC = cia;
9c55817e
JL		 2089 srcreg = translate_rreg (SD_, RM2);
2090 dstreg = translate_rreg (SD_, RN0);
6ae1456e
JL		 2091 store_half (State.regs[dstreg], State.regs[srcreg]);
2092 State.regs[dstreg] += EXTEND8 (IMM8);
377e53bb
JL		 2093}
2094
2095
2096// 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
20978.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2098"mac"
2099{
9c55817e 2100 int srcreg;
377e53bb
JL		 2101 long long temp, sum;
2102 int c, v;
2103
2104 PC = cia;
9c55817e 2105 srcreg = translate_rreg (SD_, RN2);
377e53bb 2106
080ee2ba
JL		 2107 temp = ((signed64)(signed32)EXTEND8 (IMM8)
2108 * (signed64)(signed32)State.regs[srcreg]);
377e53bb
JL		 2109 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2110 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2111 State.regs[REG_MCRL] = sum;
2112 temp >>= 32;
2113 temp &= 0xffffffff;
2114 sum = State.regs[REG_MCRH] + temp + c;
2115 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2116 && (temp & 0x80000000) != (sum & 0x80000000));
2117 State.regs[REG_MCRH] = sum;
2118 if (v)
2119 State.regs[REG_MCVF] = 1;
2120}
2121
2122// 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
21238.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2124"macu"
2125{
9c55817e 2126 int srcreg;
377e53bb
JL		 2127 long long temp, sum;
2128 int c, v;
2129
2130 PC = cia;
9c55817e 2131 srcreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2132
2133 temp = ((unsigned64) (IMM8)
9c55817e 2134 * (unsigned64)State.regs[srcreg]);
377e53bb
JL		 2135 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2136 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2137 State.regs[REG_MCRL] = sum;
2138 temp >>= 32;
2139 temp &= 0xffffffff;
2140 sum = State.regs[REG_MCRH] + temp + c;
2141 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2142 && (temp & 0x80000000) != (sum & 0x80000000));
2143 State.regs[REG_MCRH] = sum;
2144 if (v)
2145 State.regs[REG_MCVF] = 1;
2146}
2147
2148// 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
21498.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2150"macb"
2151{
9c55817e 2152 int srcreg;
377e53bb
JL		 2153 long long temp, sum;
2154 int c, v;
2155
2156 PC = cia;
9c55817e 2157 srcreg = translate_rreg (SD_, RN2);
377e53bb 2158
080ee2ba
JL		 2159 temp = ((signed64)(signed8)EXTEND8 (IMM8)
2160 * (signed64)(signed8)State.regs[srcreg] & 0xff);
377e53bb
JL		 2161 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2162 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2163 State.regs[REG_MCRL] = sum;
2164 temp >>= 32;
2165 temp &= 0xffffffff;
2166 sum = State.regs[REG_MCRH] + temp + c;
2167 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2168 && (temp & 0x80000000) != (sum & 0x80000000));
2169 State.regs[REG_MCRH] = sum;
2170 if (v)
2171 State.regs[REG_MCVF] = 1;
2172}
2173
2174// 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
21758.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2176"macbu"
2177{
9c55817e 2178 int srcreg;
377e53bb
JL		 2179 long long temp, sum;
2180 int c, v;
2181
2182 PC = cia;
9c55817e 2183 srcreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2184
2185 temp = ((unsigned64) (IMM8)
9c55817e 2186 * (unsigned64)State.regs[srcreg] & 0xff);
377e53bb
JL		 2187 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2188 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2189 State.regs[REG_MCRL] = sum;
2190 temp >>= 32;
2191 temp &= 0xffffffff;
2192 sum = State.regs[REG_MCRH] + temp + c;
2193 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2194 && (temp & 0x80000000) != (sum & 0x80000000));
2195 State.regs[REG_MCRH] = sum;
2196 if (v)
2197 State.regs[REG_MCVF] = 1;
2198}
2199
2200// 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
22018.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2202"mach"
2203{
9c55817e 2204 int srcreg;
377e53bb
JL		 2205 long long temp, sum;
2206 int c, v;
2207
2208 PC = cia;
9c55817e 2209 srcreg = translate_rreg (SD_, RN2);
377e53bb 2210
080ee2ba
JL		 2211 temp = ((signed64)(signed16)EXTEND8 (IMM8)
2212 * (signed64)(signed16)State.regs[srcreg] & 0xffff);
377e53bb
JL		 2213 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2214 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2215 State.regs[REG_MCRL] = sum;
2216 temp >>= 32;
2217 temp &= 0xffffffff;
2218 sum = State.regs[REG_MCRH] + temp + c;
2219 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2220 && (temp & 0x80000000) != (sum & 0x80000000));
2221 State.regs[REG_MCRH] = sum;
2222 if (v)
2223 State.regs[REG_MCVF] = 1;
2224}
2225
2226// 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
22278.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2228"machu"
2229{
9c55817e 2230 int srcreg;
377e53bb
JL		 2231 long long temp, sum;
2232 int c, v;
2233
2234 PC = cia;
9c55817e 2235 srcreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2236
2237 temp = ((unsigned64) (IMM8)
9c55817e 2238 * (unsigned64)State.regs[srcreg] & 0xffff);
377e53bb
JL		 2239 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2240 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2241 State.regs[REG_MCRL] = sum;
2242 temp >>= 32;
2243 temp &= 0xffffffff;
2244 sum = State.regs[REG_MCRH] + temp + c;
2245 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2246 && (temp & 0x80000000) != (sum & 0x80000000));
2247 State.regs[REG_MCRH] = sum;
2248 if (v)
2249 State.regs[REG_MCVF] = 1;
2250}
2251
1f0ba346
JL		 2252// 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
22538.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2254"mcste"
2255{
2256 int dstreg;
2257
2258 PC = cia;
2259 dstreg = translate_rreg (SD_, RN0);
2260
2261 PSW &= ~(PSW_V | PSW_C);
2262 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2263
2264 /* 32bit saturation. */
2265 if (IMM8 == 0x20)
2266 {
2267 long long tmp;
2268
2269 tmp = State.regs[REG_MCRH];
2270 tmp <<= 32;
2271 tmp += State.regs[REG_MCRL];
2272
2273 if (tmp > 0x7fffffff)
2274 State.regs[dstreg] = 0x7fffffff;
2275 else if (tmp < 0xffffffff80000000LL)
2276 State.regs[dstreg] = 0x80000000;
2277 else
2278 State.regs[dstreg] = tmp;
2279 }
2280 /* 16bit saturation */
2281 else if (IMM8 == 0x10)
2282 {
2283 long long tmp;
2284
2285 tmp = State.regs[REG_MCRH];
2286 tmp <<= 32;
2287 tmp += State.regs[REG_MCRL];
2288
2289 if (tmp > 0x7fff)
2290 State.regs[dstreg] = 0x7fff;
2291 else if (tmp < 0xffffffffffff8000LL)
2292 State.regs[dstreg] = 0x8000;
2293 else
2294 State.regs[dstreg] = tmp;
2295 }
2296 /* 8 bit saturation */
2297 else if (IMM8 == 0x8)
2298 {
2299 long long tmp;
2300
2301 tmp = State.regs[REG_MCRH];
2302 tmp <<= 32;
2303 tmp += State.regs[REG_MCRL];
2304
2305 if (tmp > 0x7f)
2306 State.regs[dstreg] = 0x7f;
2307 else if (tmp < 0xffffffffffffff80LL)
2308 State.regs[dstreg] = 0x80;
2309 else
2310 State.regs[dstreg] = tmp;
2311 }
2312 /* 9 bit saturation */
2313 else if (IMM8 == 0x9)
2314 {
2315 long long tmp;
2316
2317 tmp = State.regs[REG_MCRH];
2318 tmp <<= 32;
2319 tmp += State.regs[REG_MCRL];
2320
2321 if (tmp > 0x80)
2322 State.regs[dstreg] = 0x80;
2323 else if (tmp < 0xffffffffffffff81LL)
2324 State.regs[dstreg] = 0x81;
2325 else
2326 State.regs[dstreg] = tmp;
2327 }
2328 /* 9 bit saturation */
2329 else if (IMM8 == 0x30)
2330 {
2331 long long tmp;
2332
2333 tmp = State.regs[REG_MCRH];
2334 tmp <<= 32;
2335 tmp += State.regs[REG_MCRL];
2336
2337 if (tmp > 0x7fffffffffffLL)
2338 tmp = 0x7fffffffffffLL;
2339 else if (tmp < 0xffff800000000000LL)
2340 tmp = 0xffff800000000000LL;
2341
2342 tmp >>= 16;
2343 State.regs[dstreg] = tmp;
2344 }
2345}
377e53bb 2346
0f7d7385
JL		 2347// 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
23488.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2349"add"
2350*am33
2351{
ee61616c 2352 int z, c, n, v;
377e53bb
JL		 2353 unsigned long sum, source1, source2;
2354 int srcreg1, srcreg2, dstreg;
2355
2356 PC = cia;
9c55817e
JL		 2357 srcreg1 = translate_rreg (SD_, RM2);
2358 srcreg2 = translate_rreg (SD_, RN0);
2359 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2360
2361 source1 = State.regs[srcreg1];
2362 source2 = State.regs[srcreg2];
2363 sum = source1 + source2;
2364 State.regs[dstreg] = sum;
2365
2366 z = (sum == 0);
2367 n = (sum & 0x80000000);
2368 c = (sum < source1) || (sum < source2);
2369 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2370 && (source1 & 0x80000000) != (sum & 0x80000000));
2371
2372 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2373 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2374 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2375}
2376
2377// 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
23788.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2379"addc"
2380*am33
2381{
2382 int z, c, n, v;
2383 unsigned long sum, source1, source2;
2384 int srcreg1, srcreg2, dstreg;
2385
2386 PC = cia;
9c55817e
JL		 2387 srcreg1 = translate_rreg (SD_, RM2);
2388 srcreg2 = translate_rreg (SD_, RN0);
2389 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2390
2391 source1 = State.regs[srcreg1];
2392 source2 = State.regs[srcreg2];
2393 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2394 State.regs[dstreg] = sum;
2395
080ee2ba 2396 z = ((PSW & PSW_Z) != 0) && (sum == 0);
377e53bb
JL		 2397 n = (sum & 0x80000000);
2398 c = (sum < source1) || (sum < source2);
2399 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2400 && (source1 & 0x80000000) != (sum & 0x80000000));
2401
2402 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2403 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2404 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2405}
2406
2407// 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
24088.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2409"sub"
2410*am33
2411{
2412 int z, c, n, v;
2413 unsigned long difference, source1, source2;
2414 int srcreg1, srcreg2, dstreg;
2415
2416 PC = cia;
9c55817e
JL		 2417 srcreg1 = translate_rreg (SD_, RM2);
2418 srcreg2 = translate_rreg (SD_, RN0);
2419 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2420
2421 source1 = State.regs[srcreg1];
2422 source2 = State.regs[srcreg2];
2423 difference = source2 - source1;
2424 State.regs[dstreg] = difference;
2425
2426 z = (difference == 0);
2427 n = (difference & 0x80000000);
2428 c = (source1 > source1);
2429 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2430 && (source1 & 0x80000000) != (difference & 0x80000000));
2431
2432 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2433 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2434 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2435}
2436
2437// 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
24388.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2439"subc"
2440*am33
2441{
2442 int z, c, n, v;
2443 unsigned long difference, source1, source2;
2444 int srcreg1, srcreg2, dstreg;
2445
2446 PC = cia;
9c55817e
JL		 2447 srcreg1 = translate_rreg (SD_, RM2);
2448 srcreg2 = translate_rreg (SD_, RN0);
2449 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2450
2451 source1 = State.regs[srcreg1];
2452 source2 = State.regs[srcreg2];
2453 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2454 State.regs[dstreg] = difference;
2455
080ee2ba 2456 z = ((PSW & PSW_Z) != 0) && (difference == 0);
377e53bb
JL		 2457 n = (difference & 0x80000000);
2458 c = (source1 > source2);
2459 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2460 && (source1 & 0x80000000) != (difference & 0x80000000));
2461
2462 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2463 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2464 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2465}
2466
2467// 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
24688.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2469"and"
2470*am33
2471{
080ee2ba 2472 int z, n;
377e53bb
JL		 2473 int srcreg1, srcreg2, dstreg;
2474
2475 PC = cia;
9c55817e
JL		 2476 srcreg1 = translate_rreg (SD_, RM2);
2477 srcreg2 = translate_rreg (SD_, RN0);
2478 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2479
2480 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2481
2482 z = (State.regs[dstreg] == 0);
2483 n = (State.regs[dstreg] & 0x80000000);
2484
2485 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2486 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2487}
2488
2489// 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
24908.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2491"or"
2492*am33
2493{
080ee2ba 2494 int z, n;
0f7d7385
JL		 2495 int srcreg1, srcreg2, dstreg;
2496
2497 PC = cia;
9c55817e
JL		 2498 srcreg1 = translate_rreg (SD_, RM2);
2499 srcreg2 = translate_rreg (SD_, RN0);
2500 dstreg = translate_rreg (SD_, RD0);
0f7d7385 2501
377e53bb 2502 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
ee61616c 2503
377e53bb
JL		 2504 z = (State.regs[dstreg] == 0);
2505 n = (State.regs[dstreg] & 0x80000000);
ee61616c
JL		 2506
2507 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
377e53bb 2508 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
0f7d7385
JL		 2509}
2510
377e53bb
JL		 2511// 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
25128.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2513"xor"
0f7d7385
JL		 2514*am33
2515{
080ee2ba 2516 int z, n;
3e75ff7e 2517 int srcreg1, srcreg2, dstreg;
0f7d7385
JL		 2518
2519 PC = cia;
9c55817e
JL		 2520 srcreg1 = translate_rreg (SD_, RM2);
2521 srcreg2 = translate_rreg (SD_, RN0);
2522 dstreg = translate_rreg (SD_, RD0);
3e75ff7e 2523
377e53bb 2524 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
3e75ff7e 2525
377e53bb
JL		 2526 z = (State.regs[dstreg] == 0);
2527 n = (State.regs[dstreg] & 0x80000000);
0f7d7385 2528
3e75ff7e 2529 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
377e53bb 2530 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
0f7d7385
JL		 2531}
2532
377e53bb
JL		 2533// 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
25348.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2535"asr"
0f7d7385
JL		 2536*am33
2537{
080ee2ba 2538 int z, c, n;
377e53bb 2539 long temp;
3e75ff7e 2540 int srcreg1, srcreg2, dstreg;
0f7d7385
JL		 2541
2542 PC = cia;
9c55817e
JL		 2543 srcreg1 = translate_rreg (SD_, RM2);
2544 srcreg2 = translate_rreg (SD_, RN0);
2545 dstreg = translate_rreg (SD_, RD0);
3e75ff7e 2546
377e53bb
JL		 2547 temp = State.regs[srcreg2];
2548 c = temp & 1;
2549 temp >>= State.regs[srcreg1];
2550 State.regs[dstreg] = temp;
3e75ff7e 2551
377e53bb
JL		 2552 z = (State.regs[dstreg] == 0);
2553 n = (State.regs[dstreg] & 0x80000000);
3e75ff7e 2554
377e53bb
JL		 2555 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2556 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
0f7d7385
JL		 2557}
2558
377e53bb
JL		 2559// 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
25608.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2561"lsr"
2562*am33
2563{
080ee2ba 2564 int z, c, n;
377e53bb
JL		 2565 int srcreg1, srcreg2, dstreg;
2566
2567 PC = cia;
9c55817e
JL		 2568 srcreg1 = translate_rreg (SD_, RM2);
2569 srcreg2 = translate_rreg (SD_, RN0);
2570 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2571
2572 c = State.regs[srcreg2] & 1;
2573 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2574
2575 z = (State.regs[dstreg] == 0);
2576 n = (State.regs[dstreg] & 0x80000000);
2577
2578 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2579 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2580}
2581
2582// 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
25838.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2584"asl"
2585*am33
2586{
080ee2ba 2587 int z, n;
377e53bb
JL		 2588 int srcreg1, srcreg2, dstreg;
2589
2590 PC = cia;
9c55817e
JL		 2591 srcreg1 = translate_rreg (SD_, RM2);
2592 srcreg2 = translate_rreg (SD_, RN0);
2593 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2594
2595 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
2596
2597 z = (State.regs[dstreg] == 0);
2598 n = (State.regs[dstreg] & 0x80000000);
2599
2600 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2601 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2602}
2603
2604// 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
26058.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mul
2606"mul"
2607*am33
2608{
2609 int srcreg1, srcreg2, dstreg1, dstreg2;
2610 signed long long temp;
0a785507 2611 int n, z;
377e53bb
JL		 2612
2613 PC = cia;
9c55817e
JL		 2614 srcreg1 = translate_rreg (SD_, RM2);
2615 srcreg2 = translate_rreg (SD_, RN0);
2616 dstreg1 = translate_rreg (SD_, RD0);
2617 dstreg2 = translate_rreg (SD_, RD2);
377e53bb
JL		 2618
2619 temp = ((signed64)(signed32)State.regs[srcreg1]
2620 * (signed64)(signed32)State.regs[srcreg2]);
2621 State.regs[dstreg1] = temp & 0xffffffff;
2622 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
0a785507
JL		 2623
2624 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2625 n = (State.regs[dstreg2] & 0x80000000);
2626
2627 PSW &= ~(PSW_Z | PSW_N);
2628 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
377e53bb
JL		 2629}
2630
2631// 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
26328.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mulu
2633"mulu"
2634*am33
2635{
2636 int srcreg1, srcreg2, dstreg1, dstreg2;
2637 signed long long temp;
0a785507 2638 int n, z;
377e53bb
JL		 2639
2640 PC = cia;
9c55817e
JL		 2641 srcreg1 = translate_rreg (SD_, RM2);
2642 srcreg2 = translate_rreg (SD_, RN0);
2643 dstreg1 = translate_rreg (SD_, RD0);
2644 dstreg2 = translate_rreg (SD_, RD2);
377e53bb 2645
080ee2ba
JL		 2646 temp = ((unsigned64)State.regs[srcreg1]
2647 * (unsigned64)State.regs[srcreg2]);
377e53bb
JL		 2648 State.regs[dstreg1] = temp & 0xffffffff;
2649 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
0a785507
JL		 2650
2651 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2652 n = (State.regs[dstreg2] & 0x80000000);
2653
2654 PSW &= ~(PSW_Z | PSW_N);
2655 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
377e53bb
JL		 2656}
2657
2658// 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
26598.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2660"mov"
2661*am33
2662{
2663 int dstreg;
2664
2665 PC = cia;
9c55817e 2666 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2667 State.regs[dstreg] = load_word (IMM8);
2668}
2669
2670// 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
26718.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2672"mov"
2673*am33
2674{
2675 int srcreg;
2676
9c55817e
JL		 2677 PC = cia;
2678 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2679 store_word (IMM8, State.regs[srcreg]);
2680}
2681
2682// 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
26838.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2684"movbu"
2685*am33
2686{
2687 int dstreg;
2688
2689 PC = cia;
9c55817e 2690 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2691 State.regs[dstreg] = load_byte (IMM8);
2692}
2693
2694// 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
26958.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2696"movbu"
0f7d7385
JL		 2697*am33
2698{
377e53bb 2699 int srcreg;
0f7d7385
JL		 2700
2701 PC = cia;
9c55817e 2702 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2703 store_byte (IMM8, State.regs[srcreg]);
2704}
0f7d7385 2705
377e53bb
JL		 2706// 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
27078.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2708"movhu"
2709*am33
2710{
2711 int dstreg;
2712
2713 PC = cia;
9c55817e 2714 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2715 State.regs[dstreg] = load_half (IMM8);
2716}
3e75ff7e 2717
377e53bb
JL		 2718// 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
27198.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2720"movhu"
2721*am33
2722{
2723 int srcreg;
3e75ff7e 2724
377e53bb 2725 PC = cia;
9c55817e 2726 srcreg = translate_rreg (SD_, RM2);
377e53bb 2727 store_half (IMM8, State.regs[srcreg]);
0f7d7385
JL		 2728}
2729
377e53bb
JL		 2730// 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
27318.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2732"mov"
0f7d7385
JL		 2733*am33
2734{
3e75ff7e 2735 int srcreg1, srcreg2, dstreg;
0f7d7385
JL		 2736
2737 PC = cia;
9c55817e
JL		 2738 srcreg1 = translate_rreg (SD_, RM0);
2739 srcreg1 = translate_rreg (SD_, RI0);
2740 dstreg = translate_rreg (SD_, RN0);
377e53bb 2741 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
3e75ff7e
JL		 2742}
2743
377e53bb
JL		 2744// 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
27458.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2746"mov"
3e75ff7e
JL		 2747*am33
2748{
377e53bb 2749 int srcreg, dstreg1, dstreg2;
3e75ff7e
JL		 2750
2751 PC = cia;
9c55817e
JL		 2752 srcreg = translate_rreg (SD_, RM0);
2753 dstreg1 = translate_rreg (SD_, RI0);
2754 dstreg2 = translate_rreg (SD_, RN0);
377e53bb 2755 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
3e75ff7e
JL		 2756}
2757
377e53bb
JL		 2758// 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
27598.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2760"movbu"
3e75ff7e
JL		 2761*am33
2762{
3e75ff7e
JL		 2763 int srcreg1, srcreg2, dstreg;
2764
2765 PC = cia;
9c55817e
JL		 2766 srcreg1 = translate_rreg (SD_, RM0);
2767 srcreg1 = translate_rreg (SD_, RI0);
2768 dstreg = translate_rreg (SD_, RN0);
377e53bb 2769 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
3e75ff7e
JL		 2770}
2771
377e53bb
JL		 2772// 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
27738.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2774"movbu"
3e75ff7e
JL		 2775*am33
2776{
377e53bb 2777 int srcreg, dstreg1, dstreg2;
3e75ff7e
JL		 2778
2779 PC = cia;
9c55817e
JL		 2780 srcreg = translate_rreg (SD_, RM0);
2781 dstreg1 = translate_rreg (SD_, RI0);
2782 dstreg2 = translate_rreg (SD_, RN0);
377e53bb 2783 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
3e75ff7e
JL		 2784}
2785
377e53bb
JL		 2786// 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
27878.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2788"movhu"
3e75ff7e
JL		 2789*am33
2790{
3e75ff7e
JL		 2791 int srcreg1, srcreg2, dstreg;
2792
9c55817e
JL		 2793 PC = cia;
2794 srcreg1 = translate_rreg (SD_, RM0);
2795 srcreg1 = translate_rreg (SD_, RI0);
2796 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 2797 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2798}
2799
2800// 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
28018.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2802"movhu"
2803*am33
2804{
2805 int srcreg, dstreg1, dstreg2;
2806
2807 PC = cia;
9c55817e
JL		 2808 srcreg = translate_rreg (SD_, RM0);
2809 dstreg1 = translate_rreg (SD_, RI0);
2810 dstreg2 = translate_rreg (SD_, RN0);
377e53bb 2811 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
3e75ff7e
JL		 2812}
2813
1f0ba346
JL		 2814// 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
28158.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mac
2816"mac"
2817*am33
2818{
2819 int srcreg1, srcreg2, dstreg1, dstreg2;
2820 signed long long temp;
2821 unsigned long sum;
2822 int c, v;
2823
2824 PC = cia;
2825 srcreg1 = translate_rreg (SD_, RM2);
2826 srcreg2 = translate_rreg (SD_, RN0);
2827 dstreg1 = translate_rreg (SD_, RD0);
2828 dstreg2 = translate_rreg (SD_, RD2);
2829
2830 temp = ((signed64)(signed32)State.regs[srcreg1]
2831 * (signed64)(signed32)State.regs[srcreg2]);
2832
2833 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2834 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2835 State.regs[dstreg2] = sum;
2836 temp >>= 32;
2837 temp &= 0xffffffff;
2838 sum = State.regs[dstreg1] + temp + c;
2839 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2840 && (temp & 0x80000000) != (sum & 0x80000000));
2841 State.regs[dstreg1] = sum;
2842 if (v)
0a785507
JL		 2843 {
2844 State.regs[REG_MCVF] = 1;
2845 PSW &= ~(PSW_V);
2846 PSW |= (( v ? PSW_V : 0));
2847 }
1f0ba346
JL		 2848}
2849
2850// 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
28518.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::macu
2852"macu"
2853*am33
2854{
2855 int srcreg1, srcreg2, dstreg1, dstreg2;
2856 signed long long temp;
2857 unsigned long sum;
2858 int c, v;
2859
2860 PC = cia;
2861 srcreg1 = translate_rreg (SD_, RM2);
2862 srcreg2 = translate_rreg (SD_, RN0);
2863 dstreg1 = translate_rreg (SD_, RD0);
2864 dstreg2 = translate_rreg (SD_, RD2);
2865
2866 temp = ((unsigned64)State.regs[srcreg1]
2867 * (unsigned64)State.regs[srcreg2]);
2868
2869 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2870 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2871 State.regs[dstreg2] = sum;
2872 temp >>= 32;
2873 temp &= 0xffffffff;
2874 sum = State.regs[dstreg1] + temp + c;
2875 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2876 && (temp & 0x80000000) != (sum & 0x80000000));
2877 State.regs[dstreg1] = sum;
2878 if (v)
0a785507
JL		 2879 {
2880 State.regs[REG_MCVF] = 1;
2881 PSW &= ~(PSW_V);
2882 PSW |= (( v ? PSW_V : 0));
2883 }
1f0ba346
JL		 2884}
2885
2886// 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
28878.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2888"macb"
2889*am33
2890{
2891 int srcreg1, srcreg2, dstreg;
2892 long temp, sum;
2893 int v;
2894
2895 PC = cia;
2896 srcreg1 = translate_rreg (SD_, RM2);
2897 srcreg2 = translate_rreg (SD_, RN0);
2898 dstreg = translate_rreg (SD_, RD0);
2899
2900 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2901 * (signed32)(State.regs[srcreg1] & 0xff));
2902 sum = State.regs[dstreg] + temp;
2903 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2904 && (temp & 0x80000000) != (sum & 0x80000000));
2905 State.regs[dstreg] = sum;
2906 if (v)
0a785507
JL		 2907 {
2908 State.regs[REG_MCVF] = 1;
2909 PSW &= ~(PSW_V);
2910 PSW |= ((v ? PSW_V : 0));
2911 }
1f0ba346
JL		 2912}
2913
2914// 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
29158.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2916"macbu"
2917*am33
2918{
2919 int srcreg1, srcreg2, dstreg;
2920 long temp, sum;
2921 int v;
2922
2923 PC = cia;
2924 srcreg1 = translate_rreg (SD_, RM2);
2925 srcreg2 = translate_rreg (SD_, RN0);
2926 dstreg = translate_rreg (SD_, RD0);
2927
2928 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2929 * (unsigned32)(State.regs[srcreg1] & 0xff));
2930 sum = State.regs[dstreg] + temp;
2931 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2932 && (temp & 0x80000000) != (sum & 0x80000000));
2933 State.regs[dstreg] = sum;
2934 if (v)
0a785507
JL		 2935 {
2936 State.regs[REG_MCVF] = 1;
2937 PSW &= ~(PSW_V);
2938 PSW |= ((v ? PSW_V : 0));
2939 }
1f0ba346
JL		 2940}
2941
2942// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1
29438.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::mach
2944"mach"
2945*am33
2946{
2947 int srcreg1, srcreg2, dstreg;
2948 long temp, sum;
2949 int v;
2950
2951 PC = cia;
2952 srcreg1 = translate_rreg (SD_, RM2);
2953 srcreg2 = translate_rreg (SD_, RN0);
2954 dstreg = translate_rreg (SD_, RD0);
2955
2956 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2957 * (signed32)(State.regs[srcreg1] & 0xffff));
2958 sum = State.regs[dstreg] + temp;
2959 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2960 && (temp & 0x80000000) != (sum & 0x80000000));
2961 State.regs[dstreg] = sum;
2962 if (v)
0a785507
JL		 2963 {
2964 State.regs[REG_MCVF] = 1;
2965 PSW &= ~(PSW_V);
2966 PSW |= ((v ? PSW_V : 0));
2967 }
1f0ba346
JL		 2968}
2969
2970// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1
29718.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::machu
2972"machu"
2973*am33
2974{
2975 int srcreg1, srcreg2, dstreg;
2976 long temp, sum;
2977 int v;
2978
2979 PC = cia;
2980 srcreg1 = translate_rreg (SD_, RM2);
2981 srcreg2 = translate_rreg (SD_, RN0);
2982 dstreg = translate_rreg (SD_, RD0);
2983
2984 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2985 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2986 sum = State.regs[dstreg] + temp;
2987 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2988 && (temp & 0x80000000) != (sum & 0x80000000));
2989 State.regs[dstreg] = sum;
2990 if (v)
0a785507
JL		 2991 {
2992 State.regs[REG_MCVF] = 1;
2993 PSW &= ~(PSW_V);
2994 PSW |= ((v ? PSW_V : 0));
2995 }
1f0ba346
JL		 2996}
2997
2998// 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
29998.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
3000"dmach"
3001*am33
3002{
3003 int srcreg1, srcreg2, dstreg;
3004 long temp, temp2, sum;
3005 int v;
3006
3007 PC = cia;
3008 srcreg1 = translate_rreg (SD_, RM2);
3009 srcreg2 = translate_rreg (SD_, RN0);
3010 dstreg = translate_rreg (SD_, RD0);
3011
3012 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
3013 * (signed32)(State.regs[srcreg1] & 0xffff));
3014 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3015 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
3016 sum = temp + temp2 + State.regs[dstreg];
3017 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3018 && (temp & 0x80000000) != (sum & 0x80000000));
3019 State.regs[dstreg] = sum;
3020 if (v)
0a785507
JL		 3021 {
3022 State.regs[REG_MCVF] = 1;
3023 PSW &= ~(PSW_V);
3024 PSW |= ((v ? PSW_V : 0));
3025 }
1f0ba346
JL		 3026}
3027
3028// 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
30298.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
3030"dmachu"
3031*am33
3032{
3033 int srcreg1, srcreg2, dstreg;
3034 long temp, temp2, sum;
3035 int v;
3036
3037 PC = cia;
3038 srcreg1 = translate_rreg (SD_, RM2);
3039 srcreg2 = translate_rreg (SD_, RN0);
3040 dstreg = translate_rreg (SD_, RD0);
3041
3042 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3043 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3044 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3045 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
3046 sum = temp + temp2 + State.regs[dstreg];
3047 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3048 && (temp & 0x80000000) != (sum & 0x80000000));
3049 State.regs[dstreg] = sum;
3050 if (v)
0a785507
JL		 3051 {
3052 State.regs[REG_MCVF] = 1;
3053 PSW &= ~(PSW_V);
3054 PSW |= ((v ? PSW_V : 0));
3055 }
1f0ba346
JL		 3056}
3057
3058// 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
30598.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulh
3060"dmulh"
3061*am33
3062{
3063 int srcreg1, srcreg2, dstreg1, dstreg2;
3064 signed long long temp;
3065
3066 PC = cia;
3067 srcreg1 = translate_rreg (SD_, RM2);
3068 srcreg2 = translate_rreg (SD_, RN0);
3069 dstreg1 = translate_rreg (SD_, RD0);
3070 dstreg2 = translate_rreg (SD_, RD2);
3071
3072 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3073 * (signed32)(State.regs[srcreg1] & 0xffff));
3074 State.regs[dstreg2] = temp;
3075 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3076 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3077 State.regs[dstreg1] = temp;
3078}
3079
3080// 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
30818.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulhu
3082"dmulhu"
3083*am33
3084{
3085 int srcreg1, srcreg2, dstreg1, dstreg2;
3086 signed long long temp;
3087
3088 PC = cia;
3089 srcreg1 = translate_rreg (SD_, RM2);
3090 srcreg2 = translate_rreg (SD_, RN0);
3091 dstreg1 = translate_rreg (SD_, RD0);
3092 dstreg2 = translate_rreg (SD_, RD2);
3093
3094 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3095 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3096 State.regs[dstreg2] = temp;
3097 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3098 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3099 State.regs[dstreg1] = temp;
3100}
377e53bb
JL		 3101
3102// 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
31038.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3104"sat24"
3e75ff7e
JL		 3105*am33
3106{
377e53bb 3107 int srcreg, dstreg;
0a785507 3108 int value, n, z;
3e75ff7e
JL		 3109
3110 PC = cia;
9c55817e
JL		 3111 srcreg = translate_rreg (SD_, RM2);
3112 dstreg = translate_rreg (SD_, RN0);
3e75ff7e 3113
377e53bb 3114 value = State.regs[srcreg];
3e75ff7e 3115
377e53bb
JL		 3116 if (value >= 0x7fffff)
3117 State.regs[dstreg] = 0x7fffff;
3118 else if (value <= 0xff800000)
3119 State.regs[dstreg] = 0xff800000;
3120 else
3121 State.regs[dstreg] = value;
0a785507
JL		 3122
3123 n = (State.regs[dstreg] & 0x800000) != 0;
3124 z = (State.regs[dstreg] == 0);
3125 PSW &= ~(PSW_Z | PSW_N);
3126 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3e75ff7e
JL		 3127}
3128
1f0ba346
JL		 3129// 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
31308.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3131"bsch"
3132*am33
3133{
3134 int temp, c, i;
3135 int srcreg1, srcreg2, dstreg;
3136 int start;
3137
3138 PC = cia;
3139 srcreg1 = translate_rreg (SD_, RM2);
3140 srcreg2 = translate_rreg (SD_, RN0);
3141 dstreg = translate_rreg (SD_, RD0);
3142
3143 temp = State.regs[srcreg1];
3144 start = (State.regs[srcreg2] & 0x1f) - 1;
3145 if (start == -1)
3146 start = 31;
3147
3148 for (i = start; i >= 0; i--)
3149 {
3150 if (temp & (1 << i))
3151 {
3152 c = 1;
3153 State.regs[dstreg] = i;
3154 break;
3155 }
3156 }
3157
3158 if (i < 0)
3159 {
3160 c = 0;
3161 State.regs[dstreg] = 0;
3162 }
3163 PSW &= ~(PSW_C);
3164 PSW |= (c ? PSW_C : 0);
3165}
3e75ff7e
JL		 3166
3167// 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
31688.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3169"mov"
3170*am33
3171{
3172 int dstreg;
3173
3174 PC = cia;
9c55817e 3175 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3176 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3177}
3178
3179// 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
31808.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3181"movu"
3182*am33
3183{
3184 int dstreg;
3185
3186 PC = cia;
9c55817e 3187 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3188 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3189}
3190
3191// 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
31928.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3193"add"
3194*am33
3195{
3196 int dstreg;
3197
3198 PC = cia;
9c55817e 3199 dstreg = translate_rreg (SD_, RN0);
4e86afb8 3200 genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3e75ff7e
JL		 3201}
3202
3203// 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
32048.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3205"addc"
3206*am33
3207{
3208 int dstreg, z, n, c, v;
3209 unsigned long sum, imm, reg2;
3210
3211 PC = cia;
9c55817e 3212 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3213
3214 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3215 reg2 = State.regs[dstreg];
3216 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3217 State.regs[dstreg] = sum;
3218
080ee2ba 3219 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3e75ff7e
JL		 3220 n = (sum & 0x80000000);
3221 c = (sum < imm) || (sum < reg2);
3222 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3223 && (reg2 & 0x80000000) != (sum & 0x80000000));
3224
3225 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3226 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3227 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3228}
3229
3230// 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
32318.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3232"sub"
3233*am33
3234{
3235 int dstreg;
3236
3237 PC = cia;
9c55817e 3238 dstreg = translate_rreg (SD_, RN0);
4e86afb8 3239 genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3e75ff7e
JL		 3240}
3241
3242// 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
32438.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3244"subc"
3245*am33
3246{
3247 int dstreg, z, n, c, v;
3248 unsigned long difference, imm, reg2;
3249
3250 PC = cia;
9c55817e 3251 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3252
3253 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3254 reg2 = State.regs[dstreg];
3255 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3256 State.regs[dstreg] = difference;
3257
080ee2ba 3258 z = ((PSW & PSW_Z) != 0) && (difference == 0);
3e75ff7e
JL		 3259 n = (difference & 0x80000000);
3260 c = (imm > reg2);
3261 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3262 && (reg2 & 0x80000000) != (difference & 0x80000000));
3263
3264 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3265 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3266 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3267}
3268
3269// 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
32708.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3271"cmp"
3272*am33
3273{
3274 int srcreg;
3275
3276 PC = cia;
9c55817e 3277 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3278 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3279}
3280
3281// 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
32828.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3283"mov"
3284*am33
3285{
6d254a2d
JL		 3286 int dstreg;
3287
3e75ff7e 3288 PC = cia;
6d254a2d 3289 dstreg = translate_xreg (SD_, XRN0);
3e75ff7e 3290
6d254a2d 3291 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3e75ff7e
JL		 3292}
3293
3294// 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
32958.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3296"and"
3297*am33
3298{
3299 int dstreg;
3300 int z,n;
3301
3302 PC = cia;
9c55817e 3303 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3304
3305 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3306 z = (State.regs[dstreg] == 0);
3307 n = (State.regs[dstreg] & 0x80000000) != 0;
3308 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3309 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3310}
3311
3312// 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
33138.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3314"or"
3315*am33
3316{
3317 int dstreg;
3318 int z,n;
3319
3320 PC = cia;
9c55817e 3321 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3322
3323 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3324 z = (State.regs[dstreg] == 0);
3325 n = (State.regs[dstreg] & 0x80000000) != 0;
3326 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3327 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3328}
3329
3330// 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
33318.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3332"xor"
3333*am33
3334{
3335 int dstreg;
3336 int z,n;
3337
3338 PC = cia;
9c55817e 3339 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3340
3341 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3342 z = (State.regs[dstreg] == 0);
3343 n = (State.regs[dstreg] & 0x80000000) != 0;
3344 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3345 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3346}
3347
3348// 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
33498.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3350"asr"
3351*am33
3352{
3353 int dstreg;
3354 long temp;
3355 int c, z, n;
3356
3357 PC = cia;
9c55817e 3358 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3359
3360 temp = State.regs[dstreg];
3361 c = temp & 1;
3362 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3363 State.regs[dstreg] = temp;
3364 z = (State.regs[dstreg] == 0);
3365 n = (State.regs[dstreg] & 0x80000000) != 0;
3366 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3367 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3368}
3369
3370
3371// 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
33728.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3373"lsr"
3374*am33
3375{
3376 int dstreg;
3377 int z, n, c;
3378
3379 PC = cia;
9c55817e 3380 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3381
3382 c = State.regs[dstreg] & 1;
3383 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3384 z = (State.regs[dstreg] == 0);
3385 n = (State.regs[dstreg] & 0x80000000) != 0;
3386 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3387 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3388}
3389
3390// 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
33918.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3392"asl"
3393*am33
3394{
3395 int srcreg, dstreg;
3396 int z, n;
3397
3398 PC = cia;
9c55817e 3399 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3400
3401 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3402 z = (State.regs[dstreg] == 0);
3403 n = (State.regs[dstreg] & 0x80000000) != 0;
3404 PSW &= ~(PSW_Z | PSW_N);
3405 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3406}
3407
1f0ba346
JL		 3408// 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
34098.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3410"mul"
3411*am33
3412{
3413 int dstreg;
3414 unsigned long long temp;
3415 int z, n;
3416
3417 PC = cia;
3418 dstreg = translate_rreg (SD_, RN0);
3419
3420 temp = ((signed64)(signed32)State.regs[dstreg]
0a785507 3421 * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
1f0ba346
JL		 3422 State.regs[dstreg] = temp & 0xffffffff;
3423 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3424 z = (State.regs[dstreg] == 0);
3425 n = (State.regs[dstreg] & 0x80000000) != 0;
3426 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3427 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3428}
3429
3430// 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
34318.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3432"mulu"
3433*am33
3434{
3435 int dstreg;
3436 unsigned long long temp;
3437 int z, n;
3438
3439 PC = cia;
3440 dstreg = translate_rreg (SD_, RN0);
3441
3442 temp = ((unsigned64)State.regs[dstreg]
0a785507 3443 * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
1f0ba346
JL		 3444 State.regs[dstreg] = temp & 0xffffffff;
3445 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3446 z = (State.regs[dstreg] == 0);
3447 n = (State.regs[dstreg] & 0x80000000) != 0;
3448 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3449 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3450}
3e75ff7e
JL		 3451
3452// 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
34538.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3454"btst"
3455*am33
3456{
3457 int srcreg;
3458
3459 PC = cia;
9c55817e 3460 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3461 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3462}
3463
3464// 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
34658.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3466"mov"
3467*am33
3468{
3469 int srcreg, dstreg;
3470
3471 PC = cia;
9c55817e
JL		 3472 srcreg = translate_rreg (SD_, RM0);
3473 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3474 State.regs[dstreg] = load_word (State.regs[srcreg]
080ee2ba
JL		 3475 + EXTEND24 (FETCH24 (IMM24A,
3476 IMM24B, IMM24C)));
3e75ff7e
JL		 3477}
3478
3479// 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
34808.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3481"mov"
3482*am33
3483{
3484 int srcreg, dstreg;
3485
3486 PC = cia;
9c55817e
JL		 3487 srcreg = translate_rreg (SD_, RM2);
3488 dstreg = translate_rreg (SD_, RN0);
080ee2ba 3489 store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3490 State.regs[srcreg]);
3491}
3492
3493// 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
34948.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3495"movbu"
3496*am33
3497{
3498 int srcreg, dstreg;
3499
3500 PC = cia;
9c55817e
JL		 3501 srcreg = translate_rreg (SD_, RM0);
3502 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3503 State.regs[dstreg] = load_byte (State.regs[srcreg]
080ee2ba
JL		 3504 + EXTEND24 (FETCH24 (IMM24A,
3505 IMM24B, IMM24C)));
3e75ff7e
JL		 3506}
3507
3508// 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
35098.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3510"movbu"
3511*am33
3512{
3513 int srcreg, dstreg;
3514
3515 PC = cia;
9c55817e
JL		 3516 srcreg = translate_rreg (SD_, RM2);
3517 dstreg = translate_rreg (SD_, RN0);
080ee2ba 3518 store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3519 State.regs[srcreg]);
3520}
3521
3522// 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
35238.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3524"movhu"
3525*am33
3526{
3527 int srcreg, dstreg;
3528
3529 PC = cia;
9c55817e
JL		 3530 srcreg = translate_rreg (SD_, RM0);
3531 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3532 State.regs[dstreg] = load_half (State.regs[srcreg]
080ee2ba
JL		 3533 + EXTEND24 (FETCH24 (IMM24A,
3534 IMM24B, IMM24C)));
3e75ff7e
JL		 3535}
3536
3537// 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
35388.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3539"movhu"
3540*am33
3541{
3542 int srcreg, dstreg;
3543
3544 PC = cia;
9c55817e
JL		 3545 srcreg = translate_rreg (SD_, RM2);
3546 dstreg = translate_rreg (SD_, RN0);
080ee2ba 3547 store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3548 State.regs[srcreg]);
3549}
3550
377e53bb
JL		 3551// 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
35528.0xfd+8.0x6a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3553"mov"
3554*am33
3555{
3556 int srcreg, dstreg;
3557
3558 PC = cia;
9c55817e
JL		 3559 srcreg = translate_rreg (SD_, RM0);
3560 dstreg = translate_rreg (SD_, RN2);
6ae1456e
JL		 3561 State.regs[dstreg] = load_word (State.regs[srcreg]);
3562 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
377e53bb
JL		 3563}
3564
3565// 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
35668.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3567"mov"
3568*am33
3569{
3570 int srcreg, dstreg;
3571
3572 PC = cia;
9c55817e
JL		 3573 srcreg = translate_rreg (SD_, RM2);
3574 dstreg = translate_rreg (SD_, RN0);
6ae1456e
JL		 3575 store_word (State.regs[dstreg], State.regs[srcreg]);
3576 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
377e53bb
JL		 3577}
3578
3e75ff7e
JL		 3579
3580// 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
35818.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3582"mov"
3583*am33
3584{
3585 int dstreg;
3586
3587 PC = cia;
9c55817e 3588 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3589 State.regs[dstreg] = load_word (State.regs[REG_SP]
080ee2ba
JL		 3590 + EXTEND24 (FETCH24 (IMM24A,
3591 IMM24B, IMM24C)));
3e75ff7e
JL		 3592}
3593
3594// 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
35958.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3596"mov"
3597*am33
3598{
3599 int srcreg;
3600
3601 PC = cia;
9c55817e 3602 srcreg = translate_rreg (SD_, RM2);
080ee2ba 3603 store_word (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3604 State.regs[srcreg]);
3605}
3606
3607// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
36088.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3609"movbu"
3610*am33
3611{
3612 int dstreg;
3613
3614 PC = cia;
9c55817e 3615 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3616 State.regs[dstreg] = load_byte (State.regs[REG_SP]
080ee2ba
JL		 3617 + EXTEND24 (FETCH24 (IMM24A,
3618 IMM24B, IMM24C)));
3e75ff7e
JL		 3619}
3620
3621// 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
36228.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3623"movbu"
3624*am33
3625{
3626 int srcreg;
3627
3628 PC = cia;
9c55817e 3629 srcreg = translate_rreg (SD_, RM2);
080ee2ba 3630 store_byte (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3631 State.regs[srcreg]);
3632}
3633
3634// 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
36358.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3636"movhu"
3637*am33
3638{
3639 int dstreg;
3640
3641 PC = cia;
9c55817e 3642 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3643 State.regs[dstreg] = load_half (State.regs[REG_SP]
080ee2ba
JL		 3644 + EXTEND24 (FETCH24 (IMM24A,
3645 IMM24B, IMM24C)));
3e75ff7e
JL		 3646}
3647
3648// 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
36498.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3650"movhu"
3651*am33
3652{
3653 int srcreg;
3654
3655 PC = cia;
9c55817e 3656 srcreg = translate_rreg (SD_, RM2);
080ee2ba 3657 store_half (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3658 State.regs[srcreg]);
3659}
3660
377e53bb
JL		 3661// 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
36628.0xfd+8.0xea+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3663"movhu"
3664*am33
3665{
3666 int srcreg, dstreg;
3667
3668 PC = cia;
9c55817e
JL		 3669 srcreg = translate_rreg (SD_, RM0);
3670 dstreg = translate_rreg (SD_, RN2);
6ae1456e
JL		 3671 State.regs[dstreg] = load_half (State.regs[srcreg]);
3672 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
377e53bb
JL		 3673}
3674
3675// 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
36768.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3677"movhu"
3678*am33
3679{
3680 int srcreg, dstreg;
3681
3682 PC = cia;
9c55817e
JL		 3683 srcreg = translate_rreg (SD_, RM2);
3684 dstreg = translate_rreg (SD_, RN0);
6ae1456e
JL		 3685 store_half (State.regs[dstreg], State.regs[srcreg]);
3686 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
377e53bb
JL		 3687}
3688
1f0ba346
JL		 3689// 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
36908.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3691"mac"
3692*am33
3693{
3694 int srcreg;
3695 long long temp, sum;
3696 int c, v;
3697
3698 PC = cia;
3699 srcreg = translate_rreg (SD_, RN2);
3700
0a785507 3701 temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
1f0ba346
JL		 3702 * (signed64)State.regs[srcreg]);
3703 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3704 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3705 State.regs[REG_MCRL] = sum;
3706 temp >>= 32;
3707 temp &= 0xffffffff;
3708 sum = State.regs[REG_MCRH] + temp + c;
3709 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3710 && (temp & 0x80000000) != (sum & 0x80000000));
3711 State.regs[REG_MCRH] = sum;
3712 if (v)
3713 State.regs[REG_MCVF] = 1;
3714}
3715
3716// 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
37178.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3718"macu"
3719*am33
3720{
3721 int srcreg;
3722 long long temp, sum;
3723 int c, v;
3724
3725 PC = cia;
3726 srcreg = translate_rreg (SD_, RN2);
3727
3728 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3729 * (unsigned64)State.regs[srcreg]);
3730 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3731 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3732 State.regs[REG_MCRL] = sum;
3733 temp >>= 32;
3734 temp &= 0xffffffff;
3735 sum = State.regs[REG_MCRH] + temp + c;
3736 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3737 && (temp & 0x80000000) != (sum & 0x80000000));
3738 State.regs[REG_MCRH] = sum;
3739 if (v)
3740 State.regs[REG_MCVF] = 1;
3741}
3742
3743// 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
37448.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3745"macb"
3746*am33
3747{
3748 int srcreg;
3749 long long temp, sum;
3750 int c, v;
3751
3752 PC = cia;
3753 srcreg = translate_rreg (SD_, RN2);
3754
3755 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3756 * (signed64)State.regs[srcreg] & 0xff);
3757 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3758 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3759 State.regs[REG_MCRL] = sum;
3760 temp >>= 32;
3761 temp &= 0xffffffff;
3762 sum = State.regs[REG_MCRH] + temp + c;
3763 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3764 && (temp & 0x80000000) != (sum & 0x80000000));
3765 State.regs[REG_MCRH] = sum;
3766 if (v)
3767 State.regs[REG_MCVF] = 1;
3768}
3769
3770// 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
37718.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3772"macbu"
3773*am33
3774{
3775 int srcreg;
3776 long long temp, sum;
3777 int c, v;
3778
3779 PC = cia;
3780 srcreg = translate_rreg (SD_, RN2);
3781
3782 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3783 * (unsigned64)State.regs[srcreg] & 0xff);
3784 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3785 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3786 State.regs[REG_MCRL] = sum;
3787 temp >>= 32;
3788 temp &= 0xffffffff;
3789 sum = State.regs[REG_MCRH] + temp + c;
3790 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3791 && (temp & 0x80000000) != (sum & 0x80000000));
3792 State.regs[REG_MCRH] = sum;
3793 if (v)
3794 State.regs[REG_MCVF] = 1;
3795}
3796
3797// 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
37988.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3799"mach"
3800*am33
3801{
3802 int srcreg;
3803 long long temp, sum;
3804 int c, v;
3805
3806 PC = cia;
3807 srcreg = translate_rreg (SD_, RN2);
3808
3809 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3810 * (signed64)State.regs[srcreg] & 0xffff);
3811 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3812 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3813 State.regs[REG_MCRL] = sum;
3814 temp >>= 32;
3815 temp &= 0xffffffff;
3816 sum = State.regs[REG_MCRH] + temp + c;
3817 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3818 && (temp & 0x80000000) != (sum & 0x80000000));
3819 State.regs[REG_MCRH] = sum;
3820 if (v)
3821 State.regs[REG_MCVF] = 1;
3822}
3823
3824// 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
38258.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3826"machu"
3827*am33
3828{
3829 int srcreg;
3830 long long temp, sum;
3831 int c, v;
3832
3833 PC = cia;
3834 srcreg = translate_rreg (SD_, RN2);
3835
3836 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3837 * (unsigned64)State.regs[srcreg] & 0xffff);
3838 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3839 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3840 State.regs[REG_MCRL] = sum;
3841 temp >>= 32;
3842 temp &= 0xffffffff;
3843 sum = State.regs[REG_MCRH] + temp + c;
3844 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3845 && (temp & 0x80000000) != (sum & 0x80000000));
3846 State.regs[REG_MCRH] = sum;
3847 if (v)
3848 State.regs[REG_MCVF] = 1;
3849}
3e75ff7e
JL		 3850
3851// 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
38528.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3853"mov"
3854*am33
3855{
3856 int dstreg;
3857
3858 PC = cia;
9c55817e 3859 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3860 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3861}
3862
3863// 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
38648.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3865"mov"
3866*am33
3867{
3868 int srcreg;
3869
3870 PC = cia;
9c55817e 3871 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 3872 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3873}
3874
3875
3876// 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
38778.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3878"movbu"
3879*am33
3880{
3881 int dstreg;
3882
3883 PC = cia;
9c55817e 3884 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3885 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3886}
3887
3888// 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
38898.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3890"movbu"
3891*am33
3892{
3893 int srcreg;
3894
3895 PC = cia;
9c55817e 3896 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 3897 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3898}
3899
3900
3901// 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
39028.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3903"movhu"
3904*am33
3905{
3906 int dstreg;
3907
3908 PC = cia;
9c55817e 3909 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3910 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3911}
3912
3913// 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
39148.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3915"movhu"
3916*am33
3917{
3918 int srcreg;
3919
3920 PC = cia;
9c55817e 3921 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 3922 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3923}
3924
3925
3926// 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
39278.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3928"mov"
3929*am33
3930{
3931 int dstreg;
3932
3933 PC = cia;
9c55817e 3934 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3935 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3936}
3937
3938// 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
39398.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3940"movu"
3941*am33
3942{
3943 int dstreg;
3944
3945 PC = cia;
9c55817e 3946 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3947 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3948}
3949
3950// 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
39518.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3952"add"
3953*am33
3954{
3955 int dstreg;
3956
3957 PC = cia;
9c55817e 3958 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3959 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3960}
3961
3962// 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
39638.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3964"addc"
3965*am33
3966{
3967 int dstreg;
3968 unsigned int imm, reg2, sum;
3969 int z, n, c, v;
3970
3971 PC = cia;
9c55817e 3972 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3973
3974 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3975 reg2 = State.regs[dstreg];
3976 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3977 State.regs[dstreg] = sum;
3978
080ee2ba 3979 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3e75ff7e
JL		 3980 n = (sum & 0x80000000);
3981 c = (sum < imm) || (sum < reg2);
3982 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3983 && (reg2 & 0x80000000) != (sum & 0x80000000));
3984
3985 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3986 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3987 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3988}
3989
3990// 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
39918.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
3992"sub"
3993*am33
3994{
3995 int dstreg;
3996
3997 PC = cia;
9c55817e 3998 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3999 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
4000}
4001
4002// 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
40038.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
4004"subc"
4005*am33
4006{
4007 int dstreg;
4008 unsigned int imm, reg2, difference;
4009 int z, n, c, v;
4010
4011 PC = cia;
9c55817e 4012 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4013
4014 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4015 reg2 = State.regs[dstreg];
4016 difference = reg2 - imm - ((PSW & PSW_C) != 0);
4017 State.regs[dstreg] = difference;
4018
080ee2ba 4019 z = ((PSW & PSW_Z) != 0) && (difference == 0);
3e75ff7e
JL		 4020 n = (difference & 0x80000000);
4021 c = (imm > reg2);
4022 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4023 && (reg2 & 0x80000000) != (difference & 0x80000000));
4024
4025 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4026 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4027 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4028}
4029
4030// 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
40318.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
4032"cmp"
4033*am33
4034{
4035 int srcreg;
4036
4037 PC = cia;
9c55817e 4038 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4039 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4040}
4041
4042// 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
40438.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
4044"mov"
4045*am33
4046{
6d254a2d
JL		 4047 int dstreg;
4048
3e75ff7e 4049 PC = cia;
6d254a2d 4050 dstreg = translate_xreg (SD_, XRN0);
3e75ff7e 4051
6d254a2d 4052 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3e75ff7e
JL		 4053}
4054
4055// 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
40568.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
4057"and"
4058*am33
4059{
4060 int dstreg;
4061 int z,n;
4062
4063 PC = cia;
9c55817e 4064 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4065
4066 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4067 z = (State.regs[dstreg] == 0);
4068 n = (State.regs[dstreg] & 0x80000000) != 0;
4069 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4070 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4071}
4072
4073// 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
40748.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4075"or"
4076*am33
4077{
4078 int dstreg;
4079 int z,n;
4080
4081 PC = cia;
9c55817e 4082 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4083
4084 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4085 z = (State.regs[dstreg] == 0);
4086 n = (State.regs[dstreg] & 0x80000000) != 0;
4087 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4088 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4089}
4090
4091// 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
40928.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4093"xor"
4094*am33
4095{
4096 int dstreg;
4097 int z,n;
4098
4099 PC = cia;
9c55817e 4100 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4101
4102 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4103 z = (State.regs[dstreg] == 0);
4104 n = (State.regs[dstreg] & 0x80000000) != 0;
4105 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4106 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4107}
4108
4109// 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
41108.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4111"asr"
4112*am33
4113{
4114 int dstreg;
4115 long temp;
4116 int c, z, n;
4117
4118 PC = cia;
9c55817e 4119 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4120
4121 temp = State.regs[dstreg];
4122 c = temp & 1;
4123 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4124 State.regs[dstreg] = temp;
4125 z = (State.regs[dstreg] == 0);
4126 n = (State.regs[dstreg] & 0x80000000) != 0;
4127 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4128 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4129}
4130
4131// 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
41328.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4133"lsr"
4134*am33
4135{
4136 int dstreg;
4137 int z, n, c;
4138
4139 PC = cia;
9c55817e 4140 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4141
4142 c = State.regs[dstreg] & 1;
4143 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4144 z = (State.regs[dstreg] == 0);
4145 n = (State.regs[dstreg] & 0x80000000) != 0;
4146 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4147 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4148}
4149
4150// 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
41518.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4152"asl"
4153*am33
4154{
4155 int srcreg, dstreg;
4156 int z, n;
4157
4158 PC = cia;
9c55817e 4159 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4160
4161 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4162 z = (State.regs[dstreg] == 0);
4163 n = (State.regs[dstreg] & 0x80000000) != 0;
4164 PSW &= ~(PSW_Z | PSW_N);
4165 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4166}
4167
0a785507
JL		 4168// 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
41698.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
4170"mul"
4171*am33
4172{
4173 int dstreg;
4174 unsigned long long temp;
4175 int z, n;
4176
4177 PC = cia;
4178 dstreg = translate_rreg (SD_, RN0);
4179
4180 temp = ((signed64)(signed32)State.regs[dstreg]
4181 * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4182 State.regs[dstreg] = temp & 0xffffffff;
4183 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
4184 z = (State.regs[dstreg] == 0);
4185 n = (State.regs[dstreg] & 0x80000000) != 0;
4186 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4187 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4188}
4189
4190// 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
41918.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
4192"mulu"
4193*am33
4194{
4195 int dstreg;
4196 unsigned long long temp;
4197 int z, n;
4198
4199 PC = cia;
4200 dstreg = translate_rreg (SD_, RN0);
4201
4202 temp = ((unsigned64)State.regs[dstreg]
4203 * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4204 State.regs[dstreg] = temp & 0xffffffff;
4205 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
4206 z = (State.regs[dstreg] == 0);
4207 n = (State.regs[dstreg] & 0x80000000) != 0;
4208 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4209 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4210}
3e75ff7e
JL		 4211
4212// 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
42138.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4214"btst"
4215*am33
4216{
4217 int srcreg;
4218
4219 PC = cia;
9c55817e 4220 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4221 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4222}
4223
4224// 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
42258.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4226"mov"
4227*am33
4228{
4229 int srcreg, dstreg;
4230
4231 PC = cia;
9c55817e
JL		 4232 srcreg = translate_rreg (SD_, RM0);
4233 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4234 State.regs[dstreg] = load_word (State.regs[srcreg]
4235 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4236}
4237
4238// 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
42398.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4240"mov"
4241*am33
4242{
4243 int srcreg, dstreg;
4244
4245 PC = cia;
9c55817e
JL		 4246 srcreg = translate_rreg (SD_, RM2);
4247 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4248 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4249 State.regs[srcreg]);
4250}
4251
4252// 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
42538.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4254"movbu"
4255*am33
4256{
4257 int srcreg, dstreg;
4258
4259 PC = cia;
9c55817e
JL		 4260 srcreg = translate_rreg (SD_, RM0);
4261 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4262 State.regs[dstreg] = load_byte (State.regs[srcreg]
4263 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4264}
4265
4266// 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
42678.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4268"movbu"
4269*am33
4270{
4271 int srcreg, dstreg;
4272
4273 PC = cia;
9c55817e
JL		 4274 srcreg = translate_rreg (SD_, RM2);
4275 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4276 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4277 State.regs[srcreg]);
0f7d7385
JL		 4278}
4279
3e75ff7e
JL		 4280// 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
42818.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4282"movhu"
0f7d7385
JL		 4283*am33
4284{
3e75ff7e
JL		 4285 int srcreg, dstreg;
4286
4287 PC = cia;
9c55817e
JL		 4288 srcreg = translate_rreg (SD_, RM0);
4289 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4290 State.regs[dstreg] = load_half (State.regs[srcreg]
4291 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4292}
4293
4294// 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
42958.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4296"movhu"
4297*am33
4298{
4299 int srcreg, dstreg;
0f7d7385
JL		 4300
4301 PC = cia;
9c55817e
JL		 4302 srcreg = translate_rreg (SD_, RM2);
4303 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4304 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4305 State.regs[srcreg]);
4306}
4307
377e53bb
JL		 4308// 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
43098.0xfe+8.0x6a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4310"mov"
4311*am33
4312{
4313 int srcreg, dstreg;
4314
4315 PC = cia;
9c55817e
JL		 4316 srcreg = translate_rreg (SD_, RM0);
4317 dstreg = translate_rreg (SD_, RN2);
6ae1456e 4318 State.regs[dstreg] = load_word (State.regs[srcreg]);
4b6651c9 4319 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
377e53bb
JL		 4320}
4321
4322// 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
43238.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4324"mov"
4325*am33
4326{
4327 int srcreg, dstreg;
4328
4329 PC = cia;
9c55817e
JL		 4330 srcreg = translate_rreg (SD_, RM2);
4331 dstreg = translate_rreg (SD_, RN0);
6ae1456e
JL		 4332 store_word (State.regs[dstreg], State.regs[srcreg]);
4333 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
377e53bb
JL		 4334}
4335
3e75ff7e
JL		 4336
4337// 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
43388.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4339"mov"
4340*am33
4341{
4342 int dstreg;
4343
4344 PC = cia;
9c55817e 4345 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4346 State.regs[dstreg] = load_word (State.regs[REG_SP]
4347 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4348}
4349
4350// 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
43518.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4352"mov"
4353*am33
4354{
4355 int srcreg;
4356
4357 PC = cia;
9c55817e 4358 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4359 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4360 State.regs[srcreg]);
4361}
4362
4363// 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
43648.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4365"movbu"
4366*am33
4367{
4368 int dstreg;
4369
4370 PC = cia;
9c55817e 4371 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4372 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4373 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4374}
4375
4376// 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
43778.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4378"movbu"
4379*am33
4380{
4381 int srcreg;
4382
4383 PC = cia;
9c55817e 4384 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4385 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4386 State.regs[srcreg]);
4387}
4388
4389// 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
43908.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4391"movhu"
4392*am33
4393{
4394 int dstreg;
4395
4396 PC = cia;
9c55817e 4397 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4398 State.regs[dstreg] = load_half (State.regs[REG_SP]
4399 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4400}
4401
4402// 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
44038.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4404"movhu"
4405*am33
4406{
4407 int srcreg;
4408
4409 PC = cia;
9c55817e 4410 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4411 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4412 State.regs[srcreg]);
4413}
4414
4415
377e53bb
JL		 4416// 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
44178.0xfe+8.0xea+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4418"movhu"
4419*am33
4420{
4421 int srcreg, dstreg;
4422
4423 PC = cia;
9c55817e
JL		 4424 srcreg = translate_rreg (SD_, RM0);
4425 dstreg = translate_rreg (SD_, RN2);
6ae1456e
JL		 4426 State.regs[dstreg] = load_half (State.regs[srcreg]);
4427 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
377e53bb
JL		 4428}
4429
4430// 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
44318.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4432"movhu"
4433*am33
4434{
4435 int srcreg, dstreg;
4436
4437 PC = cia;
9c55817e
JL		 4438 srcreg = translate_rreg (SD_, RM2);
4439 dstreg = translate_rreg (SD_, RN0);
6ae1456e
JL		 4440 store_half (State.regs[dstreg], State.regs[srcreg]);
4441 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
377e53bb
JL		 4442}
4443
3e75ff7e 4444
4b6651c9
JL		 4445// 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
44468.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
4447"mac"
4448*am33
4449{
4450 int srcreg, imm;
4451 long long temp, sum;
4452 int c, v;
4453
4454 PC = cia;
4455 srcreg = translate_rreg (SD_, RN0);
4456 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4457
4458 temp = ((signed64)(signed32)State.regs[srcreg]
4459 * (signed64)(signed32)imm);
4460 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4461 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4462 State.regs[REG_MCRL] = sum;
4463 temp >>= 32;
4464 temp &= 0xffffffff;
4465 sum = State.regs[REG_MCRH] + temp + c;
4466 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4467 && (temp & 0x80000000) != (sum & 0x80000000));
4468 State.regs[REG_MCRH] = sum;
4469 if (v)
4470 State.regs[REG_MCVF] = 1;
4471}
4472
4473// 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
44748.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
4475"macu"
4476*am33
4477{
4478 int srcreg, imm;
4479 long long temp, sum;
4480 int c, v;
4481
4482 PC = cia;
4483 srcreg = translate_rreg (SD_, RN0);
4484 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4485
4486 temp = ((unsigned64)State.regs[srcreg]
4487 * (unsigned64)imm);
4488 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4489 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4490 State.regs[REG_MCRL] = sum;
4491 temp >>= 32;
4492 temp &= 0xffffffff;
4493 sum = State.regs[REG_MCRH] + temp + c;
4494 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4495 && (temp & 0x80000000) != (sum & 0x80000000));
4496 State.regs[REG_MCRH] = sum;
4497 if (v)
4498 State.regs[REG_MCVF] = 1;
4499}
4500
4501// 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
45028.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
4503"macb"
4504*am33
4505{
4506 int srcreg, imm;
4507 long temp, sum;
4508 int v;
4509
4510 PC = cia;
4511 srcreg = translate_rreg (SD_, RN0);
4512 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4513
4514 temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
4515 * (signed32)(signed8)(imm & 0xff));
4516 sum = State.regs[REG_MCRL] + temp;
4517 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4518 && (temp & 0x80000000) != (sum & 0x80000000));
4519 State.regs[REG_MCRL] = sum;
4520 if (v)
4521 State.regs[REG_MCVF] = 1;
4522}
4523
4524// 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
45258.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
4526"macbu"
4527*am33
4528{
4529 int srcreg, imm;
4530 long temp, sum;
4531 int v;
4532
4533 PC = cia;
4534 srcreg = translate_rreg (SD_, RN0);
4535 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4536
4537 temp = ((unsigned32)(State.regs[srcreg] & 0xff)
4538 * (unsigned32)(imm & 0xff));
4539 sum = State.regs[REG_MCRL] + temp;
4540 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4541 && (temp & 0x80000000) != (sum & 0x80000000));
4542 State.regs[REG_MCRL] = sum;
4543 if (v)
4544 State.regs[REG_MCVF] = 1;
4545}
4546
4547// 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
45488.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
4549"mach"
4550*am33
4551{
4552 int srcreg, imm;
4553 long temp, sum;
4554 int v;
4555
4556 PC = cia;
4557 srcreg = translate_rreg (SD_, RN0);
4558 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4559
4560 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4561 * (signed32)(signed16)(imm & 0xffff));
4562 sum = State.regs[REG_MCRL] + temp;
4563 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4564 && (temp & 0x80000000) != (sum & 0x80000000));
4565 State.regs[REG_MCRL] = sum;
4566 if (v)
4567 State.regs[REG_MCVF] = 1;
4568}
4569
4570// 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
45718.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
4572"machu"
4573*am33
4574{
4575 int srcreg, imm;
4576 long temp, sum;
4577 int v;
4578
4579 PC = cia;
4580 srcreg = translate_rreg (SD_, RN0);
4581 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4582
4583 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4584 * (unsigned32)(imm & 0xffff));
4585 sum = State.regs[REG_MCRL] + temp;
4586 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4587 && (temp & 0x80000000) != (sum & 0x80000000));
4588 State.regs[REG_MCRL] = sum;
4589 if (v)
4590 State.regs[REG_MCVF] = 1;
4591}
4592
4593// 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
45948.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
4595"dmach"
4596*am33
4597{
4598 int srcreg, imm;
4599 long temp, temp2, sum;
4600 int v;
4601
4602 PC = cia;
4603 srcreg = translate_rreg (SD_, RN0);
4604 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4605
4606 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4607 * (signed32)(signed16)(imm & 0xffff));
4608 temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
4609 * (signed32)(signed16)((imm >> 16) & 0xffff));
4610 sum = temp + temp2 + State.regs[REG_MCRL];
4611 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4612 && (temp & 0x80000000) != (sum & 0x80000000));
4613 State.regs[REG_MCRL] = sum;
4614 if (v)
4615 State.regs[REG_MCVF] = 1;
4616}
4617
4618// 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
46198.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
4620"dmachu"
4621*am33
4622{
4623 int srcreg, imm;
4624 long temp, temp2, sum;
4625 int v;
4626
4627 PC = cia;
4628 srcreg = translate_rreg (SD_, RN0);
4629 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4630
4631 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4632 * (unsigned32)(imm & 0xffff));
4633 temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
4634 * (unsigned32)((imm >> 16) & 0xffff));
4635 sum = temp + temp2 + State.regs[REG_MCRL];
4636 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4637 && (temp & 0x80000000) != (sum & 0x80000000));
4638 State.regs[REG_MCRL] = sum;
4639 if (v)
4640 State.regs[REG_MCVF] = 1;
4641}
4642
4643// 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
46448.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
4645"dmulh"
4646*am33
4647{
4648 int imm, dstreg;
4649 long temp;
4650
4651 PC = cia;
4652 dstreg = translate_rreg (SD_, RN0);
4653 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4654
4655 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
4656 * (signed32)(signed16)(imm & 0xffff));
4657 State.regs[REG_MDRQ] = temp;
4658 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
4659 * (signed32)(signed16)((imm>>16) & 0xffff));
4660 State.regs[dstreg] = temp;
4661}
4662
4663// 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
46648.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
4665"dmulhu"
4666*am33
4667{
4668 int imm, dstreg;
4669 long temp;
4670
4671 PC = cia;
4672 dstreg = translate_rreg (SD_, RN0);
4673 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4674
4675 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
4676 * (unsigned32)(imm & 0xffff));
4677 State.regs[REG_MDRQ] = temp;
4678 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
4679 * (unsigned32)((imm >>16) & 0xffff));
4680 State.regs[dstreg] = temp;
4681}
3e75ff7e
JL		 4682
4683// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
46848.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4685"mov"
4686*am33
4687{
4688 int dstreg;
4689
4690 PC = cia;
9c55817e 4691 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4692 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4693}
4694
4695// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
46968.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4697"mov"
4698*am33
4699{
4700 int srcreg;
4701
4702 PC = cia;
9c55817e 4703 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4704 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4705}
4706
4707// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
47088.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4709"movbu"
4710*am33
4711{
4712 int dstreg;
4713
4714 PC = cia;
9c55817e 4715 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4716 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4717}
4718
4719// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
47208.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4721"movbu"
4722*am33
4723{
4724 int srcreg;
4725
4726 PC = cia;
9c55817e 4727 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4728 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4729}
4730
4731// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
47328.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4733"movhu"
4734*am33
4735{
4736 int dstreg;
4737
4738 PC = cia;
9c55817e 4739 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4740 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4741}
4742
4743// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
47448.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4745"movhu"
4746*am33
4747{
4748 int srcreg;
4749
4750 PC = cia;
9c55817e 4751 srcreg = translate_rreg (SD_, RM2);
3e75ff7e 4752 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
0f7d7385
JL		 4753}
4754
0a785507
JL		 4755// 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
47568.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_add
4757"add_add"
4758*am33
4759{
4760 int srcreg1, srcreg2, dstreg1, dstreg2;
4761
4762 PC = cia;
4763 srcreg1 = translate_rreg (SD_, RM1);
4764 srcreg2 = translate_rreg (SD_, RM2);
4765 dstreg1 = translate_rreg (SD_, RN1);
4766 dstreg2 = translate_rreg (SD_, RN2);
4767
4768 State.regs[dstreg1] += State.regs[srcreg1];
4769 State.regs[dstreg2] += State.regs[srcreg2];
4770}
4771
4772// 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
47738.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_add
4774"add_add"
4775*am33
4776{
4777 int srcreg1, dstreg1, dstreg2;
4778
4779 PC = cia;
4780 srcreg1 = translate_rreg (SD_, RM1);
4781 dstreg1 = translate_rreg (SD_, RN1);
4782 dstreg2 = translate_rreg (SD_, RN2);
4783
4784 State.regs[dstreg1] += State.regs[srcreg1];
4785 State.regs[dstreg2] += EXTEND4 (IMM4);
4786}
4787
4788// 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
47898.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_sub
4790"add_sub"
4791*am33
4792{
4793 int srcreg1, srcreg2, dstreg1, dstreg2;
4794
4795 PC = cia;
4796 srcreg1 = translate_rreg (SD_, RM1);
4797 srcreg2 = translate_rreg (SD_, RM2);
4798 dstreg1 = translate_rreg (SD_, RN1);
4799 dstreg2 = translate_rreg (SD_, RN2);
4800
4801 State.regs[dstreg1] += State.regs[srcreg1];
4802 State.regs[dstreg2] -= State.regs[srcreg2];
4803}
4804
4805// 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
48068.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_sub
4807"add_sub"
4808*am33
4809{
4810 int srcreg1, dstreg1, dstreg2;
4811
4812 PC = cia;
4813 srcreg1 = translate_rreg (SD_, RM1);
4814 dstreg1 = translate_rreg (SD_, RN1);
4815 dstreg2 = translate_rreg (SD_, RN2);
4816
4817 State.regs[dstreg1] += State.regs[srcreg1];
4818 State.regs[dstreg2] -= EXTEND4 (IMM4);
4819}
4820
4821// 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
48228.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_cmp
4823"add_cmp"
4824*am33
4825{
4826 int srcreg1, srcreg2, dstreg1, dstreg2;
4827
4828 PC = cia;
4829 srcreg1 = translate_rreg (SD_, RM1);
4830 srcreg2 = translate_rreg (SD_, RM2);
4831 dstreg1 = translate_rreg (SD_, RN1);
4832 dstreg2 = translate_rreg (SD_, RN2);
4833
4834 State.regs[dstreg1] += State.regs[srcreg1];
4835 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
4836}
4837
4838// 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
48398.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_cmp
4840"add_cmp"
4841*am33
4842{
4843 int srcreg1, dstreg1, dstreg2;
4844
4845 PC = cia;
4846 srcreg1 = translate_rreg (SD_, RM1);
4847 dstreg1 = translate_rreg (SD_, RN1);
4848 dstreg2 = translate_rreg (SD_, RN2);
4849
4850 State.regs[dstreg1] += State.regs[srcreg1];
4851 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
4852}
4853
4854// 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
48558.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_mov
4856"add_mov"
4857*am33
4858{
4859 int srcreg1, srcreg2, dstreg1, dstreg2;
4860
4861 PC = cia;
4862 srcreg1 = translate_rreg (SD_, RM1);
4863 srcreg2 = translate_rreg (SD_, RM2);
4864 dstreg1 = translate_rreg (SD_, RN1);
4865 dstreg2 = translate_rreg (SD_, RN2);
4866
4867 State.regs[dstreg1] += State.regs[srcreg1];
4868 State.regs[dstreg2] = State.regs[srcreg2];
4869}
4870
4871// 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
48728.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_mov
4873"add_mov"
4874*am33
4875{
4876 int srcreg1, dstreg1, dstreg2;
4877
4878 PC = cia;
4879 srcreg1 = translate_rreg (SD_, RM1);
4880 dstreg1 = translate_rreg (SD_, RN1);
4881 dstreg2 = translate_rreg (SD_, RN2);
4882
4883 State.regs[dstreg1] += State.regs[srcreg1];
4884 State.regs[dstreg2] = EXTEND4 (IMM4);
4885}
4886
4887// 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
48888.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asr
4889"add_asr"
4890*am33
4891{
4892 int srcreg1, srcreg2, dstreg1, dstreg2;
4893 signed int temp;
4894
4895 PC = cia;
4896 srcreg1 = translate_rreg (SD_, RM1);
4897 srcreg2 = translate_rreg (SD_, RM2);
4898 dstreg1 = translate_rreg (SD_, RN1);
4899 dstreg2 = translate_rreg (SD_, RN2);
4900
4901 State.regs[dstreg1] += State.regs[srcreg1];
4902 temp = State.regs[dstreg2];
4903 temp >>= State.regs[srcreg2];
4904 State.regs[dstreg2] = temp;
4905}
4906
4907// 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
49088.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asr
4909"add_asr"
4910*am33
4911{
4912 int srcreg1, dstreg1, dstreg2;
4913 signed int temp;
4914
4915 PC = cia;
4916 srcreg1 = translate_rreg (SD_, RM1);
4917 dstreg1 = translate_rreg (SD_, RN1);
4918 dstreg2 = translate_rreg (SD_, RN2);
4919
4920 State.regs[dstreg1] += State.regs[srcreg1];
4921 temp = State.regs[dstreg2];
4922 temp >>= IMM4;
4923 State.regs[dstreg2] = temp;
4924}
4925
4926// 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
49278.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_lsr
4928"add_lsr"
4929*am33
4930{
4931 int srcreg1, srcreg2, dstreg1, dstreg2;
4932
4933 PC = cia;
4934 srcreg1 = translate_rreg (SD_, RM1);
4935 srcreg2 = translate_rreg (SD_, RM2);
4936 dstreg1 = translate_rreg (SD_, RN1);
4937 dstreg2 = translate_rreg (SD_, RN2);
4938
4939 State.regs[dstreg1] += State.regs[srcreg1];
4940 State.regs[dstreg2] >>= State.regs[srcreg2];
4941}
4942
4943// 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
49448.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_lsr
4945"add_lsr"
4946*am33
4947{
4948 int srcreg1, dstreg1, dstreg2;
4949 signed int temp;
4950
4951 PC = cia;
4952 srcreg1 = translate_rreg (SD_, RM1);
4953 dstreg1 = translate_rreg (SD_, RN1);
4954 dstreg2 = translate_rreg (SD_, RN2);
4955
4956 State.regs[dstreg1] += State.regs[srcreg1];
4957 State.regs[dstreg2] >>= IMM4;
4958}
4959
4960
4961// 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
49628.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asl
4963"add_asl"
4964*am33
4965{
4966 int srcreg1, srcreg2, dstreg1, dstreg2;
4967
4968 PC = cia;
4969 srcreg1 = translate_rreg (SD_, RM1);
4970 srcreg2 = translate_rreg (SD_, RM2);
4971 dstreg1 = translate_rreg (SD_, RN1);
4972 dstreg2 = translate_rreg (SD_, RN2);
4973
4974 State.regs[dstreg1] += State.regs[srcreg1];
4975 State.regs[dstreg2] <<= State.regs[srcreg2];
4976}
4977
4978// 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
49798.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asl
4980"add_asl"
4981*am33
4982{
4983 int srcreg1, dstreg1, dstreg2;
4984 signed int temp;
4985
4986 PC = cia;
4987 srcreg1 = translate_rreg (SD_, RM1);
4988 dstreg1 = translate_rreg (SD_, RN1);
4989 dstreg2 = translate_rreg (SD_, RN2);
4990
4991 State.regs[dstreg1] += State.regs[srcreg1];
4992 State.regs[dstreg2] <<= IMM4;
4993}
4994
4995// 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
49968.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_add
4997"cmp_add"
4998*am33
4999{
5000 int srcreg1, srcreg2, dstreg1, dstreg2;
5001
5002 PC = cia;
5003 srcreg1 = translate_rreg (SD_, RM1);
5004 srcreg2 = translate_rreg (SD_, RM2);
5005 dstreg1 = translate_rreg (SD_, RN1);
5006 dstreg2 = translate_rreg (SD_, RN2);
5007
5008 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5009 State.regs[dstreg2] += State.regs[srcreg2];
5010}
5011
5012// 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
50138.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_add
5014"cmp_add"
5015*am33
5016{
5017 int srcreg1, dstreg1, dstreg2;
5018
5019 PC = cia;
5020 srcreg1 = translate_rreg (SD_, RM1);
5021 dstreg1 = translate_rreg (SD_, RN1);
5022 dstreg2 = translate_rreg (SD_, RN2);
5023
5024 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5025 State.regs[dstreg2] += EXTEND4 (IMM4);
5026}
5027
5028// 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
50298.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_sub
5030"cmp_sub"
5031*am33
5032{
5033 int srcreg1, srcreg2, dstreg1, dstreg2;
5034
5035 PC = cia;
5036 srcreg1 = translate_rreg (SD_, RM1);
5037 srcreg2 = translate_rreg (SD_, RM2);
5038 dstreg1 = translate_rreg (SD_, RN1);
5039 dstreg2 = translate_rreg (SD_, RN2);
5040
5041 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5042 State.regs[dstreg2] -= State.regs[srcreg2];
5043}
5044
5045// 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
50468.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_sub
5047"cmp_sub"
5048*am33
5049{
5050 int srcreg1, dstreg1, dstreg2;
5051
5052 PC = cia;
5053 srcreg1 = translate_rreg (SD_, RM1);
5054 dstreg1 = translate_rreg (SD_, RN1);
5055 dstreg2 = translate_rreg (SD_, RN2);
5056
5057 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5058 State.regs[dstreg2] -= EXTEND4 (IMM4);
5059}
5060
5061// 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
50628.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_mov
5063"cmp_mov"
5064*am33
5065{
5066 int srcreg1, srcreg2, dstreg1, dstreg2;
5067
5068 PC = cia;
5069 srcreg1 = translate_rreg (SD_, RM1);
5070 srcreg2 = translate_rreg (SD_, RM2);
5071 dstreg1 = translate_rreg (SD_, RN1);
5072 dstreg2 = translate_rreg (SD_, RN2);
5073
5074 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5075 State.regs[dstreg2] = State.regs[srcreg2];
5076}
5077
5078// 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
50798.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_mov
5080"cmp_mov"
5081*am33
5082{
5083 int srcreg1, dstreg1, dstreg2;
5084
5085 PC = cia;
5086 srcreg1 = translate_rreg (SD_, RM1);
5087 dstreg1 = translate_rreg (SD_, RN1);
5088 dstreg2 = translate_rreg (SD_, RN2);
5089
5090 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5091 State.regs[dstreg2] = EXTEND4 (IMM4);
5092}
5093
5094// 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
50958.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asr
5096"cmp_asr"
5097*am33
5098{
5099 int srcreg1, srcreg2, dstreg1, dstreg2;
5100 signed int temp;
5101
5102 PC = cia;
5103 srcreg1 = translate_rreg (SD_, RM1);
5104 srcreg2 = translate_rreg (SD_, RM2);
5105 dstreg1 = translate_rreg (SD_, RN1);
5106 dstreg2 = translate_rreg (SD_, RN2);
5107
5108 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5109 temp = State.regs[dstreg2];
5110 temp >>= State.regs[srcreg2];
5111 State.regs[dstreg2] = temp;
5112}
5113
5114// 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
51158.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asr
5116"cmp_asr"
5117*am33
5118{
5119 int srcreg1, dstreg1, dstreg2;
5120 signed int temp;
5121
5122 PC = cia;
5123 srcreg1 = translate_rreg (SD_, RM1);
5124 dstreg1 = translate_rreg (SD_, RN1);
5125 dstreg2 = translate_rreg (SD_, RN2);
5126
5127 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5128 temp = State.regs[dstreg2];
5129 temp >>= IMM4;
5130 State.regs[dstreg2] = temp;
5131}
5132
5133// 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
51348.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_lsr
5135"cmp_lsr"
5136*am33
5137{
5138 int srcreg1, srcreg2, dstreg1, dstreg2;
5139
5140 PC = cia;
5141 srcreg1 = translate_rreg (SD_, RM1);
5142 srcreg2 = translate_rreg (SD_, RM2);
5143 dstreg1 = translate_rreg (SD_, RN1);
5144 dstreg2 = translate_rreg (SD_, RN2);
5145
5146 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5147 State.regs[dstreg2] >>= State.regs[srcreg2];
5148}
5149
5150// 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
51518.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_lsr
5152"cmp_lsr"
5153*am33
5154{
5155 int srcreg1, dstreg1, dstreg2;
5156 signed int temp;
5157
5158 PC = cia;
5159 srcreg1 = translate_rreg (SD_, RM1);
5160 dstreg1 = translate_rreg (SD_, RN1);
5161 dstreg2 = translate_rreg (SD_, RN2);
5162
5163 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5164 State.regs[dstreg2] >>= IMM4;
5165}
5166
5167
5168// 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
51698.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asl
5170"cmp_asl"
5171*am33
5172{
5173 int srcreg1, srcreg2, dstreg1, dstreg2;
5174
5175 PC = cia;
5176 srcreg1 = translate_rreg (SD_, RM1);
5177 srcreg2 = translate_rreg (SD_, RM2);
5178 dstreg1 = translate_rreg (SD_, RN1);
5179 dstreg2 = translate_rreg (SD_, RN2);
5180
5181 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5182 State.regs[dstreg2] <<= State.regs[srcreg2];
5183}
5184
5185// 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
51868.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asl
5187"cmp_asl"
5188*am33
5189{
5190 int srcreg1, dstreg1, dstreg2;
5191 signed int temp;
5192
5193 PC = cia;
5194 srcreg1 = translate_rreg (SD_, RM1);
5195 dstreg1 = translate_rreg (SD_, RN1);
5196 dstreg2 = translate_rreg (SD_, RN2);
5197
5198 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5199 State.regs[dstreg2] <<= IMM4;
5200}
5201
5202// 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
52038.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_add
5204"sub_add"
5205*am33
5206{
5207 int srcreg1, srcreg2, dstreg1, dstreg2;
5208
5209 PC = cia;
5210 srcreg1 = translate_rreg (SD_, RM1);
5211 srcreg2 = translate_rreg (SD_, RM2);
5212 dstreg1 = translate_rreg (SD_, RN1);
5213 dstreg2 = translate_rreg (SD_, RN2);
5214
5215 State.regs[dstreg1] -= State.regs[srcreg1];
5216 State.regs[dstreg2] += State.regs[srcreg2];
5217}
5218
5219// 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
52208.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_add
5221"sub_add"
5222*am33
5223{
5224 int srcreg1, dstreg1, dstreg2;
5225
5226 PC = cia;
5227 srcreg1 = translate_rreg (SD_, RM1);
5228 dstreg1 = translate_rreg (SD_, RN1);
5229 dstreg2 = translate_rreg (SD_, RN2);
5230
5231 State.regs[dstreg1] -= State.regs[srcreg1];
5232 State.regs[dstreg2] += EXTEND4 (IMM4);
5233}
5234
5235// 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
52368.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_sub
5237"sub_sub"
5238*am33
5239{
5240 int srcreg1, srcreg2, dstreg1, dstreg2;
5241
5242 PC = cia;
5243 srcreg1 = translate_rreg (SD_, RM1);
5244 srcreg2 = translate_rreg (SD_, RM2);
5245 dstreg1 = translate_rreg (SD_, RN1);
5246 dstreg2 = translate_rreg (SD_, RN2);
5247
5248 State.regs[dstreg1] -= State.regs[srcreg1];
5249 State.regs[dstreg2] -= State.regs[srcreg2];
5250}
5251
5252// 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
52538.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_sub
5254"sub_sub"
5255*am33
5256{
5257 int srcreg1, dstreg1, dstreg2;
5258
5259 PC = cia;
5260 srcreg1 = translate_rreg (SD_, RM1);
5261 dstreg1 = translate_rreg (SD_, RN1);
5262 dstreg2 = translate_rreg (SD_, RN2);
5263
5264 State.regs[dstreg1] -= State.regs[srcreg1];
5265 State.regs[dstreg2] -= EXTEND4 (IMM4);
5266}
5267
5268// 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
52698.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_cmp
5270"sub_cmp"
5271*am33
5272{
5273 int srcreg1, srcreg2, dstreg1, dstreg2;
5274
5275 PC = cia;
5276 srcreg1 = translate_rreg (SD_, RM1);
5277 srcreg2 = translate_rreg (SD_, RM2);
5278 dstreg1 = translate_rreg (SD_, RN1);
5279 dstreg2 = translate_rreg (SD_, RN2);
5280
5281 State.regs[dstreg1] -= State.regs[srcreg1];
5282 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5283}
5284
5285// 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
52868.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_cmp
5287"sub_cmp"
5288*am33
5289{
5290 int srcreg1, dstreg1, dstreg2;
5291
5292 PC = cia;
5293 srcreg1 = translate_rreg (SD_, RM1);
5294 dstreg1 = translate_rreg (SD_, RN1);
5295 dstreg2 = translate_rreg (SD_, RN2);
5296
5297 State.regs[dstreg1] -= State.regs[srcreg1];
5298 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5299}
5300
5301// 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
53028.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_mov
5303"sub_mov"
5304*am33
5305{
5306 int srcreg1, srcreg2, dstreg1, dstreg2;
5307
5308 PC = cia;
5309 srcreg1 = translate_rreg (SD_, RM1);
5310 srcreg2 = translate_rreg (SD_, RM2);
5311 dstreg1 = translate_rreg (SD_, RN1);
5312 dstreg2 = translate_rreg (SD_, RN2);
5313
5314 State.regs[dstreg1] -= State.regs[srcreg1];
5315 State.regs[dstreg2] = State.regs[srcreg2];
5316}
5317
5318// 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
53198.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_mov
5320"sub_mov"
5321*am33
5322{
5323 int srcreg1, dstreg1, dstreg2;
5324
5325 PC = cia;
5326 srcreg1 = translate_rreg (SD_, RM1);
5327 dstreg1 = translate_rreg (SD_, RN1);
5328 dstreg2 = translate_rreg (SD_, RN2);
5329
5330 State.regs[dstreg1] -= State.regs[srcreg1];
5331 State.regs[dstreg2] = EXTEND4 (IMM4);
5332}
5333
5334// 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
53358.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asr
5336"sub_asr"
5337*am33
5338{
5339 int srcreg1, srcreg2, dstreg1, dstreg2;
5340 signed int temp;
5341
5342 PC = cia;
5343 srcreg1 = translate_rreg (SD_, RM1);
5344 srcreg2 = translate_rreg (SD_, RM2);
5345 dstreg1 = translate_rreg (SD_, RN1);
5346 dstreg2 = translate_rreg (SD_, RN2);
5347
5348 State.regs[dstreg1] -= State.regs[srcreg1];
5349 temp = State.regs[dstreg2];
5350 temp >>= State.regs[srcreg2];
5351 State.regs[dstreg2] = temp;
5352}
5353
5354// 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
53558.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asr
5356"sub_asr"
5357*am33
5358{
5359 int srcreg1, dstreg1, dstreg2;
5360 signed int temp;
5361
5362 PC = cia;
5363 srcreg1 = translate_rreg (SD_, RM1);
5364 dstreg1 = translate_rreg (SD_, RN1);
5365 dstreg2 = translate_rreg (SD_, RN2);
5366
5367 State.regs[dstreg1] -= State.regs[srcreg1];
5368 temp = State.regs[dstreg2];
5369 temp >>= IMM4;
5370 State.regs[dstreg2] = temp;
5371}
5372
5373// 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
53748.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_lsr
5375"sub_lsr"
5376*am33
5377{
5378 int srcreg1, srcreg2, dstreg1, dstreg2;
5379
5380 PC = cia;
5381 srcreg1 = translate_rreg (SD_, RM1);
5382 srcreg2 = translate_rreg (SD_, RM2);
5383 dstreg1 = translate_rreg (SD_, RN1);
5384 dstreg2 = translate_rreg (SD_, RN2);
5385
5386 State.regs[dstreg1] -= State.regs[srcreg1];
5387 State.regs[dstreg2] >>= State.regs[srcreg2];
5388}
5389
5390// 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
53918.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_lsr
5392"sub_lsr"
5393*am33
5394{
5395 int srcreg1, dstreg1, dstreg2;
5396 signed int temp;
5397
5398 PC = cia;
5399 srcreg1 = translate_rreg (SD_, RM1);
5400 dstreg1 = translate_rreg (SD_, RN1);
5401 dstreg2 = translate_rreg (SD_, RN2);
5402
5403 State.regs[dstreg1] -= State.regs[srcreg1];
5404 State.regs[dstreg2] >>= IMM4;
5405}
5406
5407
5408// 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
54098.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asl
5410"sub_asl"
5411*am33
5412{
5413 int srcreg1, srcreg2, dstreg1, dstreg2;
5414
5415 PC = cia;
5416 srcreg1 = translate_rreg (SD_, RM1);
5417 srcreg2 = translate_rreg (SD_, RM2);
5418 dstreg1 = translate_rreg (SD_, RN1);
5419 dstreg2 = translate_rreg (SD_, RN2);
5420
5421 State.regs[dstreg1] -= State.regs[srcreg1];
5422 State.regs[dstreg2] <<= State.regs[srcreg2];
5423}
5424
5425// 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
54268.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asl
5427"sub_asl"
5428*am33
5429{
5430 int srcreg1, dstreg1, dstreg2;
5431 signed int temp;
5432
5433 PC = cia;
5434 srcreg1 = translate_rreg (SD_, RM1);
5435 dstreg1 = translate_rreg (SD_, RN1);
5436 dstreg2 = translate_rreg (SD_, RN2);
5437
5438 State.regs[dstreg1] -= State.regs[srcreg1];
5439 State.regs[dstreg2] <<= IMM4;
5440}
5441
5442// 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
54438.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_add
5444"mov_add"
5445*am33
5446{
5447 int srcreg1, srcreg2, dstreg1, dstreg2;
5448
5449 PC = cia;
5450 srcreg1 = translate_rreg (SD_, RM1);
5451 srcreg2 = translate_rreg (SD_, RM2);
5452 dstreg1 = translate_rreg (SD_, RN1);
5453 dstreg2 = translate_rreg (SD_, RN2);
5454
5455 State.regs[dstreg1] = State.regs[srcreg1];
5456 State.regs[dstreg2] += State.regs[srcreg2];
5457}
5458
5459// 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
54608.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_add
5461"mov_add"
5462*am33
5463{
5464 int srcreg1, dstreg1, dstreg2;
5465
5466 PC = cia;
5467 srcreg1 = translate_rreg (SD_, RM1);
5468 dstreg1 = translate_rreg (SD_, RN1);
5469 dstreg2 = translate_rreg (SD_, RN2);
5470
5471 State.regs[dstreg1] = State.regs[srcreg1];
5472 State.regs[dstreg2] += EXTEND4 (IMM4);
5473}
5474
5475// 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
54768.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_sub
5477"mov_sub"
5478*am33
5479{
5480 int srcreg1, srcreg2, dstreg1, dstreg2;
5481
5482 PC = cia;
5483 srcreg1 = translate_rreg (SD_, RM1);
5484 srcreg2 = translate_rreg (SD_, RM2);
5485 dstreg1 = translate_rreg (SD_, RN1);
5486 dstreg2 = translate_rreg (SD_, RN2);
5487
5488 State.regs[dstreg1] = State.regs[srcreg1];
5489 State.regs[dstreg2] -= State.regs[srcreg2];
5490}
5491
5492// 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
54938.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_sub
5494"mov_sub"
5495*am33
5496{
5497 int srcreg1, dstreg1, dstreg2;
5498
5499 PC = cia;
5500 srcreg1 = translate_rreg (SD_, RM1);
5501 dstreg1 = translate_rreg (SD_, RN1);
5502 dstreg2 = translate_rreg (SD_, RN2);
5503
5504 State.regs[dstreg1] = State.regs[srcreg1];
5505 State.regs[dstreg2] -= EXTEND4 (IMM4);
5506}
5507
5508// 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
55098.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_cmp
5510"mov_cmp"
5511*am33
5512{
5513 int srcreg1, srcreg2, dstreg1, dstreg2;
5514
5515 PC = cia;
5516 srcreg1 = translate_rreg (SD_, RM1);
5517 srcreg2 = translate_rreg (SD_, RM2);
5518 dstreg1 = translate_rreg (SD_, RN1);
5519 dstreg2 = translate_rreg (SD_, RN2);
5520
5521 State.regs[dstreg1] = State.regs[srcreg1];
5522 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5523}
5524
5525// 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
55268.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_cmp
5527"mov_cmp"
5528*am33
5529{
5530 int srcreg1, dstreg1, dstreg2;
5531
5532 PC = cia;
5533 srcreg1 = translate_rreg (SD_, RM1);
5534 dstreg1 = translate_rreg (SD_, RN1);
5535 dstreg2 = translate_rreg (SD_, RN2);
5536
5537 State.regs[dstreg1] = State.regs[srcreg1];
5538 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5539}
5540
5541// 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
55428.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_mov
5543"mov_mov"
5544*am33
5545{
5546 int srcreg1, srcreg2, dstreg1, dstreg2;
5547
5548 PC = cia;
5549 srcreg1 = translate_rreg (SD_, RM1);
5550 srcreg2 = translate_rreg (SD_, RM2);
5551 dstreg1 = translate_rreg (SD_, RN1);
5552 dstreg2 = translate_rreg (SD_, RN2);
5553
5554 State.regs[dstreg1] = State.regs[srcreg1];
5555 State.regs[dstreg2] = State.regs[srcreg2];
5556}
5557
5558// 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
55598.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_mov
5560"mov_mov"
5561*am33
5562{
5563 int srcreg1, dstreg1, dstreg2;
5564
5565 PC = cia;
5566 srcreg1 = translate_rreg (SD_, RM1);
5567 dstreg1 = translate_rreg (SD_, RN1);
5568 dstreg2 = translate_rreg (SD_, RN2);
5569
5570 State.regs[dstreg1] = State.regs[srcreg1];
5571 State.regs[dstreg2] = EXTEND4 (IMM4);
5572}
5573
5574// 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
55758.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asr
5576"mov_asr"
5577*am33
5578{
5579 int srcreg1, srcreg2, dstreg1, dstreg2;
5580 signed int temp;
5581
5582 PC = cia;
5583 srcreg1 = translate_rreg (SD_, RM1);
5584 srcreg2 = translate_rreg (SD_, RM2);
5585 dstreg1 = translate_rreg (SD_, RN1);
5586 dstreg2 = translate_rreg (SD_, RN2);
5587
5588 State.regs[dstreg1] = State.regs[srcreg1];
5589 temp = State.regs[dstreg2];
5590 temp >>= State.regs[srcreg2];
5591 State.regs[dstreg2] = temp;
5592}
5593
5594// 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
55958.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asr
5596"mov_asr"
5597*am33
5598{
5599 int srcreg1, dstreg1, dstreg2;
5600 signed int temp;
5601
5602 PC = cia;
5603 srcreg1 = translate_rreg (SD_, RM1);
5604 dstreg1 = translate_rreg (SD_, RN1);
5605 dstreg2 = translate_rreg (SD_, RN2);
5606
5607 State.regs[dstreg1] = State.regs[srcreg1];
5608 temp = State.regs[dstreg2];
5609 temp >>= IMM4;
5610 State.regs[dstreg2] = temp;
5611}
5612
5613// 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
56148.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_lsr
5615"mov_lsr"
5616*am33
5617{
5618 int srcreg1, srcreg2, dstreg1, dstreg2;
5619
5620 PC = cia;
5621 srcreg1 = translate_rreg (SD_, RM1);
5622 srcreg2 = translate_rreg (SD_, RM2);
5623 dstreg1 = translate_rreg (SD_, RN1);
5624 dstreg2 = translate_rreg (SD_, RN2);
5625
5626 State.regs[dstreg1] = State.regs[srcreg1];
5627 State.regs[dstreg2] >>= State.regs[srcreg2];
5628}
5629
5630// 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
56318.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_lsr
5632"mov_lsr"
5633*am33
5634{
5635 int srcreg1, dstreg1, dstreg2;
5636 signed int temp;
5637
5638 PC = cia;
5639 srcreg1 = translate_rreg (SD_, RM1);
5640 dstreg1 = translate_rreg (SD_, RN1);
5641 dstreg2 = translate_rreg (SD_, RN2);
5642
5643 State.regs[dstreg1] = State.regs[srcreg1];
5644 State.regs[dstreg2] >>= IMM4;
5645}
5646
5647
5648// 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
56498.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asl
5650"mov_asl"
5651*am33
5652{
5653 int srcreg1, srcreg2, dstreg1, dstreg2;
5654
5655 PC = cia;
5656 srcreg1 = translate_rreg (SD_, RM1);
5657 srcreg2 = translate_rreg (SD_, RM2);
5658 dstreg1 = translate_rreg (SD_, RN1);
5659 dstreg2 = translate_rreg (SD_, RN2);
5660
5661 State.regs[dstreg1] = State.regs[srcreg1];
5662 State.regs[dstreg2] <<= State.regs[srcreg2];
5663}
5664
5665// 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
56668.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asl
5667"mov_asl"
5668*am33
5669{
5670 int srcreg1, dstreg1, dstreg2;
5671 signed int temp;
5672
5673 PC = cia;
5674 srcreg1 = translate_rreg (SD_, RM1);
5675 dstreg1 = translate_rreg (SD_, RN1);
5676 dstreg2 = translate_rreg (SD_, RN2);
5677
5678 State.regs[dstreg1] = State.regs[srcreg1];
5679 State.regs[dstreg2] <<= IMM4;
5680}
5681
5682// 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
56838.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_add
5684"add_add"
5685*am33
5686{
5687 int srcreg2, dstreg1, dstreg2;
5688
5689 PC = cia;
5690 srcreg2 = translate_rreg (SD_, RM2);
5691 dstreg1 = translate_rreg (SD_, RN1);
5692 dstreg2 = translate_rreg (SD_, RN2);
5693
5694 State.regs[dstreg1] += EXTEND4 (IMM4A);
5695 State.regs[dstreg2] += State.regs[srcreg2];
5696}
5697
5698// 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
56998.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_add
5700"add_add"
5701*am33
5702{
5703 int dstreg1, dstreg2;
5704
5705 PC = cia;
5706 dstreg1 = translate_rreg (SD_, RN1);
5707 dstreg2 = translate_rreg (SD_, RN2);
5708
5709 State.regs[dstreg1] += EXTEND4 (IMM4A);
5710 State.regs[dstreg2] += EXTEND4 (IMM4);
5711}
5712
5713// 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
57148.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_sub
5715"add_sub"
5716*am33
5717{
5718 int srcreg2, dstreg1, dstreg2;
5719
5720 PC = cia;
5721 srcreg2 = translate_rreg (SD_, RM2);
5722 dstreg1 = translate_rreg (SD_, RN1);
5723 dstreg2 = translate_rreg (SD_, RN2);
5724
5725 State.regs[dstreg1] += EXTEND4 (IMM4A);
5726 State.regs[dstreg2] -= State.regs[srcreg2];
5727}
5728
5729// 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
57308.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_sub
5731"add_sub"
5732*am33
5733{
5734 int dstreg1, dstreg2;
5735
5736 PC = cia;
5737 dstreg1 = translate_rreg (SD_, RN1);
5738 dstreg2 = translate_rreg (SD_, RN2);
5739
5740 State.regs[dstreg1] += EXTEND4 (IMM4A);
5741 State.regs[dstreg2] -= EXTEND4 (IMM4);
5742}
5743
5744// 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
57458.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_cmp
5746"add_cmp"
5747*am33
5748{
5749 int srcreg2, dstreg1, dstreg2;
5750
5751 PC = cia;
5752 srcreg2 = translate_rreg (SD_, RM2);
5753 dstreg1 = translate_rreg (SD_, RN1);
5754 dstreg2 = translate_rreg (SD_, RN2);
5755
5756 State.regs[dstreg1] += EXTEND4 (IMM4A);
5757 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5758}
5759
5760// 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
57618.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_cmp
5762"add_cmp"
5763*am33
5764{
5765 int dstreg1, dstreg2;
5766
5767 PC = cia;
5768 dstreg1 = translate_rreg (SD_, RN1);
5769 dstreg2 = translate_rreg (SD_, RN2);
5770
5771 State.regs[dstreg1] += EXTEND4 (IMM4A);
5772 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5773}
5774
5775// 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
57768.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_mov
5777"add_mov"
5778*am33
5779{
5780 int srcreg2, dstreg1, dstreg2;
5781
5782 PC = cia;
5783 srcreg2 = translate_rreg (SD_, RM2);
5784 dstreg1 = translate_rreg (SD_, RN1);
5785 dstreg2 = translate_rreg (SD_, RN2);
5786
5787 State.regs[dstreg1] += EXTEND4 (IMM4A);
5788 State.regs[dstreg2] = State.regs[srcreg2];
5789}
5790
5791// 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
57928.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_mov
5793"add_mov"
5794*am33
5795{
5796 int dstreg1, dstreg2;
5797
5798 PC = cia;
5799 dstreg1 = translate_rreg (SD_, RN1);
5800 dstreg2 = translate_rreg (SD_, RN2);
5801
5802 State.regs[dstreg1] += EXTEND4 (IMM4A);
5803 State.regs[dstreg2] = EXTEND4 (IMM4);
5804}
5805
5806// 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
58078.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asr
5808"add_asr"
5809*am33
5810{
5811 int srcreg2, dstreg1, dstreg2;
5812 signed int temp;
5813
5814 PC = cia;
5815 srcreg2 = translate_rreg (SD_, RM2);
5816 dstreg1 = translate_rreg (SD_, RN1);
5817 dstreg2 = translate_rreg (SD_, RN2);
5818
5819 State.regs[dstreg1] += EXTEND4 (IMM4A);
5820 temp = State.regs[dstreg2];
5821 temp >>= State.regs[srcreg2];
5822 State.regs[dstreg2] = temp;
5823}
5824
5825// 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
58268.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asr
5827"add_asr"
5828*am33
5829{
5830 int dstreg1, dstreg2;
5831 signed int temp;
5832
5833 PC = cia;
5834 dstreg1 = translate_rreg (SD_, RN1);
5835 dstreg2 = translate_rreg (SD_, RN2);
5836
5837 State.regs[dstreg1] += EXTEND4 (IMM4A);
5838 temp = State.regs[dstreg2];
5839 temp >>= IMM4;
5840 State.regs[dstreg2] = temp;
5841}
5842
5843// 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
58448.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_lsr
5845"add_lsr"
5846*am33
5847{
5848 int srcreg2, dstreg1, dstreg2;
5849
5850 PC = cia;
5851 srcreg2 = translate_rreg (SD_, RM2);
5852 dstreg1 = translate_rreg (SD_, RN1);
5853 dstreg2 = translate_rreg (SD_, RN2);
5854
5855 State.regs[dstreg1] += EXTEND4 (IMM4A);
5856 State.regs[dstreg2] >>= State.regs[srcreg2];
5857}
5858
5859// 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
58608.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_lsr
5861"add_lsr"
5862*am33
5863{
5864 int dstreg1, dstreg2;
5865 signed int temp;
5866
5867 PC = cia;
5868 dstreg1 = translate_rreg (SD_, RN1);
5869 dstreg2 = translate_rreg (SD_, RN2);
5870
5871 State.regs[dstreg1] += EXTEND4 (IMM4A);
5872 State.regs[dstreg2] >>= IMM4;
5873}
5874
5875
5876// 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
58778.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asl
5878"add_asl"
5879*am33
5880{
5881 int srcreg2, dstreg1, dstreg2;
5882
5883 PC = cia;
5884 srcreg2 = translate_rreg (SD_, RM2);
5885 dstreg1 = translate_rreg (SD_, RN1);
5886 dstreg2 = translate_rreg (SD_, RN2);
5887
5888 State.regs[dstreg1] += EXTEND4 (IMM4A);
5889 State.regs[dstreg2] <<= State.regs[srcreg2];
5890}
5891
5892// 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
58938.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asl
5894"add_asl"
5895*am33
5896{
5897 int dstreg1, dstreg2;
5898 signed int temp;
5899
5900 PC = cia;
5901 dstreg1 = translate_rreg (SD_, RN1);
5902 dstreg2 = translate_rreg (SD_, RN2);
5903
5904 State.regs[dstreg1] += EXTEND4 (IMM4A);
5905 State.regs[dstreg2] <<= IMM4;
5906}
5907
5908// 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
59098.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_add
5910"cmp_add"
5911*am33
5912{
5913 int srcreg2, dstreg1, dstreg2;
5914
5915 PC = cia;
5916 srcreg2 = translate_rreg (SD_, RM2);
5917 dstreg1 = translate_rreg (SD_, RN1);
5918 dstreg2 = translate_rreg (SD_, RN2);
5919
5920 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5921 State.regs[dstreg2] += State.regs[srcreg2];
5922}
5923
5924// 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
59258.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_add
5926"cmp_add"
5927*am33
5928{
5929 int dstreg1, dstreg2;
5930
5931 PC = cia;
5932 dstreg1 = translate_rreg (SD_, RN1);
5933 dstreg2 = translate_rreg (SD_, RN2);
5934
5935 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5936 State.regs[dstreg2] += EXTEND4 (IMM4);
5937}
5938
5939// 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
59408.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_sub
5941"cmp_sub"
5942*am33
5943{
5944 int srcreg2, dstreg1, dstreg2;
5945
5946 PC = cia;
5947 srcreg2 = translate_rreg (SD_, RM2);
5948 dstreg1 = translate_rreg (SD_, RN1);
5949 dstreg2 = translate_rreg (SD_, RN2);
5950
5951 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5952 State.regs[dstreg2] -= State.regs[srcreg2];
5953}
5954
5955// 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
59568.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_sub
5957"cmp_sub"
5958*am33
5959{
5960 int dstreg1, dstreg2;
5961
5962 PC = cia;
5963 dstreg1 = translate_rreg (SD_, RN1);
5964 dstreg2 = translate_rreg (SD_, RN2);
5965
5966 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5967 State.regs[dstreg2] -= EXTEND4 (IMM4);
5968}
5969
5970// 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
59718.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_mov
5972"cmp_mov"
5973*am33
5974{
5975 int srcreg2, dstreg1, dstreg2;
5976
5977 PC = cia;
5978 srcreg2 = translate_rreg (SD_, RM2);
5979 dstreg1 = translate_rreg (SD_, RN1);
5980 dstreg2 = translate_rreg (SD_, RN2);
5981
5982 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5983 State.regs[dstreg2] = State.regs[srcreg2];
5984}
5985
5986// 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
59878.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_mov
5988"cmp_mov"
5989*am33
5990{
5991 int dstreg1, dstreg2;
5992
5993 PC = cia;
5994 dstreg1 = translate_rreg (SD_, RN1);
5995 dstreg2 = translate_rreg (SD_, RN2);
5996
5997 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5998 State.regs[dstreg2] = EXTEND4 (IMM4);
5999}
6000
6001// 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
60028.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asr
6003"cmp_asr"
6004*am33
6005{
6006 int srcreg2, dstreg1, dstreg2;
6007 signed int temp;
6008
6009 PC = cia;
6010 srcreg2 = translate_rreg (SD_, RM2);
6011 dstreg1 = translate_rreg (SD_, RN1);
6012 dstreg2 = translate_rreg (SD_, RN2);
6013
6014 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6015 temp = State.regs[dstreg2];
6016 temp >>= State.regs[srcreg2];
6017 State.regs[dstreg2] = temp;
6018}
6019
6020// 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
60218.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asr
6022"cmp_asr"
6023*am33
6024{
6025 int dstreg1, dstreg2;
6026 signed int temp;
6027
6028 PC = cia;
6029 dstreg1 = translate_rreg (SD_, RN1);
6030 dstreg2 = translate_rreg (SD_, RN2);
6031
6032 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6033 temp = State.regs[dstreg2];
6034 temp >>= IMM4;
6035 State.regs[dstreg2] = temp;
6036}
6037
6038// 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
60398.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_lsr
6040"cmp_lsr"
6041*am33
6042{
6043 int srcreg2, dstreg1, dstreg2;
6044
6045 PC = cia;
6046 srcreg2 = translate_rreg (SD_, RM2);
6047 dstreg1 = translate_rreg (SD_, RN1);
6048 dstreg2 = translate_rreg (SD_, RN2);
6049
6050 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6051 State.regs[dstreg2] >>= State.regs[srcreg2];
6052}
6053
6054// 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
60558.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_lsr
6056"cmp_lsr"
6057*am33
6058{
6059 int dstreg1, dstreg2;
6060 signed int temp;
6061
6062 PC = cia;
6063 dstreg1 = translate_rreg (SD_, RN1);
6064 dstreg2 = translate_rreg (SD_, RN2);
6065
6066 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6067 State.regs[dstreg2] >>= IMM4;
6068}
6069
6070
6071// 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
60728.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asl
6073"cmp_asl"
6074*am33
6075{
6076 int srcreg2, dstreg1, dstreg2;
6077
6078 PC = cia;
6079 srcreg2 = translate_rreg (SD_, RM2);
6080 dstreg1 = translate_rreg (SD_, RN1);
6081 dstreg2 = translate_rreg (SD_, RN2);
6082
6083 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6084 State.regs[dstreg2] <<= State.regs[srcreg2];
6085}
6086
6087// 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
60888.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asl
6089"cmp_asl"
6090*am33
6091{
6092 int dstreg1, dstreg2;
6093 signed int temp;
6094
6095 PC = cia;
6096 dstreg1 = translate_rreg (SD_, RN1);
6097 dstreg2 = translate_rreg (SD_, RN2);
6098
6099 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6100 State.regs[dstreg2] <<= IMM4;
6101}
6102
6103// 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
61048.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_add
6105"sub_add"
6106*am33
6107{
6108 int srcreg2, dstreg1, dstreg2;
6109
6110 PC = cia;
6111 srcreg2 = translate_rreg (SD_, RM2);
6112 dstreg1 = translate_rreg (SD_, RN1);
6113 dstreg2 = translate_rreg (SD_, RN2);
6114
6115 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6116 State.regs[dstreg2] += State.regs[srcreg2];
6117}
6118
6119// 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
61208.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_add
6121"sub_add"
6122*am33
6123{
6124 int dstreg1, dstreg2;
6125
6126 PC = cia;
6127 dstreg1 = translate_rreg (SD_, RN1);
6128 dstreg2 = translate_rreg (SD_, RN2);
6129
6130 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6131 State.regs[dstreg2] += EXTEND4 (IMM4);
6132}
6133
6134// 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
61358.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_sub
6136"sub_sub"
6137*am33
6138{
6139 int srcreg2, dstreg1, dstreg2;
6140
6141 PC = cia;
6142 srcreg2 = translate_rreg (SD_, RM2);
6143 dstreg1 = translate_rreg (SD_, RN1);
6144 dstreg2 = translate_rreg (SD_, RN2);
6145
6146 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6147 State.regs[dstreg2] -= State.regs[srcreg2];
6148}
6149
6150// 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
61518.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_sub
6152"sub_sub"
6153*am33
6154{
6155 int dstreg1, dstreg2;
6156
6157 PC = cia;
6158 dstreg1 = translate_rreg (SD_, RN1);
6159 dstreg2 = translate_rreg (SD_, RN2);
6160
6161 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6162 State.regs[dstreg2] -= EXTEND4 (IMM4);
6163}
6164
6165// 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
61668.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_cmp
6167"sub_cmp"
6168*am33
6169{
6170 int srcreg2, dstreg1, dstreg2;
6171
6172 PC = cia;
6173 srcreg2 = translate_rreg (SD_, RM2);
6174 dstreg1 = translate_rreg (SD_, RN1);
6175 dstreg2 = translate_rreg (SD_, RN2);
6176
6177 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6178 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6179}
6180
6181// 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
61828.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_cmp
6183"sub_cmp"
6184*am33
6185{
6186 int dstreg1, dstreg2;
6187
6188 PC = cia;
6189 dstreg1 = translate_rreg (SD_, RN1);
6190 dstreg2 = translate_rreg (SD_, RN2);
6191
6192 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6193 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6194}
6195
6196// 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
61978.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_mov
6198"sub_mov"
6199*am33
6200{
6201 int srcreg2, dstreg1, dstreg2;
6202
6203 PC = cia;
6204 srcreg2 = translate_rreg (SD_, RM2);
6205 dstreg1 = translate_rreg (SD_, RN1);
6206 dstreg2 = translate_rreg (SD_, RN2);
6207
6208 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6209 State.regs[dstreg2] = State.regs[srcreg2];
6210}
6211
6212// 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
62138.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_mov
6214"sub_mov"
6215*am33
6216{
6217 int dstreg1, dstreg2;
6218
6219 PC = cia;
6220 dstreg1 = translate_rreg (SD_, RN1);
6221 dstreg2 = translate_rreg (SD_, RN2);
6222
6223 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6224 State.regs[dstreg2] = EXTEND4 (IMM4);
6225}
6226
6227// 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
62288.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asr
6229"sub_asr"
6230*am33
6231{
6232 int srcreg2, dstreg1, dstreg2;
6233 signed int temp;
6234
6235 PC = cia;
6236 srcreg2 = translate_rreg (SD_, RM2);
6237 dstreg1 = translate_rreg (SD_, RN1);
6238 dstreg2 = translate_rreg (SD_, RN2);
6239
6240 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6241 temp = State.regs[dstreg2];
6242 temp >>= State.regs[srcreg2];
6243 State.regs[dstreg2] = temp;
6244}
6245
6246// 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
62478.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asr
6248"sub_asr"
6249*am33
6250{
6251 int dstreg1, dstreg2;
6252 signed int temp;
6253
6254 PC = cia;
6255 dstreg1 = translate_rreg (SD_, RN1);
6256 dstreg2 = translate_rreg (SD_, RN2);
6257
6258 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6259 temp = State.regs[dstreg2];
6260 temp >>= IMM4;
6261 State.regs[dstreg2] = temp;
6262}
6263
6264// 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
62658.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_lsr
6266"sub_lsr"
6267*am33
6268{
6269 int srcreg2, dstreg1, dstreg2;
6270
6271 PC = cia;
6272 srcreg2 = translate_rreg (SD_, RM2);
6273 dstreg1 = translate_rreg (SD_, RN1);
6274 dstreg2 = translate_rreg (SD_, RN2);
6275
6276 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6277 State.regs[dstreg2] >>= State.regs[srcreg2];
6278}
6279
6280// 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
62818.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_lsr
6282"sub_lsr"
6283*am33
6284{
6285 int dstreg1, dstreg2;
6286 signed int temp;
6287
6288 PC = cia;
6289 dstreg1 = translate_rreg (SD_, RN1);
6290 dstreg2 = translate_rreg (SD_, RN2);
6291
6292 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6293 State.regs[dstreg2] >>= IMM4;
6294}
6295
6296
6297// 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
62988.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asl
6299"sub_asl"
6300*am33
6301{
6302 int srcreg2, dstreg1, dstreg2;
6303
6304 PC = cia;
6305 srcreg2 = translate_rreg (SD_, RM2);
6306 dstreg1 = translate_rreg (SD_, RN1);
6307 dstreg2 = translate_rreg (SD_, RN2);
6308
6309 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6310 State.regs[dstreg2] <<= State.regs[srcreg2];
6311}
6312
6313// 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
63148.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asl
6315"sub_asl"
6316*am33
6317{
6318 int dstreg1, dstreg2;
6319 signed int temp;
6320
6321 PC = cia;
6322 dstreg1 = translate_rreg (SD_, RN1);
6323 dstreg2 = translate_rreg (SD_, RN2);
6324
6325 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6326 State.regs[dstreg2] <<= IMM4;
6327}
6328
6329// 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
63308.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_add
6331"mov_add"
6332*am33
6333{
6334 int srcreg2, dstreg1, dstreg2;
6335
6336 PC = cia;
6337 srcreg2 = translate_rreg (SD_, RM2);
6338 dstreg1 = translate_rreg (SD_, RN1);
6339 dstreg2 = translate_rreg (SD_, RN2);
6340
6341 State.regs[dstreg1] = EXTEND4 (IMM4A);
6342 State.regs[dstreg2] += State.regs[srcreg2];
6343}
6344
6345// 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
63468.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_add
6347"mov_add"
6348*am33
6349{
6350 int dstreg1, dstreg2;
6351
6352 PC = cia;
6353 dstreg1 = translate_rreg (SD_, RN1);
6354 dstreg2 = translate_rreg (SD_, RN2);
6355
6356 State.regs[dstreg1] = EXTEND4 (IMM4A);
6357 State.regs[dstreg2] += EXTEND4 (IMM4);
6358}
6359
6360// 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
63618.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_sub
6362"mov_sub"
6363*am33
6364{
6365 int srcreg2, dstreg1, dstreg2;
6366
6367 PC = cia;
6368 srcreg2 = translate_rreg (SD_, RM2);
6369 dstreg1 = translate_rreg (SD_, RN1);
6370 dstreg2 = translate_rreg (SD_, RN2);
6371
6372 State.regs[dstreg1] = EXTEND4 (IMM4A);
6373 State.regs[dstreg2] -= State.regs[srcreg2];
6374}
6375
6376// 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
63778.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_sub
6378"mov_sub"
6379*am33
6380{
6381 int dstreg1, dstreg2;
6382
6383 PC = cia;
6384 dstreg1 = translate_rreg (SD_, RN1);
6385 dstreg2 = translate_rreg (SD_, RN2);
6386
6387 State.regs[dstreg1] = EXTEND4 (IMM4A);
6388 State.regs[dstreg2] -= EXTEND4 (IMM4);
6389}
6390
6391// 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
63928.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_cmp
6393"mov_cmp"
6394*am33
6395{
6396 int srcreg2, dstreg1, dstreg2;
6397
6398 PC = cia;
6399 srcreg2 = translate_rreg (SD_, RM2);
6400 dstreg1 = translate_rreg (SD_, RN1);
6401 dstreg2 = translate_rreg (SD_, RN2);
6402
6403 State.regs[dstreg1] = EXTEND4 (IMM4A);
6404 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6405}
6406
6407// 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
64088.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_cmp
6409"mov_cmp"
6410*am33
6411{
6412 int dstreg1, dstreg2;
6413
6414 PC = cia;
6415 dstreg1 = translate_rreg (SD_, RN1);
6416 dstreg2 = translate_rreg (SD_, RN2);
6417
6418 State.regs[dstreg1] = EXTEND4 (IMM4A);
6419 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6420}
6421
6422// 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
64238.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_mov
6424"mov_mov"
6425*am33
6426{
6427 int srcreg2, dstreg1, dstreg2;
6428
6429 PC = cia;
6430 srcreg2 = translate_rreg (SD_, RM2);
6431 dstreg1 = translate_rreg (SD_, RN1);
6432 dstreg2 = translate_rreg (SD_, RN2);
6433
6434 State.regs[dstreg1] = EXTEND4 (IMM4A);
6435 State.regs[dstreg2] = State.regs[srcreg2];
6436}
6437
6438// 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
64398.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_mov
6440"mov_mov"
6441*am33
6442{
6443 int dstreg1, dstreg2;
6444
6445 PC = cia;
6446 dstreg1 = translate_rreg (SD_, RN1);
6447 dstreg2 = translate_rreg (SD_, RN2);
6448
6449 State.regs[dstreg1] = EXTEND4 (IMM4A);
6450 State.regs[dstreg2] = EXTEND4 (IMM4);
6451}
6452
6453// 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
64548.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asr
6455"mov_asr"
6456*am33
6457{
6458 int srcreg2, dstreg1, dstreg2;
6459 signed int temp;
6460
6461 PC = cia;
6462 srcreg2 = translate_rreg (SD_, RM2);
6463 dstreg1 = translate_rreg (SD_, RN1);
6464 dstreg2 = translate_rreg (SD_, RN2);
6465
6466 State.regs[dstreg1] = EXTEND4 (IMM4A);
6467 temp = State.regs[dstreg2];
6468 temp >>= State.regs[srcreg2];
6469 State.regs[dstreg2] = temp;
6470}
6471
6472// 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
64738.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asr
6474"mov_asr"
6475*am33
6476{
6477 int dstreg1, dstreg2;
6478 signed int temp;
6479
6480 PC = cia;
6481 dstreg1 = translate_rreg (SD_, RN1);
6482 dstreg2 = translate_rreg (SD_, RN2);
6483
6484 State.regs[dstreg1] = EXTEND4 (IMM4A);
6485 temp = State.regs[dstreg2];
6486 temp >>= IMM4;
6487 State.regs[dstreg2] = temp;
6488}
6489
6490// 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
64918.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_lsr
6492"mov_lsr"
6493*am33
6494{
6495 int srcreg2, dstreg1, dstreg2;
6496
6497 PC = cia;
6498 srcreg2 = translate_rreg (SD_, RM2);
6499 dstreg1 = translate_rreg (SD_, RN1);
6500 dstreg2 = translate_rreg (SD_, RN2);
6501
6502 State.regs[dstreg1] = EXTEND4 (IMM4A);
6503 State.regs[dstreg2] >>= State.regs[srcreg2];
6504}
6505
6506// 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
65078.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_lsr
6508"mov_lsr"
6509*am33
6510{
6511 int dstreg1, dstreg2;
6512 signed int temp;
6513
6514 PC = cia;
6515 dstreg1 = translate_rreg (SD_, RN1);
6516 dstreg2 = translate_rreg (SD_, RN2);
6517
6518 State.regs[dstreg1] = EXTEND4 (IMM4A);
6519 State.regs[dstreg2] >>= IMM4;
6520}
6521
6522
6523// 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
65248.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asl
6525"mov_asl"
6526*am33
6527{
6528 int srcreg2, dstreg1, dstreg2;
6529
6530 PC = cia;
6531 srcreg2 = translate_rreg (SD_, RM2);
6532 dstreg1 = translate_rreg (SD_, RN1);
6533 dstreg2 = translate_rreg (SD_, RN2);
6534
6535 State.regs[dstreg1] = EXTEND4 (IMM4A);
6536 State.regs[dstreg2] <<= State.regs[srcreg2];
6537}
6538
6539// 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
65408.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asl
6541"mov_asl"
6542*am33
6543{
6544 int dstreg1, dstreg2;
6545 signed int temp;
6546
6547 PC = cia;
6548 dstreg1 = translate_rreg (SD_, RN1);
6549 dstreg2 = translate_rreg (SD_, RN2);
6550
6551 State.regs[dstreg1] = EXTEND4 (IMM4A);
6552 State.regs[dstreg2] <<= IMM4;
6553}
6554
6555// 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
65568.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_add
6557"and_add"
6558*am33
6559{
6560 int srcreg1, srcreg2, dstreg1, dstreg2;
6561
6562 PC = cia;
6563 srcreg1 = translate_rreg (SD_, RM1);
6564 srcreg2 = translate_rreg (SD_, RM2);
6565 dstreg1 = translate_rreg (SD_, RN1);
6566 dstreg2 = translate_rreg (SD_, RN2);
6567
6568 State.regs[dstreg1] &= State.regs[srcreg1];
6569 State.regs[dstreg2] += State.regs[srcreg2];
6570}
6571
6572// 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
65738.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_add
6574"and_add"
6575*am33
6576{
6577 int srcreg1, dstreg1, dstreg2;
6578
6579 PC = cia;
6580 srcreg1 = translate_rreg (SD_, RM1);
6581 dstreg1 = translate_rreg (SD_, RN1);
6582 dstreg2 = translate_rreg (SD_, RN2);
6583
6584 State.regs[dstreg1] &= State.regs[srcreg1];
6585 State.regs[dstreg2] += EXTEND4 (IMM4);
6586}
6587
6588// 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
65898.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_sub
6590"and_sub"
6591*am33
6592{
6593 int srcreg1, srcreg2, dstreg1, dstreg2;
6594
6595 PC = cia;
6596 srcreg1 = translate_rreg (SD_, RM1);
6597 srcreg2 = translate_rreg (SD_, RM2);
6598 dstreg1 = translate_rreg (SD_, RN1);
6599 dstreg2 = translate_rreg (SD_, RN2);
6600
6601 State.regs[dstreg1] &= State.regs[srcreg1];
6602 State.regs[dstreg2] -= State.regs[srcreg2];
6603}
6604
6605// 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
66068.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_sub
6607"and_sub"
6608*am33
6609{
6610 int srcreg1, dstreg1, dstreg2;
6611
6612 PC = cia;
6613 srcreg1 = translate_rreg (SD_, RM1);
6614 dstreg1 = translate_rreg (SD_, RN1);
6615 dstreg2 = translate_rreg (SD_, RN2);
6616
6617 State.regs[dstreg1] &= State.regs[srcreg1];
6618 State.regs[dstreg2] -= EXTEND4 (IMM4);
6619}
6620
6621// 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
66228.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_cmp
6623"and_cmp"
6624*am33
6625{
6626 int srcreg1, srcreg2, dstreg1, dstreg2;
6627
6628 PC = cia;
6629 srcreg1 = translate_rreg (SD_, RM1);
6630 srcreg2 = translate_rreg (SD_, RM2);
6631 dstreg1 = translate_rreg (SD_, RN1);
6632 dstreg2 = translate_rreg (SD_, RN2);
6633
6634 State.regs[dstreg1] &= State.regs[srcreg1];
6635 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6636}
6637
6638// 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
66398.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_cmp
6640"and_cmp"
6641*am33
6642{
6643 int srcreg1, dstreg1, dstreg2;
6644
6645 PC = cia;
6646 srcreg1 = translate_rreg (SD_, RM1);
6647 dstreg1 = translate_rreg (SD_, RN1);
6648 dstreg2 = translate_rreg (SD_, RN2);
6649
6650 State.regs[dstreg1] &= State.regs[srcreg1];
6651 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6652}
6653
6654// 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
66558.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_mov
6656"and_mov"
6657*am33
6658{
6659 int srcreg1, srcreg2, dstreg1, dstreg2;
6660
6661 PC = cia;
6662 srcreg1 = translate_rreg (SD_, RM1);
6663 srcreg2 = translate_rreg (SD_, RM2);
6664 dstreg1 = translate_rreg (SD_, RN1);
6665 dstreg2 = translate_rreg (SD_, RN2);
6666
6667 State.regs[dstreg1] &= State.regs[srcreg1];
6668 State.regs[dstreg2] = State.regs[srcreg2];
6669}
6670
6671// 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
66728.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_mov
6673"and_mov"
6674*am33
6675{
6676 int srcreg1, dstreg1, dstreg2;
6677
6678 PC = cia;
6679 srcreg1 = translate_rreg (SD_, RM1);
6680 dstreg1 = translate_rreg (SD_, RN1);
6681 dstreg2 = translate_rreg (SD_, RN2);
6682
6683 State.regs[dstreg1] &= State.regs[srcreg1];
6684 State.regs[dstreg2] = EXTEND4 (IMM4);
6685}
6686
6687// 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
66888.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asr
6689"and_asr"
6690*am33
6691{
6692 int srcreg1, srcreg2, dstreg1, dstreg2;
6693 signed int temp;
6694
6695 PC = cia;
6696 srcreg1 = translate_rreg (SD_, RM1);
6697 srcreg2 = translate_rreg (SD_, RM2);
6698 dstreg1 = translate_rreg (SD_, RN1);
6699 dstreg2 = translate_rreg (SD_, RN2);
6700
6701 State.regs[dstreg1] &= State.regs[srcreg1];
6702 temp = State.regs[dstreg2];
6703 temp >>= State.regs[srcreg2];
6704 State.regs[dstreg2] = temp;
6705}
6706
6707// 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
67088.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asr
6709"and_asr"
6710*am33
6711{
6712 int srcreg1, dstreg1, dstreg2;
6713 signed int temp;
6714
6715 PC = cia;
6716 srcreg1 = translate_rreg (SD_, RM1);
6717 dstreg1 = translate_rreg (SD_, RN1);
6718 dstreg2 = translate_rreg (SD_, RN2);
6719
6720 State.regs[dstreg1] &= State.regs[srcreg1];
6721 temp = State.regs[dstreg2];
6722 temp >>= IMM4;
6723 State.regs[dstreg2] = temp;
6724}
6725
6726// 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
67278.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_lsr
6728"and_lsr"
6729*am33
6730{
6731 int srcreg1, srcreg2, dstreg1, dstreg2;
6732
6733 PC = cia;
6734 srcreg1 = translate_rreg (SD_, RM1);
6735 srcreg2 = translate_rreg (SD_, RM2);
6736 dstreg1 = translate_rreg (SD_, RN1);
6737 dstreg2 = translate_rreg (SD_, RN2);
6738
6739 State.regs[dstreg1] &= State.regs[srcreg1];
6740 State.regs[dstreg2] >>= State.regs[srcreg2];
6741}
6742
6743// 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
67448.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_lsr
6745"and_lsr"
6746*am33
6747{
6748 int srcreg1, dstreg1, dstreg2;
6749 signed int temp;
6750
6751 PC = cia;
6752 srcreg1 = translate_rreg (SD_, RM1);
6753 dstreg1 = translate_rreg (SD_, RN1);
6754 dstreg2 = translate_rreg (SD_, RN2);
6755
6756 State.regs[dstreg1] &= State.regs[srcreg1];
6757 State.regs[dstreg2] >>= IMM4;
6758}
6759
6760
6761// 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
67628.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asl
6763"and_asl"
6764*am33
6765{
6766 int srcreg1, srcreg2, dstreg1, dstreg2;
6767
6768 PC = cia;
6769 srcreg1 = translate_rreg (SD_, RM1);
6770 srcreg2 = translate_rreg (SD_, RM2);
6771 dstreg1 = translate_rreg (SD_, RN1);
6772 dstreg2 = translate_rreg (SD_, RN2);
6773
6774 State.regs[dstreg1] &= State.regs[srcreg1];
6775 State.regs[dstreg2] <<= State.regs[srcreg2];
6776}
6777
6778// 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
67798.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asl
6780"and_asl"
6781*am33
6782{
6783 int srcreg1, dstreg1, dstreg2;
6784 signed int temp;
6785
6786 PC = cia;
6787 srcreg1 = translate_rreg (SD_, RM1);
6788 dstreg1 = translate_rreg (SD_, RN1);
6789 dstreg2 = translate_rreg (SD_, RN2);
6790
6791 State.regs[dstreg1] &= State.regs[srcreg1];
6792 State.regs[dstreg2] <<= IMM4;
6793}
6794
6795// 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
67968.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_add
6797"dmach_add"
6798*am33
6799{
6800 int srcreg1, srcreg2, dstreg1, dstreg2;
6801 long temp, temp2, sum;
6802
6803 PC = cia;
6804 srcreg1 = translate_rreg (SD_, RM1);
6805 srcreg2 = translate_rreg (SD_, RM2);
6806 dstreg1 = translate_rreg (SD_, RN1);
6807 dstreg2 = translate_rreg (SD_, RN2);
6808
6809 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6810 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6811 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6812 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6813 sum = temp + temp2 + State.regs[REG_MCRL];
6814
6815 State.regs[dstreg1] = sum;
6816 State.regs[dstreg2] += State.regs[srcreg2];
6817}
6818
6819// 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
68208.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_add
6821"dmach_add"
6822*am33
6823{
6824 int srcreg1, dstreg1, dstreg2;
6825 long temp, temp2, sum;
6826
6827 PC = cia;
6828 srcreg1 = translate_rreg (SD_, RM1);
6829 dstreg1 = translate_rreg (SD_, RN1);
6830 dstreg2 = translate_rreg (SD_, RN2);
6831
6832 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6833 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6834 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6835 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6836 sum = temp + temp2 + State.regs[REG_MCRL];
6837
6838 State.regs[dstreg1] = sum;
6839 State.regs[dstreg2] += EXTEND4 (IMM4);
6840}
6841
6842// 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
68438.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_sub
6844"dmach_sub"
6845*am33
6846{
6847 int srcreg1, srcreg2, dstreg1, dstreg2;
6848 long temp, temp2, sum;
6849
6850 PC = cia;
6851 srcreg1 = translate_rreg (SD_, RM1);
6852 srcreg2 = translate_rreg (SD_, RM2);
6853 dstreg1 = translate_rreg (SD_, RN1);
6854 dstreg2 = translate_rreg (SD_, RN2);
6855
6856 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6857 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6858 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6859 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6860 sum = temp + temp2 + State.regs[REG_MCRL];
6861
6862 State.regs[dstreg1] = sum;
6863 State.regs[dstreg2] -= State.regs[srcreg2];
6864}
6865
6866// 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
68678.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_sub
6868"dmach_sub"
6869*am33
6870{
6871 int srcreg1, dstreg1, dstreg2;
6872 long temp, temp2, sum;
6873
6874 PC = cia;
6875 srcreg1 = translate_rreg (SD_, RM1);
6876 dstreg1 = translate_rreg (SD_, RN1);
6877 dstreg2 = translate_rreg (SD_, RN2);
6878
6879 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6880 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6881 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6882 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6883 sum = temp + temp2 + State.regs[REG_MCRL];
6884
6885 State.regs[dstreg1] = sum;
6886 State.regs[dstreg2] -= EXTEND4 (IMM4);
6887}
6888
6889// 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
68908.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_cmp
6891"dmach_cmp"
6892*am33
6893{
6894 int srcreg1, srcreg2, dstreg1, dstreg2;
6895 long temp, temp2, sum;
6896
6897 PC = cia;
6898 srcreg1 = translate_rreg (SD_, RM1);
6899 srcreg2 = translate_rreg (SD_, RM2);
6900 dstreg1 = translate_rreg (SD_, RN1);
6901 dstreg2 = translate_rreg (SD_, RN2);
6902
6903 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6904 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6905 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6906 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6907 sum = temp + temp2 + State.regs[REG_MCRL];
6908
6909 State.regs[dstreg1] = sum;
6910 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6911}
6912
6913// 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
69148.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_cmp
6915"dmach_cmp"
6916*am33
6917{
6918 int srcreg1, dstreg1, dstreg2;
6919 long temp, temp2, sum;
6920
6921 PC = cia;
6922 srcreg1 = translate_rreg (SD_, RM1);
6923 dstreg1 = translate_rreg (SD_, RN1);
6924 dstreg2 = translate_rreg (SD_, RN2);
6925
6926 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6927 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6928 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6929 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6930 sum = temp + temp2 + State.regs[REG_MCRL];
6931
6932 State.regs[dstreg1] = sum;
6933 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6934}
6935
6936// 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
69378.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_mov
6938"dmach_mov"
6939*am33
6940{
6941 int srcreg1, srcreg2, dstreg1, dstreg2;
6942 long temp, temp2, sum;
6943
6944 PC = cia;
6945 srcreg1 = translate_rreg (SD_, RM1);
6946 srcreg2 = translate_rreg (SD_, RM2);
6947 dstreg1 = translate_rreg (SD_, RN1);
6948 dstreg2 = translate_rreg (SD_, RN2);
6949
6950 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6951 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6952 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6953 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6954 sum = temp + temp2 + State.regs[REG_MCRL];
6955
6956 State.regs[dstreg1] = sum;
6957 State.regs[dstreg2] = State.regs[srcreg2];
6958}
6959
6960// 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
69618.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_mov
6962"dmach_mov"
6963*am33
6964{
6965 int srcreg1, dstreg1, dstreg2;
6966 long temp, temp2, sum;
6967
6968 PC = cia;
6969 srcreg1 = translate_rreg (SD_, RM1);
6970 dstreg1 = translate_rreg (SD_, RN1);
6971 dstreg2 = translate_rreg (SD_, RN2);
6972
6973 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6974 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6975 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6976 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6977 sum = temp + temp2 + State.regs[REG_MCRL];
6978
6979 State.regs[dstreg1] = sum;
6980 State.regs[dstreg2] = EXTEND4 (IMM4);
6981}
6982
6983// 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
69848.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asr
6985"dmach_asr"
6986*am33
6987{
6988 int srcreg1, srcreg2, dstreg1, dstreg2;
6989 long temp, temp2, sum;
6990
6991 PC = cia;
6992 srcreg1 = translate_rreg (SD_, RM1);
6993 srcreg2 = translate_rreg (SD_, RM2);
6994 dstreg1 = translate_rreg (SD_, RN1);
6995 dstreg2 = translate_rreg (SD_, RN2);
6996
6997 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6998 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6999 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7000 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7001 sum = temp + temp2 + State.regs[REG_MCRL];
7002
7003 State.regs[dstreg1] = sum;
7004 temp = State.regs[dstreg2];
7005 temp >>= State.regs[srcreg2];
7006 State.regs[dstreg2] = temp;
7007}
7008
7009// 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
70108.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asr
7011"dmach_asr"
7012*am33
7013{
7014 int srcreg1, dstreg1, dstreg2;
7015 long temp, temp2, sum;
7016
7017 PC = cia;
7018 srcreg1 = translate_rreg (SD_, RM1);
7019 dstreg1 = translate_rreg (SD_, RN1);
7020 dstreg2 = translate_rreg (SD_, RN2);
7021
7022 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7023 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7024 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7025 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7026 sum = temp + temp2 + State.regs[REG_MCRL];
7027
7028 State.regs[dstreg1] = sum;
7029 temp = State.regs[dstreg2];
7030 temp >>= IMM4;
7031 State.regs[dstreg2] = temp;
7032}
7033
7034// 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
70358.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_lsr
7036"dmach_lsr"
7037*am33
7038{
7039 int srcreg1, srcreg2, dstreg1, dstreg2;
7040 long temp, temp2, sum;
7041
7042 PC = cia;
7043 srcreg1 = translate_rreg (SD_, RM1);
7044 srcreg2 = translate_rreg (SD_, RM2);
7045 dstreg1 = translate_rreg (SD_, RN1);
7046 dstreg2 = translate_rreg (SD_, RN2);
7047
7048 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7049 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7050 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7051 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7052 sum = temp + temp2 + State.regs[REG_MCRL];
7053
7054 State.regs[dstreg1] = sum;
7055 State.regs[dstreg2] >>= State.regs[srcreg2];
7056}
7057
7058// 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
70598.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_lsr
7060"dmach_lsr"
7061*am33
7062{
7063 int srcreg1, dstreg1, dstreg2;
7064 long temp, temp2, sum;
7065
7066 PC = cia;
7067 srcreg1 = translate_rreg (SD_, RM1);
7068 dstreg1 = translate_rreg (SD_, RN1);
7069 dstreg2 = translate_rreg (SD_, RN2);
7070
7071 State.regs[dstreg2] >>= IMM4;
7072}
7073
7074
7075// 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
70768.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asl
7077"dmach_asl"
7078*am33
7079{
7080 int srcreg1, srcreg2, dstreg1, dstreg2;
7081 long temp, temp2, sum;
7082
7083 PC = cia;
7084 srcreg1 = translate_rreg (SD_, RM1);
7085 srcreg2 = translate_rreg (SD_, RM2);
7086 dstreg1 = translate_rreg (SD_, RN1);
7087 dstreg2 = translate_rreg (SD_, RN2);
7088
7089 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7090 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7091 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7092 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7093 sum = temp + temp2 + State.regs[REG_MCRL];
7094
7095 State.regs[dstreg1] = sum;
7096 State.regs[dstreg2] <<= State.regs[srcreg2];
7097}
7098
7099// 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
71008.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asl
7101"dmach_asl"
7102*am33
7103{
7104 int srcreg1, dstreg1, dstreg2;
7105 long temp, temp2, sum;
7106
7107 PC = cia;
7108 srcreg1 = translate_rreg (SD_, RM1);
7109 dstreg1 = translate_rreg (SD_, RN1);
7110 dstreg2 = translate_rreg (SD_, RN2);
7111
7112 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7113 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7114 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7115 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7116 sum = temp + temp2 + State.regs[REG_MCRL];
7117
7118 State.regs[dstreg1] = sum;
7119 State.regs[dstreg2] <<= IMM4;
7120}
7121
7122// 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
71238.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_add
7124"xor_add"
7125*am33
7126{
7127 int srcreg1, srcreg2, dstreg1, dstreg2;
7128
7129 PC = cia;
7130 srcreg1 = translate_rreg (SD_, RM1);
7131 srcreg2 = translate_rreg (SD_, RM2);
7132 dstreg1 = translate_rreg (SD_, RN1);
7133 dstreg2 = translate_rreg (SD_, RN2);
7134
7135 State.regs[dstreg1] ^= State.regs[srcreg1];
7136 State.regs[dstreg2] += State.regs[srcreg2];
7137}
7138
7139// 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
71408.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_add
7141"xor_add"
7142*am33
7143{
7144 int srcreg1, dstreg1, dstreg2;
7145
7146 PC = cia;
7147 srcreg1 = translate_rreg (SD_, RM1);
7148 dstreg1 = translate_rreg (SD_, RN1);
7149 dstreg2 = translate_rreg (SD_, RN2);
7150
7151 State.regs[dstreg1] ^= State.regs[srcreg1];
7152 State.regs[dstreg2] += EXTEND4 (IMM4);
7153}
7154
7155// 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
71568.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_sub
7157"xor_sub"
7158*am33
7159{
7160 int srcreg1, srcreg2, dstreg1, dstreg2;
7161
7162 PC = cia;
7163 srcreg1 = translate_rreg (SD_, RM1);
7164 srcreg2 = translate_rreg (SD_, RM2);
7165 dstreg1 = translate_rreg (SD_, RN1);
7166 dstreg2 = translate_rreg (SD_, RN2);
7167
7168 State.regs[dstreg1] ^= State.regs[srcreg1];
7169 State.regs[dstreg2] -= State.regs[srcreg2];
7170}
7171
7172// 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
71738.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_sub
7174"xor_sub"
7175*am33
7176{
7177 int srcreg1, dstreg1, dstreg2;
7178
7179 PC = cia;
7180 srcreg1 = translate_rreg (SD_, RM1);
7181 dstreg1 = translate_rreg (SD_, RN1);
7182 dstreg2 = translate_rreg (SD_, RN2);
7183
7184 State.regs[dstreg1] ^= State.regs[srcreg1];
7185 State.regs[dstreg2] -= EXTEND4 (IMM4);
7186}
7187
7188// 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
71898.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_cmp
7190"xor_cmp"
7191*am33
7192{
7193 int srcreg1, srcreg2, dstreg1, dstreg2;
7194
7195 PC = cia;
7196 srcreg1 = translate_rreg (SD_, RM1);
7197 srcreg2 = translate_rreg (SD_, RM2);
7198 dstreg1 = translate_rreg (SD_, RN1);
7199 dstreg2 = translate_rreg (SD_, RN2);
7200
7201 State.regs[dstreg1] ^= State.regs[srcreg1];
7202 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7203}
7204
7205// 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
72068.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_cmp
7207"xor_cmp"
7208*am33
7209{
7210 int srcreg1, dstreg1, dstreg2;
7211
7212 PC = cia;
7213 srcreg1 = translate_rreg (SD_, RM1);
7214 dstreg1 = translate_rreg (SD_, RN1);
7215 dstreg2 = translate_rreg (SD_, RN2);
7216
7217 State.regs[dstreg1] ^= State.regs[srcreg1];
7218 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7219}
7220
7221// 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
72228.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_mov
7223"xor_mov"
7224*am33
7225{
7226 int srcreg1, srcreg2, dstreg1, dstreg2;
7227
7228 PC = cia;
7229 srcreg1 = translate_rreg (SD_, RM1);
7230 srcreg2 = translate_rreg (SD_, RM2);
7231 dstreg1 = translate_rreg (SD_, RN1);
7232 dstreg2 = translate_rreg (SD_, RN2);
7233
7234 State.regs[dstreg1] ^= State.regs[srcreg1];
7235 State.regs[dstreg2] = State.regs[srcreg2];
7236}
7237
7238// 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
72398.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_mov
7240"xor_mov"
7241*am33
7242{
7243 int srcreg1, dstreg1, dstreg2;
7244
7245 PC = cia;
7246 srcreg1 = translate_rreg (SD_, RM1);
7247 dstreg1 = translate_rreg (SD_, RN1);
7248 dstreg2 = translate_rreg (SD_, RN2);
7249
7250 State.regs[dstreg1] ^= State.regs[srcreg1];
7251 State.regs[dstreg2] = EXTEND4 (IMM4);
7252}
7253
7254// 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
72558.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asr
7256"xor_asr"
7257*am33
7258{
7259 int srcreg1, srcreg2, dstreg1, dstreg2;
7260 signed int temp;
7261
7262 PC = cia;
7263 srcreg1 = translate_rreg (SD_, RM1);
7264 srcreg2 = translate_rreg (SD_, RM2);
7265 dstreg1 = translate_rreg (SD_, RN1);
7266 dstreg2 = translate_rreg (SD_, RN2);
7267
7268 State.regs[dstreg1] ^= State.regs[srcreg1];
7269 temp = State.regs[dstreg2];
7270 temp >>= State.regs[srcreg2];
7271 State.regs[dstreg2] = temp;
7272}
7273
7274// 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
72758.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asr
7276"xor_asr"
7277*am33
7278{
7279 int srcreg1, dstreg1, dstreg2;
7280 signed int temp;
7281
7282 PC = cia;
7283 srcreg1 = translate_rreg (SD_, RM1);
7284 dstreg1 = translate_rreg (SD_, RN1);
7285 dstreg2 = translate_rreg (SD_, RN2);
7286
7287 State.regs[dstreg1] ^= State.regs[srcreg1];
7288 temp = State.regs[dstreg2];
7289 temp >>= IMM4;
7290 State.regs[dstreg2] = temp;
7291}
7292
7293// 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
72948.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_lsr
7295"xor_lsr"
7296*am33
7297{
7298 int srcreg1, srcreg2, dstreg1, dstreg2;
7299
7300 PC = cia;
7301 srcreg1 = translate_rreg (SD_, RM1);
7302 srcreg2 = translate_rreg (SD_, RM2);
7303 dstreg1 = translate_rreg (SD_, RN1);
7304 dstreg2 = translate_rreg (SD_, RN2);
7305
7306 State.regs[dstreg1] ^= State.regs[srcreg1];
7307 State.regs[dstreg2] >>= State.regs[srcreg2];
7308}
7309
7310// 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
73118.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_lsr
7312"xor_lsr"
7313*am33
7314{
7315 int srcreg1, dstreg1, dstreg2;
7316 signed int temp;
7317
7318 PC = cia;
7319 srcreg1 = translate_rreg (SD_, RM1);
7320 dstreg1 = translate_rreg (SD_, RN1);
7321 dstreg2 = translate_rreg (SD_, RN2);
7322
7323 State.regs[dstreg1] ^= State.regs[srcreg1];
7324 State.regs[dstreg2] >>= IMM4;
7325}
7326
7327
7328// 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
73298.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asl
7330"xor_asl"
7331*am33
7332{
7333 int srcreg1, srcreg2, dstreg1, dstreg2;
7334
7335 PC = cia;
7336 srcreg1 = translate_rreg (SD_, RM1);
7337 srcreg2 = translate_rreg (SD_, RM2);
7338 dstreg1 = translate_rreg (SD_, RN1);
7339 dstreg2 = translate_rreg (SD_, RN2);
7340
7341 State.regs[dstreg1] ^= State.regs[srcreg1];
7342 State.regs[dstreg2] <<= State.regs[srcreg2];
7343}
7344
7345// 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
73468.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asl
7347"xor_asl"
7348*am33
7349{
7350 int srcreg1, dstreg1, dstreg2;
7351 signed int temp;
7352
7353 PC = cia;
7354 srcreg1 = translate_rreg (SD_, RM1);
7355 dstreg1 = translate_rreg (SD_, RN1);
7356 dstreg2 = translate_rreg (SD_, RN2);
7357
7358 State.regs[dstreg1] ^= State.regs[srcreg1];
7359 State.regs[dstreg2] <<= IMM4;
7360}
7361
7362// 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
73638.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_add
7364"swhw_add"
7365*am33
7366{
7367 int srcreg1, srcreg2, dstreg1, dstreg2;
7368
7369 PC = cia;
7370 srcreg1 = translate_rreg (SD_, RM1);
7371 srcreg2 = translate_rreg (SD_, RM2);
7372 dstreg1 = translate_rreg (SD_, RN1);
7373 dstreg2 = translate_rreg (SD_, RN2);
7374
7375 State.regs[dstreg1] ^= State.regs[srcreg1];
7376 State.regs[dstreg2] += State.regs[srcreg2];
7377}
7378
7379// 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
73808.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_add
7381"swhw_add"
7382*am33
7383{
7384 int srcreg1, dstreg1, dstreg2;
7385
7386 PC = cia;
7387 srcreg1 = translate_rreg (SD_, RM1);
7388 dstreg1 = translate_rreg (SD_, RN1);
7389 dstreg2 = translate_rreg (SD_, RN2);
7390
7391 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7392 | ((State.regs[srcreg1] >> 16) & 0xffff));
7393 State.regs[dstreg2] += EXTEND4 (IMM4);
7394}
7395
7396// 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
73978.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_sub
7398"swhw_sub"
7399*am33
7400{
7401 int srcreg1, srcreg2, dstreg1, dstreg2;
7402
7403 PC = cia;
7404 srcreg1 = translate_rreg (SD_, RM1);
7405 srcreg2 = translate_rreg (SD_, RM2);
7406 dstreg1 = translate_rreg (SD_, RN1);
7407 dstreg2 = translate_rreg (SD_, RN2);
7408
7409 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7410 | ((State.regs[srcreg1] >> 16) & 0xffff));
7411 State.regs[dstreg2] -= State.regs[srcreg2];
7412}
7413
7414// 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
74158.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_sub
7416"swhw_sub"
7417*am33
7418{
7419 int srcreg1, dstreg1, dstreg2;
7420
7421 PC = cia;
7422 srcreg1 = translate_rreg (SD_, RM1);
7423 dstreg1 = translate_rreg (SD_, RN1);
7424 dstreg2 = translate_rreg (SD_, RN2);
7425
7426 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7427 | ((State.regs[srcreg1] >> 16) & 0xffff));
7428 State.regs[dstreg2] -= EXTEND4 (IMM4);
7429}
7430
7431// 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
74328.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_cmp
7433"swhw_cmp"
7434*am33
7435{
7436 int srcreg1, srcreg2, dstreg1, dstreg2;
7437
7438 PC = cia;
7439 srcreg1 = translate_rreg (SD_, RM1);
7440 srcreg2 = translate_rreg (SD_, RM2);
7441 dstreg1 = translate_rreg (SD_, RN1);
7442 dstreg2 = translate_rreg (SD_, RN2);
7443
7444 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7445 | ((State.regs[srcreg1] >> 16) & 0xffff));
7446 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7447}
7448
7449// 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
74508.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_cmp
7451"swhw_cmp"
7452*am33
7453{
7454 int srcreg1, dstreg1, dstreg2;
7455
7456 PC = cia;
7457 srcreg1 = translate_rreg (SD_, RM1);
7458 dstreg1 = translate_rreg (SD_, RN1);
7459 dstreg2 = translate_rreg (SD_, RN2);
7460
7461 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7462 | ((State.regs[srcreg1] >> 16) & 0xffff));
7463 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7464}
7465
7466// 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
74678.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_mov
7468"swhw_mov"
7469*am33
7470{
7471 int srcreg1, srcreg2, dstreg1, dstreg2;
7472
7473 PC = cia;
7474 srcreg1 = translate_rreg (SD_, RM1);
7475 srcreg2 = translate_rreg (SD_, RM2);
7476 dstreg1 = translate_rreg (SD_, RN1);
7477 dstreg2 = translate_rreg (SD_, RN2);
7478
7479 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7480 | ((State.regs[srcreg1] >> 16) & 0xffff));
7481 State.regs[dstreg2] = State.regs[srcreg2];
7482}
7483
7484// 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
74858.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_mov
7486"swhw_mov"
7487*am33
7488{
7489 int srcreg1, dstreg1, dstreg2;
7490
7491 PC = cia;
7492 srcreg1 = translate_rreg (SD_, RM1);
7493 dstreg1 = translate_rreg (SD_, RN1);
7494 dstreg2 = translate_rreg (SD_, RN2);
7495
7496 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7497 | ((State.regs[srcreg1] >> 16) & 0xffff));
7498 State.regs[dstreg2] = EXTEND4 (IMM4);
7499}
7500
7501// 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
75028.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asr
7503"swhw_asr"
7504*am33
7505{
7506 int srcreg1, srcreg2, dstreg1, dstreg2;
7507 signed int temp;
7508
7509 PC = cia;
7510 srcreg1 = translate_rreg (SD_, RM1);
7511 srcreg2 = translate_rreg (SD_, RM2);
7512 dstreg1 = translate_rreg (SD_, RN1);
7513 dstreg2 = translate_rreg (SD_, RN2);
7514
7515 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7516 | ((State.regs[srcreg1] >> 16) & 0xffff));
7517 temp = State.regs[dstreg2];
7518 temp >>= State.regs[srcreg2];
7519 State.regs[dstreg2] = temp;
7520}
7521
7522// 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
75238.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asr
7524"swhw_asr"
7525*am33
7526{
7527 int srcreg1, dstreg1, dstreg2;
7528 signed int temp;
7529
7530 PC = cia;
7531 srcreg1 = translate_rreg (SD_, RM1);
7532 dstreg1 = translate_rreg (SD_, RN1);
7533 dstreg2 = translate_rreg (SD_, RN2);
7534
7535 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7536 | ((State.regs[srcreg1] >> 16) & 0xffff));
7537 temp = State.regs[dstreg2];
7538 temp >>= IMM4;
7539 State.regs[dstreg2] = temp;
7540}
7541
7542// 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
75438.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_lsr
7544"swhw_lsr"
7545*am33
7546{
7547 int srcreg1, srcreg2, dstreg1, dstreg2;
7548
7549 PC = cia;
7550 srcreg1 = translate_rreg (SD_, RM1);
7551 srcreg2 = translate_rreg (SD_, RM2);
7552 dstreg1 = translate_rreg (SD_, RN1);
7553 dstreg2 = translate_rreg (SD_, RN2);
7554
7555 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7556 | ((State.regs[srcreg1] >> 16) & 0xffff));
7557 State.regs[dstreg2] >>= State.regs[srcreg2];
7558}
7559
7560// 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
75618.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_lsr
7562"swhw_lsr"
7563*am33
7564{
7565 int srcreg1, dstreg1, dstreg2;
7566 signed int temp;
7567
7568 PC = cia;
7569 srcreg1 = translate_rreg (SD_, RM1);
7570 dstreg1 = translate_rreg (SD_, RN1);
7571 dstreg2 = translate_rreg (SD_, RN2);
7572
7573 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7574 | ((State.regs[srcreg1] >> 16) & 0xffff));
7575 State.regs[dstreg2] >>= IMM4;
7576}
7577
7578
7579// 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
75808.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asl
7581"swhw_asl"
7582*am33
7583{
7584 int srcreg1, srcreg2, dstreg1, dstreg2;
7585
7586 PC = cia;
7587 srcreg1 = translate_rreg (SD_, RM1);
7588 srcreg2 = translate_rreg (SD_, RM2);
7589 dstreg1 = translate_rreg (SD_, RN1);
7590 dstreg2 = translate_rreg (SD_, RN2);
7591
7592 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7593 | ((State.regs[srcreg1] >> 16) & 0xffff));
7594 State.regs[dstreg2] <<= State.regs[srcreg2];
7595}
7596
7597// 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
75988.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asl
7599"swhw_asl"
7600*am33
7601{
7602 int srcreg1, dstreg1, dstreg2;
7603 signed int temp;
7604
7605 PC = cia;
7606 srcreg1 = translate_rreg (SD_, RM1);
7607 dstreg1 = translate_rreg (SD_, RN1);
7608 dstreg2 = translate_rreg (SD_, RN2);
7609
7610 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7611 | ((State.regs[srcreg1] >> 16) & 0xffff));
7612 State.regs[dstreg2] <<= IMM4;
7613}
7614
7615// 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
76168.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_add
7617"or_add"
7618*am33
7619{
7620 int srcreg1, srcreg2, dstreg1, dstreg2;
7621
7622 PC = cia;
7623 srcreg1 = translate_rreg (SD_, RM1);
7624 srcreg2 = translate_rreg (SD_, RM2);
7625 dstreg1 = translate_rreg (SD_, RN1);
7626 dstreg2 = translate_rreg (SD_, RN2);
7627
7628 State.regs[dstreg1] |= State.regs[srcreg1];
7629 State.regs[dstreg2] += State.regs[srcreg2];
7630}
7631
7632// 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
76338.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_add
7634"or_add"
7635*am33
7636{
7637 int srcreg1, dstreg1, dstreg2;
7638
7639 PC = cia;
7640 srcreg1 = translate_rreg (SD_, RM1);
7641 dstreg1 = translate_rreg (SD_, RN1);
7642 dstreg2 = translate_rreg (SD_, RN2);
7643
7644 State.regs[dstreg1] |= State.regs[srcreg1];
7645 State.regs[dstreg2] += EXTEND4 (IMM4);
7646}
7647
7648// 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
76498.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_sub
7650"or_sub"
7651*am33
7652{
7653 int srcreg1, srcreg2, dstreg1, dstreg2;
7654
7655 PC = cia;
7656 srcreg1 = translate_rreg (SD_, RM1);
7657 srcreg2 = translate_rreg (SD_, RM2);
7658 dstreg1 = translate_rreg (SD_, RN1);
7659 dstreg2 = translate_rreg (SD_, RN2);
7660
7661 State.regs[dstreg1] |= State.regs[srcreg1];
7662 State.regs[dstreg2] -= State.regs[srcreg2];
7663}
7664
7665// 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
76668.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_sub
7667"or_sub"
7668*am33
7669{
7670 int srcreg1, dstreg1, dstreg2;
7671
7672 PC = cia;
7673 srcreg1 = translate_rreg (SD_, RM1);
7674 dstreg1 = translate_rreg (SD_, RN1);
7675 dstreg2 = translate_rreg (SD_, RN2);
7676
7677 State.regs[dstreg1] |= State.regs[srcreg1];
7678 State.regs[dstreg2] -= EXTEND4 (IMM4);
7679}
7680
7681// 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
76828.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_cmp
7683"or_cmp"
7684*am33
7685{
7686 int srcreg1, srcreg2, dstreg1, dstreg2;
7687
7688 PC = cia;
7689 srcreg1 = translate_rreg (SD_, RM1);
7690 srcreg2 = translate_rreg (SD_, RM2);
7691 dstreg1 = translate_rreg (SD_, RN1);
7692 dstreg2 = translate_rreg (SD_, RN2);
7693
7694 State.regs[dstreg1] |= State.regs[srcreg1];
7695 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7696}
7697
7698// 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
76998.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_cmp
7700"or_cmp"
7701*am33
7702{
7703 int srcreg1, dstreg1, dstreg2;
7704
7705 PC = cia;
7706 srcreg1 = translate_rreg (SD_, RM1);
7707 dstreg1 = translate_rreg (SD_, RN1);
7708 dstreg2 = translate_rreg (SD_, RN2);
7709
7710 State.regs[dstreg1] |= State.regs[srcreg1];
7711 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7712}
7713
7714// 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
77158.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_mov
7716"or_mov"
7717*am33
7718{
7719 int srcreg1, srcreg2, dstreg1, dstreg2;
7720
7721 PC = cia;
7722 srcreg1 = translate_rreg (SD_, RM1);
7723 srcreg2 = translate_rreg (SD_, RM2);
7724 dstreg1 = translate_rreg (SD_, RN1);
7725 dstreg2 = translate_rreg (SD_, RN2);
7726
7727 State.regs[dstreg1] |= State.regs[srcreg1];
7728 State.regs[dstreg2] = State.regs[srcreg2];
7729}
7730
7731// 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
77328.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_mov
7733"or_mov"
7734*am33
7735{
7736 int srcreg1, dstreg1, dstreg2;
7737
7738 PC = cia;
7739 srcreg1 = translate_rreg (SD_, RM1);
7740 dstreg1 = translate_rreg (SD_, RN1);
7741 dstreg2 = translate_rreg (SD_, RN2);
7742
7743 State.regs[dstreg1] |= State.regs[srcreg1];
7744 State.regs[dstreg2] = EXTEND4 (IMM4);
7745}
7746
7747// 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
77488.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asr
7749"or_asr"
7750*am33
7751{
7752 int srcreg1, srcreg2, dstreg1, dstreg2;
7753 signed int temp;
7754
7755 PC = cia;
7756 srcreg1 = translate_rreg (SD_, RM1);
7757 srcreg2 = translate_rreg (SD_, RM2);
7758 dstreg1 = translate_rreg (SD_, RN1);
7759 dstreg2 = translate_rreg (SD_, RN2);
7760
7761 State.regs[dstreg1] |= State.regs[srcreg1];
7762 temp = State.regs[dstreg2];
7763 temp >>= State.regs[srcreg2];
7764 State.regs[dstreg2] = temp;
7765}
7766
7767// 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
77688.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asr
7769"or_asr"
7770*am33
7771{
7772 int srcreg1, dstreg1, dstreg2;
7773 signed int temp;
7774
7775 PC = cia;
7776 srcreg1 = translate_rreg (SD_, RM1);
7777 dstreg1 = translate_rreg (SD_, RN1);
7778 dstreg2 = translate_rreg (SD_, RN2);
7779
7780 State.regs[dstreg1] |= State.regs[srcreg1];
7781 temp = State.regs[dstreg2];
7782 temp >>= IMM4;
7783 State.regs[dstreg2] = temp;
7784}
7785
7786// 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
77878.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_lsr
7788"or_lsr"
7789*am33
7790{
7791 int srcreg1, srcreg2, dstreg1, dstreg2;
7792
7793 PC = cia;
7794 srcreg1 = translate_rreg (SD_, RM1);
7795 srcreg2 = translate_rreg (SD_, RM2);
7796 dstreg1 = translate_rreg (SD_, RN1);
7797 dstreg2 = translate_rreg (SD_, RN2);
7798
7799 State.regs[dstreg1] |= State.regs[srcreg1];
7800 State.regs[dstreg2] >>= State.regs[srcreg2];
7801}
7802
7803// 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
78048.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_lsr
7805"or_lsr"
7806*am33
7807{
7808 int srcreg1, dstreg1, dstreg2;
7809 signed int temp;
7810
7811 PC = cia;
7812 srcreg1 = translate_rreg (SD_, RM1);
7813 dstreg1 = translate_rreg (SD_, RN1);
7814 dstreg2 = translate_rreg (SD_, RN2);
7815
7816 State.regs[dstreg1] |= State.regs[srcreg1];
7817 State.regs[dstreg2] >>= IMM4;
7818}
7819
7820
7821// 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
78228.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asl
7823"or_asl"
7824*am33
7825{
7826 int srcreg1, srcreg2, dstreg1, dstreg2;
7827
7828 PC = cia;
7829 srcreg1 = translate_rreg (SD_, RM1);
7830 srcreg2 = translate_rreg (SD_, RM2);
7831 dstreg1 = translate_rreg (SD_, RN1);
7832 dstreg2 = translate_rreg (SD_, RN2);
7833
7834 State.regs[dstreg1] |= State.regs[srcreg1];
7835 State.regs[dstreg2] <<= State.regs[srcreg2];
7836}
7837
7838// 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
78398.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asl
7840"or_asl"
7841*am33
7842{
7843 int srcreg1, dstreg1, dstreg2;
7844 signed int temp;
7845
7846 PC = cia;
7847 srcreg1 = translate_rreg (SD_, RM1);
7848 dstreg1 = translate_rreg (SD_, RN1);
7849 dstreg2 = translate_rreg (SD_, RN2);
7850
7851 State.regs[dstreg1] |= State.regs[srcreg1];
7852 State.regs[dstreg2] <<= IMM4;
7853}
7854
7855// 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
78568.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_add
7857"sat16_add"
7858*am33
7859{
7860 int srcreg1, srcreg2, dstreg1, dstreg2;
7861
7862 PC = cia;
7863 srcreg1 = translate_rreg (SD_, RM1);
7864 srcreg2 = translate_rreg (SD_, RM2);
7865 dstreg1 = translate_rreg (SD_, RN1);
7866 dstreg2 = translate_rreg (SD_, RN2);
7867
7868 if (State.regs[srcreg1] >= 0x7fff)
7869 State.regs[dstreg1] = 0x7fff;
7870 else if (State.regs[srcreg1] <= 0xffff8000)
7871 State.regs[dstreg1] = 0xffff8000;
7872 else
7873 State.regs[dstreg1] = State.regs[srcreg1];
7874
7875 State.regs[dstreg2] += State.regs[srcreg2];
7876}
7877
7878// 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
78798.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_add
7880"sat16_add"
7881*am33
7882{
7883 int srcreg1, dstreg1, dstreg2;
7884
7885 PC = cia;
7886 srcreg1 = translate_rreg (SD_, RM1);
7887 dstreg1 = translate_rreg (SD_, RN1);
7888 dstreg2 = translate_rreg (SD_, RN2);
7889
7890 if (State.regs[srcreg1] >= 0x7fff)
7891 State.regs[dstreg1] = 0x7fff;
7892 else if (State.regs[srcreg1] <= 0xffff8000)
7893 State.regs[dstreg1] = 0xffff8000;
7894 else
7895 State.regs[dstreg1] = State.regs[srcreg1];
7896
7897 State.regs[dstreg2] += EXTEND4 (IMM4);
7898}
7899
7900// 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
79018.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_sub
7902"sat16_sub"
7903*am33
7904{
7905 int srcreg1, srcreg2, dstreg1, dstreg2;
7906
7907 PC = cia;
7908 srcreg1 = translate_rreg (SD_, RM1);
7909 srcreg2 = translate_rreg (SD_, RM2);
7910 dstreg1 = translate_rreg (SD_, RN1);
7911 dstreg2 = translate_rreg (SD_, RN2);
7912
7913 if (State.regs[srcreg1] >= 0x7fff)
7914 State.regs[dstreg1] = 0x7fff;
7915 else if (State.regs[srcreg1] <= 0xffff8000)
7916 State.regs[dstreg1] = 0xffff8000;
7917 else
7918 State.regs[dstreg1] = State.regs[srcreg1];
7919
7920 State.regs[dstreg2] -= State.regs[srcreg2];
7921}
7922
7923// 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
79248.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_sub
7925"sat16_sub"
7926*am33
7927{
7928 int srcreg1, dstreg1, dstreg2;
7929
7930 PC = cia;
7931 srcreg1 = translate_rreg (SD_, RM1);
7932 dstreg1 = translate_rreg (SD_, RN1);
7933 dstreg2 = translate_rreg (SD_, RN2);
7934
7935 if (State.regs[srcreg1] >= 0x7fff)
7936 State.regs[dstreg1] = 0x7fff;
7937 else if (State.regs[srcreg1] <= 0xffff8000)
7938 State.regs[dstreg1] = 0xffff8000;
7939 else
7940 State.regs[dstreg1] = State.regs[srcreg1];
7941
7942 State.regs[dstreg2] -= EXTEND4 (IMM4);
7943}
7944
7945// 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
79468.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_cmp
7947"sat16_cmp"
7948*am33
7949{
7950 int srcreg1, srcreg2, dstreg1, dstreg2;
7951
7952 PC = cia;
7953 srcreg1 = translate_rreg (SD_, RM1);
7954 srcreg2 = translate_rreg (SD_, RM2);
7955 dstreg1 = translate_rreg (SD_, RN1);
7956 dstreg2 = translate_rreg (SD_, RN2);
7957
7958 if (State.regs[srcreg1] >= 0x7fff)
7959 State.regs[dstreg1] = 0x7fff;
7960 else if (State.regs[srcreg1] <= 0xffff8000)
7961 State.regs[dstreg1] = 0xffff8000;
7962 else
7963 State.regs[dstreg1] = State.regs[srcreg1];
7964
7965 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7966}
7967
7968// 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
79698.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_cmp
7970"sat16_cmp"
7971*am33
7972{
7973 int srcreg1, dstreg1, dstreg2;
7974
7975 PC = cia;
7976 srcreg1 = translate_rreg (SD_, RM1);
7977 dstreg1 = translate_rreg (SD_, RN1);
7978 dstreg2 = translate_rreg (SD_, RN2);
7979
7980 if (State.regs[srcreg1] >= 0x7fff)
7981 State.regs[dstreg1] = 0x7fff;
7982 else if (State.regs[srcreg1] <= 0xffff8000)
7983 State.regs[dstreg1] = 0xffff8000;
7984 else
7985 State.regs[dstreg1] = State.regs[srcreg1];
7986
7987 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7988}
7989
7990// 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
79918.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_mov
7992"sat16_mov"
7993*am33
7994{
7995 int srcreg1, srcreg2, dstreg1, dstreg2;
7996
7997 PC = cia;
7998 srcreg1 = translate_rreg (SD_, RM1);
7999 srcreg2 = translate_rreg (SD_, RM2);
8000 dstreg1 = translate_rreg (SD_, RN1);
8001 dstreg2 = translate_rreg (SD_, RN2);
8002
8003 if (State.regs[srcreg1] >= 0x7fff)
8004 State.regs[dstreg1] = 0x7fff;
8005 else if (State.regs[srcreg1] <= 0xffff8000)
8006 State.regs[dstreg1] = 0xffff8000;
8007 else
8008 State.regs[dstreg1] = State.regs[srcreg1];
8009
8010 State.regs[dstreg2] = State.regs[srcreg2];
8011}
8012
8013// 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
80148.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_mov
8015"sat16_mov"
8016*am33
8017{
8018 int srcreg1, dstreg1, dstreg2;
8019
8020 PC = cia;
8021 srcreg1 = translate_rreg (SD_, RM1);
8022 dstreg1 = translate_rreg (SD_, RN1);
8023 dstreg2 = translate_rreg (SD_, RN2);
8024
8025 if (State.regs[srcreg1] >= 0x7fff)
8026 State.regs[dstreg1] = 0x7fff;
8027 else if (State.regs[srcreg1] <= 0xffff8000)
8028 State.regs[dstreg1] = 0xffff8000;
8029 else
8030 State.regs[dstreg1] = State.regs[srcreg1];
8031
8032 State.regs[dstreg2] = EXTEND4 (IMM4);
8033}
8034
8035// 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
80368.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asr
8037"sat16_asr"
8038*am33
8039{
8040 int srcreg1, srcreg2, dstreg1, dstreg2;
8041 signed int temp;
8042
8043 PC = cia;
8044 srcreg1 = translate_rreg (SD_, RM1);
8045 srcreg2 = translate_rreg (SD_, RM2);
8046 dstreg1 = translate_rreg (SD_, RN1);
8047 dstreg2 = translate_rreg (SD_, RN2);
8048
8049 if (State.regs[srcreg1] >= 0x7fff)
8050 State.regs[dstreg1] = 0x7fff;
8051 else if (State.regs[srcreg1] <= 0xffff8000)
8052 State.regs[dstreg1] = 0xffff8000;
8053 else
8054 State.regs[dstreg1] = State.regs[srcreg1];
8055
8056 temp = State.regs[dstreg2];
8057 temp >>= State.regs[srcreg2];
8058 State.regs[dstreg2] = temp;
8059}
8060
8061// 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
80628.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asr
8063"sat16_asr"
8064*am33
8065{
8066 int srcreg1, dstreg1, dstreg2;
8067 signed int temp;
8068
8069 PC = cia;
8070 srcreg1 = translate_rreg (SD_, RM1);
8071 dstreg1 = translate_rreg (SD_, RN1);
8072 dstreg2 = translate_rreg (SD_, RN2);
8073
8074 if (State.regs[srcreg1] >= 0x7fff)
8075 State.regs[dstreg1] = 0x7fff;
8076 else if (State.regs[srcreg1] <= 0xffff8000)
8077 State.regs[dstreg1] = 0xffff8000;
8078 else
8079 State.regs[dstreg1] = State.regs[srcreg1];
8080
8081 temp = State.regs[dstreg2];
8082 temp >>= IMM4;
8083 State.regs[dstreg2] = temp;
8084}
8085
8086// 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
80878.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_lsr
8088"sat16_lsr"
8089*am33
8090{
8091 int srcreg1, srcreg2, dstreg1, dstreg2;
8092
8093 PC = cia;
8094 srcreg1 = translate_rreg (SD_, RM1);
8095 srcreg2 = translate_rreg (SD_, RM2);
8096 dstreg1 = translate_rreg (SD_, RN1);
8097 dstreg2 = translate_rreg (SD_, RN2);
8098
8099 if (State.regs[srcreg1] >= 0x7fff)
8100 State.regs[dstreg1] = 0x7fff;
8101 else if (State.regs[srcreg1] <= 0xffff8000)
8102 State.regs[dstreg1] = 0xffff8000;
8103 else
8104 State.regs[dstreg1] = State.regs[srcreg1];
8105
8106 State.regs[dstreg2] >>= State.regs[srcreg2];
8107}
8108
8109// 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
81108.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_lsr
8111"sat16_lsr"
8112*am33
8113{
8114 int srcreg1, dstreg1, dstreg2;
8115 signed int temp;
8116
8117 PC = cia;
8118 srcreg1 = translate_rreg (SD_, RM1);
8119 dstreg1 = translate_rreg (SD_, RN1);
8120 dstreg2 = translate_rreg (SD_, RN2);
8121
8122 if (State.regs[srcreg1] >= 0x7fff)
8123 State.regs[dstreg1] = 0x7fff;
8124 else if (State.regs[srcreg1] <= 0xffff8000)
8125 State.regs[dstreg1] = 0xffff8000;
8126 else
8127 State.regs[dstreg1] = State.regs[srcreg1];
8128
8129 State.regs[dstreg2] >>= IMM4;
8130}
8131
8132
8133// 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
81348.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asl
8135"sat16_asl"
8136*am33
8137{
8138 int srcreg1, srcreg2, dstreg1, dstreg2;
8139
8140 PC = cia;
8141 srcreg1 = translate_rreg (SD_, RM1);
8142 srcreg2 = translate_rreg (SD_, RM2);
8143 dstreg1 = translate_rreg (SD_, RN1);
8144 dstreg2 = translate_rreg (SD_, RN2);
8145
8146 if (State.regs[srcreg1] >= 0x7fff)
8147 State.regs[dstreg1] = 0x7fff;
8148 else if (State.regs[srcreg1] <= 0xffff8000)
8149 State.regs[dstreg1] = 0xffff8000;
8150 else
8151 State.regs[dstreg1] = State.regs[srcreg1];
8152
8153 State.regs[dstreg2] <<= State.regs[srcreg2];
8154}
8155
8156// 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
81578.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asl
8158"sat16_asl"
8159*am33
8160{
8161 int srcreg1, dstreg1, dstreg2;
8162 signed int temp;
8163
8164 PC = cia;
8165 srcreg1 = translate_rreg (SD_, RM1);
8166 dstreg1 = translate_rreg (SD_, RN1);
8167 dstreg2 = translate_rreg (SD_, RN2);
8168
8169 if (State.regs[srcreg1] >= 0x7fff)
8170 State.regs[dstreg1] = 0x7fff;
8171 else if (State.regs[srcreg1] <= 0xffff8000)
8172 State.regs[dstreg1] = 0xffff8000;
8173 else
8174 State.regs[dstreg1] = State.regs[srcreg1];
8175
8176 State.regs[dstreg2] <<= IMM4;
8177}
8178
6ae1456e
JL		 8179// 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
81808.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x0:D2:::mov_llt
8181"mov_llt"
8182*am33
8183{
8184 int srcreg, dstreg;
8185
8186 PC = cia;
8187 srcreg = translate_rreg (SD_, RM);
8188 dstreg = translate_rreg (SD_, RN);
8189
8190 State.regs[dstreg] = load_word (State.regs[srcreg]);
8191 State.regs[srcreg] += EXTEND4 (IMM4);
8192
8193 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
8194 {
8195 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8196 nia = PC;
8197 }
8198}
8199
8200// 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
82018.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x1:D2:::mov_lgt
8202"mov_lgt"
8203*am33
8204{
8205 int srcreg, dstreg;
8206
8207 PC = cia;
8208 srcreg = translate_rreg (SD_, RM);
8209 dstreg = translate_rreg (SD_, RN);
8210
8211 State.regs[dstreg] = load_word (State.regs[srcreg]);
8212 State.regs[srcreg] += EXTEND4 (IMM4);
8213
8214 if (!((PSW & PSW_Z)
8215 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
8216 {
8217 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8218 nia = PC;
8219 }
8220}
8221
8222// 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
82238.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x2:D2:::mov_lge
8224"mov_lge"
8225*am33
8226{
8227 int srcreg, dstreg;
8228
8229 PC = cia;
8230 srcreg = translate_rreg (SD_, RM);
8231 dstreg = translate_rreg (SD_, RN);
8232
8233 State.regs[dstreg] = load_word (State.regs[srcreg]);
8234 State.regs[srcreg] += EXTEND4 (IMM4);
8235
8236 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8237 {
8238 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8239 nia = PC;
8240 }
8241}
8242
8243// 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
82448.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x3:D2:::mov_lle
8245"mov_lle"
8246*am33
8247{
8248 int srcreg, dstreg;
8249
8250 PC = cia;
8251 srcreg = translate_rreg (SD_, RM);
8252 dstreg = translate_rreg (SD_, RN);
8253
8254 State.regs[dstreg] = load_word (State.regs[srcreg]);
8255 State.regs[srcreg] += EXTEND4 (IMM4);
8256
8257 if ((PSW & PSW_Z)
8258 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8259 {
8260 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8261 nia = PC;
8262 }
8263}
8264
8265// 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
82668.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x4:D2:::mov_lcs
8267"mov_lcs"
8268*am33
8269{
8270 int srcreg, dstreg;
8271
8272 PC = cia;
8273 srcreg = translate_rreg (SD_, RM);
8274 dstreg = translate_rreg (SD_, RN);
8275
8276 State.regs[dstreg] = load_word (State.regs[srcreg]);
8277 State.regs[srcreg] += EXTEND4 (IMM4);
8278
8279 if (PSW & PSW_C)
8280 {
8281 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8282 nia = PC;
8283 }
8284}
8285
8286// 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
82878.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x5:D2:::mov_lhi
8288"mov_lhi"
8289*am33
8290{
8291 int srcreg, dstreg;
8292
8293 PC = cia;
8294 srcreg = translate_rreg (SD_, RM);
8295 dstreg = translate_rreg (SD_, RN);
8296
8297 State.regs[dstreg] = load_word (State.regs[srcreg]);
8298 State.regs[srcreg] += EXTEND4 (IMM4);
8299
8300 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
8301 {
8302 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8303 nia = PC;
8304 }
8305}
8306
8307// 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
83088.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x6:D2:::mov_lcc
8309"mov_lcc"
8310*am33
8311{
8312 int srcreg, dstreg;
8313
8314 PC = cia;
8315 srcreg = translate_rreg (SD_, RM);
8316 dstreg = translate_rreg (SD_, RN);
8317
8318 State.regs[dstreg] = load_word (State.regs[srcreg]);
8319 State.regs[srcreg] += EXTEND4 (IMM4);
8320
8321 if (!(PSW & PSW_C))
8322 {
8323 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8324 nia = PC;
8325 }
8326}
8327
8328// 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
83298.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x7:D2:::mov_lls
8330"mov_lls"
8331*am33
8332{
8333 int srcreg, dstreg;
8334
8335 PC = cia;
8336 srcreg = translate_rreg (SD_, RM);
8337 dstreg = translate_rreg (SD_, RN);
8338
8339 State.regs[dstreg] = load_word (State.regs[srcreg]);
8340 State.regs[srcreg] += EXTEND4 (IMM4);
8341
8342 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
8343 {
8344 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8345 nia = PC;
8346 }
8347}
8348
8349// 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
83508.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x8:D2:::mov_leq
8351"mov_leq"
8352*am33
8353{
8354 int srcreg, dstreg;
8355
8356 PC = cia;
8357 srcreg = translate_rreg (SD_, RM);
8358 dstreg = translate_rreg (SD_, RN);
8359
8360 State.regs[dstreg] = load_word (State.regs[srcreg]);
8361 State.regs[srcreg] += EXTEND4 (IMM4);
8362
8363 if (PSW & PSW_Z)
8364 {
8365 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8366 nia = PC;
8367 }
8368}
8369
8370// 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
83718.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x9:D2:::mov_lne
8372"mov_lne"
8373*am33
8374{
8375 int srcreg, dstreg;
8376
8377 PC = cia;
8378 srcreg = translate_rreg (SD_, RM);
8379 dstreg = translate_rreg (SD_, RN);
8380
8381 State.regs[dstreg] = load_word (State.regs[srcreg]);
8382 State.regs[srcreg] += EXTEND4 (IMM4);
8383
8384 if (!(PSW & PSW_Z))
8385 {
8386 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8387 nia = PC;
8388 }
8389}
8390
8391// 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
83928.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0xa:D2:::mov_lra
8393"mov_lra"
8394*am33
8395{
8396 int srcreg, dstreg;
8397
8398 PC = cia;
8399 srcreg = translate_rreg (SD_, RM);
8400 dstreg = translate_rreg (SD_, RN);
8401
8402 State.regs[dstreg] = load_word (State.regs[srcreg]);
8403 State.regs[srcreg] += EXTEND4 (IMM4);
8404
8405 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8406 nia = PC;
8407}
GDB Binutils - Deliverables
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