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* mn10300.igen: Fix Z bit for addc and subc instructions.
[deliverable/binutils-gdb.git] / sim / mn10300 / am33.igen
CommitLineData
9c55817e
JL		 1// Helper:
2//
3// Given an extended register number, translate it into an index into the
4// register array. This is necessary as the upper 8 extended registers are
5// actually synonyms for the d0-d3/a0-a3 registers.
6//
7//
8
9:function:::int:translate_rreg:int rreg
10{
11
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
18 else
19 return REG_E0 + rreg;
20}
21
0f7d7385
JL		 22// 1111 0000 0010 00An; mov USP,An
238.0xf0+4.0x2,00,2.AN0:D0m:::mov
24"mov"
25*am33
26{
27 PC = cia;
28 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
29}
30
31
32// 1111 0000 0010 01An; mov SSP,An
338.0xf0+4.0x2,01,2.AN0:D0n:::mov
34"mov"
35*am33
36{
37 PC = cia;
38 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
39}
40
41
42// 1111 0000 0010 10An; mov MSP,An
438.0xf0+4.0x2,10,2.AN0:D0o:::mov
44"mov"
45*am33
46{
47 PC = cia;
48 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
49}
50
51
52// 1111 0000 0010 11An; mov PC,An
538.0xf0+4.0x2,11,2.AN0:D0p:::mov
54"mov"
55*am33
56{
57 PC = cia;
58 State.regs[REG_A0 + AN0] = PC;
59}
60
61
62// 1111 0000 0011 Am00; mov Am,USP
638.0xf0+4.0x3,2.AM1,00:D0q:::mov
64"mov"
3e75ff7e 65*am33
0f7d7385
JL		 66{
67 PC = cia;
68 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
69}
70
71// 1111 0000 0011 Am01; mov Am,SSP
728.0xf0+4.0x3,2.AM1,01:D0r:::mov
73"mov"
3e75ff7e 74*am33
0f7d7385
JL		 75{
76 PC = cia;
77 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
78}
79
80// 1111 0000 0011 Am10; mov Am,MSP
818.0xf0+4.0x3,2.AM1,10:D0s:::mov
82"mov"
3e75ff7e 83*am33
0f7d7385
JL		 84{
85 PC = cia;
86 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
87}
88
89
90// 1111 0000 1110 imm4; syscall
918.0xf0+4.0xe,IMM4:D0t:::syscall
92"syscall"
93*am33
94{
95 unsigned int sp, next_pc;
96
97 PC = cia;
98 sp = State.regs[REG_SP];
99 next_pc = State.regs[REG_PC] + 2;
100 store_word (sp - 4, next_pc);
101 store_word (sp - 8, PSW);
102 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
103 nia = PC;
104}
105
106
107// 1111 0010 1110 11Dn; mov EPSW,Dn
1088.0xf2+4.0xe,11,2.DN0:D0u:::mov
109"mov"
110*am33
111{
112 PC = cia;
113 State.regs[REG_D0 + DN0] = PSW;
114}
115
116
117// 1111 0010 1111 Dm01; mov Dm,EPSW
1188.0xf2+4.0xf,2.DM1,01:D0v:::mov
119"mov"
120*am33
121{
122 PC = cia;
123 PSW = State.regs[REG_D0 + DM1];
124}
125
126// 1111 0101 00Am Rn; mov Am,Rn
1278.0xf5+00,2.AM1,4.RN0:D0w:::mov
128"mov"
129*am33
130{
9c55817e
JL		 131 int destreg = translate_rreg (SD_, RN0);
132
0f7d7385 133 PC = cia;
9c55817e 134 State.regs[destreg] = State.regs[REG_A0 + AM1];
0f7d7385
JL		 135}
136
137// 1111 0101 01Dm Rn; mov Dm,Rn
1388.0xf5+01,2.DM1,4.RN0:D0x:::mov
139"mov"
140*am33
141{
9c55817e
JL		 142 int destreg = translate_rreg (SD_, RN0);
143
0f7d7385 144 PC = cia;
9c55817e 145 State.regs[destreg] = State.regs[REG_D0 + DM1];
0f7d7385
JL		 146}
147
148// 1111 0101 10Rm An; mov Rm,An
1498.0xf5+10,4.RM1,2.AN0:D0y:::mov
150"mov"
151*am33
152{
9c55817e
JL		 153 int destreg = translate_rreg (SD_, RM1);
154
0f7d7385 155 PC = cia;
9c55817e 156 State.regs[REG_A0 + AN0] = State.regs[destreg];
0f7d7385
JL		 157}
158
159// 1111 0101 11Rm Dn; mov Rm,Dn
1608.0xf5+11,4.RM1,2.DN0:D0z:::mov
161"mov"
162*am33
163{
9c55817e
JL		 164 int destreg = translate_rreg (SD_, RM1);
165
0f7d7385 166 PC = cia;
9c55817e 167 State.regs[REG_D0 + DN0] = State.regs[destreg];
0f7d7385
JL		 168}
169
170
171// 1111 1000 1100 1110 regs....; movm (USP),regs
1728.0xf8+8.0xce+8.REGS:D1a:::movm
173"movm"
3e75ff7e 174*am33
0f7d7385
JL		 175{
176 unsigned long usp = State.regs[REG_USP];
177 unsigned long mask;
178
179 PC = cia;
180 mask = REGS;
181
182 if (mask & 0x8)
183 {
184 usp += 4;
185 State.regs[REG_LAR] = load_word (usp);
186 usp += 4;
187 State.regs[REG_LIR] = load_word (usp);
188 usp += 4;
189 State.regs[REG_MDR] = load_word (usp);
190 usp += 4;
191 State.regs[REG_A0 + 1] = load_word (usp);
192 usp += 4;
193 State.regs[REG_A0] = load_word (usp);
194 usp += 4;
195 State.regs[REG_D0 + 1] = load_word (usp);
196 usp += 4;
197 State.regs[REG_D0] = load_word (usp);
198 usp += 4;
199 }
200
201 if (mask & 0x10)
202 {
203 State.regs[REG_A0 + 3] = load_word (usp);
204 usp += 4;
205 }
206
207 if (mask & 0x20)
208 {
209 State.regs[REG_A0 + 2] = load_word (usp);
210 usp += 4;
211 }
212
213 if (mask & 0x40)
214 {
215 State.regs[REG_D0 + 3] = load_word (usp);
216 usp += 4;
217 }
218
219 if (mask & 0x80)
220 {
221 State.regs[REG_D0 + 2] = load_word (usp);
222 usp += 4;
223 }
224
225 /* start-sanitize-am33 */
226 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
227 {
228 if (mask & 0x1)
229 {
230 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
231 usp += 16;
232 State.regs[REG_E0 + 1] = load_word (usp);
233 usp += 4;
234 State.regs[REG_E0 + 0] = load_word (usp);
235 usp += 4;
236 }
237
238 if (mask & 0x2)
239 {
240 State.regs[REG_E0 + 7] = load_word (usp);
241 usp += 4;
242 State.regs[REG_E0 + 6] = load_word (usp);
243 usp += 4;
244 State.regs[REG_E0 + 5] = load_word (usp);
245 usp += 4;
246 State.regs[REG_E0 + 4] = load_word (usp);
247 usp += 4;
248 }
249
250 if (mask & 0x4)
251 {
252 State.regs[REG_E0 + 3] = load_word (usp);
253 usp += 4;
254 State.regs[REG_E0 + 2] = load_word (usp);
255 usp += 4;
256 }
257 }
258 /* end-sanitize-am33 */
259
260 /* And make sure to update the stack pointer. */
261 State.regs[REG_USP] = usp;
262}
263
264// 1111 1000 1100 1111 regs....; movm (USP),regs
2658.0xf8+8.0xcf+8.REGS:D1b:::movm
266"movm"
3e75ff7e 267*am33
0f7d7385
JL		 268{
269 unsigned long usp = State.regs[REG_USP];
270 unsigned long mask;
271
272 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
273 {
274 if (mask & 0x4)
275 {
276 usp -= 4;
277 store_word (usp, State.regs[REG_E0 + 2]);
278 usp -= 4;
279 store_word (usp, State.regs[REG_E0 + 3]);
280 }
281
282 if (mask & 0x2)
283 {
284 usp -= 4;
285 store_word (usp, State.regs[REG_E0 + 4]);
286 usp -= 4;
287 store_word (usp, State.regs[REG_E0 + 5]);
288 usp -= 4;
289 store_word (usp, State.regs[REG_E0 + 6]);
290 usp -= 4;
291 store_word (usp, State.regs[REG_E0 + 7]);
292 }
293
294 if (mask & 0x1)
295 {
296 usp -= 4;
297 store_word (usp, State.regs[REG_E0 + 0]);
298 usp -= 4;
299 store_word (usp, State.regs[REG_E0 + 1]);
300 usp -= 16;
301 /* Need to save MDQR, MCRH, MCRL, and MCVF */
302 }
303 }
304 /* end-sanitize-am33 */
305
306 if (mask & 0x80)
307 {
308 usp -= 4;
309 store_word (usp, State.regs[REG_D0 + 2]);
310 }
311
312 if (mask & 0x40)
313 {
314 usp -= 4;
315 store_word (usp, State.regs[REG_D0 + 3]);
316 }
317
318 if (mask & 0x20)
319 {
320 usp -= 4;
321 store_word (usp, State.regs[REG_A0 + 2]);
322 }
323
324 if (mask & 0x10)
325 {
326 usp -= 4;
327 store_word (usp, State.regs[REG_A0 + 3]);
328 }
329
330 if (mask & 0x8)
331 {
332 usp -= 4;
333 store_word (usp, State.regs[REG_D0]);
334 usp -= 4;
335 store_word (usp, State.regs[REG_D0 + 1]);
336 usp -= 4;
337 store_word (usp, State.regs[REG_A0]);
338 usp -= 4;
339 store_word (usp, State.regs[REG_A0 + 1]);
340 usp -= 4;
341 store_word (usp, State.regs[REG_MDR]);
342 usp -= 4;
343 store_word (usp, State.regs[REG_LIR]);
344 usp -= 4;
345 store_word (usp, State.regs[REG_LAR]);
346 usp -= 4;
347 }
348
349 /* And make sure to update the stack pointer. */
350 State.regs[REG_USP] = usp;
351}
352
353// 1111 1100 1111 1100 imm32...; and imm32,EPSW
3548.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
355"and"
356*am33
357{
358 PC = cia;
359 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
360}
361
362// 1111 1100 1111 1101 imm32...; or imm32,EPSW
3638.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
364"or"
365*am33
366{
367 PC = cia;
368 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
369}
370
371// 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
3728.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
373"mov"
374*am33
375{
376 int srcreg, dstreg;
377
378 PC = cia;
379
9c55817e
JL		 380 srcreg = translate_rreg (SD_, RM2);
381 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 382 State.regs[dstreg] = State.regs[srcreg];
383}
384
385// 1111 1001 0001 1000 Rn Rn; ext Rn
3868.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
387"mov"
388*am33
389{
9c55817e 390 int srcreg;
0f7d7385
JL		 391
392 PC = cia;
9c55817e 393 srcreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 394 if (State.regs[srcreg] & 0x80000000)
395 State.regs[REG_MDR] = -1;
396 else
397 State.regs[REG_MDR] = 0;
398}
399
400// 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
4018.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
402"extb"
403*am33
404{
405 int srcreg, dstreg;
406
407 PC = cia;
9c55817e
JL		 408 srcreg = translate_rreg (SD_, RM2);
409 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 410 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
411}
412
413// 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
4148.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
415"extbu"
416*am33
417{
418 int srcreg, dstreg;
419
420 PC = cia;
9c55817e
JL		 421 srcreg = translate_rreg (SD_, RM2);
422 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 423 State.regs[dstreg] = State.regs[srcreg] & 0xff;
424}
425
426// 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
4278.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
428"exth"
429*am33
430{
431 int srcreg, dstreg;
432
433 PC = cia;
9c55817e
JL		 434 srcreg = translate_rreg (SD_, RM2);
435 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 436 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
437}
438
439// 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
4408.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
441"exthu"
442*am33
443{
444 int srcreg, dstreg;
445
446 PC = cia;
9c55817e
JL		 447 srcreg = translate_rreg (SD_, RM2);
448 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 449 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
450}
451
452// 1111 1001 0110 1000 Rn Rn; clr Rn
4538.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
454"clr"
455*am33
456{
9c55817e 457 int dstreg;
0f7d7385
JL		 458
459 PC = cia;
9c55817e 460 dstreg = translate_rreg (SD_, RN0);
0f7d7385 461 State.regs[dstreg] = 0;
0f7d7385
JL		 462 PSW |= PSW_Z;
463 PSW &= ~(PSW_V | PSW_C | PSW_N);
464}
465
466// 1111 1001 0111 1000 Rm Rn; add Rm,Rn
4678.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
468"add"
469*am33
470{
471 int srcreg, dstreg;
472
473 PC = cia;
9c55817e
JL		 474 srcreg = translate_rreg (SD_, RM2);
475 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 476 genericAdd (State.regs[srcreg], dstreg);
477}
478
479// 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
4808.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
481"addc"
482*am33
483{
484 int srcreg, dstreg;
485 int z, c, n, v;
486 unsigned long reg1, reg2, sum;
487
488 PC = cia;
9c55817e
JL		 489 srcreg = translate_rreg (SD_, RM2);
490 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 491
492 reg1 = State.regs[srcreg];
493 reg2 = State.regs[dstreg];
494 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
495 State.regs[dstreg] = sum;
496
4e86afb8 497 z = ((PSW & PSW_Z) != 0) && (sum == 0);
0f7d7385
JL		 498 n = (sum & 0x80000000);
499 c = (sum < reg1) || (sum < reg2);
500 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
501 && (reg2 & 0x80000000) != (sum & 0x80000000));
502
503 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
504 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
505 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
506}
507
508// 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
5098.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
510"sub"
511*am33
512{
513 int srcreg, dstreg;
514
515 PC = cia;
9c55817e
JL		 516 srcreg = translate_rreg (SD_, RM2);
517 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 518 genericSub (State.regs[srcreg], dstreg);
519}
520
521// 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
5228.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
523"subc"
524*am33
525{
526 int srcreg, dstreg;
527 int z, c, n, v;
528 unsigned long reg1, reg2, difference;
529
530 PC = cia;
9c55817e
JL		 531 srcreg = translate_rreg (SD_, RM2);
532 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 533
534 reg1 = State.regs[srcreg];
535 reg2 = State.regs[dstreg];
536 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
537 State.regs[dstreg] = difference;
538
4e86afb8 539 z = ((PSW & PSW_Z) != 0) && (difference == 0);
0f7d7385
JL		 540 n = (difference & 0x80000000);
541 c = (reg1 > reg2);
542 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
543 && (reg2 & 0x80000000) != (difference & 0x80000000));
544
545 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
546 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
547 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
548}
549
550// 1111 1001 1011 1000 Rn Rn; inc Rn
5518.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
552"inc"
553*am33
554{
555 int dstreg;
556
557 PC = cia;
9c55817e 558 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 559 genericAdd (1, dstreg);
560}
561
562// 1111 1001 1101 1000 Rn Rn; inc Rn
5638.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
564"inc4"
565*am33
566{
567 int dstreg;
568
569 PC = cia;
9c55817e 570 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 571 State.regs[dstreg] += 4;
572}
573
574// 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
5758.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
576"cmp"
577*am33
578{
579 int srcreg1, srcreg2;
580
581 PC = cia;
9c55817e
JL		 582 srcreg1 = translate_rreg (SD_, RN0);
583 srcreg2 = translate_rreg (SD_, RM2);
0f7d7385
JL		 584 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
585}
586
587// 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
5888.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
589"mov"
590*am33
591{
9c55817e 592 int dstreg;
0f7d7385
JL		 593
594 PC = cia;
9c55817e 595 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 596
597 if (XRM2 == 0)
598 {
599 State.regs[dstreg] = State.regs[REG_SP];
600 }
601 else
602 abort ();
603}
604
605// 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
6068.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
607"mov"
608*am33
609{
610 int srcreg;
611
612 PC = cia;
9c55817e 613 srcreg = translate_rreg (SD_, RM2);
0f7d7385
JL		 614
615 if (XRN0 == 0)
616 {
617 State.regs[REG_SP] = State.regs[srcreg];
618 }
619 else
620 abort ();
621}
622
623// 1111 1001 0000 1001 Rm Rn; and Rm,Rn
6248.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
625"and"
626*am33
627{
628 int srcreg, dstreg;
629 int z, n;
630
631 PC = cia;
632
9c55817e
JL		 633 srcreg = translate_rreg (SD_, RM2);
634 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 635
636 State.regs[dstreg] &= State.regs[srcreg];
637 z = (State.regs[dstreg] == 0);
638 n = (State.regs[dstreg] & 0x80000000) != 0;
639 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
640 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
641}
642
643// 1111 1001 0001 1001 Rm Rn; or Rm,Rn
6448.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
645"or"
646*am33
647{
648 int srcreg, dstreg;
649 int z, n;
650
651 PC = cia;
9c55817e
JL		 652 srcreg = translate_rreg (SD_, RM2);
653 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 654
655 State.regs[dstreg] |= State.regs[srcreg];
656 z = (State.regs[dstreg] == 0);
657 n = (State.regs[dstreg] & 0x80000000) != 0;
658 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
659 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
660}
661
662// 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
6638.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
664"xor"
665*am33
666{
667 int srcreg, dstreg;
668 int z, n;
669
670 PC = cia;
9c55817e
JL		 671 srcreg = translate_rreg (SD_, RM2);
672 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 673
674 State.regs[dstreg] ^= State.regs[srcreg];
675 z = (State.regs[dstreg] == 0);
676 n = (State.regs[dstreg] & 0x80000000) != 0;
677 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
678 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
679}
680
681// 1111 1001 0011 1001 Rn Rn; not Rn
6828.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
683"not"
684*am33
685{
686 int dstreg;
687 int z, n;
688
689 PC = cia;
9c55817e 690 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 691
692 State.regs[dstreg] = ~State.regs[dstreg];
693 z = (State.regs[dstreg] == 0);
694 n = (State.regs[dstreg] & 0x80000000) != 0;
695 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
696 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
697}
698
699// 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
7008.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
701"asr"
702*am33
703{
704 int srcreg, dstreg;
705 long temp;
706 int c, z, n;
707
708 PC = cia;
9c55817e
JL		 709 srcreg = translate_rreg (SD_, RM2);
710 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 711
712 temp = State.regs[dstreg];
713 c = temp & 1;
714 temp >>= State.regs[srcreg];
715 State.regs[dstreg] = temp;
716 z = (State.regs[dstreg] == 0);
717 n = (State.regs[dstreg] & 0x80000000) != 0;
718 PSW &= ~(PSW_Z | PSW_N | PSW_C);
719 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
720}
721
722// 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
7238.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
724"lsr"
725*am33
726{
727 int srcreg, dstreg;
728 int z, n, c;
729
730 PC = cia;
731
9c55817e
JL		 732 srcreg = translate_rreg (SD_, RM2);
733 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 734
735 c = State.regs[dstreg] & 1;
736 State.regs[dstreg] >>= State.regs[srcreg];
737 z = (State.regs[dstreg] == 0);
738 n = (State.regs[dstreg] & 0x80000000) != 0;
739 PSW &= ~(PSW_Z | PSW_N | PSW_C);
740 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
741}
742
743// 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
7448.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
745"asl"
746*am33
747{
748 int srcreg, dstreg;
749 int z, n;
750
751 PC = cia;
9c55817e
JL		 752 srcreg = translate_rreg (SD_, RM2);
753 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 754
755 State.regs[dstreg] <<= State.regs[srcreg];
756 z = (State.regs[dstreg] == 0);
757 n = (State.regs[dstreg] & 0x80000000) != 0;
758 PSW &= ~(PSW_Z | PSW_N);
759 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
760}
761
762// 1111 1001 0111 1001 Rn Rn; asl2 Rn
7638.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
764"asl2"
765*am33
766{
767 int dstreg;
768 int n, z;
769
770 PC = cia;
9c55817e 771 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 772
773 State.regs[dstreg] <<= 2;
774 z = (State.regs[dstreg] == 0);
775 n = (State.regs[dstreg] & 0x80000000) != 0;
776 PSW &= ~(PSW_Z | PSW_N);
777 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
778}
779
780// 1111 1001 1000 1001 Rn Rn; ror Rn
7818.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
782"ror"
783*am33
784{
785 int dstreg;
786 int c, n, z;
787 unsigned long value;
788
789 PC = cia;
9c55817e 790 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 791
792 value = State.regs[dstreg];
793 c = (value & 0x1);
794
795 value >>= 1;
796 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
797 State.regs[dstreg] = value;
798 z = (value == 0);
799 n = (value & 0x80000000) != 0;
800 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
801 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
802}
803
804// 1111 1001 1001 1001 Rn Rn; rol Rn
8058.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
806"rol"
807*am33
808{
809 int dstreg;
810 int c, n, z;
811 unsigned long value;
812
813 PC = cia;
9c55817e 814 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 815
816 value = State.regs[dstreg];
817 c = (value & 0x80000000) ? 1 : 0;
818
819 value <<= 1;
820 value |= ((PSW & PSW_C) != 0);
821 State.regs[dstreg] = value;
822 z = (value == 0);
823 n = (value & 0x80000000) != 0;
824 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
825 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
826}
827
828// 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
8298.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
830"mul"
831*am33
832{
833 int srcreg, dstreg;
834 unsigned long long temp;
835 int n, z;
836
837 PC = cia;
9c55817e
JL		 838 srcreg = translate_rreg (SD_, RM2);
839 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 840
841 temp = ((signed64)(signed32)State.regs[dstreg]
842 * (signed64)(signed32)State.regs[srcreg]);
843 State.regs[dstreg] = temp & 0xffffffff;
844 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
845 z = (State.regs[dstreg] == 0);
846 n = (State.regs[dstreg] & 0x80000000) != 0;
847 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
848 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
849}
850
851// 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
8528.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
853"mulu"
854*am33
855{
856 int srcreg, dstreg;
857 unsigned long long temp;
858 int n, z;
859
860 PC = cia;
9c55817e
JL		 861 srcreg = translate_rreg (SD_, RM2);
862 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 863
864 temp = ((unsigned64)State.regs[dstreg]
865 * (unsigned64)State.regs[srcreg]);
866 State.regs[dstreg] = temp & 0xffffffff;
867 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
868 z = (State.regs[dstreg] == 0);
869 n = (State.regs[dstreg] & 0x80000000) != 0;
870 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
871 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
872}
873
874// 1111 1001 1100 1001 Rm Rn; div Rm,Rn
8758.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
876"div"
877*am33
878{
879 int srcreg, dstreg;
377e53bb 880 long long temp;
0f7d7385
JL		 881 int n, z;
882
883 PC = cia;
9c55817e
JL		 884 srcreg = translate_rreg (SD_, RM2);
885 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 886
887 temp = State.regs[REG_MDR];
888 temp <<= 32;
889 temp |= State.regs[dstreg];
377e53bb 890 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
4e86afb8 891 temp /= (signed32)State.regs[srcreg];
0f7d7385
JL		 892 State.regs[dstreg] = temp & 0xffffffff;
893 z = (State.regs[dstreg] == 0);
894 n = (State.regs[dstreg] & 0x80000000) != 0;
895 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
896 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
897}
898
899// 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
9008.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
901"divu"
902*am33
903{
904 int srcreg, dstreg;
905 unsigned long long temp;
906 int n, z;
907
908 PC = cia;
9c55817e
JL		 909 srcreg = translate_rreg (SD_, RM2);
910 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 911
912 temp = State.regs[REG_MDR];
913 temp <<= 32;
914 temp |= State.regs[dstreg];
915 State.regs[REG_MDR] = temp % State.regs[srcreg];
916 temp /= State.regs[srcreg];
917 State.regs[dstreg] = temp & 0xffffffff;
918 z = (State.regs[dstreg] == 0);
919 n = (State.regs[dstreg] & 0x80000000) != 0;
920 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
921 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
922}
923
924
925// 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
3e75ff7e 9268.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
0f7d7385
JL		 927"mov"
928*am33
929{
930 int srcreg, dstreg;
931
932 PC = cia;
9c55817e
JL		 933 srcreg = translate_rreg (SD_, RM0);
934 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 935 State.regs[dstreg] = load_word (State.regs[srcreg]);
936}
937
938// 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
9398.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
940"mov"
941*am33
942{
943 int srcreg, dstreg;
944
945 PC = cia;
9c55817e
JL		 946 srcreg = translate_rreg (SD_, RM2);
947 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 948 store_word (State.regs[dstreg], State.regs[srcreg]);
949}
950
951// 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
3e75ff7e 9528.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
0f7d7385
JL		 953"movbu"
954*am33
955{
956 int srcreg, dstreg;
957
958 PC = cia;
9c55817e
JL		 959 srcreg = translate_rreg (SD_, RM0);
960 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 961 State.regs[dstreg] = load_byte (State.regs[srcreg]);
962}
963
964// 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
9658.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
966"movbu"
967*am33
968{
969 int srcreg, dstreg;
970
971 PC = cia;
9c55817e
JL		 972 srcreg = translate_rreg (SD_, RM2);
973 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 974 store_byte (State.regs[dstreg], State.regs[srcreg]);
975}
976
977// 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
3e75ff7e 9788.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
0f7d7385
JL		 979"movhu"
980*am33
981{
982 int srcreg, dstreg;
983
984 PC = cia;
9c55817e
JL		 985 srcreg = translate_rreg (SD_, RM0);
986 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 987 State.regs[dstreg] = load_half (State.regs[srcreg]);
988}
989
990// 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
9918.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
992"movhu"
993*am33
994{
995 int srcreg, dstreg;
996
997 PC = cia;
9c55817e
JL		 998 srcreg = translate_rreg (SD_, RM2);
999 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 1000 store_half (State.regs[dstreg], State.regs[srcreg]);
1001}
1002
377e53bb
JL		 1003// 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
10048.0xf9+8.0x6a+4.RN2,4.RM0:D1y:::mov
1005"mov"
1006*am33
1007{
1008 int srcreg, dstreg;
1009
1010 PC = cia;
9c55817e
JL		 1011 srcreg = translate_rreg (SD_, RM0);
1012 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1013 State.regs[dstreg] = load_word (State.regs[srcreg]);
1014 State.regs[srcreg] += 4;
1015}
1016
1017// 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
10188.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1019"mov"
1020*am33
1021{
1022 int srcreg, dstreg;
1023
1024 PC = cia;
9c55817e
JL		 1025 srcreg = translate_rreg (SD_, RM2);
1026 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1027 store_word (State.regs[dstreg], State.regs[srcreg]);
1028 State.regs[dstreg] += 4;
1029}
0f7d7385
JL		 1030
1031// 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
10328.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1033"mov"
1034*am33
1035{
9c55817e 1036 int dstreg;
0f7d7385
JL		 1037
1038 PC = cia;
9c55817e 1039 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 1040 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1041}
1042
1043// 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
10448.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1045"mov"
1046*am33
1047{
9c55817e 1048 int srcreg;
0f7d7385
JL		 1049
1050 PC = cia;
9c55817e
JL		 1051 srcreg = translate_rreg (SD_, RM2);
1052 store_word (State.regs[REG_SP], State.regs[srcreg]);
0f7d7385
JL		 1053}
1054
1055// 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
10568.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1057"movbu"
1058*am33
1059{
9c55817e 1060 int dstreg;
0f7d7385
JL		 1061
1062 PC = cia;
9c55817e 1063 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 1064 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1065}
1066
1067// 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
10688.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1069"movbu"
1070*am33
1071{
9c55817e 1072 int srcreg;
0f7d7385
JL		 1073
1074 PC = cia;
9c55817e
JL		 1075 srcreg = translate_rreg (SD_, RM2);
1076 store_byte (State.regs[REG_SP], State.regs[srcreg]);
0f7d7385
JL		 1077}
1078
1079// 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
10808.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1081"movhu"
1082*am33
1083{
9c55817e 1084 int dstreg;
0f7d7385
JL		 1085
1086 PC = cia;
9c55817e 1087 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 1088 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1089}
1090
1091// 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
10928.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1093"movhu"
1094*am33
1095{
9c55817e 1096 int srcreg;
0f7d7385
JL		 1097
1098 PC = cia;
9c55817e
JL		 1099 srcreg = translate_rreg (SD_, RM2);
1100 store_half (State.regs[REG_SP], State.regs[srcreg]);
0f7d7385
JL		 1101}
1102
377e53bb
JL		 1103// 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
11048.0xf9+8.0xea+4.RN2,4.RM0:D1y:::movhu
1105"movhu"
0f7d7385
JL		 1106*am33
1107{
377e53bb 1108 int srcreg, dstreg;
0f7d7385
JL		 1109
1110 PC = cia;
9c55817e
JL		 1111 srcreg = translate_rreg (SD_, RM0);
1112 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1113 State.regs[dstreg] = load_half (State.regs[srcreg]);
1114 State.regs[srcreg] += 2;
0f7d7385
JL		 1115}
1116
377e53bb
JL		 1117// 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
11188.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1119"movhu"
0f7d7385
JL		 1120*am33
1121{
377e53bb 1122 int srcreg, dstreg;
0f7d7385
JL		 1123
1124 PC = cia;
9c55817e
JL		 1125 srcreg = translate_rreg (SD_, RM2);
1126 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1127 store_half (State.regs[dstreg], State.regs[srcreg]);
1128 State.regs[dstreg] += 2;
0f7d7385
JL		 1129}
1130
377e53bb
JL		 1131
1132// 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
11338.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1134"mac"
0f7d7385
JL		 1135*am33
1136{
377e53bb
JL		 1137 int srcreg1, srcreg2;
1138 long long temp, sum;
1139 int c, v;
0f7d7385
JL		 1140
1141 PC = cia;
9c55817e
JL		 1142 srcreg1 = translate_rreg (SD_, RM2);
1143 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1144
4e86afb8
JL		 1145 temp = ((signed64)(signed32)State.regs[srcreg2]
1146 * (signed64)(signed32)State.regs[srcreg1]);
377e53bb
JL		 1147 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1148 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1149 State.regs[REG_MCRL] = sum;
1150 temp >>= 32;
1151 temp &= 0xffffffff;
1152 sum = State.regs[REG_MCRH] + temp + c;
1153 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1154 && (temp & 0x80000000) != (sum & 0x80000000));
1155 State.regs[REG_MCRH] = sum;
1156 if (v)
1157 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1158}
1159
377e53bb
JL		 1160// 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
11618.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1162"macu"
0f7d7385
JL		 1163*am33
1164{
377e53bb
JL		 1165 int srcreg1, srcreg2;
1166 unsigned long long temp, sum;
1167 int c, v;
0f7d7385
JL		 1168
1169 PC = cia;
9c55817e
JL		 1170 srcreg1 = translate_rreg (SD_, RM2);
1171 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1172
377e53bb
JL		 1173 temp = ((unsigned64)State.regs[srcreg2]
1174 * (unsigned64)State.regs[srcreg1]);
1175 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1176 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1177 State.regs[REG_MCRL] = sum;
1178 temp >>= 32;
1179 temp &= 0xffffffff;
1180 sum = State.regs[REG_MCRH] + temp + c;
1181 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1182 && (temp & 0x80000000) != (sum & 0x80000000));
1183 State.regs[REG_MCRH] = sum;
1184 if (v)
1185 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1186}
1187
377e53bb
JL		 1188// 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
11898.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1190"macb"
0f7d7385
JL		 1191*am33
1192{
377e53bb
JL		 1193 int srcreg1, srcreg2;
1194 long temp, sum;
1195 int v;
0f7d7385
JL		 1196
1197 PC = cia;
9c55817e
JL		 1198 srcreg1 = translate_rreg (SD_, RM2);
1199 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1200
4e86afb8
JL		 1201 temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
1202 * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
377e53bb
JL		 1203 sum = State.regs[REG_MCRL] + temp;
1204 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1205 && (temp & 0x80000000) != (sum & 0x80000000));
1206 State.regs[REG_MCRL] = sum;
1207 if (v)
1208 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1209}
1210
377e53bb
JL		 1211// 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
12128.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1213"macbu"
0f7d7385
JL		 1214*am33
1215{
377e53bb
JL		 1216 int srcreg1, srcreg2;
1217 long long temp, sum;
1218 int v;
0f7d7385
JL		 1219
1220 PC = cia;
9c55817e
JL		 1221 srcreg1 = translate_rreg (SD_, RM2);
1222 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1223
377e53bb
JL		 1224 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1225 * (unsigned32)(State.regs[srcreg1] & 0xff));
1226 sum = State.regs[REG_MCRL] + temp;
1227 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1228 && (temp & 0x80000000) != (sum & 0x80000000));
1229 State.regs[REG_MCRL] = sum;
1230 if (v)
1231 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1232}
1233
377e53bb
JL		 1234// 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
12358.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1236"mach"
0f7d7385
JL		 1237*am33
1238{
377e53bb
JL		 1239 int srcreg1, srcreg2;
1240 long long temp, sum;
1241 int c, v;
0f7d7385
JL		 1242
1243 PC = cia;
9c55817e
JL		 1244 srcreg1 = translate_rreg (SD_, RM2);
1245 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1246
4e86afb8
JL		 1247 temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
1248 * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
377e53bb
JL		 1249 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1250 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1251 State.regs[REG_MCRL] = sum;
1252 temp >>= 32;
1253 temp &= 0xffffffff;
1254 sum = State.regs[REG_MCRH] + temp + c;
1255 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1256 && (temp & 0x80000000) != (sum & 0x80000000));
1257 State.regs[REG_MCRH] = sum;
1258 if (v)
1259 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1260}
1261
377e53bb
JL		 1262// 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
12638.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1264"machu"
0f7d7385
JL		 1265*am33
1266{
377e53bb
JL		 1267 int srcreg1, srcreg2;
1268 long long temp, sum;
1269 int c, v;
0f7d7385
JL		 1270
1271 PC = cia;
9c55817e
JL		 1272 srcreg1 = translate_rreg (SD_, RM2);
1273 srcreg2 = translate_rreg (SD_, RN0);
377e53bb
JL		 1274
1275 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1276 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1277 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1278 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1279 State.regs[REG_MCRL] = sum;
1280 temp >>= 32;
1281 temp &= 0xffffffff;
1282 sum = State.regs[REG_MCRH] + temp + c;
1283 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1284 && (temp & 0x80000000) != (sum & 0x80000000));
1285 State.regs[REG_MCRH] = sum;
1286 if (v)
1287 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1288}
1289
377e53bb
JL		 1290// 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
12918.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1292"dmach"
0f7d7385
JL		 1293*am33
1294{
377e53bb
JL		 1295 int srcreg1, srcreg2;
1296 long temp, temp2, sum;
1297 int v;
0f7d7385
JL		 1298
1299 PC = cia;
9c55817e
JL		 1300 srcreg1 = translate_rreg (SD_, RM2);
1301 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1302
4e86afb8
JL		 1303 temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
1304 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
1305 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
1306 * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
377e53bb
JL		 1307 sum = temp + temp2 + State.regs[REG_MCRL];
1308 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1309 && (temp & 0x80000000) != (sum & 0x80000000));
1310 State.regs[REG_MCRL] = sum;
1311 if (v)
1312 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1313}
1314
377e53bb
JL		 1315// 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
13168.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1317"dmachu"
0f7d7385
JL		 1318*am33
1319{
377e53bb
JL		 1320 int srcreg1, srcreg2;
1321 unsigned long temp, temp2, sum;
1322 int v;
0f7d7385
JL		 1323
1324 PC = cia;
9c55817e
JL		 1325 srcreg1 = translate_rreg (SD_, RM2);
1326 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1327
377e53bb
JL		 1328 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1329 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1330 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1331 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1332 sum = temp + temp2 + State.regs[REG_MCRL];
1333 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1334 && (temp & 0x80000000) != (sum & 0x80000000));
1335 State.regs[REG_MCRL] = sum;
1336 if (v)
1337 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1338}
1339
377e53bb
JL		 1340// 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
13418.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1342"dmulh"
0f7d7385
JL		 1343*am33
1344{
377e53bb
JL		 1345 int srcreg, dstreg;
1346 long temp;
0f7d7385
JL		 1347
1348 PC = cia;
9c55817e
JL		 1349 srcreg = translate_rreg (SD_, RM2);
1350 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1351
4e86afb8
JL		 1352 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
1353 * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
377e53bb 1354 State.regs[REG_MDRQ] = temp;
4e86afb8
JL		 1355 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
1356 * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
377e53bb 1357 State.regs[dstreg] = temp;
0f7d7385
JL		 1358}
1359
377e53bb
JL		 1360// 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
13618.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1362"dmachu"
0f7d7385
JL		 1363*am33
1364{
377e53bb
JL		 1365 int srcreg, dstreg;
1366 unsigned long temp;
0f7d7385
JL		 1367
1368 PC = cia;
9c55817e
JL		 1369 srcreg = translate_rreg (SD_, RM2);
1370 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1371
377e53bb
JL		 1372 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1373 * (unsigned32)(State.regs[srcreg] & 0xffff));
1374 State.regs[REG_MDRQ] = temp;
1375 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1376 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
0f7d7385 1377 State.regs[dstreg] = temp;
0f7d7385
JL		 1378}
1379
377e53bb
JL		 1380// 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
13818.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1382"sat16"
0f7d7385
JL		 1383*am33
1384{
377e53bb 1385 int srcreg, dstreg;
4e86afb8 1386 int value, z, n;
0f7d7385
JL		 1387
1388 PC = cia;
9c55817e
JL		 1389 srcreg = translate_rreg (SD_, RM2);
1390 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1391
377e53bb
JL		 1392 value = State.regs[srcreg];
1393
1394 if (value >= 0x7fff)
1395 State.regs[dstreg] = 0x7fff;
1396 else if (value <= 0xffff8000)
1397 State.regs[dstreg] = 0xffff8000;
1398 else
1399 State.regs[dstreg] = value;
4e86afb8
JL		 1400
1401 n = (State.regs[dstreg] & 0x8000) != 0;
1402 z = (State.regs[dstreg] == 0);
1403 PSW &= ~(PSW_Z | PSW_N);
1404 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1405}
1406
1f0ba346
JL		 1407// 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
14088.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1409"mcste"
1410*am33
1411{
1412 int srcreg, dstreg;
1413
1414 PC = cia;
1415 srcreg = translate_rreg (SD_, RM2);
1416 dstreg = translate_rreg (SD_, RN0);
1417
1418 PSW &= ~(PSW_V | PSW_C);
1419 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1420
1421 /* 32bit saturation. */
1422 if (State.regs[srcreg] == 0x20)
1423 {
1424 long long tmp;
1425
1426 tmp = State.regs[REG_MCRH];
1427 tmp <<= 32;
1428 tmp += State.regs[REG_MCRL];
1429
1430 if (tmp > 0x7fffffff)
1431 State.regs[dstreg] = 0x7fffffff;
1432 else if (tmp < 0xffffffff80000000LL)
1433 State.regs[dstreg] = 0x80000000;
1434 else
1435 State.regs[dstreg] = tmp;
1436 }
1437 /* 16bit saturation */
1438 else if (State.regs[srcreg] == 0x10)
1439 {
1440 long long tmp;
1441
1442 tmp = State.regs[REG_MCRH];
1443 tmp <<= 32;
1444 tmp += State.regs[REG_MCRL];
1445
1446 if (tmp > 0x7fff)
1447 State.regs[dstreg] = 0x7fff;
1448 else if (tmp < 0xffffffffffff8000LL)
1449 State.regs[dstreg] = 0x8000;
1450 else
1451 State.regs[dstreg] = tmp;
1452 }
1453 /* 8 bit saturation */
1454 else if (State.regs[srcreg] == 0x8)
1455 {
1456 long long tmp;
1457
1458 tmp = State.regs[REG_MCRH];
1459 tmp <<= 32;
1460 tmp += State.regs[REG_MCRL];
1461
1462 if (tmp > 0x7f)
1463 State.regs[dstreg] = 0x7f;
1464 else if (tmp < 0xffffffffffffff80LL)
1465 State.regs[dstreg] = 0x80;
1466 else
1467 State.regs[dstreg] = tmp;
1468 }
1469 /* 9 bit saturation */
1470 else if (State.regs[srcreg] == 0x9)
1471 {
1472 long long tmp;
1473
1474 tmp = State.regs[REG_MCRH];
1475 tmp <<= 32;
1476 tmp += State.regs[REG_MCRL];
1477
1478 if (tmp > 0x80)
1479 State.regs[dstreg] = 0x80;
1480 else if (tmp < 0xffffffffffffff81LL)
1481 State.regs[dstreg] = 0x81;
1482 else
1483 State.regs[dstreg] = tmp;
1484 }
1485 /* 9 bit saturation */
1486 else if (State.regs[srcreg] == 0x30)
1487 {
1488 long long tmp;
1489
1490 tmp = State.regs[REG_MCRH];
1491 tmp <<= 32;
1492 tmp += State.regs[REG_MCRL];
1493
1494 if (tmp > 0x7fffffffffffLL)
1495 tmp = 0x7fffffffffffLL;
1496 else if (tmp < 0xffff800000000000LL)
1497 tmp = 0xffff800000000000LL;
1498
1499 tmp >>= 16;
1500 State.regs[dstreg] = tmp;
1501 }
1502}
377e53bb
JL		 1503
1504// 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
15058.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1506"swap"
0f7d7385
JL		 1507*am33
1508{
1509 int srcreg, dstreg;
0f7d7385 1510
9c55817e
JL		 1511 PC = cia;
1512 srcreg = translate_rreg (SD_, RM2);
1513 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1514
377e53bb
JL		 1515 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1516 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1517 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1518 | ((State.regs[srcreg] >> 24) & 0xff));
0f7d7385
JL		 1519}
1520
377e53bb
JL		 1521// 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
15228.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1523"swaph"
0f7d7385
JL		 1524*am33
1525{
377e53bb 1526 int srcreg, dstreg;
0f7d7385 1527
9c55817e
JL		 1528 PC = cia;
1529 srcreg = translate_rreg (SD_, RM2);
1530 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1531
377e53bb
JL		 1532 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1533 | ((State.regs[srcreg] >> 8) & 0xff)
1534 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1535 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
0f7d7385
JL		 1536}
1537
377e53bb
JL		 1538// 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
15398.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1540"swhw"
0f7d7385
JL		 1541*am33
1542{
377e53bb 1543 int srcreg, dstreg;
0f7d7385 1544
9c55817e
JL		 1545 PC = cia;
1546 srcreg = translate_rreg (SD_, RM2);
1547 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1548
377e53bb
JL		 1549 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1550 | ((State.regs[srcreg] >> 16) & 0xffff));
0f7d7385
JL		 1551}
1552
377e53bb
JL		 1553// 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
15548.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1555"bsch"
3e75ff7e
JL		 1556*am33
1557{
377e53bb
JL		 1558 int temp, c, i;
1559 int srcreg, dstreg;
1560 int start;
3e75ff7e
JL		 1561
1562 PC = cia;
9c55817e
JL		 1563 srcreg = translate_rreg (SD_, RM2);
1564 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1565
1566 temp = State.regs[srcreg];
1567 start = (State.regs[dstreg] & 0x1f) - 1;
1568 if (start == -1)
1569 start = 31;
1570
1571 for (i = start; i >= 0; i--)
1572 {
1573 if (temp & (1 << i))
1574 {
1575 c = 1;
1576 State.regs[dstreg] = i;
1577 break;
1578 }
1579 }
3e75ff7e 1580
377e53bb
JL		 1581 if (i < 0)
1582 {
1583 c = 0;
1584 State.regs[dstreg] = 0;
1585 }
1586 PSW &= ~(PSW_C);
1587 PSW |= (c ? PSW_C : 0);
3e75ff7e
JL		 1588}
1589
0f7d7385 1590
377e53bb
JL		 1591// 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
15928.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
0f7d7385 1593"mov"
3e75ff7e 1594*am33
0f7d7385 1595{
377e53bb 1596 int dstreg;
0f7d7385
JL		 1597
1598 PC = cia;
9c55817e 1599 dstreg = translate_rreg (SD_, RN0);
377e53bb 1600 State.regs[dstreg] = EXTEND8 (IMM8);
0f7d7385
JL		 1601}
1602
377e53bb
JL		 1603// 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
16048.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1605"movu"
1606*am33
0f7d7385 1607{
377e53bb 1608 int dstreg;
0f7d7385
JL		 1609
1610 PC = cia;
9c55817e 1611 dstreg = translate_rreg (SD_, RN0);
377e53bb 1612 State.regs[dstreg] = IMM8 & 0xff;
0f7d7385
JL		 1613}
1614
377e53bb
JL		 1615// 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
16168.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1617"add"
1618*am33
0f7d7385 1619{
377e53bb 1620 int dstreg;
0f7d7385
JL		 1621
1622 PC = cia;
9c55817e 1623 dstreg = translate_rreg (SD_, RN0);
377e53bb 1624 genericAdd (EXTEND8 (IMM8), dstreg);
0f7d7385
JL		 1625}
1626
377e53bb
JL		 1627// 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
16288.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1629"addc"
1630*am33
0f7d7385 1631{
377e53bb
JL		 1632 int dstreg, imm;
1633 int z, c, n, v;
1634 unsigned long reg1, reg2, sum;
0f7d7385
JL		 1635
1636 PC = cia;
9c55817e 1637 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1638
377e53bb
JL		 1639 imm = EXTEND8 (IMM8);
1640 reg2 = State.regs[dstreg];
1641 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1642 State.regs[dstreg] = sum;
1643
1644 z = (sum == 0);
1645 n = (sum & 0x80000000);
1646 c = (sum < imm) || (sum < reg2);
1647 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1648 && (reg2 & 0x80000000) != (sum & 0x80000000));
1649
1650 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1651 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1652 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
0f7d7385
JL		 1653}
1654
377e53bb
JL		 1655// 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
16568.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1657"sub"
1658*am33
0f7d7385 1659{
377e53bb 1660 int dstreg;
0f7d7385
JL		 1661
1662 PC = cia;
9c55817e 1663 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1664
377e53bb 1665 genericSub (EXTEND8 (IMM8), dstreg);
0f7d7385
JL		 1666}
1667
377e53bb
JL		 1668// 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
16698.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1670"subc"
1671*am33
0f7d7385 1672{
377e53bb
JL		 1673 int imm, dstreg;
1674 int z, c, n, v;
1675 unsigned long reg1, reg2, difference;
0f7d7385
JL		 1676
1677 PC = cia;
9c55817e 1678 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1679
377e53bb
JL		 1680 imm = EXTEND8 (IMM8);
1681 reg2 = State.regs[dstreg];
1682 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1683 State.regs[dstreg] = difference;
0f7d7385 1684
377e53bb
JL		 1685 z = (difference == 0);
1686 n = (difference & 0x80000000);
1687 c = (imm > reg2);
1688 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1689 && (reg2 & 0x80000000) != (difference & 0x80000000));
0f7d7385 1690
377e53bb
JL		 1691 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1692 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1693 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1694}
1695
1696// 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
16978.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1698"cmp"
1699*am33
0f7d7385 1700{
377e53bb 1701 int srcreg;
0f7d7385
JL		 1702
1703 PC = cia;
9c55817e 1704 srcreg = translate_rreg (SD_, RN0);
377e53bb 1705 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
0f7d7385
JL		 1706}
1707
377e53bb
JL		 1708// 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
17098.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
0f7d7385 1710"mov"
377e53bb 1711*am33
0f7d7385 1712{
377e53bb 1713 int dstreg;
0f7d7385
JL		 1714
1715 PC = cia;
1716
377e53bb
JL		 1717 if (XRN0 == 0)
1718 State.regs[REG_SP] = EXTEND8 (IMM8);
0f7d7385 1719 else
377e53bb 1720 abort ();
0f7d7385
JL		 1721}
1722
377e53bb
JL		 1723// 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
17248.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1725"and"
1726*am33
0f7d7385
JL		 1727{
1728 int dstreg;
377e53bb 1729 int z, n;
0f7d7385
JL		 1730
1731 PC = cia;
9c55817e 1732 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1733
377e53bb
JL		 1734 State.regs[dstreg] &= (IMM8 & 0xff);
1735 z = (State.regs[dstreg] == 0);
1736 n = (State.regs[dstreg] & 0x80000000) != 0;
1737 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1738 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1739}
1740
377e53bb
JL		 1741// 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
17428.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1743"or"
1744*am33
0f7d7385 1745{
377e53bb
JL		 1746 int dstreg;
1747 int z, n;
0f7d7385
JL		 1748
1749 PC = cia;
9c55817e 1750 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1751
377e53bb
JL		 1752 State.regs[dstreg] |= (IMM8 & 0xff);
1753 z = (State.regs[dstreg] == 0);
1754 n = (State.regs[dstreg] & 0x80000000) != 0;
1755 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1756 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1757}
1758
377e53bb
JL		 1759// 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
17608.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1761"xor"
1762*am33
0f7d7385
JL		 1763{
1764 int dstreg;
377e53bb 1765 int z, n;
0f7d7385
JL		 1766
1767 PC = cia;
9c55817e 1768 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1769
377e53bb
JL		 1770 State.regs[dstreg] ^= (IMM8 & 0xff);
1771 z = (State.regs[dstreg] == 0);
1772 n = (State.regs[dstreg] & 0x80000000) != 0;
1773 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1774 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1775}
1776
377e53bb
JL		 1777// 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
17788.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1779"asr"
1780*am33
0f7d7385 1781{
377e53bb
JL		 1782 int dstreg;
1783 long temp;
1784 int c, z, n;
0f7d7385
JL		 1785
1786 PC = cia;
9c55817e 1787 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1788
377e53bb
JL		 1789 temp = State.regs[dstreg];
1790 c = temp & 1;
1791 temp >>= (IMM8 & 0xff);
1792 State.regs[dstreg] = temp;
1793 z = (State.regs[dstreg] == 0);
1794 n = (State.regs[dstreg] & 0x80000000) != 0;
1795 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1796 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
0f7d7385
JL		 1797}
1798
377e53bb
JL		 1799// 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
18008.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1801"lsr"
1802*am33
1803{
1804 int dstreg;
1805 int z, n, c;
1806
1807 PC = cia;
9c55817e 1808 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1809
1810 c = State.regs[dstreg] & 1;
1811 State.regs[dstreg] >>= (IMM8 & 0xff);
1812 z = (State.regs[dstreg] == 0);
1813 n = (State.regs[dstreg] & 0x80000000) != 0;
1814 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1815 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1816}
1817
1818// 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
18198.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1820"asl"
1821*am33
1822{
1823 int srcreg, dstreg;
1824 int z, n;
1825
1826 PC = cia;
9c55817e 1827 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1828
1829 State.regs[dstreg] <<= (IMM8 & 0xff);
1830 z = (State.regs[dstreg] == 0);
1831 n = (State.regs[dstreg] & 0x80000000) != 0;
1832 PSW &= ~(PSW_Z | PSW_N);
1833 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1834}
1835
1836// 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
18378.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1838"mul"
1839*am33
1840{
1841 int dstreg;
1842 unsigned long long temp;
1843 int z, n;
1844
1845 PC = cia;
9c55817e 1846 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1847
1848 temp = ((signed64)(signed32)State.regs[dstreg]
1849 * (signed64)(signed32)EXTEND8 (IMM8));
1850 State.regs[dstreg] = temp & 0xffffffff;
1851 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1852 z = (State.regs[dstreg] == 0);
1853 n = (State.regs[dstreg] & 0x80000000) != 0;
1854 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1855 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1856}
1857
1858// 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
18598.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1860"mulu"
1861*am33
1862{
1863 int dstreg;
1864 unsigned long long temp;
1865 int z, n;
1866
1867 PC = cia;
9c55817e 1868 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1869
1870 temp = ((unsigned64)State.regs[dstreg]
1871 * (unsigned64)(IMM8 & 0xff));
1872 State.regs[dstreg] = temp & 0xffffffff;
1873 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1874 z = (State.regs[dstreg] == 0);
1875 n = (State.regs[dstreg] & 0x80000000) != 0;
1876 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1877 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1878}
1879
1880// 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
18818.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1882"btst"
1883*am33
1884{
1885 int srcreg;
1886
1887 PC = cia;
9c55817e 1888 srcreg = translate_rreg (SD_, RM0);
377e53bb 1889 genericBtst(IMM8, State.regs[srcreg]);
377e53bb
JL		 1890}
1891
1892
1893// 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
18948.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1895"mov"
1896*am33
1897{
1898 int srcreg, dstreg;
1899
1900 PC = cia;
9c55817e
JL		 1901 srcreg = translate_rreg (SD_, RM0);
1902 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1903 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1904}
1905
1906// 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
19078.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1908"mov"
1909{
1910 int srcreg, dstreg;
1911
1912 PC = cia;
9c55817e
JL		 1913 srcreg = translate_rreg (SD_, RM2);
1914 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1915 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1916}
1917
1918// 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
19198.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1920"movbu"
1921{
1922 int srcreg, dstreg;
1923
1924 PC = cia;
9c55817e
JL		 1925 srcreg = translate_rreg (SD_, RM0);
1926 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1927 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1928}
1929
1930// 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
19318.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1932"movbu"
1933{
1934 int srcreg, dstreg;
1935
1936 PC = cia;
9c55817e
JL		 1937 srcreg = translate_rreg (SD_, RM2);
1938 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1939 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1940}
1941
1942// 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
19438.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1944"movhu"
1945{
1946 int srcreg, dstreg;
1947
1948 PC = cia;
9c55817e
JL		 1949 srcreg = translate_rreg (SD_, RM0);
1950 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1951 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1952}
1953
1954// 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
19558.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1956"movhu"
1957{
1958 int srcreg, dstreg;
1959
1960 PC = cia;
9c55817e
JL		 1961 srcreg = translate_rreg (SD_, RM2);
1962 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1963 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1964}
1965
1966// 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
19678.0xfb+8.0x6a+4.RN2,4.RM0+8.IMM8:D2y:::mov
1968"mov"
1969*am33
1970{
1971 int srcreg, dstreg;
1972
1973 PC = cia;
9c55817e
JL		 1974 srcreg = translate_rreg (SD_, RM0);
1975 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1976 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1977 State.regs[srcreg] += 4;
1978}
1979
1980// 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
19818.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
1982"mov"
1983{
1984 int srcreg, dstreg;
1985
1986 PC = cia;
9c55817e
JL		 1987 srcreg = translate_rreg (SD_, RM2);
1988 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1989 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1990 State.regs[dstreg] += 4;
1991}
1992
1993
1994// 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
19958.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
1996"mov"
1997{
1998 int dstreg;
1999
2000 PC = cia;
9c55817e 2001 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2002 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2003}
2004
2005// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
20068.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2007"mov"
2008{
2009 int srcreg;
2010
2011 PC = cia;
9c55817e 2012 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2013 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2014}
2015
2016// 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
20178.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2018"movbu"
2019{
2020 int dstreg;
2021
2022 PC = cia;
9c55817e 2023 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2024 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2025}
2026
2027// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
20288.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2029"movbu"
2030{
2031 int srcreg;
2032
2033 PC = cia;
9c55817e 2034 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2035 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2036}
2037
2038// 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
20398.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2040"movhu"
2041{
2042 int dstreg;
2043
2044 PC = cia;
9c55817e 2045 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2046 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2047}
2048
2049// 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
20508.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2051"movhu"
2052{
2053 int srcreg;
2054
2055 PC = cia;
9c55817e 2056 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2057 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2058}
2059
2060// 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
20618.0xfb+8.0xea+4.RN2,4.RM0+8.IMM8:D2y:::movhu
2062"movhu"
2063*am33
2064{
2065 int srcreg, dstreg;
2066
2067 PC = cia;
9c55817e
JL		 2068 srcreg = translate_rreg (SD_, RM0);
2069 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2070 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
2071 State.regs[srcreg] += 2;
2072}
2073
2074// 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
20758.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2076"movhu"
2077{
2078 int srcreg, dstreg;
2079
2080 PC = cia;
9c55817e
JL		 2081 srcreg = translate_rreg (SD_, RM2);
2082 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 2083 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2084 State.regs[dstreg] += 2;
2085}
2086
2087
2088// 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
20898.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2090"mac"
2091{
9c55817e 2092 int srcreg;
377e53bb
JL		 2093 long long temp, sum;
2094 int c, v;
2095
2096 PC = cia;
9c55817e 2097 srcreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2098
2099 temp = ((signed64)EXTEND8 (IMM8)
9c55817e 2100 * (signed64)State.regs[srcreg]);
377e53bb
JL		 2101 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2102 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2103 State.regs[REG_MCRL] = sum;
2104 temp >>= 32;
2105 temp &= 0xffffffff;
2106 sum = State.regs[REG_MCRH] + temp + c;
2107 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2108 && (temp & 0x80000000) != (sum & 0x80000000));
2109 State.regs[REG_MCRH] = sum;
2110 if (v)
2111 State.regs[REG_MCVF] = 1;
2112}
2113
2114// 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
21158.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2116"macu"
2117{
9c55817e 2118 int srcreg;
377e53bb
JL		 2119 long long temp, sum;
2120 int c, v;
2121
2122 PC = cia;
9c55817e 2123 srcreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2124
2125 temp = ((unsigned64) (IMM8)
9c55817e 2126 * (unsigned64)State.regs[srcreg]);
377e53bb
JL		 2127 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2128 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2129 State.regs[REG_MCRL] = sum;
2130 temp >>= 32;
2131 temp &= 0xffffffff;
2132 sum = State.regs[REG_MCRH] + temp + c;
2133 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2134 && (temp & 0x80000000) != (sum & 0x80000000));
2135 State.regs[REG_MCRH] = sum;
2136 if (v)
2137 State.regs[REG_MCVF] = 1;
2138}
2139
2140// 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
21418.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2142"macb"
2143{
9c55817e 2144 int srcreg;
377e53bb
JL		 2145 long long temp, sum;
2146 int c, v;
2147
2148 PC = cia;
9c55817e 2149 srcreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2150
2151 temp = ((signed64)EXTEND8 (IMM8)
9c55817e 2152 * (signed64)State.regs[srcreg] & 0xff);
377e53bb
JL		 2153 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2154 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2155 State.regs[REG_MCRL] = sum;
2156 temp >>= 32;
2157 temp &= 0xffffffff;
2158 sum = State.regs[REG_MCRH] + temp + c;
2159 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2160 && (temp & 0x80000000) != (sum & 0x80000000));
2161 State.regs[REG_MCRH] = sum;
2162 if (v)
2163 State.regs[REG_MCVF] = 1;
2164}
2165
2166// 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
21678.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2168"macbu"
2169{
9c55817e 2170 int srcreg;
377e53bb
JL		 2171 long long temp, sum;
2172 int c, v;
2173
2174 PC = cia;
9c55817e 2175 srcreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2176
2177 temp = ((unsigned64) (IMM8)
9c55817e 2178 * (unsigned64)State.regs[srcreg] & 0xff);
377e53bb
JL		 2179 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2180 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2181 State.regs[REG_MCRL] = sum;
2182 temp >>= 32;
2183 temp &= 0xffffffff;
2184 sum = State.regs[REG_MCRH] + temp + c;
2185 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2186 && (temp & 0x80000000) != (sum & 0x80000000));
2187 State.regs[REG_MCRH] = sum;
2188 if (v)
2189 State.regs[REG_MCVF] = 1;
2190}
2191
2192// 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
21938.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2194"mach"
2195{
9c55817e 2196 int srcreg;
377e53bb
JL		 2197 long long temp, sum;
2198 int c, v;
2199
2200 PC = cia;
9c55817e 2201 srcreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2202
2203 temp = ((signed64)EXTEND8 (IMM8)
9c55817e 2204 * (signed64)State.regs[srcreg] & 0xffff);
377e53bb
JL		 2205 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2206 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2207 State.regs[REG_MCRL] = sum;
2208 temp >>= 32;
2209 temp &= 0xffffffff;
2210 sum = State.regs[REG_MCRH] + temp + c;
2211 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2212 && (temp & 0x80000000) != (sum & 0x80000000));
2213 State.regs[REG_MCRH] = sum;
2214 if (v)
2215 State.regs[REG_MCVF] = 1;
2216}
2217
2218// 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
22198.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2220"machu"
2221{
9c55817e 2222 int srcreg;
377e53bb
JL		 2223 long long temp, sum;
2224 int c, v;
2225
2226 PC = cia;
9c55817e 2227 srcreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2228
2229 temp = ((unsigned64) (IMM8)
9c55817e 2230 * (unsigned64)State.regs[srcreg] & 0xffff);
377e53bb
JL		 2231 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2232 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2233 State.regs[REG_MCRL] = sum;
2234 temp >>= 32;
2235 temp &= 0xffffffff;
2236 sum = State.regs[REG_MCRH] + temp + c;
2237 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2238 && (temp & 0x80000000) != (sum & 0x80000000));
2239 State.regs[REG_MCRH] = sum;
2240 if (v)
2241 State.regs[REG_MCVF] = 1;
2242}
2243
1f0ba346
JL		 2244// 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
22458.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2246"mcste"
2247{
2248 int dstreg;
2249
2250 PC = cia;
2251 dstreg = translate_rreg (SD_, RN0);
2252
2253 PSW &= ~(PSW_V | PSW_C);
2254 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2255
2256 /* 32bit saturation. */
2257 if (IMM8 == 0x20)
2258 {
2259 long long tmp;
2260
2261 tmp = State.regs[REG_MCRH];
2262 tmp <<= 32;
2263 tmp += State.regs[REG_MCRL];
2264
2265 if (tmp > 0x7fffffff)
2266 State.regs[dstreg] = 0x7fffffff;
2267 else if (tmp < 0xffffffff80000000LL)
2268 State.regs[dstreg] = 0x80000000;
2269 else
2270 State.regs[dstreg] = tmp;
2271 }
2272 /* 16bit saturation */
2273 else if (IMM8 == 0x10)
2274 {
2275 long long tmp;
2276
2277 tmp = State.regs[REG_MCRH];
2278 tmp <<= 32;
2279 tmp += State.regs[REG_MCRL];
2280
2281 if (tmp > 0x7fff)
2282 State.regs[dstreg] = 0x7fff;
2283 else if (tmp < 0xffffffffffff8000LL)
2284 State.regs[dstreg] = 0x8000;
2285 else
2286 State.regs[dstreg] = tmp;
2287 }
2288 /* 8 bit saturation */
2289 else if (IMM8 == 0x8)
2290 {
2291 long long tmp;
2292
2293 tmp = State.regs[REG_MCRH];
2294 tmp <<= 32;
2295 tmp += State.regs[REG_MCRL];
2296
2297 if (tmp > 0x7f)
2298 State.regs[dstreg] = 0x7f;
2299 else if (tmp < 0xffffffffffffff80LL)
2300 State.regs[dstreg] = 0x80;
2301 else
2302 State.regs[dstreg] = tmp;
2303 }
2304 /* 9 bit saturation */
2305 else if (IMM8 == 0x9)
2306 {
2307 long long tmp;
2308
2309 tmp = State.regs[REG_MCRH];
2310 tmp <<= 32;
2311 tmp += State.regs[REG_MCRL];
2312
2313 if (tmp > 0x80)
2314 State.regs[dstreg] = 0x80;
2315 else if (tmp < 0xffffffffffffff81LL)
2316 State.regs[dstreg] = 0x81;
2317 else
2318 State.regs[dstreg] = tmp;
2319 }
2320 /* 9 bit saturation */
2321 else if (IMM8 == 0x30)
2322 {
2323 long long tmp;
2324
2325 tmp = State.regs[REG_MCRH];
2326 tmp <<= 32;
2327 tmp += State.regs[REG_MCRL];
2328
2329 if (tmp > 0x7fffffffffffLL)
2330 tmp = 0x7fffffffffffLL;
2331 else if (tmp < 0xffff800000000000LL)
2332 tmp = 0xffff800000000000LL;
2333
2334 tmp >>= 16;
2335 State.regs[dstreg] = tmp;
2336 }
2337}
377e53bb 2338
0f7d7385
JL		 2339// 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
23408.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2341"add"
2342*am33
2343{
ee61616c 2344 int z, c, n, v;
377e53bb
JL		 2345 unsigned long sum, source1, source2;
2346 int srcreg1, srcreg2, dstreg;
2347
2348 PC = cia;
9c55817e
JL		 2349 srcreg1 = translate_rreg (SD_, RM2);
2350 srcreg2 = translate_rreg (SD_, RN0);
2351 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2352
2353 source1 = State.regs[srcreg1];
2354 source2 = State.regs[srcreg2];
2355 sum = source1 + source2;
2356 State.regs[dstreg] = sum;
2357
2358 z = (sum == 0);
2359 n = (sum & 0x80000000);
2360 c = (sum < source1) || (sum < source2);
2361 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2362 && (source1 & 0x80000000) != (sum & 0x80000000));
2363
2364 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2365 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2366 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2367}
2368
2369// 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
23708.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2371"addc"
2372*am33
2373{
2374 int z, c, n, v;
2375 unsigned long sum, source1, source2;
2376 int srcreg1, srcreg2, dstreg;
2377
2378 PC = cia;
9c55817e
JL		 2379 srcreg1 = translate_rreg (SD_, RM2);
2380 srcreg2 = translate_rreg (SD_, RN0);
2381 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2382
2383 source1 = State.regs[srcreg1];
2384 source2 = State.regs[srcreg2];
2385 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2386 State.regs[dstreg] = sum;
2387
2388 z = (sum == 0);
2389 n = (sum & 0x80000000);
2390 c = (sum < source1) || (sum < source2);
2391 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2392 && (source1 & 0x80000000) != (sum & 0x80000000));
2393
2394 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2395 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2396 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2397}
2398
2399// 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
24008.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2401"sub"
2402*am33
2403{
2404 int z, c, n, v;
2405 unsigned long difference, source1, source2;
2406 int srcreg1, srcreg2, dstreg;
2407
2408 PC = cia;
9c55817e
JL		 2409 srcreg1 = translate_rreg (SD_, RM2);
2410 srcreg2 = translate_rreg (SD_, RN0);
2411 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2412
2413 source1 = State.regs[srcreg1];
2414 source2 = State.regs[srcreg2];
2415 difference = source2 - source1;
2416 State.regs[dstreg] = difference;
2417
2418 z = (difference == 0);
2419 n = (difference & 0x80000000);
2420 c = (source1 > source1);
2421 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2422 && (source1 & 0x80000000) != (difference & 0x80000000));
2423
2424 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2425 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2426 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2427}
2428
2429// 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
24308.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2431"subc"
2432*am33
2433{
2434 int z, c, n, v;
2435 unsigned long difference, source1, source2;
2436 int srcreg1, srcreg2, dstreg;
2437
2438 PC = cia;
9c55817e
JL		 2439 srcreg1 = translate_rreg (SD_, RM2);
2440 srcreg2 = translate_rreg (SD_, RN0);
2441 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2442
2443 source1 = State.regs[srcreg1];
2444 source2 = State.regs[srcreg2];
2445 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2446 State.regs[dstreg] = difference;
2447
2448 z = (difference == 0);
2449 n = (difference & 0x80000000);
2450 c = (source1 > source2);
2451 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2452 && (source1 & 0x80000000) != (difference & 0x80000000));
2453
2454 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2455 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2456 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2457}
2458
2459// 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
24608.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2461"and"
2462*am33
2463{
2464 int z, c, n, v;
2465 int srcreg1, srcreg2, dstreg;
2466
2467 PC = cia;
9c55817e
JL		 2468 srcreg1 = translate_rreg (SD_, RM2);
2469 srcreg2 = translate_rreg (SD_, RN0);
2470 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2471
2472 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2473
2474 z = (State.regs[dstreg] == 0);
2475 n = (State.regs[dstreg] & 0x80000000);
2476
2477 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2478 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2479}
2480
2481// 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
24828.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2483"or"
2484*am33
2485{
2486 int z, c, n, v;
0f7d7385
JL		 2487 int srcreg1, srcreg2, dstreg;
2488
2489 PC = cia;
9c55817e
JL		 2490 srcreg1 = translate_rreg (SD_, RM2);
2491 srcreg2 = translate_rreg (SD_, RN0);
2492 dstreg = translate_rreg (SD_, RD0);
0f7d7385 2493
377e53bb 2494 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
ee61616c 2495
377e53bb
JL		 2496 z = (State.regs[dstreg] == 0);
2497 n = (State.regs[dstreg] & 0x80000000);
ee61616c
JL		 2498
2499 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
377e53bb 2500 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
0f7d7385
JL		 2501}
2502
377e53bb
JL		 2503// 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
25048.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2505"xor"
0f7d7385
JL		 2506*am33
2507{
3e75ff7e 2508 int z, c, n, v;
3e75ff7e 2509 int srcreg1, srcreg2, dstreg;
0f7d7385
JL		 2510
2511 PC = cia;
9c55817e
JL		 2512 srcreg1 = translate_rreg (SD_, RM2);
2513 srcreg2 = translate_rreg (SD_, RN0);
2514 dstreg = translate_rreg (SD_, RD0);
3e75ff7e 2515
377e53bb 2516 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
3e75ff7e 2517
377e53bb
JL		 2518 z = (State.regs[dstreg] == 0);
2519 n = (State.regs[dstreg] & 0x80000000);
0f7d7385 2520
3e75ff7e 2521 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
377e53bb 2522 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
0f7d7385
JL		 2523}
2524
377e53bb
JL		 2525// 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
25268.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2527"asr"
0f7d7385
JL		 2528*am33
2529{
3e75ff7e 2530 int z, c, n, v;
377e53bb 2531 long temp;
3e75ff7e 2532 int srcreg1, srcreg2, dstreg;
0f7d7385
JL		 2533
2534 PC = cia;
9c55817e
JL		 2535 srcreg1 = translate_rreg (SD_, RM2);
2536 srcreg2 = translate_rreg (SD_, RN0);
2537 dstreg = translate_rreg (SD_, RD0);
3e75ff7e 2538
377e53bb
JL		 2539 temp = State.regs[srcreg2];
2540 c = temp & 1;
2541 temp >>= State.regs[srcreg1];
2542 State.regs[dstreg] = temp;
3e75ff7e 2543
377e53bb
JL		 2544 z = (State.regs[dstreg] == 0);
2545 n = (State.regs[dstreg] & 0x80000000);
3e75ff7e 2546
377e53bb
JL		 2547 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2548 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
0f7d7385
JL		 2549}
2550
377e53bb
JL		 2551// 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
25528.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2553"lsr"
2554*am33
2555{
2556 int z, c, n, v;
2557 int srcreg1, srcreg2, dstreg;
2558
2559 PC = cia;
9c55817e
JL		 2560 srcreg1 = translate_rreg (SD_, RM2);
2561 srcreg2 = translate_rreg (SD_, RN0);
2562 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2563
2564 c = State.regs[srcreg2] & 1;
2565 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2566
2567 z = (State.regs[dstreg] == 0);
2568 n = (State.regs[dstreg] & 0x80000000);
2569
2570 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2571 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2572}
2573
2574// 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
25758.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2576"asl"
2577*am33
2578{
2579 int z, c, n, v;
2580 int srcreg1, srcreg2, dstreg;
2581
2582 PC = cia;
9c55817e
JL		 2583 srcreg1 = translate_rreg (SD_, RM2);
2584 srcreg2 = translate_rreg (SD_, RN0);
2585 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2586
2587 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
2588
2589 z = (State.regs[dstreg] == 0);
2590 n = (State.regs[dstreg] & 0x80000000);
2591
2592 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2593 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2594}
2595
2596// 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
25978.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mul
2598"mul"
2599*am33
2600{
2601 int srcreg1, srcreg2, dstreg1, dstreg2;
2602 signed long long temp;
2603
2604 PC = cia;
9c55817e
JL		 2605 srcreg1 = translate_rreg (SD_, RM2);
2606 srcreg2 = translate_rreg (SD_, RN0);
2607 dstreg1 = translate_rreg (SD_, RD0);
2608 dstreg2 = translate_rreg (SD_, RD2);
377e53bb
JL		 2609
2610 temp = ((signed64)(signed32)State.regs[srcreg1]
2611 * (signed64)(signed32)State.regs[srcreg2]);
2612 State.regs[dstreg1] = temp & 0xffffffff;
2613 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2614}
2615
2616// 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
26178.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mulu
2618"mulu"
2619*am33
2620{
2621 int srcreg1, srcreg2, dstreg1, dstreg2;
2622 signed long long temp;
2623
2624 PC = cia;
9c55817e
JL		 2625 srcreg1 = translate_rreg (SD_, RM2);
2626 srcreg2 = translate_rreg (SD_, RN0);
2627 dstreg1 = translate_rreg (SD_, RD0);
2628 dstreg2 = translate_rreg (SD_, RD2);
377e53bb
JL		 2629
2630 temp = ((unsigned64)(unsigned32)State.regs[srcreg1]
2631 * (unsigned64)(unsigned32)State.regs[srcreg2]);
2632 State.regs[dstreg1] = temp & 0xffffffff;
2633 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2634}
2635
2636// 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
26378.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2638"mov"
2639*am33
2640{
2641 int dstreg;
2642
2643 PC = cia;
9c55817e 2644 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2645 State.regs[dstreg] = load_word (IMM8);
2646}
2647
2648// 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
26498.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2650"mov"
2651*am33
2652{
2653 int srcreg;
2654
9c55817e
JL		 2655 PC = cia;
2656 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2657 store_word (IMM8, State.regs[srcreg]);
2658}
2659
2660// 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
26618.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2662"movbu"
2663*am33
2664{
2665 int dstreg;
2666
2667 PC = cia;
9c55817e 2668 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2669 State.regs[dstreg] = load_byte (IMM8);
2670}
2671
2672// 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
26738.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2674"movbu"
0f7d7385
JL		 2675*am33
2676{
377e53bb 2677 int srcreg;
0f7d7385
JL		 2678
2679 PC = cia;
9c55817e 2680 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2681 store_byte (IMM8, State.regs[srcreg]);
2682}
0f7d7385 2683
377e53bb
JL		 2684// 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
26858.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2686"movhu"
2687*am33
2688{
2689 int dstreg;
2690
2691 PC = cia;
9c55817e 2692 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2693 State.regs[dstreg] = load_half (IMM8);
2694}
3e75ff7e 2695
377e53bb
JL		 2696// 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
26978.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2698"movhu"
2699*am33
2700{
2701 int srcreg;
3e75ff7e 2702
377e53bb 2703 PC = cia;
9c55817e 2704 srcreg = translate_rreg (SD_, RM2);
377e53bb 2705 store_half (IMM8, State.regs[srcreg]);
0f7d7385
JL		 2706}
2707
377e53bb
JL		 2708// 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
27098.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2710"mov"
0f7d7385
JL		 2711*am33
2712{
3e75ff7e 2713 int srcreg1, srcreg2, dstreg;
0f7d7385
JL		 2714
2715 PC = cia;
9c55817e
JL		 2716 srcreg1 = translate_rreg (SD_, RM0);
2717 srcreg1 = translate_rreg (SD_, RI0);
2718 dstreg = translate_rreg (SD_, RN0);
377e53bb 2719 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
3e75ff7e
JL		 2720}
2721
377e53bb
JL		 2722// 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
27238.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2724"mov"
3e75ff7e
JL		 2725*am33
2726{
377e53bb 2727 int srcreg, dstreg1, dstreg2;
3e75ff7e
JL		 2728
2729 PC = cia;
9c55817e
JL		 2730 srcreg = translate_rreg (SD_, RM0);
2731 dstreg1 = translate_rreg (SD_, RI0);
2732 dstreg2 = translate_rreg (SD_, RN0);
377e53bb 2733 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
3e75ff7e
JL		 2734}
2735
377e53bb
JL		 2736// 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
27378.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2738"movbu"
3e75ff7e
JL		 2739*am33
2740{
3e75ff7e
JL		 2741 int srcreg1, srcreg2, dstreg;
2742
2743 PC = cia;
9c55817e
JL		 2744 srcreg1 = translate_rreg (SD_, RM0);
2745 srcreg1 = translate_rreg (SD_, RI0);
2746 dstreg = translate_rreg (SD_, RN0);
377e53bb 2747 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
3e75ff7e
JL		 2748}
2749
377e53bb
JL		 2750// 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
27518.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2752"movbu"
3e75ff7e
JL		 2753*am33
2754{
377e53bb 2755 int srcreg, dstreg1, dstreg2;
3e75ff7e
JL		 2756
2757 PC = cia;
9c55817e
JL		 2758 srcreg = translate_rreg (SD_, RM0);
2759 dstreg1 = translate_rreg (SD_, RI0);
2760 dstreg2 = translate_rreg (SD_, RN0);
377e53bb 2761 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
3e75ff7e
JL		 2762}
2763
377e53bb
JL		 2764// 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
27658.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2766"movhu"
3e75ff7e
JL		 2767*am33
2768{
3e75ff7e
JL		 2769 int srcreg1, srcreg2, dstreg;
2770
9c55817e
JL		 2771 PC = cia;
2772 srcreg1 = translate_rreg (SD_, RM0);
2773 srcreg1 = translate_rreg (SD_, RI0);
2774 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 2775 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2776}
2777
2778// 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
27798.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2780"movhu"
2781*am33
2782{
2783 int srcreg, dstreg1, dstreg2;
2784
2785 PC = cia;
9c55817e
JL		 2786 srcreg = translate_rreg (SD_, RM0);
2787 dstreg1 = translate_rreg (SD_, RI0);
2788 dstreg2 = translate_rreg (SD_, RN0);
377e53bb 2789 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
3e75ff7e
JL		 2790}
2791
1f0ba346
JL		 2792// 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
27938.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mac
2794"mac"
2795*am33
2796{
2797 int srcreg1, srcreg2, dstreg1, dstreg2;
2798 signed long long temp;
2799 unsigned long sum;
2800 int c, v;
2801
2802 PC = cia;
2803 srcreg1 = translate_rreg (SD_, RM2);
2804 srcreg2 = translate_rreg (SD_, RN0);
2805 dstreg1 = translate_rreg (SD_, RD0);
2806 dstreg2 = translate_rreg (SD_, RD2);
2807
2808 temp = ((signed64)(signed32)State.regs[srcreg1]
2809 * (signed64)(signed32)State.regs[srcreg2]);
2810
2811 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2812 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2813 State.regs[dstreg2] = sum;
2814 temp >>= 32;
2815 temp &= 0xffffffff;
2816 sum = State.regs[dstreg1] + temp + c;
2817 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2818 && (temp & 0x80000000) != (sum & 0x80000000));
2819 State.regs[dstreg1] = sum;
2820 if (v)
2821 State.regs[REG_MCVF] = 1;
2822}
2823
2824// 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
28258.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::macu
2826"macu"
2827*am33
2828{
2829 int srcreg1, srcreg2, dstreg1, dstreg2;
2830 signed long long temp;
2831 unsigned long sum;
2832 int c, v;
2833
2834 PC = cia;
2835 srcreg1 = translate_rreg (SD_, RM2);
2836 srcreg2 = translate_rreg (SD_, RN0);
2837 dstreg1 = translate_rreg (SD_, RD0);
2838 dstreg2 = translate_rreg (SD_, RD2);
2839
2840 temp = ((unsigned64)State.regs[srcreg1]
2841 * (unsigned64)State.regs[srcreg2]);
2842
2843 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2844 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2845 State.regs[dstreg2] = sum;
2846 temp >>= 32;
2847 temp &= 0xffffffff;
2848 sum = State.regs[dstreg1] + temp + c;
2849 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2850 && (temp & 0x80000000) != (sum & 0x80000000));
2851 State.regs[dstreg1] = sum;
2852 if (v)
2853 State.regs[REG_MCVF] = 1;
2854}
2855
2856// 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
28578.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2858"macb"
2859*am33
2860{
2861 int srcreg1, srcreg2, dstreg;
2862 long temp, sum;
2863 int v;
2864
2865 PC = cia;
2866 srcreg1 = translate_rreg (SD_, RM2);
2867 srcreg2 = translate_rreg (SD_, RN0);
2868 dstreg = translate_rreg (SD_, RD0);
2869
2870 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2871 * (signed32)(State.regs[srcreg1] & 0xff));
2872 sum = State.regs[dstreg] + temp;
2873 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2874 && (temp & 0x80000000) != (sum & 0x80000000));
2875 State.regs[dstreg] = sum;
2876 if (v)
2877 State.regs[REG_MCVF] = 1;
2878}
2879
2880// 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
28818.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2882"macbu"
2883*am33
2884{
2885 int srcreg1, srcreg2, dstreg;
2886 long temp, sum;
2887 int v;
2888
2889 PC = cia;
2890 srcreg1 = translate_rreg (SD_, RM2);
2891 srcreg2 = translate_rreg (SD_, RN0);
2892 dstreg = translate_rreg (SD_, RD0);
2893
2894 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2895 * (unsigned32)(State.regs[srcreg1] & 0xff));
2896 sum = State.regs[dstreg] + temp;
2897 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2898 && (temp & 0x80000000) != (sum & 0x80000000));
2899 State.regs[dstreg] = sum;
2900 if (v)
2901 State.regs[REG_MCVF] = 1;
2902}
2903
2904// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1
29058.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::mach
2906"mach"
2907*am33
2908{
2909 int srcreg1, srcreg2, dstreg;
2910 long temp, sum;
2911 int v;
2912
2913 PC = cia;
2914 srcreg1 = translate_rreg (SD_, RM2);
2915 srcreg2 = translate_rreg (SD_, RN0);
2916 dstreg = translate_rreg (SD_, RD0);
2917
2918 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2919 * (signed32)(State.regs[srcreg1] & 0xffff));
2920 sum = State.regs[dstreg] + temp;
2921 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2922 && (temp & 0x80000000) != (sum & 0x80000000));
2923 State.regs[dstreg] = sum;
2924 if (v)
2925 State.regs[REG_MCVF] = 1;
2926}
2927
2928// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1
29298.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::machu
2930"machu"
2931*am33
2932{
2933 int srcreg1, srcreg2, dstreg;
2934 long temp, sum;
2935 int v;
2936
2937 PC = cia;
2938 srcreg1 = translate_rreg (SD_, RM2);
2939 srcreg2 = translate_rreg (SD_, RN0);
2940 dstreg = translate_rreg (SD_, RD0);
2941
2942 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2943 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2944 sum = State.regs[dstreg] + temp;
2945 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2946 && (temp & 0x80000000) != (sum & 0x80000000));
2947 State.regs[dstreg] = sum;
2948 if (v)
2949 State.regs[REG_MCVF] = 1;
2950}
2951
2952// 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
29538.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
2954"dmach"
2955*am33
2956{
2957 int srcreg1, srcreg2, dstreg;
2958 long temp, temp2, sum;
2959 int v;
2960
2961 PC = cia;
2962 srcreg1 = translate_rreg (SD_, RM2);
2963 srcreg2 = translate_rreg (SD_, RN0);
2964 dstreg = translate_rreg (SD_, RD0);
2965
2966 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2967 * (signed32)(State.regs[srcreg1] & 0xffff));
2968 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
2969 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
2970 sum = temp + temp2 + State.regs[dstreg];
2971 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2972 && (temp & 0x80000000) != (sum & 0x80000000));
2973 State.regs[dstreg] = sum;
2974 if (v)
2975 State.regs[REG_MCVF] = 1;
2976}
2977
2978// 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
29798.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
2980"dmachu"
2981*am33
2982{
2983 int srcreg1, srcreg2, dstreg;
2984 long temp, temp2, sum;
2985 int v;
2986
2987 PC = cia;
2988 srcreg1 = translate_rreg (SD_, RM2);
2989 srcreg2 = translate_rreg (SD_, RN0);
2990 dstreg = translate_rreg (SD_, RD0);
2991
2992 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2993 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2994 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
2995 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
2996 sum = temp + temp2 + State.regs[dstreg];
2997 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2998 && (temp & 0x80000000) != (sum & 0x80000000));
2999 State.regs[dstreg] = sum;
3000 if (v)
3001 State.regs[REG_MCVF] = 1;
3002}
3003
3004// 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
30058.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulh
3006"dmulh"
3007*am33
3008{
3009 int srcreg1, srcreg2, dstreg1, dstreg2;
3010 signed long long temp;
3011
3012 PC = cia;
3013 srcreg1 = translate_rreg (SD_, RM2);
3014 srcreg2 = translate_rreg (SD_, RN0);
3015 dstreg1 = translate_rreg (SD_, RD0);
3016 dstreg2 = translate_rreg (SD_, RD2);
3017
3018 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3019 * (signed32)(State.regs[srcreg1] & 0xffff));
3020 State.regs[dstreg2] = temp;
3021 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3022 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3023 State.regs[dstreg1] = temp;
3024}
3025
3026// 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
30278.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulhu
3028"dmulhu"
3029*am33
3030{
3031 int srcreg1, srcreg2, dstreg1, dstreg2;
3032 signed long long temp;
3033
3034 PC = cia;
3035 srcreg1 = translate_rreg (SD_, RM2);
3036 srcreg2 = translate_rreg (SD_, RN0);
3037 dstreg1 = translate_rreg (SD_, RD0);
3038 dstreg2 = translate_rreg (SD_, RD2);
3039
3040 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3041 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3042 State.regs[dstreg2] = temp;
3043 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3044 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3045 State.regs[dstreg1] = temp;
3046}
377e53bb
JL		 3047
3048// 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
30498.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3050"sat24"
3e75ff7e
JL		 3051*am33
3052{
377e53bb
JL		 3053 int srcreg, dstreg;
3054 int value;
3e75ff7e
JL		 3055
3056 PC = cia;
9c55817e
JL		 3057 srcreg = translate_rreg (SD_, RM2);
3058 dstreg = translate_rreg (SD_, RN0);
3e75ff7e 3059
377e53bb 3060 value = State.regs[srcreg];
3e75ff7e 3061
377e53bb
JL		 3062 if (value >= 0x7fffff)
3063 State.regs[dstreg] = 0x7fffff;
3064 else if (value <= 0xff800000)
3065 State.regs[dstreg] = 0xff800000;
3066 else
3067 State.regs[dstreg] = value;
3e75ff7e
JL		 3068}
3069
1f0ba346
JL		 3070// 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
30718.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3072"bsch"
3073*am33
3074{
3075 int temp, c, i;
3076 int srcreg1, srcreg2, dstreg;
3077 int start;
3078
3079 PC = cia;
3080 srcreg1 = translate_rreg (SD_, RM2);
3081 srcreg2 = translate_rreg (SD_, RN0);
3082 dstreg = translate_rreg (SD_, RD0);
3083
3084 temp = State.regs[srcreg1];
3085 start = (State.regs[srcreg2] & 0x1f) - 1;
3086 if (start == -1)
3087 start = 31;
3088
3089 for (i = start; i >= 0; i--)
3090 {
3091 if (temp & (1 << i))
3092 {
3093 c = 1;
3094 State.regs[dstreg] = i;
3095 break;
3096 }
3097 }
3098
3099 if (i < 0)
3100 {
3101 c = 0;
3102 State.regs[dstreg] = 0;
3103 }
3104 PSW &= ~(PSW_C);
3105 PSW |= (c ? PSW_C : 0);
3106}
3e75ff7e
JL		 3107
3108// 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
31098.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3110"mov"
3111*am33
3112{
3113 int dstreg;
3114
3115 PC = cia;
9c55817e 3116 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3117 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3118}
3119
3120// 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
31218.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3122"movu"
3123*am33
3124{
3125 int dstreg;
3126
3127 PC = cia;
9c55817e 3128 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3129 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3130}
3131
3132// 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
31338.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3134"add"
3135*am33
3136{
3137 int dstreg;
3138
3139 PC = cia;
9c55817e 3140 dstreg = translate_rreg (SD_, RN0);
4e86afb8 3141 genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3e75ff7e
JL		 3142}
3143
3144// 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
31458.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3146"addc"
3147*am33
3148{
3149 int dstreg, z, n, c, v;
3150 unsigned long sum, imm, reg2;
3151
3152 PC = cia;
9c55817e 3153 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3154
3155 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3156 reg2 = State.regs[dstreg];
3157 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3158 State.regs[dstreg] = sum;
3159
3160 z = (sum == 0);
3161 n = (sum & 0x80000000);
3162 c = (sum < imm) || (sum < reg2);
3163 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3164 && (reg2 & 0x80000000) != (sum & 0x80000000));
3165
3166 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3167 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3168 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3169}
3170
3171// 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
31728.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3173"sub"
3174*am33
3175{
3176 int dstreg;
3177
3178 PC = cia;
9c55817e 3179 dstreg = translate_rreg (SD_, RN0);
4e86afb8 3180 genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3e75ff7e
JL		 3181}
3182
3183// 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
31848.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3185"subc"
3186*am33
3187{
3188 int dstreg, z, n, c, v;
3189 unsigned long difference, imm, reg2;
3190
3191 PC = cia;
9c55817e 3192 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3193
3194 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3195 reg2 = State.regs[dstreg];
3196 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3197 State.regs[dstreg] = difference;
3198
3199 z = (difference == 0);
3200 n = (difference & 0x80000000);
3201 c = (imm > reg2);
3202 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3203 && (reg2 & 0x80000000) != (difference & 0x80000000));
3204
3205 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3206 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3207 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3208}
3209
3210// 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
32118.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3212"cmp"
3213*am33
3214{
3215 int srcreg;
3216
3217 PC = cia;
9c55817e 3218 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3219 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3220}
3221
3222// 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
32238.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3224"mov"
3225*am33
3226{
3e75ff7e
JL		 3227 PC = cia;
3228
3229 if (XRN0 == 0)
3230 {
3231 State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3232 }
3233 else
3234 abort ();
3235}
3236
3237// 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
32388.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3239"and"
3240*am33
3241{
3242 int dstreg;
3243 int z,n;
3244
3245 PC = cia;
9c55817e 3246 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3247
3248 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3249 z = (State.regs[dstreg] == 0);
3250 n = (State.regs[dstreg] & 0x80000000) != 0;
3251 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3252 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3253}
3254
3255// 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
32568.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3257"or"
3258*am33
3259{
3260 int dstreg;
3261 int z,n;
3262
3263 PC = cia;
9c55817e 3264 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3265
3266 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3267 z = (State.regs[dstreg] == 0);
3268 n = (State.regs[dstreg] & 0x80000000) != 0;
3269 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3270 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3271}
3272
3273// 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
32748.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3275"xor"
3276*am33
3277{
3278 int dstreg;
3279 int z,n;
3280
3281 PC = cia;
9c55817e 3282 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3283
3284 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3285 z = (State.regs[dstreg] == 0);
3286 n = (State.regs[dstreg] & 0x80000000) != 0;
3287 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3288 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3289}
3290
3291// 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
32928.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3293"asr"
3294*am33
3295{
3296 int dstreg;
3297 long temp;
3298 int c, z, n;
3299
3300 PC = cia;
9c55817e 3301 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3302
3303 temp = State.regs[dstreg];
3304 c = temp & 1;
3305 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3306 State.regs[dstreg] = temp;
3307 z = (State.regs[dstreg] == 0);
3308 n = (State.regs[dstreg] & 0x80000000) != 0;
3309 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3310 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3311}
3312
3313
3314// 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
33158.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3316"lsr"
3317*am33
3318{
3319 int dstreg;
3320 int z, n, c;
3321
3322 PC = cia;
9c55817e 3323 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3324
3325 c = State.regs[dstreg] & 1;
3326 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3327 z = (State.regs[dstreg] == 0);
3328 n = (State.regs[dstreg] & 0x80000000) != 0;
3329 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3330 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3331}
3332
3333// 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
33348.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3335"asl"
3336*am33
3337{
3338 int srcreg, dstreg;
3339 int z, n;
3340
3341 PC = cia;
9c55817e 3342 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3343
3344 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3345 z = (State.regs[dstreg] == 0);
3346 n = (State.regs[dstreg] & 0x80000000) != 0;
3347 PSW &= ~(PSW_Z | PSW_N);
3348 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3349}
3350
1f0ba346
JL		 3351// 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
33528.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3353"mul"
3354*am33
3355{
3356 int dstreg;
3357 unsigned long long temp;
3358 int z, n;
3359
3360 PC = cia;
3361 dstreg = translate_rreg (SD_, RN0);
3362
3363 temp = ((signed64)(signed32)State.regs[dstreg]
3364 * (signed64)(signed32)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3365 State.regs[dstreg] = temp & 0xffffffff;
3366 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3367 z = (State.regs[dstreg] == 0);
3368 n = (State.regs[dstreg] & 0x80000000) != 0;
3369 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3370 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3371}
3372
3373// 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
33748.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3375"mulu"
3376*am33
3377{
3378 int dstreg;
3379 unsigned long long temp;
3380 int z, n;
3381
3382 PC = cia;
3383 dstreg = translate_rreg (SD_, RN0);
3384
3385 temp = ((unsigned64)State.regs[dstreg]
3386 * (unsigned64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3387 State.regs[dstreg] = temp & 0xffffffff;
3388 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3389 z = (State.regs[dstreg] == 0);
3390 n = (State.regs[dstreg] & 0x80000000) != 0;
3391 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3392 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3393}
3e75ff7e
JL		 3394
3395// 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
33968.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3397"btst"
3398*am33
3399{
3400 int srcreg;
3401
3402 PC = cia;
9c55817e 3403 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3404 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3405}
3406
3407// 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
34088.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3409"mov"
3410*am33
3411{
3412 int srcreg, dstreg;
3413
3414 PC = cia;
9c55817e
JL		 3415 srcreg = translate_rreg (SD_, RM0);
3416 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3417 State.regs[dstreg] = load_word (State.regs[srcreg]
3418 + FETCH24 (IMM24A, IMM24B, IMM24C));
3419}
3420
3421// 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
34228.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3423"mov"
3424*am33
3425{
3426 int srcreg, dstreg;
3427
3428 PC = cia;
9c55817e
JL		 3429 srcreg = translate_rreg (SD_, RM2);
3430 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3431 store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3432 State.regs[srcreg]);
3433}
3434
3435// 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
34368.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3437"movbu"
3438*am33
3439{
3440 int srcreg, dstreg;
3441
3442 PC = cia;
9c55817e
JL		 3443 srcreg = translate_rreg (SD_, RM0);
3444 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3445 State.regs[dstreg] = load_byte (State.regs[srcreg]
3446 + FETCH24 (IMM24A, IMM24B, IMM24C));
3447}
3448
3449// 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
34508.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3451"movbu"
3452*am33
3453{
3454 int srcreg, dstreg;
3455
3456 PC = cia;
9c55817e
JL		 3457 srcreg = translate_rreg (SD_, RM2);
3458 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3459 store_byte (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3460 State.regs[srcreg]);
3461}
3462
3463// 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
34648.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3465"movhu"
3466*am33
3467{
3468 int srcreg, dstreg;
3469
3470 PC = cia;
9c55817e
JL		 3471 srcreg = translate_rreg (SD_, RM0);
3472 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3473 State.regs[dstreg] = load_half (State.regs[srcreg]
3474 + FETCH24 (IMM24A, IMM24B, IMM24C));
3475}
3476
3477// 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
34788.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3479"movhu"
3480*am33
3481{
3482 int srcreg, dstreg;
3483
3484 PC = cia;
9c55817e
JL		 3485 srcreg = translate_rreg (SD_, RM2);
3486 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3487 store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3488 State.regs[srcreg]);
3489}
3490
377e53bb
JL		 3491// 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
34928.0xfd+8.0x6a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3493"mov"
3494*am33
3495{
3496 int srcreg, dstreg;
3497
3498 PC = cia;
9c55817e
JL		 3499 srcreg = translate_rreg (SD_, RM0);
3500 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 3501 State.regs[dstreg] = load_word (State.regs[srcreg]
3502 + FETCH24 (IMM24A, IMM24B, IMM24C));
3503 State.regs[srcreg] += 4;
3504}
3505
3506// 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
35078.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3508"mov"
3509*am33
3510{
3511 int srcreg, dstreg;
3512
3513 PC = cia;
9c55817e
JL		 3514 srcreg = translate_rreg (SD_, RM2);
3515 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 3516 store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3517 State.regs[srcreg]);
3518 State.regs[dstreg] += 4;
3519}
3520
3e75ff7e
JL		 3521
3522// 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
35238.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3524"mov"
3525*am33
3526{
3527 int dstreg;
3528
3529 PC = cia;
9c55817e 3530 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3531 State.regs[dstreg] = load_word (State.regs[REG_SP]
3532 + FETCH24 (IMM24A, IMM24B, IMM24C));
3533}
3534
3535// 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
35368.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3537"mov"
3538*am33
3539{
3540 int srcreg;
3541
3542 PC = cia;
9c55817e 3543 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 3544 store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3545 State.regs[srcreg]);
3546}
3547
3548// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
35498.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3550"movbu"
3551*am33
3552{
3553 int dstreg;
3554
3555 PC = cia;
9c55817e 3556 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3557 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3558 + FETCH24 (IMM24A, IMM24B, IMM24C));
3559}
3560
3561// 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
35628.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3563"movbu"
3564*am33
3565{
3566 int srcreg;
3567
3568 PC = cia;
9c55817e 3569 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 3570 store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3571 State.regs[srcreg]);
3572}
3573
3574// 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
35758.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3576"movhu"
3577*am33
3578{
3579 int dstreg;
3580
3581 PC = cia;
9c55817e 3582 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3583 State.regs[dstreg] = load_half (State.regs[REG_SP]
3584 + FETCH24 (IMM24A, IMM24B, IMM24C));
3585}
3586
3587// 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
35888.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3589"movhu"
3590*am33
3591{
3592 int srcreg;
3593
3594 PC = cia;
9c55817e 3595 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 3596 store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3597 State.regs[srcreg]);
3598}
3599
377e53bb
JL		 3600// 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
36018.0xfd+8.0xea+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3602"movhu"
3603*am33
3604{
3605 int srcreg, dstreg;
3606
3607 PC = cia;
9c55817e
JL		 3608 srcreg = translate_rreg (SD_, RM0);
3609 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 3610 State.regs[dstreg] = load_half (State.regs[srcreg]
3611 + FETCH24 (IMM24A, IMM24B, IMM24C));
3612 State.regs[dstreg] += 2;
3613}
3614
3615// 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
36168.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3617"movhu"
3618*am33
3619{
3620 int srcreg, dstreg;
3621
3622 PC = cia;
9c55817e
JL		 3623 srcreg = translate_rreg (SD_, RM2);
3624 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 3625 store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3626 State.regs[srcreg]);
3627 State.regs[srcreg] += 2;
3628}
3629
1f0ba346
JL		 3630// 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
36318.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3632"mac"
3633*am33
3634{
3635 int srcreg;
3636 long long temp, sum;
3637 int c, v;
3638
3639 PC = cia;
3640 srcreg = translate_rreg (SD_, RN2);
3641
3642 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3643 * (signed64)State.regs[srcreg]);
3644 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3645 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3646 State.regs[REG_MCRL] = sum;
3647 temp >>= 32;
3648 temp &= 0xffffffff;
3649 sum = State.regs[REG_MCRH] + temp + c;
3650 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3651 && (temp & 0x80000000) != (sum & 0x80000000));
3652 State.regs[REG_MCRH] = sum;
3653 if (v)
3654 State.regs[REG_MCVF] = 1;
3655}
3656
3657// 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
36588.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3659"macu"
3660*am33
3661{
3662 int srcreg;
3663 long long temp, sum;
3664 int c, v;
3665
3666 PC = cia;
3667 srcreg = translate_rreg (SD_, RN2);
3668
3669 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3670 * (unsigned64)State.regs[srcreg]);
3671 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3672 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3673 State.regs[REG_MCRL] = sum;
3674 temp >>= 32;
3675 temp &= 0xffffffff;
3676 sum = State.regs[REG_MCRH] + temp + c;
3677 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3678 && (temp & 0x80000000) != (sum & 0x80000000));
3679 State.regs[REG_MCRH] = sum;
3680 if (v)
3681 State.regs[REG_MCVF] = 1;
3682}
3683
3684// 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
36858.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3686"macb"
3687*am33
3688{
3689 int srcreg;
3690 long long temp, sum;
3691 int c, v;
3692
3693 PC = cia;
3694 srcreg = translate_rreg (SD_, RN2);
3695
3696 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3697 * (signed64)State.regs[srcreg] & 0xff);
3698 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3699 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3700 State.regs[REG_MCRL] = sum;
3701 temp >>= 32;
3702 temp &= 0xffffffff;
3703 sum = State.regs[REG_MCRH] + temp + c;
3704 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3705 && (temp & 0x80000000) != (sum & 0x80000000));
3706 State.regs[REG_MCRH] = sum;
3707 if (v)
3708 State.regs[REG_MCVF] = 1;
3709}
3710
3711// 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
37128.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3713"macbu"
3714*am33
3715{
3716 int srcreg;
3717 long long temp, sum;
3718 int c, v;
3719
3720 PC = cia;
3721 srcreg = translate_rreg (SD_, RN2);
3722
3723 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3724 * (unsigned64)State.regs[srcreg] & 0xff);
3725 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3726 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3727 State.regs[REG_MCRL] = sum;
3728 temp >>= 32;
3729 temp &= 0xffffffff;
3730 sum = State.regs[REG_MCRH] + temp + c;
3731 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3732 && (temp & 0x80000000) != (sum & 0x80000000));
3733 State.regs[REG_MCRH] = sum;
3734 if (v)
3735 State.regs[REG_MCVF] = 1;
3736}
3737
3738// 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
37398.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3740"mach"
3741*am33
3742{
3743 int srcreg;
3744 long long temp, sum;
3745 int c, v;
3746
3747 PC = cia;
3748 srcreg = translate_rreg (SD_, RN2);
3749
3750 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3751 * (signed64)State.regs[srcreg] & 0xffff);
3752 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3753 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3754 State.regs[REG_MCRL] = sum;
3755 temp >>= 32;
3756 temp &= 0xffffffff;
3757 sum = State.regs[REG_MCRH] + temp + c;
3758 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3759 && (temp & 0x80000000) != (sum & 0x80000000));
3760 State.regs[REG_MCRH] = sum;
3761 if (v)
3762 State.regs[REG_MCVF] = 1;
3763}
3764
3765// 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
37668.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3767"machu"
3768*am33
3769{
3770 int srcreg;
3771 long long temp, sum;
3772 int c, v;
3773
3774 PC = cia;
3775 srcreg = translate_rreg (SD_, RN2);
3776
3777 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3778 * (unsigned64)State.regs[srcreg] & 0xffff);
3779 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3780 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3781 State.regs[REG_MCRL] = sum;
3782 temp >>= 32;
3783 temp &= 0xffffffff;
3784 sum = State.regs[REG_MCRH] + temp + c;
3785 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3786 && (temp & 0x80000000) != (sum & 0x80000000));
3787 State.regs[REG_MCRH] = sum;
3788 if (v)
3789 State.regs[REG_MCVF] = 1;
3790}
3e75ff7e
JL		 3791
3792// 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
37938.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3794"mov"
3795*am33
3796{
3797 int dstreg;
3798
3799 PC = cia;
9c55817e 3800 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3801 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3802}
3803
3804// 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
38058.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3806"mov"
3807*am33
3808{
3809 int srcreg;
3810
3811 PC = cia;
9c55817e 3812 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 3813 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3814}
3815
3816
3817// 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
38188.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3819"movbu"
3820*am33
3821{
3822 int dstreg;
3823
3824 PC = cia;
9c55817e 3825 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3826 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3827}
3828
3829// 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
38308.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3831"movbu"
3832*am33
3833{
3834 int srcreg;
3835
3836 PC = cia;
9c55817e 3837 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 3838 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3839}
3840
3841
3842// 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
38438.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3844"movhu"
3845*am33
3846{
3847 int dstreg;
3848
3849 PC = cia;
9c55817e 3850 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3851 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3852}
3853
3854// 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
38558.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3856"movhu"
3857*am33
3858{
3859 int srcreg;
3860
3861 PC = cia;
9c55817e 3862 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 3863 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3864}
3865
3866
3867// 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
38688.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3869"mov"
3870*am33
3871{
3872 int dstreg;
3873
3874 PC = cia;
9c55817e 3875 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3876 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3877}
3878
3879// 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
38808.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3881"movu"
3882*am33
3883{
3884 int dstreg;
3885
3886 PC = cia;
9c55817e 3887 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3888 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3889}
3890
3891// 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
38928.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3893"add"
3894*am33
3895{
3896 int dstreg;
3897
3898 PC = cia;
9c55817e 3899 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3900 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3901}
3902
3903// 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
39048.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3905"addc"
3906*am33
3907{
3908 int dstreg;
3909 unsigned int imm, reg2, sum;
3910 int z, n, c, v;
3911
3912 PC = cia;
9c55817e 3913 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3914
3915 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3916 reg2 = State.regs[dstreg];
3917 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3918 State.regs[dstreg] = sum;
3919
3920 z = (sum == 0);
3921 n = (sum & 0x80000000);
3922 c = (sum < imm) || (sum < reg2);
3923 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3924 && (reg2 & 0x80000000) != (sum & 0x80000000));
3925
3926 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3927 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3928 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3929}
3930
3931// 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
39328.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
3933"sub"
3934*am33
3935{
3936 int dstreg;
3937
3938 PC = cia;
9c55817e 3939 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3940 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3941}
3942
3943// 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
39448.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
3945"subc"
3946*am33
3947{
3948 int dstreg;
3949 unsigned int imm, reg2, difference;
3950 int z, n, c, v;
3951
3952 PC = cia;
9c55817e 3953 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3954
3955 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3956 reg2 = State.regs[dstreg];
3957 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3958 State.regs[dstreg] = difference;
3959
3960 z = (difference == 0);
3961 n = (difference & 0x80000000);
3962 c = (imm > reg2);
3963 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3964 && (reg2 & 0x80000000) != (difference & 0x80000000));
3965
3966 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3967 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3968 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3969}
3970
3971// 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
39728.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
3973"cmp"
3974*am33
3975{
3976 int srcreg;
3977
3978 PC = cia;
9c55817e 3979 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3980 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
3981}
3982
3983// 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
39848.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
3985"mov"
3986*am33
3987{
3e75ff7e
JL		 3988 PC = cia;
3989
3990 if (XRN0 == 0)
3991 State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3992 else
3993 abort ();
3994}
3995
3996// 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
39978.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
3998"and"
3999*am33
4000{
4001 int dstreg;
4002 int z,n;
4003
4004 PC = cia;
9c55817e 4005 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4006
4007 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4008 z = (State.regs[dstreg] == 0);
4009 n = (State.regs[dstreg] & 0x80000000) != 0;
4010 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4011 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4012}
4013
4014// 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
40158.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4016"or"
4017*am33
4018{
4019 int dstreg;
4020 int z,n;
4021
4022 PC = cia;
9c55817e 4023 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4024
4025 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4026 z = (State.regs[dstreg] == 0);
4027 n = (State.regs[dstreg] & 0x80000000) != 0;
4028 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4029 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4030}
4031
4032// 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
40338.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4034"xor"
4035*am33
4036{
4037 int dstreg;
4038 int z,n;
4039
4040 PC = cia;
9c55817e 4041 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4042
4043 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4044 z = (State.regs[dstreg] == 0);
4045 n = (State.regs[dstreg] & 0x80000000) != 0;
4046 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4047 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4048}
4049
4050// 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
40518.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4052"asr"
4053*am33
4054{
4055 int dstreg;
4056 long temp;
4057 int c, z, n;
4058
4059 PC = cia;
9c55817e 4060 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4061
4062 temp = State.regs[dstreg];
4063 c = temp & 1;
4064 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4065 State.regs[dstreg] = temp;
4066 z = (State.regs[dstreg] == 0);
4067 n = (State.regs[dstreg] & 0x80000000) != 0;
4068 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4069 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4070}
4071
4072// 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
40738.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4074"lsr"
4075*am33
4076{
4077 int dstreg;
4078 int z, n, c;
4079
4080 PC = cia;
9c55817e 4081 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4082
4083 c = State.regs[dstreg] & 1;
4084 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4085 z = (State.regs[dstreg] == 0);
4086 n = (State.regs[dstreg] & 0x80000000) != 0;
4087 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4088 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4089}
4090
4091// 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
40928.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4093"asl"
4094*am33
4095{
4096 int srcreg, dstreg;
4097 int z, n;
4098
4099 PC = cia;
9c55817e 4100 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4101
4102 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4103 z = (State.regs[dstreg] == 0);
4104 n = (State.regs[dstreg] & 0x80000000) != 0;
4105 PSW &= ~(PSW_Z | PSW_N);
4106 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4107}
4108
377e53bb
JL		 4109// ??? mul
4110// ??? mulu
3e75ff7e
JL		 4111
4112// 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
41138.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4114"btst"
4115*am33
4116{
4117 int srcreg;
4118
4119 PC = cia;
9c55817e 4120 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4121 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4122}
4123
4124// 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
41258.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4126"mov"
4127*am33
4128{
4129 int srcreg, dstreg;
4130
4131 PC = cia;
9c55817e
JL		 4132 srcreg = translate_rreg (SD_, RM0);
4133 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4134 State.regs[dstreg] = load_word (State.regs[srcreg]
4135 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4136}
4137
4138// 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
41398.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4140"mov"
4141*am33
4142{
4143 int srcreg, dstreg;
4144
4145 PC = cia;
9c55817e
JL		 4146 srcreg = translate_rreg (SD_, RM2);
4147 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4148 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4149 State.regs[srcreg]);
4150}
4151
4152// 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
41538.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4154"movbu"
4155*am33
4156{
4157 int srcreg, dstreg;
4158
4159 PC = cia;
9c55817e
JL		 4160 srcreg = translate_rreg (SD_, RM0);
4161 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4162 State.regs[dstreg] = load_byte (State.regs[srcreg]
4163 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4164}
4165
4166// 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
41678.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4168"movbu"
4169*am33
4170{
4171 int srcreg, dstreg;
4172
4173 PC = cia;
9c55817e
JL		 4174 srcreg = translate_rreg (SD_, RM2);
4175 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4176 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4177 State.regs[srcreg]);
0f7d7385
JL		 4178}
4179
3e75ff7e
JL		 4180// 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
41818.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4182"movhu"
0f7d7385
JL		 4183*am33
4184{
3e75ff7e
JL		 4185 int srcreg, dstreg;
4186
4187 PC = cia;
9c55817e
JL		 4188 srcreg = translate_rreg (SD_, RM0);
4189 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4190 State.regs[dstreg] = load_half (State.regs[srcreg]
4191 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4192}
4193
4194// 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
41958.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4196"movhu"
4197*am33
4198{
4199 int srcreg, dstreg;
0f7d7385
JL		 4200
4201 PC = cia;
9c55817e
JL		 4202 srcreg = translate_rreg (SD_, RM2);
4203 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4204 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4205 State.regs[srcreg]);
4206}
4207
377e53bb
JL		 4208// 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
42098.0xfe+8.0x6a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4210"mov"
4211*am33
4212{
4213 int srcreg, dstreg;
4214
4215 PC = cia;
9c55817e
JL		 4216 srcreg = translate_rreg (SD_, RM0);
4217 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 4218 State.regs[dstreg] = load_word (State.regs[srcreg]
4219 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4220 State.regs[srcreg] += 4;
4221}
4222
4223// 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
42248.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4225"mov"
4226*am33
4227{
4228 int srcreg, dstreg;
4229
4230 PC = cia;
9c55817e
JL		 4231 srcreg = translate_rreg (SD_, RM2);
4232 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 4233 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4234 State.regs[srcreg]);
4235 State.regs[dstreg] += 4;
4236}
4237
3e75ff7e
JL		 4238
4239// 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
42408.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4241"mov"
4242*am33
4243{
4244 int dstreg;
4245
4246 PC = cia;
9c55817e 4247 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4248 State.regs[dstreg] = load_word (State.regs[REG_SP]
4249 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4250}
4251
4252// 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
42538.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4254"mov"
4255*am33
4256{
4257 int srcreg;
4258
4259 PC = cia;
9c55817e 4260 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4261 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4262 State.regs[srcreg]);
4263}
4264
4265// 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
42668.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4267"movbu"
4268*am33
4269{
4270 int dstreg;
4271
4272 PC = cia;
9c55817e 4273 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4274 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4275 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4276}
4277
4278// 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
42798.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4280"movbu"
4281*am33
4282{
4283 int srcreg;
4284
4285 PC = cia;
9c55817e 4286 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4287 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4288 State.regs[srcreg]);
4289}
4290
4291// 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
42928.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4293"movhu"
4294*am33
4295{
4296 int dstreg;
4297
4298 PC = cia;
9c55817e 4299 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4300 State.regs[dstreg] = load_half (State.regs[REG_SP]
4301 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4302}
4303
4304// 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
43058.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4306"movhu"
4307*am33
4308{
4309 int srcreg;
4310
4311 PC = cia;
9c55817e 4312 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4313 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4314 State.regs[srcreg]);
4315}
4316
4317
377e53bb
JL		 4318// 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
43198.0xfe+8.0xea+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4320"movhu"
4321*am33
4322{
4323 int srcreg, dstreg;
4324
4325 PC = cia;
9c55817e
JL		 4326 srcreg = translate_rreg (SD_, RM0);
4327 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 4328 State.regs[dstreg] = load_half (State.regs[srcreg]
4329 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4330 State.regs[srcreg] += 2;
4331}
4332
4333// 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
43348.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4335"movhu"
4336*am33
4337{
4338 int srcreg, dstreg;
4339
4340 PC = cia;
9c55817e
JL		 4341 srcreg = translate_rreg (SD_, RM2);
4342 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 4343 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4344 State.regs[srcreg]);
4345 State.regs[dstreg] += 2;
4346}
4347
3e75ff7e 4348
377e53bb
JL		 4349// ??? mac
4350// ??? macu
4351// ??? macb
4352// ??? macbu
4353// ??? mach
4354// ??? machu
4355// ??? dmach
4356// ??? dmachu
4357// ??? dmulh
4358// ??? dmulhu
3e75ff7e
JL		 4359
4360// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
43618.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4362"mov"
4363*am33
4364{
4365 int dstreg;
4366
4367 PC = cia;
9c55817e 4368 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4369 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4370}
4371
4372// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
43738.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4374"mov"
4375*am33
4376{
4377 int srcreg;
4378
4379 PC = cia;
9c55817e 4380 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4381 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4382}
4383
4384// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
43858.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4386"movbu"
4387*am33
4388{
4389 int dstreg;
4390
4391 PC = cia;
9c55817e 4392 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4393 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4394}
4395
4396// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
43978.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4398"movbu"
4399*am33
4400{
4401 int srcreg;
4402
4403 PC = cia;
9c55817e 4404 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4405 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4406}
4407
4408// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
44098.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4410"movhu"
4411*am33
4412{
4413 int dstreg;
4414
4415 PC = cia;
9c55817e 4416 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4417 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4418}
4419
4420// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
44218.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4422"movhu"
4423*am33
4424{
4425 int srcreg;
4426
4427 PC = cia;
9c55817e 4428 srcreg = translate_rreg (SD_, RM2);
3e75ff7e 4429 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
0f7d7385
JL		 4430}
4431
9c55817e 4432// ??? DSP
GDB Binutils - Deliverables
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