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* dwarf2read.c: Revert Andrew Cagney's change of Dec 15, 1997.
[deliverable/binutils-gdb.git] / sim / mn10300 / am33.igen
CommitLineData
c2d11a7d
JM		 1// Helper:
2//
3// Given an extended register number, translate it into an index into the
4// register array. This is necessary as the upper 8 extended registers are
5// actually synonyms for the d0-d3/a0-a3 registers.
6//
7//
8
9:function:::int:translate_rreg:int rreg
10{
11
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
18 else
19 return REG_E0 + rreg;
20}
21
22:function:::int:translate_xreg:int xreg
23{
24 switch (xreg)
25 {
26 case 0:
27 return REG_SP;
28 case 1:
29 return REG_MDRQ;
30 case 2:
31 return REG_MCRH;
32 case 3:
33 return REG_MCRL;
34 case 4:
35 return REG_MCVF;
36 default:
37 abort ();
38 }
39}
40
41// 1111 0000 0010 00An; mov USP,An
428.0xf0+4.0x2,00,2.AN0:D0m:::mov
43"mov"
44*am33
45{
46 PC = cia;
47 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
48}
49
50
51// 1111 0000 0010 01An; mov SSP,An
528.0xf0+4.0x2,01,2.AN0:D0n:::mov
53"mov"
54*am33
55{
56 PC = cia;
57 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
58}
59
60
61// 1111 0000 0010 10An; mov MSP,An
628.0xf0+4.0x2,10,2.AN0:D0o:::mov
63"mov"
64*am33
65{
66 PC = cia;
67 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
68}
69
70
71// 1111 0000 0010 11An; mov PC,An
728.0xf0+4.0x2,11,2.AN0:D0p:::mov
73"mov"
74*am33
75{
76 PC = cia;
77 State.regs[REG_A0 + AN0] = PC;
78}
79
80
81// 1111 0000 0011 Am00; mov Am,USP
828.0xf0+4.0x3,2.AM1,00:D0q:::mov
83"mov"
84*am33
85{
86 PC = cia;
87 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
88}
89
90// 1111 0000 0011 Am01; mov Am,SSP
918.0xf0+4.0x3,2.AM1,01:D0r:::mov
92"mov"
93*am33
94{
95 PC = cia;
96 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
97}
98
99// 1111 0000 0011 Am10; mov Am,MSP
1008.0xf0+4.0x3,2.AM1,10:D0s:::mov
101"mov"
102*am33
103{
104 PC = cia;
105 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
106}
107
108
109// 1111 0000 1110 imm4; syscall
1108.0xf0+4.0xe,IMM4:D0t:::syscall
111"syscall"
112*am33
113{
114 unsigned int sp, next_pc;
115
116 PC = cia;
117 sp = State.regs[REG_SP];
118 next_pc = State.regs[REG_PC] + 2;
119 store_word (sp - 4, next_pc);
120 store_word (sp - 8, PSW);
121 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
122 nia = PC;
123}
124
125
126// 1111 0010 1110 11Dn; mov EPSW,Dn
1278.0xf2+4.0xe,11,2.DN0:D0u:::mov
128"mov"
129*am33
130{
131 PC = cia;
132 State.regs[REG_D0 + DN0] = PSW;
133}
134
135
136// 1111 0010 1111 Dm01; mov Dm,EPSW
1378.0xf2+4.0xf,2.DM1,01:D0v:::mov
138"mov"
139*am33
140{
141 PC = cia;
142 PSW = State.regs[REG_D0 + DM1];
143}
144
145// 1111 0101 00Am Rn; mov Am,Rn
1468.0xf5+00,2.AM1,4.RN0:D0w:::mov
147"mov"
148*am33
149{
150 int destreg = translate_rreg (SD_, RN0);
151
152 PC = cia;
153 State.regs[destreg] = State.regs[REG_A0 + AM1];
154}
155
156// 1111 0101 01Dm Rn; mov Dm,Rn
1578.0xf5+01,2.DM1,4.RN0:D0x:::mov
158"mov"
159*am33
160{
161 int destreg = translate_rreg (SD_, RN0);
162
163 PC = cia;
164 State.regs[destreg] = State.regs[REG_D0 + DM1];
165}
166
167// 1111 0101 10Rm An; mov Rm,An
1688.0xf5+10,4.RM1,2.AN0:D0y:::mov
169"mov"
170*am33
171{
172 int destreg = translate_rreg (SD_, RM1);
173
174 PC = cia;
175 State.regs[REG_A0 + AN0] = State.regs[destreg];
176}
177
178// 1111 0101 11Rm Dn; mov Rm,Dn
1798.0xf5+11,4.RM1,2.DN0:D0z:::mov
180"mov"
181*am33
182{
183 int destreg = translate_rreg (SD_, RM1);
184
185 PC = cia;
186 State.regs[REG_D0 + DN0] = State.regs[destreg];
187}
188
189
190// 1111 1000 1100 1110 regs....; movm (USP),regs
1918.0xf8+8.0xce+8.REGS:D1a:::movm
192"movm"
193*am33
194{
195 unsigned long usp = State.regs[REG_USP];
196 unsigned long mask;
197
198 PC = cia;
199 mask = REGS;
200
201 if (mask & 0x8)
202 {
203 usp += 4;
204 State.regs[REG_LAR] = load_word (usp);
205 usp += 4;
206 State.regs[REG_LIR] = load_word (usp);
207 usp += 4;
208 State.regs[REG_MDR] = load_word (usp);
209 usp += 4;
210 State.regs[REG_A0 + 1] = load_word (usp);
211 usp += 4;
212 State.regs[REG_A0] = load_word (usp);
213 usp += 4;
214 State.regs[REG_D0 + 1] = load_word (usp);
215 usp += 4;
216 State.regs[REG_D0] = load_word (usp);
217 usp += 4;
218 }
219
220 if (mask & 0x10)
221 {
222 State.regs[REG_A0 + 3] = load_word (usp);
223 usp += 4;
224 }
225
226 if (mask & 0x20)
227 {
228 State.regs[REG_A0 + 2] = load_word (usp);
229 usp += 4;
230 }
231
232 if (mask & 0x40)
233 {
234 State.regs[REG_D0 + 3] = load_word (usp);
235 usp += 4;
236 }
237
238 if (mask & 0x80)
239 {
240 State.regs[REG_D0 + 2] = load_word (usp);
241 usp += 4;
242 }
243
244 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
245 {
246 if (mask & 0x1)
247 {
248 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
249 usp += 16;
250 State.regs[REG_E0 + 1] = load_word (usp);
251 usp += 4;
252 State.regs[REG_E0 + 0] = load_word (usp);
253 usp += 4;
254 }
255
256 if (mask & 0x2)
257 {
258 State.regs[REG_E0 + 7] = load_word (usp);
259 usp += 4;
260 State.regs[REG_E0 + 6] = load_word (usp);
261 usp += 4;
262 State.regs[REG_E0 + 5] = load_word (usp);
263 usp += 4;
264 State.regs[REG_E0 + 4] = load_word (usp);
265 usp += 4;
266 }
267
268 if (mask & 0x4)
269 {
270 State.regs[REG_E0 + 3] = load_word (usp);
271 usp += 4;
272 State.regs[REG_E0 + 2] = load_word (usp);
273 usp += 4;
274 }
275 }
276
277 /* And make sure to update the stack pointer. */
278 State.regs[REG_USP] = usp;
279}
280
281// 1111 1000 1100 1111 regs....; movm (USP),regs
2828.0xf8+8.0xcf+8.REGS:D1b:::movm
283"movm"
284*am33
285{
286 unsigned long usp = State.regs[REG_USP];
287 unsigned long mask;
288
289 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
290 {
291 if (mask & 0x4)
292 {
293 usp -= 4;
294 store_word (usp, State.regs[REG_E0 + 2]);
295 usp -= 4;
296 store_word (usp, State.regs[REG_E0 + 3]);
297 }
298
299 if (mask & 0x2)
300 {
301 usp -= 4;
302 store_word (usp, State.regs[REG_E0 + 4]);
303 usp -= 4;
304 store_word (usp, State.regs[REG_E0 + 5]);
305 usp -= 4;
306 store_word (usp, State.regs[REG_E0 + 6]);
307 usp -= 4;
308 store_word (usp, State.regs[REG_E0 + 7]);
309 }
310
311 if (mask & 0x1)
312 {
313 usp -= 4;
314 store_word (usp, State.regs[REG_E0 + 0]);
315 usp -= 4;
316 store_word (usp, State.regs[REG_E0 + 1]);
317 usp -= 16;
318 /* Need to save MDQR, MCRH, MCRL, and MCVF */
319 }
320 }
321
322 if (mask & 0x80)
323 {
324 usp -= 4;
325 store_word (usp, State.regs[REG_D0 + 2]);
326 }
327
328 if (mask & 0x40)
329 {
330 usp -= 4;
331 store_word (usp, State.regs[REG_D0 + 3]);
332 }
333
334 if (mask & 0x20)
335 {
336 usp -= 4;
337 store_word (usp, State.regs[REG_A0 + 2]);
338 }
339
340 if (mask & 0x10)
341 {
342 usp -= 4;
343 store_word (usp, State.regs[REG_A0 + 3]);
344 }
345
346 if (mask & 0x8)
347 {
348 usp -= 4;
349 store_word (usp, State.regs[REG_D0]);
350 usp -= 4;
351 store_word (usp, State.regs[REG_D0 + 1]);
352 usp -= 4;
353 store_word (usp, State.regs[REG_A0]);
354 usp -= 4;
355 store_word (usp, State.regs[REG_A0 + 1]);
356 usp -= 4;
357 store_word (usp, State.regs[REG_MDR]);
358 usp -= 4;
359 store_word (usp, State.regs[REG_LIR]);
360 usp -= 4;
361 store_word (usp, State.regs[REG_LAR]);
362 usp -= 4;
363 }
364
365 /* And make sure to update the stack pointer. */
366 State.regs[REG_USP] = usp;
367}
368
369// 1111 1100 1111 1100 imm32...; and imm32,EPSW
3708.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
371"and"
372*am33
373{
374 PC = cia;
375 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
376}
377
378// 1111 1100 1111 1101 imm32...; or imm32,EPSW
3798.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
380"or"
381*am33
382{
383 PC = cia;
384 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
385}
386
387// 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
3888.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
389"mov"
390*am33
391{
392 int srcreg, dstreg;
393
394 PC = cia;
395
396 srcreg = translate_rreg (SD_, RM2);
397 dstreg = translate_rreg (SD_, RN0);
398 State.regs[dstreg] = State.regs[srcreg];
399}
400
401// 1111 1001 0001 1000 Rn Rn; ext Rn
4028.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
403"mov"
404*am33
405{
406 int srcreg;
407
408 PC = cia;
409 srcreg = translate_rreg (SD_, RN0);
410 if (State.regs[srcreg] & 0x80000000)
411 State.regs[REG_MDR] = -1;
412 else
413 State.regs[REG_MDR] = 0;
414}
415
416// 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
4178.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
418"extb"
419*am33
420{
421 int srcreg, dstreg;
422
423 PC = cia;
424 srcreg = translate_rreg (SD_, RM2);
425 dstreg = translate_rreg (SD_, RN0);
426 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
427}
428
429// 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
4308.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
431"extbu"
432*am33
433{
434 int srcreg, dstreg;
435
436 PC = cia;
437 srcreg = translate_rreg (SD_, RM2);
438 dstreg = translate_rreg (SD_, RN0);
439 State.regs[dstreg] = State.regs[srcreg] & 0xff;
440}
441
442// 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
4438.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
444"exth"
445*am33
446{
447 int srcreg, dstreg;
448
449 PC = cia;
450 srcreg = translate_rreg (SD_, RM2);
451 dstreg = translate_rreg (SD_, RN0);
452 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
453}
454
455// 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
4568.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
457"exthu"
458*am33
459{
460 int srcreg, dstreg;
461
462 PC = cia;
463 srcreg = translate_rreg (SD_, RM2);
464 dstreg = translate_rreg (SD_, RN0);
465 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
466}
467
468// 1111 1001 0110 1000 Rn Rn; clr Rn
4698.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
470"clr"
471*am33
472{
473 int dstreg;
474
475 PC = cia;
476 dstreg = translate_rreg (SD_, RN0);
477 State.regs[dstreg] = 0;
478 PSW |= PSW_Z;
479 PSW &= ~(PSW_V | PSW_C | PSW_N);
480}
481
482// 1111 1001 0111 1000 Rm Rn; add Rm,Rn
4838.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
484"add"
485*am33
486{
487 int srcreg, dstreg;
488
489 PC = cia;
490 srcreg = translate_rreg (SD_, RM2);
491 dstreg = translate_rreg (SD_, RN0);
492 genericAdd (State.regs[srcreg], dstreg);
493}
494
495// 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
4968.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
497"addc"
498*am33
499{
500 int srcreg, dstreg;
501 int z, c, n, v;
502 unsigned long reg1, reg2, sum;
503
504 PC = cia;
505 srcreg = translate_rreg (SD_, RM2);
506 dstreg = translate_rreg (SD_, RN0);
507
508 reg1 = State.regs[srcreg];
509 reg2 = State.regs[dstreg];
510 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
511 State.regs[dstreg] = sum;
512
513 z = ((PSW & PSW_Z) != 0) && (sum == 0);
514 n = (sum & 0x80000000);
515 c = (sum < reg1) || (sum < reg2);
516 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
517 && (reg2 & 0x80000000) != (sum & 0x80000000));
518
519 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
520 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
521 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
522}
523
524// 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
5258.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
526"sub"
527*am33
528{
529 int srcreg, dstreg;
530
531 PC = cia;
532 srcreg = translate_rreg (SD_, RM2);
533 dstreg = translate_rreg (SD_, RN0);
534 genericSub (State.regs[srcreg], dstreg);
535}
536
537// 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
5388.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
539"subc"
540*am33
541{
542 int srcreg, dstreg;
543 int z, c, n, v;
544 unsigned long reg1, reg2, difference;
545
546 PC = cia;
547 srcreg = translate_rreg (SD_, RM2);
548 dstreg = translate_rreg (SD_, RN0);
549
550 reg1 = State.regs[srcreg];
551 reg2 = State.regs[dstreg];
552 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
553 State.regs[dstreg] = difference;
554
555 z = ((PSW & PSW_Z) != 0) && (difference == 0);
556 n = (difference & 0x80000000);
557 c = (reg1 > reg2);
558 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
559 && (reg2 & 0x80000000) != (difference & 0x80000000));
560
561 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
562 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
563 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
564}
565
566// 1111 1001 1011 1000 Rn Rn; inc Rn
5678.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
568"inc"
569*am33
570{
571 int dstreg;
572
573 PC = cia;
574 dstreg = translate_rreg (SD_, RN0);
575 genericAdd (1, dstreg);
576}
577
578// 1111 1001 1101 1000 Rn Rn; inc Rn
5798.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
580"inc4"
581*am33
582{
583 int dstreg;
584
585 PC = cia;
586 dstreg = translate_rreg (SD_, RN0);
587 State.regs[dstreg] += 4;
588}
589
590// 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
5918.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
592"cmp"
593*am33
594{
595 int srcreg1, srcreg2;
596
597 PC = cia;
598 srcreg1 = translate_rreg (SD_, RN0);
599 srcreg2 = translate_rreg (SD_, RM2);
600 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
601}
602
603// 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
6048.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
605"mov"
606*am33
607{
608 int dstreg, srcreg;
609
610 PC = cia;
611 dstreg = translate_rreg (SD_, RN0);
612 srcreg = translate_xreg (SD_, XRM2);
613
614 State.regs[dstreg] = State.regs[srcreg];
615}
616
617// 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
6188.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
619"mov"
620*am33
621{
622 int srcreg, dstreg;
623
624 PC = cia;
625 srcreg = translate_rreg (SD_, RM2);
626 dstreg = translate_xreg (SD_, XRN0);
627
628 State.regs[dstreg] = State.regs[srcreg];
629}
630
631// 1111 1001 0000 1001 Rm Rn; and Rm,Rn
6328.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
633"and"
634*am33
635{
636 int srcreg, dstreg;
637 int z, n;
638
639 PC = cia;
640
641 srcreg = translate_rreg (SD_, RM2);
642 dstreg = translate_rreg (SD_, RN0);
643
644 State.regs[dstreg] &= State.regs[srcreg];
645 z = (State.regs[dstreg] == 0);
646 n = (State.regs[dstreg] & 0x80000000) != 0;
647 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
648 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
649}
650
651// 1111 1001 0001 1001 Rm Rn; or Rm,Rn
6528.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
653"or"
654*am33
655{
656 int srcreg, dstreg;
657 int z, n;
658
659 PC = cia;
660 srcreg = translate_rreg (SD_, RM2);
661 dstreg = translate_rreg (SD_, RN0);
662
663 State.regs[dstreg] |= State.regs[srcreg];
664 z = (State.regs[dstreg] == 0);
665 n = (State.regs[dstreg] & 0x80000000) != 0;
666 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
667 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
668}
669
670// 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
6718.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
672"xor"
673*am33
674{
675 int srcreg, dstreg;
676 int z, n;
677
678 PC = cia;
679 srcreg = translate_rreg (SD_, RM2);
680 dstreg = translate_rreg (SD_, RN0);
681
682 State.regs[dstreg] ^= State.regs[srcreg];
683 z = (State.regs[dstreg] == 0);
684 n = (State.regs[dstreg] & 0x80000000) != 0;
685 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
686 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
687}
688
689// 1111 1001 0011 1001 Rn Rn; not Rn
6908.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
691"not"
692*am33
693{
694 int dstreg;
695 int z, n;
696
697 PC = cia;
698 dstreg = translate_rreg (SD_, RN0);
699
700 State.regs[dstreg] = ~State.regs[dstreg];
701 z = (State.regs[dstreg] == 0);
702 n = (State.regs[dstreg] & 0x80000000) != 0;
703 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
704 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
705}
706
707// 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
7088.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
709"asr"
710*am33
711{
712 int srcreg, dstreg;
713 long temp;
714 int c, z, n;
715
716 PC = cia;
717 srcreg = translate_rreg (SD_, RM2);
718 dstreg = translate_rreg (SD_, RN0);
719
720 temp = State.regs[dstreg];
721 c = temp & 1;
722 temp >>= State.regs[srcreg];
723 State.regs[dstreg] = temp;
724 z = (State.regs[dstreg] == 0);
725 n = (State.regs[dstreg] & 0x80000000) != 0;
726 PSW &= ~(PSW_Z | PSW_N | PSW_C);
727 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
728}
729
730// 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
7318.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
732"lsr"
733*am33
734{
735 int srcreg, dstreg;
736 int z, n, c;
737
738 PC = cia;
739
740 srcreg = translate_rreg (SD_, RM2);
741 dstreg = translate_rreg (SD_, RN0);
742
743 c = State.regs[dstreg] & 1;
744 State.regs[dstreg] >>= State.regs[srcreg];
745 z = (State.regs[dstreg] == 0);
746 n = (State.regs[dstreg] & 0x80000000) != 0;
747 PSW &= ~(PSW_Z | PSW_N | PSW_C);
748 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
749}
750
751// 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
7528.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
753"asl"
754*am33
755{
756 int srcreg, dstreg;
757 int z, n;
758
759 PC = cia;
760 srcreg = translate_rreg (SD_, RM2);
761 dstreg = translate_rreg (SD_, RN0);
762
763 State.regs[dstreg] <<= State.regs[srcreg];
764 z = (State.regs[dstreg] == 0);
765 n = (State.regs[dstreg] & 0x80000000) != 0;
766 PSW &= ~(PSW_Z | PSW_N);
767 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
768}
769
770// 1111 1001 0111 1001 Rn Rn; asl2 Rn
7718.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
772"asl2"
773*am33
774{
775 int dstreg;
776 int n, z;
777
778 PC = cia;
779 dstreg = translate_rreg (SD_, RN0);
780
781 State.regs[dstreg] <<= 2;
782 z = (State.regs[dstreg] == 0);
783 n = (State.regs[dstreg] & 0x80000000) != 0;
784 PSW &= ~(PSW_Z | PSW_N);
785 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
786}
787
788// 1111 1001 1000 1001 Rn Rn; ror Rn
7898.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
790"ror"
791*am33
792{
793 int dstreg;
794 int c, n, z;
795 unsigned long value;
796
797 PC = cia;
798 dstreg = translate_rreg (SD_, RN0);
799
800 value = State.regs[dstreg];
801 c = (value & 0x1);
802
803 value >>= 1;
804 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
805 State.regs[dstreg] = value;
806 z = (value == 0);
807 n = (value & 0x80000000) != 0;
808 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
809 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
810}
811
812// 1111 1001 1001 1001 Rn Rn; rol Rn
8138.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
814"rol"
815*am33
816{
817 int dstreg;
818 int c, n, z;
819 unsigned long value;
820
821 PC = cia;
822 dstreg = translate_rreg (SD_, RN0);
823
824 value = State.regs[dstreg];
825 c = (value & 0x80000000) ? 1 : 0;
826
827 value <<= 1;
828 value |= ((PSW & PSW_C) != 0);
829 State.regs[dstreg] = value;
830 z = (value == 0);
831 n = (value & 0x80000000) != 0;
832 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
833 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
834}
835
836// 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
8378.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
838"mul"
839*am33
840{
841 int srcreg, dstreg;
842 unsigned long long temp;
843 int n, z;
844
845 PC = cia;
846 srcreg = translate_rreg (SD_, RM2);
847 dstreg = translate_rreg (SD_, RN0);
848
849 temp = ((signed64)(signed32)State.regs[dstreg]
850 * (signed64)(signed32)State.regs[srcreg]);
851 State.regs[dstreg] = temp & 0xffffffff;
852 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
853 z = (State.regs[dstreg] == 0);
854 n = (State.regs[dstreg] & 0x80000000) != 0;
855 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
856 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
857}
858
859// 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
8608.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
861"mulu"
862*am33
863{
864 int srcreg, dstreg;
865 unsigned long long temp;
866 int n, z;
867
868 PC = cia;
869 srcreg = translate_rreg (SD_, RM2);
870 dstreg = translate_rreg (SD_, RN0);
871
872 temp = ((unsigned64)State.regs[dstreg]
873 * (unsigned64)State.regs[srcreg]);
874 State.regs[dstreg] = temp & 0xffffffff;
875 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
876 z = (State.regs[dstreg] == 0);
877 n = (State.regs[dstreg] & 0x80000000) != 0;
878 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
879 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
880}
881
882// 1111 1001 1100 1001 Rm Rn; div Rm,Rn
8838.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
884"div"
885*am33
886{
887 int srcreg, dstreg;
888 long long temp;
889 int n, z;
890
891 PC = cia;
892 srcreg = translate_rreg (SD_, RM2);
893 dstreg = translate_rreg (SD_, RN0);
894
895 temp = State.regs[REG_MDR];
896 temp <<= 32;
897 temp |= State.regs[dstreg];
898 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
899 temp /= (signed32)State.regs[srcreg];
900 State.regs[dstreg] = temp & 0xffffffff;
901 z = (State.regs[dstreg] == 0);
902 n = (State.regs[dstreg] & 0x80000000) != 0;
903 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
904 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
905}
906
907// 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
9088.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
909"divu"
910*am33
911{
912 int srcreg, dstreg;
913 unsigned long long temp;
914 int n, z;
915
916 PC = cia;
917 srcreg = translate_rreg (SD_, RM2);
918 dstreg = translate_rreg (SD_, RN0);
919
920 temp = State.regs[REG_MDR];
921 temp <<= 32;
922 temp |= State.regs[dstreg];
923 State.regs[REG_MDR] = temp % State.regs[srcreg];
924 temp /= State.regs[srcreg];
925 State.regs[dstreg] = temp & 0xffffffff;
926 z = (State.regs[dstreg] == 0);
927 n = (State.regs[dstreg] & 0x80000000) != 0;
928 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
929 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
930}
931
932
933// 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
9348.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
935"mov"
936*am33
937{
938 int srcreg, dstreg;
939
940 PC = cia;
941 srcreg = translate_rreg (SD_, RM0);
942 dstreg = translate_rreg (SD_, RN2);
943 State.regs[dstreg] = load_word (State.regs[srcreg]);
944}
945
946// 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
9478.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
948"mov"
949*am33
950{
951 int srcreg, dstreg;
952
953 PC = cia;
954 srcreg = translate_rreg (SD_, RM2);
955 dstreg = translate_rreg (SD_, RN0);
956 store_word (State.regs[dstreg], State.regs[srcreg]);
957}
958
959// 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
9608.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
961"movbu"
962*am33
963{
964 int srcreg, dstreg;
965
966 PC = cia;
967 srcreg = translate_rreg (SD_, RM0);
968 dstreg = translate_rreg (SD_, RN2);
969 State.regs[dstreg] = load_byte (State.regs[srcreg]);
970}
971
972// 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
9738.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
974"movbu"
975*am33
976{
977 int srcreg, dstreg;
978
979 PC = cia;
980 srcreg = translate_rreg (SD_, RM2);
981 dstreg = translate_rreg (SD_, RN0);
982 store_byte (State.regs[dstreg], State.regs[srcreg]);
983}
984
985// 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
9868.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
987"movhu"
988*am33
989{
990 int srcreg, dstreg;
991
992 PC = cia;
993 srcreg = translate_rreg (SD_, RM0);
994 dstreg = translate_rreg (SD_, RN2);
995 State.regs[dstreg] = load_half (State.regs[srcreg]);
996}
997
998// 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
9998.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
1000"movhu"
1001*am33
1002{
1003 int srcreg, dstreg;
1004
1005 PC = cia;
1006 srcreg = translate_rreg (SD_, RM2);
1007 dstreg = translate_rreg (SD_, RN0);
1008 store_half (State.regs[dstreg], State.regs[srcreg]);
1009}
1010
1011// 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
10128.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
1013"mov"
1014*am33
1015{
1016 int srcreg, dstreg;
1017
1018 PC = cia;
1019 srcreg = translate_rreg (SD_, RM0);
1020 dstreg = translate_rreg (SD_, RN2);
1021 State.regs[dstreg] = load_word (State.regs[srcreg]);
1022 State.regs[srcreg] += 4;
1023}
1024
1025// 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
10268.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1027"mov"
1028*am33
1029{
1030 int srcreg, dstreg;
1031
1032 PC = cia;
1033 srcreg = translate_rreg (SD_, RM2);
1034 dstreg = translate_rreg (SD_, RN0);
1035 store_word (State.regs[dstreg], State.regs[srcreg]);
1036 State.regs[dstreg] += 4;
1037}
1038
1039// 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
10408.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1041"mov"
1042*am33
1043{
1044 int dstreg;
1045
1046 PC = cia;
1047 dstreg = translate_rreg (SD_, RN2);
1048 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1049}
1050
1051// 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
10528.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1053"mov"
1054*am33
1055{
1056 int srcreg;
1057
1058 PC = cia;
1059 srcreg = translate_rreg (SD_, RM2);
1060 store_word (State.regs[REG_SP], State.regs[srcreg]);
1061}
1062
1063// 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
10648.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1065"movbu"
1066*am33
1067{
1068 int dstreg;
1069
1070 PC = cia;
1071 dstreg = translate_rreg (SD_, RN2);
1072 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1073}
1074
1075// 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
10768.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1077"movbu"
1078*am33
1079{
1080 int srcreg;
1081
1082 PC = cia;
1083 srcreg = translate_rreg (SD_, RM2);
1084 store_byte (State.regs[REG_SP], State.regs[srcreg]);
1085}
1086
1087// 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
10888.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1089"movhu"
1090*am33
1091{
1092 int dstreg;
1093
1094 PC = cia;
1095 dstreg = translate_rreg (SD_, RN2);
1096 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1097}
1098
1099// 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
11008.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1101"movhu"
1102*am33
1103{
1104 int srcreg;
1105
1106 PC = cia;
1107 srcreg = translate_rreg (SD_, RM2);
1108 store_half (State.regs[REG_SP], State.regs[srcreg]);
1109}
1110
1111// 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
11128.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
1113"movhu"
1114*am33
1115{
1116 int srcreg, dstreg;
1117
1118 PC = cia;
1119 srcreg = translate_rreg (SD_, RM0);
1120 dstreg = translate_rreg (SD_, RN2);
1121 State.regs[dstreg] = load_half (State.regs[srcreg]);
1122 State.regs[srcreg] += 2;
1123}
1124
1125// 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
11268.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1127"movhu"
1128*am33
1129{
1130 int srcreg, dstreg;
1131
1132 PC = cia;
1133 srcreg = translate_rreg (SD_, RM2);
1134 dstreg = translate_rreg (SD_, RN0);
1135 store_half (State.regs[dstreg], State.regs[srcreg]);
1136 State.regs[dstreg] += 2;
1137}
1138
1139
1140// 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
11418.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1142"mac"
1143*am33
1144{
1145 int srcreg1, srcreg2;
1146 long long temp, sum;
1147 int c, v;
1148
1149 PC = cia;
1150 srcreg1 = translate_rreg (SD_, RM2);
1151 srcreg2 = translate_rreg (SD_, RN0);
1152
1153 temp = ((signed64)(signed32)State.regs[srcreg2]
1154 * (signed64)(signed32)State.regs[srcreg1]);
1155 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1156 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1157 State.regs[REG_MCRL] = sum;
1158 temp >>= 32;
1159 temp &= 0xffffffff;
1160 sum = State.regs[REG_MCRH] + temp + c;
1161 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1162 && (temp & 0x80000000) != (sum & 0x80000000));
1163 State.regs[REG_MCRH] = sum;
1164 if (v)
1165 State.regs[REG_MCVF] = 1;
1166}
1167
1168// 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
11698.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1170"macu"
1171*am33
1172{
1173 int srcreg1, srcreg2;
1174 unsigned long long temp, sum;
1175 int c, v;
1176
1177 PC = cia;
1178 srcreg1 = translate_rreg (SD_, RM2);
1179 srcreg2 = translate_rreg (SD_, RN0);
1180
1181 temp = ((unsigned64)State.regs[srcreg2]
1182 * (unsigned64)State.regs[srcreg1]);
1183 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1184 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1185 State.regs[REG_MCRL] = sum;
1186 temp >>= 32;
1187 temp &= 0xffffffff;
1188 sum = State.regs[REG_MCRH] + temp + c;
1189 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1190 && (temp & 0x80000000) != (sum & 0x80000000));
1191 State.regs[REG_MCRH] = sum;
1192 if (v)
1193 State.regs[REG_MCVF] = 1;
1194}
1195
1196// 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
11978.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1198"macb"
1199*am33
1200{
1201 int srcreg1, srcreg2;
1202 long temp, sum;
1203 int v;
1204
1205 PC = cia;
1206 srcreg1 = translate_rreg (SD_, RM2);
1207 srcreg2 = translate_rreg (SD_, RN0);
1208
1209 temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
1210 * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
1211 sum = State.regs[REG_MCRL] + temp;
1212 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1213 && (temp & 0x80000000) != (sum & 0x80000000));
1214 State.regs[REG_MCRL] = sum;
1215 if (v)
1216 State.regs[REG_MCVF] = 1;
1217}
1218
1219// 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
12208.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1221"macbu"
1222*am33
1223{
1224 int srcreg1, srcreg2;
1225 long long temp, sum;
1226 int v;
1227
1228 PC = cia;
1229 srcreg1 = translate_rreg (SD_, RM2);
1230 srcreg2 = translate_rreg (SD_, RN0);
1231
1232 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1233 * (unsigned32)(State.regs[srcreg1] & 0xff));
1234 sum = State.regs[REG_MCRL] + temp;
1235 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1236 && (temp & 0x80000000) != (sum & 0x80000000));
1237 State.regs[REG_MCRL] = sum;
1238 if (v)
1239 State.regs[REG_MCVF] = 1;
1240}
1241
1242// 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
12438.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1244"mach"
1245*am33
1246{
1247 int srcreg1, srcreg2;
1248 long long temp, sum;
1249 int c, v;
1250
1251 PC = cia;
1252 srcreg1 = translate_rreg (SD_, RM2);
1253 srcreg2 = translate_rreg (SD_, RN0);
1254
1255 temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
1256 * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
1257 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1258 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1259 State.regs[REG_MCRL] = sum;
1260 temp >>= 32;
1261 temp &= 0xffffffff;
1262 sum = State.regs[REG_MCRH] + temp + c;
1263 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1264 && (temp & 0x80000000) != (sum & 0x80000000));
1265 State.regs[REG_MCRH] = sum;
1266 if (v)
1267 State.regs[REG_MCVF] = 1;
1268}
1269
1270// 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
12718.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1272"machu"
1273*am33
1274{
1275 int srcreg1, srcreg2;
1276 long long temp, sum;
1277 int c, v;
1278
1279 PC = cia;
1280 srcreg1 = translate_rreg (SD_, RM2);
1281 srcreg2 = translate_rreg (SD_, RN0);
1282
1283 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1284 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1285 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1286 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1287 State.regs[REG_MCRL] = sum;
1288 temp >>= 32;
1289 temp &= 0xffffffff;
1290 sum = State.regs[REG_MCRH] + temp + c;
1291 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1292 && (temp & 0x80000000) != (sum & 0x80000000));
1293 State.regs[REG_MCRH] = sum;
1294 if (v)
1295 State.regs[REG_MCVF] = 1;
1296}
1297
1298// 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
12998.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1300"dmach"
1301*am33
1302{
1303 int srcreg1, srcreg2;
1304 long temp, temp2, sum;
1305 int v;
1306
1307 PC = cia;
1308 srcreg1 = translate_rreg (SD_, RM2);
1309 srcreg2 = translate_rreg (SD_, RN0);
1310
1311 temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
1312 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
1313 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
1314 * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
1315 sum = temp + temp2 + State.regs[REG_MCRL];
1316 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1317 && (temp & 0x80000000) != (sum & 0x80000000));
1318 State.regs[REG_MCRL] = sum;
1319 if (v)
1320 State.regs[REG_MCVF] = 1;
1321}
1322
1323// 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
13248.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1325"dmachu"
1326*am33
1327{
1328 int srcreg1, srcreg2;
1329 unsigned long temp, temp2, sum;
1330 int v;
1331
1332 PC = cia;
1333 srcreg1 = translate_rreg (SD_, RM2);
1334 srcreg2 = translate_rreg (SD_, RN0);
1335
1336 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1337 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1338 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1339 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1340 sum = temp + temp2 + State.regs[REG_MCRL];
1341 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1342 && (temp & 0x80000000) != (sum & 0x80000000));
1343 State.regs[REG_MCRL] = sum;
1344 if (v)
1345 State.regs[REG_MCVF] = 1;
1346}
1347
1348// 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
13498.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1350"dmulh"
1351*am33
1352{
1353 int srcreg, dstreg;
1354 long temp;
1355
1356 PC = cia;
1357 srcreg = translate_rreg (SD_, RM2);
1358 dstreg = translate_rreg (SD_, RN0);
1359
1360 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
1361 * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
1362 State.regs[REG_MDRQ] = temp;
1363 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
1364 * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
1365 State.regs[dstreg] = temp;
1366}
1367
1368// 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
13698.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1370"dmachu"
1371*am33
1372{
1373 int srcreg, dstreg;
1374 unsigned long temp;
1375
1376 PC = cia;
1377 srcreg = translate_rreg (SD_, RM2);
1378 dstreg = translate_rreg (SD_, RN0);
1379
1380 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1381 * (unsigned32)(State.regs[srcreg] & 0xffff));
1382 State.regs[REG_MDRQ] = temp;
1383 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1384 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
1385 State.regs[dstreg] = temp;
1386}
1387
1388// 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
13898.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1390"sat16"
1391*am33
1392{
1393 int srcreg, dstreg;
1394 int value, z, n;
1395
1396 PC = cia;
1397 srcreg = translate_rreg (SD_, RM2);
1398 dstreg = translate_rreg (SD_, RN0);
1399
1400 value = State.regs[srcreg];
1401
1402 if (value >= 0x7fff)
1403 State.regs[dstreg] = 0x7fff;
1404 else if (value <= 0xffff8000)
1405 State.regs[dstreg] = 0xffff8000;
1406 else
1407 State.regs[dstreg] = value;
1408
1409 n = (State.regs[dstreg] & 0x8000) != 0;
1410 z = (State.regs[dstreg] == 0);
1411 PSW &= ~(PSW_Z | PSW_N);
1412 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1413}
1414
1415// 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
14168.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1417"mcste"
1418*am33
1419{
1420 int srcreg, dstreg;
1421
1422 PC = cia;
1423 srcreg = translate_rreg (SD_, RM2);
1424 dstreg = translate_rreg (SD_, RN0);
1425
1426 PSW &= ~(PSW_V | PSW_C);
1427 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1428
1429 /* 32bit saturation. */
1430 if (State.regs[srcreg] == 0x20)
1431 {
1432 long long tmp;
1433
1434 tmp = State.regs[REG_MCRH];
1435 tmp <<= 32;
1436 tmp += State.regs[REG_MCRL];
1437
1438 if (tmp > 0x7fffffff)
1439 State.regs[dstreg] = 0x7fffffff;
1440 else if (tmp < 0xffffffff80000000LL)
1441 State.regs[dstreg] = 0x80000000;
1442 else
1443 State.regs[dstreg] = tmp;
1444 }
1445 /* 16bit saturation */
1446 else if (State.regs[srcreg] == 0x10)
1447 {
1448 long long tmp;
1449
1450 tmp = State.regs[REG_MCRH];
1451 tmp <<= 32;
1452 tmp += State.regs[REG_MCRL];
1453
1454 if (tmp > 0x7fff)
1455 State.regs[dstreg] = 0x7fff;
1456 else if (tmp < 0xffffffffffff8000LL)
1457 State.regs[dstreg] = 0x8000;
1458 else
1459 State.regs[dstreg] = tmp;
1460 }
1461 /* 8 bit saturation */
1462 else if (State.regs[srcreg] == 0x8)
1463 {
1464 long long tmp;
1465
1466 tmp = State.regs[REG_MCRH];
1467 tmp <<= 32;
1468 tmp += State.regs[REG_MCRL];
1469
1470 if (tmp > 0x7f)
1471 State.regs[dstreg] = 0x7f;
1472 else if (tmp < 0xffffffffffffff80LL)
1473 State.regs[dstreg] = 0x80;
1474 else
1475 State.regs[dstreg] = tmp;
1476 }
1477 /* 9 bit saturation */
1478 else if (State.regs[srcreg] == 0x9)
1479 {
1480 long long tmp;
1481
1482 tmp = State.regs[REG_MCRH];
1483 tmp <<= 32;
1484 tmp += State.regs[REG_MCRL];
1485
1486 if (tmp > 0x80)
1487 State.regs[dstreg] = 0x80;
1488 else if (tmp < 0xffffffffffffff81LL)
1489 State.regs[dstreg] = 0x81;
1490 else
1491 State.regs[dstreg] = tmp;
1492 }
1493 /* 9 bit saturation */
1494 else if (State.regs[srcreg] == 0x30)
1495 {
1496 long long tmp;
1497
1498 tmp = State.regs[REG_MCRH];
1499 tmp <<= 32;
1500 tmp += State.regs[REG_MCRL];
1501
1502 if (tmp > 0x7fffffffffffLL)
1503 tmp = 0x7fffffffffffLL;
1504 else if (tmp < 0xffff800000000000LL)
1505 tmp = 0xffff800000000000LL;
1506
1507 tmp >>= 16;
1508 State.regs[dstreg] = tmp;
1509 }
1510}
1511
1512// 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
15138.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1514"swap"
1515*am33
1516{
1517 int srcreg, dstreg;
1518
1519 PC = cia;
1520 srcreg = translate_rreg (SD_, RM2);
1521 dstreg = translate_rreg (SD_, RN0);
1522
1523 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1524 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1525 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1526 | ((State.regs[srcreg] >> 24) & 0xff));
1527}
1528
1529// 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
15308.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1531"swaph"
1532*am33
1533{
1534 int srcreg, dstreg;
1535
1536 PC = cia;
1537 srcreg = translate_rreg (SD_, RM2);
1538 dstreg = translate_rreg (SD_, RN0);
1539
1540 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1541 | ((State.regs[srcreg] >> 8) & 0xff)
1542 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1543 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
1544}
1545
1546// 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
15478.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1548"swhw"
1549*am33
1550{
1551 int srcreg, dstreg;
1552
1553 PC = cia;
1554 srcreg = translate_rreg (SD_, RM2);
1555 dstreg = translate_rreg (SD_, RN0);
1556
1557 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1558 | ((State.regs[srcreg] >> 16) & 0xffff));
1559}
1560
1561// 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
15628.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1563"bsch"
1564*am33
1565{
1566 int temp, c, i;
1567 int srcreg, dstreg;
1568 int start;
1569
1570 PC = cia;
1571 srcreg = translate_rreg (SD_, RM2);
1572 dstreg = translate_rreg (SD_, RN0);
1573
1574 temp = State.regs[srcreg];
1575 start = (State.regs[dstreg] & 0x1f) - 1;
1576 if (start == -1)
1577 start = 31;
1578
1579 for (i = start; i >= 0; i--)
1580 {
1581 if (temp & (1 << i))
1582 {
1583 c = 1;
1584 State.regs[dstreg] = i;
1585 break;
1586 }
1587 }
1588
1589 if (i < 0)
1590 {
1591 c = 0;
1592 State.regs[dstreg] = 0;
1593 }
1594 PSW &= ~(PSW_C);
1595 PSW |= (c ? PSW_C : 0);
1596}
1597
1598
1599// 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
16008.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1601"mov"
1602*am33
1603{
1604 int dstreg;
1605
1606 PC = cia;
1607 dstreg = translate_rreg (SD_, RN0);
1608 State.regs[dstreg] = EXTEND8 (IMM8);
1609}
1610
1611// 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
16128.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1613"movu"
1614*am33
1615{
1616 int dstreg;
1617
1618 PC = cia;
1619 dstreg = translate_rreg (SD_, RN0);
1620 State.regs[dstreg] = IMM8 & 0xff;
1621}
1622
1623// 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
16248.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1625"add"
1626*am33
1627{
1628 int dstreg;
1629
1630 PC = cia;
1631 dstreg = translate_rreg (SD_, RN0);
1632 genericAdd (EXTEND8 (IMM8), dstreg);
1633}
1634
1635// 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
16368.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1637"addc"
1638*am33
1639{
1640 int dstreg, imm;
1641 int z, c, n, v;
1642 unsigned long reg1, reg2, sum;
1643
1644 PC = cia;
1645 dstreg = translate_rreg (SD_, RN0);
1646
1647 imm = EXTEND8 (IMM8);
1648 reg2 = State.regs[dstreg];
1649 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1650 State.regs[dstreg] = sum;
1651
1652 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1653 n = (sum & 0x80000000);
1654 c = (sum < imm) || (sum < reg2);
1655 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1656 && (reg2 & 0x80000000) != (sum & 0x80000000));
1657
1658 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1659 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1660 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1661}
1662
1663// 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
16648.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1665"sub"
1666*am33
1667{
1668 int dstreg;
1669
1670 PC = cia;
1671 dstreg = translate_rreg (SD_, RN0);
1672
1673 genericSub (EXTEND8 (IMM8), dstreg);
1674}
1675
1676// 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
16778.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1678"subc"
1679*am33
1680{
1681 int imm, dstreg;
1682 int z, c, n, v;
1683 unsigned long reg1, reg2, difference;
1684
1685 PC = cia;
1686 dstreg = translate_rreg (SD_, RN0);
1687
1688 imm = EXTEND8 (IMM8);
1689 reg2 = State.regs[dstreg];
1690 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1691 State.regs[dstreg] = difference;
1692
1693 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1694 n = (difference & 0x80000000);
1695 c = (imm > reg2);
1696 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1697 && (reg2 & 0x80000000) != (difference & 0x80000000));
1698
1699 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1700 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1701 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1702}
1703
1704// 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
17058.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1706"cmp"
1707*am33
1708{
1709 int srcreg;
1710
1711 PC = cia;
1712 srcreg = translate_rreg (SD_, RN0);
1713 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1714}
1715
1716// 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
17178.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1718"mov"
1719*am33
1720{
1721 int dstreg;
1722
1723 PC = cia;
1724 dstreg = translate_xreg (SD_, XRN0);
1725
1726 State.regs[dstreg] = IMM8;
1727}
1728
1729// 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
17308.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1731"and"
1732*am33
1733{
1734 int dstreg;
1735 int z, n;
1736
1737 PC = cia;
1738 dstreg = translate_rreg (SD_, RN0);
1739
1740 State.regs[dstreg] &= (IMM8 & 0xff);
1741 z = (State.regs[dstreg] == 0);
1742 n = (State.regs[dstreg] & 0x80000000) != 0;
1743 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1744 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1745}
1746
1747// 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
17488.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1749"or"
1750*am33
1751{
1752 int dstreg;
1753 int z, n;
1754
1755 PC = cia;
1756 dstreg = translate_rreg (SD_, RN0);
1757
1758 State.regs[dstreg] |= (IMM8 & 0xff);
1759 z = (State.regs[dstreg] == 0);
1760 n = (State.regs[dstreg] & 0x80000000) != 0;
1761 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1762 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1763}
1764
1765// 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
17668.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1767"xor"
1768*am33
1769{
1770 int dstreg;
1771 int z, n;
1772
1773 PC = cia;
1774 dstreg = translate_rreg (SD_, RN0);
1775
1776 State.regs[dstreg] ^= (IMM8 & 0xff);
1777 z = (State.regs[dstreg] == 0);
1778 n = (State.regs[dstreg] & 0x80000000) != 0;
1779 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1780 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1781}
1782
1783// 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
17848.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1785"asr"
1786*am33
1787{
1788 int dstreg;
1789 long temp;
1790 int c, z, n;
1791
1792 PC = cia;
1793 dstreg = translate_rreg (SD_, RN0);
1794
1795 temp = State.regs[dstreg];
1796 c = temp & 1;
1797 temp >>= (IMM8 & 0xff);
1798 State.regs[dstreg] = temp;
1799 z = (State.regs[dstreg] == 0);
1800 n = (State.regs[dstreg] & 0x80000000) != 0;
1801 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1802 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1803}
1804
1805// 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
18068.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1807"lsr"
1808*am33
1809{
1810 int dstreg;
1811 int z, n, c;
1812
1813 PC = cia;
1814 dstreg = translate_rreg (SD_, RN0);
1815
1816 c = State.regs[dstreg] & 1;
1817 State.regs[dstreg] >>= (IMM8 & 0xff);
1818 z = (State.regs[dstreg] == 0);
1819 n = (State.regs[dstreg] & 0x80000000) != 0;
1820 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1821 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1822}
1823
1824// 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
18258.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1826"asl"
1827*am33
1828{
1829 int srcreg, dstreg;
1830 int z, n;
1831
1832 PC = cia;
1833 dstreg = translate_rreg (SD_, RN0);
1834
1835 State.regs[dstreg] <<= (IMM8 & 0xff);
1836 z = (State.regs[dstreg] == 0);
1837 n = (State.regs[dstreg] & 0x80000000) != 0;
1838 PSW &= ~(PSW_Z | PSW_N);
1839 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1840}
1841
1842// 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
18438.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1844"mul"
1845*am33
1846{
1847 int dstreg;
1848 unsigned long long temp;
1849 int z, n;
1850
1851 PC = cia;
1852 dstreg = translate_rreg (SD_, RN0);
1853
1854 temp = ((signed64)(signed32)State.regs[dstreg]
1855 * (signed64)(signed32)EXTEND8 (IMM8));
1856 State.regs[dstreg] = temp & 0xffffffff;
1857 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1858 z = (State.regs[dstreg] == 0);
1859 n = (State.regs[dstreg] & 0x80000000) != 0;
1860 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1861 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1862}
1863
1864// 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
18658.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1866"mulu"
1867*am33
1868{
1869 int dstreg;
1870 unsigned long long temp;
1871 int z, n;
1872
1873 PC = cia;
1874 dstreg = translate_rreg (SD_, RN0);
1875
1876 temp = ((unsigned64)State.regs[dstreg]
1877 * (unsigned64)(IMM8 & 0xff));
1878 State.regs[dstreg] = temp & 0xffffffff;
1879 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1880 z = (State.regs[dstreg] == 0);
1881 n = (State.regs[dstreg] & 0x80000000) != 0;
1882 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1883 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1884}
1885
1886// 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
18878.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1888"btst"
1889*am33
1890{
1891 int srcreg;
1892
1893 PC = cia;
1894 srcreg = translate_rreg (SD_, RM0);
1895 genericBtst(IMM8, State.regs[srcreg]);
1896}
1897
1898// 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
18998.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1900"mov"
1901*am33
1902{
1903 int srcreg, dstreg;
1904
1905 PC = cia;
1906 srcreg = translate_rreg (SD_, RM0);
1907 dstreg = translate_rreg (SD_, RN2);
1908 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1909}
1910
1911// 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
19128.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1913"mov"
1914{
1915 int srcreg, dstreg;
1916
1917 PC = cia;
1918 srcreg = translate_rreg (SD_, RM2);
1919 dstreg = translate_rreg (SD_, RN0);
1920 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1921}
1922
1923// 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
19248.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1925"movbu"
1926{
1927 int srcreg, dstreg;
1928
1929 PC = cia;
1930 srcreg = translate_rreg (SD_, RM0);
1931 dstreg = translate_rreg (SD_, RN2);
1932 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1933}
1934
1935// 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
19368.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1937"movbu"
1938{
1939 int srcreg, dstreg;
1940
1941 PC = cia;
1942 srcreg = translate_rreg (SD_, RM2);
1943 dstreg = translate_rreg (SD_, RN0);
1944 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1945}
1946
1947// 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
19488.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1949"movhu"
1950{
1951 int srcreg, dstreg;
1952
1953 PC = cia;
1954 srcreg = translate_rreg (SD_, RM0);
1955 dstreg = translate_rreg (SD_, RN2);
1956 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1957}
1958
1959// 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
19608.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1961"movhu"
1962{
1963 int srcreg, dstreg;
1964
1965 PC = cia;
1966 srcreg = translate_rreg (SD_, RM2);
1967 dstreg = translate_rreg (SD_, RN0);
1968 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1969}
1970
1971// 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
19728.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
1973"mov"
1974*am33
1975{
1976 int srcreg, dstreg;
1977
1978 PC = cia;
1979 srcreg = translate_rreg (SD_, RM0);
1980 dstreg = translate_rreg (SD_, RN2);
1981 State.regs[dstreg] = load_word (State.regs[srcreg]);
1982 State.regs[srcreg] += EXTEND8 (IMM8);
1983}
1984
1985// 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
19868.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
1987"mov"
1988{
1989 int srcreg, dstreg;
1990
1991 PC = cia;
1992 srcreg = translate_rreg (SD_, RM2);
1993 dstreg = translate_rreg (SD_, RN0);
1994 store_word (State.regs[dstreg], State.regs[srcreg]);
1995 State.regs[dstreg] += EXTEND8 (IMM8);
1996}
1997
1998
1999// 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
20008.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2001"mov"
2002{
2003 int dstreg;
2004
2005 PC = cia;
2006 dstreg = translate_rreg (SD_, RN2);
2007 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2008}
2009
2010// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
20118.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2012"mov"
2013{
2014 int srcreg;
2015
2016 PC = cia;
2017 srcreg = translate_rreg (SD_, RM2);
2018 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2019}
2020
2021// 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
20228.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2023"movbu"
2024{
2025 int dstreg;
2026
2027 PC = cia;
2028 dstreg = translate_rreg (SD_, RN2);
2029 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2030}
2031
2032// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
20338.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2034"movbu"
2035{
2036 int srcreg;
2037
2038 PC = cia;
2039 srcreg = translate_rreg (SD_, RM2);
2040 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2041}
2042
2043// 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
20448.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2045"movhu"
2046{
2047 int dstreg;
2048
2049 PC = cia;
2050 dstreg = translate_rreg (SD_, RN2);
2051 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2052}
2053
2054// 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
20558.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2056"movhu"
2057{
2058 int srcreg;
2059
2060 PC = cia;
2061 srcreg = translate_rreg (SD_, RM2);
2062 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2063}
2064
2065// 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
20668.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
2067"movhu"
2068*am33
2069{
2070 int srcreg, dstreg;
2071
2072 PC = cia;
2073 srcreg = translate_rreg (SD_, RM0);
2074 dstreg = translate_rreg (SD_, RN2);
2075 State.regs[dstreg] = load_half (State.regs[srcreg]);
2076 State.regs[srcreg] += EXTEND8 (IMM8);
2077}
2078
2079// 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
20808.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2081"movhu"
2082{
2083 int srcreg, dstreg;
2084
2085 PC = cia;
2086 srcreg = translate_rreg (SD_, RM2);
2087 dstreg = translate_rreg (SD_, RN0);
2088 store_half (State.regs[dstreg], State.regs[srcreg]);
2089 State.regs[dstreg] += EXTEND8 (IMM8);
2090}
2091
2092
2093// 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
20948.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2095"mac"
2096{
2097 int srcreg;
2098 long long temp, sum;
2099 int c, v;
2100
2101 PC = cia;
2102 srcreg = translate_rreg (SD_, RN2);
2103
2104 temp = ((signed64)(signed32)EXTEND8 (IMM8)
2105 * (signed64)(signed32)State.regs[srcreg]);
2106 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2107 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2108 State.regs[REG_MCRL] = sum;
2109 temp >>= 32;
2110 temp &= 0xffffffff;
2111 sum = State.regs[REG_MCRH] + temp + c;
2112 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2113 && (temp & 0x80000000) != (sum & 0x80000000));
2114 State.regs[REG_MCRH] = sum;
2115 if (v)
2116 State.regs[REG_MCVF] = 1;
2117}
2118
2119// 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
21208.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2121"macu"
2122{
2123 int srcreg;
2124 long long temp, sum;
2125 int c, v;
2126
2127 PC = cia;
2128 srcreg = translate_rreg (SD_, RN2);
2129
2130 temp = ((unsigned64) (IMM8)
2131 * (unsigned64)State.regs[srcreg]);
2132 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2133 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2134 State.regs[REG_MCRL] = sum;
2135 temp >>= 32;
2136 temp &= 0xffffffff;
2137 sum = State.regs[REG_MCRH] + temp + c;
2138 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2139 && (temp & 0x80000000) != (sum & 0x80000000));
2140 State.regs[REG_MCRH] = sum;
2141 if (v)
2142 State.regs[REG_MCVF] = 1;
2143}
2144
2145// 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
21468.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2147"macb"
2148{
2149 int srcreg;
2150 long long temp, sum;
2151 int c, v;
2152
2153 PC = cia;
2154 srcreg = translate_rreg (SD_, RN2);
2155
2156 temp = ((signed64)(signed8)EXTEND8 (IMM8)
2157 * (signed64)(signed8)State.regs[srcreg] & 0xff);
2158 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2159 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2160 State.regs[REG_MCRL] = sum;
2161 temp >>= 32;
2162 temp &= 0xffffffff;
2163 sum = State.regs[REG_MCRH] + temp + c;
2164 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2165 && (temp & 0x80000000) != (sum & 0x80000000));
2166 State.regs[REG_MCRH] = sum;
2167 if (v)
2168 State.regs[REG_MCVF] = 1;
2169}
2170
2171// 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
21728.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2173"macbu"
2174{
2175 int srcreg;
2176 long long temp, sum;
2177 int c, v;
2178
2179 PC = cia;
2180 srcreg = translate_rreg (SD_, RN2);
2181
2182 temp = ((unsigned64) (IMM8)
2183 * (unsigned64)State.regs[srcreg] & 0xff);
2184 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2185 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2186 State.regs[REG_MCRL] = sum;
2187 temp >>= 32;
2188 temp &= 0xffffffff;
2189 sum = State.regs[REG_MCRH] + temp + c;
2190 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2191 && (temp & 0x80000000) != (sum & 0x80000000));
2192 State.regs[REG_MCRH] = sum;
2193 if (v)
2194 State.regs[REG_MCVF] = 1;
2195}
2196
2197// 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
21988.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2199"mach"
2200{
2201 int srcreg;
2202 long long temp, sum;
2203 int c, v;
2204
2205 PC = cia;
2206 srcreg = translate_rreg (SD_, RN2);
2207
2208 temp = ((signed64)(signed16)EXTEND8 (IMM8)
2209 * (signed64)(signed16)State.regs[srcreg] & 0xffff);
2210 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2211 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2212 State.regs[REG_MCRL] = sum;
2213 temp >>= 32;
2214 temp &= 0xffffffff;
2215 sum = State.regs[REG_MCRH] + temp + c;
2216 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2217 && (temp & 0x80000000) != (sum & 0x80000000));
2218 State.regs[REG_MCRH] = sum;
2219 if (v)
2220 State.regs[REG_MCVF] = 1;
2221}
2222
2223// 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
22248.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2225"machu"
2226{
2227 int srcreg;
2228 long long temp, sum;
2229 int c, v;
2230
2231 PC = cia;
2232 srcreg = translate_rreg (SD_, RN2);
2233
2234 temp = ((unsigned64) (IMM8)
2235 * (unsigned64)State.regs[srcreg] & 0xffff);
2236 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2237 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2238 State.regs[REG_MCRL] = sum;
2239 temp >>= 32;
2240 temp &= 0xffffffff;
2241 sum = State.regs[REG_MCRH] + temp + c;
2242 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2243 && (temp & 0x80000000) != (sum & 0x80000000));
2244 State.regs[REG_MCRH] = sum;
2245 if (v)
2246 State.regs[REG_MCVF] = 1;
2247}
2248
2249// 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
22508.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2251"mcste"
2252{
2253 int dstreg;
2254
2255 PC = cia;
2256 dstreg = translate_rreg (SD_, RN0);
2257
2258 PSW &= ~(PSW_V | PSW_C);
2259 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2260
2261 /* 32bit saturation. */
2262 if (IMM8 == 0x20)
2263 {
2264 long long tmp;
2265
2266 tmp = State.regs[REG_MCRH];
2267 tmp <<= 32;
2268 tmp += State.regs[REG_MCRL];
2269
2270 if (tmp > 0x7fffffff)
2271 State.regs[dstreg] = 0x7fffffff;
2272 else if (tmp < 0xffffffff80000000LL)
2273 State.regs[dstreg] = 0x80000000;
2274 else
2275 State.regs[dstreg] = tmp;
2276 }
2277 /* 16bit saturation */
2278 else if (IMM8 == 0x10)
2279 {
2280 long long tmp;
2281
2282 tmp = State.regs[REG_MCRH];
2283 tmp <<= 32;
2284 tmp += State.regs[REG_MCRL];
2285
2286 if (tmp > 0x7fff)
2287 State.regs[dstreg] = 0x7fff;
2288 else if (tmp < 0xffffffffffff8000LL)
2289 State.regs[dstreg] = 0x8000;
2290 else
2291 State.regs[dstreg] = tmp;
2292 }
2293 /* 8 bit saturation */
2294 else if (IMM8 == 0x8)
2295 {
2296 long long tmp;
2297
2298 tmp = State.regs[REG_MCRH];
2299 tmp <<= 32;
2300 tmp += State.regs[REG_MCRL];
2301
2302 if (tmp > 0x7f)
2303 State.regs[dstreg] = 0x7f;
2304 else if (tmp < 0xffffffffffffff80LL)
2305 State.regs[dstreg] = 0x80;
2306 else
2307 State.regs[dstreg] = tmp;
2308 }
2309 /* 9 bit saturation */
2310 else if (IMM8 == 0x9)
2311 {
2312 long long tmp;
2313
2314 tmp = State.regs[REG_MCRH];
2315 tmp <<= 32;
2316 tmp += State.regs[REG_MCRL];
2317
2318 if (tmp > 0x80)
2319 State.regs[dstreg] = 0x80;
2320 else if (tmp < 0xffffffffffffff81LL)
2321 State.regs[dstreg] = 0x81;
2322 else
2323 State.regs[dstreg] = tmp;
2324 }
2325 /* 9 bit saturation */
2326 else if (IMM8 == 0x30)
2327 {
2328 long long tmp;
2329
2330 tmp = State.regs[REG_MCRH];
2331 tmp <<= 32;
2332 tmp += State.regs[REG_MCRL];
2333
2334 if (tmp > 0x7fffffffffffLL)
2335 tmp = 0x7fffffffffffLL;
2336 else if (tmp < 0xffff800000000000LL)
2337 tmp = 0xffff800000000000LL;
2338
2339 tmp >>= 16;
2340 State.regs[dstreg] = tmp;
2341 }
2342}
2343
2344// 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
23458.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2346"add"
2347*am33
2348{
2349 int z, c, n, v;
2350 unsigned long sum, source1, source2;
2351 int srcreg1, srcreg2, dstreg;
2352
2353 PC = cia;
2354 srcreg1 = translate_rreg (SD_, RM2);
2355 srcreg2 = translate_rreg (SD_, RN0);
2356 dstreg = translate_rreg (SD_, RD0);
2357
2358 source1 = State.regs[srcreg1];
2359 source2 = State.regs[srcreg2];
2360 sum = source1 + source2;
2361 State.regs[dstreg] = sum;
2362
2363 z = (sum == 0);
2364 n = (sum & 0x80000000);
2365 c = (sum < source1) || (sum < source2);
2366 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2367 && (source1 & 0x80000000) != (sum & 0x80000000));
2368
2369 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2370 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2371 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2372}
2373
2374// 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
23758.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2376"addc"
2377*am33
2378{
2379 int z, c, n, v;
2380 unsigned long sum, source1, source2;
2381 int srcreg1, srcreg2, dstreg;
2382
2383 PC = cia;
2384 srcreg1 = translate_rreg (SD_, RM2);
2385 srcreg2 = translate_rreg (SD_, RN0);
2386 dstreg = translate_rreg (SD_, RD0);
2387
2388 source1 = State.regs[srcreg1];
2389 source2 = State.regs[srcreg2];
2390 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2391 State.regs[dstreg] = sum;
2392
2393 z = ((PSW & PSW_Z) != 0) && (sum == 0);
2394 n = (sum & 0x80000000);
2395 c = (sum < source1) || (sum < source2);
2396 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2397 && (source1 & 0x80000000) != (sum & 0x80000000));
2398
2399 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2400 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2401 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2402}
2403
2404// 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
24058.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2406"sub"
2407*am33
2408{
2409 int z, c, n, v;
2410 unsigned long difference, source1, source2;
2411 int srcreg1, srcreg2, dstreg;
2412
2413 PC = cia;
2414 srcreg1 = translate_rreg (SD_, RM2);
2415 srcreg2 = translate_rreg (SD_, RN0);
2416 dstreg = translate_rreg (SD_, RD0);
2417
2418 source1 = State.regs[srcreg1];
2419 source2 = State.regs[srcreg2];
2420 difference = source2 - source1;
2421 State.regs[dstreg] = difference;
2422
2423 z = (difference == 0);
2424 n = (difference & 0x80000000);
2425 c = (source1 > source1);
2426 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2427 && (source1 & 0x80000000) != (difference & 0x80000000));
2428
2429 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2430 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2431 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2432}
2433
2434// 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
24358.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2436"subc"
2437*am33
2438{
2439 int z, c, n, v;
2440 unsigned long difference, source1, source2;
2441 int srcreg1, srcreg2, dstreg;
2442
2443 PC = cia;
2444 srcreg1 = translate_rreg (SD_, RM2);
2445 srcreg2 = translate_rreg (SD_, RN0);
2446 dstreg = translate_rreg (SD_, RD0);
2447
2448 source1 = State.regs[srcreg1];
2449 source2 = State.regs[srcreg2];
2450 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2451 State.regs[dstreg] = difference;
2452
2453 z = ((PSW & PSW_Z) != 0) && (difference == 0);
2454 n = (difference & 0x80000000);
2455 c = (source1 > source2);
2456 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2457 && (source1 & 0x80000000) != (difference & 0x80000000));
2458
2459 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2460 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2461 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2462}
2463
2464// 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
24658.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2466"and"
2467*am33
2468{
2469 int z, n;
2470 int srcreg1, srcreg2, dstreg;
2471
2472 PC = cia;
2473 srcreg1 = translate_rreg (SD_, RM2);
2474 srcreg2 = translate_rreg (SD_, RN0);
2475 dstreg = translate_rreg (SD_, RD0);
2476
2477 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2478
2479 z = (State.regs[dstreg] == 0);
2480 n = (State.regs[dstreg] & 0x80000000);
2481
2482 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2483 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2484}
2485
2486// 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
24878.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2488"or"
2489*am33
2490{
2491 int z, n;
2492 int srcreg1, srcreg2, dstreg;
2493
2494 PC = cia;
2495 srcreg1 = translate_rreg (SD_, RM2);
2496 srcreg2 = translate_rreg (SD_, RN0);
2497 dstreg = translate_rreg (SD_, RD0);
2498
2499 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2500
2501 z = (State.regs[dstreg] == 0);
2502 n = (State.regs[dstreg] & 0x80000000);
2503
2504 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2505 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2506}
2507
2508// 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
25098.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2510"xor"
2511*am33
2512{
2513 int z, n;
2514 int srcreg1, srcreg2, dstreg;
2515
2516 PC = cia;
2517 srcreg1 = translate_rreg (SD_, RM2);
2518 srcreg2 = translate_rreg (SD_, RN0);
2519 dstreg = translate_rreg (SD_, RD0);
2520
2521 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2522
2523 z = (State.regs[dstreg] == 0);
2524 n = (State.regs[dstreg] & 0x80000000);
2525
2526 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2527 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2528}
2529
2530// 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
25318.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2532"asr"
2533*am33
2534{
2535 int z, c, n;
2536 long temp;
2537 int srcreg1, srcreg2, dstreg;
2538
2539 PC = cia;
2540 srcreg1 = translate_rreg (SD_, RM2);
2541 srcreg2 = translate_rreg (SD_, RN0);
2542 dstreg = translate_rreg (SD_, RD0);
2543
2544 temp = State.regs[srcreg2];
2545 c = temp & 1;
2546 temp >>= State.regs[srcreg1];
2547 State.regs[dstreg] = temp;
2548
2549 z = (State.regs[dstreg] == 0);
2550 n = (State.regs[dstreg] & 0x80000000);
2551
2552 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2553 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2554}
2555
2556// 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
25578.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2558"lsr"
2559*am33
2560{
2561 int z, c, n;
2562 int srcreg1, srcreg2, dstreg;
2563
2564 PC = cia;
2565 srcreg1 = translate_rreg (SD_, RM2);
2566 srcreg2 = translate_rreg (SD_, RN0);
2567 dstreg = translate_rreg (SD_, RD0);
2568
2569 c = State.regs[srcreg2] & 1;
2570 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2571
2572 z = (State.regs[dstreg] == 0);
2573 n = (State.regs[dstreg] & 0x80000000);
2574
2575 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2576 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2577}
2578
2579// 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
25808.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2581"asl"
2582*am33
2583{
2584 int z, n;
2585 int srcreg1, srcreg2, dstreg;
2586
2587 PC = cia;
2588 srcreg1 = translate_rreg (SD_, RM2);
2589 srcreg2 = translate_rreg (SD_, RN0);
2590 dstreg = translate_rreg (SD_, RD0);
2591
2592 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];
2593
2594 z = (State.regs[dstreg] == 0);
2595 n = (State.regs[dstreg] & 0x80000000);
2596
2597 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2598 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2599}
2600
2601// 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
26028.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
2603"mul"
2604*am33
2605{
2606 int srcreg1, srcreg2, dstreg1, dstreg2;
2607 signed long long temp;
2608 int n, z;
2609
2610 PC = cia;
2611 srcreg1 = translate_rreg (SD_, RM2);
2612 srcreg2 = translate_rreg (SD_, RN0);
2613 dstreg1 = translate_rreg (SD_, RD0);
2614 dstreg2 = translate_rreg (SD_, RD2);
2615
2616 temp = ((signed64)(signed32)State.regs[srcreg1]
2617 * (signed64)(signed32)State.regs[srcreg2]);
2618 State.regs[dstreg2] = temp & 0xffffffff;
2619 State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
2620
2621 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2622 n = (State.regs[dstreg1] & 0x80000000);
2623
2624 PSW &= ~(PSW_Z | PSW_N);
2625 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2626}
2627
2628// 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
26298.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
2630"mulu"
2631*am33
2632{
2633 int srcreg1, srcreg2, dstreg1, dstreg2;
2634 signed long long temp;
2635 int n, z;
2636
2637 PC = cia;
2638 srcreg1 = translate_rreg (SD_, RM2);
2639 srcreg2 = translate_rreg (SD_, RN0);
2640 dstreg1 = translate_rreg (SD_, RD0);
2641 dstreg2 = translate_rreg (SD_, RD2);
2642
2643 temp = ((unsigned64)State.regs[srcreg1]
2644 * (unsigned64)State.regs[srcreg2]);
2645 State.regs[dstreg2] = temp & 0xffffffff;
2646 State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
2647
2648 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2649 n = (State.regs[dstreg1] & 0x80000000);
2650
2651 PSW &= ~(PSW_Z | PSW_N);
2652 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2653}
2654
2655// 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
26568.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2657"mov"
2658*am33
2659{
2660 int dstreg;
2661
2662 PC = cia;
2663 dstreg = translate_rreg (SD_, RN2);
2664 State.regs[dstreg] = load_word (IMM8);
2665}
2666
2667// 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
26688.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2669"mov"
2670*am33
2671{
2672 int srcreg;
2673
2674 PC = cia;
2675 srcreg = translate_rreg (SD_, RM2);
2676 store_word (IMM8, State.regs[srcreg]);
2677}
2678
2679// 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
26808.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2681"movbu"
2682*am33
2683{
2684 int dstreg;
2685
2686 PC = cia;
2687 dstreg = translate_rreg (SD_, RN2);
2688 State.regs[dstreg] = load_byte (IMM8);
2689}
2690
2691// 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
26928.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2693"movbu"
2694*am33
2695{
2696 int srcreg;
2697
2698 PC = cia;
2699 srcreg = translate_rreg (SD_, RM2);
2700 store_byte (IMM8, State.regs[srcreg]);
2701}
2702
2703// 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
27048.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2705"movhu"
2706*am33
2707{
2708 int dstreg;
2709
2710 PC = cia;
2711 dstreg = translate_rreg (SD_, RN2);
2712 State.regs[dstreg] = load_half (IMM8);
2713}
2714
2715// 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
27168.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2717"movhu"
2718*am33
2719{
2720 int srcreg;
2721
2722 PC = cia;
2723 srcreg = translate_rreg (SD_, RM2);
2724 store_half (IMM8, State.regs[srcreg]);
2725}
2726
2727// 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
27288.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2729"mov"
2730*am33
2731{
2732 int srcreg1, srcreg2, dstreg;
2733
2734 PC = cia;
2735 srcreg1 = translate_rreg (SD_, RM0);
2736 srcreg1 = translate_rreg (SD_, RI0);
2737 dstreg = translate_rreg (SD_, RN0);
2738 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
2739}
2740
2741// 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
27428.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2743"mov"
2744*am33
2745{
2746 int srcreg, dstreg1, dstreg2;
2747
2748 PC = cia;
2749 srcreg = translate_rreg (SD_, RM0);
2750 dstreg1 = translate_rreg (SD_, RI0);
2751 dstreg2 = translate_rreg (SD_, RN0);
2752 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2753}
2754
2755// 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
27568.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2757"movbu"
2758*am33
2759{
2760 int srcreg1, srcreg2, dstreg;
2761
2762 PC = cia;
2763 srcreg1 = translate_rreg (SD_, RM0);
2764 srcreg1 = translate_rreg (SD_, RI0);
2765 dstreg = translate_rreg (SD_, RN0);
2766 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
2767}
2768
2769// 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
27708.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2771"movbu"
2772*am33
2773{
2774 int srcreg, dstreg1, dstreg2;
2775
2776 PC = cia;
2777 srcreg = translate_rreg (SD_, RM0);
2778 dstreg1 = translate_rreg (SD_, RI0);
2779 dstreg2 = translate_rreg (SD_, RN0);
2780 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2781}
2782
2783// 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
27848.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2785"movhu"
2786*am33
2787{
2788 int srcreg1, srcreg2, dstreg;
2789
2790 PC = cia;
2791 srcreg1 = translate_rreg (SD_, RM0);
2792 srcreg1 = translate_rreg (SD_, RI0);
2793 dstreg = translate_rreg (SD_, RN0);
2794 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2795}
2796
2797// 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
27988.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2799"movhu"
2800*am33
2801{
2802 int srcreg, dstreg1, dstreg2;
2803
2804 PC = cia;
2805 srcreg = translate_rreg (SD_, RM0);
2806 dstreg1 = translate_rreg (SD_, RI0);
2807 dstreg2 = translate_rreg (SD_, RN0);
2808 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2809}
2810
2811// 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
28128.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
2813"mac"
2814*am33
2815{
2816 int srcreg1, srcreg2, dstreg1, dstreg2;
2817 signed long long temp;
2818 unsigned long sum;
2819 int c, v;
2820
2821 PC = cia;
2822 srcreg1 = translate_rreg (SD_, RM2);
2823 srcreg2 = translate_rreg (SD_, RN0);
2824 dstreg1 = translate_rreg (SD_, RD0);
2825 dstreg2 = translate_rreg (SD_, RD2);
2826
2827 temp = ((signed64)(signed32)State.regs[srcreg1]
2828 * (signed64)(signed32)State.regs[srcreg2]);
2829
2830 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2831 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2832 State.regs[dstreg2] = sum;
2833 temp >>= 32;
2834 temp &= 0xffffffff;
2835 sum = State.regs[dstreg1] + temp + c;
2836 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2837 && (temp & 0x80000000) != (sum & 0x80000000));
2838 State.regs[dstreg1] = sum;
2839 if (v)
2840 {
2841 State.regs[REG_MCVF] = 1;
2842 PSW &= ~(PSW_V);
2843 PSW |= (( v ? PSW_V : 0));
2844 }
2845}
2846
2847// 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
28488.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
2849"macu"
2850*am33
2851{
2852 int srcreg1, srcreg2, dstreg1, dstreg2;
2853 signed long long temp;
2854 unsigned long sum;
2855 int c, v;
2856
2857 PC = cia;
2858 srcreg1 = translate_rreg (SD_, RM2);
2859 srcreg2 = translate_rreg (SD_, RN0);
2860 dstreg1 = translate_rreg (SD_, RD0);
2861 dstreg2 = translate_rreg (SD_, RD2);
2862
2863 temp = ((unsigned64)State.regs[srcreg1]
2864 * (unsigned64)State.regs[srcreg2]);
2865
2866 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2867 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2868 State.regs[dstreg2] = sum;
2869 temp >>= 32;
2870 temp &= 0xffffffff;
2871 sum = State.regs[dstreg1] + temp + c;
2872 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2873 && (temp & 0x80000000) != (sum & 0x80000000));
2874 State.regs[dstreg1] = sum;
2875 if (v)
2876 {
2877 State.regs[REG_MCVF] = 1;
2878 PSW &= ~(PSW_V);
2879 PSW |= (( v ? PSW_V : 0));
2880 }
2881}
2882
2883// 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
28848.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2885"macb"
2886*am33
2887{
2888 int srcreg1, srcreg2, dstreg;
2889 long temp, sum;
2890 int v;
2891
2892 PC = cia;
2893 srcreg1 = translate_rreg (SD_, RM2);
2894 srcreg2 = translate_rreg (SD_, RN0);
2895 dstreg = translate_rreg (SD_, RD0);
2896
2897 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2898 * (signed32)(State.regs[srcreg1] & 0xff));
2899 sum = State.regs[dstreg] + temp;
2900 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2901 && (temp & 0x80000000) != (sum & 0x80000000));
2902 State.regs[dstreg] = sum;
2903 if (v)
2904 {
2905 State.regs[REG_MCVF] = 1;
2906 PSW &= ~(PSW_V);
2907 PSW |= ((v ? PSW_V : 0));
2908 }
2909}
2910
2911// 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
29128.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2913"macbu"
2914*am33
2915{
2916 int srcreg1, srcreg2, dstreg;
2917 long temp, sum;
2918 int v;
2919
2920 PC = cia;
2921 srcreg1 = translate_rreg (SD_, RM2);
2922 srcreg2 = translate_rreg (SD_, RN0);
2923 dstreg = translate_rreg (SD_, RD0);
2924
2925 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2926 * (unsigned32)(State.regs[srcreg1] & 0xff));
2927 sum = State.regs[dstreg] + temp;
2928 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2929 && (temp & 0x80000000) != (sum & 0x80000000));
2930 State.regs[dstreg] = sum;
2931 if (v)
2932 {
2933 State.regs[REG_MCVF] = 1;
2934 PSW &= ~(PSW_V);
2935 PSW |= ((v ? PSW_V : 0));
2936 }
2937}
2938
2939// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2
29408.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
2941"mach"
2942*am33
2943{
2944 int srcreg1, srcreg2, dstreg1, dstreg2;
2945 long long temp, sum;
2946 int v;
2947
2948 PC = cia;
2949 srcreg1 = translate_rreg (SD_, RM2);
2950 srcreg2 = translate_rreg (SD_, RN0);
2951 dstreg1 = translate_rreg (SD_, RD0);
2952 dstreg2 = translate_rreg (SD_, RD0);
2953
2954 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2955 * (signed32)(State.regs[srcreg1] & 0xffff));
2956 State.regs[dstreg2] += (temp & 0xffffffff);
2957 sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
2958 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2959 && (temp & 0x80000000) != (sum & 0x80000000));
2960 State.regs[dstreg1] = sum;
2961 if (v)
2962 {
2963 State.regs[REG_MCVF] = 1;
2964 PSW &= ~(PSW_V);
2965 PSW |= ((v ? PSW_V : 0));
2966 }
2967}
2968
2969// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2
29708.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
2971"machu"
2972*am33
2973{
2974 int srcreg1, srcreg2, dstreg1, dstreg2;
2975 long long temp, sum;
2976 int v;
2977
2978 PC = cia;
2979 srcreg1 = translate_rreg (SD_, RM2);
2980 srcreg2 = translate_rreg (SD_, RN0);
2981 dstreg1 = translate_rreg (SD_, RD0);
2982 dstreg2 = translate_rreg (SD_, RD0);
2983
2984 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2985 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2986 State.regs[dstreg2] += (temp & 0xffffffff);
2987 sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
2988 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2989 && (temp & 0x80000000) != (sum & 0x80000000));
2990 State.regs[dstreg1] = sum;
2991 if (v)
2992 {
2993 State.regs[REG_MCVF] = 1;
2994 PSW &= ~(PSW_V);
2995 PSW |= ((v ? PSW_V : 0));
2996 }
2997}
2998
2999// 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
30008.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
3001"dmach"
3002*am33
3003{
3004 int srcreg1, srcreg2, dstreg;
3005 long temp, temp2, sum;
3006 int v;
3007
3008 PC = cia;
3009 srcreg1 = translate_rreg (SD_, RM2);
3010 srcreg2 = translate_rreg (SD_, RN0);
3011 dstreg = translate_rreg (SD_, RD0);
3012
3013 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
3014 * (signed32)(State.regs[srcreg1] & 0xffff));
3015 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3016 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
3017 sum = temp + temp2 + State.regs[dstreg];
3018 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3019 && (temp & 0x80000000) != (sum & 0x80000000));
3020 State.regs[dstreg] = sum;
3021 if (v)
3022 {
3023 State.regs[REG_MCVF] = 1;
3024 PSW &= ~(PSW_V);
3025 PSW |= ((v ? PSW_V : 0));
3026 }
3027}
3028
3029// 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
30308.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
3031"dmachu"
3032*am33
3033{
3034 int srcreg1, srcreg2, dstreg;
3035 long temp, temp2, sum;
3036 int v;
3037
3038 PC = cia;
3039 srcreg1 = translate_rreg (SD_, RM2);
3040 srcreg2 = translate_rreg (SD_, RN0);
3041 dstreg = translate_rreg (SD_, RD0);
3042
3043 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3044 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3045 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3046 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
3047 sum = temp + temp2 + State.regs[dstreg];
3048 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3049 && (temp & 0x80000000) != (sum & 0x80000000));
3050 State.regs[dstreg] = sum;
3051 if (v)
3052 {
3053 State.regs[REG_MCVF] = 1;
3054 PSW &= ~(PSW_V);
3055 PSW |= ((v ? PSW_V : 0));
3056 }
3057}
3058
3059// 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
30608.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
3061"dmulh"
3062*am33
3063{
3064 int srcreg1, srcreg2, dstreg1, dstreg2;
3065 signed long long temp;
3066
3067 PC = cia;
3068 srcreg1 = translate_rreg (SD_, RM2);
3069 srcreg2 = translate_rreg (SD_, RN0);
3070 dstreg1 = translate_rreg (SD_, RD0);
3071 dstreg2 = translate_rreg (SD_, RD2);
3072
3073 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3074 * (signed32)(State.regs[srcreg1] & 0xffff));
3075 State.regs[dstreg2] = temp;
3076 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3077 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3078 State.regs[dstreg1] = temp;
3079}
3080
3081// 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
30828.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
3083"dmulhu"
3084*am33
3085{
3086 int srcreg1, srcreg2, dstreg1, dstreg2;
3087 signed long long temp;
3088
3089 PC = cia;
3090 srcreg1 = translate_rreg (SD_, RM2);
3091 srcreg2 = translate_rreg (SD_, RN0);
3092 dstreg1 = translate_rreg (SD_, RD0);
3093 dstreg2 = translate_rreg (SD_, RD2);
3094
3095 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3096 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3097 State.regs[dstreg2] = temp;
3098 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3099 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3100 State.regs[dstreg1] = temp;
3101}
3102
3103// 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
31048.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3105"sat24"
3106*am33
3107{
3108 int srcreg, dstreg;
3109 int value, n, z;
3110
3111 PC = cia;
3112 srcreg = translate_rreg (SD_, RM2);
3113 dstreg = translate_rreg (SD_, RN0);
3114
3115 value = State.regs[srcreg];
3116
3117 if (value >= 0x7fffff)
3118 State.regs[dstreg] = 0x7fffff;
3119 else if (value <= 0xff800000)
3120 State.regs[dstreg] = 0xff800000;
3121 else
3122 State.regs[dstreg] = value;
3123
3124 n = (State.regs[dstreg] & 0x800000) != 0;
3125 z = (State.regs[dstreg] == 0);
3126 PSW &= ~(PSW_Z | PSW_N);
3127 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3128}
3129
3130// 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
31318.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3132"bsch"
3133*am33
3134{
3135 int temp, c, i;
3136 int srcreg1, srcreg2, dstreg;
3137 int start;
3138
3139 PC = cia;
3140 srcreg1 = translate_rreg (SD_, RM2);
3141 srcreg2 = translate_rreg (SD_, RN0);
3142 dstreg = translate_rreg (SD_, RD0);
3143
3144 temp = State.regs[srcreg1];
3145 start = (State.regs[srcreg2] & 0x1f) - 1;
3146 if (start == -1)
3147 start = 31;
3148
3149 for (i = start; i >= 0; i--)
3150 {
3151 if (temp & (1 << i))
3152 {
3153 c = 1;
3154 State.regs[dstreg] = i;
3155 break;
3156 }
3157 }
3158
3159 if (i < 0)
3160 {
3161 c = 0;
3162 State.regs[dstreg] = 0;
3163 }
3164 PSW &= ~(PSW_C);
3165 PSW |= (c ? PSW_C : 0);
3166}
3167
3168// 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
31698.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3170"mov"
3171*am33
3172{
3173 int dstreg;
3174
3175 PC = cia;
3176 dstreg = translate_rreg (SD_, RN0);
3177 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3178}
3179
3180// 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
31818.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3182"movu"
3183*am33
3184{
3185 int dstreg;
3186
3187 PC = cia;
3188 dstreg = translate_rreg (SD_, RN0);
3189 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3190}
3191
3192// 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
31938.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3194"add"
3195*am33
3196{
3197 int dstreg;
3198
3199 PC = cia;
3200 dstreg = translate_rreg (SD_, RN0);
3201 genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3202}
3203
3204// 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
32058.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3206"addc"
3207*am33
3208{
3209 int dstreg, z, n, c, v;
3210 unsigned long sum, imm, reg2;
3211
3212 PC = cia;
3213 dstreg = translate_rreg (SD_, RN0);
3214
3215 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3216 reg2 = State.regs[dstreg];
3217 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3218 State.regs[dstreg] = sum;
3219
3220 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3221 n = (sum & 0x80000000);
3222 c = (sum < imm) || (sum < reg2);
3223 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3224 && (reg2 & 0x80000000) != (sum & 0x80000000));
3225
3226 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3227 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3228 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3229}
3230
3231// 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
32328.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3233"sub"
3234*am33
3235{
3236 int dstreg;
3237
3238 PC = cia;
3239 dstreg = translate_rreg (SD_, RN0);
3240 genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3241}
3242
3243// 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
32448.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3245"subc"
3246*am33
3247{
3248 int dstreg, z, n, c, v;
3249 unsigned long difference, imm, reg2;
3250
3251 PC = cia;
3252 dstreg = translate_rreg (SD_, RN0);
3253
3254 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3255 reg2 = State.regs[dstreg];
3256 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3257 State.regs[dstreg] = difference;
3258
3259 z = ((PSW & PSW_Z) != 0) && (difference == 0);
3260 n = (difference & 0x80000000);
3261 c = (imm > reg2);
3262 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3263 && (reg2 & 0x80000000) != (difference & 0x80000000));
3264
3265 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3266 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3267 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3268}
3269
3270// 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
32718.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3272"cmp"
3273*am33
3274{
3275 int srcreg;
3276
3277 PC = cia;
3278 srcreg = translate_rreg (SD_, RN0);
3279 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3280}
3281
3282// 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
32838.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3284"mov"
3285*am33
3286{
3287 int dstreg;
3288
3289 PC = cia;
3290 dstreg = translate_xreg (SD_, XRN0);
3291
3292 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3293}
3294
3295// 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
32968.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3297"and"
3298*am33
3299{
3300 int dstreg;
3301 int z,n;
3302
3303 PC = cia;
3304 dstreg = translate_rreg (SD_, RN0);
3305
3306 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3307 z = (State.regs[dstreg] == 0);
3308 n = (State.regs[dstreg] & 0x80000000) != 0;
3309 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3310 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3311}
3312
3313// 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
33148.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3315"or"
3316*am33
3317{
3318 int dstreg;
3319 int z,n;
3320
3321 PC = cia;
3322 dstreg = translate_rreg (SD_, RN0);
3323
3324 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3325 z = (State.regs[dstreg] == 0);
3326 n = (State.regs[dstreg] & 0x80000000) != 0;
3327 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3328 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3329}
3330
3331// 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
33328.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3333"xor"
3334*am33
3335{
3336 int dstreg;
3337 int z,n;
3338
3339 PC = cia;
3340 dstreg = translate_rreg (SD_, RN0);
3341
3342 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3343 z = (State.regs[dstreg] == 0);
3344 n = (State.regs[dstreg] & 0x80000000) != 0;
3345 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3346 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3347}
3348
3349// 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
33508.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3351"asr"
3352*am33
3353{
3354 int dstreg;
3355 long temp;
3356 int c, z, n;
3357
3358 PC = cia;
3359 dstreg = translate_rreg (SD_, RN0);
3360
3361 temp = State.regs[dstreg];
3362 c = temp & 1;
3363 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3364 State.regs[dstreg] = temp;
3365 z = (State.regs[dstreg] == 0);
3366 n = (State.regs[dstreg] & 0x80000000) != 0;
3367 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3368 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3369}
3370
3371
3372// 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
33738.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3374"lsr"
3375*am33
3376{
3377 int dstreg;
3378 int z, n, c;
3379
3380 PC = cia;
3381 dstreg = translate_rreg (SD_, RN0);
3382
3383 c = State.regs[dstreg] & 1;
3384 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3385 z = (State.regs[dstreg] == 0);
3386 n = (State.regs[dstreg] & 0x80000000) != 0;
3387 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3388 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3389}
3390
3391// 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
33928.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3393"asl"
3394*am33
3395{
3396 int srcreg, dstreg;
3397 int z, n;
3398
3399 PC = cia;
3400 dstreg = translate_rreg (SD_, RN0);
3401
3402 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3403 z = (State.regs[dstreg] == 0);
3404 n = (State.regs[dstreg] & 0x80000000) != 0;
3405 PSW &= ~(PSW_Z | PSW_N);
3406 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3407}
3408
3409// 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
34108.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3411"mul"
3412*am33
3413{
3414 int dstreg;
3415 unsigned long long temp;
3416 int z, n;
3417
3418 PC = cia;
3419 dstreg = translate_rreg (SD_, RN0);
3420
3421 temp = ((signed64)(signed32)State.regs[dstreg]
3422 * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3423 State.regs[dstreg] = temp & 0xffffffff;
3424 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
3425 z = (State.regs[dstreg] == 0);
3426 n = (State.regs[dstreg] & 0x80000000) != 0;
3427 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3428 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3429}
3430
3431// 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
34328.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3433"mulu"
3434*am33
3435{
3436 int dstreg;
3437 unsigned long long temp;
3438 int z, n;
3439
3440 PC = cia;
3441 dstreg = translate_rreg (SD_, RN0);
3442
3443 temp = ((unsigned64)State.regs[dstreg]
3444 * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3445 State.regs[dstreg] = temp & 0xffffffff;
3446 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
3447 z = (State.regs[dstreg] == 0);
3448 n = (State.regs[dstreg] & 0x80000000) != 0;
3449 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3450 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3451}
3452
3453// 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
34548.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3455"btst"
3456*am33
3457{
3458 int srcreg;
3459
3460 PC = cia;
3461 srcreg = translate_rreg (SD_, RN0);
3462 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3463}
3464
3465// 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
34668.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3467"mov"
3468*am33
3469{
3470 int srcreg, dstreg;
3471
3472 PC = cia;
3473 srcreg = translate_rreg (SD_, RM0);
3474 dstreg = translate_rreg (SD_, RN2);
3475 State.regs[dstreg] = load_word (State.regs[srcreg]
3476 + EXTEND24 (FETCH24 (IMM24A,
3477 IMM24B, IMM24C)));
3478}
3479
3480// 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
34818.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3482"mov"
3483*am33
3484{
3485 int srcreg, dstreg;
3486
3487 PC = cia;
3488 srcreg = translate_rreg (SD_, RM2);
3489 dstreg = translate_rreg (SD_, RN0);
3490 store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3491 State.regs[srcreg]);
3492}
3493
3494// 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
34958.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3496"movbu"
3497*am33
3498{
3499 int srcreg, dstreg;
3500
3501 PC = cia;
3502 srcreg = translate_rreg (SD_, RM0);
3503 dstreg = translate_rreg (SD_, RN2);
3504 State.regs[dstreg] = load_byte (State.regs[srcreg]
3505 + EXTEND24 (FETCH24 (IMM24A,
3506 IMM24B, IMM24C)));
3507}
3508
3509// 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
35108.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3511"movbu"
3512*am33
3513{
3514 int srcreg, dstreg;
3515
3516 PC = cia;
3517 srcreg = translate_rreg (SD_, RM2);
3518 dstreg = translate_rreg (SD_, RN0);
3519 store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3520 State.regs[srcreg]);
3521}
3522
3523// 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
35248.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3525"movhu"
3526*am33
3527{
3528 int srcreg, dstreg;
3529
3530 PC = cia;
3531 srcreg = translate_rreg (SD_, RM0);
3532 dstreg = translate_rreg (SD_, RN2);
3533 State.regs[dstreg] = load_half (State.regs[srcreg]
3534 + EXTEND24 (FETCH24 (IMM24A,
3535 IMM24B, IMM24C)));
3536}
3537
3538// 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
35398.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3540"movhu"
3541*am33
3542{
3543 int srcreg, dstreg;
3544
3545 PC = cia;
3546 srcreg = translate_rreg (SD_, RM2);
3547 dstreg = translate_rreg (SD_, RN0);
3548 store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3549 State.regs[srcreg]);
3550}
3551
3552// 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
35538.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3554"mov"
3555*am33
3556{
3557 int srcreg, dstreg;
3558
3559 PC = cia;
3560 srcreg = translate_rreg (SD_, RM0);
3561 dstreg = translate_rreg (SD_, RN2);
3562 State.regs[dstreg] = load_word (State.regs[srcreg]);
3563 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3564}
3565
3566// 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
35678.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3568"mov"
3569*am33
3570{
3571 int srcreg, dstreg;
3572
3573 PC = cia;
3574 srcreg = translate_rreg (SD_, RM2);
3575 dstreg = translate_rreg (SD_, RN0);
3576 store_word (State.regs[dstreg], State.regs[srcreg]);
3577 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3578}
3579
3580
3581// 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
35828.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3583"mov"
3584*am33
3585{
3586 int dstreg;
3587
3588 PC = cia;
3589 dstreg = translate_rreg (SD_, RN2);
3590 State.regs[dstreg] = load_word (State.regs[REG_SP]
3591 + EXTEND24 (FETCH24 (IMM24A,
3592 IMM24B, IMM24C)));
3593}
3594
3595// 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
35968.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3597"mov"
3598*am33
3599{
3600 int srcreg;
3601
3602 PC = cia;
3603 srcreg = translate_rreg (SD_, RM2);
3604 store_word (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3605 State.regs[srcreg]);
3606}
3607
3608// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
36098.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3610"movbu"
3611*am33
3612{
3613 int dstreg;
3614
3615 PC = cia;
3616 dstreg = translate_rreg (SD_, RN2);
3617 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3618 + EXTEND24 (FETCH24 (IMM24A,
3619 IMM24B, IMM24C)));
3620}
3621
3622// 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
36238.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3624"movbu"
3625*am33
3626{
3627 int srcreg;
3628
3629 PC = cia;
3630 srcreg = translate_rreg (SD_, RM2);
3631 store_byte (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3632 State.regs[srcreg]);
3633}
3634
3635// 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
36368.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3637"movhu"
3638*am33
3639{
3640 int dstreg;
3641
3642 PC = cia;
3643 dstreg = translate_rreg (SD_, RN2);
3644 State.regs[dstreg] = load_half (State.regs[REG_SP]
3645 + EXTEND24 (FETCH24 (IMM24A,
3646 IMM24B, IMM24C)));
3647}
3648
3649// 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
36508.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3651"movhu"
3652*am33
3653{
3654 int srcreg;
3655
3656 PC = cia;
3657 srcreg = translate_rreg (SD_, RM2);
3658 store_half (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3659 State.regs[srcreg]);
3660}
3661
3662// 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
36638.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3664"movhu"
3665*am33
3666{
3667 int srcreg, dstreg;
3668
3669 PC = cia;
3670 srcreg = translate_rreg (SD_, RM0);
3671 dstreg = translate_rreg (SD_, RN2);
3672 State.regs[dstreg] = load_half (State.regs[srcreg]);
3673 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3674}
3675
3676// 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
36778.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3678"movhu"
3679*am33
3680{
3681 int srcreg, dstreg;
3682
3683 PC = cia;
3684 srcreg = translate_rreg (SD_, RM2);
3685 dstreg = translate_rreg (SD_, RN0);
3686 store_half (State.regs[dstreg], State.regs[srcreg]);
3687 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3688}
3689
3690// 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
36918.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3692"mac"
3693*am33
3694{
3695 int srcreg;
3696 long long temp, sum;
3697 int c, v;
3698
3699 PC = cia;
3700 srcreg = translate_rreg (SD_, RN2);
3701
3702 temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
3703 * (signed64)State.regs[srcreg]);
3704 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3705 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3706 State.regs[REG_MCRL] = sum;
3707 temp >>= 32;
3708 temp &= 0xffffffff;
3709 sum = State.regs[REG_MCRH] + temp + c;
3710 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3711 && (temp & 0x80000000) != (sum & 0x80000000));
3712 State.regs[REG_MCRH] = sum;
3713 if (v)
3714 State.regs[REG_MCVF] = 1;
3715}
3716
3717// 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
37188.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3719"macu"
3720*am33
3721{
3722 int srcreg;
3723 long long temp, sum;
3724 int c, v;
3725
3726 PC = cia;
3727 srcreg = translate_rreg (SD_, RN2);
3728
3729 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3730 * (unsigned64)State.regs[srcreg]);
3731 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3732 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3733 State.regs[REG_MCRL] = sum;
3734 temp >>= 32;
3735 temp &= 0xffffffff;
3736 sum = State.regs[REG_MCRH] + temp + c;
3737 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3738 && (temp & 0x80000000) != (sum & 0x80000000));
3739 State.regs[REG_MCRH] = sum;
3740 if (v)
3741 State.regs[REG_MCVF] = 1;
3742}
3743
3744// 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
37458.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3746"macb"
3747*am33
3748{
3749 int srcreg;
3750 long long temp, sum;
3751 int c, v;
3752
3753 PC = cia;
3754 srcreg = translate_rreg (SD_, RN2);
3755
3756 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3757 * (signed64)State.regs[srcreg] & 0xff);
3758 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3759 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3760 State.regs[REG_MCRL] = sum;
3761 temp >>= 32;
3762 temp &= 0xffffffff;
3763 sum = State.regs[REG_MCRH] + temp + c;
3764 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3765 && (temp & 0x80000000) != (sum & 0x80000000));
3766 State.regs[REG_MCRH] = sum;
3767 if (v)
3768 State.regs[REG_MCVF] = 1;
3769}
3770
3771// 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
37728.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3773"macbu"
3774*am33
3775{
3776 int srcreg;
3777 long long temp, sum;
3778 int c, v;
3779
3780 PC = cia;
3781 srcreg = translate_rreg (SD_, RN2);
3782
3783 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3784 * (unsigned64)State.regs[srcreg] & 0xff);
3785 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3786 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3787 State.regs[REG_MCRL] = sum;
3788 temp >>= 32;
3789 temp &= 0xffffffff;
3790 sum = State.regs[REG_MCRH] + temp + c;
3791 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3792 && (temp & 0x80000000) != (sum & 0x80000000));
3793 State.regs[REG_MCRH] = sum;
3794 if (v)
3795 State.regs[REG_MCVF] = 1;
3796}
3797
3798// 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
37998.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3800"mach"
3801*am33
3802{
3803 int srcreg;
3804 long long temp, sum;
3805 int c, v;
3806
3807 PC = cia;
3808 srcreg = translate_rreg (SD_, RN2);
3809
3810 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3811 * (signed64)State.regs[srcreg] & 0xffff);
3812 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3813 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3814 State.regs[REG_MCRL] = sum;
3815 temp >>= 32;
3816 temp &= 0xffffffff;
3817 sum = State.regs[REG_MCRH] + temp + c;
3818 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3819 && (temp & 0x80000000) != (sum & 0x80000000));
3820 State.regs[REG_MCRH] = sum;
3821 if (v)
3822 State.regs[REG_MCVF] = 1;
3823}
3824
3825// 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
38268.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3827"machu"
3828*am33
3829{
3830 int srcreg;
3831 long long temp, sum;
3832 int c, v;
3833
3834 PC = cia;
3835 srcreg = translate_rreg (SD_, RN2);
3836
3837 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3838 * (unsigned64)State.regs[srcreg] & 0xffff);
3839 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3840 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3841 State.regs[REG_MCRL] = sum;
3842 temp >>= 32;
3843 temp &= 0xffffffff;
3844 sum = State.regs[REG_MCRH] + temp + c;
3845 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3846 && (temp & 0x80000000) != (sum & 0x80000000));
3847 State.regs[REG_MCRH] = sum;
3848 if (v)
3849 State.regs[REG_MCVF] = 1;
3850}
3851
3852// 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
38538.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3854"mov"
3855*am33
3856{
3857 int dstreg;
3858
3859 PC = cia;
3860 dstreg = translate_rreg (SD_, RN2);
3861 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3862}
3863
3864// 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
38658.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3866"mov"
3867*am33
3868{
3869 int srcreg;
3870
3871 PC = cia;
3872 srcreg = translate_rreg (SD_, RM2);
3873 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3874}
3875
3876
3877// 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
38788.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3879"movbu"
3880*am33
3881{
3882 int dstreg;
3883
3884 PC = cia;
3885 dstreg = translate_rreg (SD_, RN2);
3886 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3887}
3888
3889// 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
38908.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3891"movbu"
3892*am33
3893{
3894 int srcreg;
3895
3896 PC = cia;
3897 srcreg = translate_rreg (SD_, RM2);
3898 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3899}
3900
3901
3902// 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
39038.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3904"movhu"
3905*am33
3906{
3907 int dstreg;
3908
3909 PC = cia;
3910 dstreg = translate_rreg (SD_, RN2);
3911 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3912}
3913
3914// 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
39158.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3916"movhu"
3917*am33
3918{
3919 int srcreg;
3920
3921 PC = cia;
3922 srcreg = translate_rreg (SD_, RM2);
3923 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3924}
3925
3926
3927// 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
39288.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3929"mov"
3930*am33
3931{
3932 int dstreg;
3933
3934 PC = cia;
3935 dstreg = translate_rreg (SD_, RN0);
3936 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3937}
3938
3939// 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
39408.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3941"movu"
3942*am33
3943{
3944 int dstreg;
3945
3946 PC = cia;
3947 dstreg = translate_rreg (SD_, RN0);
3948 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3949}
3950
3951// 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
39528.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3953"add"
3954*am33
3955{
3956 int dstreg;
3957
3958 PC = cia;
3959 dstreg = translate_rreg (SD_, RN0);
3960 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3961}
3962
3963// 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
39648.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3965"addc"
3966*am33
3967{
3968 int dstreg;
3969 unsigned int imm, reg2, sum;
3970 int z, n, c, v;
3971
3972 PC = cia;
3973 dstreg = translate_rreg (SD_, RN0);
3974
3975 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3976 reg2 = State.regs[dstreg];
3977 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3978 State.regs[dstreg] = sum;
3979
3980 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3981 n = (sum & 0x80000000);
3982 c = (sum < imm) || (sum < reg2);
3983 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3984 && (reg2 & 0x80000000) != (sum & 0x80000000));
3985
3986 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3987 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3988 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3989}
3990
3991// 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
39928.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
3993"sub"
3994*am33
3995{
3996 int dstreg;
3997
3998 PC = cia;
3999 dstreg = translate_rreg (SD_, RN0);
4000 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
4001}
4002
4003// 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
40048.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
4005"subc"
4006*am33
4007{
4008 int dstreg;
4009 unsigned int imm, reg2, difference;
4010 int z, n, c, v;
4011
4012 PC = cia;
4013 dstreg = translate_rreg (SD_, RN0);
4014
4015 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4016 reg2 = State.regs[dstreg];
4017 difference = reg2 - imm - ((PSW & PSW_C) != 0);
4018 State.regs[dstreg] = difference;
4019
4020 z = ((PSW & PSW_Z) != 0) && (difference == 0);
4021 n = (difference & 0x80000000);
4022 c = (imm > reg2);
4023 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4024 && (reg2 & 0x80000000) != (difference & 0x80000000));
4025
4026 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4027 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4028 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4029}
4030
4031// 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
40328.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
4033"cmp"
4034*am33
4035{
4036 int srcreg;
4037
4038 PC = cia;
4039 srcreg = translate_rreg (SD_, RN0);
4040 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4041}
4042
4043// 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
40448.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
4045"mov"
4046*am33
4047{
4048 int dstreg;
4049
4050 PC = cia;
4051 dstreg = translate_xreg (SD_, XRN0);
4052
4053 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
4054}
4055
4056// 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
40578.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
4058"and"
4059*am33
4060{
4061 int dstreg;
4062 int z,n;
4063
4064 PC = cia;
4065 dstreg = translate_rreg (SD_, RN0);
4066
4067 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4068 z = (State.regs[dstreg] == 0);
4069 n = (State.regs[dstreg] & 0x80000000) != 0;
4070 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4071 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4072}
4073
4074// 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
40758.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4076"or"
4077*am33
4078{
4079 int dstreg;
4080 int z,n;
4081
4082 PC = cia;
4083 dstreg = translate_rreg (SD_, RN0);
4084
4085 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4086 z = (State.regs[dstreg] == 0);
4087 n = (State.regs[dstreg] & 0x80000000) != 0;
4088 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4089 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4090}
4091
4092// 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
40938.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4094"xor"
4095*am33
4096{
4097 int dstreg;
4098 int z,n;
4099
4100 PC = cia;
4101 dstreg = translate_rreg (SD_, RN0);
4102
4103 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4104 z = (State.regs[dstreg] == 0);
4105 n = (State.regs[dstreg] & 0x80000000) != 0;
4106 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4107 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4108}
4109
4110// 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
41118.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4112"asr"
4113*am33
4114{
4115 int dstreg;
4116 long temp;
4117 int c, z, n;
4118
4119 PC = cia;
4120 dstreg = translate_rreg (SD_, RN0);
4121
4122 temp = State.regs[dstreg];
4123 c = temp & 1;
4124 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4125 State.regs[dstreg] = temp;
4126 z = (State.regs[dstreg] == 0);
4127 n = (State.regs[dstreg] & 0x80000000) != 0;
4128 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4129 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4130}
4131
4132// 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
41338.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4134"lsr"
4135*am33
4136{
4137 int dstreg;
4138 int z, n, c;
4139
4140 PC = cia;
4141 dstreg = translate_rreg (SD_, RN0);
4142
4143 c = State.regs[dstreg] & 1;
4144 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4145 z = (State.regs[dstreg] == 0);
4146 n = (State.regs[dstreg] & 0x80000000) != 0;
4147 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4148 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4149}
4150
4151// 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
41528.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4153"asl"
4154*am33
4155{
4156 int srcreg, dstreg;
4157 int z, n;
4158
4159 PC = cia;
4160 dstreg = translate_rreg (SD_, RN0);
4161
4162 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4163 z = (State.regs[dstreg] == 0);
4164 n = (State.regs[dstreg] & 0x80000000) != 0;
4165 PSW &= ~(PSW_Z | PSW_N);
4166 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4167}
4168
4169// 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
41708.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
4171"mul"
4172*am33
4173{
4174 int dstreg;
4175 unsigned long long temp;
4176 int z, n;
4177
4178 PC = cia;
4179 dstreg = translate_rreg (SD_, RN0);
4180
4181 temp = ((signed64)(signed32)State.regs[dstreg]
4182 * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4183 State.regs[dstreg] = temp & 0xffffffff;
4184 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
4185 z = (State.regs[dstreg] == 0);
4186 n = (State.regs[dstreg] & 0x80000000) != 0;
4187 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4188 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4189}
4190
4191// 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
41928.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
4193"mulu"
4194*am33
4195{
4196 int dstreg;
4197 unsigned long long temp;
4198 int z, n;
4199
4200 PC = cia;
4201 dstreg = translate_rreg (SD_, RN0);
4202
4203 temp = ((unsigned64)State.regs[dstreg]
4204 * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4205 State.regs[dstreg] = temp & 0xffffffff;
4206 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
4207 z = (State.regs[dstreg] == 0);
4208 n = (State.regs[dstreg] & 0x80000000) != 0;
4209 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4210 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4211}
4212
4213// 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
42148.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4215"btst"
4216*am33
4217{
4218 int srcreg;
4219
4220 PC = cia;
4221 srcreg = translate_rreg (SD_, RN0);
4222 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4223}
4224
4225// 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
42268.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4227"mov"
4228*am33
4229{
4230 int srcreg, dstreg;
4231
4232 PC = cia;
4233 srcreg = translate_rreg (SD_, RM0);
4234 dstreg = translate_rreg (SD_, RN2);
4235 State.regs[dstreg] = load_word (State.regs[srcreg]
4236 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4237}
4238
4239// 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
42408.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4241"mov"
4242*am33
4243{
4244 int srcreg, dstreg;
4245
4246 PC = cia;
4247 srcreg = translate_rreg (SD_, RM2);
4248 dstreg = translate_rreg (SD_, RN0);
4249 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4250 State.regs[srcreg]);
4251}
4252
4253// 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
42548.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4255"movbu"
4256*am33
4257{
4258 int srcreg, dstreg;
4259
4260 PC = cia;
4261 srcreg = translate_rreg (SD_, RM0);
4262 dstreg = translate_rreg (SD_, RN2);
4263 State.regs[dstreg] = load_byte (State.regs[srcreg]
4264 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4265}
4266
4267// 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
42688.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4269"movbu"
4270*am33
4271{
4272 int srcreg, dstreg;
4273
4274 PC = cia;
4275 srcreg = translate_rreg (SD_, RM2);
4276 dstreg = translate_rreg (SD_, RN0);
4277 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4278 State.regs[srcreg]);
4279}
4280
4281// 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
42828.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4283"movhu"
4284*am33
4285{
4286 int srcreg, dstreg;
4287
4288 PC = cia;
4289 srcreg = translate_rreg (SD_, RM0);
4290 dstreg = translate_rreg (SD_, RN2);
4291 State.regs[dstreg] = load_half (State.regs[srcreg]
4292 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4293}
4294
4295// 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
42968.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4297"movhu"
4298*am33
4299{
4300 int srcreg, dstreg;
4301
4302 PC = cia;
4303 srcreg = translate_rreg (SD_, RM2);
4304 dstreg = translate_rreg (SD_, RN0);
4305 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4306 State.regs[srcreg]);
4307}
4308
4309// 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
43108.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4311"mov"
4312*am33
4313{
4314 int srcreg, dstreg;
4315
4316 PC = cia;
4317 srcreg = translate_rreg (SD_, RM0);
4318 dstreg = translate_rreg (SD_, RN2);
4319 State.regs[dstreg] = load_word (State.regs[srcreg]);
4320 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4321}
4322
4323// 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
43248.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4325"mov"
4326*am33
4327{
4328 int srcreg, dstreg;
4329
4330 PC = cia;
4331 srcreg = translate_rreg (SD_, RM2);
4332 dstreg = translate_rreg (SD_, RN0);
4333 store_word (State.regs[dstreg], State.regs[srcreg]);
4334 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4335}
4336
4337
4338// 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
43398.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4340"mov"
4341*am33
4342{
4343 int dstreg;
4344
4345 PC = cia;
4346 dstreg = translate_rreg (SD_, RN2);
4347 State.regs[dstreg] = load_word (State.regs[REG_SP]
4348 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4349}
4350
4351// 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
43528.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4353"mov"
4354*am33
4355{
4356 int srcreg;
4357
4358 PC = cia;
4359 srcreg = translate_rreg (SD_, RM2);
4360 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4361 State.regs[srcreg]);
4362}
4363
4364// 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
43658.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4366"movbu"
4367*am33
4368{
4369 int dstreg;
4370
4371 PC = cia;
4372 dstreg = translate_rreg (SD_, RN2);
4373 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4374 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4375}
4376
4377// 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
43788.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4379"movbu"
4380*am33
4381{
4382 int srcreg;
4383
4384 PC = cia;
4385 srcreg = translate_rreg (SD_, RM2);
4386 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4387 State.regs[srcreg]);
4388}
4389
4390// 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
43918.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4392"movhu"
4393*am33
4394{
4395 int dstreg;
4396
4397 PC = cia;
4398 dstreg = translate_rreg (SD_, RN2);
4399 State.regs[dstreg] = load_half (State.regs[REG_SP]
4400 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4401}
4402
4403// 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
44048.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4405"movhu"
4406*am33
4407{
4408 int srcreg;
4409
4410 PC = cia;
4411 srcreg = translate_rreg (SD_, RM2);
4412 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4413 State.regs[srcreg]);
4414}
4415
4416
4417// 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
44188.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4419"movhu"
4420*am33
4421{
4422 int srcreg, dstreg;
4423
4424 PC = cia;
4425 srcreg = translate_rreg (SD_, RM0);
4426 dstreg = translate_rreg (SD_, RN2);
4427 State.regs[dstreg] = load_half (State.regs[srcreg]);
4428 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4429}
4430
4431// 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
44328.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4433"movhu"
4434*am33
4435{
4436 int srcreg, dstreg;
4437
4438 PC = cia;
4439 srcreg = translate_rreg (SD_, RM2);
4440 dstreg = translate_rreg (SD_, RN0);
4441 store_half (State.regs[dstreg], State.regs[srcreg]);
4442 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4443}
4444
4445
4446// 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
44478.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
4448"mac"
4449*am33
4450{
4451 int srcreg, imm;
4452 long long temp, sum;
4453 int c, v;
4454
4455 PC = cia;
4456 srcreg = translate_rreg (SD_, RN0);
4457 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4458
4459 temp = ((signed64)(signed32)State.regs[srcreg]
4460 * (signed64)(signed32)imm);
4461 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4462 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4463 State.regs[REG_MCRL] = sum;
4464 temp >>= 32;
4465 temp &= 0xffffffff;
4466 sum = State.regs[REG_MCRH] + temp + c;
4467 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4468 && (temp & 0x80000000) != (sum & 0x80000000));
4469 State.regs[REG_MCRH] = sum;
4470 if (v)
4471 State.regs[REG_MCVF] = 1;
4472}
4473
4474// 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
44758.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
4476"macu"
4477*am33
4478{
4479 int srcreg, imm;
4480 long long temp, sum;
4481 int c, v;
4482
4483 PC = cia;
4484 srcreg = translate_rreg (SD_, RN0);
4485 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4486
4487 temp = ((unsigned64)State.regs[srcreg]
4488 * (unsigned64)imm);
4489 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4490 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4491 State.regs[REG_MCRL] = sum;
4492 temp >>= 32;
4493 temp &= 0xffffffff;
4494 sum = State.regs[REG_MCRH] + temp + c;
4495 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4496 && (temp & 0x80000000) != (sum & 0x80000000));
4497 State.regs[REG_MCRH] = sum;
4498 if (v)
4499 State.regs[REG_MCVF] = 1;
4500}
4501
4502// 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
45038.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
4504"macb"
4505*am33
4506{
4507 int srcreg, imm;
4508 long temp, sum;
4509 int v;
4510
4511 PC = cia;
4512 srcreg = translate_rreg (SD_, RN0);
4513 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4514
4515 temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
4516 * (signed32)(signed8)(imm & 0xff));
4517 sum = State.regs[REG_MCRL] + temp;
4518 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4519 && (temp & 0x80000000) != (sum & 0x80000000));
4520 State.regs[REG_MCRL] = sum;
4521 if (v)
4522 State.regs[REG_MCVF] = 1;
4523}
4524
4525// 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
45268.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
4527"macbu"
4528*am33
4529{
4530 int srcreg, imm;
4531 long temp, sum;
4532 int v;
4533
4534 PC = cia;
4535 srcreg = translate_rreg (SD_, RN0);
4536 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4537
4538 temp = ((unsigned32)(State.regs[srcreg] & 0xff)
4539 * (unsigned32)(imm & 0xff));
4540 sum = State.regs[REG_MCRL] + temp;
4541 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4542 && (temp & 0x80000000) != (sum & 0x80000000));
4543 State.regs[REG_MCRL] = sum;
4544 if (v)
4545 State.regs[REG_MCVF] = 1;
4546}
4547
4548// 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
45498.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
4550"mach"
4551*am33
4552{
4553 int srcreg, imm;
4554 long temp, sum;
4555 int v;
4556
4557 PC = cia;
4558 srcreg = translate_rreg (SD_, RN0);
4559 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4560
4561 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4562 * (signed32)(signed16)(imm & 0xffff));
4563 sum = State.regs[REG_MCRL] + temp;
4564 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4565 && (temp & 0x80000000) != (sum & 0x80000000));
4566 State.regs[REG_MCRL] = sum;
4567 if (v)
4568 State.regs[REG_MCVF] = 1;
4569}
4570
4571// 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
45728.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
4573"machu"
4574*am33
4575{
4576 int srcreg, imm;
4577 long temp, sum;
4578 int v;
4579
4580 PC = cia;
4581 srcreg = translate_rreg (SD_, RN0);
4582 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4583
4584 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4585 * (unsigned32)(imm & 0xffff));
4586 sum = State.regs[REG_MCRL] + temp;
4587 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4588 && (temp & 0x80000000) != (sum & 0x80000000));
4589 State.regs[REG_MCRL] = sum;
4590 if (v)
4591 State.regs[REG_MCVF] = 1;
4592}
4593
4594// 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
45958.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
4596"dmach"
4597*am33
4598{
4599 int srcreg, imm;
4600 long temp, temp2, sum;
4601 int v;
4602
4603 PC = cia;
4604 srcreg = translate_rreg (SD_, RN0);
4605 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4606
4607 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4608 * (signed32)(signed16)(imm & 0xffff));
4609 temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
4610 * (signed32)(signed16)((imm >> 16) & 0xffff));
4611 sum = temp + temp2 + State.regs[REG_MCRL];
4612 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4613 && (temp & 0x80000000) != (sum & 0x80000000));
4614 State.regs[REG_MCRL] = sum;
4615 if (v)
4616 State.regs[REG_MCVF] = 1;
4617}
4618
4619// 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
46208.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
4621"dmachu"
4622*am33
4623{
4624 int srcreg, imm;
4625 long temp, temp2, sum;
4626 int v;
4627
4628 PC = cia;
4629 srcreg = translate_rreg (SD_, RN0);
4630 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4631
4632 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4633 * (unsigned32)(imm & 0xffff));
4634 temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
4635 * (unsigned32)((imm >> 16) & 0xffff));
4636 sum = temp + temp2 + State.regs[REG_MCRL];
4637 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4638 && (temp & 0x80000000) != (sum & 0x80000000));
4639 State.regs[REG_MCRL] = sum;
4640 if (v)
4641 State.regs[REG_MCVF] = 1;
4642}
4643
4644// 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
46458.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
4646"dmulh"
4647*am33
4648{
4649 int imm, dstreg;
4650 long temp;
4651
4652 PC = cia;
4653 dstreg = translate_rreg (SD_, RN0);
4654 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4655
4656 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
4657 * (signed32)(signed16)(imm & 0xffff));
4658 State.regs[REG_MDRQ] = temp;
4659 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
4660 * (signed32)(signed16)((imm>>16) & 0xffff));
4661 State.regs[dstreg] = temp;
4662}
4663
4664// 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
46658.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
4666"dmulhu"
4667*am33
4668{
4669 int imm, dstreg;
4670 long temp;
4671
4672 PC = cia;
4673 dstreg = translate_rreg (SD_, RN0);
4674 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4675
4676 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
4677 * (unsigned32)(imm & 0xffff));
4678 State.regs[REG_MDRQ] = temp;
4679 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
4680 * (unsigned32)((imm >>16) & 0xffff));
4681 State.regs[dstreg] = temp;
4682}
4683
4684// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
46858.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4686"mov"
4687*am33
4688{
4689 int dstreg;
4690
4691 PC = cia;
4692 dstreg = translate_rreg (SD_, RN2);
4693 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4694}
4695
4696// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
46978.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4698"mov"
4699*am33
4700{
4701 int srcreg;
4702
4703 PC = cia;
4704 srcreg = translate_rreg (SD_, RM2);
4705 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4706}
4707
4708// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
47098.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4710"movbu"
4711*am33
4712{
4713 int dstreg;
4714
4715 PC = cia;
4716 dstreg = translate_rreg (SD_, RN2);
4717 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4718}
4719
4720// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
47218.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4722"movbu"
4723*am33
4724{
4725 int srcreg;
4726
4727 PC = cia;
4728 srcreg = translate_rreg (SD_, RM2);
4729 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4730}
4731
4732// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
47338.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4734"movhu"
4735*am33
4736{
4737 int dstreg;
4738
4739 PC = cia;
4740 dstreg = translate_rreg (SD_, RN2);
4741 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4742}
4743
4744// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
47458.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4746"movhu"
4747*am33
4748{
4749 int srcreg;
4750
4751 PC = cia;
4752 srcreg = translate_rreg (SD_, RM2);
4753 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4754}
4755
4756// 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
47578.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
4758"add_add"
4759*am33
4760{
4761 int srcreg1, srcreg2, dstreg1, dstreg2;
4762 int result1;
4763
4764 PC = cia;
4765 srcreg1 = translate_rreg (SD_, RM1);
4766 srcreg2 = translate_rreg (SD_, RM2);
4767 dstreg1 = translate_rreg (SD_, RN1);
4768 dstreg2 = translate_rreg (SD_, RN2);
4769
4770 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4771 State.regs[dstreg2] += State.regs[srcreg2];
4772 State.regs[dstreg1] = result1;
4773}
4774
4775// 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
47768.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
4777"add_add"
4778*am33
4779{
4780 int srcreg1, dstreg1, dstreg2;
4781 int result1;
4782
4783 PC = cia;
4784 srcreg1 = translate_rreg (SD_, RM1);
4785 dstreg1 = translate_rreg (SD_, RN1);
4786 dstreg2 = translate_rreg (SD_, RN2);
4787
4788 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4789 State.regs[dstreg2] += EXTEND4 (IMM4);
4790 State.regs[dstreg1] = result1;
4791}
4792
4793// 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
47948.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
4795"add_sub"
4796*am33
4797{
4798 int srcreg1, srcreg2, dstreg1, dstreg2;
4799 int result1;
4800
4801 PC = cia;
4802 srcreg1 = translate_rreg (SD_, RM1);
4803 srcreg2 = translate_rreg (SD_, RM2);
4804 dstreg1 = translate_rreg (SD_, RN1);
4805 dstreg2 = translate_rreg (SD_, RN2);
4806
4807 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4808 State.regs[dstreg2] -= State.regs[srcreg2];
4809 State.regs[dstreg1] = result1;
4810}
4811
4812// 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
48138.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
4814"add_sub"
4815*am33
4816{
4817 int srcreg1, dstreg1, dstreg2;
4818 int result1;
4819
4820 PC = cia;
4821 srcreg1 = translate_rreg (SD_, RM1);
4822 dstreg1 = translate_rreg (SD_, RN1);
4823 dstreg2 = translate_rreg (SD_, RN2);
4824
4825 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4826 State.regs[dstreg2] -= EXTEND4 (IMM4);
4827 State.regs[dstreg1] = result1;
4828}
4829
4830// 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
48318.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
4832"add_cmp"
4833*am33
4834{
4835 int srcreg1, srcreg2, dstreg1, dstreg2;
4836
4837 PC = cia;
4838 srcreg1 = translate_rreg (SD_, RM1);
4839 srcreg2 = translate_rreg (SD_, RM2);
4840 dstreg1 = translate_rreg (SD_, RN1);
4841 dstreg2 = translate_rreg (SD_, RN2);
4842
4843 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
4844 State.regs[dstreg1] += State.regs[srcreg1];
4845}
4846
4847// 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
48488.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
4849"add_cmp"
4850*am33
4851{
4852 int srcreg1, dstreg1, dstreg2;
4853
4854 PC = cia;
4855 srcreg1 = translate_rreg (SD_, RM1);
4856 dstreg1 = translate_rreg (SD_, RN1);
4857 dstreg2 = translate_rreg (SD_, RN2);
4858
4859 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
4860 State.regs[dstreg1] += State.regs[srcreg1];
4861}
4862
4863// 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
48648.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
4865"add_mov"
4866*am33
4867{
4868 int srcreg1, srcreg2, dstreg1, dstreg2;
4869 int result1;
4870
4871 PC = cia;
4872 srcreg1 = translate_rreg (SD_, RM1);
4873 srcreg2 = translate_rreg (SD_, RM2);
4874 dstreg1 = translate_rreg (SD_, RN1);
4875 dstreg2 = translate_rreg (SD_, RN2);
4876
4877 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4878 State.regs[dstreg2] = State.regs[srcreg2];
4879 State.regs[dstreg1] = result1;
4880}
4881
4882// 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
48838.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
4884"add_mov"
4885*am33
4886{
4887 int srcreg1, dstreg1, dstreg2;
4888 int result1;
4889
4890 PC = cia;
4891 srcreg1 = translate_rreg (SD_, RM1);
4892 dstreg1 = translate_rreg (SD_, RN1);
4893 dstreg2 = translate_rreg (SD_, RN2);
4894
4895 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4896 State.regs[dstreg2] = EXTEND4 (IMM4);
4897 State.regs[dstreg1] = result1;
4898}
4899
4900// 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
49018.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
4902"add_asr"
4903*am33
4904{
4905 int srcreg1, srcreg2, dstreg1, dstreg2;
4906 int result1;
4907 signed int temp;
4908
4909 PC = cia;
4910 srcreg1 = translate_rreg (SD_, RM1);
4911 srcreg2 = translate_rreg (SD_, RM2);
4912 dstreg1 = translate_rreg (SD_, RN1);
4913 dstreg2 = translate_rreg (SD_, RN2);
4914
4915 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4916 temp = State.regs[dstreg2];
4917 temp >>= State.regs[srcreg2];
4918 State.regs[dstreg2] = temp;
4919 State.regs[dstreg1] = result1;
4920}
4921
4922// 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
49238.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
4924"add_asr"
4925*am33
4926{
4927 int srcreg1, dstreg1, dstreg2;
4928 int result1;
4929 signed int temp;
4930
4931 PC = cia;
4932 srcreg1 = translate_rreg (SD_, RM1);
4933 dstreg1 = translate_rreg (SD_, RN1);
4934 dstreg2 = translate_rreg (SD_, RN2);
4935
4936 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4937 temp = State.regs[dstreg2];
4938 temp >>= IMM4;
4939 State.regs[dstreg2] = temp;
4940 State.regs[dstreg1] = result1;
4941}
4942
4943// 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
49448.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
4945"add_lsr"
4946*am33
4947{
4948 int srcreg1, srcreg2, dstreg1, dstreg2;
4949 int result1;
4950
4951 PC = cia;
4952 srcreg1 = translate_rreg (SD_, RM1);
4953 srcreg2 = translate_rreg (SD_, RM2);
4954 dstreg1 = translate_rreg (SD_, RN1);
4955 dstreg2 = translate_rreg (SD_, RN2);
4956
4957 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4958 State.regs[dstreg2] >>= State.regs[srcreg2];
4959 State.regs[dstreg1] = result1;
4960}
4961
4962// 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
49638.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
4964"add_lsr"
4965*am33
4966{
4967 int srcreg1, dstreg1, dstreg2;
4968 int result1;
4969 signed int temp;
4970
4971 PC = cia;
4972 srcreg1 = translate_rreg (SD_, RM1);
4973 dstreg1 = translate_rreg (SD_, RN1);
4974 dstreg2 = translate_rreg (SD_, RN2);
4975
4976 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4977 State.regs[dstreg2] >>= IMM4;
4978 State.regs[dstreg1] = result1;
4979}
4980
4981
4982// 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
49838.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
4984"add_asl"
4985*am33
4986{
4987 int srcreg1, srcreg2, dstreg1, dstreg2;
4988 int result1;
4989
4990 PC = cia;
4991 srcreg1 = translate_rreg (SD_, RM1);
4992 srcreg2 = translate_rreg (SD_, RM2);
4993 dstreg1 = translate_rreg (SD_, RN1);
4994 dstreg2 = translate_rreg (SD_, RN2);
4995
4996 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4997 State.regs[dstreg2] <<= State.regs[srcreg2];
4998 State.regs[dstreg1] = result1;
4999}
5000
5001// 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
50028.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
5003"add_asl"
5004*am33
5005{
5006 int srcreg1, dstreg1, dstreg2;
5007 int result1;
5008 signed int temp;
5009
5010 PC = cia;
5011 srcreg1 = translate_rreg (SD_, RM1);
5012 dstreg1 = translate_rreg (SD_, RN1);
5013 dstreg2 = translate_rreg (SD_, RN2);
5014
5015 result1 = State.regs[dstreg1] + State.regs[srcreg1];
5016 State.regs[dstreg2] <<= IMM4;
5017 State.regs[dstreg1] = result1;
5018}
5019
5020// 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
50218.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
5022"cmp_add"
5023*am33
5024{
5025 int srcreg1, srcreg2, dstreg1, dstreg2;
5026
5027 PC = cia;
5028 srcreg1 = translate_rreg (SD_, RM1);
5029 srcreg2 = translate_rreg (SD_, RM2);
5030 dstreg1 = translate_rreg (SD_, RN1);
5031 dstreg2 = translate_rreg (SD_, RN2);
5032
5033 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5034 State.regs[dstreg2] += State.regs[srcreg2];
5035}
5036
5037// 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
50388.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
5039"cmp_add"
5040*am33
5041{
5042 int srcreg1, dstreg1, dstreg2;
5043
5044 PC = cia;
5045 srcreg1 = translate_rreg (SD_, RM1);
5046 dstreg1 = translate_rreg (SD_, RN1);
5047 dstreg2 = translate_rreg (SD_, RN2);
5048
5049 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5050 State.regs[dstreg2] += EXTEND4 (IMM4);
5051}
5052
5053// 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
50548.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
5055"cmp_sub"
5056*am33
5057{
5058 int srcreg1, srcreg2, dstreg1, dstreg2;
5059
5060 PC = cia;
5061 srcreg1 = translate_rreg (SD_, RM1);
5062 srcreg2 = translate_rreg (SD_, RM2);
5063 dstreg1 = translate_rreg (SD_, RN1);
5064 dstreg2 = translate_rreg (SD_, RN2);
5065
5066 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5067 State.regs[dstreg2] -= State.regs[srcreg2];
5068}
5069
5070// 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
50718.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
5072"cmp_sub"
5073*am33
5074{
5075 int srcreg1, dstreg1, dstreg2;
5076
5077 PC = cia;
5078 srcreg1 = translate_rreg (SD_, RM1);
5079 dstreg1 = translate_rreg (SD_, RN1);
5080 dstreg2 = translate_rreg (SD_, RN2);
5081
5082 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5083 State.regs[dstreg2] -= EXTEND4 (IMM4);
5084}
5085
5086// 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
50878.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
5088"cmp_mov"
5089*am33
5090{
5091 int srcreg1, srcreg2, dstreg1, dstreg2;
5092
5093 PC = cia;
5094 srcreg1 = translate_rreg (SD_, RM1);
5095 srcreg2 = translate_rreg (SD_, RM2);
5096 dstreg1 = translate_rreg (SD_, RN1);
5097 dstreg2 = translate_rreg (SD_, RN2);
5098
5099 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5100 State.regs[dstreg2] = State.regs[srcreg2];
5101}
5102
5103// 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
51048.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
5105"cmp_mov"
5106*am33
5107{
5108 int srcreg1, dstreg1, dstreg2;
5109
5110 PC = cia;
5111 srcreg1 = translate_rreg (SD_, RM1);
5112 dstreg1 = translate_rreg (SD_, RN1);
5113 dstreg2 = translate_rreg (SD_, RN2);
5114
5115 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5116 State.regs[dstreg2] = EXTEND4 (IMM4);
5117}
5118
5119// 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
51208.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
5121"cmp_asr"
5122*am33
5123{
5124 int srcreg1, srcreg2, dstreg1, dstreg2;
5125 signed int temp;
5126
5127 PC = cia;
5128 srcreg1 = translate_rreg (SD_, RM1);
5129 srcreg2 = translate_rreg (SD_, RM2);
5130 dstreg1 = translate_rreg (SD_, RN1);
5131 dstreg2 = translate_rreg (SD_, RN2);
5132
5133 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5134 temp = State.regs[dstreg2];
5135 temp >>= State.regs[srcreg2];
5136 State.regs[dstreg2] = temp;
5137}
5138
5139// 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
51408.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
5141"cmp_asr"
5142*am33
5143{
5144 int srcreg1, dstreg1, dstreg2;
5145 signed int temp;
5146
5147 PC = cia;
5148 srcreg1 = translate_rreg (SD_, RM1);
5149 dstreg1 = translate_rreg (SD_, RN1);
5150 dstreg2 = translate_rreg (SD_, RN2);
5151
5152 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5153 temp = State.regs[dstreg2];
5154 temp >>= IMM4;
5155 State.regs[dstreg2] = temp;
5156}
5157
5158// 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
51598.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
5160"cmp_lsr"
5161*am33
5162{
5163 int srcreg1, srcreg2, dstreg1, dstreg2;
5164
5165 PC = cia;
5166 srcreg1 = translate_rreg (SD_, RM1);
5167 srcreg2 = translate_rreg (SD_, RM2);
5168 dstreg1 = translate_rreg (SD_, RN1);
5169 dstreg2 = translate_rreg (SD_, RN2);
5170
5171 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5172 State.regs[dstreg2] >>= State.regs[srcreg2];
5173}
5174
5175// 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
51768.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
5177"cmp_lsr"
5178*am33
5179{
5180 int srcreg1, dstreg1, dstreg2;
5181 signed int temp;
5182
5183 PC = cia;
5184 srcreg1 = translate_rreg (SD_, RM1);
5185 dstreg1 = translate_rreg (SD_, RN1);
5186 dstreg2 = translate_rreg (SD_, RN2);
5187
5188 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5189 State.regs[dstreg2] >>= IMM4;
5190}
5191
5192
5193// 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
51948.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
5195"cmp_asl"
5196*am33
5197{
5198 int srcreg1, srcreg2, dstreg1, dstreg2;
5199
5200 PC = cia;
5201 srcreg1 = translate_rreg (SD_, RM1);
5202 srcreg2 = translate_rreg (SD_, RM2);
5203 dstreg1 = translate_rreg (SD_, RN1);
5204 dstreg2 = translate_rreg (SD_, RN2);
5205
5206 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5207 State.regs[dstreg2] <<= State.regs[srcreg2];
5208}
5209
5210// 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
52118.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
5212"cmp_asl"
5213*am33
5214{
5215 int srcreg1, dstreg1, dstreg2;
5216 signed int temp;
5217
5218 PC = cia;
5219 srcreg1 = translate_rreg (SD_, RM1);
5220 dstreg1 = translate_rreg (SD_, RN1);
5221 dstreg2 = translate_rreg (SD_, RN2);
5222
5223 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5224 State.regs[dstreg2] <<= IMM4;
5225}
5226
5227// 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
52288.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
5229"sub_add"
5230*am33
5231{
5232 int srcreg1, srcreg2, dstreg1, dstreg2;
5233 int result1;
5234
5235 PC = cia;
5236 srcreg1 = translate_rreg (SD_, RM1);
5237 srcreg2 = translate_rreg (SD_, RM2);
5238 dstreg1 = translate_rreg (SD_, RN1);
5239 dstreg2 = translate_rreg (SD_, RN2);
5240
5241 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5242 State.regs[dstreg2] += State.regs[srcreg2];
5243 State.regs[dstreg1] = result1;
5244}
5245
5246// 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
52478.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
5248"sub_add"
5249*am33
5250{
5251 int srcreg1, dstreg1, dstreg2;
5252 int result1;
5253
5254 PC = cia;
5255 srcreg1 = translate_rreg (SD_, RM1);
5256 dstreg1 = translate_rreg (SD_, RN1);
5257 dstreg2 = translate_rreg (SD_, RN2);
5258
5259 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5260 State.regs[dstreg2] += EXTEND4 (IMM4);
5261 State.regs[dstreg1] = result1;
5262}
5263
5264// 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
52658.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
5266"sub_sub"
5267*am33
5268{
5269 int srcreg1, srcreg2, dstreg1, dstreg2;
5270 int result1;
5271
5272 PC = cia;
5273 srcreg1 = translate_rreg (SD_, RM1);
5274 srcreg2 = translate_rreg (SD_, RM2);
5275 dstreg1 = translate_rreg (SD_, RN1);
5276 dstreg2 = translate_rreg (SD_, RN2);
5277
5278 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5279 State.regs[dstreg2] -= State.regs[srcreg2];
5280 State.regs[dstreg1] = result1;
5281}
5282
5283// 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
52848.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
5285"sub_sub"
5286*am33
5287{
5288 int srcreg1, dstreg1, dstreg2;
5289 int result1;
5290
5291 PC = cia;
5292 srcreg1 = translate_rreg (SD_, RM1);
5293 dstreg1 = translate_rreg (SD_, RN1);
5294 dstreg2 = translate_rreg (SD_, RN2);
5295
5296 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5297 State.regs[dstreg2] -= EXTEND4 (IMM4);
5298 State.regs[dstreg1] = result1;
5299}
5300
5301// 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
53028.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
5303"sub_cmp"
5304*am33
5305{
5306 int srcreg1, srcreg2, dstreg1, dstreg2;
5307
5308 PC = cia;
5309 srcreg1 = translate_rreg (SD_, RM1);
5310 srcreg2 = translate_rreg (SD_, RM2);
5311 dstreg1 = translate_rreg (SD_, RN1);
5312 dstreg2 = translate_rreg (SD_, RN2);
5313
5314 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5315 State.regs[dstreg1] -= State.regs[srcreg1];
5316}
5317
5318// 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
53198.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
5320"sub_cmp"
5321*am33
5322{
5323 int srcreg1, dstreg1, dstreg2;
5324 int result1;
5325
5326 PC = cia;
5327 srcreg1 = translate_rreg (SD_, RM1);
5328 dstreg1 = translate_rreg (SD_, RN1);
5329 dstreg2 = translate_rreg (SD_, RN2);
5330
5331 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5332 State.regs[dstreg1] -= State.regs[srcreg1];
5333}
5334
5335// 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
53368.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
5337"sub_mov"
5338*am33
5339{
5340 int srcreg1, srcreg2, dstreg1, dstreg2;
5341 int result1;
5342
5343 PC = cia;
5344 srcreg1 = translate_rreg (SD_, RM1);
5345 srcreg2 = translate_rreg (SD_, RM2);
5346 dstreg1 = translate_rreg (SD_, RN1);
5347 dstreg2 = translate_rreg (SD_, RN2);
5348
5349 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5350 State.regs[dstreg2] = State.regs[srcreg2];
5351 State.regs[dstreg1] = result1;
5352}
5353
5354// 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
53558.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
5356"sub_mov"
5357*am33
5358{
5359 int srcreg1, dstreg1, dstreg2;
5360 int result1;
5361
5362 PC = cia;
5363 srcreg1 = translate_rreg (SD_, RM1);
5364 dstreg1 = translate_rreg (SD_, RN1);
5365 dstreg2 = translate_rreg (SD_, RN2);
5366
5367 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5368 State.regs[dstreg2] = EXTEND4 (IMM4);
5369 State.regs[dstreg1] = result1;
5370}
5371
5372// 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
53738.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
5374"sub_asr"
5375*am33
5376{
5377 int srcreg1, srcreg2, dstreg1, dstreg2;
5378 int result1;
5379 signed int temp;
5380
5381 PC = cia;
5382 srcreg1 = translate_rreg (SD_, RM1);
5383 srcreg2 = translate_rreg (SD_, RM2);
5384 dstreg1 = translate_rreg (SD_, RN1);
5385 dstreg2 = translate_rreg (SD_, RN2);
5386
5387 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5388 temp = State.regs[dstreg2];
5389 temp >>= State.regs[srcreg2];
5390 State.regs[dstreg2] = temp;
5391 State.regs[dstreg1] = result1;
5392}
5393
5394// 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
53958.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
5396"sub_asr"
5397*am33
5398{
5399 int srcreg1, dstreg1, dstreg2;
5400 int result1;
5401 signed int temp;
5402
5403 PC = cia;
5404 srcreg1 = translate_rreg (SD_, RM1);
5405 dstreg1 = translate_rreg (SD_, RN1);
5406 dstreg2 = translate_rreg (SD_, RN2);
5407
5408 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5409 temp = State.regs[dstreg2];
5410 temp >>= IMM4;
5411 State.regs[dstreg2] = temp;
5412 State.regs[dstreg1] = result1;
5413}
5414
5415// 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
54168.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
5417"sub_lsr"
5418*am33
5419{
5420 int srcreg1, srcreg2, dstreg1, dstreg2;
5421 int result1;
5422
5423 PC = cia;
5424 srcreg1 = translate_rreg (SD_, RM1);
5425 srcreg2 = translate_rreg (SD_, RM2);
5426 dstreg1 = translate_rreg (SD_, RN1);
5427 dstreg2 = translate_rreg (SD_, RN2);
5428
5429 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5430 State.regs[dstreg2] >>= State.regs[srcreg2];
5431 State.regs[dstreg1] = result1;
5432}
5433
5434// 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
54358.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
5436"sub_lsr"
5437*am33
5438{
5439 int srcreg1, dstreg1, dstreg2;
5440 int result1;
5441 signed int temp;
5442
5443 PC = cia;
5444 srcreg1 = translate_rreg (SD_, RM1);
5445 dstreg1 = translate_rreg (SD_, RN1);
5446 dstreg2 = translate_rreg (SD_, RN2);
5447
5448 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5449 State.regs[dstreg2] >>= IMM4;
5450 State.regs[dstreg1] = result1;
5451}
5452
5453
5454// 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
54558.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
5456"sub_asl"
5457*am33
5458{
5459 int srcreg1, srcreg2, dstreg1, dstreg2;
5460 int result1;
5461
5462 PC = cia;
5463 srcreg1 = translate_rreg (SD_, RM1);
5464 srcreg2 = translate_rreg (SD_, RM2);
5465 dstreg1 = translate_rreg (SD_, RN1);
5466 dstreg2 = translate_rreg (SD_, RN2);
5467
5468 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5469 State.regs[dstreg2] <<= State.regs[srcreg2];
5470 State.regs[dstreg1] = result1;
5471}
5472
5473// 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
54748.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
5475"sub_asl"
5476*am33
5477{
5478 int srcreg1, dstreg1, dstreg2;
5479 int result1;
5480 signed int temp;
5481
5482 PC = cia;
5483 srcreg1 = translate_rreg (SD_, RM1);
5484 dstreg1 = translate_rreg (SD_, RN1);
5485 dstreg2 = translate_rreg (SD_, RN2);
5486
5487 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5488 State.regs[dstreg2] <<= IMM4;
5489 State.regs[dstreg1] = result1;
5490}
5491
5492// 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
54938.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
5494"mov_add"
5495*am33
5496{
5497 int srcreg1, srcreg2, dstreg1, dstreg2;
5498 int result1;
5499
5500 PC = cia;
5501 srcreg1 = translate_rreg (SD_, RM1);
5502 srcreg2 = translate_rreg (SD_, RM2);
5503 dstreg1 = translate_rreg (SD_, RN1);
5504 dstreg2 = translate_rreg (SD_, RN2);
5505
5506 result1 = State.regs[srcreg1];
5507 State.regs[dstreg2] += State.regs[srcreg2];
5508 State.regs[dstreg1] = result1;
5509}
5510
5511// 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
55128.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
5513"mov_add"
5514*am33
5515{
5516 int srcreg1, dstreg1, dstreg2;
5517 int result1;
5518
5519 PC = cia;
5520 srcreg1 = translate_rreg (SD_, RM1);
5521 dstreg1 = translate_rreg (SD_, RN1);
5522 dstreg2 = translate_rreg (SD_, RN2);
5523
5524 result1 = State.regs[srcreg1];
5525 State.regs[dstreg2] += EXTEND4 (IMM4);
5526 State.regs[dstreg1] = result1;
5527}
5528
5529// 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
55308.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
5531"mov_sub"
5532*am33
5533{
5534 int srcreg1, srcreg2, dstreg1, dstreg2;
5535 int result1;
5536
5537 PC = cia;
5538 srcreg1 = translate_rreg (SD_, RM1);
5539 srcreg2 = translate_rreg (SD_, RM2);
5540 dstreg1 = translate_rreg (SD_, RN1);
5541 dstreg2 = translate_rreg (SD_, RN2);
5542
5543 result1 = State.regs[srcreg1];
5544 State.regs[dstreg2] -= State.regs[srcreg2];
5545 State.regs[dstreg1] = result1;
5546}
5547
5548// 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
55498.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
5550"mov_sub"
5551*am33
5552{
5553 int srcreg1, dstreg1, dstreg2;
5554 int result1;
5555
5556 PC = cia;
5557 srcreg1 = translate_rreg (SD_, RM1);
5558 dstreg1 = translate_rreg (SD_, RN1);
5559 dstreg2 = translate_rreg (SD_, RN2);
5560
5561 result1 = State.regs[srcreg1];
5562 State.regs[dstreg2] -= EXTEND4 (IMM4);
5563 State.regs[dstreg1] = result1;
5564}
5565
5566// 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
55678.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
5568"mov_cmp"
5569*am33
5570{
5571 int srcreg1, srcreg2, dstreg1, dstreg2;
5572
5573 PC = cia;
5574 srcreg1 = translate_rreg (SD_, RM1);
5575 srcreg2 = translate_rreg (SD_, RM2);
5576 dstreg1 = translate_rreg (SD_, RN1);
5577 dstreg2 = translate_rreg (SD_, RN2);
5578
5579 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5580 State.regs[dstreg1] = State.regs[srcreg1];
5581}
5582
5583// 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
55848.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
5585"mov_cmp"
5586*am33
5587{
5588 int srcreg1, dstreg1, dstreg2;
5589
5590 PC = cia;
5591 srcreg1 = translate_rreg (SD_, RM1);
5592 dstreg1 = translate_rreg (SD_, RN1);
5593 dstreg2 = translate_rreg (SD_, RN2);
5594
5595 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5596 State.regs[dstreg1] = State.regs[srcreg1];
5597}
5598
5599// 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
56008.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
5601"mov_mov"
5602*am33
5603{
5604 int srcreg1, srcreg2, dstreg1, dstreg2;
5605 int result1;
5606
5607 PC = cia;
5608 srcreg1 = translate_rreg (SD_, RM1);
5609 srcreg2 = translate_rreg (SD_, RM2);
5610 dstreg1 = translate_rreg (SD_, RN1);
5611 dstreg2 = translate_rreg (SD_, RN2);
5612
5613 result1 = State.regs[srcreg1];
5614 State.regs[dstreg2] = State.regs[srcreg2];
5615 State.regs[dstreg1] = result1;
5616}
5617
5618// 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
56198.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
5620"mov_mov"
5621*am33
5622{
5623 int srcreg1, dstreg1, dstreg2;
5624 int result1;
5625
5626 PC = cia;
5627 srcreg1 = translate_rreg (SD_, RM1);
5628 dstreg1 = translate_rreg (SD_, RN1);
5629 dstreg2 = translate_rreg (SD_, RN2);
5630
5631 result1 = State.regs[srcreg1];
5632 State.regs[dstreg2] = EXTEND4 (IMM4);
5633 State.regs[dstreg1] = result1;
5634}
5635
5636// 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
56378.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
5638"mov_asr"
5639*am33
5640{
5641 int srcreg1, srcreg2, dstreg1, dstreg2;
5642 int result1;
5643 signed int temp;
5644
5645 PC = cia;
5646 srcreg1 = translate_rreg (SD_, RM1);
5647 srcreg2 = translate_rreg (SD_, RM2);
5648 dstreg1 = translate_rreg (SD_, RN1);
5649 dstreg2 = translate_rreg (SD_, RN2);
5650
5651 result1 = State.regs[srcreg1];
5652 temp = State.regs[dstreg2];
5653 temp >>= State.regs[srcreg2];
5654 State.regs[dstreg2] = temp;
5655 State.regs[dstreg1] = result1;
5656}
5657
5658// 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
56598.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
5660"mov_asr"
5661*am33
5662{
5663 int srcreg1, dstreg1, dstreg2;
5664 int result1;
5665 signed int temp;
5666
5667 PC = cia;
5668 srcreg1 = translate_rreg (SD_, RM1);
5669 dstreg1 = translate_rreg (SD_, RN1);
5670 dstreg2 = translate_rreg (SD_, RN2);
5671
5672 result1 = State.regs[srcreg1];
5673 temp = State.regs[dstreg2];
5674 temp >>= IMM4;
5675 State.regs[dstreg2] = temp;
5676 State.regs[dstreg1] = result1;
5677}
5678
5679// 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
56808.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
5681"mov_lsr"
5682*am33
5683{
5684 int srcreg1, srcreg2, dstreg1, dstreg2;
5685 int result1;
5686
5687 PC = cia;
5688 srcreg1 = translate_rreg (SD_, RM1);
5689 srcreg2 = translate_rreg (SD_, RM2);
5690 dstreg1 = translate_rreg (SD_, RN1);
5691 dstreg2 = translate_rreg (SD_, RN2);
5692
5693 result1 = State.regs[srcreg1];
5694 State.regs[dstreg2] >>= State.regs[srcreg2];
5695 State.regs[dstreg1] = result1;
5696}
5697
5698// 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
56998.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
5700"mov_lsr"
5701*am33
5702{
5703 int srcreg1, dstreg1, dstreg2;
5704 int result1;
5705 signed int temp;
5706
5707 PC = cia;
5708 srcreg1 = translate_rreg (SD_, RM1);
5709 dstreg1 = translate_rreg (SD_, RN1);
5710 dstreg2 = translate_rreg (SD_, RN2);
5711
5712 result1 = State.regs[srcreg1];
5713 State.regs[dstreg2] >>= IMM4;
5714 State.regs[dstreg1] = result1;
5715}
5716
5717
5718// 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
57198.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
5720"mov_asl"
5721*am33
5722{
5723 int srcreg1, srcreg2, dstreg1, dstreg2;
5724 int result1;
5725
5726 PC = cia;
5727 srcreg1 = translate_rreg (SD_, RM1);
5728 srcreg2 = translate_rreg (SD_, RM2);
5729 dstreg1 = translate_rreg (SD_, RN1);
5730 dstreg2 = translate_rreg (SD_, RN2);
5731
5732 result1 = State.regs[srcreg1];
5733 State.regs[dstreg2] <<= State.regs[srcreg2];
5734 State.regs[dstreg1] = result1;
5735}
5736
5737// 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
57388.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
5739"mov_asl"
5740*am33
5741{
5742 int srcreg1, dstreg1, dstreg2;
5743 int result1;
5744 signed int temp;
5745
5746 PC = cia;
5747 srcreg1 = translate_rreg (SD_, RM1);
5748 dstreg1 = translate_rreg (SD_, RN1);
5749 dstreg2 = translate_rreg (SD_, RN2);
5750
5751 result1 = State.regs[srcreg1];
5752 State.regs[dstreg2] <<= IMM4;
5753 State.regs[dstreg1] = result1;
5754}
5755
5756// 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
57578.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
5758"add_add"
5759*am33
5760{
5761 int srcreg2, dstreg1, dstreg2;
5762 int result1;
5763
5764 PC = cia;
5765 srcreg2 = translate_rreg (SD_, RM2);
5766 dstreg1 = translate_rreg (SD_, RN1);
5767 dstreg2 = translate_rreg (SD_, RN2);
5768
5769 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5770 State.regs[dstreg2] += State.regs[srcreg2];
5771 State.regs[dstreg1] = result1;
5772}
5773
5774// 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
57758.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
5776"add_add"
5777*am33
5778{
5779 int dstreg1, dstreg2;
5780 int result1;
5781
5782 PC = cia;
5783 dstreg1 = translate_rreg (SD_, RN1);
5784 dstreg2 = translate_rreg (SD_, RN2);
5785
5786 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5787 State.regs[dstreg2] += EXTEND4 (IMM4);
5788 State.regs[dstreg1] = result1;
5789}
5790
5791// 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
57928.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
5793"add_sub"
5794*am33
5795{
5796 int srcreg2, dstreg1, dstreg2;
5797 int result1;
5798
5799 PC = cia;
5800 srcreg2 = translate_rreg (SD_, RM2);
5801 dstreg1 = translate_rreg (SD_, RN1);
5802 dstreg2 = translate_rreg (SD_, RN2);
5803
5804 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5805 State.regs[dstreg2] -= State.regs[srcreg2];
5806 State.regs[dstreg1] = result1;
5807}
5808
5809// 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
58108.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
5811"add_sub"
5812*am33
5813{
5814 int dstreg1, dstreg2;
5815 int result1;
5816
5817 PC = cia;
5818 dstreg1 = translate_rreg (SD_, RN1);
5819 dstreg2 = translate_rreg (SD_, RN2);
5820
5821 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5822 State.regs[dstreg2] -= EXTEND4 (IMM4);
5823 State.regs[dstreg1] = result1;
5824}
5825
5826// 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
58278.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
5828"add_cmp"
5829*am33
5830{
5831 int srcreg2, dstreg1, dstreg2;
5832
5833 PC = cia;
5834 srcreg2 = translate_rreg (SD_, RM2);
5835 dstreg1 = translate_rreg (SD_, RN1);
5836 dstreg2 = translate_rreg (SD_, RN2);
5837
5838 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5839 State.regs[dstreg1] += EXTEND4 (IMM4A);
5840}
5841
5842// 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
58438.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
5844"add_cmp"
5845*am33
5846{
5847 int dstreg1, dstreg2;
5848
5849 PC = cia;
5850 dstreg1 = translate_rreg (SD_, RN1);
5851 dstreg2 = translate_rreg (SD_, RN2);
5852
5853 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5854 State.regs[dstreg1] += EXTEND4 (IMM4A);
5855}
5856
5857// 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
58588.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
5859"add_mov"
5860*am33
5861{
5862 int srcreg2, dstreg1, dstreg2;
5863 int result1;
5864
5865 PC = cia;
5866 srcreg2 = translate_rreg (SD_, RM2);
5867 dstreg1 = translate_rreg (SD_, RN1);
5868 dstreg2 = translate_rreg (SD_, RN2);
5869
5870 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5871 State.regs[dstreg2] = State.regs[srcreg2];
5872 State.regs[dstreg1] = result1;
5873}
5874
5875// 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
58768.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
5877"add_mov"
5878*am33
5879{
5880 int dstreg1, dstreg2;
5881 int result1;
5882
5883 PC = cia;
5884 dstreg1 = translate_rreg (SD_, RN1);
5885 dstreg2 = translate_rreg (SD_, RN2);
5886
5887 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5888 State.regs[dstreg2] = EXTEND4 (IMM4);
5889 State.regs[dstreg1] = result1;
5890}
5891
5892// 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
58938.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
5894"add_asr"
5895*am33
5896{
5897 int srcreg2, dstreg1, dstreg2;
5898 int result1;
5899 signed int temp;
5900
5901 PC = cia;
5902 srcreg2 = translate_rreg (SD_, RM2);
5903 dstreg1 = translate_rreg (SD_, RN1);
5904 dstreg2 = translate_rreg (SD_, RN2);
5905
5906 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5907 temp = State.regs[dstreg2];
5908 temp >>= State.regs[srcreg2];
5909 State.regs[dstreg2] = temp;
5910 State.regs[dstreg1] = result1;
5911}
5912
5913// 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
59148.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
5915"add_asr"
5916*am33
5917{
5918 int dstreg1, dstreg2;
5919 int result1;
5920 signed int temp;
5921
5922 PC = cia;
5923 dstreg1 = translate_rreg (SD_, RN1);
5924 dstreg2 = translate_rreg (SD_, RN2);
5925
5926 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5927 temp = State.regs[dstreg2];
5928 temp >>= IMM4;
5929 State.regs[dstreg2] = temp;
5930 State.regs[dstreg1] = result1;
5931}
5932
5933// 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
59348.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
5935"add_lsr"
5936*am33
5937{
5938 int srcreg2, dstreg1, dstreg2;
5939 int result1;
5940
5941 PC = cia;
5942 srcreg2 = translate_rreg (SD_, RM2);
5943 dstreg1 = translate_rreg (SD_, RN1);
5944 dstreg2 = translate_rreg (SD_, RN2);
5945
5946 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5947 State.regs[dstreg2] >>= State.regs[srcreg2];
5948 State.regs[dstreg1] = result1;
5949}
5950
5951// 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
59528.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
5953"add_lsr"
5954*am33
5955{
5956 int dstreg1, dstreg2;
5957 int result1;
5958 signed int temp;
5959
5960 PC = cia;
5961 dstreg1 = translate_rreg (SD_, RN1);
5962 dstreg2 = translate_rreg (SD_, RN2);
5963
5964 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5965 State.regs[dstreg2] >>= IMM4;
5966 State.regs[dstreg1] = result1;
5967}
5968
5969
5970// 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
59718.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
5972"add_asl"
5973*am33
5974{
5975 int srcreg2, dstreg1, dstreg2;
5976 int result1;
5977
5978 PC = cia;
5979 srcreg2 = translate_rreg (SD_, RM2);
5980 dstreg1 = translate_rreg (SD_, RN1);
5981 dstreg2 = translate_rreg (SD_, RN2);
5982
5983 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5984 State.regs[dstreg2] <<= State.regs[srcreg2];
5985 State.regs[dstreg1] = result1;
5986}
5987
5988// 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
59898.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
5990"add_asl"
5991*am33
5992{
5993 int dstreg1, dstreg2;
5994 int result1;
5995 signed int temp;
5996
5997 PC = cia;
5998 dstreg1 = translate_rreg (SD_, RN1);
5999 dstreg2 = translate_rreg (SD_, RN2);
6000
6001 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
6002 State.regs[dstreg2] <<= IMM4;
6003 State.regs[dstreg1] = result1;
6004}
6005
6006// 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
60078.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
6008"cmp_add"
6009*am33
6010{
6011 int srcreg2, dstreg1, dstreg2;
6012
6013 PC = cia;
6014 srcreg2 = translate_rreg (SD_, RM2);
6015 dstreg1 = translate_rreg (SD_, RN1);
6016 dstreg2 = translate_rreg (SD_, RN2);
6017
6018 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6019 State.regs[dstreg2] += State.regs[srcreg2];
6020}
6021
6022// 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
60238.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
6024"cmp_add"
6025*am33
6026{
6027 int dstreg1, dstreg2;
6028
6029 PC = cia;
6030 dstreg1 = translate_rreg (SD_, RN1);
6031 dstreg2 = translate_rreg (SD_, RN2);
6032
6033 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6034 State.regs[dstreg2] += EXTEND4 (IMM4);
6035}
6036
6037// 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
60388.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
6039"cmp_sub"
6040*am33
6041{
6042 int srcreg2, dstreg1, dstreg2;
6043
6044 PC = cia;
6045 srcreg2 = translate_rreg (SD_, RM2);
6046 dstreg1 = translate_rreg (SD_, RN1);
6047 dstreg2 = translate_rreg (SD_, RN2);
6048
6049 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6050 State.regs[dstreg2] -= State.regs[srcreg2];
6051}
6052
6053// 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
60548.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
6055"cmp_sub"
6056*am33
6057{
6058 int dstreg1, dstreg2;
6059
6060 PC = cia;
6061 dstreg1 = translate_rreg (SD_, RN1);
6062 dstreg2 = translate_rreg (SD_, RN2);
6063
6064 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6065 State.regs[dstreg2] -= EXTEND4 (IMM4);
6066}
6067
6068// 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
60698.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
6070"cmp_mov"
6071*am33
6072{
6073 int srcreg2, dstreg1, dstreg2;
6074
6075 PC = cia;
6076 srcreg2 = translate_rreg (SD_, RM2);
6077 dstreg1 = translate_rreg (SD_, RN1);
6078 dstreg2 = translate_rreg (SD_, RN2);
6079
6080 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6081 State.regs[dstreg2] = State.regs[srcreg2];
6082}
6083
6084// 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
60858.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
6086"cmp_mov"
6087*am33
6088{
6089 int dstreg1, dstreg2;
6090
6091 PC = cia;
6092 dstreg1 = translate_rreg (SD_, RN1);
6093 dstreg2 = translate_rreg (SD_, RN2);
6094
6095 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6096 State.regs[dstreg2] = EXTEND4 (IMM4);
6097}
6098
6099// 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
61008.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
6101"cmp_asr"
6102*am33
6103{
6104 int srcreg2, dstreg1, dstreg2;
6105 signed int temp;
6106
6107 PC = cia;
6108 srcreg2 = translate_rreg (SD_, RM2);
6109 dstreg1 = translate_rreg (SD_, RN1);
6110 dstreg2 = translate_rreg (SD_, RN2);
6111
6112 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6113 temp = State.regs[dstreg2];
6114 temp >>= State.regs[srcreg2];
6115 State.regs[dstreg2] = temp;
6116}
6117
6118// 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
61198.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
6120"cmp_asr"
6121*am33
6122{
6123 int dstreg1, dstreg2;
6124 signed int temp;
6125
6126 PC = cia;
6127 dstreg1 = translate_rreg (SD_, RN1);
6128 dstreg2 = translate_rreg (SD_, RN2);
6129
6130 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6131 temp = State.regs[dstreg2];
6132 temp >>= IMM4;
6133 State.regs[dstreg2] = temp;
6134}
6135
6136// 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
61378.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
6138"cmp_lsr"
6139*am33
6140{
6141 int srcreg2, dstreg1, dstreg2;
6142
6143 PC = cia;
6144 srcreg2 = translate_rreg (SD_, RM2);
6145 dstreg1 = translate_rreg (SD_, RN1);
6146 dstreg2 = translate_rreg (SD_, RN2);
6147
6148 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6149 State.regs[dstreg2] >>= State.regs[srcreg2];
6150}
6151
6152// 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
61538.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
6154"cmp_lsr"
6155*am33
6156{
6157 int dstreg1, dstreg2;
6158 signed int temp;
6159
6160 PC = cia;
6161 dstreg1 = translate_rreg (SD_, RN1);
6162 dstreg2 = translate_rreg (SD_, RN2);
6163
6164 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6165 State.regs[dstreg2] >>= IMM4;
6166}
6167
6168
6169// 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
61708.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
6171"cmp_asl"
6172*am33
6173{
6174 int srcreg2, dstreg1, dstreg2;
6175
6176 PC = cia;
6177 srcreg2 = translate_rreg (SD_, RM2);
6178 dstreg1 = translate_rreg (SD_, RN1);
6179 dstreg2 = translate_rreg (SD_, RN2);
6180
6181 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6182 State.regs[dstreg2] <<= State.regs[srcreg2];
6183}
6184
6185// 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
61868.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
6187"cmp_asl"
6188*am33
6189{
6190 int dstreg1, dstreg2;
6191 signed int temp;
6192
6193 PC = cia;
6194 dstreg1 = translate_rreg (SD_, RN1);
6195 dstreg2 = translate_rreg (SD_, RN2);
6196
6197 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6198 State.regs[dstreg2] <<= IMM4;
6199}
6200
6201// 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
62028.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
6203"sub_add"
6204*am33
6205{
6206 int srcreg2, dstreg1, dstreg2;
6207 int result1;
6208
6209 PC = cia;
6210 srcreg2 = translate_rreg (SD_, RM2);
6211 dstreg1 = translate_rreg (SD_, RN1);
6212 dstreg2 = translate_rreg (SD_, RN2);
6213
6214 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6215 State.regs[dstreg2] += State.regs[srcreg2];
6216 State.regs[dstreg1] = result1;
6217}
6218
6219// 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
62208.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
6221"sub_add"
6222*am33
6223{
6224 int dstreg1, dstreg2;
6225 int result1;
6226
6227 PC = cia;
6228 dstreg1 = translate_rreg (SD_, RN1);
6229 dstreg2 = translate_rreg (SD_, RN2);
6230
6231 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6232 State.regs[dstreg2] += EXTEND4 (IMM4);
6233 State.regs[dstreg1] = result1;
6234}
6235
6236// 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
62378.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
6238"sub_sub"
6239*am33
6240{
6241 int srcreg2, dstreg1, dstreg2;
6242 int result1;
6243
6244 PC = cia;
6245 srcreg2 = translate_rreg (SD_, RM2);
6246 dstreg1 = translate_rreg (SD_, RN1);
6247 dstreg2 = translate_rreg (SD_, RN2);
6248
6249 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6250 State.regs[dstreg2] -= State.regs[srcreg2];
6251 State.regs[dstreg1] = result1;
6252}
6253
6254// 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
62558.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
6256"sub_sub"
6257*am33
6258{
6259 int dstreg1, dstreg2;
6260 int result1;
6261
6262 PC = cia;
6263 dstreg1 = translate_rreg (SD_, RN1);
6264 dstreg2 = translate_rreg (SD_, RN2);
6265
6266 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6267 State.regs[dstreg2] -= EXTEND4 (IMM4);
6268 State.regs[dstreg1] = result1;
6269}
6270
6271// 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
62728.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
6273"sub_cmp"
6274*am33
6275{
6276 int srcreg2, dstreg1, dstreg2;
6277 int result1;
6278
6279 PC = cia;
6280 srcreg2 = translate_rreg (SD_, RM2);
6281 dstreg1 = translate_rreg (SD_, RN1);
6282 dstreg2 = translate_rreg (SD_, RN2);
6283
6284 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6285 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6286}
6287
6288// 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
62898.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
6290"sub_cmp"
6291*am33
6292{
6293 int dstreg1, dstreg2;
6294 int result1;
6295
6296 PC = cia;
6297 dstreg1 = translate_rreg (SD_, RN1);
6298 dstreg2 = translate_rreg (SD_, RN2);
6299
6300 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6301 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6302}
6303
6304// 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
63058.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
6306"sub_mov"
6307*am33
6308{
6309 int srcreg2, dstreg1, dstreg2;
6310 int result1;
6311
6312 PC = cia;
6313 srcreg2 = translate_rreg (SD_, RM2);
6314 dstreg1 = translate_rreg (SD_, RN1);
6315 dstreg2 = translate_rreg (SD_, RN2);
6316
6317 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6318 State.regs[dstreg2] = State.regs[srcreg2];
6319 State.regs[dstreg1] = result1;
6320}
6321
6322// 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
63238.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
6324"sub_mov"
6325*am33
6326{
6327 int dstreg1, dstreg2;
6328 int result1;
6329
6330 PC = cia;
6331 dstreg1 = translate_rreg (SD_, RN1);
6332 dstreg2 = translate_rreg (SD_, RN2);
6333
6334 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6335 State.regs[dstreg2] = EXTEND4 (IMM4);
6336 State.regs[dstreg1] = result1;
6337}
6338
6339// 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
63408.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
6341"sub_asr"
6342*am33
6343{
6344 int srcreg2, dstreg1, dstreg2;
6345 int result1;
6346 signed int temp;
6347
6348 PC = cia;
6349 srcreg2 = translate_rreg (SD_, RM2);
6350 dstreg1 = translate_rreg (SD_, RN1);
6351 dstreg2 = translate_rreg (SD_, RN2);
6352
6353 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6354 temp = State.regs[dstreg2];
6355 temp >>= State.regs[srcreg2];
6356 State.regs[dstreg2] = temp;
6357 State.regs[dstreg1] = result1;
6358}
6359
6360// 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
63618.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
6362"sub_asr"
6363*am33
6364{
6365 int dstreg1, dstreg2;
6366 int result1;
6367 signed int temp;
6368
6369 PC = cia;
6370 dstreg1 = translate_rreg (SD_, RN1);
6371 dstreg2 = translate_rreg (SD_, RN2);
6372
6373 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6374 temp = State.regs[dstreg2];
6375 temp >>= IMM4;
6376 State.regs[dstreg2] = temp;
6377 State.regs[dstreg1] = result1;
6378}
6379
6380// 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
63818.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
6382"sub_lsr"
6383*am33
6384{
6385 int srcreg2, dstreg1, dstreg2;
6386 int result1;
6387
6388 PC = cia;
6389 srcreg2 = translate_rreg (SD_, RM2);
6390 dstreg1 = translate_rreg (SD_, RN1);
6391 dstreg2 = translate_rreg (SD_, RN2);
6392
6393 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6394 State.regs[dstreg2] >>= State.regs[srcreg2];
6395 State.regs[dstreg1] = result1;
6396}
6397
6398// 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
63998.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
6400"sub_lsr"
6401*am33
6402{
6403 int dstreg1, dstreg2;
6404 int result1;
6405 signed int temp;
6406
6407 PC = cia;
6408 dstreg1 = translate_rreg (SD_, RN1);
6409 dstreg2 = translate_rreg (SD_, RN2);
6410
6411 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6412 State.regs[dstreg2] >>= IMM4;
6413 State.regs[dstreg1] = result1;
6414}
6415
6416
6417// 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
64188.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
6419"sub_asl"
6420*am33
6421{
6422 int srcreg2, dstreg1, dstreg2;
6423 int result1;
6424
6425 PC = cia;
6426 srcreg2 = translate_rreg (SD_, RM2);
6427 dstreg1 = translate_rreg (SD_, RN1);
6428 dstreg2 = translate_rreg (SD_, RN2);
6429
6430 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6431 State.regs[dstreg2] <<= State.regs[srcreg2];
6432 State.regs[dstreg1] = result1;
6433}
6434
6435// 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
64368.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
6437"sub_asl"
6438*am33
6439{
6440 int dstreg1, dstreg2;
6441 int result1;
6442 signed int temp;
6443
6444 PC = cia;
6445 dstreg1 = translate_rreg (SD_, RN1);
6446 dstreg2 = translate_rreg (SD_, RN2);
6447
6448 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6449 State.regs[dstreg2] <<= IMM4;
6450 State.regs[dstreg1] = result1;
6451}
6452
6453// 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
64548.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
6455"mov_add"
6456*am33
6457{
6458 int srcreg2, dstreg1, dstreg2;
6459 int result1;
6460
6461 PC = cia;
6462 srcreg2 = translate_rreg (SD_, RM2);
6463 dstreg1 = translate_rreg (SD_, RN1);
6464 dstreg2 = translate_rreg (SD_, RN2);
6465
6466 result1 = EXTEND4 (IMM4A);
6467 State.regs[dstreg2] += State.regs[srcreg2];
6468 State.regs[dstreg1] = result1;
6469}
6470
6471// 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
64728.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
6473"mov_add"
6474*am33
6475{
6476 int dstreg1, dstreg2;
6477 int result1;
6478
6479 PC = cia;
6480 dstreg1 = translate_rreg (SD_, RN1);
6481 dstreg2 = translate_rreg (SD_, RN2);
6482
6483 result1 = EXTEND4 (IMM4A);
6484 State.regs[dstreg2] += EXTEND4 (IMM4);
6485 State.regs[dstreg1] = result1;
6486}
6487
6488// 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
64898.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
6490"mov_sub"
6491*am33
6492{
6493 int srcreg2, dstreg1, dstreg2;
6494 int result1;
6495
6496 PC = cia;
6497 srcreg2 = translate_rreg (SD_, RM2);
6498 dstreg1 = translate_rreg (SD_, RN1);
6499 dstreg2 = translate_rreg (SD_, RN2);
6500
6501 result1 = EXTEND4 (IMM4A);
6502 State.regs[dstreg2] -= State.regs[srcreg2];
6503 State.regs[dstreg1] = result1;
6504}
6505
6506// 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
65078.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
6508"mov_sub"
6509*am33
6510{
6511 int dstreg1, dstreg2;
6512 int result1;
6513
6514 PC = cia;
6515 dstreg1 = translate_rreg (SD_, RN1);
6516 dstreg2 = translate_rreg (SD_, RN2);
6517
6518 result1 = EXTEND4 (IMM4A);
6519 State.regs[dstreg2] -= EXTEND4 (IMM4);
6520 State.regs[dstreg1] = result1;
6521}
6522
6523// 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
65248.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
6525"mov_cmp"
6526*am33
6527{
6528 int srcreg2, dstreg1, dstreg2;
6529
6530 PC = cia;
6531 srcreg2 = translate_rreg (SD_, RM2);
6532 dstreg1 = translate_rreg (SD_, RN1);
6533 dstreg2 = translate_rreg (SD_, RN2);
6534
6535 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6536 State.regs[dstreg1] = EXTEND4 (IMM4A);
6537}
6538
6539// 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
65408.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
6541"mov_cmp"
6542*am33
6543{
6544 int dstreg1, dstreg2;
6545
6546 PC = cia;
6547 dstreg1 = translate_rreg (SD_, RN1);
6548 dstreg2 = translate_rreg (SD_, RN2);
6549
6550 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6551 State.regs[dstreg1] = EXTEND4 (IMM4A);
6552}
6553
6554// 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
65558.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
6556"mov_mov"
6557*am33
6558{
6559 int srcreg2, dstreg1, dstreg2;
6560 int result1;
6561
6562 PC = cia;
6563 srcreg2 = translate_rreg (SD_, RM2);
6564 dstreg1 = translate_rreg (SD_, RN1);
6565 dstreg2 = translate_rreg (SD_, RN2);
6566
6567 result1 = EXTEND4 (IMM4A);
6568 State.regs[dstreg2] = State.regs[srcreg2];
6569 State.regs[dstreg1] = result1;
6570}
6571
6572// 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
65738.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
6574"mov_mov"
6575*am33
6576{
6577 int dstreg1, dstreg2;
6578 int result1;
6579
6580 PC = cia;
6581 dstreg1 = translate_rreg (SD_, RN1);
6582 dstreg2 = translate_rreg (SD_, RN2);
6583
6584 result1 = EXTEND4 (IMM4A);
6585 State.regs[dstreg2] = EXTEND4 (IMM4);
6586 State.regs[dstreg1] = result1;
6587}
6588
6589// 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
65908.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
6591"mov_asr"
6592*am33
6593{
6594 int srcreg2, dstreg1, dstreg2;
6595 int result1;
6596 signed int temp;
6597
6598 PC = cia;
6599 srcreg2 = translate_rreg (SD_, RM2);
6600 dstreg1 = translate_rreg (SD_, RN1);
6601 dstreg2 = translate_rreg (SD_, RN2);
6602
6603 result1 = EXTEND4 (IMM4A);
6604 temp = State.regs[dstreg2];
6605 temp >>= State.regs[srcreg2];
6606 State.regs[dstreg2] = temp;
6607 State.regs[dstreg1] = result1;
6608}
6609
6610// 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
66118.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
6612"mov_asr"
6613*am33
6614{
6615 int dstreg1, dstreg2;
6616 int result1;
6617 signed int temp;
6618
6619 PC = cia;
6620 dstreg1 = translate_rreg (SD_, RN1);
6621 dstreg2 = translate_rreg (SD_, RN2);
6622
6623 result1 = EXTEND4 (IMM4A);
6624 temp = State.regs[dstreg2];
6625 temp >>= IMM4;
6626 State.regs[dstreg2] = temp;
6627 State.regs[dstreg1] = result1;
6628}
6629
6630// 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
66318.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
6632"mov_lsr"
6633*am33
6634{
6635 int srcreg2, dstreg1, dstreg2;
6636 int result1;
6637
6638 PC = cia;
6639 srcreg2 = translate_rreg (SD_, RM2);
6640 dstreg1 = translate_rreg (SD_, RN1);
6641 dstreg2 = translate_rreg (SD_, RN2);
6642
6643 result1 = EXTEND4 (IMM4A);
6644 State.regs[dstreg2] >>= State.regs[srcreg2];
6645 State.regs[dstreg1] = result1;
6646}
6647
6648// 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
66498.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
6650"mov_lsr"
6651*am33
6652{
6653 int dstreg1, dstreg2;
6654 int result1;
6655 signed int temp;
6656
6657 PC = cia;
6658 dstreg1 = translate_rreg (SD_, RN1);
6659 dstreg2 = translate_rreg (SD_, RN2);
6660
6661 result1 = EXTEND4 (IMM4A);
6662 State.regs[dstreg2] >>= IMM4;
6663 State.regs[dstreg1] = result1;
6664}
6665
6666
6667// 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
66688.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
6669"mov_asl"
6670*am33
6671{
6672 int srcreg2, dstreg1, dstreg2;
6673 int result1;
6674
6675 PC = cia;
6676 srcreg2 = translate_rreg (SD_, RM2);
6677 dstreg1 = translate_rreg (SD_, RN1);
6678 dstreg2 = translate_rreg (SD_, RN2);
6679
6680 result1 = EXTEND4 (IMM4A);
6681 State.regs[dstreg2] <<= State.regs[srcreg2];
6682 State.regs[dstreg1] = result1;
6683}
6684
6685// 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
66868.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
6687"mov_asl"
6688*am33
6689{
6690 int dstreg1, dstreg2;
6691 int result1;
6692 signed int temp;
6693
6694 PC = cia;
6695 dstreg1 = translate_rreg (SD_, RN1);
6696 dstreg2 = translate_rreg (SD_, RN2);
6697
6698 result1 = EXTEND4 (IMM4A);
6699 State.regs[dstreg2] <<= IMM4;
6700 State.regs[dstreg1] = result1;
6701}
6702
6703// 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
67048.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
6705"and_add"
6706*am33
6707{
6708 int srcreg1, srcreg2, dstreg1, dstreg2;
6709 int result1;
6710
6711 PC = cia;
6712 srcreg1 = translate_rreg (SD_, RM1);
6713 srcreg2 = translate_rreg (SD_, RM2);
6714 dstreg1 = translate_rreg (SD_, RN1);
6715 dstreg2 = translate_rreg (SD_, RN2);
6716
6717 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6718 State.regs[dstreg2] += State.regs[srcreg2];
6719 State.regs[dstreg1] = result1;
6720}
6721
6722// 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
67238.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
6724"and_add"
6725*am33
6726{
6727 int srcreg1, dstreg1, dstreg2;
6728 int result1;
6729
6730 PC = cia;
6731 srcreg1 = translate_rreg (SD_, RM1);
6732 dstreg1 = translate_rreg (SD_, RN1);
6733 dstreg2 = translate_rreg (SD_, RN2);
6734
6735 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6736 State.regs[dstreg2] += EXTEND4 (IMM4);
6737 State.regs[dstreg1] = result1;
6738}
6739
6740// 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
67418.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
6742"and_sub"
6743*am33
6744{
6745 int srcreg1, srcreg2, dstreg1, dstreg2;
6746 int result1;
6747
6748 PC = cia;
6749 srcreg1 = translate_rreg (SD_, RM1);
6750 srcreg2 = translate_rreg (SD_, RM2);
6751 dstreg1 = translate_rreg (SD_, RN1);
6752 dstreg2 = translate_rreg (SD_, RN2);
6753
6754 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6755 State.regs[dstreg2] -= State.regs[srcreg2];
6756 State.regs[dstreg1] = result1;
6757}
6758
6759// 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
67608.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
6761"and_sub"
6762*am33
6763{
6764 int srcreg1, dstreg1, dstreg2;
6765 int result1;
6766
6767 PC = cia;
6768 srcreg1 = translate_rreg (SD_, RM1);
6769 dstreg1 = translate_rreg (SD_, RN1);
6770 dstreg2 = translate_rreg (SD_, RN2);
6771
6772 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6773 State.regs[dstreg2] -= EXTEND4 (IMM4);
6774 State.regs[dstreg1] = result1;
6775}
6776
6777// 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
67788.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
6779"and_cmp"
6780*am33
6781{
6782 int srcreg1, srcreg2, dstreg1, dstreg2;
6783
6784 PC = cia;
6785 srcreg1 = translate_rreg (SD_, RM1);
6786 srcreg2 = translate_rreg (SD_, RM2);
6787 dstreg1 = translate_rreg (SD_, RN1);
6788 dstreg2 = translate_rreg (SD_, RN2);
6789
6790 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6791 State.regs[dstreg1] &= State.regs[srcreg1];
6792}
6793
6794// 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
67958.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
6796"and_cmp"
6797*am33
6798{
6799 int srcreg1, dstreg1, dstreg2;
6800
6801 PC = cia;
6802 srcreg1 = translate_rreg (SD_, RM1);
6803 dstreg1 = translate_rreg (SD_, RN1);
6804 dstreg2 = translate_rreg (SD_, RN2);
6805
6806 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6807 State.regs[dstreg1] &= State.regs[srcreg1];
6808}
6809
6810// 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
68118.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
6812"and_mov"
6813*am33
6814{
6815 int srcreg1, srcreg2, dstreg1, dstreg2;
6816 int result1;
6817
6818 PC = cia;
6819 srcreg1 = translate_rreg (SD_, RM1);
6820 srcreg2 = translate_rreg (SD_, RM2);
6821 dstreg1 = translate_rreg (SD_, RN1);
6822 dstreg2 = translate_rreg (SD_, RN2);
6823
6824 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6825 State.regs[dstreg2] = State.regs[srcreg2];
6826 State.regs[dstreg1] = result1;
6827}
6828
6829// 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
68308.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
6831"and_mov"
6832*am33
6833{
6834 int srcreg1, dstreg1, dstreg2;
6835 int result1;
6836
6837 PC = cia;
6838 srcreg1 = translate_rreg (SD_, RM1);
6839 dstreg1 = translate_rreg (SD_, RN1);
6840 dstreg2 = translate_rreg (SD_, RN2);
6841
6842 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6843 State.regs[dstreg2] = EXTEND4 (IMM4);
6844 State.regs[dstreg1] = result1;
6845}
6846
6847// 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
68488.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
6849"and_asr"
6850*am33
6851{
6852 int srcreg1, srcreg2, dstreg1, dstreg2;
6853 int result1;
6854 signed int temp;
6855
6856 PC = cia;
6857 srcreg1 = translate_rreg (SD_, RM1);
6858 srcreg2 = translate_rreg (SD_, RM2);
6859 dstreg1 = translate_rreg (SD_, RN1);
6860 dstreg2 = translate_rreg (SD_, RN2);
6861
6862 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6863 temp = State.regs[dstreg2];
6864 temp >>= State.regs[srcreg2];
6865 State.regs[dstreg2] = temp;
6866 State.regs[dstreg1] = result1;
6867}
6868
6869// 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
68708.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
6871"and_asr"
6872*am33
6873{
6874 int srcreg1, dstreg1, dstreg2;
6875 int result1;
6876 signed int temp;
6877
6878 PC = cia;
6879 srcreg1 = translate_rreg (SD_, RM1);
6880 dstreg1 = translate_rreg (SD_, RN1);
6881 dstreg2 = translate_rreg (SD_, RN2);
6882
6883 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6884 temp = State.regs[dstreg2];
6885 temp >>= IMM4;
6886 State.regs[dstreg2] = temp;
6887 State.regs[dstreg1] = result1;
6888}
6889
6890// 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
68918.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
6892"and_lsr"
6893*am33
6894{
6895 int srcreg1, srcreg2, dstreg1, dstreg2;
6896 int result1;
6897
6898 PC = cia;
6899 srcreg1 = translate_rreg (SD_, RM1);
6900 srcreg2 = translate_rreg (SD_, RM2);
6901 dstreg1 = translate_rreg (SD_, RN1);
6902 dstreg2 = translate_rreg (SD_, RN2);
6903
6904 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6905 State.regs[dstreg2] >>= State.regs[srcreg2];
6906 State.regs[dstreg1] = result1;
6907}
6908
6909// 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
69108.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
6911"and_lsr"
6912*am33
6913{
6914 int srcreg1, dstreg1, dstreg2;
6915 int result1;
6916 signed int temp;
6917
6918 PC = cia;
6919 srcreg1 = translate_rreg (SD_, RM1);
6920 dstreg1 = translate_rreg (SD_, RN1);
6921 dstreg2 = translate_rreg (SD_, RN2);
6922
6923 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6924 State.regs[dstreg2] >>= IMM4;
6925 State.regs[dstreg1] = result1;
6926}
6927
6928
6929// 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
69308.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
6931"and_asl"
6932*am33
6933{
6934 int srcreg1, srcreg2, dstreg1, dstreg2;
6935 int result1;
6936
6937 PC = cia;
6938 srcreg1 = translate_rreg (SD_, RM1);
6939 srcreg2 = translate_rreg (SD_, RM2);
6940 dstreg1 = translate_rreg (SD_, RN1);
6941 dstreg2 = translate_rreg (SD_, RN2);
6942
6943 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6944 State.regs[dstreg2] <<= State.regs[srcreg2];
6945 State.regs[dstreg1] = result1;
6946}
6947
6948// 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
69498.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
6950"and_asl"
6951*am33
6952{
6953 int srcreg1, dstreg1, dstreg2;
6954 int result1;
6955 signed int temp;
6956
6957 PC = cia;
6958 srcreg1 = translate_rreg (SD_, RM1);
6959 dstreg1 = translate_rreg (SD_, RN1);
6960 dstreg2 = translate_rreg (SD_, RN2);
6961
6962 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6963 State.regs[dstreg2] <<= IMM4;
6964 State.regs[dstreg1] = result1;
6965}
6966
6967// 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
69688.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
6969"dmach_add"
6970*am33
6971{
6972 int srcreg1, srcreg2, dstreg1, dstreg2;
6973 long temp, temp2, sum;
6974
6975 PC = cia;
6976 srcreg1 = translate_rreg (SD_, RM1);
6977 srcreg2 = translate_rreg (SD_, RM2);
6978 dstreg1 = translate_rreg (SD_, RN1);
6979 dstreg2 = translate_rreg (SD_, RN2);
6980
6981 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6982 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6983 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6984 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6985 sum = temp + temp2 + State.regs[REG_MCRL];
6986
6987 State.regs[dstreg2] += State.regs[srcreg2];
6988 State.regs[dstreg1] = sum;
6989}
6990
6991// 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
69928.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
6993"dmach_add"
6994*am33
6995{
6996 int srcreg1, dstreg1, dstreg2;
6997 long temp, temp2, sum;
6998
6999 PC = cia;
7000 srcreg1 = translate_rreg (SD_, RM1);
7001 dstreg1 = translate_rreg (SD_, RN1);
7002 dstreg2 = translate_rreg (SD_, RN2);
7003
7004 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7005 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7006 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7007 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7008 sum = temp + temp2 + State.regs[REG_MCRL];
7009
7010 State.regs[dstreg2] += EXTEND4 (IMM4);
7011 State.regs[dstreg1] = sum;
7012}
7013
7014// 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
70158.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
7016"dmach_sub"
7017*am33
7018{
7019 int srcreg1, srcreg2, dstreg1, dstreg2;
7020 long temp, temp2, sum;
7021
7022 PC = cia;
7023 srcreg1 = translate_rreg (SD_, RM1);
7024 srcreg2 = translate_rreg (SD_, RM2);
7025 dstreg1 = translate_rreg (SD_, RN1);
7026 dstreg2 = translate_rreg (SD_, RN2);
7027
7028 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7029 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7030 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7031 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7032 sum = temp + temp2 + State.regs[REG_MCRL];
7033
7034 State.regs[dstreg2] -= State.regs[srcreg2];
7035 State.regs[dstreg1] = sum;
7036}
7037
7038// 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
70398.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
7040"dmach_sub"
7041*am33
7042{
7043 int srcreg1, dstreg1, dstreg2;
7044 long temp, temp2, sum;
7045
7046 PC = cia;
7047 srcreg1 = translate_rreg (SD_, RM1);
7048 dstreg1 = translate_rreg (SD_, RN1);
7049 dstreg2 = translate_rreg (SD_, RN2);
7050
7051 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7052 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7053 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7054 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7055 sum = temp + temp2 + State.regs[REG_MCRL];
7056
7057 State.regs[dstreg2] -= EXTEND4 (IMM4);
7058 State.regs[dstreg1] = sum;
7059}
7060
7061// 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
70628.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
7063"dmach_cmp"
7064*am33
7065{
7066 int srcreg1, srcreg2, dstreg1, dstreg2;
7067 long temp, temp2, sum;
7068
7069 PC = cia;
7070 srcreg1 = translate_rreg (SD_, RM1);
7071 srcreg2 = translate_rreg (SD_, RM2);
7072 dstreg1 = translate_rreg (SD_, RN1);
7073 dstreg2 = translate_rreg (SD_, RN2);
7074
7075 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7076 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7077 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7078 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7079 sum = temp + temp2 + State.regs[REG_MCRL];
7080
7081 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7082 State.regs[dstreg1] = sum;
7083}
7084
7085// 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
70868.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
7087"dmach_cmp"
7088*am33
7089{
7090 int srcreg1, dstreg1, dstreg2;
7091 long temp, temp2, sum;
7092
7093 PC = cia;
7094 srcreg1 = translate_rreg (SD_, RM1);
7095 dstreg1 = translate_rreg (SD_, RN1);
7096 dstreg2 = translate_rreg (SD_, RN2);
7097
7098 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7099 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7100 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7101 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7102 sum = temp + temp2 + State.regs[REG_MCRL];
7103
7104 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7105 State.regs[dstreg1] = sum;
7106}
7107
7108// 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
71098.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
7110"dmach_mov"
7111*am33
7112{
7113 int srcreg1, srcreg2, dstreg1, dstreg2;
7114 long temp, temp2, sum;
7115
7116 PC = cia;
7117 srcreg1 = translate_rreg (SD_, RM1);
7118 srcreg2 = translate_rreg (SD_, RM2);
7119 dstreg1 = translate_rreg (SD_, RN1);
7120 dstreg2 = translate_rreg (SD_, RN2);
7121
7122 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7123 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7124 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7125 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7126 sum = temp + temp2 + State.regs[REG_MCRL];
7127
7128 State.regs[dstreg2] = State.regs[srcreg2];
7129 State.regs[dstreg1] = sum;
7130}
7131
7132// 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
71338.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
7134"dmach_mov"
7135*am33
7136{
7137 int srcreg1, dstreg1, dstreg2;
7138 long temp, temp2, sum;
7139
7140 PC = cia;
7141 srcreg1 = translate_rreg (SD_, RM1);
7142 dstreg1 = translate_rreg (SD_, RN1);
7143 dstreg2 = translate_rreg (SD_, RN2);
7144
7145 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7146 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7147 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7148 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7149 sum = temp + temp2 + State.regs[REG_MCRL];
7150
7151 State.regs[dstreg2] = EXTEND4 (IMM4);
7152 State.regs[dstreg1] = sum;
7153}
7154
7155// 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
71568.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
7157"dmach_asr"
7158*am33
7159{
7160 int srcreg1, srcreg2, dstreg1, dstreg2;
7161 long temp, temp2, sum;
7162
7163 PC = cia;
7164 srcreg1 = translate_rreg (SD_, RM1);
7165 srcreg2 = translate_rreg (SD_, RM2);
7166 dstreg1 = translate_rreg (SD_, RN1);
7167 dstreg2 = translate_rreg (SD_, RN2);
7168
7169 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7170 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7171 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7172 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7173 sum = temp + temp2 + State.regs[REG_MCRL];
7174
7175 temp = State.regs[dstreg2];
7176 temp >>= State.regs[srcreg2];
7177 State.regs[dstreg2] = temp;
7178 State.regs[dstreg1] = sum;
7179}
7180
7181// 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
71828.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
7183"dmach_asr"
7184*am33
7185{
7186 int srcreg1, dstreg1, dstreg2;
7187 long temp, temp2, sum;
7188
7189 PC = cia;
7190 srcreg1 = translate_rreg (SD_, RM1);
7191 dstreg1 = translate_rreg (SD_, RN1);
7192 dstreg2 = translate_rreg (SD_, RN2);
7193
7194 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7195 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7196 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7197 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7198 sum = temp + temp2 + State.regs[REG_MCRL];
7199
7200 temp = State.regs[dstreg2];
7201 temp >>= IMM4;
7202 State.regs[dstreg2] = temp;
7203 State.regs[dstreg1] = sum;
7204}
7205
7206// 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
72078.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
7208"dmach_lsr"
7209*am33
7210{
7211 int srcreg1, srcreg2, dstreg1, dstreg2;
7212 long temp, temp2, sum;
7213
7214 PC = cia;
7215 srcreg1 = translate_rreg (SD_, RM1);
7216 srcreg2 = translate_rreg (SD_, RM2);
7217 dstreg1 = translate_rreg (SD_, RN1);
7218 dstreg2 = translate_rreg (SD_, RN2);
7219
7220 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7221 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7222 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7223 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7224 sum = temp + temp2 + State.regs[REG_MCRL];
7225
7226 State.regs[dstreg2] >>= State.regs[srcreg2];
7227 State.regs[dstreg1] = sum;
7228}
7229
7230// 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
72318.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
7232"dmach_lsr"
7233*am33
7234{
7235 int srcreg1, dstreg1, dstreg2;
7236 long temp, temp2, sum;
7237
7238 PC = cia;
7239 srcreg1 = translate_rreg (SD_, RM1);
7240 dstreg1 = translate_rreg (SD_, RN1);
7241 dstreg2 = translate_rreg (SD_, RN2);
7242
7243 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7244 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7245 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7246 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7247 sum = temp + temp2 + State.regs[REG_MCRL];
7248
7249 State.regs[dstreg2] >>= IMM4;
7250 State.regs[dstreg1] = sum;
7251}
7252
7253
7254// 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
72558.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
7256"dmach_asl"
7257*am33
7258{
7259 int srcreg1, srcreg2, dstreg1, dstreg2;
7260 long temp, temp2, sum;
7261
7262 PC = cia;
7263 srcreg1 = translate_rreg (SD_, RM1);
7264 srcreg2 = translate_rreg (SD_, RM2);
7265 dstreg1 = translate_rreg (SD_, RN1);
7266 dstreg2 = translate_rreg (SD_, RN2);
7267
7268 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7269 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7270 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7271 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7272 sum = temp + temp2 + State.regs[REG_MCRL];
7273
7274 State.regs[dstreg2] <<= State.regs[srcreg2];
7275 State.regs[dstreg1] = sum;
7276}
7277
7278// 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
72798.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
7280"dmach_asl"
7281*am33
7282{
7283 int srcreg1, dstreg1, dstreg2;
7284 long temp, temp2, sum;
7285
7286 PC = cia;
7287 srcreg1 = translate_rreg (SD_, RM1);
7288 dstreg1 = translate_rreg (SD_, RN1);
7289 dstreg2 = translate_rreg (SD_, RN2);
7290
7291 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7292 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7293 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7294 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7295 sum = temp + temp2 + State.regs[REG_MCRL];
7296
7297 State.regs[dstreg2] <<= IMM4;
7298 State.regs[dstreg1] = sum;
7299}
7300
7301// 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
73028.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
7303"xor_add"
7304*am33
7305{
7306 int srcreg1, srcreg2, dstreg1, dstreg2;
7307 int result1;
7308
7309 PC = cia;
7310 srcreg1 = translate_rreg (SD_, RM1);
7311 srcreg2 = translate_rreg (SD_, RM2);
7312 dstreg1 = translate_rreg (SD_, RN1);
7313 dstreg2 = translate_rreg (SD_, RN2);
7314
7315 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7316 State.regs[dstreg2] += State.regs[srcreg2];
7317 State.regs[dstreg1] = result1;
7318}
7319
7320// 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
73218.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
7322"xor_add"
7323*am33
7324{
7325 int srcreg1, dstreg1, dstreg2;
7326 int result1;
7327
7328 PC = cia;
7329 srcreg1 = translate_rreg (SD_, RM1);
7330 dstreg1 = translate_rreg (SD_, RN1);
7331 dstreg2 = translate_rreg (SD_, RN2);
7332
7333 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7334 State.regs[dstreg2] += EXTEND4 (IMM4);
7335 State.regs[dstreg1] = result1;
7336}
7337
7338// 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
73398.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
7340"xor_sub"
7341*am33
7342{
7343 int srcreg1, srcreg2, dstreg1, dstreg2;
7344 int result1;
7345
7346 PC = cia;
7347 srcreg1 = translate_rreg (SD_, RM1);
7348 srcreg2 = translate_rreg (SD_, RM2);
7349 dstreg1 = translate_rreg (SD_, RN1);
7350 dstreg2 = translate_rreg (SD_, RN2);
7351
7352 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7353 State.regs[dstreg2] -= State.regs[srcreg2];
7354 State.regs[dstreg1] = result1;
7355}
7356
7357// 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
73588.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
7359"xor_sub"
7360*am33
7361{
7362 int srcreg1, dstreg1, dstreg2;
7363 int result1;
7364
7365 PC = cia;
7366 srcreg1 = translate_rreg (SD_, RM1);
7367 dstreg1 = translate_rreg (SD_, RN1);
7368 dstreg2 = translate_rreg (SD_, RN2);
7369
7370 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7371 State.regs[dstreg2] -= EXTEND4 (IMM4);
7372 State.regs[dstreg1] = result1;
7373}
7374
7375// 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
73768.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
7377"xor_cmp"
7378*am33
7379{
7380 int srcreg1, srcreg2, dstreg1, dstreg2;
7381
7382 PC = cia;
7383 srcreg1 = translate_rreg (SD_, RM1);
7384 srcreg2 = translate_rreg (SD_, RM2);
7385 dstreg1 = translate_rreg (SD_, RN1);
7386 dstreg2 = translate_rreg (SD_, RN2);
7387
7388 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7389 State.regs[dstreg1] ^= State.regs[srcreg1];
7390}
7391
7392// 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
73938.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
7394"xor_cmp"
7395*am33
7396{
7397 int srcreg1, dstreg1, dstreg2;
7398
7399 PC = cia;
7400 srcreg1 = translate_rreg (SD_, RM1);
7401 dstreg1 = translate_rreg (SD_, RN1);
7402 dstreg2 = translate_rreg (SD_, RN2);
7403
7404 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7405 State.regs[dstreg1] ^= State.regs[srcreg1];
7406}
7407
7408// 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
74098.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
7410"xor_mov"
7411*am33
7412{
7413 int srcreg1, srcreg2, dstreg1, dstreg2;
7414 int result1;
7415
7416 PC = cia;
7417 srcreg1 = translate_rreg (SD_, RM1);
7418 srcreg2 = translate_rreg (SD_, RM2);
7419 dstreg1 = translate_rreg (SD_, RN1);
7420 dstreg2 = translate_rreg (SD_, RN2);
7421
7422 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7423 State.regs[dstreg2] = State.regs[srcreg2];
7424 State.regs[dstreg1] = result1;
7425}
7426
7427// 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
74288.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
7429"xor_mov"
7430*am33
7431{
7432 int srcreg1, dstreg1, dstreg2;
7433 int result1;
7434
7435 PC = cia;
7436 srcreg1 = translate_rreg (SD_, RM1);
7437 dstreg1 = translate_rreg (SD_, RN1);
7438 dstreg2 = translate_rreg (SD_, RN2);
7439
7440 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7441 State.regs[dstreg2] = EXTEND4 (IMM4);
7442 State.regs[dstreg1] = result1;
7443}
7444
7445// 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
74468.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
7447"xor_asr"
7448*am33
7449{
7450 int srcreg1, srcreg2, dstreg1, dstreg2;
7451 int result1;
7452 signed int temp;
7453
7454 PC = cia;
7455 srcreg1 = translate_rreg (SD_, RM1);
7456 srcreg2 = translate_rreg (SD_, RM2);
7457 dstreg1 = translate_rreg (SD_, RN1);
7458 dstreg2 = translate_rreg (SD_, RN2);
7459
7460 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7461 temp = State.regs[dstreg2];
7462 temp >>= State.regs[srcreg2];
7463 State.regs[dstreg2] = temp;
7464 State.regs[dstreg1] = result1;
7465}
7466
7467// 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
74688.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
7469"xor_asr"
7470*am33
7471{
7472 int srcreg1, dstreg1, dstreg2;
7473 int result1;
7474 signed int temp;
7475
7476 PC = cia;
7477 srcreg1 = translate_rreg (SD_, RM1);
7478 dstreg1 = translate_rreg (SD_, RN1);
7479 dstreg2 = translate_rreg (SD_, RN2);
7480
7481 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7482 temp = State.regs[dstreg2];
7483 temp >>= IMM4;
7484 State.regs[dstreg2] = temp;
7485 State.regs[dstreg1] = result1;
7486}
7487
7488// 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
74898.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
7490"xor_lsr"
7491*am33
7492{
7493 int srcreg1, srcreg2, dstreg1, dstreg2;
7494 int result1;
7495
7496 PC = cia;
7497 srcreg1 = translate_rreg (SD_, RM1);
7498 srcreg2 = translate_rreg (SD_, RM2);
7499 dstreg1 = translate_rreg (SD_, RN1);
7500 dstreg2 = translate_rreg (SD_, RN2);
7501
7502 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7503 State.regs[dstreg2] >>= State.regs[srcreg2];
7504 State.regs[dstreg1] = result1;
7505}
7506
7507// 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
75088.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
7509"xor_lsr"
7510*am33
7511{
7512 int srcreg1, dstreg1, dstreg2;
7513 int result1;
7514 signed int temp;
7515
7516 PC = cia;
7517 srcreg1 = translate_rreg (SD_, RM1);
7518 dstreg1 = translate_rreg (SD_, RN1);
7519 dstreg2 = translate_rreg (SD_, RN2);
7520
7521 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7522 State.regs[dstreg2] >>= IMM4;
7523 State.regs[dstreg1] = result1;
7524}
7525
7526
7527// 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
75288.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
7529"xor_asl"
7530*am33
7531{
7532 int srcreg1, srcreg2, dstreg1, dstreg2;
7533 int result1;
7534
7535 PC = cia;
7536 srcreg1 = translate_rreg (SD_, RM1);
7537 srcreg2 = translate_rreg (SD_, RM2);
7538 dstreg1 = translate_rreg (SD_, RN1);
7539 dstreg2 = translate_rreg (SD_, RN2);
7540
7541 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7542 State.regs[dstreg2] <<= State.regs[srcreg2];
7543 State.regs[dstreg1] = result1;
7544}
7545
7546// 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
75478.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
7548"xor_asl"
7549*am33
7550{
7551 int srcreg1, dstreg1, dstreg2;
7552 int result1;
7553 signed int temp;
7554
7555 PC = cia;
7556 srcreg1 = translate_rreg (SD_, RM1);
7557 dstreg1 = translate_rreg (SD_, RN1);
7558 dstreg2 = translate_rreg (SD_, RN2);
7559
7560 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7561 State.regs[dstreg2] <<= IMM4;
7562 State.regs[dstreg1] = result1;
7563}
7564
7565// 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
75668.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
7567"swhw_add"
7568*am33
7569{
7570 int srcreg1, srcreg2, dstreg1, dstreg2;
7571 int result1;
7572
7573 PC = cia;
7574 srcreg1 = translate_rreg (SD_, RM1);
7575 srcreg2 = translate_rreg (SD_, RM2);
7576 dstreg1 = translate_rreg (SD_, RN1);
7577 dstreg2 = translate_rreg (SD_, RN2);
7578
7579 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7580 State.regs[dstreg2] += State.regs[srcreg2];
7581 State.regs[dstreg1] = result1;
7582}
7583
7584// 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
75858.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
7586"swhw_add"
7587*am33
7588{
7589 int srcreg1, dstreg1, dstreg2;
7590 int result1;
7591
7592 PC = cia;
7593 srcreg1 = translate_rreg (SD_, RM1);
7594 dstreg1 = translate_rreg (SD_, RN1);
7595 dstreg2 = translate_rreg (SD_, RN2);
7596
7597 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7598 | ((State.regs[srcreg1] >> 16) & 0xffff));
7599 State.regs[dstreg2] += EXTEND4 (IMM4);
7600 State.regs[dstreg1] = result1;
7601}
7602
7603// 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
76048.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
7605"swhw_sub"
7606*am33
7607{
7608 int srcreg1, srcreg2, dstreg1, dstreg2;
7609 int result1;
7610
7611 PC = cia;
7612 srcreg1 = translate_rreg (SD_, RM1);
7613 srcreg2 = translate_rreg (SD_, RM2);
7614 dstreg1 = translate_rreg (SD_, RN1);
7615 dstreg2 = translate_rreg (SD_, RN2);
7616
7617 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7618 | ((State.regs[srcreg1] >> 16) & 0xffff));
7619 State.regs[dstreg2] -= State.regs[srcreg2];
7620 State.regs[dstreg1] = result1;
7621}
7622
7623// 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
76248.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
7625"swhw_sub"
7626*am33
7627{
7628 int srcreg1, dstreg1, dstreg2;
7629 int result1;
7630
7631 PC = cia;
7632 srcreg1 = translate_rreg (SD_, RM1);
7633 dstreg1 = translate_rreg (SD_, RN1);
7634 dstreg2 = translate_rreg (SD_, RN2);
7635
7636 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7637 | ((State.regs[srcreg1] >> 16) & 0xffff));
7638 State.regs[dstreg2] -= EXTEND4 (IMM4);
7639 State.regs[dstreg1] = result1;
7640}
7641
7642// 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
76438.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
7644"swhw_cmp"
7645*am33
7646{
7647 int srcreg1, srcreg2, dstreg1, dstreg2;
7648
7649 PC = cia;
7650 srcreg1 = translate_rreg (SD_, RM1);
7651 srcreg2 = translate_rreg (SD_, RM2);
7652 dstreg1 = translate_rreg (SD_, RN1);
7653 dstreg2 = translate_rreg (SD_, RN2);
7654
7655 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7656 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7657 | ((State.regs[srcreg1] >> 16) & 0xffff));
7658}
7659
7660// 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
76618.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
7662"swhw_cmp"
7663*am33
7664{
7665 int srcreg1, dstreg1, dstreg2;
7666
7667 PC = cia;
7668 srcreg1 = translate_rreg (SD_, RM1);
7669 dstreg1 = translate_rreg (SD_, RN1);
7670 dstreg2 = translate_rreg (SD_, RN2);
7671
7672 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7673 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7674 | ((State.regs[srcreg1] >> 16) & 0xffff));
7675}
7676
7677// 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
76788.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
7679"swhw_mov"
7680*am33
7681{
7682 int srcreg1, srcreg2, dstreg1, dstreg2;
7683 int result1;
7684
7685 PC = cia;
7686 srcreg1 = translate_rreg (SD_, RM1);
7687 srcreg2 = translate_rreg (SD_, RM2);
7688 dstreg1 = translate_rreg (SD_, RN1);
7689 dstreg2 = translate_rreg (SD_, RN2);
7690
7691 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7692 | ((State.regs[srcreg1] >> 16) & 0xffff));
7693 State.regs[dstreg2] = State.regs[srcreg2];
7694 State.regs[dstreg1] = result1;
7695}
7696
7697// 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
76988.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
7699"swhw_mov"
7700*am33
7701{
7702 int srcreg1, dstreg1, dstreg2;
7703 int result1;
7704
7705 PC = cia;
7706 srcreg1 = translate_rreg (SD_, RM1);
7707 dstreg1 = translate_rreg (SD_, RN1);
7708 dstreg2 = translate_rreg (SD_, RN2);
7709
7710 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7711 | ((State.regs[srcreg1] >> 16) & 0xffff));
7712 State.regs[dstreg2] = EXTEND4 (IMM4);
7713 State.regs[dstreg1] = result1;
7714}
7715
7716// 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
77178.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
7718"swhw_asr"
7719*am33
7720{
7721 int srcreg1, srcreg2, dstreg1, dstreg2;
7722 int result1;
7723 signed int temp;
7724
7725 PC = cia;
7726 srcreg1 = translate_rreg (SD_, RM1);
7727 srcreg2 = translate_rreg (SD_, RM2);
7728 dstreg1 = translate_rreg (SD_, RN1);
7729 dstreg2 = translate_rreg (SD_, RN2);
7730
7731 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7732 | ((State.regs[srcreg1] >> 16) & 0xffff));
7733 temp = State.regs[dstreg2];
7734 temp >>= State.regs[srcreg2];
7735 State.regs[dstreg2] = temp;
7736 State.regs[dstreg1] = result1;
7737}
7738
7739// 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
77408.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
7741"swhw_asr"
7742*am33
7743{
7744 int srcreg1, dstreg1, dstreg2;
7745 int result1;
7746 signed int temp;
7747
7748 PC = cia;
7749 srcreg1 = translate_rreg (SD_, RM1);
7750 dstreg1 = translate_rreg (SD_, RN1);
7751 dstreg2 = translate_rreg (SD_, RN2);
7752
7753 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7754 | ((State.regs[srcreg1] >> 16) & 0xffff));
7755 temp = State.regs[dstreg2];
7756 temp >>= IMM4;
7757 State.regs[dstreg2] = temp;
7758 State.regs[dstreg1] = result1;
7759}
7760
7761// 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
77628.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
7763"swhw_lsr"
7764*am33
7765{
7766 int srcreg1, srcreg2, dstreg1, dstreg2;
7767 int result1;
7768
7769 PC = cia;
7770 srcreg1 = translate_rreg (SD_, RM1);
7771 srcreg2 = translate_rreg (SD_, RM2);
7772 dstreg1 = translate_rreg (SD_, RN1);
7773 dstreg2 = translate_rreg (SD_, RN2);
7774
7775 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7776 | ((State.regs[srcreg1] >> 16) & 0xffff));
7777 State.regs[dstreg2] >>= State.regs[srcreg2];
7778 State.regs[dstreg1] = result1;
7779}
7780
7781// 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
77828.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
7783"swhw_lsr"
7784*am33
7785{
7786 int srcreg1, dstreg1, dstreg2;
7787 int result1;
7788 signed int temp;
7789
7790 PC = cia;
7791 srcreg1 = translate_rreg (SD_, RM1);
7792 dstreg1 = translate_rreg (SD_, RN1);
7793 dstreg2 = translate_rreg (SD_, RN2);
7794
7795 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7796 | ((State.regs[srcreg1] >> 16) & 0xffff));
7797 State.regs[dstreg2] >>= IMM4;
7798 State.regs[dstreg1] = result1;
7799}
7800
7801
7802// 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
78038.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
7804"swhw_asl"
7805*am33
7806{
7807 int srcreg1, srcreg2, dstreg1, dstreg2;
7808 int result1;
7809
7810 PC = cia;
7811 srcreg1 = translate_rreg (SD_, RM1);
7812 srcreg2 = translate_rreg (SD_, RM2);
7813 dstreg1 = translate_rreg (SD_, RN1);
7814 dstreg2 = translate_rreg (SD_, RN2);
7815
7816 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7817 | ((State.regs[srcreg1] >> 16) & 0xffff));
7818 State.regs[dstreg2] <<= State.regs[srcreg2];
7819 State.regs[dstreg1] = result1;
7820}
7821
7822// 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
78238.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
7824"swhw_asl"
7825*am33
7826{
7827 int srcreg1, dstreg1, dstreg2;
7828 int result1;
7829 signed int temp;
7830
7831 PC = cia;
7832 srcreg1 = translate_rreg (SD_, RM1);
7833 dstreg1 = translate_rreg (SD_, RN1);
7834 dstreg2 = translate_rreg (SD_, RN2);
7835
7836 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7837 | ((State.regs[srcreg1] >> 16) & 0xffff));
7838 State.regs[dstreg2] <<= IMM4;
7839 State.regs[dstreg1] = result1;
7840}
7841
7842// 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
78438.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
7844"or_add"
7845*am33
7846{
7847 int srcreg1, srcreg2, dstreg1, dstreg2;
7848 int result1;
7849
7850 PC = cia;
7851 srcreg1 = translate_rreg (SD_, RM1);
7852 srcreg2 = translate_rreg (SD_, RM2);
7853 dstreg1 = translate_rreg (SD_, RN1);
7854 dstreg2 = translate_rreg (SD_, RN2);
7855
7856 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7857 State.regs[dstreg2] += State.regs[srcreg2];
7858 State.regs[dstreg1] = result1;
7859}
7860
7861// 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
78628.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
7863"or_add"
7864*am33
7865{
7866 int srcreg1, dstreg1, dstreg2;
7867 int result1;
7868
7869 PC = cia;
7870 srcreg1 = translate_rreg (SD_, RM1);
7871 dstreg1 = translate_rreg (SD_, RN1);
7872 dstreg2 = translate_rreg (SD_, RN2);
7873
7874 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7875 State.regs[dstreg2] += EXTEND4 (IMM4);
7876 State.regs[dstreg1] = result1;
7877}
7878
7879// 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
78808.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
7881"or_sub"
7882*am33
7883{
7884 int srcreg1, srcreg2, dstreg1, dstreg2;
7885 int result1;
7886
7887 PC = cia;
7888 srcreg1 = translate_rreg (SD_, RM1);
7889 srcreg2 = translate_rreg (SD_, RM2);
7890 dstreg1 = translate_rreg (SD_, RN1);
7891 dstreg2 = translate_rreg (SD_, RN2);
7892
7893 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7894 State.regs[dstreg2] -= State.regs[srcreg2];
7895 State.regs[dstreg1] = result1;
7896}
7897
7898// 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
78998.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
7900"or_sub"
7901*am33
7902{
7903 int srcreg1, dstreg1, dstreg2;
7904 int result1;
7905
7906 PC = cia;
7907 srcreg1 = translate_rreg (SD_, RM1);
7908 dstreg1 = translate_rreg (SD_, RN1);
7909 dstreg2 = translate_rreg (SD_, RN2);
7910
7911 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7912 State.regs[dstreg2] -= EXTEND4 (IMM4);
7913 State.regs[dstreg1] = result1;
7914}
7915
7916// 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
79178.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
7918"or_cmp"
7919*am33
7920{
7921 int srcreg1, srcreg2, dstreg1, dstreg2;
7922
7923 PC = cia;
7924 srcreg1 = translate_rreg (SD_, RM1);
7925 srcreg2 = translate_rreg (SD_, RM2);
7926 dstreg1 = translate_rreg (SD_, RN1);
7927 dstreg2 = translate_rreg (SD_, RN2);
7928
7929 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7930 State.regs[dstreg1] |= State.regs[srcreg1];
7931}
7932
7933// 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
79348.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
7935"or_cmp"
7936*am33
7937{
7938 int srcreg1, dstreg1, dstreg2;
7939
7940 PC = cia;
7941 srcreg1 = translate_rreg (SD_, RM1);
7942 dstreg1 = translate_rreg (SD_, RN1);
7943 dstreg2 = translate_rreg (SD_, RN2);
7944
7945 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7946 State.regs[dstreg1] |= State.regs[srcreg1];
7947}
7948
7949// 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
79508.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
7951"or_mov"
7952*am33
7953{
7954 int srcreg1, srcreg2, dstreg1, dstreg2;
7955 int result1;
7956
7957 PC = cia;
7958 srcreg1 = translate_rreg (SD_, RM1);
7959 srcreg2 = translate_rreg (SD_, RM2);
7960 dstreg1 = translate_rreg (SD_, RN1);
7961 dstreg2 = translate_rreg (SD_, RN2);
7962
7963 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7964 State.regs[dstreg2] = State.regs[srcreg2];
7965 State.regs[dstreg1] = result1;
7966}
7967
7968// 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
79698.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
7970"or_mov"
7971*am33
7972{
7973 int srcreg1, dstreg1, dstreg2;
7974 int result1;
7975
7976 PC = cia;
7977 srcreg1 = translate_rreg (SD_, RM1);
7978 dstreg1 = translate_rreg (SD_, RN1);
7979 dstreg2 = translate_rreg (SD_, RN2);
7980
7981 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7982 State.regs[dstreg2] = EXTEND4 (IMM4);
7983 State.regs[dstreg1] = result1;
7984}
7985
7986// 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
79878.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
7988"or_asr"
7989*am33
7990{
7991 int srcreg1, srcreg2, dstreg1, dstreg2;
7992 int result1;
7993 signed int temp;
7994
7995 PC = cia;
7996 srcreg1 = translate_rreg (SD_, RM1);
7997 srcreg2 = translate_rreg (SD_, RM2);
7998 dstreg1 = translate_rreg (SD_, RN1);
7999 dstreg2 = translate_rreg (SD_, RN2);
8000
8001 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8002 temp = State.regs[dstreg2];
8003 temp >>= State.regs[srcreg2];
8004 State.regs[dstreg2] = temp;
8005 State.regs[dstreg1] = result1;
8006}
8007
8008// 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
80098.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
8010"or_asr"
8011*am33
8012{
8013 int srcreg1, dstreg1, dstreg2;
8014 int result1;
8015 signed int temp;
8016
8017 PC = cia;
8018 srcreg1 = translate_rreg (SD_, RM1);
8019 dstreg1 = translate_rreg (SD_, RN1);
8020 dstreg2 = translate_rreg (SD_, RN2);
8021
8022 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8023 temp = State.regs[dstreg2];
8024 temp >>= IMM4;
8025 State.regs[dstreg2] = temp;
8026 State.regs[dstreg1] = result1;
8027}
8028
8029// 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
80308.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
8031"or_lsr"
8032*am33
8033{
8034 int srcreg1, srcreg2, dstreg1, dstreg2;
8035 int result1;
8036
8037 PC = cia;
8038 srcreg1 = translate_rreg (SD_, RM1);
8039 srcreg2 = translate_rreg (SD_, RM2);
8040 dstreg1 = translate_rreg (SD_, RN1);
8041 dstreg2 = translate_rreg (SD_, RN2);
8042
8043 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8044 State.regs[dstreg2] >>= State.regs[srcreg2];
8045 State.regs[dstreg1] = result1;
8046}
8047
8048// 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
80498.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
8050"or_lsr"
8051*am33
8052{
8053 int srcreg1, dstreg1, dstreg2;
8054 int result1;
8055 signed int temp;
8056
8057 PC = cia;
8058 srcreg1 = translate_rreg (SD_, RM1);
8059 dstreg1 = translate_rreg (SD_, RN1);
8060 dstreg2 = translate_rreg (SD_, RN2);
8061
8062 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8063 State.regs[dstreg2] >>= IMM4;
8064 State.regs[dstreg1] = result1;
8065}
8066
8067
8068// 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
80698.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
8070"or_asl"
8071*am33
8072{
8073 int srcreg1, srcreg2, dstreg1, dstreg2;
8074 int result1;
8075
8076 PC = cia;
8077 srcreg1 = translate_rreg (SD_, RM1);
8078 srcreg2 = translate_rreg (SD_, RM2);
8079 dstreg1 = translate_rreg (SD_, RN1);
8080 dstreg2 = translate_rreg (SD_, RN2);
8081
8082 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8083 State.regs[dstreg2] <<= State.regs[srcreg2];
8084 State.regs[dstreg1] = result1;
8085}
8086
8087// 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
80888.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
8089"or_asl"
8090*am33
8091{
8092 int srcreg1, dstreg1, dstreg2;
8093 int result1;
8094 signed int temp;
8095
8096 PC = cia;
8097 srcreg1 = translate_rreg (SD_, RM1);
8098 dstreg1 = translate_rreg (SD_, RN1);
8099 dstreg2 = translate_rreg (SD_, RN2);
8100
8101 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8102 State.regs[dstreg2] <<= IMM4;
8103 State.regs[dstreg1] = result1;
8104}
8105
8106// 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
81078.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
8108"sat16_add"
8109*am33
8110{
8111 int srcreg1, srcreg2, dstreg1, dstreg2;
8112 int result1;
8113
8114 PC = cia;
8115 srcreg1 = translate_rreg (SD_, RM1);
8116 srcreg2 = translate_rreg (SD_, RM2);
8117 dstreg1 = translate_rreg (SD_, RN1);
8118 dstreg2 = translate_rreg (SD_, RN2);
8119
8120 if (State.regs[srcreg1] >= 0x7fff)
8121 result1 = 0x7fff;
8122 else if (State.regs[srcreg1] <= 0xffff8000)
8123 result1 = 0xffff8000;
8124 else
8125 result1 = State.regs[srcreg1];
8126
8127 State.regs[dstreg2] += State.regs[srcreg2];
8128 State.regs[dstreg1] = result1;
8129}
8130
8131// 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
81328.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
8133"sat16_add"
8134*am33
8135{
8136 int srcreg1, dstreg1, dstreg2;
8137 int result1;
8138
8139 PC = cia;
8140 srcreg1 = translate_rreg (SD_, RM1);
8141 dstreg1 = translate_rreg (SD_, RN1);
8142 dstreg2 = translate_rreg (SD_, RN2);
8143
8144 if (State.regs[srcreg1] >= 0x7fff)
8145 result1 = 0x7fff;
8146 else if (State.regs[srcreg1] <= 0xffff8000)
8147 result1 = 0xffff8000;
8148 else
8149 result1 = State.regs[srcreg1];
8150
8151 State.regs[dstreg2] += EXTEND4 (IMM4);
8152 State.regs[dstreg1] = result1;
8153}
8154
8155// 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
81568.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
8157"sat16_sub"
8158*am33
8159{
8160 int srcreg1, srcreg2, dstreg1, dstreg2;
8161 int result1;
8162
8163 PC = cia;
8164 srcreg1 = translate_rreg (SD_, RM1);
8165 srcreg2 = translate_rreg (SD_, RM2);
8166 dstreg1 = translate_rreg (SD_, RN1);
8167 dstreg2 = translate_rreg (SD_, RN2);
8168
8169 if (State.regs[srcreg1] >= 0x7fff)
8170 result1 = 0x7fff;
8171 else if (State.regs[srcreg1] <= 0xffff8000)
8172 result1 = 0xffff8000;
8173 else
8174 result1 = State.regs[srcreg1];
8175
8176 State.regs[dstreg2] -= State.regs[srcreg2];
8177 State.regs[dstreg1] = result1;
8178}
8179
8180// 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
81818.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
8182"sat16_sub"
8183*am33
8184{
8185 int srcreg1, dstreg1, dstreg2;
8186 int result1;
8187
8188 PC = cia;
8189 srcreg1 = translate_rreg (SD_, RM1);
8190 dstreg1 = translate_rreg (SD_, RN1);
8191 dstreg2 = translate_rreg (SD_, RN2);
8192
8193 if (State.regs[srcreg1] >= 0x7fff)
8194 result1 = 0x7fff;
8195 else if (State.regs[srcreg1] <= 0xffff8000)
8196 result1 = 0xffff8000;
8197 else
8198 result1 = State.regs[srcreg1];
8199
8200 State.regs[dstreg2] -= EXTEND4 (IMM4);
8201 State.regs[dstreg1] = result1;
8202}
8203
8204// 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
82058.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
8206"sat16_cmp"
8207*am33
8208{
8209 int srcreg1, srcreg2, dstreg1, dstreg2;
8210 int result1;
8211
8212 PC = cia;
8213 srcreg1 = translate_rreg (SD_, RM1);
8214 srcreg2 = translate_rreg (SD_, RM2);
8215 dstreg1 = translate_rreg (SD_, RN1);
8216 dstreg2 = translate_rreg (SD_, RN2);
8217
8218 State.regs[dstreg1] = result1;
8219 if (State.regs[srcreg1] >= 0x7fff)
8220 State.regs[dstreg1] = 0x7fff;
8221 else if (State.regs[srcreg1] <= 0xffff8000)
8222 State.regs[dstreg1] = 0xffff8000;
8223 else
8224 State.regs[dstreg1] = State.regs[srcreg1];
8225}
8226
8227// 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
82288.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
8229"sat16_cmp"
8230*am33
8231{
8232 int srcreg1, dstreg1, dstreg2;
8233
8234 PC = cia;
8235 srcreg1 = translate_rreg (SD_, RM1);
8236 dstreg1 = translate_rreg (SD_, RN1);
8237 dstreg2 = translate_rreg (SD_, RN2);
8238
8239 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
8240 if (State.regs[srcreg1] >= 0x7fff)
8241 State.regs[dstreg1] = 0x7fff;
8242 else if (State.regs[srcreg1] <= 0xffff8000)
8243 State.regs[dstreg1] = 0xffff8000;
8244 else
8245 State.regs[dstreg1] = State.regs[srcreg1];
8246}
8247
8248// 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
82498.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
8250"sat16_mov"
8251*am33
8252{
8253 int srcreg1, srcreg2, dstreg1, dstreg2;
8254 int result1;
8255
8256 PC = cia;
8257 srcreg1 = translate_rreg (SD_, RM1);
8258 srcreg2 = translate_rreg (SD_, RM2);
8259 dstreg1 = translate_rreg (SD_, RN1);
8260 dstreg2 = translate_rreg (SD_, RN2);
8261
8262 if (State.regs[srcreg1] >= 0x7fff)
8263 result1 = 0x7fff;
8264 else if (State.regs[srcreg1] <= 0xffff8000)
8265 result1 = 0xffff8000;
8266 else
8267 result1 = State.regs[srcreg1];
8268
8269 State.regs[dstreg2] = State.regs[srcreg2];
8270 State.regs[dstreg1] = result1;
8271}
8272
8273// 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
82748.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
8275"sat16_mov"
8276*am33
8277{
8278 int srcreg1, dstreg1, dstreg2;
8279 int result1;
8280
8281 PC = cia;
8282 srcreg1 = translate_rreg (SD_, RM1);
8283 dstreg1 = translate_rreg (SD_, RN1);
8284 dstreg2 = translate_rreg (SD_, RN2);
8285
8286 if (State.regs[srcreg1] >= 0x7fff)
8287 result1 = 0x7fff;
8288 else if (State.regs[srcreg1] <= 0xffff8000)
8289 result1 = 0xffff8000;
8290 else
8291 result1 = State.regs[srcreg1];
8292
8293 State.regs[dstreg2] = EXTEND4 (IMM4);
8294 State.regs[dstreg1] = result1;
8295}
8296
8297// 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
82988.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
8299"sat16_asr"
8300*am33
8301{
8302 int srcreg1, srcreg2, dstreg1, dstreg2;
8303 int result1;
8304 signed int temp;
8305
8306 PC = cia;
8307 srcreg1 = translate_rreg (SD_, RM1);
8308 srcreg2 = translate_rreg (SD_, RM2);
8309 dstreg1 = translate_rreg (SD_, RN1);
8310 dstreg2 = translate_rreg (SD_, RN2);
8311
8312 if (State.regs[srcreg1] >= 0x7fff)
8313 result1 = 0x7fff;
8314 else if (State.regs[srcreg1] <= 0xffff8000)
8315 result1 = 0xffff8000;
8316 else
8317 result1 = State.regs[srcreg1];
8318
8319 temp = State.regs[dstreg2];
8320 temp >>= State.regs[srcreg2];
8321 State.regs[dstreg2] = temp;
8322 State.regs[dstreg1] = result1;
8323}
8324
8325// 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
83268.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
8327"sat16_asr"
8328*am33
8329{
8330 int srcreg1, dstreg1, dstreg2;
8331 int result1;
8332 signed int temp;
8333
8334 PC = cia;
8335 srcreg1 = translate_rreg (SD_, RM1);
8336 dstreg1 = translate_rreg (SD_, RN1);
8337 dstreg2 = translate_rreg (SD_, RN2);
8338
8339 if (State.regs[srcreg1] >= 0x7fff)
8340 result1 = 0x7fff;
8341 else if (State.regs[srcreg1] <= 0xffff8000)
8342 result1 = 0xffff8000;
8343 else
8344 result1 = State.regs[srcreg1];
8345
8346 temp = State.regs[dstreg2];
8347 temp >>= IMM4;
8348 State.regs[dstreg2] = temp;
8349 State.regs[dstreg1] = result1;
8350}
8351
8352// 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
83538.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
8354"sat16_lsr"
8355*am33
8356{
8357 int srcreg1, srcreg2, dstreg1, dstreg2;
8358 int result1;
8359
8360 PC = cia;
8361 srcreg1 = translate_rreg (SD_, RM1);
8362 srcreg2 = translate_rreg (SD_, RM2);
8363 dstreg1 = translate_rreg (SD_, RN1);
8364 dstreg2 = translate_rreg (SD_, RN2);
8365
8366 if (State.regs[srcreg1] >= 0x7fff)
8367 result1 = 0x7fff;
8368 else if (State.regs[srcreg1] <= 0xffff8000)
8369 result1 = 0xffff8000;
8370 else
8371 result1 = State.regs[srcreg1];
8372
8373 State.regs[dstreg2] >>= State.regs[srcreg2];
8374 State.regs[dstreg1] = result1;
8375}
8376
8377// 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
83788.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
8379"sat16_lsr"
8380*am33
8381{
8382 int srcreg1, dstreg1, dstreg2;
8383 int result1;
8384 signed int temp;
8385
8386 PC = cia;
8387 srcreg1 = translate_rreg (SD_, RM1);
8388 dstreg1 = translate_rreg (SD_, RN1);
8389 dstreg2 = translate_rreg (SD_, RN2);
8390
8391 if (State.regs[srcreg1] >= 0x7fff)
8392 result1 = 0x7fff;
8393 else if (State.regs[srcreg1] <= 0xffff8000)
8394 result1 = 0xffff8000;
8395 else
8396 result1 = State.regs[srcreg1];
8397
8398 State.regs[dstreg2] >>= IMM4;
8399 State.regs[dstreg1] = result1;
8400}
8401
8402
8403// 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
84048.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
8405"sat16_asl"
8406*am33
8407{
8408 int srcreg1, srcreg2, dstreg1, dstreg2;
8409 int result1;
8410
8411 PC = cia;
8412 srcreg1 = translate_rreg (SD_, RM1);
8413 srcreg2 = translate_rreg (SD_, RM2);
8414 dstreg1 = translate_rreg (SD_, RN1);
8415 dstreg2 = translate_rreg (SD_, RN2);
8416
8417 if (State.regs[srcreg1] >= 0x7fff)
8418 result1 = 0x7fff;
8419 else if (State.regs[srcreg1] <= 0xffff8000)
8420 result1 = 0xffff8000;
8421 else
8422 result1 = State.regs[srcreg1];
8423
8424 State.regs[dstreg2] <<= State.regs[srcreg2];
8425 State.regs[dstreg1] = result1;
8426}
8427
8428// 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
84298.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
8430"sat16_asl"
8431*am33
8432{
8433 int srcreg1, dstreg1, dstreg2;
8434 int result1;
8435 signed int temp;
8436
8437 PC = cia;
8438 srcreg1 = translate_rreg (SD_, RM1);
8439 dstreg1 = translate_rreg (SD_, RN1);
8440 dstreg2 = translate_rreg (SD_, RN2);
8441
8442 if (State.regs[srcreg1] >= 0x7fff)
8443 result1 = 0x7fff;
8444 else if (State.regs[srcreg1] <= 0xffff8000)
8445 result1 = 0xffff8000;
8446 else
8447 result1 = State.regs[srcreg1];
8448
8449 State.regs[dstreg2] <<= IMM4;
8450 State.regs[dstreg1] = result1;
8451}
8452
8453// 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
84548.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
8455"mov_llt"
8456*am33
8457{
8458 int srcreg, dstreg;
8459 int result1;
8460
8461 PC = cia;
8462 srcreg = translate_rreg (SD_, RM);
8463 dstreg = translate_rreg (SD_, RN);
8464
8465 State.regs[dstreg] = load_word (State.regs[srcreg]);
8466 State.regs[srcreg] += EXTEND4 (IMM4);
8467
8468 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
8469 {
8470 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8471 nia = PC;
8472 }
8473 State.regs[dstreg] = result1;
8474}
8475
8476// 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
84778.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
8478"mov_lgt"
8479*am33
8480{
8481 int srcreg, dstreg;
8482
8483 PC = cia;
8484 srcreg = translate_rreg (SD_, RM);
8485 dstreg = translate_rreg (SD_, RN);
8486
8487 State.regs[dstreg] = load_word (State.regs[srcreg]);
8488 State.regs[srcreg] += EXTEND4 (IMM4);
8489
8490 if (!((PSW & PSW_Z)
8491 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
8492 {
8493 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8494 nia = PC;
8495 }
8496}
8497
8498// 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
84998.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
8500"mov_lge"
8501*am33
8502{
8503 int srcreg, dstreg;
8504
8505 PC = cia;
8506 srcreg = translate_rreg (SD_, RM);
8507 dstreg = translate_rreg (SD_, RN);
8508
8509 State.regs[dstreg] = load_word (State.regs[srcreg]);
8510 State.regs[srcreg] += EXTEND4 (IMM4);
8511
8512 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8513 {
8514 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8515 nia = PC;
8516 }
8517}
8518
8519// 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
85208.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
8521"mov_lle"
8522*am33
8523{
8524 int srcreg, dstreg;
8525
8526 PC = cia;
8527 srcreg = translate_rreg (SD_, RM);
8528 dstreg = translate_rreg (SD_, RN);
8529
8530 State.regs[dstreg] = load_word (State.regs[srcreg]);
8531 State.regs[srcreg] += EXTEND4 (IMM4);
8532
8533 if ((PSW & PSW_Z)
8534 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8535 {
8536 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8537 nia = PC;
8538 }
8539}
8540
8541// 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
85428.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
8543"mov_lcs"
8544*am33
8545{
8546 int srcreg, dstreg;
8547
8548 PC = cia;
8549 srcreg = translate_rreg (SD_, RM);
8550 dstreg = translate_rreg (SD_, RN);
8551
8552 State.regs[dstreg] = load_word (State.regs[srcreg]);
8553 State.regs[srcreg] += EXTEND4 (IMM4);
8554
8555 if (PSW & PSW_C)
8556 {
8557 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8558 nia = PC;
8559 }
8560}
8561
8562// 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
85638.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
8564"mov_lhi"
8565*am33
8566{
8567 int srcreg, dstreg;
8568
8569 PC = cia;
8570 srcreg = translate_rreg (SD_, RM);
8571 dstreg = translate_rreg (SD_, RN);
8572
8573 State.regs[dstreg] = load_word (State.regs[srcreg]);
8574 State.regs[srcreg] += EXTEND4 (IMM4);
8575
8576 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
8577 {
8578 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8579 nia = PC;
8580 }
8581}
8582
8583// 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
85848.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
8585"mov_lcc"
8586*am33
8587{
8588 int srcreg, dstreg;
8589
8590 PC = cia;
8591 srcreg = translate_rreg (SD_, RM);
8592 dstreg = translate_rreg (SD_, RN);
8593
8594 State.regs[dstreg] = load_word (State.regs[srcreg]);
8595 State.regs[srcreg] += EXTEND4 (IMM4);
8596
8597 if (!(PSW & PSW_C))
8598 {
8599 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8600 nia = PC;
8601 }
8602}
8603
8604// 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
86058.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
8606"mov_lls"
8607*am33
8608{
8609 int srcreg, dstreg;
8610
8611 PC = cia;
8612 srcreg = translate_rreg (SD_, RM);
8613 dstreg = translate_rreg (SD_, RN);
8614
8615 State.regs[dstreg] = load_word (State.regs[srcreg]);
8616 State.regs[srcreg] += EXTEND4 (IMM4);
8617
8618 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
8619 {
8620 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8621 nia = PC;
8622 }
8623}
8624
8625// 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
86268.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
8627"mov_leq"
8628*am33
8629{
8630 int srcreg, dstreg;
8631
8632 PC = cia;
8633 srcreg = translate_rreg (SD_, RM);
8634 dstreg = translate_rreg (SD_, RN);
8635
8636 State.regs[dstreg] = load_word (State.regs[srcreg]);
8637 State.regs[srcreg] += EXTEND4 (IMM4);
8638
8639 if (PSW & PSW_Z)
8640 {
8641 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8642 nia = PC;
8643 }
8644}
8645
8646// 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
86478.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
8648"mov_lne"
8649*am33
8650{
8651 int srcreg, dstreg;
8652
8653 PC = cia;
8654 srcreg = translate_rreg (SD_, RM);
8655 dstreg = translate_rreg (SD_, RN);
8656
8657 State.regs[dstreg] = load_word (State.regs[srcreg]);
8658 State.regs[srcreg] += EXTEND4 (IMM4);
8659
8660 if (!(PSW & PSW_Z))
8661 {
8662 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8663 nia = PC;
8664 }
8665}
8666
8667// 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
86688.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
8669"mov_lra"
8670*am33
8671{
8672 int srcreg, dstreg;
8673
8674 PC = cia;
8675 srcreg = translate_rreg (SD_, RM);
8676 dstreg = translate_rreg (SD_, RN);
8677
8678 State.regs[dstreg] = load_word (State.regs[srcreg]);
8679 State.regs[srcreg] += EXTEND4 (IMM4);
8680
8681 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8682 nia = PC;
8683}
GDB Binutils - Deliverables
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