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c906108c SS |
1 | #include <signal.h> |
2 | ||
3 | #if WITH_COMMON | |
4 | #include "sim-main.h" | |
5 | #include "sim-options.h" | |
6 | #include "sim-hw.h" | |
7 | #else | |
8 | #include "mn10300_sim.h" | |
9 | #endif | |
10 | ||
11 | #include "sysdep.h" | |
12 | #include "bfd.h" | |
13 | #include "sim-assert.h" | |
14 | ||
15 | ||
16 | #ifdef HAVE_STDLIB_H | |
17 | #include <stdlib.h> | |
18 | #endif | |
19 | ||
20 | #ifdef HAVE_STRING_H | |
21 | #include <string.h> | |
22 | #else | |
23 | #ifdef HAVE_STRINGS_H | |
24 | #include <strings.h> | |
25 | #endif | |
26 | #endif | |
27 | ||
28 | #include "bfd.h" | |
29 | ||
30 | #ifndef INLINE | |
31 | #ifdef __GNUC__ | |
32 | #define INLINE inline | |
33 | #else | |
34 | #define INLINE | |
35 | #endif | |
36 | #endif | |
37 | ||
38 | ||
39 | host_callback *mn10300_callback; | |
40 | int mn10300_debug; | |
41 | struct _state State; | |
42 | ||
43 | ||
44 | /* simulation target board. NULL=default configuration */ | |
45 | static char* board = NULL; | |
46 | ||
47 | static DECLARE_OPTION_HANDLER (mn10300_option_handler); | |
48 | ||
49 | enum { | |
50 | OPTION_BOARD = OPTION_START, | |
51 | }; | |
52 | ||
53 | static SIM_RC | |
54 | mn10300_option_handler (sd, cpu, opt, arg, is_command) | |
55 | SIM_DESC sd; | |
56 | sim_cpu *cpu; | |
57 | int opt; | |
58 | char *arg; | |
59 | int is_command; | |
60 | { | |
61 | int cpu_nr; | |
62 | switch (opt) | |
63 | { | |
64 | case OPTION_BOARD: | |
65 | { | |
66 | if (arg) | |
67 | { | |
68 | board = zalloc(strlen(arg) + 1); | |
69 | strcpy(board, arg); | |
70 | } | |
71 | return SIM_RC_OK; | |
72 | } | |
73 | } | |
74 | ||
75 | return SIM_RC_OK; | |
76 | } | |
77 | ||
78 | static const OPTION mn10300_options[] = | |
79 | { | |
80 | #define BOARD_AM32 "stdeval1" | |
81 | { {"board", required_argument, NULL, OPTION_BOARD}, | |
82 | '\0', "none" /* rely on compile-time string concatenation for other options */ | |
83 | "|" BOARD_AM32 | |
84 | , "Customize simulation for a particular board.", mn10300_option_handler }, | |
85 | ||
86 | { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } | |
87 | }; | |
88 | ||
89 | #if WITH_COMMON | |
90 | #else | |
91 | static void dispatch PARAMS ((uint32, uint32, int)); | |
92 | static long hash PARAMS ((long)); | |
93 | static void init_system PARAMS ((void)); | |
94 | ||
95 | static SIM_OPEN_KIND sim_kind; | |
96 | static char *myname; | |
97 | #define MAX_HASH 127 | |
98 | ||
99 | struct hash_entry | |
100 | { | |
101 | struct hash_entry *next; | |
102 | long opcode; | |
103 | long mask; | |
104 | struct simops *ops; | |
105 | #ifdef HASH_STAT | |
106 | unsigned long count; | |
107 | #endif | |
108 | }; | |
109 | ||
110 | static int max_mem = 0; | |
111 | struct hash_entry hash_table[MAX_HASH+1]; | |
112 | ||
113 | ||
114 | /* This probably doesn't do a very good job at bucket filling, but | |
115 | it's simple... */ | |
116 | static INLINE long | |
117 | hash(insn) | |
118 | long insn; | |
119 | { | |
120 | /* These are one byte insns, we special case these since, in theory, | |
121 | they should be the most heavily used. */ | |
122 | if ((insn & 0xffffff00) == 0) | |
123 | { | |
124 | switch (insn & 0xf0) | |
125 | { | |
126 | case 0x00: | |
127 | return 0x70; | |
128 | ||
129 | case 0x40: | |
130 | return 0x71; | |
131 | ||
132 | case 0x10: | |
133 | return 0x72; | |
134 | ||
135 | case 0x30: | |
136 | return 0x73; | |
137 | ||
138 | case 0x50: | |
139 | return 0x74; | |
140 | ||
141 | case 0x60: | |
142 | return 0x75; | |
143 | ||
144 | case 0x70: | |
145 | return 0x76; | |
146 | ||
147 | case 0x80: | |
148 | return 0x77; | |
149 | ||
150 | case 0x90: | |
151 | return 0x78; | |
152 | ||
153 | case 0xa0: | |
154 | return 0x79; | |
155 | ||
156 | case 0xb0: | |
157 | return 0x7a; | |
158 | ||
159 | case 0xe0: | |
160 | return 0x7b; | |
161 | ||
162 | default: | |
163 | return 0x7c; | |
164 | } | |
165 | } | |
166 | ||
167 | /* These are two byte insns */ | |
168 | if ((insn & 0xffff0000) == 0) | |
169 | { | |
170 | if ((insn & 0xf000) == 0x2000 | |
171 | || (insn & 0xf000) == 0x5000) | |
172 | return ((insn & 0xfc00) >> 8) & 0x7f; | |
173 | ||
174 | if ((insn & 0xf000) == 0x4000) | |
175 | return ((insn & 0xf300) >> 8) & 0x7f; | |
176 | ||
177 | if ((insn & 0xf000) == 0x8000 | |
178 | || (insn & 0xf000) == 0x9000 | |
179 | || (insn & 0xf000) == 0xa000 | |
180 | || (insn & 0xf000) == 0xb000) | |
181 | return ((insn & 0xf000) >> 8) & 0x7f; | |
182 | ||
183 | if ((insn & 0xff00) == 0xf000 | |
184 | || (insn & 0xff00) == 0xf100 | |
185 | || (insn & 0xff00) == 0xf200 | |
186 | || (insn & 0xff00) == 0xf500 | |
187 | || (insn & 0xff00) == 0xf600) | |
188 | return ((insn & 0xfff0) >> 4) & 0x7f; | |
189 | ||
190 | if ((insn & 0xf000) == 0xc000) | |
191 | return ((insn & 0xff00) >> 8) & 0x7f; | |
192 | ||
193 | return ((insn & 0xffc0) >> 6) & 0x7f; | |
194 | } | |
195 | ||
196 | /* These are three byte insns. */ | |
197 | if ((insn & 0xff000000) == 0) | |
198 | { | |
199 | if ((insn & 0xf00000) == 0x000000) | |
200 | return ((insn & 0xf30000) >> 16) & 0x7f; | |
201 | ||
202 | if ((insn & 0xf00000) == 0x200000 | |
203 | || (insn & 0xf00000) == 0x300000) | |
204 | return ((insn & 0xfc0000) >> 16) & 0x7f; | |
205 | ||
206 | if ((insn & 0xff0000) == 0xf80000) | |
207 | return ((insn & 0xfff000) >> 12) & 0x7f; | |
208 | ||
209 | if ((insn & 0xff0000) == 0xf90000) | |
210 | return ((insn & 0xfffc00) >> 10) & 0x7f; | |
211 | ||
212 | return ((insn & 0xff0000) >> 16) & 0x7f; | |
213 | } | |
214 | ||
215 | /* These are four byte or larger insns. */ | |
216 | if ((insn & 0xf0000000) == 0xf0000000) | |
217 | return ((insn & 0xfff00000) >> 20) & 0x7f; | |
218 | ||
219 | return ((insn & 0xff000000) >> 24) & 0x7f; | |
220 | } | |
221 | ||
222 | static INLINE void | |
223 | dispatch (insn, extension, length) | |
224 | uint32 insn; | |
225 | uint32 extension; | |
226 | int length; | |
227 | { | |
228 | struct hash_entry *h; | |
229 | ||
230 | h = &hash_table[hash(insn)]; | |
231 | ||
232 | while ((insn & h->mask) != h->opcode | |
233 | || (length != h->ops->length)) | |
234 | { | |
235 | if (!h->next) | |
236 | { | |
237 | (*mn10300_callback->printf_filtered) (mn10300_callback, | |
238 | "ERROR looking up hash for 0x%x, PC=0x%x\n", insn, PC); | |
239 | exit(1); | |
240 | } | |
241 | h = h->next; | |
242 | } | |
243 | ||
244 | ||
245 | #ifdef HASH_STAT | |
246 | h->count++; | |
247 | #endif | |
248 | ||
249 | /* Now call the right function. */ | |
250 | (h->ops->func)(insn, extension); | |
251 | PC += length; | |
252 | } | |
253 | ||
254 | void | |
255 | sim_size (power) | |
256 | int power; | |
257 | ||
258 | { | |
259 | if (State.mem) | |
260 | free (State.mem); | |
261 | ||
262 | max_mem = 1 << power; | |
263 | State.mem = (uint8 *) calloc (1, 1 << power); | |
264 | if (!State.mem) | |
265 | { | |
266 | (*mn10300_callback->printf_filtered) (mn10300_callback, "Allocation of main memory failed.\n"); | |
267 | exit (1); | |
268 | } | |
269 | } | |
270 | ||
271 | static void | |
272 | init_system () | |
273 | { | |
274 | if (!State.mem) | |
275 | sim_size(19); | |
276 | } | |
277 | ||
278 | int | |
279 | sim_write (sd, addr, buffer, size) | |
280 | SIM_DESC sd; | |
281 | SIM_ADDR addr; | |
282 | unsigned char *buffer; | |
283 | int size; | |
284 | { | |
285 | int i; | |
286 | ||
287 | init_system (); | |
288 | ||
289 | for (i = 0; i < size; i++) | |
290 | store_byte (addr + i, buffer[i]); | |
291 | ||
292 | return size; | |
293 | } | |
294 | ||
295 | /* Compare two opcode table entries for qsort. */ | |
296 | static int | |
297 | compare_simops (arg1, arg2) | |
298 | const PTR arg1; | |
299 | const PTR arg2; | |
300 | { | |
301 | unsigned long code1 = ((struct simops *)arg1)->opcode; | |
302 | unsigned long code2 = ((struct simops *)arg2)->opcode; | |
303 | ||
304 | if (code1 < code2) | |
305 | return -1; | |
306 | if (code2 < code1) | |
307 | return 1; | |
308 | return 0; | |
309 | } | |
310 | ||
311 | SIM_DESC | |
312 | sim_open (kind, cb, abfd, argv) | |
313 | SIM_OPEN_KIND kind; | |
314 | host_callback *cb; | |
315 | struct _bfd *abfd; | |
316 | char **argv; | |
317 | { | |
318 | struct simops *s; | |
319 | struct hash_entry *h; | |
320 | char **p; | |
321 | int i; | |
322 | ||
323 | mn10300_callback = cb; | |
324 | ||
325 | /* Sort the opcode array from smallest opcode to largest. | |
326 | This will generally improve simulator performance as the smaller | |
327 | opcodes are generally preferred to the larger opcodes. */ | |
328 | for (i = 0, s = Simops; s->func; s++, i++) | |
329 | ; | |
330 | qsort (Simops, i, sizeof (Simops[0]), compare_simops); | |
331 | ||
332 | sim_kind = kind; | |
333 | myname = argv[0]; | |
334 | ||
335 | for (p = argv + 1; *p; ++p) | |
336 | { | |
337 | if (strcmp (*p, "-E") == 0) | |
338 | ++p; /* ignore endian spec */ | |
339 | else | |
340 | #ifdef DEBUG | |
341 | if (strcmp (*p, "-t") == 0) | |
342 | mn10300_debug = DEBUG; | |
343 | else | |
344 | #endif | |
345 | (*mn10300_callback->printf_filtered) (mn10300_callback, "ERROR: unsupported option(s): %s\n",*p); | |
346 | } | |
347 | ||
348 | /* put all the opcodes in the hash table */ | |
349 | for (s = Simops; s->func; s++) | |
350 | { | |
351 | h = &hash_table[hash(s->opcode)]; | |
352 | ||
353 | /* go to the last entry in the chain */ | |
354 | while (h->next) | |
355 | { | |
356 | /* Don't insert the same opcode more than once. */ | |
357 | if (h->opcode == s->opcode | |
358 | && h->mask == s->mask | |
359 | && h->ops == s) | |
360 | break; | |
361 | else | |
362 | h = h->next; | |
363 | } | |
364 | ||
365 | /* Don't insert the same opcode more than once. */ | |
366 | if (h->opcode == s->opcode | |
367 | && h->mask == s->mask | |
368 | && h->ops == s) | |
369 | continue; | |
370 | ||
371 | if (h->ops) | |
372 | { | |
373 | h->next = calloc(1,sizeof(struct hash_entry)); | |
374 | h = h->next; | |
375 | } | |
376 | h->ops = s; | |
377 | h->mask = s->mask; | |
378 | h->opcode = s->opcode; | |
379 | #if HASH_STAT | |
380 | h->count = 0; | |
381 | #endif | |
382 | } | |
383 | ||
384 | ||
385 | /* fudge our descriptor for now */ | |
386 | return (SIM_DESC) 1; | |
387 | } | |
388 | ||
389 | ||
390 | void | |
391 | sim_close (sd, quitting) | |
392 | SIM_DESC sd; | |
393 | int quitting; | |
394 | { | |
395 | /* nothing to do */ | |
396 | } | |
397 | ||
398 | void | |
399 | sim_set_profile (n) | |
400 | int n; | |
401 | { | |
402 | (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile %d\n", n); | |
403 | } | |
404 | ||
405 | void | |
406 | sim_set_profile_size (n) | |
407 | int n; | |
408 | { | |
409 | (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile_size %d\n", n); | |
410 | } | |
411 | ||
412 | int | |
413 | sim_stop (sd) | |
414 | SIM_DESC sd; | |
415 | { | |
416 | return 0; | |
417 | } | |
418 | ||
419 | void | |
420 | sim_resume (sd, step, siggnal) | |
421 | SIM_DESC sd; | |
422 | int step, siggnal; | |
423 | { | |
424 | uint32 inst; | |
425 | reg_t oldpc; | |
426 | struct hash_entry *h; | |
427 | ||
428 | if (step) | |
429 | State.exception = SIGTRAP; | |
430 | else | |
431 | State.exception = 0; | |
432 | ||
433 | State.exited = 0; | |
434 | ||
435 | do | |
436 | { | |
437 | unsigned long insn, extension; | |
438 | ||
439 | /* Fetch the current instruction. */ | |
440 | inst = load_mem_big (PC, 2); | |
441 | oldpc = PC; | |
442 | ||
443 | /* Using a giant case statement may seem like a waste because of the | |
444 | code/rodata size the table itself will consume. However, using | |
445 | a giant case statement speeds up the simulator by 10-15% by avoiding | |
446 | cascading if/else statements or cascading case statements. */ | |
447 | ||
448 | switch ((inst >> 8) & 0xff) | |
449 | { | |
450 | /* All the single byte insns except 0x80, 0x90, 0xa0, 0xb0 | |
451 | which must be handled specially. */ | |
452 | case 0x00: | |
453 | case 0x04: | |
454 | case 0x08: | |
455 | case 0x0c: | |
456 | case 0x10: | |
457 | case 0x11: | |
458 | case 0x12: | |
459 | case 0x13: | |
460 | case 0x14: | |
461 | case 0x15: | |
462 | case 0x16: | |
463 | case 0x17: | |
464 | case 0x18: | |
465 | case 0x19: | |
466 | case 0x1a: | |
467 | case 0x1b: | |
468 | case 0x1c: | |
469 | case 0x1d: | |
470 | case 0x1e: | |
471 | case 0x1f: | |
472 | case 0x3c: | |
473 | case 0x3d: | |
474 | case 0x3e: | |
475 | case 0x3f: | |
476 | case 0x40: | |
477 | case 0x41: | |
478 | case 0x44: | |
479 | case 0x45: | |
480 | case 0x48: | |
481 | case 0x49: | |
482 | case 0x4c: | |
483 | case 0x4d: | |
484 | case 0x50: | |
485 | case 0x51: | |
486 | case 0x52: | |
487 | case 0x53: | |
488 | case 0x54: | |
489 | case 0x55: | |
490 | case 0x56: | |
491 | case 0x57: | |
492 | case 0x60: | |
493 | case 0x61: | |
494 | case 0x62: | |
495 | case 0x63: | |
496 | case 0x64: | |
497 | case 0x65: | |
498 | case 0x66: | |
499 | case 0x67: | |
500 | case 0x68: | |
501 | case 0x69: | |
502 | case 0x6a: | |
503 | case 0x6b: | |
504 | case 0x6c: | |
505 | case 0x6d: | |
506 | case 0x6e: | |
507 | case 0x6f: | |
508 | case 0x70: | |
509 | case 0x71: | |
510 | case 0x72: | |
511 | case 0x73: | |
512 | case 0x74: | |
513 | case 0x75: | |
514 | case 0x76: | |
515 | case 0x77: | |
516 | case 0x78: | |
517 | case 0x79: | |
518 | case 0x7a: | |
519 | case 0x7b: | |
520 | case 0x7c: | |
521 | case 0x7d: | |
522 | case 0x7e: | |
523 | case 0x7f: | |
524 | case 0xcb: | |
525 | case 0xd0: | |
526 | case 0xd1: | |
527 | case 0xd2: | |
528 | case 0xd3: | |
529 | case 0xd4: | |
530 | case 0xd5: | |
531 | case 0xd6: | |
532 | case 0xd7: | |
533 | case 0xd8: | |
534 | case 0xd9: | |
535 | case 0xda: | |
536 | case 0xdb: | |
537 | case 0xe0: | |
538 | case 0xe1: | |
539 | case 0xe2: | |
540 | case 0xe3: | |
541 | case 0xe4: | |
542 | case 0xe5: | |
543 | case 0xe6: | |
544 | case 0xe7: | |
545 | case 0xe8: | |
546 | case 0xe9: | |
547 | case 0xea: | |
548 | case 0xeb: | |
549 | case 0xec: | |
550 | case 0xed: | |
551 | case 0xee: | |
552 | case 0xef: | |
553 | case 0xff: | |
554 | insn = (inst >> 8) & 0xff; | |
555 | extension = 0; | |
556 | dispatch (insn, extension, 1); | |
557 | break; | |
558 | ||
559 | /* Special cases where dm == dn is used to encode a different | |
560 | instruction. */ | |
561 | case 0x80: | |
562 | case 0x85: | |
563 | case 0x8a: | |
564 | case 0x8f: | |
565 | case 0x90: | |
566 | case 0x95: | |
567 | case 0x9a: | |
568 | case 0x9f: | |
569 | case 0xa0: | |
570 | case 0xa5: | |
571 | case 0xaa: | |
572 | case 0xaf: | |
573 | case 0xb0: | |
574 | case 0xb5: | |
575 | case 0xba: | |
576 | case 0xbf: | |
577 | insn = inst; | |
578 | extension = 0; | |
579 | dispatch (insn, extension, 2); | |
580 | break; | |
581 | ||
582 | case 0x81: | |
583 | case 0x82: | |
584 | case 0x83: | |
585 | case 0x84: | |
586 | case 0x86: | |
587 | case 0x87: | |
588 | case 0x88: | |
589 | case 0x89: | |
590 | case 0x8b: | |
591 | case 0x8c: | |
592 | case 0x8d: | |
593 | case 0x8e: | |
594 | case 0x91: | |
595 | case 0x92: | |
596 | case 0x93: | |
597 | case 0x94: | |
598 | case 0x96: | |
599 | case 0x97: | |
600 | case 0x98: | |
601 | case 0x99: | |
602 | case 0x9b: | |
603 | case 0x9c: | |
604 | case 0x9d: | |
605 | case 0x9e: | |
606 | case 0xa1: | |
607 | case 0xa2: | |
608 | case 0xa3: | |
609 | case 0xa4: | |
610 | case 0xa6: | |
611 | case 0xa7: | |
612 | case 0xa8: | |
613 | case 0xa9: | |
614 | case 0xab: | |
615 | case 0xac: | |
616 | case 0xad: | |
617 | case 0xae: | |
618 | case 0xb1: | |
619 | case 0xb2: | |
620 | case 0xb3: | |
621 | case 0xb4: | |
622 | case 0xb6: | |
623 | case 0xb7: | |
624 | case 0xb8: | |
625 | case 0xb9: | |
626 | case 0xbb: | |
627 | case 0xbc: | |
628 | case 0xbd: | |
629 | case 0xbe: | |
630 | insn = (inst >> 8) & 0xff; | |
631 | extension = 0; | |
632 | dispatch (insn, extension, 1); | |
633 | break; | |
634 | ||
635 | /* The two byte instructions. */ | |
636 | case 0x20: | |
637 | case 0x21: | |
638 | case 0x22: | |
639 | case 0x23: | |
640 | case 0x28: | |
641 | case 0x29: | |
642 | case 0x2a: | |
643 | case 0x2b: | |
644 | case 0x42: | |
645 | case 0x43: | |
646 | case 0x46: | |
647 | case 0x47: | |
648 | case 0x4a: | |
649 | case 0x4b: | |
650 | case 0x4e: | |
651 | case 0x4f: | |
652 | case 0x58: | |
653 | case 0x59: | |
654 | case 0x5a: | |
655 | case 0x5b: | |
656 | case 0x5c: | |
657 | case 0x5d: | |
658 | case 0x5e: | |
659 | case 0x5f: | |
660 | case 0xc0: | |
661 | case 0xc1: | |
662 | case 0xc2: | |
663 | case 0xc3: | |
664 | case 0xc4: | |
665 | case 0xc5: | |
666 | case 0xc6: | |
667 | case 0xc7: | |
668 | case 0xc8: | |
669 | case 0xc9: | |
670 | case 0xca: | |
671 | case 0xce: | |
672 | case 0xcf: | |
673 | case 0xf0: | |
674 | case 0xf1: | |
675 | case 0xf2: | |
676 | case 0xf3: | |
677 | case 0xf4: | |
678 | case 0xf5: | |
679 | case 0xf6: | |
680 | insn = inst; | |
681 | extension = 0; | |
682 | dispatch (insn, extension, 2); | |
683 | break; | |
684 | ||
685 | /* The three byte insns with a 16bit operand in little endian | |
686 | format. */ | |
687 | case 0x01: | |
688 | case 0x02: | |
689 | case 0x03: | |
690 | case 0x05: | |
691 | case 0x06: | |
692 | case 0x07: | |
693 | case 0x09: | |
694 | case 0x0a: | |
695 | case 0x0b: | |
696 | case 0x0d: | |
697 | case 0x0e: | |
698 | case 0x0f: | |
699 | case 0x24: | |
700 | case 0x25: | |
701 | case 0x26: | |
702 | case 0x27: | |
703 | case 0x2c: | |
704 | case 0x2d: | |
705 | case 0x2e: | |
706 | case 0x2f: | |
707 | case 0x30: | |
708 | case 0x31: | |
709 | case 0x32: | |
710 | case 0x33: | |
711 | case 0x34: | |
712 | case 0x35: | |
713 | case 0x36: | |
714 | case 0x37: | |
715 | case 0x38: | |
716 | case 0x39: | |
717 | case 0x3a: | |
718 | case 0x3b: | |
719 | case 0xcc: | |
720 | insn = load_byte (PC); | |
721 | insn <<= 16; | |
722 | insn |= load_half (PC + 1); | |
723 | extension = 0; | |
724 | dispatch (insn, extension, 3); | |
725 | break; | |
726 | ||
727 | /* The three byte insns without 16bit operand. */ | |
728 | case 0xde: | |
729 | case 0xdf: | |
730 | case 0xf8: | |
731 | case 0xf9: | |
732 | insn = load_mem_big (PC, 3); | |
733 | extension = 0; | |
734 | dispatch (insn, extension, 3); | |
735 | break; | |
736 | ||
737 | /* Four byte insns. */ | |
738 | case 0xfa: | |
739 | case 0xfb: | |
740 | if ((inst & 0xfffc) == 0xfaf0 | |
741 | || (inst & 0xfffc) == 0xfaf4 | |
742 | || (inst & 0xfffc) == 0xfaf8) | |
743 | insn = load_mem_big (PC, 4); | |
744 | else | |
745 | { | |
746 | insn = inst; | |
747 | insn <<= 16; | |
748 | insn |= load_half (PC + 2); | |
749 | extension = 0; | |
750 | } | |
751 | dispatch (insn, extension, 4); | |
752 | break; | |
753 | ||
754 | /* Five byte insns. */ | |
755 | case 0xcd: | |
756 | insn = load_byte (PC); | |
757 | insn <<= 24; | |
758 | insn |= (load_half (PC + 1) << 8); | |
759 | insn |= load_byte (PC + 3); | |
760 | extension = load_byte (PC + 4); | |
761 | dispatch (insn, extension, 5); | |
762 | break; | |
763 | ||
764 | case 0xdc: | |
765 | insn = load_byte (PC); | |
766 | insn <<= 24; | |
767 | extension = load_word (PC + 1); | |
768 | insn |= (extension & 0xffffff00) >> 8; | |
769 | extension &= 0xff; | |
770 | dispatch (insn, extension, 5); | |
771 | break; | |
772 | ||
773 | /* Six byte insns. */ | |
774 | case 0xfc: | |
775 | case 0xfd: | |
776 | insn = (inst << 16); | |
777 | extension = load_word (PC + 2); | |
778 | insn |= ((extension & 0xffff0000) >> 16); | |
779 | extension &= 0xffff; | |
780 | dispatch (insn, extension, 6); | |
781 | break; | |
782 | ||
783 | case 0xdd: | |
784 | insn = load_byte (PC) << 24; | |
785 | extension = load_word (PC + 1); | |
786 | insn |= ((extension >> 8) & 0xffffff); | |
787 | extension = (extension & 0xff) << 16; | |
788 | extension |= load_byte (PC + 5) << 8; | |
789 | extension |= load_byte (PC + 6); | |
790 | dispatch (insn, extension, 7); | |
791 | break; | |
792 | ||
793 | case 0xfe: | |
794 | insn = inst << 16; | |
795 | extension = load_word (PC + 2); | |
796 | insn |= ((extension >> 16) & 0xffff); | |
797 | extension <<= 8; | |
798 | extension &= 0xffff00; | |
799 | extension |= load_byte (PC + 6); | |
800 | dispatch (insn, extension, 7); | |
801 | break; | |
802 | ||
803 | default: | |
804 | abort (); | |
805 | } | |
806 | } | |
807 | while (!State.exception); | |
808 | ||
809 | #ifdef HASH_STAT | |
810 | { | |
811 | int i; | |
812 | for (i = 0; i < MAX_HASH; i++) | |
813 | { | |
814 | struct hash_entry *h; | |
815 | h = &hash_table[i]; | |
816 | ||
817 | printf("hash 0x%x:\n", i); | |
818 | ||
819 | while (h) | |
820 | { | |
821 | printf("h->opcode = 0x%x, count = 0x%x\n", h->opcode, h->count); | |
822 | h = h->next; | |
823 | } | |
824 | ||
825 | printf("\n\n"); | |
826 | } | |
827 | fflush (stdout); | |
828 | } | |
829 | #endif | |
830 | ||
831 | } | |
832 | ||
833 | int | |
834 | sim_trace (sd) | |
835 | SIM_DESC sd; | |
836 | { | |
837 | #ifdef DEBUG | |
838 | mn10300_debug = DEBUG; | |
839 | #endif | |
840 | sim_resume (sd, 0, 0); | |
841 | return 1; | |
842 | } | |
843 | ||
844 | void | |
845 | sim_info (sd, verbose) | |
846 | SIM_DESC sd; | |
847 | int verbose; | |
848 | { | |
849 | (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_info\n"); | |
850 | } | |
851 | ||
852 | SIM_RC | |
853 | sim_create_inferior (sd, abfd, argv, env) | |
854 | SIM_DESC sd; | |
855 | struct _bfd *abfd; | |
856 | char **argv; | |
857 | char **env; | |
858 | { | |
859 | if (abfd != NULL) | |
860 | PC = bfd_get_start_address (abfd); | |
861 | else | |
862 | PC = 0; | |
863 | return SIM_RC_OK; | |
864 | } | |
865 | ||
866 | void | |
867 | sim_set_callbacks (p) | |
868 | host_callback *p; | |
869 | { | |
870 | mn10300_callback = p; | |
871 | } | |
872 | ||
873 | /* All the code for exiting, signals, etc needs to be revamped. | |
874 | ||
875 | This is enough to get c-torture limping though. */ | |
876 | ||
877 | void | |
878 | sim_stop_reason (sd, reason, sigrc) | |
879 | SIM_DESC sd; | |
880 | enum sim_stop *reason; | |
881 | int *sigrc; | |
882 | { | |
883 | if (State.exited) | |
884 | *reason = sim_exited; | |
885 | else | |
886 | *reason = sim_stopped; | |
887 | ||
888 | if (State.exception == SIGQUIT) | |
889 | *sigrc = 0; | |
890 | else | |
891 | *sigrc = State.exception; | |
892 | } | |
893 | ||
894 | int | |
895 | sim_read (sd, addr, buffer, size) | |
896 | SIM_DESC sd; | |
897 | SIM_ADDR addr; | |
898 | unsigned char *buffer; | |
899 | int size; | |
900 | { | |
901 | int i; | |
902 | for (i = 0; i < size; i++) | |
903 | buffer[i] = load_byte (addr + i); | |
904 | ||
905 | return size; | |
906 | } | |
907 | ||
908 | void | |
909 | sim_do_command (sd, cmd) | |
910 | SIM_DESC sd; | |
911 | char *cmd; | |
912 | { | |
913 | (*mn10300_callback->printf_filtered) (mn10300_callback, "\"%s\" is not a valid mn10300 simulator command.\n", cmd); | |
914 | } | |
915 | ||
916 | SIM_RC | |
917 | sim_load (sd, prog, abfd, from_tty) | |
918 | SIM_DESC sd; | |
919 | char *prog; | |
920 | bfd *abfd; | |
921 | int from_tty; | |
922 | { | |
923 | extern bfd *sim_load_file (); /* ??? Don't know where this should live. */ | |
924 | bfd *prog_bfd; | |
925 | ||
926 | prog_bfd = sim_load_file (sd, myname, mn10300_callback, prog, abfd, | |
927 | sim_kind == SIM_OPEN_DEBUG, | |
928 | 0, sim_write); | |
929 | if (prog_bfd == NULL) | |
930 | return SIM_RC_FAIL; | |
931 | if (abfd == NULL) | |
932 | bfd_close (prog_bfd); | |
933 | return SIM_RC_OK; | |
934 | } | |
935 | #endif /* not WITH_COMMON */ | |
936 | ||
937 | ||
938 | #if WITH_COMMON | |
939 | ||
940 | /* For compatibility */ | |
941 | SIM_DESC simulator; | |
942 | ||
943 | /* These default values correspond to expected usage for the chip. */ | |
944 | ||
945 | SIM_DESC | |
946 | sim_open (kind, cb, abfd, argv) | |
947 | SIM_OPEN_KIND kind; | |
948 | host_callback *cb; | |
949 | struct _bfd *abfd; | |
950 | char **argv; | |
951 | { | |
952 | SIM_DESC sd = sim_state_alloc (kind, cb); | |
953 | mn10300_callback = cb; | |
954 | ||
955 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
956 | ||
957 | /* for compatibility */ | |
958 | simulator = sd; | |
959 | ||
960 | /* FIXME: should be better way of setting up interrupts. For | |
961 | moment, only support watchpoints causing a breakpoint (gdb | |
962 | halt). */ | |
963 | STATE_WATCHPOINTS (sd)->pc = &(PC); | |
964 | STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); | |
965 | STATE_WATCHPOINTS (sd)->interrupt_handler = NULL; | |
966 | STATE_WATCHPOINTS (sd)->interrupt_names = NULL; | |
967 | ||
968 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
969 | return 0; | |
970 | sim_add_option_table (sd, NULL, mn10300_options); | |
971 | ||
972 | /* Allocate core managed memory */ | |
973 | sim_do_command (sd, "memory region 0,0x100000"); | |
974 | sim_do_command (sd, "memory region 0x40000000,0x200000"); | |
975 | ||
976 | /* getopt will print the error message so we just have to exit if this fails. | |
977 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
978 | print_filtered. */ | |
979 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
980 | { | |
981 | /* Uninstall the modules to avoid memory leaks, | |
982 | file descriptor leaks, etc. */ | |
983 | sim_module_uninstall (sd); | |
984 | return 0; | |
985 | } | |
986 | ||
987 | if ( NULL != board | |
988 | && (strcmp(board, BOARD_AM32) == 0 ) ) | |
989 | { | |
990 | /* environment */ | |
991 | STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT; | |
992 | ||
993 | sim_do_command (sd, "memory region 0x44000000,0x40000"); | |
994 | sim_do_command (sd, "memory region 0x48000000,0x400000"); | |
995 | ||
996 | /* device support for mn1030002 */ | |
997 | /* interrupt controller */ | |
998 | ||
999 | sim_hw_parse (sd, "/mn103int@0x34000100/reg 0x34000100 0x7C 0x34000200 0x8 0x34000280 0x8"); | |
1000 | ||
1001 | /* DEBUG: NMI input's */ | |
1002 | sim_hw_parse (sd, "/glue@0x30000000/reg 0x30000000 12"); | |
1003 | sim_hw_parse (sd, "/glue@0x30000000 > int0 nmirq /mn103int"); | |
1004 | sim_hw_parse (sd, "/glue@0x30000000 > int1 watchdog /mn103int"); | |
1005 | sim_hw_parse (sd, "/glue@0x30000000 > int2 syserr /mn103int"); | |
1006 | ||
1007 | /* DEBUG: ACK input */ | |
1008 | sim_hw_parse (sd, "/glue@0x30002000/reg 0x30002000 4"); | |
1009 | sim_hw_parse (sd, "/glue@0x30002000 > int ack /mn103int"); | |
1010 | ||
1011 | /* DEBUG: LEVEL output */ | |
1012 | sim_hw_parse (sd, "/glue@0x30004000/reg 0x30004000 8"); | |
1013 | sim_hw_parse (sd, "/mn103int > nmi int0 /glue@0x30004000"); | |
1014 | sim_hw_parse (sd, "/mn103int > level int1 /glue@0x30004000"); | |
1015 | ||
1016 | /* DEBUG: A bunch of interrupt inputs */ | |
1017 | sim_hw_parse (sd, "/glue@0x30006000/reg 0x30006000 32"); | |
1018 | sim_hw_parse (sd, "/glue@0x30006000 > int0 irq-0 /mn103int"); | |
1019 | sim_hw_parse (sd, "/glue@0x30006000 > int1 irq-1 /mn103int"); | |
1020 | sim_hw_parse (sd, "/glue@0x30006000 > int2 irq-2 /mn103int"); | |
1021 | sim_hw_parse (sd, "/glue@0x30006000 > int3 irq-3 /mn103int"); | |
1022 | sim_hw_parse (sd, "/glue@0x30006000 > int4 irq-4 /mn103int"); | |
1023 | sim_hw_parse (sd, "/glue@0x30006000 > int5 irq-5 /mn103int"); | |
1024 | sim_hw_parse (sd, "/glue@0x30006000 > int6 irq-6 /mn103int"); | |
1025 | sim_hw_parse (sd, "/glue@0x30006000 > int7 irq-7 /mn103int"); | |
1026 | ||
1027 | /* processor interrupt device */ | |
1028 | ||
1029 | /* the device */ | |
1030 | sim_hw_parse (sd, "/mn103cpu@0x20000000"); | |
1031 | sim_hw_parse (sd, "/mn103cpu@0x20000000/reg 0x20000000 0x42"); | |
1032 | ||
1033 | /* DEBUG: ACK output wired upto a glue device */ | |
1034 | sim_hw_parse (sd, "/glue@0x20002000"); | |
1035 | sim_hw_parse (sd, "/glue@0x20002000/reg 0x20002000 4"); | |
1036 | sim_hw_parse (sd, "/mn103cpu > ack int0 /glue@0x20002000"); | |
1037 | ||
1038 | /* DEBUG: RESET/NMI/LEVEL wired up to a glue device */ | |
1039 | sim_hw_parse (sd, "/glue@0x20004000"); | |
1040 | sim_hw_parse (sd, "/glue@0x20004000/reg 0x20004000 12"); | |
1041 | sim_hw_parse (sd, "/glue@0x20004000 > int0 reset /mn103cpu"); | |
1042 | sim_hw_parse (sd, "/glue@0x20004000 > int1 nmi /mn103cpu"); | |
1043 | sim_hw_parse (sd, "/glue@0x20004000 > int2 level /mn103cpu"); | |
1044 | ||
1045 | /* REAL: The processor wired up to the real interrupt controller */ | |
1046 | sim_hw_parse (sd, "/mn103cpu > ack ack /mn103int"); | |
1047 | sim_hw_parse (sd, "/mn103int > level level /mn103cpu"); | |
1048 | sim_hw_parse (sd, "/mn103int > nmi nmi /mn103cpu"); | |
1049 | ||
1050 | ||
1051 | /* PAL */ | |
1052 | ||
1053 | /* the device */ | |
1054 | sim_hw_parse (sd, "/pal@0x31000000"); | |
1055 | sim_hw_parse (sd, "/pal@0x31000000/reg 0x31000000 64"); | |
1056 | sim_hw_parse (sd, "/pal@0x31000000/poll? true"); | |
1057 | ||
1058 | /* DEBUG: PAL wired up to a glue device */ | |
1059 | sim_hw_parse (sd, "/glue@0x31002000"); | |
1060 | sim_hw_parse (sd, "/glue@0x31002000/reg 0x31002000 16"); | |
1061 | sim_hw_parse (sd, "/pal@0x31000000 > countdown int0 /glue@0x31002000"); | |
1062 | sim_hw_parse (sd, "/pal@0x31000000 > timer int1 /glue@0x31002000"); | |
1063 | sim_hw_parse (sd, "/pal@0x31000000 > int int2 /glue@0x31002000"); | |
1064 | sim_hw_parse (sd, "/glue@0x31002000 > int0 int3 /glue@0x31002000"); | |
1065 | sim_hw_parse (sd, "/glue@0x31002000 > int1 int3 /glue@0x31002000"); | |
1066 | sim_hw_parse (sd, "/glue@0x31002000 > int2 int3 /glue@0x31002000"); | |
1067 | ||
1068 | /* REAL: The PAL wired up to the real interrupt controller */ | |
1069 | sim_hw_parse (sd, "/pal@0x31000000 > countdown irq-0 /mn103int"); | |
1070 | sim_hw_parse (sd, "/pal@0x31000000 > timer irq-1 /mn103int"); | |
1071 | sim_hw_parse (sd, "/pal@0x31000000 > int irq-2 /mn103int"); | |
1072 | ||
1073 | /* 8 and 16 bit timers */ | |
1074 | sim_hw_parse (sd, "/mn103tim@0x34001000/reg 0x34001000 36 0x34001080 100 0x34004000 16"); | |
1075 | ||
1076 | /* Hook timer interrupts up to interrupt controller */ | |
1077 | sim_hw_parse (sd, "/mn103tim > timer-0-underflow timer-0-underflow /mn103int"); | |
1078 | sim_hw_parse (sd, "/mn103tim > timer-1-underflow timer-1-underflow /mn103int"); | |
1079 | sim_hw_parse (sd, "/mn103tim > timer-2-underflow timer-2-underflow /mn103int"); | |
1080 | sim_hw_parse (sd, "/mn103tim > timer-3-underflow timer-3-underflow /mn103int"); | |
1081 | sim_hw_parse (sd, "/mn103tim > timer-4-underflow timer-4-underflow /mn103int"); | |
1082 | sim_hw_parse (sd, "/mn103tim > timer-5-underflow timer-5-underflow /mn103int"); | |
1083 | sim_hw_parse (sd, "/mn103tim > timer-6-underflow timer-6-underflow /mn103int"); | |
1084 | sim_hw_parse (sd, "/mn103tim > timer-6-compare-a timer-6-compare-a /mn103int"); | |
1085 | sim_hw_parse (sd, "/mn103tim > timer-6-compare-b timer-6-compare-b /mn103int"); | |
1086 | ||
1087 | ||
1088 | /* Serial devices 0,1,2 */ | |
1089 | sim_hw_parse (sd, "/mn103ser@0x34000800/reg 0x34000800 48"); | |
1090 | sim_hw_parse (sd, "/mn103ser@0x34000800/poll? true"); | |
1091 | ||
1092 | /* Hook serial interrupts up to interrupt controller */ | |
1093 | sim_hw_parse (sd, "/mn103ser > serial-0-receive serial-0-receive /mn103int"); | |
1094 | sim_hw_parse (sd, "/mn103ser > serial-0-transmit serial-0-transmit /mn103int"); | |
1095 | sim_hw_parse (sd, "/mn103ser > serial-1-receive serial-1-receive /mn103int"); | |
1096 | sim_hw_parse (sd, "/mn103ser > serial-1-transmit serial-1-transmit /mn103int"); | |
1097 | sim_hw_parse (sd, "/mn103ser > serial-2-receive serial-2-receive /mn103int"); | |
1098 | sim_hw_parse (sd, "/mn103ser > serial-2-transmit serial-2-transmit /mn103int"); | |
1099 | ||
1100 | sim_hw_parse (sd, "/mn103iop@0x36008000/reg 0x36008000 8 0x36008020 8 0x36008040 0xc 0x36008060 8 0x36008080 8"); | |
1101 | ||
1102 | /* Memory control registers */ | |
1103 | sim_do_command (sd, "memory region 0x32000020,0x30"); | |
1104 | /* Cache control register */ | |
1105 | sim_do_command (sd, "memory region 0x20000070,0x4"); | |
1106 | /* Cache purge regions */ | |
1107 | sim_do_command (sd, "memory region 0x28400000,0x800"); | |
1108 | sim_do_command (sd, "memory region 0x28401000,0x800"); | |
1109 | /* DMA registers */ | |
1110 | sim_do_command (sd, "memory region 0x32000100,0xF"); | |
1111 | sim_do_command (sd, "memory region 0x32000200,0xF"); | |
1112 | sim_do_command (sd, "memory region 0x32000400,0xF"); | |
1113 | sim_do_command (sd, "memory region 0x32000800,0xF"); | |
1114 | } | |
1115 | else | |
1116 | { | |
adf40b2e JM |
1117 | if (board != NULL) |
1118 | { | |
1119 | sim_io_eprintf (sd, "Error: Board `%s' unknown.\n", board); | |
1120 | return 0; | |
c906108c SS |
1121 | } |
1122 | } | |
1123 | ||
1124 | ||
1125 | ||
1126 | /* check for/establish the a reference program image */ | |
1127 | if (sim_analyze_program (sd, | |
1128 | (STATE_PROG_ARGV (sd) != NULL | |
1129 | ? *STATE_PROG_ARGV (sd) | |
1130 | : NULL), | |
1131 | abfd) != SIM_RC_OK) | |
1132 | { | |
1133 | sim_module_uninstall (sd); | |
1134 | return 0; | |
1135 | } | |
1136 | ||
1137 | /* establish any remaining configuration options */ | |
1138 | if (sim_config (sd) != SIM_RC_OK) | |
1139 | { | |
1140 | sim_module_uninstall (sd); | |
1141 | return 0; | |
1142 | } | |
1143 | ||
1144 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
1145 | { | |
1146 | /* Uninstall the modules to avoid memory leaks, | |
1147 | file descriptor leaks, etc. */ | |
1148 | sim_module_uninstall (sd); | |
1149 | return 0; | |
1150 | } | |
1151 | ||
1152 | ||
1153 | /* set machine specific configuration */ | |
1154 | /* STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT */ | |
1155 | /* | PSW_CY | PSW_OV | PSW_S | PSW_Z); */ | |
1156 | ||
1157 | return sd; | |
1158 | } | |
1159 | ||
1160 | ||
1161 | void | |
1162 | sim_close (sd, quitting) | |
1163 | SIM_DESC sd; | |
1164 | int quitting; | |
1165 | { | |
1166 | sim_module_uninstall (sd); | |
1167 | } | |
1168 | ||
1169 | ||
1170 | SIM_RC | |
1171 | sim_create_inferior (sd, prog_bfd, argv, env) | |
1172 | SIM_DESC sd; | |
1173 | struct _bfd *prog_bfd; | |
1174 | char **argv; | |
1175 | char **env; | |
1176 | { | |
1177 | memset (&State, 0, sizeof (State)); | |
1178 | if (prog_bfd != NULL) { | |
1179 | PC = bfd_get_start_address (prog_bfd); | |
1180 | } else { | |
1181 | PC = 0; | |
1182 | } | |
1183 | CIA_SET (STATE_CPU (sd, 0), (unsigned64) PC); | |
1184 | ||
1185 | return SIM_RC_OK; | |
1186 | } | |
1187 | ||
1188 | void | |
1189 | sim_do_command (sd, cmd) | |
1190 | SIM_DESC sd; | |
1191 | char *cmd; | |
1192 | { | |
1193 | char *mm_cmd = "memory-map"; | |
1194 | char *int_cmd = "interrupt"; | |
1195 | ||
1196 | if (sim_args_command (sd, cmd) != SIM_RC_OK) | |
1197 | { | |
1198 | if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0)) | |
1199 | sim_io_eprintf (sd, "`memory-map' command replaced by `sim memory'\n"); | |
1200 | else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0) | |
1201 | sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n"); | |
1202 | else | |
1203 | sim_io_eprintf (sd, "Unknown command `%s'\n", cmd); | |
1204 | } | |
1205 | } | |
1206 | #endif /* WITH_COMMON */ | |
1207 | ||
1208 | /* FIXME These would more efficient to use than load_mem/store_mem, | |
1209 | but need to be changed to use the memory map. */ | |
1210 | ||
1211 | uint8 | |
1212 | get_byte (x) | |
1213 | uint8 *x; | |
1214 | { | |
1215 | return *x; | |
1216 | } | |
1217 | ||
1218 | uint16 | |
1219 | get_half (x) | |
1220 | uint8 *x; | |
1221 | { | |
1222 | uint8 *a = x; | |
1223 | return (a[1] << 8) + (a[0]); | |
1224 | } | |
1225 | ||
1226 | uint32 | |
1227 | get_word (x) | |
1228 | uint8 *x; | |
1229 | { | |
1230 | uint8 *a = x; | |
1231 | return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]); | |
1232 | } | |
1233 | ||
1234 | void | |
1235 | put_byte (addr, data) | |
1236 | uint8 *addr; | |
1237 | uint8 data; | |
1238 | { | |
1239 | uint8 *a = addr; | |
1240 | a[0] = data; | |
1241 | } | |
1242 | ||
1243 | void | |
1244 | put_half (addr, data) | |
1245 | uint8 *addr; | |
1246 | uint16 data; | |
1247 | { | |
1248 | uint8 *a = addr; | |
1249 | a[0] = data & 0xff; | |
1250 | a[1] = (data >> 8) & 0xff; | |
1251 | } | |
1252 | ||
1253 | void | |
1254 | put_word (addr, data) | |
1255 | uint8 *addr; | |
1256 | uint32 data; | |
1257 | { | |
1258 | uint8 *a = addr; | |
1259 | a[0] = data & 0xff; | |
1260 | a[1] = (data >> 8) & 0xff; | |
1261 | a[2] = (data >> 16) & 0xff; | |
1262 | a[3] = (data >> 24) & 0xff; | |
1263 | } | |
1264 | ||
1265 | int | |
1266 | sim_fetch_register (sd, rn, memory, length) | |
1267 | SIM_DESC sd; | |
1268 | int rn; | |
1269 | unsigned char *memory; | |
1270 | int length; | |
1271 | { | |
1272 | put_word (memory, State.regs[rn]); | |
1273 | return -1; | |
1274 | } | |
1275 | ||
1276 | int | |
1277 | sim_store_register (sd, rn, memory, length) | |
1278 | SIM_DESC sd; | |
1279 | int rn; | |
1280 | unsigned char *memory; | |
1281 | int length; | |
1282 | { | |
1283 | State.regs[rn] = get_word (memory); | |
1284 | return -1; | |
1285 | } | |
1286 | ||
1287 | ||
1288 | void | |
1289 | mn10300_core_signal (SIM_DESC sd, | |
1290 | sim_cpu *cpu, | |
1291 | sim_cia cia, | |
1292 | unsigned map, | |
1293 | int nr_bytes, | |
1294 | address_word addr, | |
1295 | transfer_type transfer, | |
1296 | sim_core_signals sig) | |
1297 | { | |
1298 | const char *copy = (transfer == read_transfer ? "read" : "write"); | |
1299 | address_word ip = CIA_ADDR (cia); | |
1300 | ||
1301 | switch (sig) | |
1302 | { | |
1303 | case sim_core_unmapped_signal: | |
1304 | sim_io_eprintf (sd, "mn10300-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n", | |
1305 | nr_bytes, copy, | |
1306 | (unsigned long) addr, (unsigned long) ip); | |
1307 | program_interrupt(sd, cpu, cia, SIM_SIGSEGV); | |
1308 | break; | |
1309 | ||
1310 | case sim_core_unaligned_signal: | |
1311 | sim_io_eprintf (sd, "mn10300-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n", | |
1312 | nr_bytes, copy, | |
1313 | (unsigned long) addr, (unsigned long) ip); | |
1314 | program_interrupt(sd, cpu, cia, SIM_SIGBUS); | |
1315 | break; | |
1316 | ||
1317 | default: | |
1318 | sim_engine_abort (sd, cpu, cia, | |
1319 | "mn10300_core_signal - internal error - bad switch"); | |
1320 | } | |
1321 | } | |
1322 | ||
1323 | ||
1324 | void | |
1325 | program_interrupt (SIM_DESC sd, | |
1326 | sim_cpu *cpu, | |
1327 | sim_cia cia, | |
1328 | SIM_SIGNAL sig) | |
1329 | { | |
1330 | int status; | |
1331 | struct hw *device; | |
7a292a7a | 1332 | static int in_interrupt = 0; |
c906108c SS |
1333 | |
1334 | #ifdef SIM_CPU_EXCEPTION_TRIGGER | |
1335 | SIM_CPU_EXCEPTION_TRIGGER(sd,cpu,cia); | |
1336 | #endif | |
1337 | ||
7a292a7a SS |
1338 | /* avoid infinite recursion */ |
1339 | if (in_interrupt) | |
1340 | { | |
1341 | (*mn10300_callback->printf_filtered) (mn10300_callback, | |
1342 | "ERROR: recursion in program_interrupt during software exception dispatch."); | |
1343 | } | |
1344 | else | |
1345 | { | |
1346 | in_interrupt = 1; | |
1347 | /* copy NMI handler code from dv-mn103cpu.c */ | |
1348 | store_word (SP - 4, CIA_GET (cpu)); | |
1349 | store_half (SP - 8, PSW); | |
1350 | ||
1351 | /* Set the SYSEF flag in NMICR by backdoor method. See | |
1352 | dv-mn103int.c:write_icr(). This is necessary because | |
1353 | software exceptions are not modelled by actually talking to | |
1354 | the interrupt controller, so it cannot set its own SYSEF | |
1355 | flag. */ | |
1356 | if ((NULL != board) && (strcmp(board, BOARD_AM32) == 0)) | |
1357 | store_byte (0x34000103, 0x04); | |
1358 | } | |
1359 | ||
c906108c SS |
1360 | PSW &= ~PSW_IE; |
1361 | SP = SP - 8; | |
1362 | CIA_SET (cpu, 0x40000008); | |
1363 | ||
7a292a7a | 1364 | in_interrupt = 0; |
c906108c SS |
1365 | sim_engine_halt(sd, cpu, NULL, cia, sim_stopped, sig); |
1366 | } | |
1367 | ||
1368 | ||
1369 | void | |
1370 | mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia) | |
1371 | { | |
1372 | ASSERT(cpu != NULL); | |
1373 | ||
1374 | if(State.exc_suspended > 0) | |
1375 | sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", State.exc_suspended); | |
1376 | ||
1377 | CIA_SET (cpu, cia); | |
1378 | memcpy(State.exc_trigger_regs, State.regs, sizeof(State.exc_trigger_regs)); | |
1379 | State.exc_suspended = 0; | |
1380 | } | |
1381 | ||
1382 | void | |
1383 | mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception) | |
1384 | { | |
1385 | ASSERT(cpu != NULL); | |
1386 | ||
1387 | if(State.exc_suspended > 0) | |
1388 | sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n", | |
1389 | State.exc_suspended, exception); | |
1390 | ||
1391 | memcpy(State.exc_suspend_regs, State.regs, sizeof(State.exc_suspend_regs)); | |
1392 | memcpy(State.regs, State.exc_trigger_regs, sizeof(State.regs)); | |
1393 | CIA_SET (cpu, PC); /* copy PC back from new State.regs */ | |
1394 | State.exc_suspended = exception; | |
1395 | } | |
1396 | ||
1397 | void | |
1398 | mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception) | |
1399 | { | |
1400 | ASSERT(cpu != NULL); | |
1401 | ||
1402 | if(exception == 0 && State.exc_suspended > 0) | |
1403 | { | |
1404 | if(State.exc_suspended != SIGTRAP) /* warn not for breakpoints */ | |
1405 | sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n", | |
1406 | State.exc_suspended); | |
1407 | } | |
1408 | else if(exception != 0 && State.exc_suspended > 0) | |
1409 | { | |
1410 | if(exception != State.exc_suspended) | |
1411 | sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n", | |
1412 | State.exc_suspended, exception); | |
1413 | ||
1414 | memcpy(State.regs, State.exc_suspend_regs, sizeof(State.regs)); | |
1415 | CIA_SET (cpu, PC); /* copy PC back from new State.regs */ | |
1416 | } | |
1417 | else if(exception != 0 && State.exc_suspended == 0) | |
1418 | { | |
1419 | sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception); | |
1420 | } | |
1421 | State.exc_suspended = 0; | |
1422 | } |