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Fix autoconf breakage + commit target.c, omitted in previous delta
[deliverable/binutils-gdb.git] / sim / mn10300 / mn10300.igen
CommitLineData
c906108c
SS		 1// -*- C -*-
2:option:::insn-bit-size:8
3:option:::insn-specifying-widths:true
4:option:::hi-bit-nr:7
5:model:::mn10300:mn10300:
c2d11a7d 6:model:::am33:am33:
c906108c
SS		 7
8// What do we do with an illegal instruction?
9:internal::::illegal:
10{
11 PC = cia;
12 program_interrupt(SD, CPU, cia, SIM_SIGILL);
13}
14
15// 1000 DnDn imm8....; mov imm8,Dn (imm8 is sign extended)
164.0x8,2.DM1,2.DN0=DM1+8.IMM8:S0i:::mov
17"mov"
18*mn10300
c2d11a7d 19*am33
c906108c
SS		 20{
21 /* OP_8000 (); */
22 signed32 immed = EXTEND8 (IMM8);
23 State.regs[REG_D0+DN0] = immed;
24 PC = cia;
25}
26
27// 1000 DmDn; mov Dm,Dn (Dm != Dn, see above when Dm == Dn)
284.0x8,2.DM1,2.DN0!DM1:S0:::mov
29"mov"
30*mn10300
c2d11a7d 31*am33
c906108c
SS		 32{
33 PC = cia;
34 /* OP_80 (); */
35 State.regs[REG_D0+DN0] = State.regs[REG_D0+DM1];
36}
37
38
39// 1111 0001 1110 DmAn; mov Dm,An
408.0xf1+1110,2.DM1,2.AN0:D0:::mov
41"mov"
42*mn10300
c2d11a7d 43*am33
c906108c
SS		 44{
45 /* OP_F1E0 (); */
46 PC = cia;
47 State.regs[REG_A0 + AN0] = State.regs[REG_D0 + DM1];
48}
49
50
51// 1111 0001 1101 AmDn; mov Am,Dn
528.0xf1+1101,2.AM1,2.DN0:D0a:::mov
53"mov"
54*mn10300
c2d11a7d 55*am33
c906108c
SS		 56{
57 /* OP_F1D0 (); */
58 PC = cia;
59 State.regs[REG_D0 + DN0] = State.regs[REG_A0 + AM1];
60}
61
62
63// 1001 AnAn imm8....; mov imm8,An (imm8 is zero-extended)
644.0x9,2.AM1,2.AN0=AM1+8.IMM8:S0ai:::mov
65"mov"
66*mn10300
c2d11a7d 67*am33
c906108c
SS		 68{
69 PC = cia;
70 /* OP_9000 (); */
71 State.regs[REG_A0+AN0] = IMM8;
72}
73
74
75// 1001 AmAn; mov Am,An (Am != An, save above when Am == An)
764.0x9,2.AM1,2.AN0!AM1:S0a:::mov
77"mov"
78*mn10300
c2d11a7d 79*am33
c906108c
SS		 80{
81 PC = cia;
82 /* OP_90 (); */
83 State.regs[REG_A0+AN0] = State.regs[REG_A0+AM1];
84}
85
86
87// 0011 11An; mov SP,An
884.0x3,11,2.AN0:S0b:::mov
89"mov"
90*mn10300
c2d11a7d 91*am33
c906108c
SS		 92{
93 /* OP_3C (); */
94 PC = cia;
95 State.regs[REG_A0 + AN0] = State.regs[REG_SP];
96}
97
98
99// 1111 0010 1111 Am00; mov Am,SP
1008.0xf2+4.0xf,2.AM1,00:D0b:::mov
101"mov"
102*mn10300
c2d11a7d 103*am33
c906108c
SS		 104{
105 /* OP_F2F0 (); */
106 PC = cia;
107 State.regs[REG_SP] = State.regs[REG_A0 + AM1];
108}
109
110
111// 1111 0010 1110 01Dn; mov PSW,Dn
1128.0xf2+4.0xe,01,2.DN0:D0c:::mov
113"mov"
114*mn10300
c2d11a7d 115*am33
c906108c
SS		 116{
117 /* OP_F2E4 (); */
118 PC = cia;
119 State.regs[REG_D0 + DN0] = PSW;
120}
121
122
123// 1111 0010 1111 Dm11; mov Dm,PSW
1248.0xf2+4.0xf,2.DM1,11:D0d:::mov
125"mov"
126*mn10300
c2d11a7d 127*am33
c906108c
SS		 128{
129 /* OP_F2F3 (); */
130 PC = cia;
131 PSW = State.regs[REG_D0 + DM1];
132}
133
134
135// 1111 0010 1110 00Dn; mov MDR,Dn
1368.0xf2+4.0xe,00,2.DN0:D0e:::mov
137"mov"
138*mn10300
c2d11a7d 139*am33
c906108c
SS		 140{
141 /* OP_F2E0 (); */
142 PC = cia;
143 State.regs[REG_D0 + DN0] = State.regs[REG_MDR];
144}
145
146
147// 1111 0010 1111 Dm10; mov Dm,MDR
1488.0xf2+4.0xf,2.DM1,10:D0f:::mov
149"mov"
150*mn10300
c2d11a7d 151*am33
c906108c
SS		 152{
153 /* OP_F2F2 (); */
154 PC = cia;
155 State.regs[REG_MDR] = State.regs[REG_D0 + DM1];
156}
157
158
159// 0111 DnAm; mov (Am),Dn
1604.0x7,2.DN1,2.AM0:S0c:::mov
161"mov"
162*mn10300
c2d11a7d 163*am33
c906108c
SS		 164{
165 /* OP_70 (); */
166 PC = cia;
167 State.regs[REG_D0 + DN1] = load_word (State.regs[REG_A0 + AM0]);
168}
169
170
171// 1111 1000 0000 DnAm d8......; mov (d8,Am),Dn (d8 is sign-extended)
1728.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov
173"mov"
174*mn10300
c2d11a7d 175*am33
c906108c
SS		 176{
177 /* OP_F80000 (); */
178 PC = cia;
179 State.regs[REG_D0 + DN1]
180 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
181}
182
183
184// 1111 1010 0000 DnAm d16.....; mov (d16,Am),Dn (d16 is sign-extended.)
1858.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov
186"mov"
187*mn10300
c2d11a7d 188*am33
c906108c
SS		 189{
190 /* OP_FA000000 (); */
191 PC = cia;
192 State.regs[REG_D0 + DN1]
193 = load_word ((State.regs[REG_A0 + AM0] + EXTEND16 (FETCH16(D16A, D16B))));
194}
195
196
197// 1111 1100 0000 DnAm d32.....; mov (d32,Am),Dn
1988.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov
199"mov"
200*mn10300
c2d11a7d 201*am33
c906108c
SS		 202{
203 /* OP_FC000000 (); */
204 PC = cia;
205 State.regs[REG_D0 + DN1]
206 = load_word ((State.regs[REG_A0 + AM0]
207 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
208}
209
210
211// 0101 10Dn d8......; mov (d8,SP),Dn (d8 is zero-extended)
2124.0x5,10,2.DN0+8.D8:S1:::mov
213"mov"
214*mn10300
c2d11a7d 215*am33
c906108c
SS		 216{
217 /* OP_5800 (); */
218 PC = cia;
219 State.regs[REG_D0 + DN0] = load_word (State.regs[REG_SP] + D8);
220}
221
222
223// 1111 1010 1011 01Dn d16.....; mov (d16,SP),Dn (d16 is zero-extended.)
2248.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov
225"mov"
226*mn10300
c2d11a7d 227*am33
c906108c
SS		 228{
229 /* OP_FAB40000 (); */
230 PC = cia;
231 State.regs[REG_D0 + DN0]
232 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
233}
234
235
236// 1111 1010 1011 01Dn d32.....; mov (d32,SP),Dn
2378.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov
238"mov"
239*mn10300
c2d11a7d 240*am33
c906108c
SS		 241{
242 /* OP_FCB40000 (); */
243 PC = cia;
244 State.regs[REG_D0 + DN0]
245 = load_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
246}
247
248
249// 1111 0011 00Dn DiAm; mov (Di,Am),Dn
2508.0xf3+00,2.DN2,2.DI,2.AM0:D0g:::mov
251"mov"
252*mn10300
c2d11a7d 253*am33
c906108c
SS		 254{
255 /* OP_F300 (); */
256 PC = cia;
257 State.regs[REG_D0 + DN2]
258 = load_word ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
259}
260
261
262// 0011 00Dn abs16...; mov (abs16),Dn (abs16 is zero-extended)
2634.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov
264"mov"
265*mn10300
c2d11a7d 266*am33
c906108c
SS		 267{
268 /* OP_300000 (); */
269 PC = cia;
270 State.regs[REG_D0 + DN0] = load_word (FETCH16(IMM16A, IMM16B));
271}
272
273// 1111 1100 1010 01Dn abs32...; mov (abs32),Dn
2748.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov
275"mov"
276*mn10300
c2d11a7d 277*am33
c906108c
SS		 278{
279 /* OP_FCA40000 (); */
280 PC = cia;
281 State.regs[REG_D0 + DN0] = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
282}
283
284
285// 1111 0000 0000 AnAm; mov (Am),An
2868.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov
287"mov"
288*mn10300
c2d11a7d 289*am33
c906108c
SS		 290{
291 /* OP_F000 (); */
292 PC = cia;
293 State.regs[REG_A0 + AN1] = load_word (State.regs[REG_A0 + AM0]);
294}
295
296
297// 1111 1000 0010 AnAm d8......; mov (d8,Am),An (d8 is sign-extended)
2988.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov
299"mov"
300*mn10300
c2d11a7d 301*am33
c906108c
SS		 302{
303 /* OP_F82000 (); */
304 PC = cia;
305 State.regs[REG_A0 + AN1]
306 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
307}
308
309
310// 1111 1010 0010 AnAm d16.....; mov (d16,Am),An (d16 is sign-extended.)
3118.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov
312"mov"
313*mn10300
c2d11a7d 314*am33
c906108c
SS		 315{
316 /* OP_FA200000 (); */
317 PC = cia;
318 State.regs[REG_A0 + AN1]
319 = load_word ((State.regs[REG_A0 + AM0]
320 + EXTEND16 (FETCH16(D16A, D16B))));
321}
322
323
324// 1111 1100 0010 AnAm d32.....; mov (d32,Am),An
3258.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov
326"mov"
327*mn10300
c2d11a7d 328*am33
c906108c
SS		 329{
330 /* OP_FC200000 (); */
331 PC = cia;
332 State.regs[REG_A0 + AN1]
333 = load_word ((State.regs[REG_A0 + AM0]
334 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
335}
336
337
338// 0101 11An d8......; mov (d8,SP),An (d8 is zero-extended)
3394.0x5,11,2.AN0+8.D8:S1a:::mov
340"mov"
341*mn10300
c2d11a7d 342*am33
c906108c
SS		 343{
344 /* OP_5C00 (); */
345 PC = cia;
346 State.regs[REG_A0 + AN0]
347 = load_word (State.regs[REG_SP] + D8);
348}
349
350
351// 1111 1010 1011 00An d16.....; mov (d16,SP),An (d16 is zero-extended.)
3528.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov
353"mov"
354*mn10300
c2d11a7d 355*am33
c906108c
SS		 356{
357 /* OP_FAB00000 (); */
358 PC = cia;
359 State.regs[REG_A0 + AN0]
360 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
361}
362
363
364// 1111 1100 1011 00An d32.....; mov (d32,SP),An
3658.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov
366"mov"
367*mn10300
c2d11a7d 368*am33
c906108c
SS		 369{
370 /* OP_FCB00000 (); */
371 PC = cia;
372 State.regs[REG_A0 + AN0]
373 = load_word (State.regs[REG_SP]
374 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
375}
376
377
378// 1111 0011 10An DiAm; mov (Di,Am),An
3798.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov
380"mov"
381*mn10300
c2d11a7d 382*am33
c906108c
SS		 383{
384 /* OP_F380 (); */
385 PC = cia;
386 State.regs[REG_A0 + AN2]
387 = load_word ((State.regs[REG_A0 + AM0]
388 + State.regs[REG_D0 + DI]));
389}
390
391
392// 1111 1010 1010 00An abs16...; mov (abs16),An (abs16 is zero-extended)
3938.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov
394"mov"
395*mn10300
c2d11a7d 396*am33
c906108c
SS		 397{
398 /* OP_FAA00000 (); */
399 PC = cia;
400 State.regs[REG_A0 + AN0] = load_word (FETCH16(IMM16A, IMM16B));
401}
402
403
404// 1111 1100 1010 00An abs32...; mov (abs32),An
4058.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov
406"mov"
407*mn10300
c2d11a7d 408*am33
c906108c
SS		 409{
410 /* OP_FCA00000 (); */
411 PC = cia;
412 State.regs[REG_A0 + AN0]
413 = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
414}
415
416
417// 1111 1000 1111 00Am d8......; mov (d8,Am),SP (d8 is sign-extended)
4188.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov
419"mov"
420*mn10300
c2d11a7d 421*am33
c906108c
SS		 422{
423 /* OP_F8F000 (); */
424 PC = cia;
425 State.regs[REG_SP]
426 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
427}
428
429
430// 0110 DmAn; mov Dm,(An)
4314.0x6,2.DM1,2.AN0:S0d:::mov
432"mov"
433*mn10300
c2d11a7d 434*am33
c906108c
SS		 435{
436 /* OP_60 (); */
437 PC = cia;
438 store_word (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
439}
440
441
442// 1111 1000 0001 DmAn d8......; mov Dm,(d8,An) (d8 is sign-extended)
4438.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov
444"mov"
445*mn10300
c2d11a7d 446*am33
c906108c
SS		 447{
448 /* OP_F81000 (); */
449 PC = cia;
450 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
451 State.regs[REG_D0 + DM1]);
452}
453
454
455// 1111 1010 0001 DmAn d16.....; mov Dm,(d16,An) (d16 is sign-extended.)
4568.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov
457"mov"
458*mn10300
c2d11a7d 459*am33
c906108c
SS		 460{
461 /* OP_FA100000 (); */
462 PC = cia;
463 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
464 State.regs[REG_D0 + DM1]);
465}
466
467
468// 1111 1100 0001 DmAn d32.....; mov Dm,(d32,An)
4698.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov
470"mov"
471*mn10300
c2d11a7d 472*am33
c906108c
SS		 473{
474 /* OP_FC100000 (); */
475 PC = cia;
476 store_word ((State.regs[REG_A0 + AN0]
477 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
478 State.regs[REG_D0 + DM1]);
479}
480
481
482// 0100 Dm10 d8......; mov Dm,(d8,SP) (d8 is zero-extended)
4834.0x4,2.DM1,10+8.D8:S1b:::mov
484"mov"
485*mn10300
c2d11a7d 486*am33
c906108c
SS		 487{
488 /* OP_4200 (); */
489 PC = cia;
490 store_word (State.regs[REG_SP] + D8, State.regs[REG_D0 + DM1]);
491}
492
493
494// 1111 1010 1001 Dm01 d16.....; mov Dm,(d16,SP) (d16 is zero-extended.)
4958.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov
496"mov"
497*mn10300
c2d11a7d 498*am33
c906108c
SS		 499{
500 /* OP_FA910000 (); */
501 PC = cia;
502 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
503 State.regs[REG_D0 + DM1]);
504}
505
506
507// 1111 1100 1001 Dm01 d32.....; mov Dm,(d32,SP)
5088.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov
509"mov"
510*mn10300
c2d11a7d 511*am33
c906108c
SS		 512{
513 /* OP_FC910000 (); */
514 PC = cia;
515 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
516 State.regs[REG_D0 + DM1]);
517}
518
519
520// 1111 0011 01Dm DiAn; mov Dm,(Di,An)
5218.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov
522"mov"
523*mn10300
c2d11a7d 524*am33
c906108c
SS		 525{
526 /* OP_F340 (); */
527 PC = cia;
528 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
529 State.regs[REG_D0 + DM2]);
530}
531
532
533// 0000 Dm01 abs16..., mov Dm,(abs16) (abs16 is zero-extended).
5344.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov
535"mov"
536*mn10300
c2d11a7d 537*am33
c906108c
SS		 538{
539 /* OP_10000 (); */
540 PC = cia;
541 store_word (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
542}
543
544
545// 1111 1100 1000 Dm01 abs32...; mov Dm,(abs32)
5468.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov
547"mov"
548*mn10300
c2d11a7d 549*am33
c906108c
SS		 550{
551 /* OP_FC810000 (); */
552 PC = cia;
553 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
554 State.regs[REG_D0 + DM1]);
555}
556
557
558// 1111 0000 0001 AmAn; mov Am,(An)
5598.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov
560"mov"
561*mn10300
c2d11a7d 562*am33
c906108c
SS		 563{
564 /* OP_F010 (); */
565 PC = cia;
566 store_word (State.regs[REG_A0 + AN0], State.regs[REG_A0 + AM1]);
567}
568
569
570// 1111 1000 0011 AmAn d8......; mov Am,(d8,An) (d8 is sign-extended)
5718.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov
572"mov"
573*mn10300
c2d11a7d 574*am33
c906108c
SS		 575{
576 /* OP_F83000 (); */
577 PC = cia;
578 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
579 State.regs[REG_A0 + AM1]);
580}
581
582
583// 1111 1010 0011 AmAn d16.....; mov Am,(d16,An) (d16 is sign-extended.)
5848.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov
585"mov"
586*mn10300
c2d11a7d 587*am33
c906108c
SS		 588{
589 /* OP_FA300000 (); */
590 PC = cia;
591 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
592 State.regs[REG_A0 + AM1]);
593}
594
595
596// 1111 1100 0011 AmAn d32.....; mov Am,(d32,An)
5978.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov
598"mov"
599*mn10300
c2d11a7d 600*am33
c906108c
SS		 601{
602 /* OP_FC300000 (); */
603 PC = cia;
604 store_word ((State.regs[REG_A0 + AN0]
605 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
606 State.regs[REG_A0 + AM1]);
607}
608
609
610// 0100 Am11 d8......; mov Am,(d8,SP) (d8 is zero-extended)
6114.0x4,2.AM1,11+8.D8:S1c:::mov
612"mov"
613*mn10300
c2d11a7d
JM		 614
615*am33
616
c906108c
SS		 617{
618 /* OP_4300 (); */
619 PC = cia;
620 store_word (State.regs[REG_SP] + (D8), State.regs[REG_A0 + (AM1)]);
621}
622
623
624// 1111 1010 1001 Am00 d16.....; mov Am,(d16,SP) (d16 is zero-extended.)
6258.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov
626"mov"
627*mn10300
c2d11a7d
JM		 628
629*am33
630
c906108c
SS		 631{
632 /* OP_FA900000 (); */
633 PC = cia;
634 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
635 State.regs[REG_A0 + AM1]);
636}
637
638
639// 1111 1100 1001 Am00 d32.....; mov Am,(d32,SP)
6408.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov
641"mov"
642*mn10300
c2d11a7d
JM		 643
644*am33
645
c906108c
SS		 646{
647 /* OP_FC900000 (); */
648 PC = cia;
649 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
650 State.regs[REG_A0 + AM1]);
651}
652
653
654// 1111 0011 11Am DiAn; mov Am,(Di,An)
6558.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov
656"mov"
657*mn10300
c2d11a7d
JM		 658
659*am33
660
c906108c
SS		 661{
662 /* OP_F3C0 (); */
663 PC = cia;
664 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
665 State.regs[REG_A0 + AM2]);
666}
667
668
669// 1111 1010 1000 Am00 abs16...; mov Am,(abs16) (abs16 is zero-extended)
6708.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov
671"mov"
672*mn10300
c2d11a7d
JM		 673
674*am33
675
c906108c
SS		 676{
677 /* OP_FA800000 (); */
678 PC = cia;
679 store_word (FETCH16(IMM16A, IMM16B),
680 State.regs[REG_A0 + AM1]);
681}
682
683
684// 1111 1100 1000 Am00 abs32...; mov Am,(abs32)
6858.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov
686"mov"
687*mn10300
c2d11a7d
JM		 688
689*am33
690
c906108c
SS		 691{
692 /* OP_FC800000 (); */
693 PC = cia;
694 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
695 State.regs[REG_A0 + AM1]);
696}
697
698
699// 1111 1000 1111 01An d8......; mov SP,(d8,An) (d8 is sign-extended)
7008.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov
701"mov"
702*mn10300
c2d11a7d
JM		 703
704*am33
705
c906108c
SS		 706{
707 /* OP_F8F400 (); */
708 PC = cia;
709 store_word (State.regs[REG_A0 + AN0] + EXTEND8 (D8),
710 State.regs[REG_SP]);
711}
712
713
714// 0010 11Dn imm16...; mov imm16,Dn (imm16 is sign-extended)
7154.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov
716"mov"
717*mn10300
c2d11a7d
JM		 718
719*am33
720
c906108c
SS		 721{
722 /* OP_2C0000 (); */
24a39d88 723 unsigned32 value;
c906108c
SS		 724
725 PC = cia;
726 value = EXTEND16 (FETCH16(IMM16A, IMM16B));
727 State.regs[REG_D0 + DN0] = value;
728}
729
730
731// 1111 1100 1100 11Dn imm32...; mov imm32,Dn
7328.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov
733"mov"
734*mn10300
c2d11a7d
JM		 735
736*am33
737
c906108c
SS		 738{
739 /* OP_FCCC0000 (); */
24a39d88 740 unsigned32 value;
c906108c
SS		 741
742 PC = cia;
743 value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
744 State.regs[REG_D0 + DN0] = value;
745}
746
747
748// 0010 01An imm16...; mov imm16,An (imm16 is zero-extended)
7494.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov
750"mov"
751*mn10300
c2d11a7d
JM		 752
753*am33
754
c906108c
SS		 755{
756 /* OP_240000 (); */
24a39d88 757 unsigned32 value;
c906108c
SS		 758
759 PC = cia;
760 value = FETCH16(IMM16A, IMM16B);
761 State.regs[REG_A0 + AN0] = value;
762}
763
764
765// 1111 1100 1101 11An imm32...; mov imm32,An
7668.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov
767"mov"
768*mn10300
c2d11a7d
JM		 769
770*am33
771
c906108c
SS		 772{
773 /* OP_FCDC0000 (); */
774 PC = cia;
775 State.regs[REG_A0 + AN0] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
776}
777
778
779// 1111 0000 0100 DnAm; movbu (Am),Dn
7808.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu
781"movbu"
782*mn10300
c2d11a7d
JM		 783
784*am33
785
c906108c
SS		 786{
787 /* OP_F040 (); */
788 PC = cia;
789 State.regs[REG_D0 + DN1]
790 = load_byte (State.regs[REG_A0 + AM0]);
791}
792
793
794// 1111 1000 0100 DnAm d8......; movbu (d8,Am),Dn (d8 is sign-extended)
7958.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu
796"movbu"
797*mn10300
c2d11a7d
JM		 798
799*am33
800
c906108c
SS		 801{
802 /* OP_F84000 (); */
803 PC = cia;
804 State.regs[REG_D0 + DN1]
805 = load_byte ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
806}
807
808
809// 1111 1010 0100 DnAm d16.....; movbu (d16,Am),Dn (d16 is sign-extended.)
8108.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu
811"movbu"
812*mn10300
c2d11a7d
JM		 813
814*am33
815
c906108c
SS		 816{
817 /* OP_FA400000 (); */
818 PC = cia;
819 State.regs[REG_D0 + DN1]
820 = load_byte ((State.regs[REG_A0 + AM0]
821 + EXTEND16 (FETCH16(D16A, D16B))));
822}
823
824
825// 1111 1100 0100 DnAm d32.....; movbu (d32,Am),Dn
8268.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu
827"movbu"
828*mn10300
c2d11a7d
JM		 829
830*am33
831
c906108c
SS		 832{
833 /* OP_FC400000 (); */
834 PC = cia;
835 State.regs[REG_D0 + DN1]
836 = load_byte ((State.regs[REG_A0 + AM0]
837 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
838}
839
840
841// 1111 1000 1011 10Dn d8......; movbu (d8,SP),Dn (d8 is zero-extended)
8428.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu
843"movbu"
844*mn10300
c2d11a7d
JM		 845
846*am33
847
c906108c
SS		 848{
849 /* OP_F8B800 (); */
850 PC = cia;
851 State.regs[REG_D0 + DN0]
852 = load_byte ((State.regs[REG_SP] + (D8)));
853}
854
855
856// 1111 1010 1011 10Dn d16.....; movbu (d16,SP),Dn (d16 is zero-extended.)
8578.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu
858"movbu"
859*mn10300
c2d11a7d
JM		 860
861*am33
862
c906108c
SS		 863{
864 /* OP_FAB80000 (); */
865 PC = cia;
866 State.regs[REG_D0 + DN0]
867 = load_byte ((State.regs[REG_SP]
868 + FETCH16(IMM16A, IMM16B)));
869}
870
871
872// 1111 1100 1011 10Dn d32.....; movbu (d32,SP),Dn
8738.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu
874"movbu"
875*mn10300
c2d11a7d
JM		 876
877*am33
878
c906108c
SS		 879{
880 /* OP_FCB80000 (); */
881 PC = cia;
882 State.regs[REG_D0 + DN0]
883 = load_byte (State.regs[REG_SP]
884 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
885}
886
887
888// 1111 0100 00Dn DiAm; movbu (Di,Am),Dn
8898.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu
890"movbu"
891*mn10300
c2d11a7d
JM		 892
893*am33
894
c906108c
SS		 895{
896 /* OP_F400 (); */
897 PC = cia;
898 State.regs[REG_D0 + DN2]
899 = load_byte ((State.regs[REG_A0 + AM0]
900 + State.regs[REG_D0 + DI]));
901}
902
903
904// 0011 01Dn abs16...; movbu (abs16),Dn (abs16 is zero-extended)
9054.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu
906"movbu"
907*mn10300
c2d11a7d
JM		 908
909*am33
910
c906108c
SS		 911{
912 /* OP_340000 (); */
913 PC = cia;
914 State.regs[REG_D0 + DN0] = load_byte (FETCH16(IMM16A, IMM16B));
915}
916
917
918// 1111 1100 1010 10Dn abs32...; movbu (abs32),Dn
9198.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu
920"movbu"
921*mn10300
c2d11a7d
JM		 922
923*am33
924
c906108c
SS		 925{
926 /* OP_FCA80000 (); */
927 PC = cia;
928 State.regs[REG_D0 + DN0]
929 = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
930}
931
932
933// 1111 0000 0101 DmAn; movbu Dm,(An)
9348.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu
935"movbu"
936*mn10300
c2d11a7d
JM		 937
938*am33
939
c906108c
SS		 940{
941 /* OP_F050 (); */
942 PC = cia;
943 store_byte (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
944}
945
946
947// 1111 1000 0101 DmAn d8......; movbu Dm,(d8,An) (d8 is sign-extended)
9488.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu
949"movbu"
950*mn10300
c2d11a7d
JM		 951
952*am33
953
c906108c
SS		 954{
955 /* OP_F85000 (); */
956 PC = cia;
957 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
958 State.regs[REG_D0 + DM1]);
959}
960
961
962// 1111 1010 0101 DmAn d16.....; movbu Dm,(d16,An) (d16 is sign-extended.)
9638.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu
964"movbu"
965*mn10300
c2d11a7d
JM		 966
967*am33
968
c906108c
SS		 969{
970 /* OP_FA500000 (); */
971 PC = cia;
972 store_byte ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
973 State.regs[REG_D0 + DM1]);
974}
975
976
977// 1111 1100 0101 DmAn d32.....; movbu Dm,(d32,An)
9788.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu
979"movbu"
980*mn10300
c2d11a7d
JM		 981
982*am33
983
c906108c
SS		 984{
985 /* OP_FC500000 (); */
986 PC = cia;
987 store_byte ((State.regs[REG_A0 + AN0]
988 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
989 State.regs[REG_D0 + DM1]);
990}
991
992
993// 1111 1000 1001 Dm10 d8......; movbu Dm,(d8,SP) (d8 is zero-extended)
9948.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu
995"movbu"
996*mn10300
c2d11a7d
JM		 997
998*am33
999
c906108c
SS		 1000{
1001 /* OP_F89200 (); */
1002 PC = cia;
1003 store_byte (State.regs[REG_SP] + (D8), State.regs[REG_D0 + DM1]);
1004}
1005
1006
1007// 1111 1010 1001 Dm10 d16.....; movbu Dm,(d16,SP) (d16 is zero-extended.)
10088.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu
1009"movbu"
1010*mn10300
c2d11a7d
JM		 1011
1012*am33
1013
c906108c
SS		 1014{
1015 /* OP_FA920000 (); */
1016 PC = cia;
1017 store_byte (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1018 State.regs[REG_D0 + DM1]);
1019}
1020
1021
1022// 1111 1100 1001 Dm10 d32.....; movbu Dm,(d32,SP)
10238.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu
1024"movbu"
1025*mn10300
c2d11a7d
JM		 1026
1027*am33
1028
c906108c
SS		 1029{
1030 /* OP_FC920000 (); */
1031 PC = cia;
1032 store_byte (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1033 State.regs[REG_D0 + DM1]);
1034}
1035
1036
1037// 1111 0100 01Dm DiAn; movbu Dm,(Di,An)
10388.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu
1039"movbu"
1040*mn10300
c2d11a7d
JM		 1041
1042*am33
1043
c906108c
SS		 1044{
1045 /* OP_F440 (); */
1046 PC = cia;
1047 store_byte ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1048 State.regs[REG_D0 + DM2]);
1049}
1050
1051
1052// 0000 Dm10 abs16...; movbu Dm,(abs16) (abs16 is zero-extended)
10534.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu
1054"movbu"
1055*mn10300
c2d11a7d
JM		 1056
1057*am33
1058
c906108c
SS		 1059{
1060 /* OP_20000 (); */
1061 PC = cia;
1062 store_byte (FETCH16(IMM16A, IMM16B),
1063 State.regs[REG_D0 + DM1]);
1064}
1065
1066
1067// 1111 1100 1000 Dm10 abs32...; movbu Dm,(abs32)
10688.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu
1069"movbu"
1070*mn10300
c2d11a7d
JM		 1071
1072*am33
1073
c906108c
SS		 1074{
1075 /* OP_FC820000 (); */
1076 PC = cia;
1077 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1078 State.regs[REG_D0 + DM1]);
1079}
1080
1081
1082// 1111 0000 0110 DnAm; movhu (Am),Dn
10838.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu
1084"movhu"
1085*mn10300
c2d11a7d
JM		 1086
1087*am33
1088
c906108c
SS		 1089{
1090 /* OP_F060 (); */
1091 PC = cia;
1092 State.regs[REG_D0 + DN1]
1093 = load_half (State.regs[REG_A0 + AM0]);
1094}
1095
1096
1097// 1111 1000 0110 DnAm d8......; movhu (d8,Am),Dn (d8 is sign-extended)
10988.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu
1099"movhu"
1100*mn10300
c2d11a7d
JM		 1101
1102*am33
1103
c906108c
SS		 1104{
1105 /* OP_F86000 (); */
1106 PC = cia;
1107 State.regs[REG_D0 + DN1]
1108 = load_half ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
1109}
1110
1111
1112// 1111 1010 0110 DnAm d16.....; movhu (d16,Am),Dn (d16 is sign-extended.)
11138.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu
1114"movhu"
1115*mn10300
c2d11a7d
JM		 1116
1117*am33
1118
c906108c
SS		 1119{
1120 /* OP_FA600000 (); */
1121 PC = cia;
1122 State.regs[REG_D0 + DN1]
1123 = load_half ((State.regs[REG_A0 + AM0]
1124 + EXTEND16 (FETCH16(D16A, D16B))));
1125}
1126
1127
1128// 1111 1100 0110 DnAm d32.....; movhu (d32,Am),Dn
11298.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu
1130"movhu"
1131*mn10300
c2d11a7d
JM		 1132
1133*am33
1134
c906108c
SS		 1135{
1136 /* OP_FC600000 (); */
1137 PC = cia;
1138 State.regs[REG_D0 + DN1]
1139 = load_half ((State.regs[REG_A0 + AM0]
1140 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
1141}
1142
1143
1144// 1111 1000 1011 11Dn d8.....; movhu (d8,SP),Dn (d8 is zero-extended)
11458.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu
1146"movhu"
1147*mn10300
c2d11a7d
JM		 1148
1149*am33
1150
c906108c
SS		 1151{
1152 /* OP_F8BC00 (); */
1153 PC = cia;
1154 State.regs[REG_D0 + DN0]
1155 = load_half ((State.regs[REG_SP] + (D8)));
1156}
1157
1158
1159// 1111 1010 1011 11Dn d16.....; movhu (d16,SP),Dn (d16 is zero-extended.)
11608.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu
1161"movhu"
1162*mn10300
c2d11a7d
JM		 1163
1164*am33
1165
c906108c
SS		 1166{
1167 /* OP_FABC0000 (); */
1168 PC = cia;
1169 State.regs[REG_D0 + DN0]
1170 = load_half ((State.regs[REG_SP] + FETCH16(IMM16A, IMM16B)));
1171}
1172
1173
1174// 1111 1100 1011 11Dn d32.....; movhu (d32,SP),Dn
11758.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu
1176"movhu"
1177*mn10300
c2d11a7d
JM		 1178
1179*am33
1180
c906108c
SS		 1181{
1182 /* OP_FCBC0000 (); */
1183 PC = cia;
1184 State.regs[REG_D0 + DN0]
1185 = load_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1186}
1187
1188
1189// 1111 0100 10Dn DiAm; movhu (Di,Am),Dn
11908.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu
1191"movhu"
1192*mn10300
c2d11a7d
JM		 1193
1194*am33
1195
c906108c
SS		 1196{
1197 /* OP_F480 (); */
1198 PC = cia;
1199 State.regs[REG_D0 + DN2]
1200 = load_half ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
1201}
1202
1203
1204// 0011 10Dn abs16...; movhu (abs16),Dn (abs16 is zero-extended)
12054.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu
1206"movhu"
1207*mn10300
c2d11a7d
JM		 1208
1209*am33
1210
c906108c
SS		 1211{
1212 /* OP_380000 (); */
1213 PC = cia;
1214 State.regs[REG_D0 + DN0] = load_half (FETCH16(IMM16A, IMM16B));
1215}
1216
1217
1218// 1111 1100 1010 11Dn abs32...; movhu (abs32),Dn
12198.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu
1220"movhu"
1221*mn10300
c2d11a7d
JM		 1222
1223*am33
1224
c906108c
SS		 1225{
1226 /* OP_FCAC0000 (); */
1227 PC = cia;
1228 State.regs[REG_D0 + DN0]
1229 = load_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1230}
1231
1232
1233// 1111 0000 0111 DmAn; movhu Dm,(An)
12348.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu
1235"movhu"
1236*mn10300
c2d11a7d
JM		 1237
1238*am33
1239
c906108c
SS		 1240{
1241 /* OP_F070 (); */
1242 PC = cia;
1243 store_half (State.regs[REG_A0 + AN0],
1244 State.regs[REG_D0 + DM1]);
1245}
1246
1247
1248// 1111 1000 0111 DmAn d8......; movhu Dm,(d8,An) (d8 is sign-extended)
12498.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu
1250"movhu"
1251*mn10300
c2d11a7d
JM		 1252
1253*am33
1254
c906108c
SS		 1255{
1256 /* OP_F87000 (); */
1257 PC = cia;
1258 store_half ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
1259 State.regs[REG_D0 + DM1]);
1260}
1261
1262
1263// 1111 1010 0111 DnAm d16.....; movhu Dm,(d16,An) (d16 is sign-extended.)
12648.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu
1265"movhu"
1266*mn10300
c2d11a7d
JM		 1267
1268*am33
1269
c906108c
SS		 1270{
1271 /* OP_FA700000 (); */
1272 PC = cia;
1273 store_half ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
1274 State.regs[REG_D0 + DM1]);
1275}
1276
1277
1278// 1111 1100 0111 DmAn d32.....; movhu Dm,(d32,An)
12798.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu
1280"movhu"
1281*mn10300
c2d11a7d
JM		 1282
1283*am33
1284
c906108c
SS		 1285{
1286 /* OP_FC700000 (); */
1287 PC = cia;
1288 store_half ((State.regs[REG_A0 + AN0]
1289 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
1290 State.regs[REG_D0 + DM1]);
1291}
1292
1293
1294// 1111 1000 1001 Dm11 d8....; movhu Dm,(d8,SP) (d8 is zero-extended)
12958.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu
1296"movhu"
1297*mn10300
c2d11a7d
JM		 1298
1299*am33
1300
c906108c
SS		 1301{
1302 /* OP_F89300 (); */
1303 PC = cia;
1304 store_half (State.regs[REG_SP] + (D8),
1305 State.regs[REG_D0 + DM1]);
1306}
1307
1308
1309// 1111 1010 1001 Dm11 d16.....; movhu Dm,(d16,SP) (d16 is zero-extended.)
13108.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu
1311"movhu"
1312*mn10300
c2d11a7d
JM		 1313
1314*am33
1315
c906108c
SS		 1316{
1317 /* OP_FA930000 (); */
1318 PC = cia;
1319 store_half (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1320 State.regs[REG_D0 + DM1]);
1321}
1322
1323
1324// 1111 1100 1001 Dm11 d32.....; movhu Dm,(d32,SP)
13258.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu
1326"movhu"
1327*mn10300
c2d11a7d
JM		 1328
1329*am33
1330
c906108c
SS		 1331{
1332 /* OP_FC930000 (); */
1333 PC = cia;
1334 store_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1335 State.regs[REG_D0 + DM1]);
1336}
1337
1338
1339// 1111 0100 11Dm DiAn; movhu Dm,(Di,An)
13408.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu
1341"movhu"
1342*mn10300
c2d11a7d
JM		 1343
1344*am33
1345
c906108c
SS		 1346{
1347 /* OP_F4C0 (); */
1348 PC = cia;
1349 store_half ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1350 State.regs[REG_D0 + DM2]);
1351}
1352
1353
1354// 0000 Dm11 abs16...; movhu Dm,(abs16) (abs16 is zero-extended)
13554.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu
1356"movhu"
1357*mn10300
c2d11a7d
JM		 1358
1359*am33
1360
c906108c
SS		 1361{
1362 /* OP_30000 (); */
1363 PC = cia;
1364 store_half (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
1365}
1366
1367
1368// 1111 1100 1000 Dm11 abs32...; movhu Dm,(abs32)
13698.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu
1370"movhu"
1371*mn10300
c2d11a7d
JM		 1372
1373*am33
1374
c906108c
SS		 1375{
1376 /* OP_FC830000 (); */
1377 PC = cia;
1378 store_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1379 State.regs[REG_D0 + DM1]);
1380}
1381
1382
1383// 1111 0010 1101 00Dn; ext Dn
13848.0xf2+4.0xd,00,2.DN0:D0:::ext
1385"ext"
1386*mn10300
c2d11a7d
JM		 1387
1388*am33
1389
c906108c
SS		 1390{
1391 /* OP_F2D0 (); */
1392 PC = cia;
1393 if (State.regs[REG_D0 + DN0] & 0x80000000)
1394 State.regs[REG_MDR] = -1;
1395 else
1396 State.regs[REG_MDR] = 0;
1397}
1398
1399
1400// 0001 00Dn; extb Dn
14014.0x1,00,2.DN0:S0:::extb
1402"extb"
1403*mn10300
c2d11a7d
JM		 1404
1405*am33
1406
c906108c
SS		 1407{
1408 /* OP_10 (); */
1409 PC = cia;
1410 State.regs[REG_D0 + DN0] = EXTEND8 (State.regs[REG_D0 + DN0]);
1411}
1412
1413
1414// 0001 01Dn; extbu Dn
14154.0x1,01,2.DN0:S0:::extbu
1416"extbu"
1417*mn10300
c2d11a7d
JM		 1418
1419*am33
1420
c906108c
SS		 1421{
1422 /* OP_14 (); */
1423 PC = cia;
1424 State.regs[REG_D0 + DN0] &= 0xff;
1425}
1426
1427
1428// 0001 10Dn; exth Dn
14294.0x1,10,2.DN0:S0:::exth
1430"exth"
1431*mn10300
c2d11a7d
JM		 1432
1433*am33
1434
c906108c
SS		 1435{
1436 /* OP_18 (); */
1437 PC = cia;
1438 State.regs[REG_D0 + DN0] = EXTEND16 (State.regs[REG_D0 + DN0]);
1439}
1440
1441
1442// 0001 11Dn; exthu Dn
14434.0x1,11,2.DN0:S0:::exthu
1444"exthu"
1445*mn10300
c2d11a7d
JM		 1446
1447*am33
1448
c906108c
SS		 1449{
1450 /* OP_1C (); */
1451 PC = cia;
1452 State.regs[REG_D0 + DN0] &= 0xffff;
1453}
1454
1455
1456// 0000 Dn00; clr Dn
14574.0x0,2.DN1,00:S0:::clr
1458"clr"
1459*mn10300
c2d11a7d
JM		 1460
1461*am33
1462
c906108c
SS		 1463{
1464 /* OP_0 (); */
1465 PC = cia;
1466 State.regs[REG_D0 + DN1] = 0;
1467
1468 PSW |= PSW_Z;
1469 PSW &= ~(PSW_V | PSW_C | PSW_N);
1470}
1471
1472
1473// 1110 DmDn; add Dm,Dn
14744.0xe,2.DM1,2.DN0:S0:::add
1475"add"
1476*mn10300
c2d11a7d
JM		 1477
1478*am33
1479
c906108c
SS		 1480{
1481 /* OP_E0 (); */
1482 PC = cia;
1483 genericAdd(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1484}
1485
1486// 1111 0001 0110 DmAn; add Dm,An
14878.0xf1+4.0x6,2.DM1,2.AN0:D0:::add
1488"add"
1489*mn10300
c2d11a7d
JM		 1490
1491*am33
1492
c906108c
SS		 1493{
1494 /* OP_F160 (); */
1495 PC = cia;
1496 genericAdd(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1497}
1498
1499
1500// 1111 0001 0101 AmDn; add Am,Dn
15018.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add
1502"add"
1503*mn10300
c2d11a7d
JM		 1504
1505*am33
1506
c906108c
SS		 1507{
1508 /* OP_F150 (); */
1509 PC = cia;
1510 genericAdd(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1511}
1512
1513
1514// 1111 0001 0111 AmAn; add Am,An
15158.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add
1516"add"
1517*mn10300
c2d11a7d
JM		 1518
1519*am33
1520
c906108c
SS		 1521{
1522 /* OP_F170 (); */
1523 PC = cia;
1524 genericAdd(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1525}
1526
1527
1528// 0010 10Dn imm8....; add imm8,Dn (imm8 is sign-extended)
15294.0x2,10,2.DN0+8.IMM8:S1:::add
1530"add"
1531*mn10300
c2d11a7d
JM		 1532
1533*am33
1534
c906108c
SS		 1535{
1536 /* OP_2800 (); */
1537 PC = cia;
1538 genericAdd(EXTEND8(IMM8), REG_D0 + DN0);
1539}
1540
1541
1542// 1111 1010 1100 00Dn imm16...; add imm16,Dn
15438.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add
1544"add"
1545*mn10300
c2d11a7d
JM		 1546
1547*am33
1548
c906108c
SS		 1549{
1550 /* OP_FAC00000 (); */
1551 PC = cia;
1552 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_D0 + DN0);
1553}
1554
1555
1556// 1111 1100 1100 00Dn imm32...; add imm32,Dn
15578.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add
1558"add"
1559*mn10300
c2d11a7d
JM		 1560
1561*am33
1562
c906108c
SS		 1563{
1564 /* OP_FCC00000 (); */
1565 PC = cia;
1566 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1567}
1568
1569
1570// 0010 00An imm8....; add imm8,An (imm8 is sign-extended)
15714.0x2,00,2.AN0+8.IMM8:S1a:::add
1572"add"
1573*mn10300
c2d11a7d
JM		 1574
1575*am33
1576
c906108c
SS		 1577{
1578 /* OP_2000 (); */
1579 PC = cia;
1580 genericAdd(EXTEND8(IMM8), REG_A0 + AN0);
1581}
1582
1583
1584// 1111 1010 1101 00An imm16...; add imm16,An (imm16 is sign-extended.)
15858.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add
1586"add"
1587*mn10300
c2d11a7d
JM		 1588
1589*am33
1590
c906108c
SS		 1591{
1592 /* OP_FAD00000 (); */
1593 PC = cia;
1594 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_A0 + AN0);
1595}
1596
1597
1598// 1111 1100 1101 00An imm32...; add imm32,An
15998.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add
1600"add"
1601*mn10300
c2d11a7d
JM		 1602
1603*am33
1604
c906108c
SS		 1605{
1606 /* OP_FCD00000 (); */
1607 PC = cia;
1608 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1609}
1610
1611
1612// 1111 1000 1111 1110 imm8....; add imm8,SP (imm8 is sign-extended.)
16138.0xf8+8.0xfe+8.IMM8:D1:::add
1614"add"
1615*mn10300
c2d11a7d
JM		 1616
1617*am33
1618
c906108c
SS		 1619{
1620 /* OP_F8FE00 (); */
24a39d88 1621 unsigned32 imm;
c906108c
SS		 1622
1623 /* Note: no PSW changes. */
1624 PC = cia;
1625 imm = EXTEND8 (IMM8);
1626 State.regs[REG_SP] += imm;
1627}
1628
1629
1630// 1111 1010 1111 1110 imm16...; add imm16,SP (imm16 is sign-extended.)
16318.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add
1632"add"
1633*mn10300
c2d11a7d
JM		 1634
1635*am33
1636
c906108c
SS		 1637{
1638 /* OP_FAFE0000 (); */
24a39d88 1639 unsigned32 imm;
c906108c
SS		 1640
1641 /* Note: no PSW changes. */
1642 PC = cia;
1643 imm = EXTEND16 (FETCH16(IMM16A, IMM16B));
1644 State.regs[REG_SP] += imm;
1645}
1646
1647
1648// 1111 1100 1111 1110 imm32...; add imm32,SP
16498.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add
1650"add"
1651*mn10300
c2d11a7d
JM		 1652
1653*am33
1654
c906108c
SS		 1655{
1656 /* OP_FCFE0000 (); */
24a39d88 1657 unsigned32 imm;
c906108c
SS		 1658
1659 /* Note: no PSW changes. */
1660 PC = cia;
1661 imm = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
1662 State.regs[REG_SP] += imm;
1663}
1664
1665
1666// 1111 0001 0100 DmDn; addc Dm,Dn
16678.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc
1668"addc"
1669*mn10300
c2d11a7d
JM		 1670
1671*am33
1672
c906108c
SS		 1673{
1674 /* OP_F140 (); */
1675 int z, c, n, v;
24a39d88 1676 unsigned32 reg1, reg2, sum;
c906108c
SS		 1677
1678 PC = cia;
1679 reg1 = State.regs[REG_D0 + DM1];
1680 reg2 = State.regs[REG_D0 + DN0];
1681 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
1682 State.regs[REG_D0 + DN0] = sum;
1683
1684 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1685 n = (sum & 0x80000000);
1686 c = (sum < reg1) || (sum < reg2);
1687 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1688 && (reg2 & 0x80000000) != (sum & 0x80000000));
1689
1690 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1691 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1692 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1693}
1694
1695
1696// 1111 0001 0000 DmDn; sub Dm,Dn
16978.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub
1698"sub"
1699*mn10300
c2d11a7d
JM		 1700
1701*am33
1702
c906108c
SS		 1703{
1704 /* OP_F100 (); */
1705 PC = cia;
1706 genericSub(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1707}
1708
1709// 1111 0001 0010 DmAn; sub DmAn
17108.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub
1711"sub"
1712*mn10300
c2d11a7d
JM		 1713
1714*am33
1715
c906108c
SS		 1716{
1717 /* OP_F120 (); */
1718 PC = cia;
1719 genericSub(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1720}
1721
1722
1723// 1111 0001 0001 AmDn; sub AmDn
17248.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub
1725"sub"
1726*mn10300
c2d11a7d
JM		 1727
1728*am33
1729
c906108c
SS		 1730{
1731 /* OP_F110 (); */
1732 PC = cia;
1733 genericSub(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1734}
1735
1736
1737// 1111 0001 0011 AmAn; sub Am,An
17388.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub
1739"sub"
1740*mn10300
c2d11a7d
JM		 1741
1742*am33
1743
c906108c
SS		 1744{
1745 /* OP_F130 (); */
1746 PC = cia;
1747 genericSub(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1748}
1749
1750
1751// 1111 1100 1100 01Dn imm32...; sub imm32,Dn
17528.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub
1753"sub"
1754*mn10300
c2d11a7d
JM		 1755
1756*am33
1757
c906108c
SS		 1758{
1759 /* OP_FCC40000 (); */
1760 PC = cia;
1761 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1762}
1763
1764
1765// 1111 1100 1101 01An imm32...; sub imm32,An
17668.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub
1767"sub"
1768*mn10300
c2d11a7d
JM		 1769
1770*am33
1771
c906108c
SS		 1772{
1773 /* OP_FCD40000 (); */
1774 PC = cia;
1775 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1776}
1777
1778
1779// 1111 0001 1000 DmDn; subc Dm,Dn
17808.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc
1781"subc"
1782*mn10300
c2d11a7d
JM		 1783
1784*am33
1785
c906108c
SS		 1786{
1787 /* OP_F180 (); */
1788 int z, c, n, v;
24a39d88 1789 unsigned32 reg1, reg2, difference;
c906108c
SS		 1790
1791 PC = cia;
1792 reg1 = State.regs[REG_D0 + DM1];
1793 reg2 = State.regs[REG_D0 + DN0];
1794 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
1795 State.regs[REG_D0 + DN0] = difference;
1796
1797 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1798 n = (difference & 0x80000000);
1799 c = (reg1 > reg2);
1800 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1801 && (reg2 & 0x80000000) != (difference & 0x80000000));
1802
1803 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1804 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1805 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1806}
1807
1808
1809// 1111 0010 0100 DmDn; mul Dm,Dn
18108.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul
1811"mul"
1812*mn10300
c2d11a7d
JM		 1813
1814*am33
1815
c906108c
SS		 1816{
1817 /* OP_F240 (); */
24a39d88 1818 unsigned64 temp;
c906108c
SS		 1819 int n, z;
1820
1821 PC = cia;
1822 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
1823 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
1824 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1825 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1826 z = (State.regs[REG_D0 + DN0] == 0);
1827 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1828 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1829 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1830}
1831
1832
1833// 1111 0010 0101 DmDn; mulu Dm,Dn
18348.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu
1835"mulu"
1836*mn10300
c2d11a7d
JM		 1837
1838*am33
1839
c906108c
SS		 1840{
1841 /* OP_F250 (); */
24a39d88 1842 unsigned64 temp;
c906108c
SS		 1843 int n, z;
1844
1845 PC = cia;
1846 temp = ((unsigned64)State.regs[REG_D0 + DN0]
1847 * (unsigned64)State.regs[REG_D0 + DM1]);
1848 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1849 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1850 z = (State.regs[REG_D0 + DN0] == 0);
1851 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1852 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1853 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1854}
1855
1856
1857// 1111 0010 0110 DmDn; div Dm,Dn
18588.0xf2+4.0x6,2.DM1,2.DN0:D0:::div
1859"div"
1860*mn10300
c2d11a7d
JM		 1861
1862*am33
1863
c906108c
SS		 1864{
1865 /* OP_F260 (); */
1866 signed64 temp;
1867 signed32 denom;
1868 int n, z, v;
1869
1870 PC = cia;
1871 denom = (signed32)State.regs[REG_D0 + DM1];
1872
1873 temp = State.regs[REG_MDR];
1874 temp <<= 32;
1875 temp |= State.regs[REG_D0 + DN0];
1876 if ( !(v = (0 == denom)) )
1877 {
1878 State.regs[REG_MDR] = temp % (signed32)State.regs[REG_D0 + DM1];
1879 temp /= (signed32)State.regs[REG_D0 + DM1];
1880 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1881 }
1882 else
1883 {
1884 State.regs[REG_MDR] = temp;
1885 State.regs[REG_D0 + DN0] = 0xff;
1886 }
1887 z = (State.regs[REG_D0 + DN0] == 0);
1888 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1889 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1890 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
1891}
1892
1893
1894// 1111 0010 0111 DmDn; divu Dm,Dn
18958.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu
1896"divu"
1897*mn10300
c2d11a7d
JM		 1898
1899*am33
1900
c906108c
SS		 1901{
1902 /* OP_F270 (); */
1903 unsigned64 temp;
1904 unsigned32 denom;
1905 int n, z, v;
1906
1907 PC = cia;
1908 denom = (unsigned32)State.regs[REG_D0 + DM1];
1909 temp = State.regs[REG_MDR];
1910 temp <<= 32;
1911 temp |= State.regs[REG_D0 + DN0];
1912 if ( !(v = (0 == denom)) )
1913 {
1914 State.regs[REG_MDR] = temp % State.regs[REG_D0 + DM1];
1915 temp /= State.regs[REG_D0 + DM1];
1916 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1917 }
1918 else
1919 {
1920 State.regs[REG_MDR] = temp;
1921 State.regs[REG_D0 + DN0] = 0xff;
1922 }
1923 z = (State.regs[REG_D0 + DN0] == 0);
1924 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1925 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1926 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
1927}
1928
1929
1930// 0100 Dn00; inc Dn
19314.0x4,2.DN1,00:S0:::inc
1932"inc"
1933*mn10300
c2d11a7d
JM		 1934
1935*am33
1936
c906108c
SS		 1937{
1938 /* OP_40 (); */
24a39d88 1939 unsigned32 imm;
c906108c
SS		 1940
1941 PC = cia;
1942 imm = 1;
1943 genericAdd(imm, REG_D0 + DN1);
1944}
1945
1946
1947// 0100 An01
19484.0x4,2.AN1,01:S0a:::inc
1949"inc"
1950*mn10300
c2d11a7d
JM		 1951
1952*am33
1953
c906108c
SS		 1954{
1955 /* OP_41 (); */
1956 PC = cia;
1957 State.regs[REG_A0 + AN1] += 1;
1958}
1959
1960
1961// 0101 00An; inc4 An
19624.0x5,00,2.AN0:S0:::inc4
1963"inc4"
1964*mn10300
c2d11a7d
JM		 1965
1966*am33
1967
c906108c
SS		 1968{
1969 /* OP_50 (); */
1970 PC = cia;
1971 State.regs[REG_A0 + AN0] += 4;
1972}
1973
1974
1975// 1010 DnDn imm8....; cmp imm8,Dn (imm8 is sign-extended.)
19764.0xa,2.DM1,2.DN0=DM1+IMM8:S0i:::cmp
1977"cmp"
1978*mn10300
c2d11a7d
JM		 1979
1980*am33
1981
c906108c
SS		 1982{
1983 PC = cia;
1984 /* OP_A000 (); */
1985 genericCmp(EXTEND8 (IMM8), State.regs[REG_D0 + DN0]);
1986}
1987
1988
1989// 1010 DmDn; cmp Dm,Dn (Dm != Dn, see above when Dm == Dn)
19904.0xa,2.DM1,2.DN0!DM1:S0:::cmp
1991"cmp"
1992*mn10300
c2d11a7d
JM		 1993
1994*am33
1995
c906108c
SS		 1996{
1997 PC = cia;
1998 /* OP_A0 (); */
1999 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_D0 + DN0]);
2000}
2001
2002
2003// 1111 0001 1010 DmAn; cmp Dm,An
20048.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp
2005"cmp"
2006*mn10300
c2d11a7d
JM		 2007
2008*am33
2009
c906108c
SS		 2010{
2011 /* OP_F1A0 (); */
2012 PC = cia;
2013 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_A0 + AN0]);
2014}
2015
2016
2017// 1111 0001 1001 AmDn; cmp Am,Dn
20188.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp
2019"cmp"
2020*mn10300
c2d11a7d
JM		 2021
2022*am33
2023
c906108c
SS		 2024{
2025 /* OP_F190 (); */
2026 PC = cia;
2027 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_D0 + DN0]);
2028}
2029
2030
2031// 1011 AnAn imm8....; cmp imm8,An (imm8 is zero-extended.)
20324.0xb,2.AM1,2.AN0=AM1+IMM8:S0ai:::cmp
2033"cmp"
2034*mn10300
c2d11a7d
JM		 2035
2036*am33
2037
c906108c
SS		 2038{
2039 PC = cia;
2040 /* OP_B000 (); */
2041 genericCmp(IMM8,
2042 State.regs[REG_A0 + AN0]);
2043}
2044
2045
2046// 1011 AmAn; cmp Am,An (Dm != Dn, see above when Dm == Dn)
20474.0xb,2.AM1,2.AN0!AM1:S0a:::cmp
2048"cmp"
2049*mn10300
c2d11a7d
JM		 2050
2051*am33
2052
c906108c
SS		 2053{
2054 PC = cia;
2055 /* OP_B0 (); */
2056 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_A0 + AN0]);
2057}
2058
2059
2060// 1111 1010 1100 10Dn imm16...; cmp imm16,Dn (imm16 is sign-extended.)
20618.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp
2062"cmp"
2063*mn10300
c2d11a7d
JM		 2064
2065*am33
2066
c906108c
SS		 2067{
2068 /* OP_FAC80000 (); */
2069 PC = cia;
2070 genericCmp(EXTEND16(FETCH16(IMM16A, IMM16B)),
2071 State.regs[REG_D0 + DN0]);
2072}
2073
2074
2075// 1111 1100 1100 10Dn imm32...; cmp imm32,Dn
20768.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp
2077"cmp"
2078*mn10300
c2d11a7d
JM		 2079
2080*am33
2081
c906108c
SS		 2082{
2083 /* OP_FCC80000 (); */
2084 PC = cia;
2085 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2086 State.regs[REG_D0 + DN0]);
2087}
2088
2089
2090// 1111 1010 1101 10An imm16...; cmp imm16,An (imm16 is zero-extended.)
20918.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp
2092"cmp"
2093*mn10300
c2d11a7d
JM		 2094
2095*am33
2096
c906108c
SS		 2097{
2098 /* OP_FAD80000 (); */
2099 PC = cia;
2100 genericCmp(FETCH16(IMM16A, IMM16B),
2101 State.regs[REG_A0 + AN0]);
2102}
2103
2104
2105// 1111 1100 1101 10An imm32...; cmp imm32,An
21068.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp
2107"cmp"
2108*mn10300
c2d11a7d
JM		 2109
2110*am33
2111
c906108c
SS		 2112{
2113 /* OP_FCD80000 (); */
2114 PC = cia;
2115 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2116 State.regs[REG_A0 + AN0]);
2117}
2118
2119
2120// 1111 0010 0000 DmDn; and Dm,Dn
21218.0xf2+4.0x0,2.DM1,2.DN0:D0:::and
2122"and"
2123*mn10300
c2d11a7d
JM		 2124
2125*am33
2126
c906108c
SS		 2127{
2128 /* OP_F200 (); */
2129 int n, z;
2130
2131 PC = cia;
2132 State.regs[REG_D0 + DN0] &= State.regs[REG_D0 + DM1];
2133 z = (State.regs[REG_D0 + DN0] == 0);
2134 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2135 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2136 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2137}
2138
2139
2140// 1111 1000 1110 00Dn imm8....; and imm8,Dn (imm8 is zero-extended.)
21418.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and
2142"and"
2143*mn10300
c2d11a7d
JM		 2144
2145*am33
2146
c906108c
SS		 2147{
2148 /* OP_F8E000 (); */
2149 int n, z;
2150
2151 PC = cia;
2152 State.regs[REG_D0 + DN0] &= IMM8;
2153 z = (State.regs[REG_D0 + DN0] == 0);
2154 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2155 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2156 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2157}
2158
2159
2160// 1111 1010 1110 00Dn imm16...; and imm16,Dn (imm16 is zero-extended.)
21618.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and
2162"and"
2163*mn10300
c2d11a7d
JM		 2164
2165*am33
2166
c906108c
SS		 2167{
2168 /* OP_FAE00000 (); */
2169 int n, z;
2170
2171 PC = cia;
2172 State.regs[REG_D0 + DN0] &= FETCH16(IMM16A, IMM16B);
2173 z = (State.regs[REG_D0 + DN0] == 0);
2174 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2175 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2176 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2177}
2178
2179
2180// 1111 1100 1110 00Dn imm32...; and imm32,Dn
21818.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and
2182"and"
2183*mn10300
c2d11a7d
JM		 2184
2185*am33
2186
c906108c
SS		 2187{
2188 /* OP_FCE00000 (); */
2189 int n, z;
2190
2191 PC = cia;
2192 State.regs[REG_D0 + DN0]
2193 &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
2194 z = (State.regs[REG_D0 + DN0] == 0);
2195 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2196 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2197 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2198}
2199
2200
2201// 1111 1010 1111 1100 imm16...; and imm16,PSW (imm16 is zero-extended.)
22028.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and
2203"and"
2204*mn10300
c2d11a7d
JM		 2205
2206*am33
2207
c906108c
SS		 2208{
2209 /* OP_FAFC0000 (); */
2210 PC = cia;
2211 PSW &= FETCH16(IMM16A, IMM16B);
2212}
2213
2214
2215
2216// 1111 0010 0001 DmDn; or DmDn
22178.0xf2+4.0x1,2.DM1,2.DN0:D0:::or
2218"or"
2219*mn10300
c2d11a7d
JM		 2220
2221*am33
2222
c906108c
SS		 2223{
2224 /* OP_F210 (); */
2225 PC = cia;
2226 genericOr(State.regs[REG_D0 + DM1], REG_D0 + DN0);
2227}
2228
2229
2230// 1111 1000 1110 01Dn imm8....; or imm8,Dn (imm8 is zero-extended.)n
22318.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or
2232"or"
2233*mn10300
c2d11a7d
JM		 2234
2235*am33
2236
c906108c
SS		 2237{
2238 /* OP_F8E400 (); */
2239 PC = cia;
2240 genericOr(IMM8, REG_D0 + DN0);
2241}
2242
2243
2244// 1111 1010 1110 01Dn imm16...; or imm16,DN (imm16 is zero-extended.)
22458.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or
2246"or"
2247*mn10300
c2d11a7d
JM		 2248
2249*am33
2250
c906108c
SS		 2251{
2252 /* OP_FAE40000 (); */
2253 PC = cia;
2254 genericOr(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
2255}
2256
2257
2258// 1111 1100 1110 01Dn imm32...; or imm32,Dn
22598.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or
2260"or"
2261*mn10300
c2d11a7d
JM		 2262
2263*am33
2264
c906108c
SS		 2265{
2266 /* OP_FCE40000 (); */
2267 PC = cia;
2268 genericOr(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2269}
2270
2271
2272// 1111 1010 1111 1101 imm16...; or imm16,PSW (imm16 is zero-extended.)
22738.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or
2274"or"
2275*mn10300
c2d11a7d
JM		 2276
2277*am33
2278
c906108c
SS		 2279{
2280 /* OP_FAFD0000 (); */
2281 PC = cia;
2282 PSW |= FETCH16(IMM16A, IMM16B);
2283}
2284
2285
2286// 1111 0010 0010 DmDn; xor Dm,Dn
22878.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor
2288"xor"
2289*mn10300
c2d11a7d
JM		 2290
2291*am33
2292
c906108c
SS		 2293{
2294 /* OP_F220 (); */
2295 PC = cia;
2296 genericXor(State.regs[REG_D0 + DM1], REG_D0 + DN0);
2297}
2298
2299
2300// 1111 1010 1110 10Dn imm16...; xor imm16,Dn (imm16 is zero-extended.)
23018.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor
2302"xor"
2303*mn10300
c2d11a7d
JM		 2304
2305*am33
2306
c906108c
SS		 2307{
2308 /* OP_FAE80000 (); */
2309 PC = cia;
2310 genericXor(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
2311}
2312
2313
2314// 1111 1100 1110 10Dn imm32...; xor imm32,Dn
23158.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor
2316"xor"
2317*mn10300
c2d11a7d
JM		 2318
2319*am33
2320
c906108c
SS		 2321{
2322 /* OP_FCE80000 (); */
2323 PC = cia;
2324 genericXor(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2325}
2326
2327
2328// 1111 0010 0011 00Dn; not Dn
23298.0xf2+4.0x3,00,2.DN0:D0:::not
2330"not"
2331*mn10300
c2d11a7d
JM		 2332
2333*am33
2334
c906108c
SS		 2335{
2336 /* OP_F230 (); */
2337 int n, z;
2338
2339 PC = cia;
2340 State.regs[REG_D0 + DN0] = ~State.regs[REG_D0 + DN0];
2341 z = (State.regs[REG_D0 + DN0] == 0);
2342 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2343 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2344 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2345}
2346
2347
2348// 1111 1000 1110 11Dn imm8....; btst imm8,Dn (imm8 is zero-extended.)
23498.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst
2350"btst"
2351*mn10300
c2d11a7d
JM		 2352
2353*am33
2354
c906108c
SS		 2355{
2356 /* OP_F8EC00 (); */
2357 PC = cia;
2358 genericBtst(IMM8, State.regs[REG_D0 + DN0]);
2359}
2360
2361
2362// 1111 1010 1110 11Dn imm16.....; btst imm16,Dn (imm16 is zero-extended.)
23638.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst
2364"btst"
2365*mn10300
c2d11a7d
JM		 2366
2367*am33
2368
c906108c
SS		 2369{
2370 /* OP_FAEC0000 (); */
2371 PC = cia;
2372 genericBtst(FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DN0]);
2373}
2374
2375
2376// 1111 1100 1110 11Dn imm32...; btst imm32,Dn
23778.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst
2378"btst"
2379*mn10300
c2d11a7d
JM		 2380
2381*am33
2382
c906108c
SS		 2383{
2384 /* OP_FCEC0000 (); */
2385 PC = cia;
2386 genericBtst(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2387 State.regs[REG_D0 + DN0]);
2388}
2389
2390
2391// 1111 1110 0000 0010 abs32... imm8....; btst imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
23928.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst
2393"btst"
2394*mn10300
c2d11a7d
JM		 2395
2396*am33
2397
c906108c
SS		 2398{
2399 /* OP_FE020000 (); */
2400 PC = cia;
2401 genericBtst(IMM8,
2402 load_byte(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
2403}
2404
2405
2406// 1111 1010 1111 10An d8...... imm8....;
2407// btst imm8,(d8,An) (d8 is sign-extended,imm8 is zero-extended., processing unit: byte)
24088.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst
2409"btst"
2410*mn10300
c2d11a7d
JM		 2411
2412*am33
2413
c906108c
SS		 2414{
2415 /* OP_FAF80000 (); */
2416 PC = cia;
2417 genericBtst(IMM8,
2418 load_byte(State.regs[REG_A0 + AN0] + EXTEND8(D8)));
2419}
2420
2421
2422// 1111 0000 1000 DmAn; bset Dm,(An) (Processing unit byte)
24238.0xf0+4.8,2.DM1,2.AN0:D0:::bset
2424"bset"
2425*mn10300
c2d11a7d
JM		 2426
2427*am33
2428
c906108c
SS		 2429{
2430 /* OP_F080 (); */
24a39d88 2431 unsigned32 temp;
c906108c
SS		 2432 int z;
2433
2434 PC = cia;
2435 temp = load_byte (State.regs[REG_A0 + AN0]);
2436 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2437 temp |= State.regs[REG_D0 + DM1];
2438 store_byte (State.regs[REG_A0 + AN0], temp);
2439 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2440 PSW |= (z ? PSW_Z : 0);
2441}
2442
2443
2444// 1111 1110 0000 0000 abs32... imm8....;
2445// bset imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
24468.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset
2447"bset"
2448*mn10300
c2d11a7d
JM		 2449
2450*am33
2451
c906108c
SS		 2452{
2453 /* OP_FE000000 (); */
24a39d88 2454 unsigned32 temp;
c906108c
SS		 2455 int z;
2456
2457 PC = cia;
2458 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2459 z = (temp & IMM8) == 0;
2460 temp |= IMM8;
2461 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2462 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2463 PSW |= (z ? PSW_Z : 0);
2464}
2465
2466
2467// 1111 1010 1111 00AnAn d8...... imm8....;
2468// bset imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
24698.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset
2470"bset"
2471*mn10300
c2d11a7d
JM		 2472
2473*am33
2474
c906108c
SS		 2475{
2476 /* OP_FAF00000 (); */
24a39d88 2477 unsigned32 temp;
c906108c
SS		 2478 int z;
2479
2480 PC = cia;
2481 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2482 z = (temp & (IMM8)) == 0;
2483 temp |= (IMM8);
2484 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2485 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2486 PSW |= (z ? PSW_Z : 0);
2487}
2488
2489
2490// 1111 0000 1001 DmAn; bclr Dm,(An) (Processing unit byte)
24918.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr
2492"bclr"
2493*mn10300
c2d11a7d
JM		 2494
2495*am33
2496
c906108c
SS		 2497{
2498 /* OP_F090 (); */
24a39d88 2499 unsigned32 temp;
c906108c
SS		 2500 int z;
2501
2502 PC = cia;
2503 temp = load_byte (State.regs[REG_A0 + AN0]);
2504 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2505 temp = temp & ~State.regs[REG_D0 + DM1];
2506 store_byte (State.regs[REG_A0 + AN0], temp);
2507 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2508 PSW |= (z ? PSW_Z : 0);
2509}
2510
2511
2512// 1111 1110 0000 0001 abs32... imm8....;
2513// bclr imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
25148.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr
2515"bclr"
2516*mn10300
c2d11a7d
JM		 2517
2518*am33
2519
c906108c
SS		 2520{
2521 /* OP_FE010000 (); */
24a39d88 2522 unsigned32 temp;
c906108c
SS		 2523 int z;
2524
2525 PC = cia;
2526 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2527 z = (temp & IMM8) == 0;
2528 temp = temp & ~(IMM8);
2529 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2530 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2531 PSW |= (z ? PSW_Z : 0);
2532}
2533
2534
2535// 1111 1010 1111 01An d8...... imm8....;
2536// bclr imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
25378.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr
2538"bclr"
2539*mn10300
c2d11a7d
JM		 2540
2541*am33
2542
c906108c
SS		 2543{
2544 /* OP_FAF40000 (); */
24a39d88 2545 unsigned32 temp;
c906108c
SS		 2546 int z;
2547
2548 PC = cia;
2549 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2550 z = (temp & (IMM8)) == 0;
2551 temp = temp & ~(IMM8);
2552 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2553 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2554 PSW |= (z ? PSW_Z : 0);
2555}
2556
2557
2558// 1111 0010 1011 DmDn; asr Dm,Dn
25598.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr
2560"asr"
2561*mn10300
c2d11a7d
JM		 2562
2563*am33
2564
c906108c
SS		 2565{
2566 /* OP_F2B0 (); */
24a39d88 2567 signed32 temp;
c906108c
SS		 2568 int z, n, c;
2569
2570 PC = cia;
2571 temp = State.regs[REG_D0 + DN0];
2572 c = temp & 1;
2573 temp >>= State.regs[REG_D0 + DM1];
2574 State.regs[REG_D0 + DN0] = temp;
2575 z = (State.regs[REG_D0 + DN0] == 0);
2576 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2577 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2578 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2579}
2580
2581
2582// 1111 1000 1100 10Dn imm8...; asr imm8,Dn (imm8 is zero-extended.)
25838.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr
2584"asr"
2585*mn10300
c2d11a7d
JM		 2586
2587*am33
2588
c906108c
SS		 2589{
2590 /* OP_F8C800 (); */
24a39d88 2591 signed32 temp;
c906108c
SS		 2592 int z, n, c;
2593
2594 PC = cia;
2595 temp = State.regs[REG_D0 + DN0];
2596 c = temp & 1;
2597 temp >>= IMM8;
2598 State.regs[REG_D0 + DN0] = temp;
2599 z = (State.regs[REG_D0 + DN0] == 0);
2600 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2601 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2602 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2603}
2604
2605
2606// 1111 0010 1010 DmDn; lsr Dm,Dn
26078.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr
2608"lsr"
2609*mn10300
c2d11a7d
JM		 2610
2611*am33
2612
c906108c
SS		 2613{
2614 /* OP_F2A0 (); */
2615 int z, n, c;
2616
2617 PC = cia;
2618 c = State.regs[REG_D0 + DN0] & 1;
2619 State.regs[REG_D0 + DN0]
2620 >>= State.regs[REG_D0 + DM1];
2621 z = (State.regs[REG_D0 + DN0] == 0);
2622 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2623 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2624 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2625}
2626
2627
2628// 1111 1000 1100 01Dn imm8...; lsr imm8,Dn (imm8 is zero-extended.)
26298.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr
2630"lsr"
2631*mn10300
c2d11a7d
JM		 2632
2633*am33
2634
c906108c
SS		 2635{
2636 /* OP_F8C400 (); */
2637 int z, n, c;
2638
2639 PC = cia;
2640 c = State.regs[REG_D0 + DN0] & 1;
2641 State.regs[REG_D0 + DN0] >>= IMM8;
2642 z = (State.regs[REG_D0 + DN0] == 0);
2643 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2644 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2645 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2646}
2647
2648
2649// 1111 0010 1001 DmDn; asl Dm,Dn
26508.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl
2651"asl"
2652*mn10300
c2d11a7d
JM		 2653
2654*am33
2655
c906108c
SS		 2656{
2657 /* OP_F290 (); */
2658 int n, z;
2659
2660 PC = cia;
2661 State.regs[REG_D0 + DN0]
2662 <<= State.regs[REG_D0 + DM1];
2663 z = (State.regs[REG_D0 + DN0] == 0);
2664 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2665 PSW &= ~(PSW_Z | PSW_N);
2666 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2667}
2668
2669
2670// 1111 1000 1100 00Dn imm8...; asl imm8,Dn (imm8 is zero-extended.)
26718.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl
2672"asl"
2673*mn10300
c2d11a7d
JM		 2674
2675*am33
2676
c906108c
SS		 2677{
2678 /* OP_F8C000 (); */
2679 int n, z;
2680
2681 PC = cia;
2682 State.regs[REG_D0 + DN0] <<= IMM8;
2683 z = (State.regs[REG_D0 + DN0] == 0);
2684 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2685 PSW &= ~(PSW_Z | PSW_N);
2686 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2687}
2688
2689
2690// 0101 01Dn; als2 Dn
26914.0x5,01,2.DN0:S0:::asl2
2692"asl2"
2693*mn10300
c2d11a7d
JM		 2694
2695*am33
2696
c906108c
SS		 2697{
2698 /* OP_54 (); */
2699 int n, z;
2700 PC = cia;
2701
2702 State.regs[REG_D0 + DN0] <<= 2;
2703 z = (State.regs[REG_D0 + DN0] == 0);
2704 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2705 PSW &= ~(PSW_Z | PSW_N);
2706 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2707}
2708
2709
2710// 1111 0010 1000 01Dn; ror Dn
27118.0xf2+4.0x8,01,2.DN0:D0:::ror
2712"ror"
2713*mn10300
c2d11a7d
JM		 2714
2715*am33
2716
c906108c
SS		 2717{
2718 /* OP_F284 (); */
24a39d88 2719 unsigned32 value;
c906108c
SS		 2720 int c,n,z;
2721
2722 PC = cia;
2723 value = State.regs[REG_D0 + DN0];
2724 c = (value & 0x1);
2725
2726 value >>= 1;
2727 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2728 State.regs[REG_D0 + DN0] = value;
2729 z = (value == 0);
2730 n = (value & 0x80000000) != 0;
2731 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2732 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2733}
2734
2735
2736// 1111 0010 1000 00Dn; rol Dn
27378.0xf2+4.0x8,00,2.DN0:D0:::rol
2738"rol"
2739*mn10300
c2d11a7d
JM		 2740
2741*am33
2742
c906108c
SS		 2743{
2744 /* OP_F280 (); */
24a39d88 2745 unsigned32 value;
c906108c
SS		 2746 int c,n,z;
2747
2748 PC = cia;
2749 value = State.regs[REG_D0 + DN0];
2750 c = (value & 0x80000000) ? 1 : 0;
2751
2752 value <<= 1;
2753 value |= ((PSW & PSW_C) != 0);
2754 State.regs[REG_D0 + DN0] = value;
2755 z = (value == 0);
2756 n = (value & 0x80000000) != 0;
2757 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2758 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2759}
2760
2761
2762// 1100 1000 d8......; beq (d8,PC) (d8 is sign-extended)
27638.0xc8+8.D8:S1:::beq
2764"beq"
2765*mn10300
c2d11a7d
JM		 2766
2767*am33
2768
c906108c
SS		 2769{
2770 /* OP_C800 (); */
2771 PC = cia;
2772 if ((PSW & PSW_Z))
2773 {
2774 State.regs[REG_PC] += EXTEND8 (D8);
2775 nia = PC;
2776 }
2777}
2778
2779
2780// 1100 1001 d8......; bne (d8,PC) (d8 is sign-extended)
27818.0xc9+8.D8:S1:::bne
2782"bne"
2783*mn10300
c2d11a7d
JM		 2784
2785*am33
2786
c906108c
SS		 2787{
2788 /* OP_C900 (); */
2789 PC = cia;
2790 if (!(PSW & PSW_Z))
2791 {
2792 State.regs[REG_PC] += EXTEND8 (D8);
2793 nia = PC;
2794 }
2795}
2796
2797
2798// 1100 0001 d8......; bgt (d8,PC) (d8 is sign-extended)
27998.0xc1+8.D8:S1:::bgt
2800"bgt"
2801*mn10300
c2d11a7d
JM		 2802
2803*am33
2804
c906108c
SS		 2805{
2806 /* OP_C100 (); */
2807 PC = cia;
2808 if (!((PSW & PSW_Z)
2809 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2810 {
2811 State.regs[REG_PC] += EXTEND8 (D8);
2812 nia = PC;
2813 }
2814}
2815
2816
2817// 1100 0010 d8......; bge (d8,PC) (d8 is sign-extended)
28188.0xc2+8.D8:S1:::bge
2819"bge"
2820*mn10300
c2d11a7d
JM		 2821
2822*am33
2823
c906108c
SS		 2824{
2825 /* OP_C200 (); */
2826 PC = cia;
2827 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2828 {
2829 State.regs[REG_PC] += EXTEND8 (D8);
2830 nia = PC;
2831 }
2832}
2833
2834
2835// 1100 0011 d8......; ble (d8,PC) (d8 is sign-extended)
28368.0xc3+8.D8:S1:::ble
2837"ble"
2838*mn10300
c2d11a7d
JM		 2839
2840*am33
2841
c906108c
SS		 2842{
2843 /* OP_C300 (); */
2844 PC = cia;
2845 if ((PSW & PSW_Z)
2846 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2847 {
2848 State.regs[REG_PC] += EXTEND8 (D8);
2849 nia = PC;
2850 }
2851}
2852
2853
2854// 1100 0000 d8......; blt (d8,PC) (d8 is sign-extended)
28558.0xc0+8.D8:S1:::blt
2856"blt"
2857*mn10300
c2d11a7d
JM		 2858
2859*am33
2860
c906108c
SS		 2861{
2862 /* OP_C000 (); */
2863 PC = cia;
2864 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2865 {
2866 State.regs[REG_PC] += EXTEND8 (D8);
2867 nia = PC;
2868 }
2869}
2870
2871
2872// 1100 0101 d8......; bhi (d8,PC) (d8 is sign-extended)
28738.0xc5+8.D8:S1:::bhi
2874"bhi"
2875*mn10300
c2d11a7d
JM		 2876
2877*am33
2878
c906108c
SS		 2879{
2880 /* OP_C500 (); */
2881 PC = cia;
2882 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2883 {
2884 State.regs[REG_PC] += EXTEND8 (D8);
2885 nia = PC;
2886 }
2887}
2888
2889
2890// 1100 0110 d8......; bcc (d8,PC) (d8 is sign-extended)
28918.0xc6+8.D8:S1:::bcc
2892"bcc"
2893*mn10300
c2d11a7d
JM		 2894
2895*am33
2896
c906108c
SS		 2897{
2898 /* OP_C600 (); */
2899 PC = cia;
2900 if (!(PSW & PSW_C))
2901 {
2902 State.regs[REG_PC] += EXTEND8 (D8);
2903 nia = PC;
2904 }
2905}
2906
2907
2908// 1100 0101 d8......; bls (d8,PC) (d8 is sign-extended)
29098.0xc7+8.D8:S1:::bls
2910"bls"
2911*mn10300
c2d11a7d
JM		 2912
2913*am33
2914
c906108c
SS		 2915{
2916 /* OP_C700 (); */
2917 PC = cia;
2918 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2919 {
2920 State.regs[REG_PC] += EXTEND8 (D8);
2921 nia = PC;
2922 }
2923}
2924
2925
2926// 1100 0100 d8......; bcs (d8,PC) (d8 is sign-extended)
29278.0xc4+8.D8:S1:::bcs
2928"bcs"
2929*mn10300
c2d11a7d
JM		 2930
2931*am33
2932
c906108c
SS		 2933{
2934 /* OP_C400 (); */
2935 PC = cia;
2936 if (PSW & PSW_C)
2937 {
2938 State.regs[REG_PC] += EXTEND8 (D8);
2939 nia = PC;
2940 }
2941}
2942
2943
2944// 1111 1000 1110 1000 d8......; bvc (d8,PC) (d8 is sign-extended)
29458.0xf8+8.0xe8+8.D8:D1:::bvc
2946"bvc"
2947*mn10300
c2d11a7d
JM		 2948
2949*am33
2950
c906108c
SS		 2951{
2952 /* OP_F8E800 (); */
2953 PC = cia;
2954 if (!(PSW & PSW_V))
2955 {
2956 State.regs[REG_PC] += EXTEND8 (D8);
2957 nia = PC;
2958 }
2959}
2960
2961
2962// 1111 1000 1110 1001 d8......; bvs (d8,PC) (d8 is sign-extended)
29638.0xf8+8.0xe9+8.D8:D1:::bvs
2964"bvs"
2965*mn10300
c2d11a7d
JM		 2966
2967*am33
2968
c906108c
SS		 2969{
2970 /* OP_F8E900 (); */
2971 PC = cia;
2972 if (PSW & PSW_V)
2973 {
2974 State.regs[REG_PC] += EXTEND8 (D8);
2975 nia = PC;
2976 }
2977}
2978
2979
2980// 1111 1000 1110 1010 d8......; bnc (d8,PC) (d8 is sign-extended)
29818.0xf8+8.0xea+8.D8:D1:::bnc
2982"bnc"
2983*mn10300
c2d11a7d
JM		 2984
2985*am33
2986
c906108c
SS		 2987{
2988 /* OP_F8EA00 (); */
2989 PC = cia;
2990 if (!(PSW & PSW_N))
2991 {
2992 State.regs[REG_PC] += EXTEND8 (D8);
2993 nia = PC;
2994 }
2995}
2996
2997
2998// 1111 1000 1110 1010 d8......; bns (d8,PC) (d8 is sign-extended)
29998.0xf8+8.0xeb+8.D8:D1:::bns
3000"bns"
3001*mn10300
c2d11a7d
JM		 3002
3003*am33
3004
c906108c
SS		 3005{
3006 /* OP_F8EB00 (); */
3007 PC = cia;
3008 if (PSW & PSW_N)
3009 {
3010 State.regs[REG_PC] += EXTEND8 (D8);
3011 nia = PC;
3012 }
3013}
3014
3015
3016// 1100 1010 d8......; bra (d8,PC) (d8 is sign-extended)
30178.0xca+8.D8:S1:::bra
3018"bra"
3019*mn10300
c2d11a7d
JM		 3020
3021*am33
3022
c906108c
SS		 3023{
3024 /* OP_CA00 (); */
3025 PC = cia;
3026 State.regs[REG_PC] += EXTEND8 (D8);
3027 nia = PC;
3028}
3029
3030
3031// 1101 1000; leq
30328.0xd8:S0:::leq
3033"leq"
3034*mn10300
c2d11a7d
JM		 3035
3036*am33
3037
c906108c
SS		 3038{
3039 /* OP_D8 (); */
3040 PC = cia;
3041 if (PSW & PSW_Z)
3042 {
3043 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3044 nia = PC;
3045 }
3046}
3047
3048
3049// 1101 1001; lne
30508.0xd9:S0:::lne
3051"lne"
3052*mn10300
c2d11a7d
JM		 3053
3054*am33
3055
c906108c
SS		 3056{
3057 /* OP_D9 (); */
3058 PC = cia;
3059 if (!(PSW & PSW_Z))
3060 {
3061 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3062 nia = PC;
3063 }
3064}
3065
3066
3067// 1101 0001; lgt
30688.0xd1:S0:::lgt
3069"lgt"
3070*mn10300
c2d11a7d
JM		 3071
3072*am33
3073
c906108c
SS		 3074{
3075 /* OP_D1 (); */
3076 PC = cia;
3077 if (!((PSW & PSW_Z)
3078 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
3079 {
3080 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3081 nia = PC;
3082 }
3083}
3084
3085
3086// 1101 0010; lge
30878.0xd2:S0:::lge
3088"lge"
3089*mn10300
c2d11a7d
JM		 3090
3091*am33
3092
c906108c
SS		 3093{
3094 /* OP_D2 (); */
3095 PC = cia;
3096 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
3097 {
3098 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3099 nia = PC;
3100 }
3101}
3102
3103
3104// 1101 0011; lle
31058.0xd3:S0:::lle
3106"lle"
3107*mn10300
c2d11a7d
JM		 3108
3109*am33
3110
c906108c
SS		 3111{
3112 /* OP_D3 (); */
3113 PC = cia;
3114 if ((PSW & PSW_Z)
3115 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
3116 {
3117 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3118 nia = PC;
3119 }
3120}
3121
3122
3123// 1101 0000; llt
31248.0xd0:S0:::llt
3125"llt"
3126*mn10300
c2d11a7d
JM		 3127
3128*am33
3129
c906108c
SS		 3130{
3131 /* OP_D0 (); */
3132 PC = cia;
3133 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
3134 {
3135 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3136 nia = PC;
3137 }
3138}
3139
3140
3141// 1101 0101; lhi
31428.0xd5:S0:::lhi
3143"lhi"
3144*mn10300
c2d11a7d
JM		 3145
3146*am33
3147
c906108c
SS		 3148{
3149 /* OP_D5 (); */
3150 PC = cia;
3151 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
3152 {
3153 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3154 nia = PC;
3155 }
3156}
3157
3158
3159// 1101 0110; lcc
31608.0xd6:S0:::lcc
3161"lcc"
3162*mn10300
c2d11a7d
JM		 3163
3164*am33
3165
c906108c
SS		 3166{
3167 /* OP_D6 (); */
3168 PC = cia;
3169 if (!(PSW & PSW_C))
3170 {
3171 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3172 nia = PC;
3173 }
3174}
3175
3176
3177// 1101 0111; lls
31788.0xd7:S0:::lls
3179"lls"
3180*mn10300
c2d11a7d
JM		 3181
3182*am33
3183
c906108c
SS		 3184{
3185 /* OP_D7 (); */
3186 PC = cia;
3187 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
3188 {
3189 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3190 nia = PC;
3191 }
3192}
3193
3194
3195// 1101 0100; lcs
31968.0xd4:S0:::lcs
3197"lcs"
3198*mn10300
c2d11a7d
JM		 3199
3200*am33
3201
c906108c
SS		 3202{
3203 /* OP_D4 (); */
3204 PC = cia;
3205 if (PSW & PSW_C)
3206 {
3207 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3208 nia = PC;
3209 }
3210}
3211
3212
3213// 1101 1010; lra
32148.0xda:S0:::lra
3215"lra"
3216*mn10300
c2d11a7d
JM		 3217
3218*am33
3219
c906108c
SS		 3220{
3221 /* OP_DA (); */
3222 PC = cia;
3223 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3224 nia = PC;
3225}
3226
3227
3228// 1101 1010; setlb
32298.0xdb:S0:::setlb
3230"setlb"
3231*mn10300
c2d11a7d
JM		 3232
3233*am33
3234
c906108c
SS		 3235{
3236 /* OP_DB (); */
3237 PC = cia;
3238 State.regs[REG_LIR] = load_word (State.regs[REG_PC] + 1);
3239 State.regs[REG_LAR] = State.regs[REG_PC] + 5;
3240}
3241
3242
3243// 1111 0000 1111 01An; jmp (An)
32448.0xf0+4.0xf,01,2.AN0:D0:::jmp
3245"jmp"
3246*mn10300
c2d11a7d
JM		 3247
3248*am33
3249
c906108c
SS		 3250{
3251 /* OP_F0F4 (); */
3252 PC = State.regs[REG_A0 + AN0];
3253 nia = PC;
3254}
3255
3256
3257// 1100 1100 d16.....; jmp (d16,PC) (d16 is sign-extended.)
32588.0xcc+8.D16A+8.D16B:S2:::jmp
3259"jmp"
3260*mn10300
c2d11a7d
JM		 3261
3262*am33
3263
c906108c
SS		 3264{
3265 /* OP_CC0000 (); */
3266 PC = cia + EXTEND16(FETCH16(D16A, D16B));
3267 nia = PC;
3268}
3269
3270
3271// 1101 1100 d32........; jmp (d32, PC)
32728.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp
3273"jmp"
3274*mn10300
c2d11a7d
JM		 3275
3276*am33
3277
c906108c
SS		 3278{
3279 /* OP_DC000000 (); */
3280 PC = cia + FETCH32(D32A, D32B, D32C, D32D);
3281 nia = PC;
3282}
3283
3284
3285// 1111 0000 1111 00An; calls (An)
32868.0xf0+4.0xf,00,2.AN0:D0:::calls
3287"calls"
3288*mn10300
c2d11a7d
JM		 3289
3290*am33
3291
c906108c
SS		 3292{
3293 /* OP_F0F0 (); */
24a39d88 3294 unsigned32 next_pc, sp;
c906108c
SS		 3295
3296 PC = cia;
3297 sp = State.regs[REG_SP];
3298 next_pc = State.regs[REG_PC] + 2;
3299 store_word(sp, next_pc);
3300 State.regs[REG_MDR] = next_pc;
3301 State.regs[REG_PC] = State.regs[REG_A0 + AN0];
3302 nia = PC;
3303}
3304
3305
3306// 1111 1010 1111 1111 d16.....; calls (d16,PC) (d16 is sign-extended.)
33078.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls
3308"calls"
3309*mn10300
c2d11a7d
JM		 3310
3311*am33
3312
c906108c
SS		 3313{
3314 /* OP_FAFF0000 (); */
24a39d88 3315 unsigned32 next_pc, sp;
c906108c
SS		 3316
3317 PC = cia;
3318 sp = State.regs[REG_SP];
3319 next_pc = State.regs[REG_PC] + 4;
3320 store_word(sp, next_pc);
3321 State.regs[REG_MDR] = next_pc;
3322 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
3323 nia = PC;
3324}
3325
3326
3327// 1111 1100 1111 1111 d32.....; calls (d32,PC)
33288.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls
3329"calls"
3330*mn10300
c2d11a7d
JM		 3331
3332*am33
3333
c906108c
SS		 3334{
3335 /* OP_FCFF0000 (); */
24a39d88 3336 unsigned32 next_pc, sp;
c906108c
SS		 3337
3338 PC = cia;
3339 sp = State.regs[REG_SP];
3340 next_pc = State.regs[REG_PC] + 6;
3341 store_word(sp, next_pc);
3342 State.regs[REG_MDR] = next_pc;
3343 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
3344 nia = PC;
3345}
3346
3347
3348// 1111 0000 1111 1100; rets
33498.0xf0+8.0xfc:D0:::rets
3350"rets"
3351*mn10300
c2d11a7d
JM		 3352
3353*am33
3354
c906108c
SS		 3355{
3356 /* OP_F0FC (); */
24a39d88 3357 unsigned32 sp;
c906108c
SS		 3358
3359 sp = State.regs[REG_SP];
3360 State.regs[REG_PC] = load_word(sp);
3361 nia = PC;
3362}
3363
3364
3365// 1111 0000 1111 1101; rti
33668.0xf0+8.0xfd:D0:::rti
3367"rti"
3368*mn10300
c2d11a7d
JM		 3369
3370*am33
3371
c906108c
SS		 3372{
3373 /* OP_F0FD (); */
24a39d88 3374 unsigned32 sp;
c906108c
SS		 3375
3376 sp = State.regs[REG_SP];
3377 PSW = load_half(sp);
3378 State.regs[REG_PC] = load_word(sp+4);
3379 State.regs[REG_SP] +=8;
3380 nia = PC;
3381}
3382
3383
3384// 1111 0000 1111 1110; trap
33858.0xf0+8.0xfe:D0:::trap
3386"trap"
3387*mn10300
c2d11a7d
JM		 3388
3389*am33
3390
c906108c
SS		 3391{
3392 /* OP_F0FE (); */
24a39d88 3393 unsigned32 sp, next_pc;
c906108c
SS		 3394
3395 PC = cia;
3396 sp = State.regs[REG_SP];
3397 next_pc = State.regs[REG_PC] + 2;
3398 store_word(sp, next_pc);
3399 nia = PC;
3400}
3401
3402
3403// 1111 0000 1111 1111; rtm
34048.0xf0+8.0xff:D0:::rtm
3405"rtm"
3406*mn10300
c2d11a7d
JM		 3407
3408*am33
3409
c906108c
SS		 3410{
3411 /* OP_F0FF (); */
3412 PC = cia;
3413 abort ();
3414}
3415
3416
3417// 1100 1011; nop
34188.0xcb:S0:::nop
3419"nop"
3420*mn10300
c2d11a7d
JM		 3421
3422*am33
3423
c906108c
SS		 3424{
3425 /* OP_CB (); */
3426 PC = cia;
3427}
3428
3429
3430// 1111 0101 0000 DmDn; udf20 Dm,Dn
34318.0xf5+4.0x0,2.DM1,2.DN0:D0:::putx
3432"putx"
3433*mn10300
3434{
3435 /* OP_F500 (); */
3436 PC = cia;
3437 State.regs[REG_MDRQ] = State.regs[REG_D0 + DN0];
3438}
3439
3440
3441// 1111 0110 1111 DmDn; udf15 Dm,Dn
34428.0xf6+4.0xf,2.DM1,2.DN0:D0:::getx
3443"getx"
3444*mn10300
c2d11a7d
JM		 3445
3446*am33
3447
c906108c
SS		 3448{
3449 /* OP_F6F0 (); */
3450 int z, n;
3451
3452 PC = cia;
3453 z = (State.regs[REG_MDRQ] == 0);
3454 n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
3455 State.regs[REG_D0 + DN0] = State.regs[REG_MDRQ];
3456
3457 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3458 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
3459}
3460
3461
3462// 1111 0110 0000 DmDn; udf00 Dm,Dn
34638.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq
3464"mulq"
3465*mn10300
c2d11a7d
JM		 3466
3467*am33
3468
c906108c
SS		 3469{
3470 /* OP_F600 (); */
24a39d88 3471 unsigned64 temp;
c906108c
SS		 3472 int n, z;
3473
3474 PC = cia;
3475 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3476 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
3477 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3478 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3479 z = (State.regs[REG_D0 + DN0] == 0);
3480 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3481 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3482 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3483}
3484
3485
3486// 1111 1001 0000 00Dn imm8....; udf00 imm8,Dn (imm8 is sign-extended.)
34878.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq
3488"mulq"
3489*mn10300
c2d11a7d
JM		 3490
3491*am33
3492
c906108c
SS		 3493{
3494 /* OP_F90000 (); */
24a39d88 3495 unsigned64 temp;
c906108c
SS		 3496 int n, z;
3497
3498 PC = cia;
3499 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3500 * (signed64)(signed32)EXTEND8 (IMM8));
3501 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3502 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3503 z = (State.regs[REG_D0 + DN0] == 0);
3504 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3505 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3506 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3507}
3508
3509
3510// 1111 1011 0000 00Dn imm16...; udf00 imm16,Dn (imm16 is sign-extended.)
35118.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq
3512"mulq"
3513*mn10300
c2d11a7d
JM		 3514
3515*am33
3516
c906108c
SS		 3517{
3518 /* OP_FB000000 (); */
24a39d88 3519 unsigned64 temp;
c906108c
SS		 3520 int n, z;
3521
3522 PC = cia;
3523 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3524 * (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B)));
3525 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3526 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3527 z = (State.regs[REG_D0 + DN0] == 0);
3528 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3529 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3530 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3531}
3532
3533
3534// 1111 1101 0000 00Dn imm32...; udf00 imm32,Dn
35358.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq
3536"mulq"
3537*mn10300
c2d11a7d
JM		 3538
3539*am33
3540
c906108c
SS		 3541{
3542 /* OP_FD000000 (); */
24a39d88 3543 unsigned64 temp;
c906108c
SS		 3544 int n, z;
3545
3546 PC = cia;
3547 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3548 * (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3549 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3550 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3551 z = (State.regs[REG_D0 + DN0] == 0);
3552 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3553 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3554 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3555}
3556
3557
3558// 1111 0110 0001 DmDn; udf01 Dm,Dn
35598.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu
3560"mulqu"
3561*mn10300
c2d11a7d
JM		 3562
3563*am33
3564
c906108c
SS		 3565{
3566 /* OP_F610 (); */
24a39d88 3567 unsigned64 temp;
c906108c
SS		 3568 int n, z;
3569
3570 PC = cia;
3571 temp = ((unsigned64) State.regs[REG_D0 + DN0]
3572 * (unsigned64) State.regs[REG_D0 + DM1]);
3573 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3574 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3575 z = (State.regs[REG_D0 + DN0] == 0);
3576 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3577 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3578 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3579}
3580
3581
3582// 1111 1001 0001 01Dn imm8....; udfu01 imm8,Dn (imm8 is zero-extended.)
35838.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu
3584"mulqu"
3585*mn10300
c2d11a7d
JM		 3586
3587*am33
3588
c906108c
SS		 3589{
3590 /* OP_F91400 (); */
24a39d88 3591 unsigned64 temp;
c906108c
SS		 3592 int n, z;
3593
3594 PC = cia;
3595 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3596 * (unsigned64)EXTEND8 (IMM8));
3597 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3598 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3599 z = (State.regs[REG_D0 + DN0] == 0);
3600 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3601 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3602 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3603}
3604
3605
3606// 1111 1011 0001 01Dn imm16...; udfu01 imm16,Dn (imm16 is zero-extended.)
36078.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu
3608"mulqu"
3609*mn10300
c2d11a7d
JM		 3610
3611*am33
3612
c906108c
SS		 3613{
3614 /* OP_FB140000 (); */
24a39d88 3615 unsigned64 temp;
c906108c
SS		 3616 int n, z;
3617
3618 PC = cia;
3619 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3620 * (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B)));
3621 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3622 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3623 z = (State.regs[REG_D0 + DN0] == 0);
3624 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3625 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3626 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3627}
3628
3629
3630// 1111 1101 0001 01Dn imm32...; udfu01 imm32,Dn
36318.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu
3632"mulqu"
3633*mn10300
c2d11a7d
JM		 3634
3635*am33
3636
c906108c
SS		 3637{
3638 /* OP_FD140000 (); */
24a39d88 3639 unsigned64 temp;
c906108c
SS		 3640 int n, z;
3641
3642 PC = cia;
3643 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3644 * (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3645 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3646 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3647 z = (State.regs[REG_D0 + DN0] == 0);
3648 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3649 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3650 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3651}
3652
3653
3654// 1111 0110 0100 DmDn; udf04 Dm,Dn
36558.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16
3656"sat16"
3657*mn10300
c2d11a7d
JM		 3658
3659*am33
3660
c906108c
SS		 3661{
3662 /* OP_F640 (); */
3663 int temp;
3664
3665 PC = cia;
3666 temp = State.regs[REG_D0 + DM1];
3667 temp = (temp > 0x7fff ? 0x7fff : temp);
3668 temp = (temp < -0x8000 ? -0x8000 : temp);
3669 State.regs[REG_D0 + DN0] = temp;
3670}
3671
3672
3673// 1111 0110 0101 DmDn; udf05 Dm,Dn
36748.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24
3675"sat24"
3676*mn10300
c2d11a7d
JM		 3677
3678*am33
3679
c906108c
SS		 3680{
3681 /* OP_F650 (); */
3682 int temp;
3683
3684 PC = cia;
3685 temp = State.regs[REG_D0 + DM1];
3686 temp = (temp > 0x7fffff ? 0x7fffff : temp);
3687 temp = (temp < -0x800000 ? -0x800000 : temp);
3688 State.regs[REG_D0 + DN0] = temp;
3689}
3690
3691
3692// 1111 0110 0111 DmDn; udf07 Dm,Dn
36938.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch
3694"bsch"
3695*mn10300
c2d11a7d
JM		 3696
3697*am33
3698
c906108c
SS		 3699{
3700 /* OP_F670 (); */
3701 int temp, c;
3702
3703 PC = cia;
3704 temp = State.regs[REG_D0 + DM1];
3705 temp <<= (State.regs[REG_D0 + DN0] & 0x1f);
3706 c = (temp != 0 ? 1 : 0);
3707 PSW &= ~(PSW_C);
3708 PSW |= (c ? PSW_C : 0);
3709}
3710
3711
3712// 1111 0000 1100 0000; syscall
37138.0xf0+8.0xc0:D0:::syscall
3714"syscall"
3715*mn10300
c2d11a7d
JM		 3716
3717*am33
3718
c906108c
SS		 3719{
3720 /* OP_F0C0 (); */
3721 PC = cia;
3722 do_syscall ();
3723}
3724
3725
3726// 1111 1111; break
37278.0xff:S0:::break
3728"break"
3729*mn10300
c2d11a7d
JM		 3730
3731*am33
3732
c906108c
SS		 3733{
3734 /* OP_FF (); */
3735 PC = cia;
3736 program_interrupt(SD, CPU, cia, SIM_SIGTRAP);
3737}
3738
3739// 1100 1110 regs....; movm (SP),regs
37408.0xce+8.REGS:S1:::movm
3741"movm"
3742*mn10300
c2d11a7d
JM		 3743
3744*am33
3745
c906108c
SS		 3746{
3747 /* OP_CE00 (); */
24a39d88
AO		 3748 unsigned32 sp = State.regs[REG_SP];
3749 unsigned32 mask;
c906108c
SS		 3750
3751 PC = cia;
3752 mask = REGS;
3753
3754 if (mask & 0x8)
3755 {
3756 sp += 4;
3757 State.regs[REG_LAR] = load_word (sp);
3758 sp += 4;
3759 State.regs[REG_LIR] = load_word (sp);
3760 sp += 4;
3761 State.regs[REG_MDR] = load_word (sp);
3762 sp += 4;
3763 State.regs[REG_A0 + 1] = load_word (sp);
3764 sp += 4;
3765 State.regs[REG_A0] = load_word (sp);
3766 sp += 4;
3767 State.regs[REG_D0 + 1] = load_word (sp);
3768 sp += 4;
3769 State.regs[REG_D0] = load_word (sp);
3770 sp += 4;
3771 }
3772
3773 if (mask & 0x10)
3774 {
3775 State.regs[REG_A0 + 3] = load_word (sp);
3776 sp += 4;
3777 }
3778
3779 if (mask & 0x20)
3780 {
3781 State.regs[REG_A0 + 2] = load_word (sp);
3782 sp += 4;
3783 }
3784
3785 if (mask & 0x40)
3786 {
3787 State.regs[REG_D0 + 3] = load_word (sp);
3788 sp += 4;
3789 }
3790
3791 if (mask & 0x80)
3792 {
3793 State.regs[REG_D0 + 2] = load_word (sp);
3794 sp += 4;
3795 }
3796
ceec3559
NC		 3797 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
3798 )
c2d11a7d
JM		 3799 {
3800 if (mask & 0x1)
3801 {
3802 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
3803 sp += 16;
3804 State.regs[REG_E0 + 1] = load_word (sp);
3805 sp += 4;
3806 State.regs[REG_E0 + 0] = load_word (sp);
3807 sp += 4;
3808 }
3809
3810 if (mask & 0x2)
3811 {
3812 State.regs[REG_E0 + 7] = load_word (sp);
3813 sp += 4;
3814 State.regs[REG_E0 + 6] = load_word (sp);
3815 sp += 4;
3816 State.regs[REG_E0 + 5] = load_word (sp);
3817 sp += 4;
3818 State.regs[REG_E0 + 4] = load_word (sp);
3819 sp += 4;
3820 }
3821
3822 if (mask & 0x4)
3823 {
3824 State.regs[REG_E0 + 3] = load_word (sp);
3825 sp += 4;
3826 State.regs[REG_E0 + 2] = load_word (sp);
3827 sp += 4;
3828 }
3829 }
c906108c
SS		 3830
3831 /* And make sure to update the stack pointer. */
3832 State.regs[REG_SP] = sp;
3833}
3834
3835
3836// 1100 1111 regs....; movm regs,(SP)
38378.0xcf+8.REGS:S1a:::movm
3838"movm"
3839*mn10300
c2d11a7d
JM		 3840
3841*am33
3842
c906108c
SS		 3843{
3844 /* OP_CF00 (); */
24a39d88
AO		 3845 unsigned32 sp = State.regs[REG_SP];
3846 unsigned32 mask;
c906108c
SS		 3847
3848 PC = cia;
3849 mask = REGS;
3850
ceec3559
NC		 3851 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
3852 )
c2d11a7d
JM		 3853 {
3854 if (mask & 0x4)
3855 {
3856 sp -= 4;
3857 store_word (sp, State.regs[REG_E0 + 2]);
3858 sp -= 4;
3859 store_word (sp, State.regs[REG_E0 + 3]);
3860 }
3861
3862 if (mask & 0x2)
3863 {
3864 sp -= 4;
3865 store_word (sp, State.regs[REG_E0 + 4]);
3866 sp -= 4;
3867 store_word (sp, State.regs[REG_E0 + 5]);
3868 sp -= 4;
3869 store_word (sp, State.regs[REG_E0 + 6]);
3870 sp -= 4;
3871 store_word (sp, State.regs[REG_E0 + 7]);
3872 }
3873
3874 if (mask & 0x1)
3875 {
3876 sp -= 4;
3877 store_word (sp, State.regs[REG_E0 + 0]);
3878 sp -= 4;
3879 store_word (sp, State.regs[REG_E0 + 1]);
3880 sp -= 16;
3881 /* Need to save MDQR, MCRH, MCRL, and MCVF */
3882 }
3883 }
c906108c
SS		 3884
3885 if (mask & 0x80)
3886 {
3887 sp -= 4;
3888 store_word (sp, State.regs[REG_D0 + 2]);
3889 }
3890
3891 if (mask & 0x40)
3892 {
3893 sp -= 4;
3894 store_word (sp, State.regs[REG_D0 + 3]);
3895 }
3896
3897 if (mask & 0x20)
3898 {
3899 sp -= 4;
3900 store_word (sp, State.regs[REG_A0 + 2]);
3901 }
3902
3903 if (mask & 0x10)
3904 {
3905 sp -= 4;
3906 store_word (sp, State.regs[REG_A0 + 3]);
3907 }
3908
3909 if (mask & 0x8)
3910 {
3911 sp -= 4;
3912 store_word (sp, State.regs[REG_D0]);
3913 sp -= 4;
3914 store_word (sp, State.regs[REG_D0 + 1]);
3915 sp -= 4;
3916 store_word (sp, State.regs[REG_A0]);
3917 sp -= 4;
3918 store_word (sp, State.regs[REG_A0 + 1]);
3919 sp -= 4;
3920 store_word (sp, State.regs[REG_MDR]);
3921 sp -= 4;
3922 store_word (sp, State.regs[REG_LIR]);
3923 sp -= 4;
3924 store_word (sp, State.regs[REG_LAR]);
3925 sp -= 4;
3926 }
3927
3928 /* And make sure to update the stack pointer. */
3929 State.regs[REG_SP] = sp;
3930}
3931
3932// 1100 1101 d16..... regs.... imm8....;
3933// call (d16,PC),regs,imm8 (d16 is sign-extended., imm8 is zero-extended.)
39348.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call
3935"call"
3936*mn10300
c2d11a7d
JM		 3937
3938*am33
3939
c906108c
SS		 3940{
3941 /* OP_CD000000 (); */
24a39d88
AO		 3942 unsigned32 next_pc, sp;
3943 unsigned32 mask;
c906108c
SS		 3944
3945 PC = cia;
3946 sp = State.regs[REG_SP];
3947 next_pc = PC + 5;
3948 store_word(sp, next_pc);
3949
3950 mask = REGS;
3951
ceec3559
NC		 3952 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
3953 )
c2d11a7d
JM		 3954 {
3955 if (mask & 0x4)
3956 {
3957 sp -= 4;
3958 store_word (sp, State.regs[REG_E0 + 2]);
3959 sp -= 4;
3960 store_word (sp, State.regs[REG_E0 + 3]);
3961 }
3962
3963 if (mask & 0x2)
3964 {
3965 sp -= 4;
3966 store_word (sp, State.regs[REG_E0 + 4]);
3967 sp -= 4;
3968 store_word (sp, State.regs[REG_E0 + 5]);
3969 sp -= 4;
3970 store_word (sp, State.regs[REG_E0 + 6]);
3971 sp -= 4;
3972 store_word (sp, State.regs[REG_E0 + 7]);
3973 }
3974
3975 if (mask & 0x1)
3976 {
3977 sp -= 4;
3978 store_word (sp, State.regs[REG_E0 + 0]);
3979 sp -= 4;
3980 store_word (sp, State.regs[REG_E0 + 1]);
3981 sp -= 16;
3982 /* Need to save MDQR, MCRH, MCRL, and MCVF */
3983 }
3984 }
c906108c
SS		 3985
3986 if (mask & 0x80)
3987 {
3988 sp -= 4;
3989 store_word (sp, State.regs[REG_D0 + 2]);
3990 }
3991
3992 if (mask & 0x40)
3993 {
3994 sp -= 4;
3995 store_word (sp, State.regs[REG_D0 + 3]);
3996 }
3997
3998 if (mask & 0x20)
3999 {
4000 sp -= 4;
4001 store_word (sp, State.regs[REG_A0 + 2]);
4002 }
4003
4004 if (mask & 0x10)
4005 {
4006 sp -= 4;
4007 store_word (sp, State.regs[REG_A0 + 3]);
4008 }
4009
4010 if (mask & 0x8)
4011 {
4012 sp -= 4;
4013 store_word (sp, State.regs[REG_D0]);
4014 sp -= 4;
4015 store_word (sp, State.regs[REG_D0 + 1]);
4016 sp -= 4;
4017 store_word (sp, State.regs[REG_A0]);
4018 sp -= 4;
4019 store_word (sp, State.regs[REG_A0 + 1]);
4020 sp -= 4;
4021 store_word (sp, State.regs[REG_MDR]);
4022 sp -= 4;
4023 store_word (sp, State.regs[REG_LIR]);
4024 sp -= 4;
4025 store_word (sp, State.regs[REG_LAR]);
4026 sp -= 4;
4027 }
4028
4029 /* Update the stack pointer, note that the register saves to do not
4030 modify SP. The SP adjustment is derived totally from the imm8
4031 field. */
4032 State.regs[REG_SP] -= IMM8;
4033 State.regs[REG_MDR] = next_pc;
4034 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
4035 nia = PC;
4036}
4037
4038
4039// 1101 1101 d32..... regs.... imm8....;
4040// call (d32,PC),regs,imm8 (imm8 is zero-extended.)
40418.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call
4042"call"
4043*mn10300
c2d11a7d
JM		 4044
4045*am33
4046
c906108c
SS		 4047{
4048 /* OP_DD000000 (); */
24a39d88
AO		 4049 unsigned32 next_pc, sp;
4050 unsigned32 mask;
c906108c
SS		 4051
4052 PC = cia;
4053 sp = State.regs[REG_SP];
4054 next_pc = State.regs[REG_PC] + 7;
4055 /* could assert that nia == next_pc here */
4056 store_word(sp, next_pc);
4057
4058 mask = REGS;
4059
ceec3559
NC		 4060 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
4061 )
c2d11a7d
JM		 4062 {
4063 if (mask & 0x4)
4064 {
4065 sp -= 4;
4066 store_word (sp, State.regs[REG_E0 + 2]);
4067 sp -= 4;
4068 store_word (sp, State.regs[REG_E0 + 3]);
4069 }
4070
4071 if (mask & 0x2)
4072 {
4073 sp -= 4;
4074 store_word (sp, State.regs[REG_E0 + 4]);
4075 sp -= 4;
4076 store_word (sp, State.regs[REG_E0 + 5]);
4077 sp -= 4;
4078 store_word (sp, State.regs[REG_E0 + 6]);
4079 sp -= 4;
4080 store_word (sp, State.regs[REG_E0 + 7]);
4081 }
4082
4083 if (mask & 0x1)
4084 {
4085 sp -= 4;
4086 store_word (sp, State.regs[REG_E0 + 0]);
4087 sp -= 4;
4088 store_word (sp, State.regs[REG_E0 + 1]);
4089 sp -= 16;
4090 /* Need to save MDQR, MCRH, MCRL, and MCVF */
4091 }
4092 }
c906108c
SS		 4093
4094 if (mask & 0x80)
4095 {
4096 sp -= 4;
4097 store_word (sp, State.regs[REG_D0 + 2]);
4098 }
4099
4100 if (mask & 0x40)
4101 {
4102 sp -= 4;
4103 store_word (sp, State.regs[REG_D0 + 3]);
4104 }
4105
4106 if (mask & 0x20)
4107 {
4108 sp -= 4;
4109 store_word (sp, State.regs[REG_A0 + 2]);
4110 }
4111
4112 if (mask & 0x10)
4113 {
4114 sp -= 4;
4115 store_word (sp, State.regs[REG_A0 + 3]);
4116 }
4117
4118 if (mask & 0x8)
4119 {
4120 sp -= 4;
4121 store_word (sp, State.regs[REG_D0]);
4122 sp -= 4;
4123 store_word (sp, State.regs[REG_D0 + 1]);
4124 sp -= 4;
4125 store_word (sp, State.regs[REG_A0]);
4126 sp -= 4;
4127 store_word (sp, State.regs[REG_A0 + 1]);
4128 sp -= 4;
4129 store_word (sp, State.regs[REG_MDR]);
4130 sp -= 4;
4131 store_word (sp, State.regs[REG_LIR]);
4132 sp -= 4;
4133 store_word (sp, State.regs[REG_LAR]);
4134 sp -= 4;
4135 }
4136
4137 /* Update the stack pointer, note that the register saves to do not
4138 modify SP. The SP adjustment is derived totally from the imm8
4139 field. */
4140 State.regs[REG_SP] -= IMM8;
4141 State.regs[REG_MDR] = next_pc;
4142 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
4143 nia = PC;
4144}
4145
4146
4147// 1101 1111 regs.... imm8....; ret regs,imm8 (imm8 is zero-extended.)
41488.0xdf+8.REGS+8.IMM8:S2:::ret
4149"ret"
4150*mn10300
c2d11a7d
JM		 4151
4152*am33
4153
c906108c
SS		 4154{
4155 /* OP_DF0000 (); */
24a39d88
AO		 4156 unsigned32 sp, offset;
4157 unsigned32 mask;
c906108c
SS		 4158
4159 PC = cia;
4160 State.regs[REG_SP] += IMM8;
4161 sp = State.regs[REG_SP];
4162
4163 offset = -4;
4164 mask = REGS;
4165
ceec3559
NC		 4166 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
4167 )
c2d11a7d
JM		 4168 {
4169
4170 if (mask & 0x4)
4171 {
4172 State.regs[REG_E0 + 2] = load_word (sp + offset);
4173 offset -= 4;
4174 State.regs[REG_E0 + 3] = load_word (sp + offset);
4175 offset -= 4;
4176 }
4177
4178 if (mask & 0x2)
4179 {
4180 State.regs[REG_E0 + 4] = load_word (sp + offset);
4181 offset -= 4;
4182 State.regs[REG_E0 + 5] = load_word (sp + offset);
4183 offset -= 4;
4184 State.regs[REG_E0 + 6] = load_word (sp + offset);
4185 offset -= 4;
4186 State.regs[REG_E0 + 7] = load_word (sp + offset);
4187 offset -= 4;
4188 }
4189
4190 if (mask & 0x1)
4191 {
4192 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
4193 offset -= 16;
4194 State.regs[REG_E0 + 0] = load_word (sp + offset);
4195 offset -= 4;
4196 State.regs[REG_E0 + 1] = load_word (sp + offset);
4197 offset -= 4;
4198 }
4199
4200 }
c906108c
SS		 4201
4202 if (mask & 0x80)
4203 {
4204 State.regs[REG_D0 + 2] = load_word (sp + offset);
4205 offset -= 4;
4206 }
4207
4208 if (mask & 0x40)
4209 {
4210 State.regs[REG_D0 + 3] = load_word (sp + offset);
4211 offset -= 4;
4212 }
4213
4214 if (mask & 0x20)
4215 {
4216 State.regs[REG_A0 + 2] = load_word (sp + offset);
4217 offset -= 4;
4218 }
4219
4220 if (mask & 0x10)
4221 {
4222 State.regs[REG_A0 + 3] = load_word (sp + offset);
4223 offset -= 4;
4224 }
4225
4226 if (mask & 0x8)
4227 {
4228 State.regs[REG_D0] = load_word (sp + offset);
4229 offset -= 4;
4230 State.regs[REG_D0 + 1] = load_word (sp + offset);
4231 offset -= 4;
4232 State.regs[REG_A0] = load_word (sp + offset);
4233 offset -= 4;
4234 State.regs[REG_A0 + 1] = load_word (sp + offset);
4235 offset -= 4;
4236 State.regs[REG_MDR] = load_word (sp + offset);
4237 offset -= 4;
4238 State.regs[REG_LIR] = load_word (sp + offset);
4239 offset -= 4;
4240 State.regs[REG_LAR] = load_word (sp + offset);
4241 offset -= 4;
4242 }
4243
4244 /* Restore the PC value. */
4245 State.regs[REG_PC] = load_word(sp);
4246 nia = PC;
4247}
4248
4249
4250// 1101 1110 regs.... imm8....; retf regs,imm8 (imm8 is zero-extended.)
42518.0xde+8.REGS+8.IMM8:S2:::retf
4252"retf"
4253*mn10300
c2d11a7d
JM		 4254
4255*am33
4256
c906108c
SS		 4257{
4258 /* OP_DE0000 (); */
24a39d88
AO		 4259 unsigned32 sp, offset;
4260 unsigned32 mask;
c906108c
SS		 4261
4262 PC = cia;
4263 State.regs[REG_SP] += IMM8;
4264 sp = State.regs[REG_SP];
7a292a7a 4265 State.regs[REG_PC] = State.regs[REG_MDR];
c906108c
SS		 4266
4267 offset = -4;
4268 mask = REGS;
4269
ceec3559
NC		 4270 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
4271 )
c2d11a7d
JM		 4272 {
4273
4274 if (mask & 0x4)
4275 {
4276 State.regs[REG_E0 + 2] = load_word (sp + offset);
4277 offset -= 4;
4278 State.regs[REG_E0 + 3] = load_word (sp + offset);
4279 offset -= 4;
4280 }
4281
4282 if (mask & 0x2)
4283 {
4284 State.regs[REG_E0 + 4] = load_word (sp + offset);
4285 offset -= 4;
4286 State.regs[REG_E0 + 5] = load_word (sp + offset);
4287 offset -= 4;
4288 State.regs[REG_E0 + 6] = load_word (sp + offset);
4289 offset -= 4;
4290 State.regs[REG_E0 + 7] = load_word (sp + offset);
4291 offset -= 4;
4292 }
4293
4294 if (mask & 0x1)
4295 {
4296 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
4297 offset -= 16;
4298 State.regs[REG_E0 + 0] = load_word (sp + offset);
4299 offset -= 4;
4300 State.regs[REG_E0 + 1] = load_word (sp + offset);
4301 offset -= 4;
4302 }
4303
4304 }
c906108c
SS		 4305
4306 if (mask & 0x80)
4307 {
4308 State.regs[REG_D0 + 2] = load_word (sp + offset);
4309 offset -= 4;
4310 }
4311
4312 if (mask & 0x40)
4313 {
4314 State.regs[REG_D0 + 3] = load_word (sp + offset);
4315 offset -= 4;
4316 }
4317
4318 if (mask & 0x20)
4319 {
4320 State.regs[REG_A0 + 2] = load_word (sp + offset);
4321 offset -= 4;
4322 }
4323
4324 if (mask & 0x10)
4325 {
4326 State.regs[REG_A0 + 3] = load_word (sp + offset);
4327 offset -= 4;
4328 }
4329
4330 if (mask & 0x8)
4331 {
4332 State.regs[REG_D0] = load_word (sp + offset);
4333 offset -= 4;
4334 State.regs[REG_D0 + 1] = load_word (sp + offset);
4335 offset -= 4;
4336 State.regs[REG_A0] = load_word (sp + offset);
4337 offset -= 4;
4338 State.regs[REG_A0 + 1] = load_word (sp + offset);
4339 offset -= 4;
4340 State.regs[REG_MDR] = load_word (sp + offset);
4341 offset -= 4;
4342 State.regs[REG_LIR] = load_word (sp + offset);
4343 offset -= 4;
4344 State.regs[REG_LAR] = load_word (sp + offset);
4345 offset -= 4;
4346 }
7a292a7a 4347 nia = PC;
c906108c
SS		 4348}
4349
c2d11a7d
JM		 4350
4351:include::am33:am33.igen
4352
GDB Binutils - Deliverables
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