Commit | Line | Data |
---|---|---|
d2b02ab2 | 1 | // -*- C -*- |
7986ea13 JJ |
2 | :option:::insn-bit-size:8 |
3 | :option:::insn-specifying-widths:true | |
4 | :option:::hi-bit-nr:7 | |
5 | :model:::mn10300:mn10300: | |
d2b02ab2 | 6 | :model:::am33:am33: |
7986ea13 JJ |
7 | |
8 | // What do we do with an illegal instruction? | |
9 | :internal::::illegal: | |
10 | { | |
11 | sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n", | |
12 | (unsigned long) cia); | |
13 | sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL); | |
14 | } | |
15 | ||
16 | // 1000 DnDn imm8....; mov imm8,Dn (imm8 is sign extended) | |
d2b02ab2 JL |
17 | 4.0x8,2.DM1,2.DN0=DM1+IMM8:S0i:::mov |
18 | "mov" | |
19 | *mn10300 | |
20 | // start-sanitize-am33 | |
21 | *am33 | |
22 | // end-sanitize-am33 | |
23 | { | |
24 | // OP_8000 (); | |
25 | signed32 immed = EXTEND8 (IMM8); | |
26 | State.regs[REG_D0+DN0] = immed; | |
27 | PC = cia; | |
28 | } | |
29 | ||
7986ea13 | 30 | // 1000 DmDn; mov Dm,Dn (Dm != Dn, see above when Dm == Dn) |
d2b02ab2 | 31 | 4.0x8,2.DM1,2.DN0!DM1:S0:::mov |
7986ea13 JJ |
32 | "mov" |
33 | *mn10300 | |
d2b02ab2 JL |
34 | // start-sanitize-am33 |
35 | *am33 | |
36 | // end-sanitize-am33 | |
7986ea13 JJ |
37 | { |
38 | PC = cia; | |
d2b02ab2 JL |
39 | // OP_80 (); |
40 | State.regs[REG_D0+DN0] = State.regs[REG_D0+DM1]; | |
7986ea13 JJ |
41 | } |
42 | ||
43 | ||
44 | // 1111 0001 1110 DmAn; mov Dm,An | |
45 | 8.0xf1+1110,2.DM1,2.AN0:D0:::mov | |
46 | "mov" | |
47 | *mn10300 | |
d2b02ab2 JL |
48 | // start-sanitize-am33 |
49 | *am33 | |
50 | // end-sanitize-am33 | |
7986ea13 JJ |
51 | { |
52 | // OP_F1E0 (); | |
53 | PC = cia; | |
54 | State.regs[REG_A0 + AN0] = State.regs[REG_D0 + DM1]; | |
55 | } | |
56 | ||
57 | ||
58 | // 1111 0001 1101 AmDn; mov Am,Dn | |
59 | 8.0xf1+1101,2.AM1,2.DN0:D0a:::mov | |
60 | "mov" | |
61 | *mn10300 | |
d2b02ab2 JL |
62 | // start-sanitize-am33 |
63 | *am33 | |
64 | // end-sanitize-am33 | |
7986ea13 JJ |
65 | { |
66 | // OP_F1D0 (); | |
67 | PC = cia; | |
68 | State.regs[REG_D0 + DN0] = State.regs[REG_A0 + AM1]; | |
69 | } | |
70 | ||
71 | ||
72 | // 1001 AnAn imm8....; mov imm8,An (imm8 is zero-extended) | |
d2b02ab2 JL |
73 | 4.0x9,2.AM1,2.AN0=AM1+IMM8:S0ai:::mov |
74 | "mov" | |
75 | *mn10300 | |
76 | // start-sanitize-am33 | |
77 | *am33 | |
78 | // end-sanitize-am33 | |
79 | { | |
80 | PC = cia; | |
81 | // OP_9000 (); | |
82 | State.regs[REG_A0+AN0] = IMM8; | |
83 | } | |
84 | ||
85 | ||
7986ea13 | 86 | // 1001 AmAn; mov Am,An (Am != An, save above when Am == An) |
d2b02ab2 | 87 | 4.0x9,2.AM1,2.AN0!AM1:S0a:::mov |
7986ea13 JJ |
88 | "mov" |
89 | *mn10300 | |
d2b02ab2 JL |
90 | // start-sanitize-am33 |
91 | *am33 | |
92 | // end-sanitize-am33 | |
7986ea13 JJ |
93 | { |
94 | PC = cia; | |
d2b02ab2 JL |
95 | // OP_90 (); |
96 | State.regs[REG_A0+AN0] = State.regs[REG_A0+AM1]; | |
7986ea13 JJ |
97 | } |
98 | ||
99 | ||
100 | // 0011 11An; mov SP,An | |
101 | 4.0x3,11,2.AN0:S0b:::mov | |
102 | "mov" | |
103 | *mn10300 | |
d2b02ab2 JL |
104 | // start-sanitize-am33 |
105 | *am33 | |
106 | // end-sanitize-am33 | |
7986ea13 JJ |
107 | { |
108 | // OP_3C (); | |
109 | PC = cia; | |
110 | State.regs[REG_A0 + AN0] = State.regs[REG_SP]; | |
111 | } | |
112 | ||
113 | ||
114 | // 1111 0010 1111 Am00; mov Am,SP | |
115 | 8.0xf2+4.0xf,2.AM1,00:D0b:::mov | |
116 | "mov" | |
117 | *mn10300 | |
d2b02ab2 JL |
118 | // start-sanitize-am33 |
119 | *am33 | |
120 | // end-sanitize-am33 | |
7986ea13 JJ |
121 | { |
122 | // OP_F2F0 (); | |
123 | PC = cia; | |
124 | State.regs[REG_SP] = State.regs[REG_A0 + AM1]; | |
125 | } | |
126 | ||
127 | ||
128 | // 1111 0010 1110 01Dn; mov PSW,Dn | |
129 | 8.0xf2+4.0xe,01,2.DN0:D0c:::mov | |
130 | "mov" | |
131 | *mn10300 | |
d2b02ab2 JL |
132 | // start-sanitize-am33 |
133 | *am33 | |
134 | // end-sanitize-am33 | |
7986ea13 JJ |
135 | { |
136 | // OP_F2E4 (); | |
137 | PC = cia; | |
138 | State.regs[REG_D0 + DN0] = PSW; | |
139 | } | |
140 | ||
141 | ||
142 | // 1111 0010 1111 Dm11; mov Dm,PSW | |
143 | 8.0xf2+4.0xf,2.DM1,11:D0d:::mov | |
144 | "mov" | |
145 | *mn10300 | |
d2b02ab2 JL |
146 | // start-sanitize-am33 |
147 | *am33 | |
148 | // end-sanitize-am33 | |
7986ea13 JJ |
149 | { |
150 | // OP_F2F3 (); | |
151 | PC = cia; | |
152 | PSW = State.regs[REG_D0 + DM1]; | |
153 | } | |
154 | ||
155 | ||
156 | // 1111 0010 1110 00Dn; mov MDR,Dn | |
157 | 8.0xf2+4.0xe,00,2.DN0:D0e:::mov | |
158 | "mov" | |
159 | *mn10300 | |
d2b02ab2 JL |
160 | // start-sanitize-am33 |
161 | *am33 | |
162 | // end-sanitize-am33 | |
7986ea13 JJ |
163 | { |
164 | // OP_F2E0 (); | |
165 | PC = cia; | |
166 | State.regs[REG_D0 + DN0] = State.regs[REG_MDR]; | |
167 | } | |
168 | ||
169 | ||
170 | // 1111 0010 1111 Dm10; mov Dm,MDR | |
171 | 8.0xf2+4.0xf,2.DM1,10:D0f:::mov | |
172 | "mov" | |
173 | *mn10300 | |
d2b02ab2 JL |
174 | // start-sanitize-am33 |
175 | *am33 | |
176 | // end-sanitize-am33 | |
7986ea13 JJ |
177 | { |
178 | // OP_F2F2 (); | |
179 | PC = cia; | |
180 | State.regs[REG_MDR] = State.regs[REG_D0 + DM1]; | |
181 | } | |
182 | ||
183 | ||
184 | // 0111 DnAm; mov (Am),Dn | |
185 | 4.0x7,2.DN1,2.AM0:S0c:::mov | |
186 | "mov" | |
187 | *mn10300 | |
d2b02ab2 JL |
188 | // start-sanitize-am33 |
189 | *am33 | |
190 | // end-sanitize-am33 | |
7986ea13 JJ |
191 | { |
192 | // OP_70 (); | |
193 | PC = cia; | |
194 | State.regs[REG_D0 + DN1] = load_word (State.regs[REG_A0 + AM0]); | |
195 | } | |
196 | ||
197 | ||
198 | // 1111 1000 0000 DnAm d8......; mov (d8,Am),Dn (d8 is sign-extended) | |
199 | 8.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov | |
200 | "mov" | |
201 | *mn10300 | |
d2b02ab2 JL |
202 | // start-sanitize-am33 |
203 | *am33 | |
204 | // end-sanitize-am33 | |
7986ea13 JJ |
205 | { |
206 | // OP_F80000 (); | |
207 | PC = cia; | |
208 | State.regs[REG_D0 + DN1] | |
209 | = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8))); | |
210 | } | |
211 | ||
212 | ||
213 | // 1111 1010 0000 DnAm d16.....; mov (d16,Am),Dn (d16 is sign-extended.) | |
214 | 8.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov | |
215 | "mov" | |
216 | *mn10300 | |
d2b02ab2 JL |
217 | // start-sanitize-am33 |
218 | *am33 | |
219 | // end-sanitize-am33 | |
7986ea13 JJ |
220 | { |
221 | // OP_FA000000 (); | |
222 | PC = cia; | |
223 | State.regs[REG_D0 + DN1] | |
224 | = load_word ((State.regs[REG_A0 + AM0] + EXTEND16 (FETCH16(D16A, D16B)))); | |
225 | } | |
226 | ||
227 | ||
228 | // 1111 1100 0000 DnAm d32.....; mov (d32,Am),Dn | |
229 | 8.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov | |
230 | "mov" | |
231 | *mn10300 | |
d2b02ab2 JL |
232 | // start-sanitize-am33 |
233 | *am33 | |
234 | // end-sanitize-am33 | |
7986ea13 JJ |
235 | { |
236 | // OP_FC000000 (); | |
237 | PC = cia; | |
238 | State.regs[REG_D0 + DN1] | |
239 | = load_word ((State.regs[REG_A0 + AM0] | |
240 | + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D))); | |
241 | } | |
242 | ||
243 | ||
244 | // 0101 10Dn d8......; mov (d8,SP),Dn (d8 is zero-extended) | |
245 | 4.0x5,10,2.DN0+8.D8:S1:::mov | |
246 | "mov" | |
247 | *mn10300 | |
d2b02ab2 JL |
248 | // start-sanitize-am33 |
249 | *am33 | |
250 | // end-sanitize-am33 | |
7986ea13 JJ |
251 | { |
252 | // OP_5800 (); | |
253 | PC = cia; | |
254 | State.regs[REG_D0 + DN0] = load_word (State.regs[REG_SP] + D8); | |
255 | } | |
256 | ||
257 | ||
258 | // 1111 1010 1011 01Dn d16.....; mov (d16,SP),Dn (d16 is zero-extended.) | |
259 | 8.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov | |
260 | "mov" | |
261 | *mn10300 | |
d2b02ab2 JL |
262 | // start-sanitize-am33 |
263 | *am33 | |
264 | // end-sanitize-am33 | |
7986ea13 JJ |
265 | { |
266 | // OP_FAB40000 (); | |
267 | PC = cia; | |
268 | State.regs[REG_D0 + DN0] | |
269 | = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B)); | |
270 | } | |
271 | ||
272 | ||
273 | // 1111 1010 1011 01Dn d32.....; mov (d32,SP),Dn | |
274 | 8.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov | |
275 | "mov" | |
276 | *mn10300 | |
d2b02ab2 JL |
277 | // start-sanitize-am33 |
278 | *am33 | |
279 | // end-sanitize-am33 | |
7986ea13 JJ |
280 | { |
281 | // OP_FCB40000 (); | |
282 | PC = cia; | |
283 | State.regs[REG_D0 + DN0] | |
284 | = load_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)); | |
285 | } | |
286 | ||
287 | ||
288 | // 1111 0011 00Dn DiAm; mov (Di,Am),Dn | |
d2b02ab2 | 289 | 8.0xf3+00,2.DN2,2.DI,2.AM0:D0g:::mov |
7986ea13 JJ |
290 | "mov" |
291 | *mn10300 | |
d2b02ab2 JL |
292 | // start-sanitize-am33 |
293 | *am33 | |
294 | // end-sanitize-am33 | |
7986ea13 JJ |
295 | { |
296 | // OP_F300 (); | |
297 | PC = cia; | |
298 | State.regs[REG_D0 + DN2] | |
299 | = load_word ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI])); | |
300 | } | |
301 | ||
302 | ||
303 | // 0011 00Dn abs16...; mov (abs16),Dn (abs16 is zero-extended) | |
304 | 4.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov | |
305 | "mov" | |
306 | *mn10300 | |
d2b02ab2 JL |
307 | // start-sanitize-am33 |
308 | *am33 | |
309 | // end-sanitize-am33 | |
7986ea13 JJ |
310 | { |
311 | // OP_300000 (); | |
312 | PC = cia; | |
313 | State.regs[REG_D0 + DN0] = load_word (FETCH16(IMM16A, IMM16B)); | |
314 | } | |
315 | ||
316 | // 1111 1100 1010 01Dn abs32...; mov (abs32),Dn | |
317 | 8.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov | |
318 | "mov" | |
319 | *mn10300 | |
d2b02ab2 JL |
320 | // start-sanitize-am33 |
321 | *am33 | |
322 | // end-sanitize-am33 | |
7986ea13 JJ |
323 | { |
324 | // OP_FCA40000 (); | |
325 | PC = cia; | |
326 | State.regs[REG_D0 + DN0] = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)); | |
327 | } | |
328 | ||
329 | ||
330 | // 1111 0000 0000 AnAm; mov (Am),An | |
331 | 8.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov | |
332 | "mov" | |
333 | *mn10300 | |
d2b02ab2 JL |
334 | // start-sanitize-am33 |
335 | *am33 | |
336 | // end-sanitize-am33 | |
7986ea13 JJ |
337 | { |
338 | // OP_F000 (); | |
339 | PC = cia; | |
340 | State.regs[REG_A0 + AN1] = load_word (State.regs[REG_A0 + AM0]); | |
341 | } | |
342 | ||
343 | ||
344 | // 1111 1000 0010 AnAm d8......; mov (d8,Am),An (d8 is sign-extended) | |
345 | 8.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov | |
346 | "mov" | |
347 | *mn10300 | |
d2b02ab2 JL |
348 | // start-sanitize-am33 |
349 | *am33 | |
350 | // end-sanitize-am33 | |
7986ea13 JJ |
351 | { |
352 | // OP_F82000 (); | |
353 | PC = cia; | |
354 | State.regs[REG_A0 + AN1] | |
355 | = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8))); | |
356 | } | |
357 | ||
358 | ||
359 | // 1111 1010 0010 AnAm d16.....; mov (d16,Am),An (d16 is sign-extended.) | |
360 | 8.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov | |
361 | "mov" | |
362 | *mn10300 | |
d2b02ab2 JL |
363 | // start-sanitize-am33 |
364 | *am33 | |
365 | // end-sanitize-am33 | |
7986ea13 JJ |
366 | { |
367 | // OP_FA200000 (); | |
368 | PC = cia; | |
369 | State.regs[REG_A0 + AN1] | |
370 | = load_word ((State.regs[REG_A0 + AM0] | |
371 | + EXTEND16 (FETCH16(D16A, D16B)))); | |
372 | } | |
373 | ||
374 | ||
375 | // 1111 1100 0010 AnAm d32.....; mov (d32,Am),An | |
376 | 8.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov | |
377 | "mov" | |
378 | *mn10300 | |
d2b02ab2 JL |
379 | // start-sanitize-am33 |
380 | *am33 | |
381 | // end-sanitize-am33 | |
7986ea13 JJ |
382 | { |
383 | // OP_FC200000 (); | |
384 | PC = cia; | |
385 | State.regs[REG_A0 + AN1] | |
386 | = load_word ((State.regs[REG_A0 + AM0] | |
387 | + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D))); | |
388 | } | |
389 | ||
390 | ||
391 | // 0101 11An d8......; mov (d8,SP),An (d8 is zero-extended) | |
392 | 4.0x5,11,2.AN0+8.D8:S1a:::mov | |
393 | "mov" | |
394 | *mn10300 | |
d2b02ab2 JL |
395 | // start-sanitize-am33 |
396 | *am33 | |
397 | // end-sanitize-am33 | |
7986ea13 JJ |
398 | { |
399 | // OP_5C00 (); | |
400 | PC = cia; | |
401 | State.regs[REG_A0 + AN0] | |
402 | = load_word (State.regs[REG_SP] + D8); | |
403 | } | |
404 | ||
405 | ||
406 | // 1111 1010 1011 00An d16.....; mov (d16,SP),An (d16 is zero-extended.) | |
407 | 8.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov | |
408 | "mov" | |
409 | *mn10300 | |
d2b02ab2 JL |
410 | // start-sanitize-am33 |
411 | *am33 | |
412 | // end-sanitize-am33 | |
7986ea13 JJ |
413 | { |
414 | // OP_FAB00000 (); | |
415 | PC = cia; | |
416 | State.regs[REG_A0 + AN0] | |
417 | = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B)); | |
418 | } | |
419 | ||
420 | ||
421 | // 1111 1100 1011 00An d32.....; mov (d32,SP),An | |
422 | 8.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov | |
423 | "mov" | |
424 | *mn10300 | |
d2b02ab2 JL |
425 | // start-sanitize-am33 |
426 | *am33 | |
427 | // end-sanitize-am33 | |
7986ea13 JJ |
428 | { |
429 | // OP_FCB00000 (); | |
430 | PC = cia; | |
431 | State.regs[REG_A0 + AN0] | |
432 | = load_word (State.regs[REG_SP] | |
433 | + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)); | |
434 | } | |
435 | ||
436 | ||
437 | // 1111 0011 10An DiAm; mov (Di,Am),An | |
438 | 8.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov | |
439 | "mov" | |
440 | *mn10300 | |
d2b02ab2 JL |
441 | // start-sanitize-am33 |
442 | *am33 | |
443 | // end-sanitize-am33 | |
7986ea13 JJ |
444 | { |
445 | // OP_F380 (); | |
446 | PC = cia; | |
447 | State.regs[REG_A0 + AN2] | |
448 | = load_word ((State.regs[REG_A0 + AM0] | |
449 | + State.regs[REG_D0 + DI])); | |
450 | } | |
451 | ||
452 | ||
453 | // 1111 1010 1010 00An abs16...; mov (abs16),An (abs16 is zero-extended) | |
454 | 8.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov | |
455 | "mov" | |
456 | *mn10300 | |
d2b02ab2 JL |
457 | // start-sanitize-am33 |
458 | *am33 | |
459 | // end-sanitize-am33 | |
7986ea13 JJ |
460 | { |
461 | // OP_FAA00000 (); | |
462 | PC = cia; | |
463 | State.regs[REG_A0 + AN0] = load_word (FETCH16(IMM16A, IMM16B)); | |
464 | } | |
465 | ||
466 | ||
467 | // 1111 1100 1010 00An abs32...; mov (abs32),An | |
468 | 8.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov | |
469 | "mov" | |
470 | *mn10300 | |
d2b02ab2 JL |
471 | // start-sanitize-am33 |
472 | *am33 | |
473 | // end-sanitize-am33 | |
7986ea13 JJ |
474 | { |
475 | // OP_FCA00000 (); | |
476 | PC = cia; | |
477 | State.regs[REG_A0 + AN0] | |
478 | = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)); | |
479 | } | |
480 | ||
481 | ||
482 | // 1111 1000 1111 00Am d8......; mov (d8,Am),SP (d8 is sign-extended) | |
483 | 8.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov | |
484 | "mov" | |
485 | *mn10300 | |
d2b02ab2 JL |
486 | // start-sanitize-am33 |
487 | *am33 | |
488 | // end-sanitize-am33 | |
7986ea13 JJ |
489 | { |
490 | // OP_F8F000 (); | |
491 | PC = cia; | |
492 | State.regs[REG_SP] | |
493 | = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8))); | |
494 | } | |
495 | ||
496 | ||
497 | // 0110 DmAn; mov Dm,(An) | |
498 | 4.0x6,2.DM1,2.AN0:S0d:::mov | |
499 | "mov" | |
500 | *mn10300 | |
d2b02ab2 JL |
501 | // start-sanitize-am33 |
502 | *am33 | |
503 | // end-sanitize-am33 | |
7986ea13 JJ |
504 | { |
505 | // OP_60 (); | |
506 | PC = cia; | |
507 | store_word (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]); | |
508 | } | |
509 | ||
510 | ||
511 | // 1111 1000 0001 DmAn d8......; mov Dm,(d8,An) (d8 is sign-extended) | |
512 | 8.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov | |
513 | "mov" | |
514 | *mn10300 | |
d2b02ab2 JL |
515 | // start-sanitize-am33 |
516 | *am33 | |
517 | // end-sanitize-am33 | |
7986ea13 JJ |
518 | { |
519 | // OP_F81000 (); | |
520 | PC = cia; | |
521 | store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), | |
522 | State.regs[REG_D0 + DM1]); | |
523 | } | |
524 | ||
525 | ||
526 | // 1111 1010 0001 DmAn d16.....; mov Dm,(d16,An) (d16 is sign-extended.) | |
527 | 8.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov | |
528 | "mov" | |
529 | *mn10300 | |
d2b02ab2 JL |
530 | // start-sanitize-am33 |
531 | *am33 | |
532 | // end-sanitize-am33 | |
7986ea13 JJ |
533 | { |
534 | // OP_FA100000 (); | |
535 | PC = cia; | |
536 | store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))), | |
537 | State.regs[REG_D0 + DM1]); | |
538 | } | |
539 | ||
540 | ||
541 | // 1111 1100 0001 DmAn d32.....; mov Dm,(d32,An) | |
542 | 8.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov | |
543 | "mov" | |
544 | *mn10300 | |
d2b02ab2 JL |
545 | // start-sanitize-am33 |
546 | *am33 | |
547 | // end-sanitize-am33 | |
7986ea13 JJ |
548 | { |
549 | // OP_FC100000 (); | |
550 | PC = cia; | |
551 | store_word ((State.regs[REG_A0 + AN0] | |
552 | + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)), | |
553 | State.regs[REG_D0 + DM1]); | |
554 | } | |
555 | ||
556 | ||
557 | // 0100 Dm10 d8......; mov Dm,(d8,SP) (d8 is zero-extended) | |
558 | 4.0x4,2.DM1,10+8.D8:S1b:::mov | |
559 | "mov" | |
560 | *mn10300 | |
d2b02ab2 JL |
561 | // start-sanitize-am33 |
562 | *am33 | |
563 | // end-sanitize-am33 | |
7986ea13 JJ |
564 | { |
565 | // OP_4200 (); | |
566 | PC = cia; | |
567 | store_word (State.regs[REG_SP] + D8, State.regs[REG_D0 + DM1]); | |
568 | } | |
569 | ||
570 | ||
571 | // 1111 1010 1001 Dm01 d16.....; mov Dm,(d16,SP) (d16 is zero-extended.) | |
572 | 8.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov | |
573 | "mov" | |
574 | *mn10300 | |
d2b02ab2 JL |
575 | // start-sanitize-am33 |
576 | *am33 | |
577 | // end-sanitize-am33 | |
7986ea13 JJ |
578 | { |
579 | // OP_FA910000 (); | |
580 | PC = cia; | |
581 | store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B), | |
582 | State.regs[REG_D0 + DM1]); | |
583 | } | |
584 | ||
585 | ||
586 | // 1111 1100 1001 Dm01 d32.....; mov Dm,(d32,SP) | |
587 | 8.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov | |
588 | "mov" | |
589 | *mn10300 | |
d2b02ab2 JL |
590 | // start-sanitize-am33 |
591 | *am33 | |
592 | // end-sanitize-am33 | |
7986ea13 JJ |
593 | { |
594 | // OP_FC910000 (); | |
595 | PC = cia; | |
596 | store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), | |
597 | State.regs[REG_D0 + DM1]); | |
598 | } | |
599 | ||
600 | ||
601 | // 1111 0011 01Dm DiAn; mov Dm,(Di,An) | |
602 | 8.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov | |
603 | "mov" | |
604 | *mn10300 | |
d2b02ab2 JL |
605 | // start-sanitize-am33 |
606 | *am33 | |
607 | // end-sanitize-am33 | |
7986ea13 JJ |
608 | { |
609 | // OP_F340 (); | |
610 | PC = cia; | |
611 | store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]), | |
612 | State.regs[REG_D0 + DM2]); | |
613 | } | |
614 | ||
615 | ||
616 | // 0000 Dm01 abs16..., mov Dm,(abs16) (abs16 is zero-extended). | |
617 | 4.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov | |
618 | "mov" | |
619 | *mn10300 | |
d2b02ab2 JL |
620 | // start-sanitize-am33 |
621 | *am33 | |
622 | // end-sanitize-am33 | |
7986ea13 JJ |
623 | { |
624 | // OP_10000 (); | |
625 | PC = cia; | |
626 | store_word (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]); | |
627 | } | |
628 | ||
629 | ||
630 | // 1111 1100 1000 Dm01 abs32...; mov Dm,(abs32) | |
631 | 8.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov | |
632 | "mov" | |
633 | *mn10300 | |
d2b02ab2 JL |
634 | // start-sanitize-am33 |
635 | *am33 | |
636 | // end-sanitize-am33 | |
7986ea13 JJ |
637 | { |
638 | // OP_FC810000 (); | |
639 | PC = cia; | |
640 | store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), | |
641 | State.regs[REG_D0 + DM1]); | |
642 | } | |
643 | ||
644 | ||
645 | // 1111 0000 0001 AmAn; mov Am,(An) | |
646 | 8.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov | |
647 | "mov" | |
648 | *mn10300 | |
d2b02ab2 JL |
649 | // start-sanitize-am33 |
650 | *am33 | |
651 | // end-sanitize-am33 | |
7986ea13 JJ |
652 | { |
653 | // OP_F010 (); | |
654 | PC = cia; | |
655 | store_word (State.regs[REG_A0 + AN0], State.regs[REG_A0 + AM1]); | |
656 | } | |
657 | ||
658 | ||
659 | // 1111 1000 0011 AmAn d8......; mov Am,(d8,An) (d8 is sign-extended) | |
660 | 8.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov | |
661 | "mov" | |
662 | *mn10300 | |
d2b02ab2 JL |
663 | // start-sanitize-am33 |
664 | *am33 | |
665 | // end-sanitize-am33 | |
7986ea13 JJ |
666 | { |
667 | // OP_F83000 (); | |
668 | PC = cia; | |
669 | store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), | |
670 | State.regs[REG_A0 + AM1]); | |
671 | } | |
672 | ||
673 | ||
674 | // 1111 1010 0011 AmAn d16.....; mov Am,(d16,An) (d16 is sign-extended.) | |
675 | 8.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov | |
676 | "mov" | |
677 | *mn10300 | |
d2b02ab2 JL |
678 | // start-sanitize-am33 |
679 | *am33 | |
680 | // end-sanitize-am33 | |
7986ea13 JJ |
681 | { |
682 | // OP_FA300000 (); | |
683 | PC = cia; | |
684 | store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))), | |
685 | State.regs[REG_A0 + AM1]); | |
686 | } | |
687 | ||
688 | ||
689 | // 1111 1100 0011 AmAn d32.....; mov Am,(d32,An) | |
690 | 8.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov | |
691 | "mov" | |
692 | *mn10300 | |
d2b02ab2 JL |
693 | // start-sanitize-am33 |
694 | *am33 | |
695 | // end-sanitize-am33 | |
7986ea13 JJ |
696 | { |
697 | // OP_FC300000 (); | |
698 | PC = cia; | |
699 | store_word ((State.regs[REG_A0 + AN0] | |
700 | + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)), | |
701 | State.regs[REG_A0 + AM1]); | |
702 | } | |
703 | ||
704 | ||
705 | // 0100 Am11 d8......; mov Am,(d8,SP) (d8 is zero-extended) | |
706 | 4.0x4,2.AM1,11+8.D8:S1c:::mov | |
707 | "mov" | |
708 | *mn10300 | |
d2b02ab2 JL |
709 | // start-sanitize-am33 |
710 | *am33 | |
711 | // end-sanitize-am33 | |
7986ea13 JJ |
712 | { |
713 | // OP_4300 (); | |
714 | PC = cia; | |
715 | store_word (State.regs[REG_SP] + (D8), State.regs[REG_A0 + (AM1)]); | |
716 | } | |
717 | ||
718 | ||
719 | // 1111 1010 1001 Am00 d16.....; mov Am,(d16,SP) (d16 is zero-extended.) | |
720 | 8.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov | |
721 | "mov" | |
722 | *mn10300 | |
d2b02ab2 JL |
723 | // start-sanitize-am33 |
724 | *am33 | |
725 | // end-sanitize-am33 | |
7986ea13 JJ |
726 | { |
727 | // OP_FA900000 (); | |
728 | PC = cia; | |
729 | store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B), | |
730 | State.regs[REG_A0 + AM1]); | |
731 | } | |
732 | ||
733 | ||
734 | // 1111 1100 1001 Am00 d32.....; mov Am,(d32,SP) | |
735 | 8.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov | |
736 | "mov" | |
737 | *mn10300 | |
d2b02ab2 JL |
738 | // start-sanitize-am33 |
739 | *am33 | |
740 | // end-sanitize-am33 | |
7986ea13 JJ |
741 | { |
742 | // OP_FC900000 (); | |
743 | PC = cia; | |
744 | store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), | |
745 | State.regs[REG_A0 + AM1]); | |
746 | } | |
747 | ||
748 | ||
749 | // 1111 0011 11Am DiAn; mov Am,(Di,An) | |
750 | 8.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov | |
751 | "mov" | |
752 | *mn10300 | |
d2b02ab2 JL |
753 | // start-sanitize-am33 |
754 | *am33 | |
755 | // end-sanitize-am33 | |
7986ea13 JJ |
756 | { |
757 | // OP_F3C0 (); | |
758 | PC = cia; | |
759 | store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]), | |
760 | State.regs[REG_A0 + AM2]); | |
761 | } | |
762 | ||
763 | ||
764 | // 1111 1010 1000 Am00 abs16...; mov Am,(abs16) (abs16 is zero-extended) | |
765 | 8.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov | |
766 | "mov" | |
767 | *mn10300 | |
d2b02ab2 JL |
768 | // start-sanitize-am33 |
769 | *am33 | |
770 | // end-sanitize-am33 | |
7986ea13 JJ |
771 | { |
772 | // OP_FA800000 (); | |
773 | PC = cia; | |
774 | store_word (FETCH16(IMM16A, IMM16B), | |
775 | State.regs[REG_A0 + AM1]); | |
776 | } | |
777 | ||
778 | ||
779 | // 1111 1100 1000 Am00 abs32...; mov Am,(abs32) | |
780 | 8.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov | |
781 | "mov" | |
782 | *mn10300 | |
d2b02ab2 JL |
783 | // start-sanitize-am33 |
784 | *am33 | |
785 | // end-sanitize-am33 | |
7986ea13 JJ |
786 | { |
787 | // OP_FC800000 (); | |
788 | PC = cia; | |
789 | store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), | |
790 | State.regs[REG_A0 + AM1]); | |
791 | } | |
792 | ||
793 | ||
794 | // 1111 1000 1111 01An d8......; mov SP,(d8,An) (d8 is sign-extended) | |
795 | 8.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov | |
796 | "mov" | |
797 | *mn10300 | |
d2b02ab2 JL |
798 | // start-sanitize-am33 |
799 | *am33 | |
800 | // end-sanitize-am33 | |
7986ea13 JJ |
801 | { |
802 | // OP_F8F400 (); | |
803 | PC = cia; | |
804 | store_word (State.regs[REG_A0 + AN0] + EXTEND8 (D8), | |
805 | State.regs[REG_SP]); | |
806 | } | |
807 | ||
808 | ||
809 | // 0010 11Dn imm16...; mov imm16,Dn (imm16 is sign-extended) | |
810 | 4.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov | |
811 | "mov" | |
812 | *mn10300 | |
d2b02ab2 JL |
813 | // start-sanitize-am33 |
814 | *am33 | |
815 | // end-sanitize-am33 | |
7986ea13 JJ |
816 | { |
817 | // OP_2C0000 (); | |
818 | unsigned long value; | |
819 | ||
820 | PC = cia; | |
821 | value = EXTEND16 (FETCH16(IMM16A, IMM16B)); | |
822 | State.regs[REG_D0 + DN0] = value; | |
823 | } | |
824 | ||
825 | ||
826 | // 1111 1100 1100 11Dn imm32...; mov imm32,Dn | |
827 | 8.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov | |
828 | "mov" | |
829 | *mn10300 | |
d2b02ab2 JL |
830 | // start-sanitize-am33 |
831 | *am33 | |
832 | // end-sanitize-am33 | |
7986ea13 JJ |
833 | { |
834 | // OP_FCCC0000 (); | |
835 | unsigned long value; | |
836 | ||
837 | PC = cia; | |
838 | value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); | |
839 | State.regs[REG_D0 + DN0] = value; | |
840 | } | |
841 | ||
842 | ||
843 | // 0010 01An imm16...; mov imm16,An (imm16 is zero-extended) | |
844 | 4.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov | |
845 | "mov" | |
846 | *mn10300 | |
d2b02ab2 JL |
847 | // start-sanitize-am33 |
848 | *am33 | |
849 | // end-sanitize-am33 | |
7986ea13 JJ |
850 | { |
851 | // OP_240000 (); | |
852 | unsigned long value; | |
853 | ||
854 | PC = cia; | |
855 | value = FETCH16(IMM16A, IMM16B); | |
856 | State.regs[REG_A0 + AN0] = value; | |
857 | } | |
858 | ||
859 | ||
860 | // 1111 1100 1101 11An imm32...; mov imm32,An | |
861 | 8.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov | |
862 | "mov" | |
863 | *mn10300 | |
d2b02ab2 JL |
864 | // start-sanitize-am33 |
865 | *am33 | |
866 | // end-sanitize-am33 | |
7986ea13 JJ |
867 | { |
868 | // OP_FCDC0000 (); | |
869 | PC = cia; | |
870 | State.regs[REG_A0 + AN0] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); | |
871 | } | |
872 | ||
873 | ||
874 | // 1111 0000 0100 DnAm; movbu (Am),Dn | |
875 | 8.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu | |
876 | "movbu" | |
877 | *mn10300 | |
d2b02ab2 JL |
878 | // start-sanitize-am33 |
879 | *am33 | |
880 | // end-sanitize-am33 | |
7986ea13 JJ |
881 | { |
882 | // OP_F040 (); | |
883 | PC = cia; | |
884 | State.regs[REG_D0 + DN1] | |
885 | = load_byte (State.regs[REG_A0 + AM0]); | |
886 | } | |
887 | ||
888 | ||
889 | // 1111 1000 0100 DnAm d8......; movbu (d8,Am),Dn (d8 is sign-extended) | |
890 | 8.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu | |
891 | "movbu" | |
892 | *mn10300 | |
d2b02ab2 JL |
893 | // start-sanitize-am33 |
894 | *am33 | |
895 | // end-sanitize-am33 | |
7986ea13 JJ |
896 | { |
897 | // OP_F84000 (); | |
898 | PC = cia; | |
899 | State.regs[REG_D0 + DN1] | |
900 | = load_byte ((State.regs[REG_A0 + AM0] + EXTEND8 (D8))); | |
901 | } | |
902 | ||
903 | ||
904 | // 1111 1010 0100 DnAm d16.....; movbu (d16,Am),Dn (d16 is sign-extended.) | |
905 | 8.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu | |
906 | "movbu" | |
907 | *mn10300 | |
d2b02ab2 JL |
908 | // start-sanitize-am33 |
909 | *am33 | |
910 | // end-sanitize-am33 | |
7986ea13 JJ |
911 | { |
912 | // OP_FA400000 (); | |
913 | PC = cia; | |
914 | State.regs[REG_D0 + DN1] | |
915 | = load_byte ((State.regs[REG_A0 + AM0] | |
916 | + EXTEND16 (FETCH16(D16A, D16B)))); | |
917 | } | |
918 | ||
919 | ||
920 | // 1111 1100 0100 DnAm d32.....; movbu (d32,Am),Dn | |
921 | 8.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu | |
922 | "movbu" | |
923 | *mn10300 | |
d2b02ab2 JL |
924 | // start-sanitize-am33 |
925 | *am33 | |
926 | // end-sanitize-am33 | |
7986ea13 JJ |
927 | { |
928 | // OP_FC400000 (); | |
929 | PC = cia; | |
930 | State.regs[REG_D0 + DN1] | |
931 | = load_byte ((State.regs[REG_A0 + AM0] | |
932 | + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D))); | |
933 | } | |
934 | ||
935 | ||
936 | // 1111 1000 1011 10Dn d8......; movbu (d8,SP),Dn (d8 is zero-extended) | |
937 | 8.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu | |
938 | "movbu" | |
939 | *mn10300 | |
d2b02ab2 JL |
940 | // start-sanitize-am33 |
941 | *am33 | |
942 | // end-sanitize-am33 | |
7986ea13 JJ |
943 | { |
944 | // OP_F8B800 (); | |
945 | PC = cia; | |
946 | State.regs[REG_D0 + DN0] | |
947 | = load_byte ((State.regs[REG_SP] + (D8))); | |
948 | } | |
949 | ||
950 | ||
951 | // 1111 1010 1011 10Dn d16.....; movbu (d16,SP),Dn (d16 is zero-extended.) | |
952 | 8.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu | |
953 | "movbu" | |
954 | *mn10300 | |
d2b02ab2 JL |
955 | // start-sanitize-am33 |
956 | *am33 | |
957 | // end-sanitize-am33 | |
7986ea13 JJ |
958 | { |
959 | // OP_FAB80000 (); | |
960 | PC = cia; | |
961 | State.regs[REG_D0 + DN0] | |
962 | = load_byte ((State.regs[REG_SP] | |
963 | + FETCH16(IMM16A, IMM16B))); | |
964 | } | |
965 | ||
966 | ||
967 | // 1111 1100 1011 10Dn d32.....; movbu (d32,SP),Dn | |
968 | 8.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu | |
969 | "movbu" | |
970 | *mn10300 | |
d2b02ab2 JL |
971 | // start-sanitize-am33 |
972 | *am33 | |
973 | // end-sanitize-am33 | |
7986ea13 JJ |
974 | { |
975 | // OP_FCB80000 (); | |
976 | PC = cia; | |
977 | State.regs[REG_D0 + DN0] | |
978 | = load_byte (State.regs[REG_SP] | |
979 | + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)); | |
980 | } | |
981 | ||
982 | ||
983 | // 1111 0100 00Dn DiAm; movbu (Di,Am),Dn | |
984 | 8.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu | |
985 | "movbu" | |
986 | *mn10300 | |
d2b02ab2 JL |
987 | // start-sanitize-am33 |
988 | *am33 | |
989 | // end-sanitize-am33 | |
7986ea13 JJ |
990 | { |
991 | // OP_F400 (); | |
992 | PC = cia; | |
993 | State.regs[REG_D0 + DN2] | |
994 | = load_byte ((State.regs[REG_A0 + AM0] | |
995 | + State.regs[REG_D0 + DI])); | |
996 | } | |
997 | ||
998 | ||
999 | // 0011 01Dn abs16...; movbu (abs16),Dn (abs16 is zero-extended) | |
1000 | 4.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu | |
1001 | "movbu" | |
1002 | *mn10300 | |
d2b02ab2 JL |
1003 | // start-sanitize-am33 |
1004 | *am33 | |
1005 | // end-sanitize-am33 | |
7986ea13 JJ |
1006 | { |
1007 | // OP_340000 (); | |
1008 | PC = cia; | |
1009 | State.regs[REG_D0 + DN0] = load_byte (FETCH16(IMM16A, IMM16B)); | |
1010 | } | |
1011 | ||
1012 | ||
1013 | // 1111 1100 1010 10Dn abs32...; movbu (abs32),Dn | |
1014 | 8.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu | |
1015 | "movbu" | |
1016 | *mn10300 | |
d2b02ab2 JL |
1017 | // start-sanitize-am33 |
1018 | *am33 | |
1019 | // end-sanitize-am33 | |
7986ea13 JJ |
1020 | { |
1021 | // OP_FCA80000 (); | |
1022 | PC = cia; | |
1023 | State.regs[REG_D0 + DN0] | |
1024 | = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)); | |
1025 | } | |
1026 | ||
1027 | ||
1028 | // 1111 0000 0101 DmAn; movbu Dm,(An) | |
1029 | 8.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu | |
1030 | "movbu" | |
1031 | *mn10300 | |
d2b02ab2 JL |
1032 | // start-sanitize-am33 |
1033 | *am33 | |
1034 | // end-sanitize-am33 | |
7986ea13 JJ |
1035 | { |
1036 | // OP_F050 (); | |
1037 | PC = cia; | |
1038 | store_byte (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]); | |
1039 | } | |
1040 | ||
1041 | ||
1042 | // 1111 1000 0101 DmAn d8......; movbu Dm,(d8,An) (d8 is sign-extended) | |
1043 | 8.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu | |
1044 | "movbu" | |
1045 | *mn10300 | |
d2b02ab2 JL |
1046 | // start-sanitize-am33 |
1047 | *am33 | |
1048 | // end-sanitize-am33 | |
7986ea13 JJ |
1049 | { |
1050 | // OP_F85000 (); | |
1051 | PC = cia; | |
1052 | store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), | |
1053 | State.regs[REG_D0 + DM1]); | |
1054 | } | |
1055 | ||
1056 | ||
1057 | // 1111 1010 0101 DmAn d16.....; movbu Dm,(d16,An) (d16 is sign-extended.) | |
1058 | 8.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu | |
1059 | "movbu" | |
1060 | *mn10300 | |
d2b02ab2 JL |
1061 | // start-sanitize-am33 |
1062 | *am33 | |
1063 | // end-sanitize-am33 | |
7986ea13 JJ |
1064 | { |
1065 | // OP_FA500000 (); | |
1066 | PC = cia; | |
1067 | store_byte ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))), | |
1068 | State.regs[REG_D0 + DM1]); | |
1069 | } | |
1070 | ||
1071 | ||
1072 | // 1111 1100 0101 DmAn d32.....; movbu Dm,(d32,An) | |
1073 | 8.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu | |
1074 | "movbu" | |
1075 | *mn10300 | |
d2b02ab2 JL |
1076 | // start-sanitize-am33 |
1077 | *am33 | |
1078 | // end-sanitize-am33 | |
7986ea13 JJ |
1079 | { |
1080 | // OP_FC500000 (); | |
1081 | PC = cia; | |
1082 | store_byte ((State.regs[REG_A0 + AN0] | |
1083 | + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)), | |
1084 | State.regs[REG_D0 + DM1]); | |
1085 | } | |
1086 | ||
1087 | ||
1088 | // 1111 1000 1001 Dm10 d8......; movbu Dm,(d8,SP) (d8 is zero-extended) | |
1089 | 8.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu | |
1090 | "movbu" | |
1091 | *mn10300 | |
d2b02ab2 JL |
1092 | // start-sanitize-am33 |
1093 | *am33 | |
1094 | // end-sanitize-am33 | |
7986ea13 JJ |
1095 | { |
1096 | // OP_F89200 (); | |
1097 | PC = cia; | |
1098 | store_byte (State.regs[REG_SP] + (D8), State.regs[REG_D0 + DM1]); | |
1099 | } | |
1100 | ||
1101 | ||
1102 | // 1111 1010 1001 Dm10 d16.....; movbu Dm,(d16,SP) (d16 is zero-extended.) | |
1103 | 8.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu | |
1104 | "movbu" | |
1105 | *mn10300 | |
d2b02ab2 JL |
1106 | // start-sanitize-am33 |
1107 | *am33 | |
1108 | // end-sanitize-am33 | |
7986ea13 JJ |
1109 | { |
1110 | // OP_FA920000 (); | |
1111 | PC = cia; | |
1112 | store_byte (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B), | |
1113 | State.regs[REG_D0 + DM1]); | |
1114 | } | |
1115 | ||
1116 | ||
1117 | // 1111 1100 1001 Dm10 d32.....; movbu Dm,(d32,SP) | |
1118 | 8.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu | |
1119 | "movbu" | |
1120 | *mn10300 | |
d2b02ab2 JL |
1121 | // start-sanitize-am33 |
1122 | *am33 | |
1123 | // end-sanitize-am33 | |
7986ea13 JJ |
1124 | { |
1125 | // OP_FC920000 (); | |
1126 | PC = cia; | |
1127 | store_byte (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), | |
1128 | State.regs[REG_D0 + DM1]); | |
1129 | } | |
1130 | ||
1131 | ||
1132 | // 1111 0100 01Dm DiAn; movbu Dm,(Di,An) | |
1133 | 8.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu | |
1134 | "movbu" | |
1135 | *mn10300 | |
d2b02ab2 JL |
1136 | // start-sanitize-am33 |
1137 | *am33 | |
1138 | // end-sanitize-am33 | |
7986ea13 JJ |
1139 | { |
1140 | // OP_F440 (); | |
1141 | PC = cia; | |
1142 | store_byte ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]), | |
1143 | State.regs[REG_D0 + DM2]); | |
1144 | } | |
1145 | ||
1146 | ||
1147 | // 0000 Dm10 abs16...; movbu Dm,(abs16) (abs16 is zero-extended) | |
1148 | 4.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu | |
1149 | "movbu" | |
1150 | *mn10300 | |
d2b02ab2 JL |
1151 | // start-sanitize-am33 |
1152 | *am33 | |
1153 | // end-sanitize-am33 | |
7986ea13 JJ |
1154 | { |
1155 | // OP_20000 (); | |
1156 | PC = cia; | |
1157 | store_byte (FETCH16(IMM16A, IMM16B), | |
1158 | State.regs[REG_D0 + DM1]); | |
1159 | } | |
1160 | ||
1161 | ||
1162 | // 1111 1100 1000 Dm10 abs32...; movbu Dm,(abs32) | |
1163 | 8.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu | |
1164 | "movbu" | |
1165 | *mn10300 | |
d2b02ab2 JL |
1166 | // start-sanitize-am33 |
1167 | *am33 | |
1168 | // end-sanitize-am33 | |
7986ea13 JJ |
1169 | { |
1170 | // OP_FC820000 (); | |
1171 | PC = cia; | |
1172 | store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), | |
1173 | State.regs[REG_D0 + DM1]); | |
1174 | } | |
1175 | ||
1176 | ||
1177 | // 1111 0000 0110 DnAm; movhu (Am),Dn | |
1178 | 8.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu | |
1179 | "movhu" | |
1180 | *mn10300 | |
d2b02ab2 JL |
1181 | // start-sanitize-am33 |
1182 | *am33 | |
1183 | // end-sanitize-am33 | |
7986ea13 JJ |
1184 | { |
1185 | // OP_F060 (); | |
1186 | PC = cia; | |
1187 | State.regs[REG_D0 + DN1] | |
1188 | = load_half (State.regs[REG_A0 + AM0]); | |
1189 | } | |
1190 | ||
1191 | ||
1192 | // 1111 1000 0110 DnAm d8......; movhu (d8,Am),Dn (d8 is sign-extended) | |
1193 | 8.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu | |
1194 | "movhu" | |
1195 | *mn10300 | |
d2b02ab2 JL |
1196 | // start-sanitize-am33 |
1197 | *am33 | |
1198 | // end-sanitize-am33 | |
7986ea13 JJ |
1199 | { |
1200 | // OP_F86000 (); | |
1201 | PC = cia; | |
1202 | State.regs[REG_D0 + DN1] | |
1203 | = load_half ((State.regs[REG_A0 + AM0] + EXTEND8 (D8))); | |
1204 | } | |
1205 | ||
1206 | ||
1207 | // 1111 1010 0110 DnAm d16.....; movhu (d16,Am),Dn (d16 is sign-extended.) | |
1208 | 8.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu | |
1209 | "movhu" | |
1210 | *mn10300 | |
d2b02ab2 JL |
1211 | // start-sanitize-am33 |
1212 | *am33 | |
1213 | // end-sanitize-am33 | |
7986ea13 JJ |
1214 | { |
1215 | // OP_FA600000 (); | |
1216 | PC = cia; | |
1217 | State.regs[REG_D0 + DN1] | |
1218 | = load_half ((State.regs[REG_A0 + AM0] | |
1219 | + EXTEND16 (FETCH16(D16A, D16B)))); | |
1220 | } | |
1221 | ||
1222 | ||
1223 | // 1111 1100 0110 DnAm d32.....; movhu (d32,Am),Dn | |
1224 | 8.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu | |
1225 | "movhu" | |
1226 | *mn10300 | |
d2b02ab2 JL |
1227 | // start-sanitize-am33 |
1228 | *am33 | |
1229 | // end-sanitize-am33 | |
7986ea13 JJ |
1230 | { |
1231 | // OP_FC600000 (); | |
1232 | PC = cia; | |
1233 | State.regs[REG_D0 + DN1] | |
1234 | = load_half ((State.regs[REG_A0 + AM0] | |
1235 | + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D))); | |
1236 | } | |
1237 | ||
1238 | ||
1239 | // 1111 1000 1011 11Dn d8.....; movhu (d8,SP),Dn (d8 is zero-extended) | |
1240 | 8.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu | |
1241 | "movhu" | |
1242 | *mn10300 | |
d2b02ab2 JL |
1243 | // start-sanitize-am33 |
1244 | *am33 | |
1245 | // end-sanitize-am33 | |
7986ea13 JJ |
1246 | { |
1247 | // OP_F8BC00 (); | |
1248 | PC = cia; | |
1249 | State.regs[REG_D0 + DN0] | |
1250 | = load_half ((State.regs[REG_SP] + (D8))); | |
1251 | } | |
1252 | ||
1253 | ||
1254 | // 1111 1010 1011 11Dn d16.....; movhu (d16,SP),Dn (d16 is zero-extended.) | |
1255 | 8.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu | |
1256 | "movhu" | |
1257 | *mn10300 | |
d2b02ab2 JL |
1258 | // start-sanitize-am33 |
1259 | *am33 | |
1260 | // end-sanitize-am33 | |
7986ea13 JJ |
1261 | { |
1262 | // OP_FABC0000 (); | |
1263 | PC = cia; | |
1264 | State.regs[REG_D0 + DN0] | |
1265 | = load_half ((State.regs[REG_SP] + FETCH16(IMM16A, IMM16B))); | |
1266 | } | |
1267 | ||
1268 | ||
1269 | // 1111 1100 1011 11Dn d32.....; movhu (d32,SP),Dn | |
1270 | 8.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu | |
1271 | "movhu" | |
1272 | *mn10300 | |
d2b02ab2 JL |
1273 | // start-sanitize-am33 |
1274 | *am33 | |
1275 | // end-sanitize-am33 | |
7986ea13 JJ |
1276 | { |
1277 | // OP_FCBC0000 (); | |
1278 | PC = cia; | |
1279 | State.regs[REG_D0 + DN0] | |
1280 | = load_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)); | |
1281 | } | |
1282 | ||
1283 | ||
1284 | // 1111 0100 10Dn DiAm; movhu (Di,Am),Dn | |
1285 | 8.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu | |
1286 | "movhu" | |
1287 | *mn10300 | |
d2b02ab2 JL |
1288 | // start-sanitize-am33 |
1289 | *am33 | |
1290 | // end-sanitize-am33 | |
7986ea13 JJ |
1291 | { |
1292 | // OP_F480 (); | |
1293 | PC = cia; | |
1294 | State.regs[REG_D0 + DN2] | |
1295 | = load_half ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI])); | |
1296 | } | |
1297 | ||
1298 | ||
1299 | // 0011 10Dn abs16...; movhu (abs16),Dn (abs16 is zero-extended) | |
1300 | 4.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu | |
1301 | "movhu" | |
1302 | *mn10300 | |
d2b02ab2 JL |
1303 | // start-sanitize-am33 |
1304 | *am33 | |
1305 | // end-sanitize-am33 | |
7986ea13 JJ |
1306 | { |
1307 | // OP_380000 (); | |
1308 | PC = cia; | |
1309 | State.regs[REG_D0 + DN0] = load_half (FETCH16(IMM16A, IMM16B)); | |
1310 | } | |
1311 | ||
1312 | ||
1313 | // 1111 1100 1010 11Dn abs32...; movhu (abs32),Dn | |
1314 | 8.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu | |
1315 | "movhu" | |
1316 | *mn10300 | |
d2b02ab2 JL |
1317 | // start-sanitize-am33 |
1318 | *am33 | |
1319 | // end-sanitize-am33 | |
7986ea13 JJ |
1320 | { |
1321 | // OP_FCAC0000 (); | |
1322 | PC = cia; | |
1323 | State.regs[REG_D0 + DN0] | |
1324 | = load_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)); | |
1325 | } | |
1326 | ||
1327 | ||
1328 | // 1111 0000 0111 DmAn; movhu Dm,(An) | |
1329 | 8.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu | |
1330 | "movhu" | |
1331 | *mn10300 | |
d2b02ab2 JL |
1332 | // start-sanitize-am33 |
1333 | *am33 | |
1334 | // end-sanitize-am33 | |
7986ea13 JJ |
1335 | { |
1336 | // OP_F070 (); | |
1337 | PC = cia; | |
1338 | store_half (State.regs[REG_A0 + AN0], | |
1339 | State.regs[REG_D0 + DM1]); | |
1340 | } | |
1341 | ||
1342 | ||
1343 | // 1111 1000 0111 DmAn d8......; movhu Dm,(d8,An) (d8 is sign-extended) | |
1344 | 8.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu | |
1345 | "movhu" | |
1346 | *mn10300 | |
d2b02ab2 JL |
1347 | // start-sanitize-am33 |
1348 | *am33 | |
1349 | // end-sanitize-am33 | |
7986ea13 JJ |
1350 | { |
1351 | // OP_F87000 (); | |
1352 | PC = cia; | |
1353 | store_half ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), | |
1354 | State.regs[REG_D0 + DM1]); | |
1355 | } | |
1356 | ||
1357 | ||
1358 | // 1111 1010 0111 DnAm d16.....; movhu Dm,(d16,An) (d16 is sign-extended.) | |
1359 | 8.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu | |
1360 | "movhu" | |
1361 | *mn10300 | |
d2b02ab2 JL |
1362 | // start-sanitize-am33 |
1363 | *am33 | |
1364 | // end-sanitize-am33 | |
7986ea13 JJ |
1365 | { |
1366 | // OP_FA700000 (); | |
1367 | PC = cia; | |
1368 | store_half ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))), | |
1369 | State.regs[REG_D0 + DM1]); | |
1370 | } | |
1371 | ||
1372 | ||
1373 | // 1111 1100 0111 DmAn d32.....; movhu Dm,(d32,An) | |
1374 | 8.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu | |
1375 | "movhu" | |
1376 | *mn10300 | |
d2b02ab2 JL |
1377 | // start-sanitize-am33 |
1378 | *am33 | |
1379 | // end-sanitize-am33 | |
7986ea13 JJ |
1380 | { |
1381 | // OP_FC700000 (); | |
1382 | PC = cia; | |
1383 | store_half ((State.regs[REG_A0 + AN0] | |
1384 | + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)), | |
1385 | State.regs[REG_D0 + DM1]); | |
1386 | } | |
1387 | ||
1388 | ||
1389 | // 1111 1000 1001 Dm11 d8....; movhu Dm,(d8,SP) (d8 is zero-extended) | |
1390 | 8.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu | |
1391 | "movhu" | |
1392 | *mn10300 | |
d2b02ab2 JL |
1393 | // start-sanitize-am33 |
1394 | *am33 | |
1395 | // end-sanitize-am33 | |
7986ea13 JJ |
1396 | { |
1397 | // OP_F89300 (); | |
1398 | PC = cia; | |
1399 | store_half (State.regs[REG_SP] + (D8), | |
1400 | State.regs[REG_D0 + DM1]); | |
1401 | } | |
1402 | ||
1403 | ||
1404 | // 1111 1010 1001 Dm11 d16.....; movhu Dm,(d16,SP) (d16 is zero-extended.) | |
1405 | 8.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu | |
1406 | "movhu" | |
1407 | *mn10300 | |
d2b02ab2 JL |
1408 | // start-sanitize-am33 |
1409 | *am33 | |
1410 | // end-sanitize-am33 | |
7986ea13 JJ |
1411 | { |
1412 | // OP_FA930000 (); | |
1413 | PC = cia; | |
1414 | store_half (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B), | |
1415 | State.regs[REG_D0 + DM1]); | |
1416 | } | |
1417 | ||
1418 | ||
1419 | // 1111 1100 1001 Dm11 d32.....; movhu Dm,(d32,SP) | |
1420 | 8.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu | |
1421 | "movhu" | |
1422 | *mn10300 | |
d2b02ab2 JL |
1423 | // start-sanitize-am33 |
1424 | *am33 | |
1425 | // end-sanitize-am33 | |
7986ea13 JJ |
1426 | { |
1427 | // OP_FC930000 (); | |
1428 | PC = cia; | |
1429 | store_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), | |
1430 | State.regs[REG_D0 + DM1]); | |
1431 | } | |
1432 | ||
1433 | ||
1434 | // 1111 0100 11Dm DiAn; movhu Dm,(Di,An) | |
1435 | 8.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu | |
1436 | "movhu" | |
1437 | *mn10300 | |
d2b02ab2 JL |
1438 | // start-sanitize-am33 |
1439 | *am33 | |
1440 | // end-sanitize-am33 | |
7986ea13 JJ |
1441 | { |
1442 | // OP_F4C0 (); | |
1443 | PC = cia; | |
1444 | store_half ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]), | |
1445 | State.regs[REG_D0 + DM2]); | |
1446 | } | |
1447 | ||
1448 | ||
1449 | // 0000 Dm11 abs16...; movhu Dm,(abs16) (abs16 is zero-extended) | |
1450 | 4.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu | |
1451 | "movhu" | |
1452 | *mn10300 | |
d2b02ab2 JL |
1453 | // start-sanitize-am33 |
1454 | *am33 | |
1455 | // end-sanitize-am33 | |
7986ea13 JJ |
1456 | { |
1457 | // OP_30000 (); | |
1458 | PC = cia; | |
1459 | store_half (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]); | |
1460 | } | |
1461 | ||
1462 | ||
1463 | // 1111 1100 1000 Dm11 abs32...; movhu Dm,(abs32) | |
1464 | 8.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu | |
1465 | "movhu" | |
1466 | *mn10300 | |
d2b02ab2 JL |
1467 | // start-sanitize-am33 |
1468 | *am33 | |
1469 | // end-sanitize-am33 | |
7986ea13 JJ |
1470 | { |
1471 | // OP_FC830000 (); | |
1472 | PC = cia; | |
1473 | store_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), | |
1474 | State.regs[REG_D0 + DM1]); | |
1475 | } | |
1476 | ||
1477 | ||
1478 | // 1111 0010 1101 00Dn; ext Dn | |
1479 | 8.0xf2+4.0xd,00,2.DN0:D0:::ext | |
1480 | "ext" | |
1481 | *mn10300 | |
d2b02ab2 JL |
1482 | // start-sanitize-am33 |
1483 | *am33 | |
1484 | // end-sanitize-am33 | |
7986ea13 JJ |
1485 | { |
1486 | // OP_F2D0 (); | |
1487 | PC = cia; | |
1488 | if (State.regs[REG_D0 + DN0] & 0x80000000) | |
1489 | State.regs[REG_MDR] = -1; | |
1490 | else | |
1491 | State.regs[REG_MDR] = 0; | |
1492 | } | |
1493 | ||
1494 | ||
1495 | // 0001 00Dn; extb Dn | |
1496 | 4.0x1,00,2.DN0:S0:::extb | |
1497 | "extb" | |
1498 | *mn10300 | |
d2b02ab2 JL |
1499 | // start-sanitize-am33 |
1500 | *am33 | |
1501 | // end-sanitize-am33 | |
7986ea13 JJ |
1502 | { |
1503 | // OP_10 (); | |
1504 | PC = cia; | |
1505 | State.regs[REG_D0 + DN0] = EXTEND8 (State.regs[REG_D0 + DN0]); | |
1506 | } | |
1507 | ||
1508 | ||
1509 | // 0001 01Dn; extbu Dn | |
1510 | 4.0x1,01,2.DN0:S0:::extbu | |
1511 | "extbu" | |
1512 | *mn10300 | |
d2b02ab2 JL |
1513 | // start-sanitize-am33 |
1514 | *am33 | |
1515 | // end-sanitize-am33 | |
7986ea13 JJ |
1516 | { |
1517 | // OP_14 (); | |
1518 | PC = cia; | |
1519 | State.regs[REG_D0 + DN0] &= 0xff; | |
1520 | } | |
1521 | ||
1522 | ||
1523 | // 0001 10Dn; exth Dn | |
1524 | 4.0x1,10,2.DN0:S0:::exth | |
1525 | "exth" | |
1526 | *mn10300 | |
d2b02ab2 JL |
1527 | // start-sanitize-am33 |
1528 | *am33 | |
1529 | // end-sanitize-am33 | |
7986ea13 JJ |
1530 | { |
1531 | // OP_18 (); | |
1532 | PC = cia; | |
1533 | State.regs[REG_D0 + DN0] = EXTEND16 (State.regs[REG_D0 + DN0]); | |
1534 | } | |
1535 | ||
1536 | ||
1537 | // 0001 11Dn; exthu Dn | |
1538 | 4.0x1,11,2.DN0:S0:::exthu | |
1539 | "exthu" | |
1540 | *mn10300 | |
d2b02ab2 JL |
1541 | // start-sanitize-am33 |
1542 | *am33 | |
1543 | // end-sanitize-am33 | |
7986ea13 JJ |
1544 | { |
1545 | // OP_1C (); | |
1546 | PC = cia; | |
1547 | State.regs[REG_D0 + DN0] &= 0xffff; | |
1548 | } | |
1549 | ||
1550 | ||
7986ea13 JJ |
1551 | // 0000 Dn00; clr Dn |
1552 | 4.0x0,2.DN1,00:S0:::clr | |
1553 | "clr" | |
1554 | *mn10300 | |
d2b02ab2 JL |
1555 | // start-sanitize-am33 |
1556 | *am33 | |
1557 | // end-sanitize-am33 | |
7986ea13 JJ |
1558 | { |
1559 | // OP_0 (); | |
1560 | PC = cia; | |
1561 | State.regs[REG_D0 + DN1] = 0; | |
1562 | ||
1563 | PSW |= PSW_Z; | |
1564 | PSW &= ~(PSW_V | PSW_C | PSW_N); | |
1565 | } | |
1566 | ||
1567 | ||
1568 | // 1110 DmDn; add Dm,Dn | |
1569 | 4.0xe,2.DM1,2.DN0:S0:::add | |
1570 | "add" | |
1571 | *mn10300 | |
d2b02ab2 JL |
1572 | // start-sanitize-am33 |
1573 | *am33 | |
1574 | // end-sanitize-am33 | |
7986ea13 JJ |
1575 | { |
1576 | // OP_E0 (); | |
1577 | PC = cia; | |
1578 | genericAdd(State.regs[REG_D0 + DM1], REG_D0 + DN0); | |
1579 | } | |
1580 | ||
1581 | // 1111 0001 0110 DmAn; add Dm,An | |
1582 | 8.0xf1+4.0x6,2.DM1,2.AN0:D0:::add | |
1583 | "add" | |
1584 | *mn10300 | |
d2b02ab2 JL |
1585 | // start-sanitize-am33 |
1586 | *am33 | |
1587 | // end-sanitize-am33 | |
7986ea13 JJ |
1588 | { |
1589 | // OP_F160 (); | |
7986ea13 JJ |
1590 | PC = cia; |
1591 | genericAdd(State.regs[REG_D0 + DM1], REG_A0 + AN0); | |
1592 | } | |
1593 | ||
1594 | ||
1595 | // 1111 0001 0101 AmDn; add Am,Dn | |
1596 | 8.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add | |
1597 | "add" | |
1598 | *mn10300 | |
d2b02ab2 JL |
1599 | // start-sanitize-am33 |
1600 | *am33 | |
1601 | // end-sanitize-am33 | |
7986ea13 JJ |
1602 | { |
1603 | // OP_F150 (); | |
1604 | PC = cia; | |
1605 | genericAdd(State.regs[REG_A0 + AM1], REG_D0 + DN0); | |
1606 | } | |
1607 | ||
1608 | ||
1609 | // 1111 0001 0111 AmAn; add Am,An | |
1610 | 8.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add | |
1611 | "add" | |
1612 | *mn10300 | |
d2b02ab2 JL |
1613 | // start-sanitize-am33 |
1614 | *am33 | |
1615 | // end-sanitize-am33 | |
7986ea13 JJ |
1616 | { |
1617 | // OP_F170 (); | |
1618 | PC = cia; | |
1619 | genericAdd(State.regs[REG_A0 + AM1], REG_A0 + AN0); | |
1620 | } | |
1621 | ||
1622 | ||
1623 | // 0010 10Dn imm8....; add imm8,Dn (imm8 is sign-extended) | |
1624 | 4.0x2,10,2.DN0+8.IMM8:S1:::add | |
1625 | "add" | |
1626 | *mn10300 | |
d2b02ab2 JL |
1627 | // start-sanitize-am33 |
1628 | *am33 | |
1629 | // end-sanitize-am33 | |
7986ea13 JJ |
1630 | { |
1631 | // OP_2800 (); | |
1632 | PC = cia; | |
1633 | genericAdd(EXTEND8(IMM8), REG_D0 + DN0); | |
1634 | } | |
1635 | ||
1636 | ||
1637 | // 1111 1010 1100 00Dn imm16...; add imm16,Dn | |
1638 | 8.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add | |
1639 | "add" | |
1640 | *mn10300 | |
d2b02ab2 JL |
1641 | // start-sanitize-am33 |
1642 | *am33 | |
1643 | // end-sanitize-am33 | |
7986ea13 JJ |
1644 | { |
1645 | // OP_FAC00000 (); | |
1646 | PC = cia; | |
1647 | genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_D0 + DN0); | |
1648 | } | |
1649 | ||
1650 | ||
1651 | // 1111 1100 1100 00Dn imm32...; add imm32,Dn | |
1652 | 8.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add | |
1653 | "add" | |
1654 | *mn10300 | |
d2b02ab2 JL |
1655 | // start-sanitize-am33 |
1656 | *am33 | |
1657 | // end-sanitize-am33 | |
7986ea13 JJ |
1658 | { |
1659 | // OP_FCC00000 (); | |
1660 | PC = cia; | |
1661 | genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0); | |
1662 | } | |
1663 | ||
1664 | ||
1665 | // 0010 00An imm8....; add imm8,An (imm8 is sign-extended) | |
1666 | 4.0x2,00,2.AN0+8.IMM8:S1a:::add | |
1667 | "add" | |
1668 | *mn10300 | |
d2b02ab2 JL |
1669 | // start-sanitize-am33 |
1670 | *am33 | |
1671 | // end-sanitize-am33 | |
7986ea13 JJ |
1672 | { |
1673 | // OP_2000 (); | |
1674 | PC = cia; | |
1675 | genericAdd(EXTEND8(IMM8), REG_A0 + AN0); | |
1676 | } | |
1677 | ||
1678 | ||
1679 | // 1111 1010 1101 00An imm16...; add imm16,An (imm16 is sign-extended.) | |
1680 | 8.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add | |
1681 | "add" | |
1682 | *mn10300 | |
d2b02ab2 JL |
1683 | // start-sanitize-am33 |
1684 | *am33 | |
1685 | // end-sanitize-am33 | |
7986ea13 JJ |
1686 | { |
1687 | // OP_FAD00000 (); | |
1688 | PC = cia; | |
1689 | genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_A0 + AN0); | |
1690 | } | |
1691 | ||
1692 | ||
1693 | // 1111 1100 1101 00An imm32...; add imm32,An | |
1694 | 8.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add | |
1695 | "add" | |
1696 | *mn10300 | |
d2b02ab2 JL |
1697 | // start-sanitize-am33 |
1698 | *am33 | |
1699 | // end-sanitize-am33 | |
7986ea13 JJ |
1700 | { |
1701 | // OP_FCD00000 (); | |
1702 | PC = cia; | |
1703 | genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0); | |
1704 | } | |
1705 | ||
1706 | ||
1707 | // 1111 1000 1111 1110 imm8....; add imm8,SP (imm8 is sign-extended.) | |
1708 | 8.0xf8+8.0xfe+8.IMM8:D1:::add | |
1709 | "add" | |
1710 | *mn10300 | |
d2b02ab2 JL |
1711 | // start-sanitize-am33 |
1712 | *am33 | |
1713 | // end-sanitize-am33 | |
7986ea13 JJ |
1714 | { |
1715 | // OP_F8FE00 (); | |
1716 | unsigned long imm; | |
1717 | ||
1718 | // Note: no PSW changes. | |
1719 | PC = cia; | |
1720 | imm = EXTEND8 (IMM8); | |
1721 | State.regs[REG_SP] += imm; | |
1722 | } | |
1723 | ||
1724 | ||
1725 | // 1111 1010 1111 1110 imm16...; add imm16,SP (imm16 is sign-extended.) | |
1726 | 8.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add | |
1727 | "add" | |
1728 | *mn10300 | |
d2b02ab2 JL |
1729 | // start-sanitize-am33 |
1730 | *am33 | |
1731 | // end-sanitize-am33 | |
7986ea13 JJ |
1732 | { |
1733 | // OP_FAFE0000 (); | |
1734 | unsigned long imm; | |
1735 | ||
1736 | // Note: no PSW changes. | |
1737 | PC = cia; | |
1738 | imm = EXTEND16 (FETCH16(IMM16A, IMM16B)); | |
1739 | State.regs[REG_SP] += imm; | |
1740 | } | |
1741 | ||
1742 | ||
1743 | // 1111 1100 1111 1110 imm32...; add imm32,SP | |
1744 | 8.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add | |
1745 | "add" | |
1746 | *mn10300 | |
d2b02ab2 JL |
1747 | // start-sanitize-am33 |
1748 | *am33 | |
1749 | // end-sanitize-am33 | |
7986ea13 JJ |
1750 | { |
1751 | // OP_FCFE0000 (); | |
1752 | unsigned long imm; | |
1753 | ||
1754 | // Note: no PSW changes. | |
1755 | PC = cia; | |
1756 | imm = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); | |
1757 | State.regs[REG_SP] += imm; | |
1758 | } | |
1759 | ||
1760 | ||
1761 | // 1111 0001 0100 DmDn; addc Dm,Dn | |
1762 | 8.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc | |
1763 | "addc" | |
1764 | *mn10300 | |
d2b02ab2 JL |
1765 | // start-sanitize-am33 |
1766 | *am33 | |
1767 | // end-sanitize-am33 | |
7986ea13 JJ |
1768 | { |
1769 | // OP_F140 (); | |
1770 | int z, c, n, v; | |
1771 | unsigned long reg1, reg2, sum; | |
1772 | ||
1773 | PC = cia; | |
1774 | reg1 = State.regs[REG_D0 + DM1]; | |
1775 | reg2 = State.regs[REG_D0 + DN0]; | |
1776 | sum = reg1 + reg2 + ((PSW & PSW_C) != 0); | |
1777 | State.regs[REG_D0 + DN0] = sum; | |
1778 | ||
1779 | z = (sum == 0); | |
1780 | n = (sum & 0x80000000); | |
1781 | c = (sum < reg1) || (sum < reg2); | |
1782 | v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) | |
1783 | && (reg2 & 0x80000000) != (sum & 0x80000000)); | |
1784 | ||
1785 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1786 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1787 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
1788 | } | |
1789 | ||
1790 | ||
1791 | // 1111 0001 0000 DmDn; sub Dm,Dn | |
1792 | 8.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub | |
1793 | "sub" | |
1794 | *mn10300 | |
d2b02ab2 JL |
1795 | // start-sanitize-am33 |
1796 | *am33 | |
1797 | // end-sanitize-am33 | |
7986ea13 JJ |
1798 | { |
1799 | // OP_F100 (); | |
1800 | PC = cia; | |
1801 | genericSub(State.regs[REG_D0 + DM1], REG_D0 + DN0); | |
1802 | } | |
1803 | ||
1804 | // 1111 0001 0010 DmAn; sub DmAn | |
1805 | 8.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub | |
1806 | "sub" | |
1807 | *mn10300 | |
d2b02ab2 JL |
1808 | // start-sanitize-am33 |
1809 | *am33 | |
1810 | // end-sanitize-am33 | |
7986ea13 JJ |
1811 | { |
1812 | // OP_F120 (); | |
1813 | PC = cia; | |
1814 | genericSub(State.regs[REG_D0 + DM1], REG_A0 + AN0); | |
1815 | } | |
1816 | ||
1817 | ||
1818 | // 1111 0001 0001 AmDn; sub AmDn | |
1819 | 8.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub | |
1820 | "sub" | |
1821 | *mn10300 | |
d2b02ab2 JL |
1822 | // start-sanitize-am33 |
1823 | *am33 | |
1824 | // end-sanitize-am33 | |
7986ea13 JJ |
1825 | { |
1826 | // OP_F110 (); | |
1827 | PC = cia; | |
1828 | genericSub(State.regs[REG_A0 + AM1], REG_D0 + DN0); | |
1829 | } | |
1830 | ||
1831 | ||
1832 | // 1111 0001 0011 AmAn; sub Am,An | |
1833 | 8.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub | |
1834 | "sub" | |
1835 | *mn10300 | |
d2b02ab2 JL |
1836 | // start-sanitize-am33 |
1837 | *am33 | |
1838 | // end-sanitize-am33 | |
7986ea13 JJ |
1839 | { |
1840 | // OP_F130 (); | |
1841 | PC = cia; | |
1842 | genericSub(State.regs[REG_A0 + AM1], REG_A0 + AN0); | |
1843 | } | |
1844 | ||
1845 | ||
1846 | // 1111 1100 1100 01Dn imm32...; sub imm32,Dn | |
1847 | 8.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub | |
1848 | "sub" | |
1849 | *mn10300 | |
d2b02ab2 JL |
1850 | // start-sanitize-am33 |
1851 | *am33 | |
1852 | // end-sanitize-am33 | |
7986ea13 JJ |
1853 | { |
1854 | // OP_FCC40000 (); | |
1855 | PC = cia; | |
1856 | genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0); | |
1857 | } | |
1858 | ||
1859 | ||
1860 | // 1111 1100 1101 01An imm32...; sub imm32,An | |
1861 | 8.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub | |
1862 | "sub" | |
1863 | *mn10300 | |
d2b02ab2 JL |
1864 | // start-sanitize-am33 |
1865 | *am33 | |
1866 | // end-sanitize-am33 | |
7986ea13 JJ |
1867 | { |
1868 | // OP_FCD40000 (); | |
1869 | PC = cia; | |
1870 | genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0); | |
1871 | } | |
1872 | ||
1873 | ||
1874 | // 1111 0001 1000 DmDn; subc Dm,Dn | |
1875 | 8.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc | |
1876 | "subc" | |
1877 | *mn10300 | |
d2b02ab2 JL |
1878 | // start-sanitize-am33 |
1879 | *am33 | |
1880 | // end-sanitize-am33 | |
7986ea13 JJ |
1881 | { |
1882 | // OP_F180 (); | |
1883 | int z, c, n, v; | |
1884 | unsigned long reg1, reg2, difference; | |
1885 | ||
1886 | PC = cia; | |
1887 | reg1 = State.regs[REG_D0 + DM1]; | |
1888 | reg2 = State.regs[REG_D0 + DN0]; | |
1889 | difference = reg2 - reg1 - ((PSW & PSW_C) != 0); | |
1890 | State.regs[REG_D0 + DN0] = difference; | |
1891 | ||
1892 | z = (difference == 0); | |
1893 | n = (difference & 0x80000000); | |
1894 | c = (reg1 > reg2); | |
1895 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) | |
1896 | && (reg2 & 0x80000000) != (difference & 0x80000000)); | |
1897 | ||
1898 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1899 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1900 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
1901 | } | |
1902 | ||
1903 | ||
1904 | // 1111 0010 0100 DmDn; mul Dm,Dn | |
1905 | 8.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul | |
1906 | "mul" | |
1907 | *mn10300 | |
d2b02ab2 JL |
1908 | // start-sanitize-am33 |
1909 | *am33 | |
1910 | // end-sanitize-am33 | |
7986ea13 JJ |
1911 | { |
1912 | // OP_F240 (); | |
1913 | unsigned long long temp; | |
1914 | int n, z; | |
1915 | ||
1916 | PC = cia; | |
1917 | temp = ((signed64)(signed32)State.regs[REG_D0 + DN0] | |
1918 | * (signed64)(signed32)State.regs[REG_D0 + DM1]); | |
1919 | State.regs[REG_D0 + DN0] = temp & 0xffffffff; | |
1920 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;; | |
1921 | z = (State.regs[REG_D0 + DN0] == 0); | |
1922 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
1923 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1924 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
1925 | } | |
1926 | ||
1927 | ||
1928 | // 1111 0010 0101 DmDn; mulu Dm,Dn | |
1929 | 8.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu | |
1930 | "mulu" | |
1931 | *mn10300 | |
d2b02ab2 JL |
1932 | // start-sanitize-am33 |
1933 | *am33 | |
1934 | // end-sanitize-am33 | |
7986ea13 JJ |
1935 | { |
1936 | // OP_F250 (); | |
1937 | unsigned long long temp; | |
1938 | int n, z; | |
1939 | ||
1940 | PC = cia; | |
1941 | temp = ((unsigned64)State.regs[REG_D0 + DN0] | |
1942 | * (unsigned64)State.regs[REG_D0 + DM1]); | |
1943 | State.regs[REG_D0 + DN0] = temp & 0xffffffff; | |
1944 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; | |
1945 | z = (State.regs[REG_D0 + DN0] == 0); | |
1946 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
1947 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1948 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
1949 | } | |
1950 | ||
1951 | ||
1952 | // 1111 0010 0110 DmDn; div Dm,Dn | |
1953 | 8.0xf2+4.0x6,2.DM1,2.DN0:D0:::div | |
1954 | "div" | |
1955 | *mn10300 | |
d2b02ab2 JL |
1956 | // start-sanitize-am33 |
1957 | *am33 | |
1958 | // end-sanitize-am33 | |
7986ea13 JJ |
1959 | { |
1960 | // OP_F260 (); | |
1961 | long long temp; | |
1962 | int n, z; | |
1963 | ||
1964 | PC = cia; | |
1965 | temp = State.regs[REG_MDR]; | |
1966 | temp <<= 32; | |
1967 | temp |= State.regs[REG_D0 + DN0]; | |
1968 | State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + DM1]; | |
1969 | temp /= (long)State.regs[REG_D0 + DM1]; | |
1970 | State.regs[REG_D0 + DN0] = temp & 0xffffffff; | |
1971 | z = (State.regs[REG_D0 + DN0] == 0); | |
1972 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
1973 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1974 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
1975 | } | |
1976 | ||
1977 | ||
1978 | // 1111 0010 0111 DmDn; divu Dm,Dn | |
1979 | 8.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu | |
1980 | "divu" | |
1981 | *mn10300 | |
d2b02ab2 JL |
1982 | // start-sanitize-am33 |
1983 | *am33 | |
1984 | // end-sanitize-am33 | |
7986ea13 JJ |
1985 | { |
1986 | // OP_F270 (); | |
1987 | unsigned long long temp; | |
1988 | int n, z; | |
1989 | ||
1990 | PC = cia; | |
1991 | temp = State.regs[REG_MDR]; | |
1992 | temp <<= 32; | |
1993 | temp |= State.regs[REG_D0 + DN0]; | |
1994 | State.regs[REG_MDR] = temp % State.regs[REG_D0 + DM1]; | |
1995 | temp /= State.regs[REG_D0 + DM1]; | |
1996 | State.regs[REG_D0 + DN0] = temp & 0xffffffff; | |
1997 | z = (State.regs[REG_D0 + DN0] == 0); | |
1998 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
1999 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2000 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
2001 | } | |
2002 | ||
2003 | ||
2004 | // 0100 Dn00; inc Dn | |
2005 | 4.0x4,2.DN1,00:S0:::inc | |
2006 | "inc" | |
2007 | *mn10300 | |
d2b02ab2 JL |
2008 | // start-sanitize-am33 |
2009 | *am33 | |
2010 | // end-sanitize-am33 | |
7986ea13 JJ |
2011 | { |
2012 | // OP_40 (); | |
2013 | unsigned int imm; | |
2014 | ||
2015 | PC = cia; | |
2016 | imm = 1; | |
2017 | genericAdd(imm, REG_D0 + DN1); | |
2018 | } | |
2019 | ||
2020 | ||
2021 | // 0100 An01 | |
2022 | 4.0x4,2.AN1,01:S0a:::inc | |
2023 | "inc" | |
2024 | *mn10300 | |
d2b02ab2 JL |
2025 | // start-sanitize-am33 |
2026 | *am33 | |
2027 | // end-sanitize-am33 | |
7986ea13 JJ |
2028 | { |
2029 | // OP_41 (); | |
2030 | PC = cia; | |
2031 | State.regs[REG_A0 + AN1] += 1; | |
2032 | } | |
2033 | ||
2034 | ||
2035 | // 0101 00An; inc4 An | |
2036 | 4.0x5,00,2.AN0:S0:::inc4 | |
2037 | "inc4" | |
2038 | *mn10300 | |
d2b02ab2 JL |
2039 | // start-sanitize-am33 |
2040 | *am33 | |
2041 | // end-sanitize-am33 | |
7986ea13 JJ |
2042 | { |
2043 | // OP_50 (); | |
2044 | PC = cia; | |
2045 | State.regs[REG_A0 + AN0] += 4; | |
2046 | } | |
2047 | ||
2048 | ||
2049 | // 1010 DnDn imm8....; cmp imm8,Dn (imm8 is sign-extended.) | |
d2b02ab2 JL |
2050 | 4.0xa,2.DM1,2.DN0=DM1+IMM8:S0i:::cmp |
2051 | "cmp" | |
2052 | *mn10300 | |
2053 | // start-sanitize-am33 | |
2054 | *am33 | |
2055 | // end-sanitize-am33 | |
2056 | { | |
2057 | PC = cia; | |
2058 | // OP_A000 (); | |
2059 | genericCmp(EXTEND8 (IMM8), State.regs[REG_D0 + DN0]); | |
2060 | } | |
2061 | ||
2062 | ||
7986ea13 | 2063 | // 1010 DmDn; cmp Dm,Dn (Dm != Dn, see above when Dm == Dn) |
d2b02ab2 | 2064 | 4.0xa,2.DM1,2.DN0!DM1:S0:::cmp |
7986ea13 JJ |
2065 | "cmp" |
2066 | *mn10300 | |
d2b02ab2 JL |
2067 | // start-sanitize-am33 |
2068 | *am33 | |
2069 | // end-sanitize-am33 | |
7986ea13 JJ |
2070 | { |
2071 | PC = cia; | |
d2b02ab2 JL |
2072 | // OP_A0 (); |
2073 | genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_D0 + DN0]); | |
7986ea13 JJ |
2074 | } |
2075 | ||
2076 | ||
2077 | // 1111 0001 1010 DmAn; cmp Dm,An | |
2078 | 8.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp | |
2079 | "cmp" | |
2080 | *mn10300 | |
d2b02ab2 JL |
2081 | // start-sanitize-am33 |
2082 | *am33 | |
2083 | // end-sanitize-am33 | |
7986ea13 JJ |
2084 | { |
2085 | // OP_F1A0 (); | |
2086 | PC = cia; | |
2087 | genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_A0 + AN0]); | |
2088 | } | |
2089 | ||
2090 | ||
2091 | // 1111 0001 1001 AmDn; cmp Am,Dn | |
2092 | 8.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp | |
2093 | "cmp" | |
2094 | *mn10300 | |
d2b02ab2 JL |
2095 | // start-sanitize-am33 |
2096 | *am33 | |
2097 | // end-sanitize-am33 | |
7986ea13 JJ |
2098 | { |
2099 | // OP_F190 (); | |
2100 | PC = cia; | |
2101 | genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_D0 + DN0]); | |
2102 | } | |
2103 | ||
2104 | ||
2105 | // 1011 AnAn imm8....; cmp imm8,An (imm8 is zero-extended.) | |
d2b02ab2 JL |
2106 | 4.0xb,2.AM1,2.AN0=AM1+IMM8:S0ai:::cmp |
2107 | "cmp" | |
2108 | *mn10300 | |
2109 | // start-sanitize-am33 | |
2110 | *am33 | |
2111 | // end-sanitize-am33 | |
2112 | { | |
2113 | PC = cia; | |
2114 | // op_B000 (); | |
2115 | genericCmp(IMM8, | |
2116 | State.regs[REG_A0 + AN0]); | |
2117 | } | |
2118 | ||
2119 | ||
7986ea13 | 2120 | // 1011 AmAn; cmp Am,An (Dm != Dn, see above when Dm == Dn) |
d2b02ab2 | 2121 | 4.0xb,2.AM1,2.AN0!AM1:S0a:::cmp |
7986ea13 JJ |
2122 | "cmp" |
2123 | *mn10300 | |
d2b02ab2 JL |
2124 | // start-sanitize-am33 |
2125 | *am33 | |
2126 | // end-sanitize-am33 | |
7986ea13 JJ |
2127 | { |
2128 | PC = cia; | |
d2b02ab2 JL |
2129 | // OP_B0 (); |
2130 | genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_A0 + AN0]); | |
7986ea13 JJ |
2131 | } |
2132 | ||
2133 | ||
2134 | // 1111 1010 1100 10Dn imm16...; cmp imm16,Dn (imm16 is sign-extended.) | |
2135 | 8.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp | |
2136 | "cmp" | |
2137 | *mn10300 | |
d2b02ab2 JL |
2138 | // start-sanitize-am33 |
2139 | *am33 | |
2140 | // end-sanitize-am33 | |
7986ea13 JJ |
2141 | { |
2142 | // OP_FAC80000 (); | |
2143 | PC = cia; | |
2144 | genericCmp(EXTEND16(FETCH16(IMM16A, IMM16B)), | |
2145 | State.regs[REG_D0 + DN0]); | |
2146 | } | |
2147 | ||
2148 | ||
2149 | // 1111 1100 1100 10Dn imm32...; cmp imm32,Dn | |
2150 | 8.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp | |
2151 | "cmp" | |
2152 | *mn10300 | |
d2b02ab2 JL |
2153 | // start-sanitize-am33 |
2154 | *am33 | |
2155 | // end-sanitize-am33 | |
7986ea13 JJ |
2156 | { |
2157 | // OP_FCC80000 (); | |
2158 | PC = cia; | |
2159 | genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), | |
2160 | State.regs[REG_D0 + DN0]); | |
2161 | } | |
2162 | ||
2163 | ||
2164 | // 1111 1010 1101 10An imm16...; cmp imm16,An (imm16 is zero-extended.) | |
2165 | 8.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp | |
2166 | "cmp" | |
2167 | *mn10300 | |
d2b02ab2 JL |
2168 | // start-sanitize-am33 |
2169 | *am33 | |
2170 | // end-sanitize-am33 | |
7986ea13 JJ |
2171 | { |
2172 | // OP_FAD80000 (); | |
2173 | PC = cia; | |
2174 | genericCmp(FETCH16(IMM16A, IMM16B), | |
2175 | State.regs[REG_A0 + AN0]); | |
2176 | } | |
2177 | ||
2178 | ||
2179 | // 1111 1100 1101 10An imm32...; cmp imm32,An | |
2180 | 8.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp | |
2181 | "cmp" | |
2182 | *mn10300 | |
d2b02ab2 JL |
2183 | // start-sanitize-am33 |
2184 | *am33 | |
2185 | // end-sanitize-am33 | |
7986ea13 JJ |
2186 | { |
2187 | // OP_FCD80000 (); | |
2188 | PC = cia; | |
2189 | genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), | |
2190 | State.regs[REG_A0 + AN0]); | |
2191 | } | |
2192 | ||
2193 | ||
2194 | // 1111 0010 0000 DmDn; and Dm,Dn | |
2195 | 8.0xf2+4.0x0,2.DM1,2.DN0:D0:::and | |
2196 | "and" | |
2197 | *mn10300 | |
d2b02ab2 JL |
2198 | // start-sanitize-am33 |
2199 | *am33 | |
2200 | // end-sanitize-am33 | |
7986ea13 JJ |
2201 | { |
2202 | // OP_F200 (); | |
2203 | int n, z; | |
2204 | ||
2205 | PC = cia; | |
2206 | State.regs[REG_D0 + DN0] &= State.regs[REG_D0 + DM1]; | |
2207 | z = (State.regs[REG_D0 + DN0] == 0); | |
2208 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
2209 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2210 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
2211 | } | |
2212 | ||
2213 | ||
2214 | // 1111 1000 1110 00Dn imm8....; and imm8,Dn (imm8 is zero-extended.) | |
2215 | 8.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and | |
2216 | "and" | |
2217 | *mn10300 | |
d2b02ab2 JL |
2218 | // start-sanitize-am33 |
2219 | *am33 | |
2220 | // end-sanitize-am33 | |
7986ea13 JJ |
2221 | { |
2222 | // OP_F8E000 (); | |
2223 | int n, z; | |
2224 | ||
2225 | PC = cia; | |
2226 | State.regs[REG_D0 + DN0] &= IMM8; | |
2227 | z = (State.regs[REG_D0 + DN0] == 0); | |
2228 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
2229 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2230 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
2231 | } | |
2232 | ||
2233 | ||
2234 | // 1111 1010 1110 00Dn imm16...; and imm16,Dn (imm16 is zero-extended.) | |
2235 | 8.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and | |
2236 | "and" | |
2237 | *mn10300 | |
d2b02ab2 JL |
2238 | // start-sanitize-am33 |
2239 | *am33 | |
2240 | // end-sanitize-am33 | |
7986ea13 JJ |
2241 | { |
2242 | // OP_FAE00000 (); | |
2243 | int n, z; | |
2244 | ||
2245 | PC = cia; | |
2246 | State.regs[REG_D0 + DN0] &= FETCH16(IMM16A, IMM16B); | |
2247 | z = (State.regs[REG_D0 + DN0] == 0); | |
2248 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
2249 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2250 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
2251 | } | |
2252 | ||
2253 | ||
2254 | // 1111 1100 1110 00Dn imm32...; and imm32,Dn | |
2255 | 8.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and | |
2256 | "and" | |
2257 | *mn10300 | |
d2b02ab2 JL |
2258 | // start-sanitize-am33 |
2259 | *am33 | |
2260 | // end-sanitize-am33 | |
7986ea13 JJ |
2261 | { |
2262 | // OP_FCE00000 (); | |
2263 | int n, z; | |
2264 | ||
2265 | PC = cia; | |
2266 | State.regs[REG_D0 + DN0] | |
2267 | &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); | |
2268 | z = (State.regs[REG_D0 + DN0] == 0); | |
2269 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
2270 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2271 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
2272 | } | |
2273 | ||
2274 | ||
2275 | // 1111 1010 1111 1100 imm16...; and imm16,PSW (imm16 is zero-extended.) | |
2276 | 8.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and | |
2277 | "and" | |
2278 | *mn10300 | |
d2b02ab2 JL |
2279 | // start-sanitize-am33 |
2280 | *am33 | |
2281 | // end-sanitize-am33 | |
7986ea13 JJ |
2282 | { |
2283 | // OP_FAFC0000 (); | |
2284 | PC = cia; | |
2285 | PSW &= FETCH16(IMM16A, IMM16B); | |
2286 | } | |
2287 | ||
2288 | ||
2289 | ||
2290 | // 1111 0010 0001 DmDn; or DmDn | |
2291 | 8.0xf2+4.0x1,2.DM1,2.DN0:D0:::or | |
2292 | "or" | |
2293 | *mn10300 | |
d2b02ab2 JL |
2294 | // start-sanitize-am33 |
2295 | *am33 | |
2296 | // end-sanitize-am33 | |
7986ea13 JJ |
2297 | { |
2298 | // OP_F210 (); | |
2299 | PC = cia; | |
2300 | genericOr(State.regs[REG_D0 + DM1], REG_D0 + DN0); | |
2301 | } | |
2302 | ||
2303 | ||
2304 | // 1111 1000 1110 01Dn imm8....; or imm8,Dn (imm8 is zero-extended.)n | |
2305 | 8.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or | |
2306 | "or" | |
2307 | *mn10300 | |
d2b02ab2 JL |
2308 | // start-sanitize-am33 |
2309 | *am33 | |
2310 | // end-sanitize-am33 | |
7986ea13 JJ |
2311 | { |
2312 | // OP_F8E400 (); | |
2313 | PC = cia; | |
2314 | genericOr(IMM8, REG_D0 + DN0); | |
2315 | } | |
2316 | ||
2317 | ||
2318 | // 1111 1010 1110 01Dn imm16...; or imm16,DN (imm16 is zero-extended.) | |
2319 | 8.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or | |
2320 | "or" | |
2321 | *mn10300 | |
d2b02ab2 JL |
2322 | // start-sanitize-am33 |
2323 | *am33 | |
2324 | // end-sanitize-am33 | |
7986ea13 JJ |
2325 | { |
2326 | // OP_FAE40000 (); | |
2327 | PC = cia; | |
2328 | genericOr(FETCH16(IMM16A, IMM16B), REG_D0 + DN0); | |
2329 | } | |
2330 | ||
2331 | ||
2332 | // 1111 1100 1110 01Dn imm32...; or imm32,Dn | |
2333 | 8.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or | |
2334 | "or" | |
2335 | *mn10300 | |
d2b02ab2 JL |
2336 | // start-sanitize-am33 |
2337 | *am33 | |
2338 | // end-sanitize-am33 | |
7986ea13 JJ |
2339 | { |
2340 | // OP_FCE40000 (); | |
2341 | PC = cia; | |
2342 | genericOr(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0); | |
2343 | } | |
2344 | ||
2345 | ||
2346 | // 1111 1010 1111 1101 imm16...; or imm16,PSW (imm16 is zero-extended.) | |
2347 | 8.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or | |
2348 | "or" | |
2349 | *mn10300 | |
d2b02ab2 JL |
2350 | // start-sanitize-am33 |
2351 | *am33 | |
2352 | // end-sanitize-am33 | |
7986ea13 JJ |
2353 | { |
2354 | // OP_FAFD0000 (); | |
2355 | PC = cia; | |
2356 | PSW |= FETCH16(IMM16A, IMM16B); | |
2357 | } | |
2358 | ||
2359 | ||
2360 | // 1111 0010 0010 DmDn; xor Dm,Dn | |
2361 | 8.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor | |
2362 | "xor" | |
2363 | *mn10300 | |
d2b02ab2 JL |
2364 | // start-sanitize-am33 |
2365 | *am33 | |
2366 | // end-sanitize-am33 | |
7986ea13 JJ |
2367 | { |
2368 | // OP_F220 (); | |
2369 | PC = cia; | |
2370 | genericXor(State.regs[REG_D0 + DM1], REG_D0 + DN0); | |
2371 | } | |
2372 | ||
2373 | ||
2374 | // 1111 1010 1110 10Dn imm16...; xor imm16,Dn (imm16 is zero-extended.) | |
2375 | 8.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor | |
2376 | "xor" | |
2377 | *mn10300 | |
d2b02ab2 JL |
2378 | // start-sanitize-am33 |
2379 | *am33 | |
2380 | // end-sanitize-am33 | |
7986ea13 JJ |
2381 | { |
2382 | // OP_FAE80000 (); | |
2383 | PC = cia; | |
2384 | genericXor(FETCH16(IMM16A, IMM16B), REG_D0 + DN0); | |
2385 | } | |
2386 | ||
2387 | ||
2388 | // 1111 1100 1110 10Dn imm32...; xor imm32,Dn | |
2389 | 8.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor | |
2390 | "xor" | |
2391 | *mn10300 | |
d2b02ab2 JL |
2392 | // start-sanitize-am33 |
2393 | *am33 | |
2394 | // end-sanitize-am33 | |
7986ea13 JJ |
2395 | { |
2396 | // OP_FCE80000 (); | |
2397 | PC = cia; | |
2398 | genericXor(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0); | |
2399 | } | |
2400 | ||
2401 | ||
2402 | // 1111 0010 0011 00Dn; not Dn | |
2403 | 8.0xf2+4.0x3,00,2.DN0:D0:::not | |
2404 | "not" | |
2405 | *mn10300 | |
d2b02ab2 JL |
2406 | // start-sanitize-am33 |
2407 | *am33 | |
2408 | // end-sanitize-am33 | |
7986ea13 JJ |
2409 | { |
2410 | // OP_F230 (); | |
2411 | int n, z; | |
2412 | ||
2413 | PC = cia; | |
2414 | State.regs[REG_D0 + DN0] = ~State.regs[REG_D0 + DN0]; | |
2415 | z = (State.regs[REG_D0 + DN0] == 0); | |
2416 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
2417 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2418 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
2419 | } | |
2420 | ||
2421 | ||
2422 | // 1111 1000 1110 11Dn imm8....; btst imm8,Dn (imm8 is zero-extended.) | |
2423 | 8.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst | |
2424 | "btst" | |
2425 | *mn10300 | |
d2b02ab2 JL |
2426 | // start-sanitize-am33 |
2427 | *am33 | |
2428 | // end-sanitize-am33 | |
7986ea13 JJ |
2429 | { |
2430 | // OP_F8EC00 (); | |
2431 | PC = cia; | |
2432 | genericBtst(IMM8, State.regs[REG_D0 + DN0]); | |
2433 | } | |
2434 | ||
2435 | ||
2436 | // 1111 1010 1110 11Dn imm16.....; btst imm16,Dn (imm16 is zero-extended.) | |
2437 | 8.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst | |
2438 | "btst" | |
2439 | *mn10300 | |
d2b02ab2 JL |
2440 | // start-sanitize-am33 |
2441 | *am33 | |
2442 | // end-sanitize-am33 | |
7986ea13 JJ |
2443 | { |
2444 | // OP_FAEC0000 (); | |
2445 | PC = cia; | |
2446 | genericBtst(FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DN0]); | |
2447 | } | |
2448 | ||
2449 | ||
2450 | // 1111 1100 1110 11Dn imm32...; btst imm32,Dn | |
2451 | 8.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst | |
2452 | "btst" | |
2453 | *mn10300 | |
d2b02ab2 JL |
2454 | // start-sanitize-am33 |
2455 | *am33 | |
2456 | // end-sanitize-am33 | |
7986ea13 JJ |
2457 | { |
2458 | // OP_FCEC0000 (); | |
2459 | PC = cia; | |
2460 | genericBtst(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), | |
2461 | State.regs[REG_D0 + DN0]); | |
2462 | } | |
2463 | ||
2464 | ||
2465 | // 1111 1110 0000 0010 abs32... imm8....; btst imm8,(abs32) (imm8 is zero-extended., processing unit: byte) | |
2466 | 8.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst | |
2467 | "btst" | |
2468 | *mn10300 | |
d2b02ab2 JL |
2469 | // start-sanitize-am33 |
2470 | *am33 | |
2471 | // end-sanitize-am33 | |
7986ea13 JJ |
2472 | { |
2473 | // OP_FE020000 (); | |
2474 | PC = cia; | |
2475 | genericBtst(IMM8, | |
2476 | load_byte(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D))); | |
2477 | } | |
2478 | ||
2479 | ||
2480 | // 1111 1010 1111 10An d8...... imm8....; | |
2481 | // btst imm8,(d8,An) (d8 is sign-extended,imm8 is zero-extended., processing unit: byte) | |
2482 | 8.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst | |
2483 | "btst" | |
2484 | *mn10300 | |
d2b02ab2 JL |
2485 | // start-sanitize-am33 |
2486 | *am33 | |
2487 | // end-sanitize-am33 | |
7986ea13 JJ |
2488 | { |
2489 | // OP_FAF80000 (); | |
2490 | PC = cia; | |
2491 | genericBtst(IMM8, | |
2492 | load_byte(State.regs[REG_A0 + AN0] + EXTEND8(D8))); | |
2493 | } | |
2494 | ||
2495 | ||
2496 | // 1111 0000 1000 DmAn; bset Dm,(An) (Processing unit byte) | |
2497 | 8.0xf0+4.8,2.DM1,2.AN0:D0:::bset | |
2498 | "bset" | |
2499 | *mn10300 | |
d2b02ab2 JL |
2500 | // start-sanitize-am33 |
2501 | *am33 | |
2502 | // end-sanitize-am33 | |
7986ea13 JJ |
2503 | { |
2504 | // OP_F080 (); | |
2505 | unsigned long temp; | |
2506 | int z; | |
2507 | ||
2508 | PC = cia; | |
2509 | temp = load_byte (State.regs[REG_A0 + AN0]); | |
2510 | z = (temp & State.regs[REG_D0 + DM1]) == 0; | |
2511 | temp |= State.regs[REG_D0 + DM1]; | |
2512 | store_byte (State.regs[REG_A0 + AN0], temp); | |
2513 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2514 | PSW |= (z ? PSW_Z : 0); | |
2515 | } | |
2516 | ||
2517 | ||
2518 | // 1111 1110 0000 0000 abs32... imm8....; | |
2519 | // bset imm8,(abs32) (imm8 is zero-extended., processing unit: byte) | |
2520 | 8.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset | |
2521 | "bset" | |
2522 | *mn10300 | |
d2b02ab2 JL |
2523 | // start-sanitize-am33 |
2524 | *am33 | |
2525 | // end-sanitize-am33 | |
7986ea13 JJ |
2526 | { |
2527 | // OP_FE000000 (); | |
2528 | unsigned long temp; | |
2529 | int z; | |
2530 | ||
2531 | PC = cia; | |
2532 | temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)); | |
2533 | z = (temp & IMM8) == 0; | |
2534 | temp |= IMM8; | |
2535 | store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp); | |
2536 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2537 | PSW |= (z ? PSW_Z : 0); | |
2538 | } | |
2539 | ||
2540 | ||
2541 | // 1111 1010 1111 00AnAn d8...... imm8....; | |
2542 | // bset imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte) | |
2543 | 8.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset | |
2544 | "bset" | |
2545 | *mn10300 | |
d2b02ab2 JL |
2546 | // start-sanitize-am33 |
2547 | *am33 | |
2548 | // end-sanitize-am33 | |
7986ea13 JJ |
2549 | { |
2550 | // OP_FAF00000 (); | |
2551 | unsigned long temp; | |
2552 | int z; | |
2553 | ||
2554 | PC = cia; | |
2555 | temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8))); | |
2556 | z = (temp & (IMM8)) == 0; | |
2557 | temp |= (IMM8); | |
2558 | store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp); | |
2559 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2560 | PSW |= (z ? PSW_Z : 0); | |
2561 | } | |
2562 | ||
2563 | ||
2564 | // 1111 0000 1001 DmAn; bclr Dm,(An) (Processing unit byte) | |
2565 | 8.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr | |
2566 | "bclr" | |
2567 | *mn10300 | |
d2b02ab2 JL |
2568 | // start-sanitize-am33 |
2569 | *am33 | |
2570 | // end-sanitize-am33 | |
7986ea13 JJ |
2571 | { |
2572 | // OP_F090 (); | |
2573 | unsigned long temp; | |
2574 | int z; | |
2575 | ||
2576 | PC = cia; | |
2577 | temp = load_byte (State.regs[REG_A0 + AN0]); | |
2578 | z = (temp & State.regs[REG_D0 + DM1]) == 0; | |
2579 | temp = temp & ~State.regs[REG_D0 + DM1]; | |
2580 | store_byte (State.regs[REG_A0 + AN0], temp); | |
2581 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2582 | PSW |= (z ? PSW_Z : 0); | |
2583 | } | |
2584 | ||
2585 | ||
2586 | // 1111 1110 0000 0001 abs32... imm8....; | |
2587 | // bclr imm8,(abs32) (imm8 is zero-extended., processing unit: byte) | |
2588 | 8.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr | |
2589 | "bclr" | |
2590 | *mn10300 | |
d2b02ab2 JL |
2591 | // start-sanitize-am33 |
2592 | *am33 | |
2593 | // end-sanitize-am33 | |
7986ea13 JJ |
2594 | { |
2595 | // OP_FE010000 (); | |
2596 | unsigned long temp; | |
2597 | int z; | |
2598 | ||
2599 | PC = cia; | |
2600 | temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)); | |
2601 | z = (temp & IMM8) == 0; | |
2602 | temp = temp & ~(IMM8); | |
2603 | store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp); | |
2604 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2605 | PSW |= (z ? PSW_Z : 0); | |
2606 | } | |
2607 | ||
2608 | ||
2609 | // 1111 1010 1111 01An d8...... imm8....; | |
2610 | // bclr imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte) | |
2611 | 8.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr | |
2612 | "bclr" | |
2613 | *mn10300 | |
d2b02ab2 JL |
2614 | // start-sanitize-am33 |
2615 | *am33 | |
2616 | // end-sanitize-am33 | |
7986ea13 JJ |
2617 | { |
2618 | // OP_FAF40000 (); | |
2619 | unsigned long temp; | |
2620 | int z; | |
2621 | ||
2622 | PC = cia; | |
2623 | temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8))); | |
2624 | z = (temp & (IMM8)) == 0; | |
2625 | temp = temp & ~(IMM8); | |
2626 | store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp); | |
2627 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2628 | PSW |= (z ? PSW_Z : 0); | |
2629 | } | |
2630 | ||
2631 | ||
2632 | // 1111 0010 1011 DmDn; asr Dm,Dn | |
2633 | 8.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr | |
2634 | "asr" | |
2635 | *mn10300 | |
d2b02ab2 JL |
2636 | // start-sanitize-am33 |
2637 | *am33 | |
2638 | // end-sanitize-am33 | |
7986ea13 JJ |
2639 | { |
2640 | // OP_F2B0 (); | |
2641 | long temp; | |
2642 | int z, n, c; | |
2643 | ||
2644 | PC = cia; | |
2645 | temp = State.regs[REG_D0 + DN0]; | |
2646 | c = temp & 1; | |
2647 | temp >>= State.regs[REG_D0 + DM1]; | |
2648 | State.regs[REG_D0 + DN0] = temp; | |
2649 | z = (State.regs[REG_D0 + DN0] == 0); | |
2650 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
2651 | PSW &= ~(PSW_Z | PSW_N | PSW_C); | |
2652 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
2653 | } | |
2654 | ||
2655 | ||
2656 | // 1111 1000 1100 10Dn imm8...; asr imm8,Dn (imm8 is zero-extended.) | |
2657 | 8.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr | |
2658 | "asr" | |
2659 | *mn10300 | |
d2b02ab2 JL |
2660 | // start-sanitize-am33 |
2661 | *am33 | |
2662 | // end-sanitize-am33 | |
7986ea13 JJ |
2663 | { |
2664 | // OP_F8C800 (); | |
2665 | long temp; | |
2666 | int z, n, c; | |
2667 | ||
2668 | PC = cia; | |
2669 | temp = State.regs[REG_D0 + DN0]; | |
2670 | c = temp & 1; | |
2671 | temp >>= IMM8; | |
2672 | State.regs[REG_D0 + DN0] = temp; | |
2673 | z = (State.regs[REG_D0 + DN0] == 0); | |
2674 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
2675 | PSW &= ~(PSW_Z | PSW_N | PSW_C); | |
2676 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
2677 | } | |
2678 | ||
2679 | ||
2680 | // 1111 0010 1010 DmDn; lsr Dm,Dn | |
2681 | 8.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr | |
2682 | "lsr" | |
2683 | *mn10300 | |
d2b02ab2 JL |
2684 | // start-sanitize-am33 |
2685 | *am33 | |
2686 | // end-sanitize-am33 | |
7986ea13 JJ |
2687 | { |
2688 | // OP_F2A0 (); | |
2689 | int z, n, c; | |
2690 | ||
2691 | PC = cia; | |
2692 | c = State.regs[REG_D0 + DN0] & 1; | |
2693 | State.regs[REG_D0 + DN0] | |
2694 | >>= State.regs[REG_D0 + DM1]; | |
2695 | z = (State.regs[REG_D0 + DN0] == 0); | |
2696 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
2697 | PSW &= ~(PSW_Z | PSW_N | PSW_C); | |
2698 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
2699 | } | |
2700 | ||
2701 | ||
2702 | // 1111 1000 1100 01Dn imm8...; lsr imm8,Dn (imm8 is zero-extended.) | |
2703 | 8.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr | |
2704 | "lsr" | |
2705 | *mn10300 | |
d2b02ab2 JL |
2706 | // start-sanitize-am33 |
2707 | *am33 | |
2708 | // end-sanitize-am33 | |
7986ea13 JJ |
2709 | { |
2710 | // OP_F8C400 (); | |
2711 | int z, n, c; | |
2712 | ||
2713 | PC = cia; | |
2714 | c = State.regs[REG_D0 + DN0] & 1; | |
2715 | State.regs[REG_D0 + DN0] >>= IMM8; | |
2716 | z = (State.regs[REG_D0 + DN0] == 0); | |
2717 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
2718 | PSW &= ~(PSW_Z | PSW_N | PSW_C); | |
2719 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
2720 | } | |
2721 | ||
2722 | ||
2723 | // 1111 0010 1001 DmDn; asl Dm,Dn | |
2724 | 8.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl | |
2725 | "asl" | |
2726 | *mn10300 | |
d2b02ab2 JL |
2727 | // start-sanitize-am33 |
2728 | *am33 | |
2729 | // end-sanitize-am33 | |
7986ea13 JJ |
2730 | { |
2731 | // OP_F290 (); | |
2732 | int n, z; | |
2733 | ||
2734 | PC = cia; | |
2735 | State.regs[REG_D0 + DN0] | |
2736 | <<= State.regs[REG_D0 + DM1]; | |
2737 | z = (State.regs[REG_D0 + DN0] == 0); | |
2738 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
2739 | PSW &= ~(PSW_Z | PSW_N); | |
2740 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
2741 | } | |
2742 | ||
2743 | ||
2744 | // 1111 1000 1100 00Dn imm8...; asl imm8,Dn (imm8 is zero-extended.) | |
2745 | 8.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl | |
2746 | "asl" | |
2747 | *mn10300 | |
d2b02ab2 JL |
2748 | // start-sanitize-am33 |
2749 | *am33 | |
2750 | // end-sanitize-am33 | |
7986ea13 JJ |
2751 | { |
2752 | // OP_F8C000 (); | |
2753 | int n, z; | |
2754 | ||
2755 | PC = cia; | |
2756 | State.regs[REG_D0 + DN0] <<= IMM8; | |
2757 | z = (State.regs[REG_D0 + DN0] == 0); | |
2758 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
2759 | PSW &= ~(PSW_Z | PSW_N); | |
2760 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
2761 | } | |
2762 | ||
2763 | ||
2764 | // 0101 01Dn; als2 Dn | |
2765 | 4.0x5,01,2.DN0:S0:::asl2 | |
2766 | "asl2" | |
2767 | *mn10300 | |
d2b02ab2 JL |
2768 | // start-sanitize-am33 |
2769 | *am33 | |
2770 | // end-sanitize-am33 | |
7986ea13 JJ |
2771 | { |
2772 | // OP_54 (); | |
2773 | int n, z; | |
2774 | PC = cia; | |
2775 | ||
2776 | State.regs[REG_D0 + DN0] <<= 2; | |
2777 | z = (State.regs[REG_D0 + DN0] == 0); | |
2778 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
2779 | PSW &= ~(PSW_Z | PSW_N); | |
2780 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
2781 | } | |
2782 | ||
2783 | ||
2784 | // 1111 0010 1000 01Dn; ror Dn | |
2785 | 8.0xf2+4.0x8,01,2.DN0:D0:::ror | |
2786 | "ror" | |
2787 | *mn10300 | |
d2b02ab2 JL |
2788 | // start-sanitize-am33 |
2789 | *am33 | |
2790 | // end-sanitize-am33 | |
7986ea13 JJ |
2791 | { |
2792 | // OP_F284 (); | |
2793 | unsigned long value; | |
2794 | int c,n,z; | |
2795 | ||
2796 | PC = cia; | |
2797 | value = State.regs[REG_D0 + DN0]; | |
2798 | c = (value & 0x1); | |
2799 | ||
2800 | value >>= 1; | |
2801 | value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0; | |
2802 | State.regs[REG_D0 + DN0] = value; | |
2803 | z = (value == 0); | |
2804 | n = (value & 0x80000000) != 0; | |
2805 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2806 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
2807 | } | |
2808 | ||
2809 | ||
2810 | // 1111 0010 1000 00Dn; rol Dn | |
2811 | 8.0xf2+4.0x8,00,2.DN0:D0:::rol | |
2812 | "rol" | |
2813 | *mn10300 | |
d2b02ab2 JL |
2814 | // start-sanitize-am33 |
2815 | *am33 | |
2816 | // end-sanitize-am33 | |
7986ea13 JJ |
2817 | { |
2818 | // handle ror above, too. | |
2819 | // OP_F280 (); | |
2820 | unsigned long value; | |
2821 | int c,n,z; | |
2822 | ||
2823 | PC = cia; | |
2824 | value = State.regs[REG_D0 + DN0]; | |
2825 | c = (value & 0x80000000) ? 1 : 0; | |
2826 | ||
2827 | value <<= 1; | |
2828 | value |= ((PSW & PSW_C) != 0); | |
2829 | State.regs[REG_D0 + DN0] = value; | |
2830 | z = (value == 0); | |
2831 | n = (value & 0x80000000) != 0; | |
2832 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2833 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
2834 | } | |
2835 | ||
2836 | ||
2837 | // 1100 1000 d8......; beq (d8,PC) (d8 is sign-extended) | |
2838 | 8.0xc8+8.D8:S1:::beq | |
2839 | "beq" | |
2840 | *mn10300 | |
d2b02ab2 JL |
2841 | // start-sanitize-am33 |
2842 | *am33 | |
2843 | // end-sanitize-am33 | |
7986ea13 JJ |
2844 | { |
2845 | // OP_C800 (); | |
2846 | PC = cia; | |
2847 | if ((PSW & PSW_Z)) | |
2848 | { | |
2849 | State.regs[REG_PC] += EXTEND8 (D8); | |
2850 | nia = PC; | |
2851 | } | |
2852 | } | |
2853 | ||
2854 | ||
2855 | // 1100 1001 d8......; bne (d8,PC) (d8 is sign-extended) | |
2856 | 8.0xc9+8.D8:S1:::bne | |
2857 | "bne" | |
2858 | *mn10300 | |
d2b02ab2 JL |
2859 | // start-sanitize-am33 |
2860 | *am33 | |
2861 | // end-sanitize-am33 | |
7986ea13 JJ |
2862 | { |
2863 | // OP_C900 (); | |
2864 | PC = cia; | |
2865 | if (!(PSW & PSW_Z)) | |
2866 | { | |
2867 | State.regs[REG_PC] += EXTEND8 (D8); | |
2868 | nia = PC; | |
2869 | } | |
2870 | } | |
2871 | ||
2872 | ||
2873 | // 1100 0001 d8......; bgt (d8,PC) (d8 is sign-extended) | |
2874 | 8.0xc1+8.D8:S1:::bgt | |
2875 | "bgt" | |
2876 | *mn10300 | |
d2b02ab2 JL |
2877 | // start-sanitize-am33 |
2878 | *am33 | |
2879 | // end-sanitize-am33 | |
7986ea13 JJ |
2880 | { |
2881 | // OP_C100 (); | |
2882 | PC = cia; | |
2883 | if (!((PSW & PSW_Z) | |
2884 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))) | |
2885 | { | |
2886 | State.regs[REG_PC] += EXTEND8 (D8); | |
2887 | nia = PC; | |
2888 | } | |
2889 | } | |
2890 | ||
2891 | ||
2892 | // 1100 0010 d8......; bge (d8,PC) (d8 is sign-extended) | |
2893 | 8.0xc2+8.D8:S1:::bge | |
2894 | "bge" | |
2895 | *mn10300 | |
d2b02ab2 JL |
2896 | // start-sanitize-am33 |
2897 | *am33 | |
2898 | // end-sanitize-am33 | |
7986ea13 JJ |
2899 | { |
2900 | // OP_C200 (); | |
2901 | PC = cia; | |
2902 | if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) | |
2903 | { | |
2904 | State.regs[REG_PC] += EXTEND8 (D8); | |
2905 | nia = PC; | |
2906 | } | |
2907 | } | |
2908 | ||
2909 | ||
2910 | // 1100 0011 d8......; ble (d8,PC) (d8 is sign-extended) | |
2911 | 8.0xc3+8.D8:S1:::ble | |
2912 | "ble" | |
2913 | *mn10300 | |
d2b02ab2 JL |
2914 | // start-sanitize-am33 |
2915 | *am33 | |
2916 | // end-sanitize-am33 | |
7986ea13 JJ |
2917 | { |
2918 | // OP_C300 (); | |
2919 | PC = cia; | |
2920 | if ((PSW & PSW_Z) | |
2921 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) | |
2922 | { | |
2923 | State.regs[REG_PC] += EXTEND8 (D8); | |
2924 | nia = PC; | |
2925 | } | |
2926 | } | |
2927 | ||
2928 | ||
2929 | // 1100 0000 d8......; blt (d8,PC) (d8 is sign-extended) | |
2930 | 8.0xc0+8.D8:S1:::blt | |
2931 | "blt" | |
2932 | *mn10300 | |
d2b02ab2 JL |
2933 | // start-sanitize-am33 |
2934 | *am33 | |
2935 | // end-sanitize-am33 | |
7986ea13 JJ |
2936 | { |
2937 | // OP_C000 (); | |
2938 | PC = cia; | |
2939 | if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)) | |
2940 | { | |
2941 | State.regs[REG_PC] += EXTEND8 (D8); | |
2942 | nia = PC; | |
2943 | } | |
2944 | } | |
2945 | ||
2946 | ||
2947 | // 1100 0101 d8......; bhi (d8,PC) (d8 is sign-extended) | |
2948 | 8.0xc5+8.D8:S1:::bhi | |
2949 | "bhi" | |
2950 | *mn10300 | |
d2b02ab2 JL |
2951 | // start-sanitize-am33 |
2952 | *am33 | |
2953 | // end-sanitize-am33 | |
7986ea13 JJ |
2954 | { |
2955 | // OP_C500 (); | |
2956 | PC = cia; | |
2957 | if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)) | |
2958 | { | |
2959 | State.regs[REG_PC] += EXTEND8 (D8); | |
2960 | nia = PC; | |
2961 | } | |
2962 | } | |
2963 | ||
2964 | ||
2965 | // 1100 0110 d8......; bcc (d8,PC) (d8 is sign-extended) | |
2966 | 8.0xc6+8.D8:S1:::bcc | |
2967 | "bcc" | |
2968 | *mn10300 | |
d2b02ab2 JL |
2969 | // start-sanitize-am33 |
2970 | *am33 | |
2971 | // end-sanitize-am33 | |
7986ea13 JJ |
2972 | { |
2973 | // OP_C600 (); | |
2974 | PC = cia; | |
2975 | if (!(PSW & PSW_C)) | |
2976 | { | |
2977 | State.regs[REG_PC] += EXTEND8 (D8); | |
2978 | nia = PC; | |
2979 | } | |
2980 | } | |
2981 | ||
2982 | ||
2983 | // 1100 0101 d8......; bls (d8,PC) (d8 is sign-extended) | |
2984 | 8.0xc7+8.D8:S1:::bls | |
2985 | "bls" | |
2986 | *mn10300 | |
d2b02ab2 JL |
2987 | // start-sanitize-am33 |
2988 | *am33 | |
2989 | // end-sanitize-am33 | |
7986ea13 JJ |
2990 | { |
2991 | // OP_C700 (); | |
2992 | PC = cia; | |
2993 | if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0) | |
2994 | { | |
2995 | State.regs[REG_PC] += EXTEND8 (D8); | |
2996 | nia = PC; | |
2997 | } | |
2998 | } | |
2999 | ||
3000 | ||
3001 | // 1100 0100 d8......; bcs (d8,PC) (d8 is sign-extended) | |
3002 | 8.0xc4+8.D8:S1:::bcs | |
3003 | "bcs" | |
3004 | *mn10300 | |
d2b02ab2 JL |
3005 | // start-sanitize-am33 |
3006 | *am33 | |
3007 | // end-sanitize-am33 | |
7986ea13 JJ |
3008 | { |
3009 | // OP_C400 (); | |
3010 | PC = cia; | |
3011 | if (PSW & PSW_C) | |
3012 | { | |
3013 | State.regs[REG_PC] += EXTEND8 (D8); | |
3014 | nia = PC; | |
3015 | } | |
3016 | } | |
3017 | ||
3018 | ||
3019 | // 1111 1000 1110 1000 d8......; bvc (d8,PC) (d8 is sign-extended) | |
3020 | 8.0xf8+8.0xe8+8.D8:D1:::bvc | |
3021 | "bvc" | |
3022 | *mn10300 | |
d2b02ab2 JL |
3023 | // start-sanitize-am33 |
3024 | *am33 | |
3025 | // end-sanitize-am33 | |
7986ea13 JJ |
3026 | { |
3027 | // OP_F8E800 (); | |
3028 | PC = cia; | |
3029 | if (!(PSW & PSW_V)) | |
3030 | { | |
3031 | State.regs[REG_PC] += EXTEND8 (D8); | |
3032 | nia = PC; | |
3033 | } | |
3034 | } | |
3035 | ||
3036 | ||
3037 | // 1111 1000 1110 1001 d8......; bvs (d8,PC) (d8 is sign-extended) | |
3038 | 8.0xf8+8.0xe9+8.D8:D1:::bvs | |
3039 | "bvs" | |
3040 | *mn10300 | |
d2b02ab2 JL |
3041 | // start-sanitize-am33 |
3042 | *am33 | |
3043 | // end-sanitize-am33 | |
7986ea13 JJ |
3044 | { |
3045 | // OP_F8E900 (); | |
3046 | PC = cia; | |
3047 | if (PSW & PSW_V) | |
3048 | { | |
3049 | State.regs[REG_PC] += EXTEND8 (D8); | |
3050 | nia = PC; | |
3051 | } | |
3052 | } | |
3053 | ||
3054 | ||
3055 | // 1111 1000 1110 1010 d8......; bnc (d8,PC) (d8 is sign-extended) | |
3056 | 8.0xf8+8.0xea+8.D8:D1:::bnc | |
3057 | "bnc" | |
3058 | *mn10300 | |
d2b02ab2 JL |
3059 | // start-sanitize-am33 |
3060 | *am33 | |
3061 | // end-sanitize-am33 | |
7986ea13 JJ |
3062 | { |
3063 | // OP_F8EA00 (); | |
3064 | PC = cia; | |
3065 | if (!(PSW & PSW_N)) | |
3066 | { | |
3067 | State.regs[REG_PC] += EXTEND8 (D8); | |
3068 | nia = PC; | |
3069 | } | |
3070 | } | |
3071 | ||
3072 | ||
3073 | // 1111 1000 1110 1010 d8......; bns (d8,PC) (d8 is sign-extended) | |
3074 | 8.0xf8+8.0xeb+8.D8:D1:::bns | |
3075 | "bns" | |
3076 | *mn10300 | |
d2b02ab2 JL |
3077 | // start-sanitize-am33 |
3078 | *am33 | |
3079 | // end-sanitize-am33 | |
7986ea13 JJ |
3080 | { |
3081 | // OP_F8EB00 (); | |
3082 | PC = cia; | |
3083 | if (PSW & PSW_N) | |
3084 | { | |
3085 | State.regs[REG_PC] += EXTEND8 (D8); | |
3086 | nia = PC; | |
3087 | } | |
3088 | } | |
3089 | ||
3090 | ||
3091 | // 1100 1010 d8......; bra (d8,PC) (d8 is sign-extended) | |
3092 | 8.0xca+8.D8:S1:::bra | |
3093 | "bra" | |
3094 | *mn10300 | |
d2b02ab2 JL |
3095 | // start-sanitize-am33 |
3096 | *am33 | |
3097 | // end-sanitize-am33 | |
7986ea13 JJ |
3098 | { |
3099 | // OP_CA00 (); | |
3100 | PC = cia; | |
3101 | State.regs[REG_PC] += EXTEND8 (D8); | |
3102 | nia = PC; | |
3103 | } | |
3104 | ||
3105 | ||
3106 | // 1101 1000; leq | |
3107 | 8.0xd8:S0:::leq | |
3108 | "leq" | |
3109 | *mn10300 | |
d2b02ab2 JL |
3110 | // start-sanitize-am33 |
3111 | *am33 | |
3112 | // end-sanitize-am33 | |
7986ea13 JJ |
3113 | { |
3114 | // OP_D8 (); | |
3115 | PC = cia; | |
3116 | if (PSW & PSW_Z) | |
3117 | { | |
3118 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
3119 | nia = PC; | |
3120 | } | |
3121 | } | |
3122 | ||
3123 | ||
3124 | // 1101 1001; lne | |
3125 | 8.0xd9:S0:::lne | |
3126 | "lne" | |
3127 | *mn10300 | |
d2b02ab2 JL |
3128 | // start-sanitize-am33 |
3129 | *am33 | |
3130 | // end-sanitize-am33 | |
7986ea13 JJ |
3131 | { |
3132 | // OP_D9 (); | |
3133 | PC = cia; | |
3134 | if (!(PSW & PSW_Z)) | |
3135 | { | |
3136 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
3137 | nia = PC; | |
3138 | } | |
3139 | } | |
3140 | ||
3141 | ||
3142 | // 1101 0001; lgt | |
3143 | 8.0xd1:S0:::lgt | |
3144 | "lgt" | |
3145 | *mn10300 | |
d2b02ab2 JL |
3146 | // start-sanitize-am33 |
3147 | *am33 | |
3148 | // end-sanitize-am33 | |
7986ea13 JJ |
3149 | { |
3150 | // OP_D1 (); | |
3151 | PC = cia; | |
3152 | if (!((PSW & PSW_Z) | |
3153 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))) | |
3154 | { | |
3155 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
3156 | nia = PC; | |
3157 | } | |
3158 | } | |
3159 | ||
3160 | ||
3161 | // 1101 0010; lge | |
3162 | 8.0xd2:S0:::lge | |
3163 | "lge" | |
3164 | *mn10300 | |
d2b02ab2 JL |
3165 | // start-sanitize-am33 |
3166 | *am33 | |
3167 | // end-sanitize-am33 | |
7986ea13 JJ |
3168 | { |
3169 | // OP_D2 (); | |
3170 | PC = cia; | |
3171 | if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) | |
3172 | { | |
3173 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
3174 | nia = PC; | |
3175 | } | |
3176 | } | |
3177 | ||
3178 | ||
3179 | // 1101 0011; lle | |
3180 | 8.0xd3:S0:::lle | |
3181 | "lle" | |
3182 | *mn10300 | |
d2b02ab2 JL |
3183 | // start-sanitize-am33 |
3184 | *am33 | |
3185 | // end-sanitize-am33 | |
7986ea13 JJ |
3186 | { |
3187 | // OP_D3 (); | |
3188 | PC = cia; | |
3189 | if ((PSW & PSW_Z) | |
3190 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) | |
3191 | { | |
3192 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
3193 | nia = PC; | |
3194 | } | |
3195 | } | |
3196 | ||
3197 | ||
3198 | // 1101 0000; llt | |
3199 | 8.0xd0:S0:::llt | |
3200 | "llt" | |
3201 | *mn10300 | |
d2b02ab2 JL |
3202 | // start-sanitize-am33 |
3203 | *am33 | |
3204 | // end-sanitize-am33 | |
7986ea13 JJ |
3205 | { |
3206 | // OP_D0 (); | |
3207 | PC = cia; | |
3208 | if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)) | |
3209 | { | |
3210 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
3211 | nia = PC; | |
3212 | } | |
3213 | } | |
3214 | ||
3215 | ||
3216 | // 1101 0101; lhi | |
3217 | 8.0xd5:S0:::lhi | |
3218 | "lhi" | |
3219 | *mn10300 | |
d2b02ab2 JL |
3220 | // start-sanitize-am33 |
3221 | *am33 | |
3222 | // end-sanitize-am33 | |
7986ea13 JJ |
3223 | { |
3224 | // OP_D5 (); | |
3225 | PC = cia; | |
3226 | if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)) | |
3227 | { | |
3228 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
3229 | nia = PC; | |
3230 | } | |
3231 | } | |
3232 | ||
3233 | ||
3234 | // 1101 0110; lcc | |
3235 | 8.0xd6:S0:::lcc | |
3236 | "lcc" | |
3237 | *mn10300 | |
d2b02ab2 JL |
3238 | // start-sanitize-am33 |
3239 | *am33 | |
3240 | // end-sanitize-am33 | |
7986ea13 JJ |
3241 | { |
3242 | // OP_D6 (); | |
3243 | PC = cia; | |
3244 | if (!(PSW & PSW_C)) | |
3245 | { | |
3246 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
3247 | nia = PC; | |
3248 | } | |
3249 | } | |
3250 | ||
3251 | ||
3252 | // 1101 0111; lls | |
3253 | 8.0xd7:S0:::lls | |
3254 | "lls" | |
3255 | *mn10300 | |
d2b02ab2 JL |
3256 | // start-sanitize-am33 |
3257 | *am33 | |
3258 | // end-sanitize-am33 | |
7986ea13 JJ |
3259 | { |
3260 | // OP_D7 (); | |
3261 | PC = cia; | |
3262 | if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0) | |
3263 | { | |
3264 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
3265 | nia = PC; | |
3266 | } | |
3267 | } | |
3268 | ||
3269 | ||
3270 | // 1101 0100; lcs | |
3271 | 8.0xd4:S0:::lcs | |
3272 | "lcs" | |
3273 | *mn10300 | |
d2b02ab2 JL |
3274 | // start-sanitize-am33 |
3275 | *am33 | |
3276 | // end-sanitize-am33 | |
7986ea13 JJ |
3277 | { |
3278 | // OP_D4 (); | |
3279 | PC = cia; | |
3280 | if (PSW & PSW_C) | |
3281 | { | |
3282 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
3283 | nia = PC; | |
3284 | } | |
3285 | } | |
3286 | ||
3287 | ||
3288 | // 1101 1010; lra | |
3289 | 8.0xda:S0:::lra | |
3290 | "lra" | |
3291 | *mn10300 | |
d2b02ab2 JL |
3292 | // start-sanitize-am33 |
3293 | *am33 | |
3294 | // end-sanitize-am33 | |
7986ea13 JJ |
3295 | { |
3296 | // OP_DA (); | |
3297 | PC = cia; | |
3298 | State.regs[REG_PC] = State.regs[REG_LAR] - 4; | |
3299 | nia = PC; | |
3300 | } | |
3301 | ||
3302 | ||
3303 | // 1101 1010; setlb | |
3304 | 8.0xdb:S0:::setlb | |
3305 | "setlb" | |
3306 | *mn10300 | |
d2b02ab2 JL |
3307 | // start-sanitize-am33 |
3308 | *am33 | |
3309 | // end-sanitize-am33 | |
7986ea13 JJ |
3310 | { |
3311 | // OP_DB (); | |
3312 | PC = cia; | |
3313 | State.regs[REG_LIR] = load_word (State.regs[REG_PC] + 1); | |
3314 | State.regs[REG_LAR] = State.regs[REG_PC] + 5; | |
3315 | } | |
3316 | ||
3317 | ||
3318 | // 1111 0000 1111 01An; jmp (An) | |
3319 | 8.0xf0+4.0xf,01,2.AN0:D0:::jmp | |
3320 | "jmp" | |
3321 | *mn10300 | |
d2b02ab2 JL |
3322 | // start-sanitize-am33 |
3323 | *am33 | |
3324 | // end-sanitize-am33 | |
7986ea13 JJ |
3325 | { |
3326 | // OP_F0F4 (); | |
3327 | PC = State.regs[REG_A0 + AN0]; | |
3328 | nia = PC; | |
3329 | } | |
3330 | ||
3331 | ||
3332 | // 1100 1100 d16.....; jmp (d16,PC) (d16 is sign-extended.) | |
3333 | 8.0xcc+8.D16A+8.D16B:S2:::jmp | |
3334 | "jmp" | |
3335 | *mn10300 | |
d2b02ab2 JL |
3336 | // start-sanitize-am33 |
3337 | *am33 | |
3338 | // end-sanitize-am33 | |
7986ea13 JJ |
3339 | { |
3340 | // OP_CC0000 (); | |
3341 | PC = cia + EXTEND16(FETCH16(D16A, D16B)); | |
3342 | nia = PC; | |
3343 | } | |
3344 | ||
3345 | ||
3346 | // 1101 1100 d32........; jmp (d32, PC) | |
3347 | 8.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp | |
3348 | "jmp" | |
3349 | *mn10300 | |
d2b02ab2 JL |
3350 | // start-sanitize-am33 |
3351 | *am33 | |
3352 | // end-sanitize-am33 | |
7986ea13 JJ |
3353 | { |
3354 | // OP_DC000000 (); | |
3355 | PC = cia + FETCH32(D32A, D32B, D32C, D32D); | |
3356 | nia = PC; | |
3357 | } | |
3358 | ||
3359 | ||
d2b02ab2 JL |
3360 | // 1111 0000 1111 00An; calls (An) |
3361 | 8.0xf0+4.0xf,00,2.AN0:D0:::calls | |
3362 | "calls" | |
7986ea13 | 3363 | *mn10300 |
d2b02ab2 JL |
3364 | // start-sanitize-am33 |
3365 | *am33 | |
3366 | // end-sanitize-am33 | |
7986ea13 | 3367 | { |
d2b02ab2 | 3368 | // OP_F0F0 (); |
7986ea13 | 3369 | unsigned int next_pc, sp; |
7986ea13 JJ |
3370 | |
3371 | PC = cia; | |
3372 | sp = State.regs[REG_SP]; | |
d2b02ab2 | 3373 | next_pc = State.regs[REG_PC] + 2; |
7986ea13 | 3374 | store_word(sp, next_pc); |
d2b02ab2 JL |
3375 | State.regs[REG_MDR] = next_pc; |
3376 | State.regs[REG_PC] = State.regs[REG_A0 + AN0]; | |
3377 | nia = PC; | |
3378 | } | |
7986ea13 | 3379 | |
7986ea13 | 3380 | |
d2b02ab2 JL |
3381 | // 1111 1010 1111 1111 d16.....; calls (d16,PC) (d16 is sign-extended.) |
3382 | 8.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls | |
3383 | "calls" | |
3384 | *mn10300 | |
3385 | // start-sanitize-am33 | |
3386 | *am33 | |
3387 | // end-sanitize-am33 | |
3388 | { | |
3389 | // OP_FAFF0000 (); | |
3390 | unsigned int next_pc, sp; | |
7986ea13 | 3391 | |
d2b02ab2 JL |
3392 | PC = cia; |
3393 | sp = State.regs[REG_SP]; | |
3394 | next_pc = State.regs[REG_PC] + 4; | |
3395 | store_word(sp, next_pc); | |
7986ea13 JJ |
3396 | State.regs[REG_MDR] = next_pc; |
3397 | State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B)); | |
3398 | nia = PC; | |
3399 | } | |
3400 | ||
3401 | ||
d2b02ab2 JL |
3402 | // 1111 1100 1111 1111 d32.....; calls (d32,PC) |
3403 | 8.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls | |
3404 | "calls" | |
7986ea13 | 3405 | *mn10300 |
d2b02ab2 JL |
3406 | // start-sanitize-am33 |
3407 | *am33 | |
3408 | // end-sanitize-am33 | |
7986ea13 | 3409 | { |
d2b02ab2 | 3410 | // OP_FCFF0000 (); |
7986ea13 JJ |
3411 | unsigned int next_pc, sp; |
3412 | ||
3413 | PC = cia; | |
3414 | sp = State.regs[REG_SP]; | |
3415 | next_pc = State.regs[REG_PC] + 6; | |
3416 | store_word(sp, next_pc); | |
3417 | State.regs[REG_MDR] = next_pc; | |
3418 | State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D); | |
3419 | nia = PC; | |
3420 | } | |
3421 | ||
3422 | ||
7986ea13 JJ |
3423 | // 1111 0000 1111 1100; rets |
3424 | 8.0xf0+8.0xfc:D0:::rets | |
3425 | "rets" | |
3426 | *mn10300 | |
d2b02ab2 JL |
3427 | // start-sanitize-am33 |
3428 | *am33 | |
3429 | // end-sanitize-am33 | |
7986ea13 JJ |
3430 | { |
3431 | // OP_F0FC (); | |
3432 | unsigned int sp; | |
3433 | ||
3434 | sp = State.regs[REG_SP]; | |
3435 | State.regs[REG_PC] = load_word(sp); | |
3436 | nia = PC; | |
3437 | } | |
3438 | ||
3439 | ||
3440 | // 1111 0000 1111 1101; rti | |
3441 | 8.0xf0+8.0xfd:D0:::rti | |
3442 | "rti" | |
3443 | *mn10300 | |
d2b02ab2 JL |
3444 | // start-sanitize-am33 |
3445 | *am33 | |
3446 | // end-sanitize-am33 | |
7986ea13 JJ |
3447 | { |
3448 | // OP_F0FD (); | |
3449 | unsigned int sp; | |
3450 | ||
3451 | sp = State.regs[REG_SP]; | |
3452 | PSW = load_half(sp); | |
3453 | State.regs[REG_PC] = load_word(sp+4); | |
3454 | State.regs[REG_SP] +=8; | |
3455 | nia = PC; | |
3456 | } | |
3457 | ||
3458 | ||
3459 | // 1111 0000 1111 1110; trap | |
3460 | 8.0xf0+8.0xfe:D0:::trap | |
3461 | "trap" | |
3462 | *mn10300 | |
d2b02ab2 JL |
3463 | // start-sanitize-am33 |
3464 | *am33 | |
3465 | // end-sanitize-am33 | |
7986ea13 JJ |
3466 | { |
3467 | // OP_F0FE (); | |
3468 | unsigned int sp, next_pc; | |
3469 | ||
3470 | PC = cia; | |
3471 | sp = State.regs[REG_SP]; | |
3472 | next_pc = State.regs[REG_PC] + 2; | |
3473 | store_word(sp, next_pc); | |
3474 | nia = PC; | |
3475 | } | |
3476 | ||
3477 | ||
3478 | // 1111 0000 1111 1111; rtm | |
3479 | 8.0xf0+8.0xff:D0:::rtm | |
3480 | "rtm" | |
3481 | *mn10300 | |
d2b02ab2 JL |
3482 | // start-sanitize-am33 |
3483 | *am33 | |
3484 | // end-sanitize-am33 | |
7986ea13 JJ |
3485 | { |
3486 | // OP_F0FF (); | |
3487 | PC = cia; | |
3488 | abort (); | |
3489 | } | |
3490 | ||
3491 | ||
3492 | // 1100 1011; nop | |
3493 | 8.0xcb:S0:::nop | |
3494 | "nop" | |
3495 | *mn10300 | |
d2b02ab2 JL |
3496 | // start-sanitize-am33 |
3497 | *am33 | |
3498 | // end-sanitize-am33 | |
7986ea13 JJ |
3499 | { |
3500 | // OP_CB (); | |
3501 | PC = cia; | |
3502 | } | |
3503 | ||
3504 | ||
3505 | // 1111 0101 0000 DmDn; udf20 Dm,Dn | |
3506 | 8.0xf5+4.0x0,2.DN1,2.DN0:D0:::putx | |
3507 | "putx" | |
3508 | *mn10300 | |
3509 | { | |
3510 | // OP_F500 (); | |
3511 | PC = cia; | |
3512 | State.regs[REG_MDRQ] = State.regs[REG_D0 + DN0]; | |
3513 | } | |
3514 | ||
3515 | ||
3516 | // 1111 0110 1111 DmDn; udf15 Dm,Dn | |
3517 | 8.0xf6+4.0xf,2.DM1,2.DN0:D0:::getx | |
3518 | "getx" | |
3519 | *mn10300 | |
d2b02ab2 JL |
3520 | // start-sanitize-am33 |
3521 | *am33 | |
3522 | // end-sanitize-am33 | |
7986ea13 JJ |
3523 | { |
3524 | // OP_F6F0 (); | |
3525 | int z, n; | |
3526 | ||
3527 | PC = cia; | |
3528 | z = (State.regs[REG_MDRQ] == 0); | |
3529 | n = ((State.regs[REG_MDRQ] & 0x80000000) != 0); | |
3530 | State.regs[REG_D0 + DN0] = State.regs[REG_MDRQ]; | |
3531 | ||
3532 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3533 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
3534 | } | |
3535 | ||
3536 | ||
3537 | // 1111 0110 0000 DmDn; udf00 Dm,Dn | |
3538 | 8.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq | |
3539 | "mulq" | |
3540 | *mn10300 | |
d2b02ab2 JL |
3541 | // start-sanitize-am33 |
3542 | *am33 | |
3543 | // end-sanitize-am33 | |
7986ea13 JJ |
3544 | { |
3545 | // OP_F600 (); | |
3546 | unsigned long long temp; | |
3547 | int n, z; | |
3548 | ||
3549 | PC = cia; | |
3550 | temp = ((signed64)(signed32)State.regs[REG_D0 + DN0] | |
3551 | * (signed64)(signed32)State.regs[REG_D0 + DM1]); | |
3552 | State.regs[REG_D0 + DN0] = temp & 0xffffffff; | |
3553 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3554 | z = (State.regs[REG_D0 + DN0] == 0); | |
3555 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
3556 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3557 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
3558 | } | |
3559 | ||
3560 | ||
3561 | // 1111 1001 0000 00Dn imm8....; udf00 imm8,Dn (imm8 is sign-extended.) | |
3562 | 8.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq | |
3563 | "mulq" | |
3564 | *mn10300 | |
d2b02ab2 JL |
3565 | // start-sanitize-am33 |
3566 | *am33 | |
3567 | // end-sanitize-am33 | |
7986ea13 JJ |
3568 | { |
3569 | // OP_F90000 (); | |
3570 | unsigned long long temp; | |
3571 | int n, z; | |
3572 | ||
3573 | PC = cia; | |
3574 | temp = ((signed64)(signed32)State.regs[REG_D0 + DN0] | |
3575 | * (signed64)(signed32)EXTEND8 (IMM8)); | |
3576 | State.regs[REG_D0 + DN0] = temp & 0xffffffff; | |
3577 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3578 | z = (State.regs[REG_D0 + DN0] == 0); | |
3579 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
3580 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3581 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
3582 | } | |
3583 | ||
3584 | ||
3585 | // 1111 1011 0000 00Dn imm16...; udf00 imm16,Dn (imm16 is sign-extended.) | |
3586 | 8.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq | |
3587 | "mulq" | |
3588 | *mn10300 | |
d2b02ab2 JL |
3589 | // start-sanitize-am33 |
3590 | *am33 | |
3591 | // end-sanitize-am33 | |
7986ea13 JJ |
3592 | { |
3593 | // OP_FB000000 (); | |
3594 | unsigned long long temp; | |
3595 | int n, z; | |
3596 | ||
3597 | PC = cia; | |
3598 | temp = ((signed64)(signed32)State.regs[REG_D0 + DN0] | |
3599 | * (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B))); | |
3600 | State.regs[REG_D0 + DN0] = temp & 0xffffffff; | |
3601 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3602 | z = (State.regs[REG_D0 + DN0] == 0); | |
3603 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
3604 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3605 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
3606 | } | |
3607 | ||
3608 | ||
3609 | // 1111 1101 0000 00Dn imm32...; udf00 imm32,Dn | |
3610 | 8.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq | |
3611 | "mulq" | |
3612 | *mn10300 | |
d2b02ab2 JL |
3613 | // start-sanitize-am33 |
3614 | *am33 | |
3615 | // end-sanitize-am33 | |
7986ea13 JJ |
3616 | { |
3617 | // OP_FD000000 (); | |
3618 | unsigned long long temp; | |
3619 | int n, z; | |
3620 | ||
3621 | PC = cia; | |
3622 | temp = ((signed64)(signed32)State.regs[REG_D0 + DN0] | |
3623 | * (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D))); | |
3624 | State.regs[REG_D0 + DN0] = temp & 0xffffffff; | |
3625 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3626 | z = (State.regs[REG_D0 + DN0] == 0); | |
3627 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
3628 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3629 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
3630 | } | |
3631 | ||
3632 | ||
3633 | // 1111 0110 0001 DmDn; udf01 Dm,Dn | |
3634 | 8.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu | |
3635 | "mulqu" | |
3636 | *mn10300 | |
d2b02ab2 JL |
3637 | // start-sanitize-am33 |
3638 | *am33 | |
3639 | // end-sanitize-am33 | |
7986ea13 JJ |
3640 | { |
3641 | // OP_F610 (); | |
3642 | unsigned long long temp; | |
3643 | int n, z; | |
3644 | ||
3645 | PC = cia; | |
3646 | temp = ((unsigned64) State.regs[REG_D0 + DN0] | |
3647 | * (unsigned64) State.regs[REG_D0 + DM1]); | |
3648 | State.regs[REG_D0 + DN0] = temp & 0xffffffff; | |
3649 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3650 | z = (State.regs[REG_D0 + DN0] == 0); | |
3651 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
3652 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3653 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
3654 | } | |
3655 | ||
3656 | ||
3657 | // 1111 1001 0001 01Dn imm8....; udfu01 imm8,Dn (imm8 is zero-extended.) | |
3658 | 8.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu | |
3659 | "mulqu" | |
3660 | *mn10300 | |
d2b02ab2 JL |
3661 | // start-sanitize-am33 |
3662 | *am33 | |
3663 | // end-sanitize-am33 | |
7986ea13 JJ |
3664 | { |
3665 | // OP_F91400 (); | |
3666 | unsigned long long temp; | |
3667 | int n, z; | |
3668 | ||
3669 | PC = cia; | |
3670 | temp = ((unsigned64)State.regs[REG_D0 + DN0] | |
3671 | * (unsigned64)EXTEND8 (IMM8)); | |
3672 | State.regs[REG_D0 + DN0] = temp & 0xffffffff; | |
3673 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3674 | z = (State.regs[REG_D0 + DN0] == 0); | |
3675 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
3676 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3677 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
3678 | } | |
3679 | ||
3680 | ||
3681 | // 1111 1011 0001 01Dn imm16...; udfu01 imm16,Dn (imm16 is zero-extended.) | |
3682 | 8.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu | |
3683 | "mulqu" | |
3684 | *mn10300 | |
d2b02ab2 JL |
3685 | // start-sanitize-am33 |
3686 | *am33 | |
3687 | // end-sanitize-am33 | |
7986ea13 JJ |
3688 | { |
3689 | // OP_FB140000 (); | |
3690 | unsigned long long temp; | |
3691 | int n, z; | |
3692 | ||
3693 | PC = cia; | |
3694 | temp = ((unsigned64)State.regs[REG_D0 + DN0] | |
3695 | * (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B))); | |
3696 | State.regs[REG_D0 + DN0] = temp & 0xffffffff; | |
3697 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3698 | z = (State.regs[REG_D0 + DN0] == 0); | |
3699 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
3700 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3701 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
3702 | } | |
3703 | ||
3704 | ||
3705 | // 1111 1101 0001 01Dn imm32...; udfu01 imm32,Dn | |
3706 | 8.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu | |
3707 | "mulqu" | |
3708 | *mn10300 | |
d2b02ab2 JL |
3709 | // start-sanitize-am33 |
3710 | *am33 | |
3711 | // end-sanitize-am33 | |
7986ea13 JJ |
3712 | { |
3713 | // OP_FD140000 (); | |
3714 | unsigned long long temp; | |
3715 | int n, z; | |
3716 | ||
3717 | PC = cia; | |
3718 | temp = ((unsigned64)State.regs[REG_D0 + DN0] | |
3719 | * (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D))); | |
3720 | State.regs[REG_D0 + DN0] = temp & 0xffffffff; | |
3721 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3722 | z = (State.regs[REG_D0 + DN0] == 0); | |
3723 | n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0; | |
3724 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3725 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
3726 | } | |
3727 | ||
3728 | ||
3729 | // 1111 0110 0100 DmDn; udf04 Dm,Dn | |
3730 | 8.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16 | |
3731 | "sat16" | |
3732 | *mn10300 | |
d2b02ab2 JL |
3733 | // start-sanitize-am33 |
3734 | *am33 | |
3735 | // end-sanitize-am33 | |
7986ea13 JJ |
3736 | { |
3737 | // OP_F640 (); | |
3738 | int temp; | |
3739 | ||
3740 | PC = cia; | |
3741 | temp = State.regs[REG_D0 + DM1]; | |
3742 | temp = (temp > 0x7fff ? 0x7fff : temp); | |
3743 | temp = (temp < -0x8000 ? -0x8000 : temp); | |
3744 | State.regs[REG_D0 + DN0] = temp; | |
3745 | } | |
3746 | ||
3747 | ||
3748 | // 1111 0110 0101 DmDn; udf05 Dm,Dn | |
3749 | 8.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24 | |
3750 | "sat24" | |
3751 | *mn10300 | |
d2b02ab2 JL |
3752 | // start-sanitize-am33 |
3753 | *am33 | |
3754 | // end-sanitize-am33 | |
7986ea13 JJ |
3755 | { |
3756 | // OP_F650 (); | |
3757 | int temp; | |
3758 | ||
3759 | PC = cia; | |
3760 | temp = State.regs[REG_D0 + DM1]; | |
3761 | temp = (temp > 0x7fffff ? 0x7fffff : temp); | |
3762 | temp = (temp < -0x800000 ? -0x800000 : temp); | |
3763 | State.regs[REG_D0 + DN0] = temp; | |
3764 | } | |
3765 | ||
3766 | ||
3767 | // 1111 0110 0111 DmDn; udf07 Dm,Dn | |
3768 | 8.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch | |
3769 | "bsch" | |
3770 | *mn10300 | |
d2b02ab2 JL |
3771 | // start-sanitize-am33 |
3772 | *am33 | |
3773 | // end-sanitize-am33 | |
7986ea13 JJ |
3774 | { |
3775 | // OP_F670 (); | |
3776 | int temp, c; | |
3777 | ||
3778 | PC = cia; | |
3779 | temp = State.regs[REG_D0 + DM1]; | |
3780 | temp <<= (State.regs[REG_D0 + DN0] & 0x1f); | |
3781 | c = (temp != 0 ? 1 : 0); | |
3782 | PSW &= ~(PSW_C); | |
3783 | PSW |= (c ? PSW_C : 0); | |
3784 | } | |
3785 | ||
3786 | ||
d2b02ab2 JL |
3787 | // 1111 0000 1100 0000; syscall |
3788 | 8.0xf0+8.0xc0:D0:::syscall | |
7986ea13 JJ |
3789 | "syscall" |
3790 | *mn10300 | |
d2b02ab2 JL |
3791 | // start-sanitize-am33 |
3792 | *am33 | |
3793 | // end-sanitize-am33 | |
7986ea13 | 3794 | { |
d2b02ab2 | 3795 | // OP_F0C0 (); |
7986ea13 JJ |
3796 | PC = cia; |
3797 | do_syscall (); | |
3798 | } | |
3799 | ||
3800 | ||
3801 | // 1111 1111; break | |
3802 | 8.0xff:S0:::break | |
3803 | "break" | |
3804 | *mn10300 | |
d2b02ab2 JL |
3805 | // start-sanitize-am33 |
3806 | *am33 | |
3807 | // end-sanitize-am33 | |
7986ea13 JJ |
3808 | { |
3809 | // OP_FF (); | |
3810 | PC = cia; | |
3811 | // State.exception = SIGTRAP; | |
3812 | sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); | |
3813 | PC -= 1; | |
3814 | } | |
d2b02ab2 JL |
3815 | |
3816 | // 1100 1110 regs....; movm (SP),regs | |
3817 | 8.0xce+8.REGS:S1:::movm | |
3818 | "movm" | |
3819 | *mn10300 | |
3820 | // start-sanitize-am33 | |
3821 | *am33 | |
3822 | // end-sanitize-am33 | |
3823 | { | |
3824 | // OP_CE00 (); | |
3825 | unsigned long sp = State.regs[REG_SP]; | |
3826 | unsigned long mask; | |
3827 | ||
3828 | PC = cia; | |
3829 | mask = REGS; | |
3830 | ||
3831 | if (mask & 0x8) | |
3832 | { | |
3833 | sp += 4; | |
3834 | State.regs[REG_LAR] = load_word (sp); | |
3835 | sp += 4; | |
3836 | State.regs[REG_LIR] = load_word (sp); | |
3837 | sp += 4; | |
3838 | State.regs[REG_MDR] = load_word (sp); | |
3839 | sp += 4; | |
3840 | State.regs[REG_A0 + 1] = load_word (sp); | |
3841 | sp += 4; | |
3842 | State.regs[REG_A0] = load_word (sp); | |
3843 | sp += 4; | |
3844 | State.regs[REG_D0 + 1] = load_word (sp); | |
3845 | sp += 4; | |
3846 | State.regs[REG_D0] = load_word (sp); | |
3847 | sp += 4; | |
3848 | } | |
3849 | ||
3850 | if (mask & 0x10) | |
3851 | { | |
3852 | State.regs[REG_A0 + 3] = load_word (sp); | |
3853 | sp += 4; | |
3854 | } | |
3855 | ||
3856 | if (mask & 0x20) | |
3857 | { | |
3858 | State.regs[REG_A0 + 2] = load_word (sp); | |
3859 | sp += 4; | |
3860 | } | |
3861 | ||
3862 | if (mask & 0x40) | |
3863 | { | |
3864 | State.regs[REG_D0 + 3] = load_word (sp); | |
3865 | sp += 4; | |
3866 | } | |
3867 | ||
3868 | if (mask & 0x80) | |
3869 | { | |
3870 | State.regs[REG_D0 + 2] = load_word (sp); | |
3871 | sp += 4; | |
3872 | } | |
3873 | ||
3874 | /* start-sanitize-am33 */ | |
3875 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33) | |
3876 | { | |
3877 | if (mask & 0x1) | |
3878 | { | |
3879 | /* Need to restore MDQR, MCRH, MCRL, and MCVF */ | |
3880 | sp += 16; | |
3881 | State.regs[REG_E0 + 1] = load_word (sp); | |
3882 | sp += 4; | |
3883 | State.regs[REG_E0 + 0] = load_word (sp); | |
3884 | sp += 4; | |
3885 | } | |
3886 | ||
3887 | if (mask & 0x2) | |
3888 | { | |
3889 | State.regs[REG_E0 + 7] = load_word (sp); | |
3890 | sp += 4; | |
3891 | State.regs[REG_E0 + 6] = load_word (sp); | |
3892 | sp += 4; | |
3893 | State.regs[REG_E0 + 5] = load_word (sp); | |
3894 | sp += 4; | |
3895 | State.regs[REG_E0 + 4] = load_word (sp); | |
3896 | sp += 4; | |
3897 | } | |
3898 | ||
3899 | if (mask & 0x4) | |
3900 | { | |
3901 | State.regs[REG_E0 + 3] = load_word (sp); | |
3902 | sp += 4; | |
3903 | State.regs[REG_E0 + 2] = load_word (sp); | |
3904 | sp += 4; | |
3905 | } | |
3906 | } | |
3907 | /* end-sanitize-am33 */ | |
3908 | ||
3909 | /* And make sure to update the stack pointer. */ | |
3910 | State.regs[REG_SP] = sp; | |
3911 | } | |
3912 | ||
3913 | ||
3914 | // 1100 1111 regs....; movm regs,(SP) | |
3915 | 8.0xcf+8.REGS:S1a:::movm | |
3916 | "movm" | |
3917 | *mn10300 | |
3918 | // start-sanitize-am33 | |
3919 | *am33 | |
3920 | // end-sanitize-am33 | |
3921 | { | |
3922 | // OP_CF00 (); | |
3923 | unsigned long sp = State.regs[REG_SP]; | |
3924 | unsigned long mask; | |
3925 | ||
3926 | PC = cia; | |
3927 | mask = REGS; | |
3928 | ||
3929 | /* start-sanitize-am33 */ | |
3930 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33) | |
3931 | { | |
3932 | if (mask & 0x4) | |
3933 | { | |
3934 | sp -= 4; | |
3935 | store_word (sp, State.regs[REG_E0 + 2]); | |
3936 | sp -= 4; | |
3937 | store_word (sp, State.regs[REG_E0 + 3]); | |
3938 | } | |
3939 | ||
3940 | if (mask & 0x2) | |
3941 | { | |
3942 | sp -= 4; | |
3943 | store_word (sp, State.regs[REG_E0 + 4]); | |
3944 | sp -= 4; | |
3945 | store_word (sp, State.regs[REG_E0 + 5]); | |
3946 | sp -= 4; | |
3947 | store_word (sp, State.regs[REG_E0 + 6]); | |
3948 | sp -= 4; | |
3949 | store_word (sp, State.regs[REG_E0 + 7]); | |
3950 | } | |
3951 | ||
3952 | if (mask & 0x1) | |
3953 | { | |
3954 | sp -= 4; | |
3955 | store_word (sp, State.regs[REG_E0 + 0]); | |
3956 | sp -= 4; | |
3957 | store_word (sp, State.regs[REG_E0 + 1]); | |
3958 | sp -= 16; | |
3959 | /* Need to save MDQR, MCRH, MCRL, and MCVF */ | |
3960 | } | |
3961 | } | |
3962 | /* end-sanitize-am33 */ | |
3963 | ||
3964 | if (mask & 0x80) | |
3965 | { | |
3966 | sp -= 4; | |
3967 | store_word (sp, State.regs[REG_D0 + 2]); | |
3968 | } | |
3969 | ||
3970 | if (mask & 0x40) | |
3971 | { | |
3972 | sp -= 4; | |
3973 | store_word (sp, State.regs[REG_D0 + 3]); | |
3974 | } | |
3975 | ||
3976 | if (mask & 0x20) | |
3977 | { | |
3978 | sp -= 4; | |
3979 | store_word (sp, State.regs[REG_A0 + 2]); | |
3980 | } | |
3981 | ||
3982 | if (mask & 0x10) | |
3983 | { | |
3984 | sp -= 4; | |
3985 | store_word (sp, State.regs[REG_A0 + 3]); | |
3986 | } | |
3987 | ||
3988 | if (mask & 0x8) | |
3989 | { | |
3990 | sp -= 4; | |
3991 | store_word (sp, State.regs[REG_D0]); | |
3992 | sp -= 4; | |
3993 | store_word (sp, State.regs[REG_D0 + 1]); | |
3994 | sp -= 4; | |
3995 | store_word (sp, State.regs[REG_A0]); | |
3996 | sp -= 4; | |
3997 | store_word (sp, State.regs[REG_A0 + 1]); | |
3998 | sp -= 4; | |
3999 | store_word (sp, State.regs[REG_MDR]); | |
4000 | sp -= 4; | |
4001 | store_word (sp, State.regs[REG_LIR]); | |
4002 | sp -= 4; | |
4003 | store_word (sp, State.regs[REG_LAR]); | |
4004 | sp -= 4; | |
4005 | } | |
4006 | ||
4007 | /* And make sure to update the stack pointer. */ | |
4008 | State.regs[REG_SP] = sp; | |
4009 | } | |
4010 | ||
4011 | // 1100 1101 d16..... regs.... imm8....; | |
4012 | // call (d16,PC),regs,imm8 (d16 is sign-extended., imm8 is zero-extended.) | |
4013 | 8.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call | |
4014 | "call" | |
4015 | *mn10300 | |
4016 | // start-sanitize-am33 | |
4017 | *am33 | |
4018 | // end-sanitize-am33 | |
4019 | { | |
4020 | // OP_CD000000 (); | |
4021 | unsigned int next_pc, sp; | |
4022 | unsigned long mask; | |
4023 | ||
4024 | PC = cia; | |
4025 | sp = State.regs[REG_SP]; | |
4026 | next_pc = PC + 5; | |
4027 | store_word(sp, next_pc); | |
4028 | ||
4029 | mask = REGS; | |
4030 | ||
4031 | /* start-sanitize-am33 */ | |
4032 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33) | |
4033 | { | |
4034 | if (mask & 0x4) | |
4035 | { | |
4036 | sp -= 4; | |
4037 | store_word (sp, State.regs[REG_E0 + 2]); | |
4038 | sp -= 4; | |
4039 | store_word (sp, State.regs[REG_E0 + 3]); | |
4040 | } | |
4041 | ||
4042 | if (mask & 0x2) | |
4043 | { | |
4044 | sp -= 4; | |
4045 | store_word (sp, State.regs[REG_E0 + 4]); | |
4046 | sp -= 4; | |
4047 | store_word (sp, State.regs[REG_E0 + 5]); | |
4048 | sp -= 4; | |
4049 | store_word (sp, State.regs[REG_E0 + 6]); | |
4050 | sp -= 4; | |
4051 | store_word (sp, State.regs[REG_E0 + 7]); | |
4052 | } | |
4053 | ||
4054 | if (mask & 0x1) | |
4055 | { | |
4056 | sp -= 4; | |
4057 | store_word (sp, State.regs[REG_E0 + 0]); | |
4058 | sp -= 4; | |
4059 | store_word (sp, State.regs[REG_E0 + 1]); | |
4060 | sp -= 16; | |
4061 | /* Need to save MDQR, MCRH, MCRL, and MCVF */ | |
4062 | } | |
4063 | } | |
4064 | /* end-sanitize-am33 */ | |
4065 | ||
4066 | if (mask & 0x80) | |
4067 | { | |
4068 | sp -= 4; | |
4069 | store_word (sp, State.regs[REG_D0 + 2]); | |
4070 | } | |
4071 | ||
4072 | if (mask & 0x40) | |
4073 | { | |
4074 | sp -= 4; | |
4075 | store_word (sp, State.regs[REG_D0 + 3]); | |
4076 | } | |
4077 | ||
4078 | if (mask & 0x20) | |
4079 | { | |
4080 | sp -= 4; | |
4081 | store_word (sp, State.regs[REG_A0 + 2]); | |
4082 | } | |
4083 | ||
4084 | if (mask & 0x10) | |
4085 | { | |
4086 | sp -= 4; | |
4087 | store_word (sp, State.regs[REG_A0 + 3]); | |
4088 | } | |
4089 | ||
4090 | if (mask & 0x8) | |
4091 | { | |
4092 | sp -= 4; | |
4093 | store_word (sp, State.regs[REG_D0]); | |
4094 | sp -= 4; | |
4095 | store_word (sp, State.regs[REG_D0 + 1]); | |
4096 | sp -= 4; | |
4097 | store_word (sp, State.regs[REG_A0]); | |
4098 | sp -= 4; | |
4099 | store_word (sp, State.regs[REG_A0 + 1]); | |
4100 | sp -= 4; | |
4101 | store_word (sp, State.regs[REG_MDR]); | |
4102 | sp -= 4; | |
4103 | store_word (sp, State.regs[REG_LIR]); | |
4104 | sp -= 4; | |
4105 | store_word (sp, State.regs[REG_LAR]); | |
4106 | sp -= 4; | |
4107 | } | |
4108 | ||
4109 | /* Update the stack pointer, note that the register saves to do not | |
4110 | modify SP. The SP adjustment is derived totally from the imm8 | |
4111 | field. */ | |
4112 | State.regs[REG_SP] -= IMM8; | |
4113 | State.regs[REG_MDR] = next_pc; | |
4114 | State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B)); | |
4115 | nia = PC; | |
4116 | } | |
4117 | ||
4118 | ||
4119 | // 1101 1101 d32..... regs.... imm8....; | |
4120 | // call (d32,PC),regs,imm8 (imm8 is zero-extended.) | |
4121 | 8.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call | |
4122 | "call" | |
4123 | *mn10300 | |
4124 | // start-sanitize-am33 | |
4125 | *am33 | |
4126 | // end-sanitize-am33 | |
4127 | { | |
4128 | // op_DD000000(); | |
4129 | unsigned int next_pc, sp; | |
4130 | unsigned long mask; | |
4131 | ||
4132 | PC = cia; | |
4133 | sp = State.regs[REG_SP]; | |
4134 | next_pc = State.regs[REG_PC] + 7; | |
4135 | /* could assert that nia == next_pc here */ | |
4136 | store_word(sp, next_pc); | |
4137 | // store_byte(sp, next_pc & 0xff); | |
4138 | // store_byte(sp+1, (next_pc & 0xff00) >> 8 ); | |
4139 | // store_byte(sp+2, (next_pc & 0xff0000) >> 16 ); | |
4140 | // store_byte(sp+3, (next_pc & 0xff000000) >> 24); | |
4141 | ||
4142 | mask = REGS; | |
4143 | ||
4144 | /* start-sanitize-am33 */ | |
4145 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33) | |
4146 | { | |
4147 | if (mask & 0x4) | |
4148 | { | |
4149 | sp -= 4; | |
4150 | store_word (sp, State.regs[REG_E0 + 2]); | |
4151 | sp -= 4; | |
4152 | store_word (sp, State.regs[REG_E0 + 3]); | |
4153 | } | |
4154 | ||
4155 | if (mask & 0x2) | |
4156 | { | |
4157 | sp -= 4; | |
4158 | store_word (sp, State.regs[REG_E0 + 4]); | |
4159 | sp -= 4; | |
4160 | store_word (sp, State.regs[REG_E0 + 5]); | |
4161 | sp -= 4; | |
4162 | store_word (sp, State.regs[REG_E0 + 6]); | |
4163 | sp -= 4; | |
4164 | store_word (sp, State.regs[REG_E0 + 7]); | |
4165 | } | |
4166 | ||
4167 | if (mask & 0x1) | |
4168 | { | |
4169 | sp -= 4; | |
4170 | store_word (sp, State.regs[REG_E0 + 0]); | |
4171 | sp -= 4; | |
4172 | store_word (sp, State.regs[REG_E0 + 1]); | |
4173 | sp -= 16; | |
4174 | /* Need to save MDQR, MCRH, MCRL, and MCVF */ | |
4175 | } | |
4176 | } | |
4177 | /* end-sanitize-am33 */ | |
4178 | ||
4179 | if (mask & 0x80) | |
4180 | { | |
4181 | sp -= 4; | |
4182 | store_word (sp, State.regs[REG_D0 + 2]); | |
4183 | } | |
4184 | ||
4185 | if (mask & 0x40) | |
4186 | { | |
4187 | sp -= 4; | |
4188 | store_word (sp, State.regs[REG_D0 + 3]); | |
4189 | } | |
4190 | ||
4191 | if (mask & 0x20) | |
4192 | { | |
4193 | sp -= 4; | |
4194 | store_word (sp, State.regs[REG_A0 + 2]); | |
4195 | } | |
4196 | ||
4197 | if (mask & 0x10) | |
4198 | { | |
4199 | sp -= 4; | |
4200 | store_word (sp, State.regs[REG_A0 + 3]); | |
4201 | } | |
4202 | ||
4203 | if (mask & 0x8) | |
4204 | { | |
4205 | sp -= 4; | |
4206 | store_word (sp, State.regs[REG_D0]); | |
4207 | sp -= 4; | |
4208 | store_word (sp, State.regs[REG_D0 + 1]); | |
4209 | sp -= 4; | |
4210 | store_word (sp, State.regs[REG_A0]); | |
4211 | sp -= 4; | |
4212 | store_word (sp, State.regs[REG_A0 + 1]); | |
4213 | sp -= 4; | |
4214 | store_word (sp, State.regs[REG_MDR]); | |
4215 | sp -= 4; | |
4216 | store_word (sp, State.regs[REG_LIR]); | |
4217 | sp -= 4; | |
4218 | store_word (sp, State.regs[REG_LAR]); | |
4219 | sp -= 4; | |
4220 | } | |
4221 | ||
4222 | /* Update the stack pointer, note that the register saves to do not | |
4223 | modify SP. The SP adjustment is derived totally from the imm8 | |
4224 | field. */ | |
4225 | State.regs[REG_SP] -= IMM8; | |
4226 | State.regs[REG_MDR] = next_pc; | |
4227 | State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D); | |
4228 | nia = PC; | |
4229 | } | |
4230 | ||
4231 | ||
4232 | // 1101 1111 regs.... imm8....; ret regs,imm8 (imm8 is zero-extended.) | |
4233 | 8.0xdf+8.REGS+8.IMM8:S2:::ret | |
4234 | "ret" | |
4235 | *mn10300 | |
4236 | // start-sanitize-am33 | |
4237 | *am33 | |
4238 | // end-sanitize-am33 | |
4239 | { | |
4240 | // OP_DF0000 (); | |
4241 | unsigned int sp, offset; | |
4242 | unsigned long mask; | |
4243 | ||
4244 | PC = cia; | |
4245 | State.regs[REG_SP] += IMM8; | |
4246 | sp = State.regs[REG_SP]; | |
4247 | ||
4248 | offset = -4; | |
4249 | mask = REGS; | |
4250 | ||
4251 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33) | |
4252 | { | |
4253 | ||
4254 | if (mask & 0x4) | |
4255 | { | |
4256 | State.regs[REG_E0 + 2] = load_word (sp + offset); | |
4257 | offset -= 4; | |
4258 | State.regs[REG_E0 + 3] = load_word (sp + offset); | |
4259 | offset -= 4; | |
4260 | } | |
4261 | ||
4262 | if (mask & 0x2) | |
4263 | { | |
4264 | State.regs[REG_E0 + 4] = load_word (sp + offset); | |
4265 | offset -= 4; | |
4266 | State.regs[REG_E0 + 5] = load_word (sp + offset); | |
4267 | offset -= 4; | |
4268 | State.regs[REG_E0 + 6] = load_word (sp + offset); | |
4269 | offset -= 4; | |
4270 | State.regs[REG_E0 + 7] = load_word (sp + offset); | |
4271 | offset -= 4; | |
4272 | } | |
4273 | ||
4274 | if (mask & 0x1) | |
4275 | { | |
4276 | /* Need to restore MDQR, MCRH, MCRL, and MCVF */ | |
4277 | offset -= 16; | |
4278 | State.regs[REG_E0 + 0] = load_word (sp + offset); | |
4279 | offset -= 4; | |
4280 | State.regs[REG_E0 + 1] = load_word (sp + offset); | |
4281 | offset -= 4; | |
4282 | } | |
4283 | ||
4284 | } | |
4285 | ||
4286 | if (mask & 0x80) | |
4287 | { | |
4288 | State.regs[REG_D0 + 2] = load_word (sp + offset); | |
4289 | offset -= 4; | |
4290 | } | |
4291 | ||
4292 | if (mask & 0x40) | |
4293 | { | |
4294 | State.regs[REG_D0 + 3] = load_word (sp + offset); | |
4295 | offset -= 4; | |
4296 | } | |
4297 | ||
4298 | if (mask & 0x20) | |
4299 | { | |
4300 | State.regs[REG_A0 + 2] = load_word (sp + offset); | |
4301 | offset -= 4; | |
4302 | } | |
4303 | ||
4304 | if (mask & 0x10) | |
4305 | { | |
4306 | State.regs[REG_A0 + 3] = load_word (sp + offset); | |
4307 | offset -= 4; | |
4308 | } | |
4309 | ||
4310 | if (mask & 0x8) | |
4311 | { | |
4312 | State.regs[REG_D0] = load_word (sp + offset); | |
4313 | offset -= 4; | |
4314 | State.regs[REG_D0 + 1] = load_word (sp + offset); | |
4315 | offset -= 4; | |
4316 | State.regs[REG_A0] = load_word (sp + offset); | |
4317 | offset -= 4; | |
4318 | State.regs[REG_A0 + 1] = load_word (sp + offset); | |
4319 | offset -= 4; | |
4320 | State.regs[REG_MDR] = load_word (sp + offset); | |
4321 | offset -= 4; | |
4322 | State.regs[REG_LIR] = load_word (sp + offset); | |
4323 | offset -= 4; | |
4324 | State.regs[REG_LAR] = load_word (sp + offset); | |
4325 | offset -= 4; | |
4326 | } | |
4327 | ||
4328 | /* Restore the PC value. */ | |
4329 | State.regs[REG_PC] = load_word(sp); | |
4330 | nia = PC; | |
4331 | } | |
4332 | ||
4333 | ||
4334 | // 1101 1110 regs.... imm8....; retf regs,imm8 (imm8 is zero-extended.) | |
4335 | 8.0xde+8.REGS+8.IMM8:S2:::retf | |
4336 | "retf" | |
4337 | *mn10300 | |
4338 | // start-sanitize-am33 | |
4339 | *am33 | |
4340 | // end-sanitize-am33 | |
4341 | { | |
4342 | // OP_DE0000 (); | |
4343 | unsigned int sp, offset; | |
4344 | unsigned long mask; | |
4345 | ||
4346 | PC = cia; | |
4347 | State.regs[REG_SP] += IMM8; | |
4348 | sp = State.regs[REG_SP]; | |
4349 | State.regs[REG_PC] = State.regs[REG_MDR] - 3; | |
4350 | ||
4351 | offset = -4; | |
4352 | mask = REGS; | |
4353 | ||
4354 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33) | |
4355 | { | |
4356 | ||
4357 | if (mask & 0x4) | |
4358 | { | |
4359 | State.regs[REG_E0 + 2] = load_word (sp + offset); | |
4360 | offset -= 4; | |
4361 | State.regs[REG_E0 + 3] = load_word (sp + offset); | |
4362 | offset -= 4; | |
4363 | } | |
4364 | ||
4365 | if (mask & 0x2) | |
4366 | { | |
4367 | State.regs[REG_E0 + 4] = load_word (sp + offset); | |
4368 | offset -= 4; | |
4369 | State.regs[REG_E0 + 5] = load_word (sp + offset); | |
4370 | offset -= 4; | |
4371 | State.regs[REG_E0 + 6] = load_word (sp + offset); | |
4372 | offset -= 4; | |
4373 | State.regs[REG_E0 + 7] = load_word (sp + offset); | |
4374 | offset -= 4; | |
4375 | } | |
4376 | ||
4377 | if (mask & 0x1) | |
4378 | { | |
4379 | /* Need to restore MDQR, MCRH, MCRL, and MCVF */ | |
4380 | offset -= 16; | |
4381 | State.regs[REG_E0 + 0] = load_word (sp + offset); | |
4382 | offset -= 4; | |
4383 | State.regs[REG_E0 + 1] = load_word (sp + offset); | |
4384 | offset -= 4; | |
4385 | } | |
4386 | ||
4387 | } | |
4388 | ||
4389 | if (mask & 0x80) | |
4390 | { | |
4391 | State.regs[REG_D0 + 2] = load_word (sp + offset); | |
4392 | offset -= 4; | |
4393 | } | |
4394 | ||
4395 | if (mask & 0x40) | |
4396 | { | |
4397 | State.regs[REG_D0 + 3] = load_word (sp + offset); | |
4398 | offset -= 4; | |
4399 | } | |
4400 | ||
4401 | if (mask & 0x20) | |
4402 | { | |
4403 | State.regs[REG_A0 + 2] = load_word (sp + offset); | |
4404 | offset -= 4; | |
4405 | } | |
4406 | ||
4407 | if (mask & 0x10) | |
4408 | { | |
4409 | State.regs[REG_A0 + 3] = load_word (sp + offset); | |
4410 | offset -= 4; | |
4411 | } | |
4412 | ||
4413 | if (mask & 0x8) | |
4414 | { | |
4415 | State.regs[REG_D0] = load_word (sp + offset); | |
4416 | offset -= 4; | |
4417 | State.regs[REG_D0 + 1] = load_word (sp + offset); | |
4418 | offset -= 4; | |
4419 | State.regs[REG_A0] = load_word (sp + offset); | |
4420 | offset -= 4; | |
4421 | State.regs[REG_A0 + 1] = load_word (sp + offset); | |
4422 | offset -= 4; | |
4423 | State.regs[REG_MDR] = load_word (sp + offset); | |
4424 | offset -= 4; | |
4425 | State.regs[REG_LIR] = load_word (sp + offset); | |
4426 | offset -= 4; | |
4427 | State.regs[REG_LAR] = load_word (sp + offset); | |
4428 | offset -= 4; | |
4429 | } | |
4430 | } | |
4431 | ||
4432 | // start-sanitize-am33 | |
4433 | :include::am33:am33.igen | |
4434 | // end-sanitize-am33 |