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c906108c SS |
1 | #include <stdio.h> |
2 | #include <ctype.h> | |
3 | #include "ansidecl.h" | |
4 | #include "callback.h" | |
5 | #include "opcode/mn10300.h" | |
6 | #include <limits.h> | |
7 | #include "remote-sim.h" | |
8 | #include "bfd.h" | |
9 | ||
10 | #ifndef INLINE | |
11 | #ifdef __GNUC__ | |
12 | #define INLINE inline | |
13 | #else | |
14 | #define INLINE | |
15 | #endif | |
16 | #endif | |
17 | ||
18 | extern host_callback *mn10300_callback; | |
19 | extern SIM_DESC simulator; | |
20 | ||
21 | #define DEBUG_TRACE 0x00000001 | |
22 | #define DEBUG_VALUES 0x00000002 | |
23 | ||
24 | extern int mn10300_debug; | |
25 | ||
26 | #if UCHAR_MAX == 255 | |
27 | typedef unsigned char uint8; | |
28 | typedef signed char int8; | |
29 | #else | |
30 | #error "Char is not an 8-bit type" | |
31 | #endif | |
32 | ||
33 | #if SHRT_MAX == 32767 | |
34 | typedef unsigned short uint16; | |
35 | typedef signed short int16; | |
36 | #else | |
37 | #error "Short is not a 16-bit type" | |
38 | #endif | |
39 | ||
40 | #if INT_MAX == 2147483647 | |
41 | ||
42 | typedef unsigned int uint32; | |
43 | typedef signed int int32; | |
44 | ||
45 | #else | |
46 | # if LONG_MAX == 2147483647 | |
47 | ||
48 | typedef unsigned long uint32; | |
49 | typedef signed long int32; | |
50 | ||
51 | # else | |
52 | # error "Neither int nor long is a 32-bit type" | |
53 | # endif | |
54 | #endif | |
55 | ||
56 | typedef uint32 reg_t; | |
57 | ||
58 | struct simops | |
59 | { | |
60 | long opcode; | |
61 | long mask; | |
62 | void (*func)(); | |
63 | int length; | |
64 | int format; | |
65 | int numops; | |
66 | int operands[16]; | |
67 | }; | |
68 | ||
69 | /* The current state of the processor; registers, memory, etc. */ | |
70 | ||
71 | struct _state | |
72 | { | |
73 | reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw, | |
74 | lir, lar, mdrq, plus some room for processor | |
75 | specific regs. */ | |
76 | uint8 *mem; /* main memory */ | |
77 | int exception; | |
78 | int exited; | |
79 | ||
80 | /* All internal state modified by signal_exception() that may need to be | |
81 | rolled back for passing moment-of-exception image back to gdb. */ | |
82 | reg_t exc_trigger_regs[32]; | |
83 | reg_t exc_suspend_regs[32]; | |
84 | int exc_suspended; | |
85 | ||
86 | #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA) | |
87 | #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC) | |
88 | #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC) | |
89 | }; | |
90 | ||
91 | extern struct _state State; | |
92 | extern uint32 OP[4]; | |
93 | extern struct simops Simops[]; | |
94 | ||
95 | #define PC (State.regs[REG_PC]) | |
96 | #define SP (State.regs[REG_SP]) | |
97 | ||
98 | #define PSW (State.regs[11]) | |
99 | #define PSW_Z 0x1 | |
100 | #define PSW_N 0x2 | |
101 | #define PSW_C 0x4 | |
102 | #define PSW_V 0x8 | |
103 | #define PSW_IE LSBIT (11) | |
104 | #define PSW_LM LSMASK (10, 8) | |
105 | ||
106 | #define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8) | |
107 | #define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8) | |
108 | ||
109 | #define REG_D0 0 | |
110 | #define REG_A0 4 | |
111 | #define REG_SP 8 | |
112 | #define REG_PC 9 | |
113 | #define REG_MDR 10 | |
114 | #define REG_PSW 11 | |
115 | #define REG_LIR 12 | |
116 | #define REG_LAR 13 | |
117 | #define REG_MDRQ 14 | |
118 | ||
119 | #if WITH_COMMON | |
120 | /* These definitions conflict with similar macros in common. */ | |
121 | #else | |
122 | #define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4) | |
123 | ||
124 | /* sign-extend a 4-bit number */ | |
125 | #define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8) | |
126 | ||
127 | /* sign-extend a 5-bit number */ | |
128 | #define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10) | |
129 | ||
130 | /* sign-extend an 8-bit number */ | |
131 | #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80) | |
132 | ||
133 | /* sign-extend a 9-bit number */ | |
134 | #define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100) | |
135 | ||
136 | /* sign-extend a 16-bit number */ | |
137 | #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000) | |
138 | ||
139 | /* sign-extend a 22-bit number */ | |
140 | #define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000) | |
141 | ||
142 | #define MAX32 0x7fffffffLL | |
143 | #define MIN32 0xff80000000LL | |
144 | #define MASK32 0xffffffffLL | |
145 | #define MASK40 0xffffffffffLL | |
146 | #endif /* not WITH_COMMON */ | |
147 | ||
148 | #ifdef _WIN32 | |
149 | #define SIGTRAP 5 | |
150 | #define SIGQUIT 3 | |
151 | #endif | |
152 | ||
153 | #if WITH_COMMON | |
154 | ||
155 | #define FETCH32(a,b,c,d) \ | |
156 | ((a)+((b)<<8)+((c)<<16)+((d)<<24)) | |
157 | ||
158 | #define FETCH24(a,b,c) \ | |
159 | ((a)+((b)<<8)+((c)<<16)) | |
160 | ||
161 | #define FETCH16(a,b) ((a)+((b)<<8)) | |
162 | ||
163 | #define load_byte(ADDR) \ | |
164 | sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR)) | |
165 | ||
166 | #define load_half(ADDR) \ | |
167 | sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR)) | |
168 | ||
169 | #define load_word(ADDR) \ | |
170 | sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR)) | |
171 | ||
172 | #define store_byte(ADDR, DATA) \ | |
173 | sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \ | |
174 | PC, write_map, (ADDR), (DATA)) | |
175 | ||
176 | ||
177 | #define store_half(ADDR, DATA) \ | |
178 | sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \ | |
179 | PC, write_map, (ADDR), (DATA)) | |
180 | ||
181 | ||
182 | #define store_word(ADDR, DATA) \ | |
183 | sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \ | |
184 | PC, write_map, (ADDR), (DATA)) | |
185 | #endif /* WITH_COMMON */ | |
186 | ||
187 | #if WITH_COMMON | |
188 | #else | |
189 | #define load_mem_big(addr,len) \ | |
190 | (len == 1 ? *((addr) + State.mem) : \ | |
191 | len == 2 ? ((*((addr) + State.mem) << 8) \ | |
192 | | *(((addr) + 1) + State.mem)) : \ | |
193 | len == 3 ? ((*((addr) + State.mem) << 16) \ | |
194 | | (*(((addr) + 1) + State.mem) << 8) \ | |
195 | | *(((addr) + 2) + State.mem)) : \ | |
196 | ((*((addr) + State.mem) << 24) \ | |
197 | | (*(((addr) + 1) + State.mem) << 16) \ | |
198 | | (*(((addr) + 2) + State.mem) << 8) \ | |
199 | | *(((addr) + 3) + State.mem))) | |
200 | ||
201 | static INLINE uint32 | |
202 | load_byte (addr) | |
203 | SIM_ADDR addr; | |
204 | { | |
205 | uint8 *p = (addr & 0xffffff) + State.mem; | |
206 | ||
207 | #ifdef CHECK_ADDR | |
208 | if ((addr & 0xffffff) > max_mem) | |
209 | abort (); | |
210 | #endif | |
211 | ||
212 | return p[0]; | |
213 | } | |
214 | ||
215 | static INLINE uint32 | |
216 | load_half (addr) | |
217 | SIM_ADDR addr; | |
218 | { | |
219 | uint8 *p = (addr & 0xffffff) + State.mem; | |
220 | ||
221 | #ifdef CHECK_ADDR | |
222 | if ((addr & 0xffffff) > max_mem) | |
223 | abort (); | |
224 | #endif | |
225 | ||
226 | return p[1] << 8 | p[0]; | |
227 | } | |
228 | ||
229 | static INLINE uint32 | |
230 | load_3_byte (addr) | |
231 | SIM_ADDR addr; | |
232 | { | |
233 | uint8 *p = (addr & 0xffffff) + State.mem; | |
234 | ||
235 | #ifdef CHECK_ADDR | |
236 | if ((addr & 0xffffff) > max_mem) | |
237 | abort (); | |
238 | #endif | |
239 | ||
240 | return p[2] << 16 | p[1] << 8 | p[0]; | |
241 | } | |
242 | ||
243 | static INLINE uint32 | |
244 | load_word (addr) | |
245 | SIM_ADDR addr; | |
246 | { | |
247 | uint8 *p = (addr & 0xffffff) + State.mem; | |
248 | ||
249 | #ifdef CHECK_ADDR | |
250 | if ((addr & 0xffffff) > max_mem) | |
251 | abort (); | |
252 | #endif | |
253 | ||
254 | return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0]; | |
255 | } | |
256 | ||
257 | static INLINE uint32 | |
258 | load_mem (addr, len) | |
259 | SIM_ADDR addr; | |
260 | int len; | |
261 | { | |
262 | uint8 *p = (addr & 0xffffff) + State.mem; | |
263 | ||
264 | #ifdef CHECK_ADDR | |
265 | if ((addr & 0xffffff) > max_mem) | |
266 | abort (); | |
267 | #endif | |
268 | ||
269 | switch (len) | |
270 | { | |
271 | case 1: | |
272 | return p[0]; | |
273 | case 2: | |
274 | return p[1] << 8 | p[0]; | |
275 | case 3: | |
276 | return p[2] << 16 | p[1] << 8 | p[0]; | |
277 | case 4: | |
278 | return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0]; | |
279 | default: | |
280 | abort (); | |
281 | } | |
282 | } | |
283 | ||
284 | static INLINE void | |
285 | store_byte (addr, data) | |
286 | SIM_ADDR addr; | |
287 | uint32 data; | |
288 | { | |
289 | uint8 *p = (addr & 0xffffff) + State.mem; | |
290 | ||
291 | #ifdef CHECK_ADDR | |
292 | if ((addr & 0xffffff) > max_mem) | |
293 | abort (); | |
294 | #endif | |
295 | ||
296 | p[0] = data; | |
297 | } | |
298 | ||
299 | static INLINE void | |
300 | store_half (addr, data) | |
301 | SIM_ADDR addr; | |
302 | uint32 data; | |
303 | { | |
304 | uint8 *p = (addr & 0xffffff) + State.mem; | |
305 | ||
306 | #ifdef CHECK_ADDR | |
307 | if ((addr & 0xffffff) > max_mem) | |
308 | abort (); | |
309 | #endif | |
310 | ||
311 | p[0] = data; | |
312 | p[1] = data >> 8; | |
313 | } | |
314 | ||
315 | static INLINE void | |
316 | store_3_byte (addr, data) | |
317 | SIM_ADDR addr; | |
318 | uint32 data; | |
319 | { | |
320 | uint8 *p = (addr & 0xffffff) + State.mem; | |
321 | ||
322 | #ifdef CHECK_ADDR | |
323 | if ((addr & 0xffffff) > max_mem) | |
324 | abort (); | |
325 | #endif | |
326 | ||
327 | p[0] = data; | |
328 | p[1] = data >> 8; | |
329 | p[2] = data >> 16; | |
330 | } | |
331 | ||
332 | static INLINE void | |
333 | store_word (addr, data) | |
334 | SIM_ADDR addr; | |
335 | uint32 data; | |
336 | { | |
337 | uint8 *p = (addr & 0xffffff) + State.mem; | |
338 | ||
339 | #ifdef CHECK_ADDR | |
340 | if ((addr & 0xffffff) > max_mem) | |
341 | abort (); | |
342 | #endif | |
343 | ||
344 | p[0] = data; | |
345 | p[1] = data >> 8; | |
346 | p[2] = data >> 16; | |
347 | p[3] = data >> 24; | |
348 | } | |
349 | #endif /* not WITH_COMMON */ | |
350 | ||
351 | /* Function declarations. */ | |
352 | ||
353 | uint32 get_word PARAMS ((uint8 *)); | |
354 | uint16 get_half PARAMS ((uint8 *)); | |
355 | uint8 get_byte PARAMS ((uint8 *)); | |
356 | void put_word PARAMS ((uint8 *, uint32)); | |
357 | void put_half PARAMS ((uint8 *, uint16)); | |
358 | void put_byte PARAMS ((uint8 *, uint8)); | |
359 | ||
360 | extern uint8 *map PARAMS ((SIM_ADDR addr)); | |
361 | ||
362 | INLINE_SIM_MAIN (void) genericAdd PARAMS ((unsigned long source, unsigned long destReg)); | |
363 | INLINE_SIM_MAIN (void) genericSub PARAMS ((unsigned long source, unsigned long destReg)); | |
364 | INLINE_SIM_MAIN (void) genericCmp PARAMS ((unsigned long leftOpnd, unsigned long rightOpnd)); | |
365 | INLINE_SIM_MAIN (void) genericOr PARAMS ((unsigned long source, unsigned long destReg)); | |
366 | INLINE_SIM_MAIN (void) genericXor PARAMS ((unsigned long source, unsigned long destReg)); | |
367 | INLINE_SIM_MAIN (void) genericBtst PARAMS ((unsigned long leftOpnd, unsigned long rightOpnd)); | |
368 | INLINE_SIM_MAIN (int) syscall_read_mem PARAMS ((host_callback *cb, | |
369 | struct cb_syscall *sc, | |
370 | unsigned long taddr, | |
371 | char *buf, | |
372 | int bytes)); | |
373 | INLINE_SIM_MAIN (int) syscall_write_mem PARAMS ((host_callback *cb, | |
374 | struct cb_syscall *sc, | |
375 | unsigned long taddr, | |
376 | const char *buf, | |
377 | int bytes)); | |
378 | INLINE_SIM_MAIN (void) do_syscall PARAMS ((void)); | |
379 | void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig); | |
380 | ||
381 | void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc); | |
382 | void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception); | |
383 | void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception); |