sim: syscall: unify memory helpers
[deliverable/binutils-gdb.git] / sim / mn10300 / op_utils.c
CommitLineData
c906108c 1#include "sim-main.h"
61a0c964 2#include "sim-syscall.h"
c906108c
SS
3#include "targ-vals.h"
4
5#ifdef HAVE_UTIME_H
6#include <utime.h>
7#endif
8
9#ifdef HAVE_TIME_H
10#include <time.h>
11#endif
12
13#ifdef HAVE_UNISTD_H
14#include <unistd.h>
15#endif
16
17#ifdef HAVE_STRING_H
18#include <string.h>
19#else
20#ifdef HAVE_STRINGS_H
21#include <strings.h>
22#endif
23#endif
24#include <sys/stat.h>
25#include <sys/times.h>
26#include <sys/time.h>
27
28
29
30#define REG0(X) ((X) & 0x3)
31#define REG1(X) (((X) & 0xc) >> 2)
32#define REG0_4(X) (((X) & 0x30) >> 4)
33#define REG0_8(X) (((X) & 0x300) >> 8)
34#define REG1_8(X) (((X) & 0xc00) >> 10)
35#define REG0_16(X) (((X) & 0x30000) >> 16)
36#define REG1_16(X) (((X) & 0xc0000) >> 18)
37
38
39INLINE_SIM_MAIN (void)
24a39d88 40genericAdd(unsigned32 source, unsigned32 destReg)
c906108c
SS
41{
42 int z, c, n, v;
24a39d88 43 unsigned32 dest, sum;
c906108c
SS
44
45 dest = State.regs[destReg];
46 sum = source + dest;
47 State.regs[destReg] = sum;
48
49 z = (sum == 0);
50 n = (sum & 0x80000000);
51 c = (sum < source) || (sum < dest);
52 v = ((dest & 0x80000000) == (source & 0x80000000)
53 && (dest & 0x80000000) != (sum & 0x80000000));
54
55 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
56 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
57 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
58}
59
60
61
62
63INLINE_SIM_MAIN (void)
24a39d88 64genericSub(unsigned32 source, unsigned32 destReg)
c906108c
SS
65{
66 int z, c, n, v;
24a39d88 67 unsigned32 dest, difference;
c906108c
SS
68
69 dest = State.regs[destReg];
70 difference = dest - source;
71 State.regs[destReg] = difference;
72
73 z = (difference == 0);
74 n = (difference & 0x80000000);
75 c = (source > dest);
76 v = ((dest & 0x80000000) != (source & 0x80000000)
77 && (dest & 0x80000000) != (difference & 0x80000000));
78
79 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
80 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
81 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
82}
83
84INLINE_SIM_MAIN (void)
24a39d88 85genericCmp(unsigned32 leftOpnd, unsigned32 rightOpnd)
c906108c
SS
86{
87 int z, c, n, v;
24a39d88 88 unsigned32 value;
c906108c
SS
89
90 value = rightOpnd - leftOpnd;
91
92 z = (value == 0);
93 n = (value & 0x80000000);
94 c = (leftOpnd > rightOpnd);
95 v = ((rightOpnd & 0x80000000) != (leftOpnd & 0x80000000)
96 && (rightOpnd & 0x80000000) != (value & 0x80000000));
97
98 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
99 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
100 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
101}
102
103
104INLINE_SIM_MAIN (void)
24a39d88 105genericOr(unsigned32 source, unsigned32 destReg)
c906108c
SS
106{
107 int n, z;
108
109 State.regs[destReg] |= source;
110 z = (State.regs[destReg] == 0);
111 n = (State.regs[destReg] & 0x80000000) != 0;
112 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
113 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
114}
115
116
117INLINE_SIM_MAIN (void)
24a39d88 118genericXor(unsigned32 source, unsigned32 destReg)
c906108c
SS
119{
120 int n, z;
121
122 State.regs[destReg] ^= source;
123 z = (State.regs[destReg] == 0);
124 n = (State.regs[destReg] & 0x80000000) != 0;
125 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
126 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
127}
128
129
130INLINE_SIM_MAIN (void)
24a39d88 131genericBtst(unsigned32 leftOpnd, unsigned32 rightOpnd)
c906108c 132{
24a39d88 133 unsigned32 temp;
c906108c
SS
134 int z, n;
135
136 temp = rightOpnd;
137 temp &= leftOpnd;
138 n = (temp & 0x80000000) != 0;
139 z = (temp == 0);
140 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
141 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
142}
143
c906108c
SS
144/* syscall */
145INLINE_SIM_MAIN (void)
489503ee 146do_syscall (void)
c906108c
SS
147{
148
149 /* We use this for simulated system calls; we may need to change
150 it to a reserved instruction if we conflict with uses at
151 Matsushita. */
152 int save_errno = errno;
153 errno = 0;
154
155/* Registers passed to trap 0 */
156
157/* Function number. */
158#define FUNC (State.regs[0])
159
160/* Parameters. */
161#define PARM1 (State.regs[1])
162#define PARM2 (load_word (State.regs[REG_SP] + 12))
163#define PARM3 (load_word (State.regs[REG_SP] + 16))
164
165/* Registers set by trap 0 */
166
167#define RETVAL State.regs[0] /* return value */
168#define RETERR State.regs[1] /* return error code */
169
c906108c
SS
170 if ( FUNC == TARGET_SYS_exit )
171 {
172 /* EXIT - caller can look in PARM1 to work out the reason */
96eaf29e
MF
173 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
174 (PARM1 == 0xdead ? SIM_SIGABRT : sim_exited), PARM1);
c906108c
SS
175 }
176 else
177 {
178 CB_SYSCALL syscall;
179
180 CB_SYSCALL_INIT (&syscall);
181 syscall.arg1 = PARM1;
182 syscall.arg2 = PARM2;
183 syscall.arg3 = PARM3;
184 syscall.func = FUNC;
185 syscall.p1 = (PTR) simulator;
61a0c964
MF
186 syscall.p2 = (PTR) STATE_CPU (simulator, 0);
187 syscall.read_mem = sim_syscall_read_mem;
188 syscall.write_mem = sim_syscall_write_mem;
c906108c
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189 cb_syscall (STATE_CALLBACK (simulator), &syscall);
190 RETERR = syscall.errcode;
191 RETVAL = syscall.result;
192 }
193
194
195 errno = save_errno;
196}
197
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