Commit | Line | Data |
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05ccbdfd JL |
1 | #include "config.h" |
2 | ||
3 | #include <signal.h> | |
4 | #ifdef HAVE_UNISTD_H | |
5 | #include <unistd.h> | |
6 | #endif | |
7 | #include "mn10300_sim.h" | |
8 | #include "simops.h" | |
7eab31b7 | 9 | #include "sim-types.h" |
a9faef12 | 10 | #include "targ-vals.h" |
05ccbdfd JL |
11 | #include "bfd.h" |
12 | #include <errno.h> | |
13 | #include <sys/stat.h> | |
14 | #include <sys/times.h> | |
15 | #include <sys/time.h> | |
16 | ||
9f4a551e JL |
17 | #define REG0(X) ((X) & 0x3) |
18 | #define REG1(X) (((X) & 0xc) >> 2) | |
95d18eb7 | 19 | #define REG0_4(X) (((X) & 0x30) >> 4) |
9f4a551e JL |
20 | #define REG0_8(X) (((X) & 0x300) >> 8) |
21 | #define REG1_8(X) (((X) & 0xc00) >> 10) | |
2e8f4133 | 22 | #define REG0_16(X) (((X) & 0x30000) >> 16) |
9f4a551e | 23 | #define REG1_16(X) (((X) & 0xc0000) >> 18) |
05ccbdfd | 24 | \f |
707641f6 | 25 | /* mov imm8, dn */ |
d2523010 JL |
26 | void OP_8000 (insn, extension) |
27 | unsigned long insn, extension; | |
05ccbdfd | 28 | { |
9f4a551e | 29 | State.regs[REG_D0 + REG0_8 (insn)] = SEXT8 (insn & 0xff); |
05ccbdfd JL |
30 | } |
31 | ||
707641f6 | 32 | /* mov dm, dn */ |
d2523010 JL |
33 | void OP_80 (insn, extension) |
34 | unsigned long insn, extension; | |
05ccbdfd | 35 | { |
9f4a551e | 36 | State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)]; |
05ccbdfd JL |
37 | } |
38 | ||
707641f6 | 39 | /* mov dm, an */ |
d2523010 JL |
40 | void OP_F1E0 (insn, extension) |
41 | unsigned long insn, extension; | |
05ccbdfd | 42 | { |
9f4a551e | 43 | State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)]; |
05ccbdfd JL |
44 | } |
45 | ||
707641f6 | 46 | /* mov am, dn */ |
d2523010 JL |
47 | void OP_F1D0 (insn, extension) |
48 | unsigned long insn, extension; | |
05ccbdfd | 49 | { |
9f4a551e | 50 | State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)]; |
05ccbdfd JL |
51 | } |
52 | ||
707641f6 | 53 | /* mov imm8, an */ |
d2523010 JL |
54 | void OP_9000 (insn, extension) |
55 | unsigned long insn, extension; | |
05ccbdfd | 56 | { |
9f4a551e | 57 | State.regs[REG_A0 + REG0_8 (insn)] = insn & 0xff; |
05ccbdfd JL |
58 | } |
59 | ||
707641f6 | 60 | /* mov am, an */ |
d2523010 JL |
61 | void OP_90 (insn, extension) |
62 | unsigned long insn, extension; | |
05ccbdfd | 63 | { |
9f4a551e | 64 | State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)]; |
05ccbdfd JL |
65 | } |
66 | ||
1f3bea21 | 67 | /* mov sp, an */ |
d2523010 JL |
68 | void OP_3C (insn, extension) |
69 | unsigned long insn, extension; | |
05ccbdfd | 70 | { |
9f4a551e | 71 | State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_SP]; |
05ccbdfd JL |
72 | } |
73 | ||
1f3bea21 | 74 | /* mov am, sp */ |
d2523010 JL |
75 | void OP_F2F0 (insn, extension) |
76 | unsigned long insn, extension; | |
05ccbdfd | 77 | { |
9f4a551e | 78 | State.regs[REG_SP] = State.regs[REG_A0 + REG1 (insn)]; |
05ccbdfd JL |
79 | } |
80 | ||
707641f6 | 81 | /* mov psw, dn */ |
d2523010 JL |
82 | void OP_F2E4 (insn, extension) |
83 | unsigned long insn, extension; | |
05ccbdfd | 84 | { |
9f4a551e | 85 | State.regs[REG_D0 + REG0 (insn)] = PSW; |
05ccbdfd JL |
86 | } |
87 | ||
707641f6 | 88 | /* mov dm, psw */ |
d2523010 JL |
89 | void OP_F2F3 (insn, extension) |
90 | unsigned long insn, extension; | |
05ccbdfd | 91 | { |
9f4a551e | 92 | PSW = State.regs[REG_D0 + REG1 (insn)]; |
05ccbdfd JL |
93 | } |
94 | ||
707641f6 | 95 | /* mov mdr, dn */ |
d2523010 JL |
96 | void OP_F2E0 (insn, extension) |
97 | unsigned long insn, extension; | |
05ccbdfd | 98 | { |
9f4a551e | 99 | State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDR]; |
05ccbdfd JL |
100 | } |
101 | ||
707641f6 | 102 | /* mov dm, mdr */ |
d2523010 JL |
103 | void OP_F2F2 (insn, extension) |
104 | unsigned long insn, extension; | |
05ccbdfd | 105 | { |
9f4a551e | 106 | State.regs[REG_MDR] = State.regs[REG_D0 + REG1 (insn)]; |
05ccbdfd JL |
107 | } |
108 | ||
2e35551c | 109 | /* mov (am), dn */ |
d2523010 JL |
110 | void OP_70 (insn, extension) |
111 | unsigned long insn, extension; | |
05ccbdfd | 112 | { |
9f4a551e | 113 | State.regs[REG_D0 + REG1 (insn)] |
003c91be | 114 | = load_word (State.regs[REG_A0 + REG0 (insn)]); |
05ccbdfd JL |
115 | } |
116 | ||
2e35551c | 117 | /* mov (d8,am), dn */ |
d2523010 JL |
118 | void OP_F80000 (insn, extension) |
119 | unsigned long insn, extension; | |
05ccbdfd | 120 | { |
9f4a551e | 121 | State.regs[REG_D0 + REG1_8 (insn)] |
003c91be | 122 | = load_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff))); |
05ccbdfd JL |
123 | } |
124 | ||
ecb4b5a3 | 125 | /* mov (d16,am), dn */ |
d2523010 JL |
126 | void OP_FA000000 (insn, extension) |
127 | unsigned long insn, extension; | |
05ccbdfd | 128 | { |
9f4a551e | 129 | State.regs[REG_D0 + REG1_16 (insn)] |
003c91be JL |
130 | = load_word ((State.regs[REG_A0 + REG0_16 (insn)] |
131 | + SEXT16 (insn & 0xffff))); | |
05ccbdfd JL |
132 | } |
133 | ||
de0dce7c | 134 | /* mov (d32,am), dn */ |
d2523010 JL |
135 | void OP_FC000000 (insn, extension) |
136 | unsigned long insn, extension; | |
05ccbdfd | 137 | { |
9f4a551e | 138 | State.regs[REG_D0 + REG1_16 (insn)] |
003c91be JL |
139 | = load_word ((State.regs[REG_A0 + REG0_16 (insn)] |
140 | + ((insn & 0xffff) << 16) + extension)); | |
05ccbdfd JL |
141 | } |
142 | ||
707641f6 | 143 | /* mov (d8,sp), dn */ |
d2523010 JL |
144 | void OP_5800 (insn, extension) |
145 | unsigned long insn, extension; | |
05ccbdfd | 146 | { |
9f4a551e | 147 | State.regs[REG_D0 + REG0_8 (insn)] |
003c91be | 148 | = load_word (State.regs[REG_SP] + (insn & 0xff)); |
05ccbdfd JL |
149 | } |
150 | ||
ecb4b5a3 | 151 | /* mov (d16,sp), dn */ |
d2523010 JL |
152 | void OP_FAB40000 (insn, extension) |
153 | unsigned long insn, extension; | |
05ccbdfd | 154 | { |
9f4a551e | 155 | State.regs[REG_D0 + REG0_16 (insn)] |
003c91be | 156 | = load_word (State.regs[REG_SP] + (insn & 0xffff)); |
05ccbdfd JL |
157 | } |
158 | ||
de0dce7c | 159 | /* mov (d32,sp), dn */ |
d2523010 JL |
160 | void OP_FCB40000 (insn, extension) |
161 | unsigned long insn, extension; | |
05ccbdfd | 162 | { |
9f4a551e | 163 | State.regs[REG_D0 + REG0_16 (insn)] |
003c91be | 164 | = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension)); |
05ccbdfd JL |
165 | } |
166 | ||
f5f13c1d | 167 | /* mov (di,am), dn */ |
d2523010 JL |
168 | void OP_F300 (insn, extension) |
169 | unsigned long insn, extension; | |
05ccbdfd | 170 | { |
95d18eb7 | 171 | State.regs[REG_D0 + REG0_4 (insn)] |
003c91be JL |
172 | = load_word ((State.regs[REG_A0 + REG0 (insn)] |
173 | + State.regs[REG_D0 + REG1 (insn)])); | |
05ccbdfd JL |
174 | } |
175 | ||
707641f6 | 176 | /* mov (abs16), dn */ |
d2523010 JL |
177 | void OP_300000 (insn, extension) |
178 | unsigned long insn, extension; | |
05ccbdfd | 179 | { |
003c91be | 180 | State.regs[REG_D0 + REG0_16 (insn)] = load_word ((insn & 0xffff)); |
05ccbdfd JL |
181 | } |
182 | ||
de0dce7c | 183 | /* mov (abs32), dn */ |
d2523010 JL |
184 | void OP_FCA40000 (insn, extension) |
185 | unsigned long insn, extension; | |
05ccbdfd | 186 | { |
9f4a551e | 187 | State.regs[REG_D0 + REG0_16 (insn)] |
003c91be | 188 | = load_word ((((insn & 0xffff) << 16) + extension)); |
05ccbdfd JL |
189 | } |
190 | ||
707641f6 | 191 | /* mov (am), an */ |
d2523010 JL |
192 | void OP_F000 (insn, extension) |
193 | unsigned long insn, extension; | |
05ccbdfd | 194 | { |
9f4a551e | 195 | State.regs[REG_A0 + REG1 (insn)] |
003c91be | 196 | = load_word (State.regs[REG_A0 + REG0 (insn)]); |
05ccbdfd JL |
197 | } |
198 | ||
2e35551c | 199 | /* mov (d8,am), an */ |
d2523010 JL |
200 | void OP_F82000 (insn, extension) |
201 | unsigned long insn, extension; | |
05ccbdfd | 202 | { |
9f4a551e | 203 | State.regs[REG_A0 + REG1_8 (insn)] |
003c91be JL |
204 | = load_word ((State.regs[REG_A0 + REG0_8 (insn)] |
205 | + SEXT8 (insn & 0xff))); | |
05ccbdfd JL |
206 | } |
207 | ||
ecb4b5a3 | 208 | /* mov (d16,am), an */ |
d2523010 JL |
209 | void OP_FA200000 (insn, extension) |
210 | unsigned long insn, extension; | |
05ccbdfd | 211 | { |
9f4a551e | 212 | State.regs[REG_A0 + REG1_16 (insn)] |
003c91be JL |
213 | = load_word ((State.regs[REG_A0 + REG0_16 (insn)] |
214 | + SEXT16 (insn & 0xffff))); | |
05ccbdfd JL |
215 | } |
216 | ||
de0dce7c | 217 | /* mov (d32,am), an */ |
d2523010 JL |
218 | void OP_FC200000 (insn, extension) |
219 | unsigned long insn, extension; | |
05ccbdfd | 220 | { |
9f4a551e | 221 | State.regs[REG_A0 + REG1_16 (insn)] |
003c91be JL |
222 | = load_word ((State.regs[REG_A0 + REG0_16 (insn)] |
223 | + ((insn & 0xffff) << 16) + extension)); | |
05ccbdfd JL |
224 | } |
225 | ||
707641f6 | 226 | /* mov (d8,sp), an */ |
d2523010 JL |
227 | void OP_5C00 (insn, extension) |
228 | unsigned long insn, extension; | |
05ccbdfd | 229 | { |
9f4a551e | 230 | State.regs[REG_A0 + REG0_8 (insn)] |
003c91be | 231 | = load_word (State.regs[REG_SP] + (insn & 0xff)); |
05ccbdfd JL |
232 | } |
233 | ||
ecb4b5a3 | 234 | /* mov (d16,sp), an */ |
d2523010 JL |
235 | void OP_FAB00000 (insn, extension) |
236 | unsigned long insn, extension; | |
05ccbdfd | 237 | { |
9f4a551e | 238 | State.regs[REG_A0 + REG0_16 (insn)] |
003c91be | 239 | = load_word (State.regs[REG_SP] + (insn & 0xffff)); |
05ccbdfd JL |
240 | } |
241 | ||
de0dce7c | 242 | /* mov (d32,sp), an */ |
d2523010 JL |
243 | void OP_FCB00000 (insn, extension) |
244 | unsigned long insn, extension; | |
05ccbdfd | 245 | { |
9f4a551e | 246 | State.regs[REG_A0 + REG0_16 (insn)] |
003c91be | 247 | = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension)); |
05ccbdfd JL |
248 | } |
249 | ||
de0dce7c | 250 | /* mov (di,am), an */ |
d2523010 JL |
251 | void OP_F380 (insn, extension) |
252 | unsigned long insn, extension; | |
05ccbdfd | 253 | { |
95d18eb7 | 254 | State.regs[REG_A0 + REG0_4 (insn)] |
003c91be JL |
255 | = load_word ((State.regs[REG_A0 + REG0 (insn)] |
256 | + State.regs[REG_D0 + REG1 (insn)])); | |
05ccbdfd JL |
257 | } |
258 | ||
ecb4b5a3 | 259 | /* mov (abs16), an */ |
d2523010 JL |
260 | void OP_FAA00000 (insn, extension) |
261 | unsigned long insn, extension; | |
05ccbdfd | 262 | { |
003c91be | 263 | State.regs[REG_A0 + REG0_16 (insn)] = load_word ((insn & 0xffff)); |
05ccbdfd JL |
264 | } |
265 | ||
de0dce7c | 266 | /* mov (abs32), an */ |
d2523010 JL |
267 | void OP_FCA00000 (insn, extension) |
268 | unsigned long insn, extension; | |
05ccbdfd | 269 | { |
9f4a551e | 270 | State.regs[REG_A0 + REG0_16 (insn)] |
003c91be | 271 | = load_word ((((insn & 0xffff) << 16) + extension)); |
05ccbdfd JL |
272 | } |
273 | ||
2e35551c | 274 | /* mov (d8,am), sp */ |
d2523010 JL |
275 | void OP_F8F000 (insn, extension) |
276 | unsigned long insn, extension; | |
05ccbdfd | 277 | { |
2e35551c | 278 | State.regs[REG_SP] |
003c91be JL |
279 | = load_word ((State.regs[REG_A0 + REG0_8 (insn)] |
280 | + SEXT8 (insn & 0xff))); | |
05ccbdfd JL |
281 | } |
282 | ||
707641f6 | 283 | /* mov dm, (an) */ |
d2523010 JL |
284 | void OP_60 (insn, extension) |
285 | unsigned long insn, extension; | |
05ccbdfd | 286 | { |
003c91be JL |
287 | store_word (State.regs[REG_A0 + REG0 (insn)], |
288 | State.regs[REG_D0 + REG1 (insn)]); | |
05ccbdfd JL |
289 | } |
290 | ||
2e35551c | 291 | /* mov dm, (d8,an) */ |
d2523010 JL |
292 | void OP_F81000 (insn, extension) |
293 | unsigned long insn, extension; | |
05ccbdfd | 294 | { |
003c91be JL |
295 | store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)), |
296 | State.regs[REG_D0 + REG1_8 (insn)]); | |
05ccbdfd JL |
297 | } |
298 | ||
ecb4b5a3 | 299 | /* mov dm (d16,an) */ |
d2523010 JL |
300 | void OP_FA100000 (insn, extension) |
301 | unsigned long insn, extension; | |
05ccbdfd | 302 | { |
003c91be JL |
303 | store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)), |
304 | State.regs[REG_D0 + REG1_16 (insn)]); | |
05ccbdfd JL |
305 | } |
306 | ||
de0dce7c | 307 | /* mov dm (d32,an) */ |
d2523010 JL |
308 | void OP_FC100000 (insn, extension) |
309 | unsigned long insn, extension; | |
05ccbdfd | 310 | { |
003c91be JL |
311 | store_word ((State.regs[REG_A0 + REG0_16 (insn)] |
312 | + ((insn & 0xffff) << 16) + extension), | |
313 | State.regs[REG_D0 + REG1_16 (insn)]); | |
05ccbdfd JL |
314 | } |
315 | ||
707641f6 | 316 | /* mov dm, (d8,sp) */ |
d2523010 JL |
317 | void OP_4200 (insn, extension) |
318 | unsigned long insn, extension; | |
05ccbdfd | 319 | { |
003c91be JL |
320 | store_word (State.regs[REG_SP] + (insn & 0xff), |
321 | State.regs[REG_D0 + REG1_8 (insn)]); | |
05ccbdfd JL |
322 | } |
323 | ||
ecb4b5a3 | 324 | /* mov dm, (d16,sp) */ |
d2523010 JL |
325 | void OP_FA910000 (insn, extension) |
326 | unsigned long insn, extension; | |
05ccbdfd | 327 | { |
003c91be JL |
328 | store_word (State.regs[REG_SP] + (insn & 0xffff), |
329 | State.regs[REG_D0 + REG1_16 (insn)]); | |
05ccbdfd JL |
330 | } |
331 | ||
de0dce7c | 332 | /* mov dm, (d32,sp) */ |
d2523010 JL |
333 | void OP_FC910000 (insn, extension) |
334 | unsigned long insn, extension; | |
05ccbdfd | 335 | { |
003c91be JL |
336 | store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), |
337 | State.regs[REG_D0 + REG1_16 (insn)]); | |
05ccbdfd JL |
338 | } |
339 | ||
f5f13c1d | 340 | /* mov dm, (di,an) */ |
d2523010 JL |
341 | void OP_F340 (insn, extension) |
342 | unsigned long insn, extension; | |
05ccbdfd | 343 | { |
003c91be JL |
344 | store_word ((State.regs[REG_A0 + REG0 (insn)] |
345 | + State.regs[REG_D0 + REG1 (insn)]), | |
346 | State.regs[REG_D0 + REG0_4 (insn)]); | |
05ccbdfd JL |
347 | } |
348 | ||
707641f6 | 349 | /* mov dm, (abs16) */ |
d2523010 JL |
350 | void OP_10000 (insn, extension) |
351 | unsigned long insn, extension; | |
05ccbdfd | 352 | { |
003c91be | 353 | store_word ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
354 | } |
355 | ||
de0dce7c | 356 | /* mov dm, (abs32) */ |
d2523010 JL |
357 | void OP_FC810000 (insn, extension) |
358 | unsigned long insn, extension; | |
05ccbdfd | 359 | { |
003c91be JL |
360 | store_word ((((insn & 0xffff) << 16) + extension), |
361 | State.regs[REG_D0 + REG1_16 (insn)]); | |
05ccbdfd JL |
362 | } |
363 | ||
707641f6 | 364 | /* mov am, (an) */ |
d2523010 JL |
365 | void OP_F010 (insn, extension) |
366 | unsigned long insn, extension; | |
05ccbdfd | 367 | { |
003c91be JL |
368 | store_word (State.regs[REG_A0 + REG0 (insn)], |
369 | State.regs[REG_A0 + REG1 (insn)]); | |
05ccbdfd JL |
370 | } |
371 | ||
2e35551c | 372 | /* mov am, (d8,an) */ |
d2523010 JL |
373 | void OP_F83000 (insn, extension) |
374 | unsigned long insn, extension; | |
05ccbdfd | 375 | { |
003c91be JL |
376 | store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)), |
377 | State.regs[REG_A0 + REG1_8 (insn)]); | |
05ccbdfd JL |
378 | } |
379 | ||
de0dce7c | 380 | /* mov am, (d16,an) */ |
d2523010 JL |
381 | void OP_FA300000 (insn, extension) |
382 | unsigned long insn, extension; | |
05ccbdfd | 383 | { |
003c91be JL |
384 | store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)), |
385 | State.regs[REG_A0 + REG1_16 (insn)]); | |
05ccbdfd JL |
386 | } |
387 | ||
de0dce7c | 388 | /* mov am, (d32,an) */ |
d2523010 JL |
389 | void OP_FC300000 (insn, extension) |
390 | unsigned long insn, extension; | |
05ccbdfd | 391 | { |
003c91be JL |
392 | store_word ((State.regs[REG_A0 + REG0_16 (insn)] |
393 | + ((insn & 0xffff) << 16) + extension), | |
394 | State.regs[REG_A0 + REG1_16 (insn)]); | |
05ccbdfd JL |
395 | } |
396 | ||
707641f6 | 397 | /* mov am, (d8,sp) */ |
d2523010 JL |
398 | void OP_4300 (insn, extension) |
399 | unsigned long insn, extension; | |
05ccbdfd | 400 | { |
003c91be JL |
401 | store_word (State.regs[REG_SP] + (insn & 0xff), |
402 | State.regs[REG_A0 + REG1_8 (insn)]); | |
05ccbdfd JL |
403 | } |
404 | ||
ecb4b5a3 | 405 | /* mov am, (d16,sp) */ |
d2523010 JL |
406 | void OP_FA900000 (insn, extension) |
407 | unsigned long insn, extension; | |
05ccbdfd | 408 | { |
003c91be JL |
409 | store_word (State.regs[REG_SP] + (insn & 0xffff), |
410 | State.regs[REG_A0 + REG1_16 (insn)]); | |
05ccbdfd JL |
411 | } |
412 | ||
de0dce7c | 413 | /* mov am, (d32,sp) */ |
d2523010 JL |
414 | void OP_FC900000 (insn, extension) |
415 | unsigned long insn, extension; | |
05ccbdfd | 416 | { |
003c91be JL |
417 | store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), |
418 | State.regs[REG_A0 + REG1_16 (insn)]); | |
05ccbdfd JL |
419 | } |
420 | ||
f5f13c1d | 421 | /* mov am, (di,an) */ |
d2523010 JL |
422 | void OP_F3C0 (insn, extension) |
423 | unsigned long insn, extension; | |
05ccbdfd | 424 | { |
003c91be JL |
425 | store_word ((State.regs[REG_A0 + REG0 (insn)] |
426 | + State.regs[REG_D0 + REG1 (insn)]), | |
427 | State.regs[REG_A0 + REG0_4 (insn)]); | |
05ccbdfd JL |
428 | } |
429 | ||
ecb4b5a3 | 430 | /* mov am, (abs16) */ |
d2523010 JL |
431 | void OP_FA800000 (insn, extension) |
432 | unsigned long insn, extension; | |
05ccbdfd | 433 | { |
003c91be | 434 | store_word ((insn & 0xffff), State.regs[REG_A0 + REG1_16 (insn)]); |
05ccbdfd JL |
435 | } |
436 | ||
de0dce7c | 437 | /* mov am, (abs32) */ |
d2523010 JL |
438 | void OP_FC800000 (insn, extension) |
439 | unsigned long insn, extension; | |
05ccbdfd | 440 | { |
003c91be | 441 | store_word ((((insn & 0xffff) << 16) + extension), State.regs[REG_A0 + REG1_16 (insn)]); |
05ccbdfd JL |
442 | } |
443 | ||
2e35551c | 444 | /* mov sp, (d8,an) */ |
d2523010 JL |
445 | void OP_F8F400 (insn, extension) |
446 | unsigned long insn, extension; | |
05ccbdfd | 447 | { |
003c91be JL |
448 | store_word (State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff), |
449 | State.regs[REG_SP]); | |
05ccbdfd JL |
450 | } |
451 | ||
707641f6 | 452 | /* mov imm16, dn */ |
d2523010 JL |
453 | void OP_2C0000 (insn, extension) |
454 | unsigned long insn, extension; | |
05ccbdfd | 455 | { |
707641f6 JL |
456 | unsigned long value; |
457 | ||
458 | value = SEXT16 (insn & 0xffff); | |
9f4a551e | 459 | State.regs[REG_D0 + REG0_16 (insn)] = value; |
05ccbdfd JL |
460 | } |
461 | ||
de0dce7c | 462 | /* mov imm32,dn */ |
d2523010 JL |
463 | void OP_FCCC0000 (insn, extension) |
464 | unsigned long insn, extension; | |
05ccbdfd | 465 | { |
de0dce7c JL |
466 | unsigned long value; |
467 | ||
7c52bf32 | 468 | value = ((insn & 0xffff) << 16) + extension; |
9f4a551e | 469 | State.regs[REG_D0 + REG0_16 (insn)] = value; |
05ccbdfd JL |
470 | } |
471 | ||
707641f6 | 472 | /* mov imm16, an */ |
d2523010 JL |
473 | void OP_240000 (insn, extension) |
474 | unsigned long insn, extension; | |
05ccbdfd | 475 | { |
707641f6 JL |
476 | unsigned long value; |
477 | ||
478 | value = insn & 0xffff; | |
9f4a551e | 479 | State.regs[REG_A0 + REG0_16 (insn)] = value; |
05ccbdfd JL |
480 | } |
481 | ||
de0dce7c | 482 | /* mov imm32, an */ |
d2523010 JL |
483 | void OP_FCDC0000 (insn, extension) |
484 | unsigned long insn, extension; | |
05ccbdfd | 485 | { |
73e65298 JL |
486 | unsigned long value; |
487 | ||
7c52bf32 | 488 | value = ((insn & 0xffff) << 16) + extension; |
9f4a551e | 489 | State.regs[REG_A0 + REG0_16 (insn)] = value; |
05ccbdfd JL |
490 | } |
491 | ||
707641f6 | 492 | /* movbu (am), dn */ |
d2523010 JL |
493 | void OP_F040 (insn, extension) |
494 | unsigned long insn, extension; | |
05ccbdfd | 495 | { |
9f4a551e | 496 | State.regs[REG_D0 + REG1 (insn)] |
003c91be | 497 | = load_byte (State.regs[REG_A0 + REG0 (insn)]); |
05ccbdfd JL |
498 | } |
499 | ||
2e35551c | 500 | /* movbu (d8,am), dn */ |
d2523010 JL |
501 | void OP_F84000 (insn, extension) |
502 | unsigned long insn, extension; | |
05ccbdfd | 503 | { |
9f4a551e | 504 | State.regs[REG_D0 + REG1_8 (insn)] |
003c91be JL |
505 | = load_byte ((State.regs[REG_A0 + REG0_8 (insn)] |
506 | + SEXT8 (insn & 0xff))); | |
05ccbdfd JL |
507 | } |
508 | ||
ecb4b5a3 | 509 | /* movbu (d16,am), dn */ |
d2523010 JL |
510 | void OP_FA400000 (insn, extension) |
511 | unsigned long insn, extension; | |
05ccbdfd | 512 | { |
9f4a551e | 513 | State.regs[REG_D0 + REG1_16 (insn)] |
003c91be JL |
514 | = load_byte ((State.regs[REG_A0 + REG0_16 (insn)] |
515 | + SEXT16 (insn & 0xffff))); | |
05ccbdfd JL |
516 | } |
517 | ||
de0dce7c | 518 | /* movbu (d32,am), dn */ |
d2523010 JL |
519 | void OP_FC400000 (insn, extension) |
520 | unsigned long insn, extension; | |
05ccbdfd | 521 | { |
9f4a551e | 522 | State.regs[REG_D0 + REG1_16 (insn)] |
003c91be JL |
523 | = load_byte ((State.regs[REG_A0 + REG0_16 (insn)] |
524 | + ((insn & 0xffff) << 16) + extension)); | |
05ccbdfd JL |
525 | } |
526 | ||
2e35551c | 527 | /* movbu (d8,sp), dn */ |
d2523010 JL |
528 | void OP_F8B800 (insn, extension) |
529 | unsigned long insn, extension; | |
05ccbdfd | 530 | { |
9f4a551e | 531 | State.regs[REG_D0 + REG0_8 (insn)] |
003c91be | 532 | = load_byte ((State.regs[REG_SP] + (insn & 0xff))); |
05ccbdfd JL |
533 | } |
534 | ||
ecb4b5a3 | 535 | /* movbu (d16,sp), dn */ |
d2523010 JL |
536 | void OP_FAB80000 (insn, extension) |
537 | unsigned long insn, extension; | |
05ccbdfd | 538 | { |
9f4a551e | 539 | State.regs[REG_D0 + REG0_16 (insn)] |
003c91be | 540 | = load_byte ((State.regs[REG_SP] + (insn & 0xffff))); |
05ccbdfd JL |
541 | } |
542 | ||
de0dce7c | 543 | /* movbu (d32,sp), dn */ |
d2523010 JL |
544 | void OP_FCB80000 (insn, extension) |
545 | unsigned long insn, extension; | |
05ccbdfd | 546 | { |
9f4a551e | 547 | State.regs[REG_D0 + REG0_16 (insn)] |
003c91be | 548 | = load_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension)); |
05ccbdfd JL |
549 | } |
550 | ||
f5f13c1d | 551 | /* movbu (di,am), dn */ |
d2523010 JL |
552 | void OP_F400 (insn, extension) |
553 | unsigned long insn, extension; | |
05ccbdfd | 554 | { |
95d18eb7 | 555 | State.regs[REG_D0 + REG0_4 (insn)] |
003c91be JL |
556 | = load_byte ((State.regs[REG_A0 + REG0 (insn)] |
557 | + State.regs[REG_D0 + REG1 (insn)])); | |
05ccbdfd JL |
558 | } |
559 | ||
707641f6 | 560 | /* movbu (abs16), dn */ |
d2523010 JL |
561 | void OP_340000 (insn, extension) |
562 | unsigned long insn, extension; | |
05ccbdfd | 563 | { |
003c91be | 564 | State.regs[REG_D0 + REG0_16 (insn)] = load_byte ((insn & 0xffff)); |
05ccbdfd JL |
565 | } |
566 | ||
de0dce7c | 567 | /* movbu (abs32), dn */ |
d2523010 JL |
568 | void OP_FCA80000 (insn, extension) |
569 | unsigned long insn, extension; | |
05ccbdfd | 570 | { |
9f4a551e | 571 | State.regs[REG_D0 + REG0_16 (insn)] |
003c91be | 572 | = load_byte ((((insn & 0xffff) << 16) + extension)); |
05ccbdfd JL |
573 | } |
574 | ||
707641f6 | 575 | /* movbu dm, (an) */ |
d2523010 JL |
576 | void OP_F050 (insn, extension) |
577 | unsigned long insn, extension; | |
05ccbdfd | 578 | { |
003c91be JL |
579 | store_byte (State.regs[REG_A0 + REG0 (insn)], |
580 | State.regs[REG_D0 + REG1 (insn)]); | |
05ccbdfd JL |
581 | } |
582 | ||
2e35551c | 583 | /* movbu dm, (d8,an) */ |
d2523010 JL |
584 | void OP_F85000 (insn, extension) |
585 | unsigned long insn, extension; | |
05ccbdfd | 586 | { |
003c91be JL |
587 | store_byte ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)), |
588 | State.regs[REG_D0 + REG1_8 (insn)]); | |
05ccbdfd JL |
589 | } |
590 | ||
ecb4b5a3 | 591 | /* movbu dm, (d16,an) */ |
d2523010 JL |
592 | void OP_FA500000 (insn, extension) |
593 | unsigned long insn, extension; | |
05ccbdfd | 594 | { |
003c91be JL |
595 | store_byte ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)), |
596 | State.regs[REG_D0 + REG1_16 (insn)]); | |
05ccbdfd JL |
597 | } |
598 | ||
de0dce7c | 599 | /* movbu dm, (d32,an) */ |
d2523010 JL |
600 | void OP_FC500000 (insn, extension) |
601 | unsigned long insn, extension; | |
05ccbdfd | 602 | { |
003c91be JL |
603 | store_byte ((State.regs[REG_A0 + REG0_16 (insn)] |
604 | + ((insn & 0xffff) << 16) + extension), | |
605 | State.regs[REG_D0 + REG1_16 (insn)]); | |
05ccbdfd JL |
606 | } |
607 | ||
2e35551c | 608 | /* movbu dm, (d8,sp) */ |
d2523010 JL |
609 | void OP_F89200 (insn, extension) |
610 | unsigned long insn, extension; | |
05ccbdfd | 611 | { |
003c91be JL |
612 | store_byte (State.regs[REG_SP] + (insn & 0xff), |
613 | State.regs[REG_D0 + REG1_8 (insn)]); | |
05ccbdfd JL |
614 | } |
615 | ||
ecb4b5a3 | 616 | /* movbu dm, (d16,sp) */ |
d2523010 JL |
617 | void OP_FA920000 (insn, extension) |
618 | unsigned long insn, extension; | |
05ccbdfd | 619 | { |
003c91be JL |
620 | store_byte (State.regs[REG_SP] + (insn & 0xffff), |
621 | State.regs[REG_D0 + REG1_16 (insn)]); | |
05ccbdfd JL |
622 | } |
623 | ||
de0dce7c | 624 | /* movbu dm (d32,sp) */ |
d2523010 JL |
625 | void OP_FC920000 (insn, extension) |
626 | unsigned long insn, extension; | |
05ccbdfd | 627 | { |
003c91be JL |
628 | store_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), |
629 | State.regs[REG_D0 + REG1_16 (insn)]); | |
05ccbdfd JL |
630 | } |
631 | ||
f5f13c1d | 632 | /* movbu dm, (di,an) */ |
d2523010 JL |
633 | void OP_F440 (insn, extension) |
634 | unsigned long insn, extension; | |
05ccbdfd | 635 | { |
003c91be JL |
636 | store_byte ((State.regs[REG_A0 + REG0 (insn)] |
637 | + State.regs[REG_D0 + REG1 (insn)]), | |
638 | State.regs[REG_D0 + REG0_4 (insn)]); | |
05ccbdfd JL |
639 | } |
640 | ||
707641f6 | 641 | /* movbu dm, (abs16) */ |
d2523010 JL |
642 | void OP_20000 (insn, extension) |
643 | unsigned long insn, extension; | |
05ccbdfd | 644 | { |
003c91be | 645 | store_byte ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
646 | } |
647 | ||
de0dce7c | 648 | /* movbu dm, (abs32) */ |
d2523010 JL |
649 | void OP_FC820000 (insn, extension) |
650 | unsigned long insn, extension; | |
05ccbdfd | 651 | { |
003c91be | 652 | store_byte ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
653 | } |
654 | ||
707641f6 | 655 | /* movhu (am), dn */ |
d2523010 JL |
656 | void OP_F060 (insn, extension) |
657 | unsigned long insn, extension; | |
05ccbdfd | 658 | { |
9f4a551e | 659 | State.regs[REG_D0 + REG1 (insn)] |
003c91be | 660 | = load_half (State.regs[REG_A0 + REG0 (insn)]); |
05ccbdfd JL |
661 | } |
662 | ||
2e35551c | 663 | /* movhu (d8,am), dn */ |
d2523010 JL |
664 | void OP_F86000 (insn, extension) |
665 | unsigned long insn, extension; | |
05ccbdfd | 666 | { |
9f4a551e | 667 | State.regs[REG_D0 + REG1_8 (insn)] |
003c91be JL |
668 | = load_half ((State.regs[REG_A0 + REG0_8 (insn)] |
669 | + SEXT8 (insn & 0xff))); | |
05ccbdfd JL |
670 | } |
671 | ||
ecb4b5a3 | 672 | /* movhu (d16,am), dn */ |
d2523010 JL |
673 | void OP_FA600000 (insn, extension) |
674 | unsigned long insn, extension; | |
05ccbdfd | 675 | { |
9f4a551e | 676 | State.regs[REG_D0 + REG1_16 (insn)] |
003c91be JL |
677 | = load_half ((State.regs[REG_A0 + REG0_16 (insn)] |
678 | + SEXT16 (insn & 0xffff))); | |
05ccbdfd JL |
679 | } |
680 | ||
de0dce7c | 681 | /* movhu (d32,am), dn */ |
d2523010 JL |
682 | void OP_FC600000 (insn, extension) |
683 | unsigned long insn, extension; | |
05ccbdfd | 684 | { |
9f4a551e | 685 | State.regs[REG_D0 + REG1_16 (insn)] |
003c91be JL |
686 | = load_half ((State.regs[REG_A0 + REG0_16 (insn)] |
687 | + ((insn & 0xffff) << 16) + extension)); | |
05ccbdfd JL |
688 | } |
689 | ||
2e35551c | 690 | /* movhu (d8,sp) dn */ |
d2523010 JL |
691 | void OP_F8BC00 (insn, extension) |
692 | unsigned long insn, extension; | |
05ccbdfd | 693 | { |
9f4a551e | 694 | State.regs[REG_D0 + REG0_8 (insn)] |
003c91be | 695 | = load_half ((State.regs[REG_SP] + (insn & 0xff))); |
05ccbdfd JL |
696 | } |
697 | ||
ecb4b5a3 | 698 | /* movhu (d16,sp), dn */ |
d2523010 JL |
699 | void OP_FABC0000 (insn, extension) |
700 | unsigned long insn, extension; | |
05ccbdfd | 701 | { |
9f4a551e | 702 | State.regs[REG_D0 + REG0_16 (insn)] |
003c91be | 703 | = load_half ((State.regs[REG_SP] + (insn & 0xffff))); |
05ccbdfd JL |
704 | } |
705 | ||
de0dce7c | 706 | /* movhu (d32,sp), dn */ |
d2523010 JL |
707 | void OP_FCBC0000 (insn, extension) |
708 | unsigned long insn, extension; | |
05ccbdfd | 709 | { |
9f4a551e | 710 | State.regs[REG_D0 + REG0_16 (insn)] |
003c91be | 711 | = load_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension)); |
05ccbdfd JL |
712 | } |
713 | ||
f5f13c1d | 714 | /* movhu (di,am), dn */ |
d2523010 JL |
715 | void OP_F480 (insn, extension) |
716 | unsigned long insn, extension; | |
05ccbdfd | 717 | { |
95d18eb7 | 718 | State.regs[REG_D0 + REG0_4 (insn)] |
003c91be JL |
719 | = load_half ((State.regs[REG_A0 + REG0 (insn)] |
720 | + State.regs[REG_D0 + REG1 (insn)])); | |
05ccbdfd JL |
721 | } |
722 | ||
707641f6 | 723 | /* movhu (abs16), dn */ |
d2523010 JL |
724 | void OP_380000 (insn, extension) |
725 | unsigned long insn, extension; | |
05ccbdfd | 726 | { |
003c91be | 727 | State.regs[REG_D0 + REG0_16 (insn)] = load_half ((insn & 0xffff)); |
05ccbdfd JL |
728 | } |
729 | ||
de0dce7c | 730 | /* movhu (abs32), dn */ |
d2523010 JL |
731 | void OP_FCAC0000 (insn, extension) |
732 | unsigned long insn, extension; | |
05ccbdfd | 733 | { |
9f4a551e | 734 | State.regs[REG_D0 + REG0_16 (insn)] |
003c91be | 735 | = load_half ((((insn & 0xffff) << 16) + extension)); |
05ccbdfd JL |
736 | } |
737 | ||
707641f6 | 738 | /* movhu dm, (an) */ |
d2523010 JL |
739 | void OP_F070 (insn, extension) |
740 | unsigned long insn, extension; | |
05ccbdfd | 741 | { |
003c91be JL |
742 | store_half (State.regs[REG_A0 + REG0 (insn)], |
743 | State.regs[REG_D0 + REG1 (insn)]); | |
05ccbdfd JL |
744 | } |
745 | ||
2e35551c | 746 | /* movhu dm, (d8,an) */ |
d2523010 JL |
747 | void OP_F87000 (insn, extension) |
748 | unsigned long insn, extension; | |
05ccbdfd | 749 | { |
003c91be JL |
750 | store_half ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)), |
751 | State.regs[REG_D0 + REG1_8 (insn)]); | |
05ccbdfd JL |
752 | } |
753 | ||
ecb4b5a3 | 754 | /* movhu dm, (d16,an) */ |
d2523010 JL |
755 | void OP_FA700000 (insn, extension) |
756 | unsigned long insn, extension; | |
05ccbdfd | 757 | { |
003c91be JL |
758 | store_half ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)), |
759 | State.regs[REG_D0 + REG1_16 (insn)]); | |
05ccbdfd JL |
760 | } |
761 | ||
de0dce7c | 762 | /* movhu dm, (d32,an) */ |
d2523010 JL |
763 | void OP_FC700000 (insn, extension) |
764 | unsigned long insn, extension; | |
05ccbdfd | 765 | { |
003c91be JL |
766 | store_half ((State.regs[REG_A0 + REG0_16 (insn)] |
767 | + ((insn & 0xffff) << 16) + extension), | |
768 | State.regs[REG_D0 + REG1_16 (insn)]); | |
05ccbdfd JL |
769 | } |
770 | ||
2e35551c | 771 | /* movhu dm,(d8,sp) */ |
d2523010 JL |
772 | void OP_F89300 (insn, extension) |
773 | unsigned long insn, extension; | |
05ccbdfd | 774 | { |
003c91be JL |
775 | store_half (State.regs[REG_SP] + (insn & 0xff), |
776 | State.regs[REG_D0 + REG1_8 (insn)]); | |
05ccbdfd JL |
777 | } |
778 | ||
ecb4b5a3 | 779 | /* movhu dm,(d16,sp) */ |
d2523010 JL |
780 | void OP_FA930000 (insn, extension) |
781 | unsigned long insn, extension; | |
05ccbdfd | 782 | { |
003c91be JL |
783 | store_half (State.regs[REG_SP] + (insn & 0xffff), |
784 | State.regs[REG_D0 + REG1_16 (insn)]); | |
05ccbdfd JL |
785 | } |
786 | ||
de0dce7c | 787 | /* movhu dm,(d32,sp) */ |
d2523010 JL |
788 | void OP_FC930000 (insn, extension) |
789 | unsigned long insn, extension; | |
05ccbdfd | 790 | { |
003c91be JL |
791 | store_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), |
792 | State.regs[REG_D0 + REG1_16 (insn)]); | |
05ccbdfd JL |
793 | } |
794 | ||
f5f13c1d | 795 | /* movhu dm, (di,an) */ |
d2523010 JL |
796 | void OP_F4C0 (insn, extension) |
797 | unsigned long insn, extension; | |
05ccbdfd | 798 | { |
003c91be JL |
799 | store_half ((State.regs[REG_A0 + REG0 (insn)] |
800 | + State.regs[REG_D0 + REG1 (insn)]), | |
801 | State.regs[REG_D0 + REG0_4 (insn)]); | |
05ccbdfd JL |
802 | } |
803 | ||
707641f6 | 804 | /* movhu dm, (abs16) */ |
d2523010 JL |
805 | void OP_30000 (insn, extension) |
806 | unsigned long insn, extension; | |
05ccbdfd | 807 | { |
003c91be | 808 | store_half ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
809 | } |
810 | ||
de0dce7c | 811 | /* movhu dm, (abs32) */ |
d2523010 JL |
812 | void OP_FC830000 (insn, extension) |
813 | unsigned long insn, extension; | |
05ccbdfd | 814 | { |
003c91be | 815 | store_half ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]); |
05ccbdfd JL |
816 | } |
817 | ||
707641f6 | 818 | /* ext dn */ |
d2523010 JL |
819 | void OP_F2D0 (insn, extension) |
820 | unsigned long insn, extension; | |
05ccbdfd | 821 | { |
9f4a551e | 822 | if (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) |
707641f6 JL |
823 | State.regs[REG_MDR] = -1; |
824 | else | |
825 | State.regs[REG_MDR] = 0; | |
05ccbdfd JL |
826 | } |
827 | ||
707641f6 | 828 | /* extb dn */ |
d2523010 JL |
829 | void OP_10 (insn, extension) |
830 | unsigned long insn, extension; | |
05ccbdfd | 831 | { |
9f4a551e | 832 | State.regs[REG_D0 + REG0 (insn)] = SEXT8 (State.regs[REG_D0 + REG0 (insn)]); |
05ccbdfd JL |
833 | } |
834 | ||
707641f6 | 835 | /* extbu dn */ |
d2523010 JL |
836 | void OP_14 (insn, extension) |
837 | unsigned long insn, extension; | |
05ccbdfd | 838 | { |
9f4a551e | 839 | State.regs[REG_D0 + REG0 (insn)] &= 0xff; |
05ccbdfd JL |
840 | } |
841 | ||
707641f6 | 842 | /* exth dn */ |
d2523010 JL |
843 | void OP_18 (insn, extension) |
844 | unsigned long insn, extension; | |
05ccbdfd | 845 | { |
9f4a551e JL |
846 | State.regs[REG_D0 + REG0 (insn)] |
847 | = SEXT16 (State.regs[REG_D0 + REG0 (insn)]); | |
05ccbdfd JL |
848 | } |
849 | ||
707641f6 | 850 | /* exthu dn */ |
d2523010 JL |
851 | void OP_1C (insn, extension) |
852 | unsigned long insn, extension; | |
05ccbdfd | 853 | { |
9f4a551e | 854 | State.regs[REG_D0 + REG0 (insn)] &= 0xffff; |
05ccbdfd JL |
855 | } |
856 | ||
1f3bea21 | 857 | /* movm (sp), reg_list */ |
d2523010 JL |
858 | void OP_CE00 (insn, extension) |
859 | unsigned long insn, extension; | |
05ccbdfd | 860 | { |
1f3bea21 JL |
861 | unsigned long sp = State.regs[REG_SP]; |
862 | unsigned long mask; | |
863 | ||
864 | mask = insn & 0xff; | |
865 | ||
866 | if (mask & 0x8) | |
867 | { | |
868 | sp += 4; | |
003c91be | 869 | State.regs[REG_LAR] = load_word (sp); |
1f3bea21 | 870 | sp += 4; |
003c91be | 871 | State.regs[REG_LIR] = load_word (sp); |
1f3bea21 | 872 | sp += 4; |
003c91be | 873 | State.regs[REG_MDR] = load_word (sp); |
1f3bea21 | 874 | sp += 4; |
003c91be | 875 | State.regs[REG_A0 + 1] = load_word (sp); |
1f3bea21 | 876 | sp += 4; |
003c91be | 877 | State.regs[REG_A0] = load_word (sp); |
1f3bea21 | 878 | sp += 4; |
003c91be | 879 | State.regs[REG_D0 + 1] = load_word (sp); |
1f3bea21 | 880 | sp += 4; |
003c91be | 881 | State.regs[REG_D0] = load_word (sp); |
1f3bea21 JL |
882 | sp += 4; |
883 | } | |
884 | ||
885 | if (mask & 0x10) | |
886 | { | |
003c91be | 887 | State.regs[REG_A0 + 3] = load_word (sp); |
1f3bea21 JL |
888 | sp += 4; |
889 | } | |
890 | ||
891 | if (mask & 0x20) | |
892 | { | |
003c91be | 893 | State.regs[REG_A0 + 2] = load_word (sp); |
1f3bea21 JL |
894 | sp += 4; |
895 | } | |
896 | ||
897 | if (mask & 0x40) | |
898 | { | |
003c91be | 899 | State.regs[REG_D0 + 3] = load_word (sp); |
1f3bea21 JL |
900 | sp += 4; |
901 | } | |
902 | ||
903 | if (mask & 0x80) | |
904 | { | |
003c91be | 905 | State.regs[REG_D0 + 2] = load_word (sp); |
1f3bea21 JL |
906 | sp += 4; |
907 | } | |
908 | ||
909 | /* And make sure to update the stack pointer. */ | |
910 | State.regs[REG_SP] = sp; | |
911 | } | |
912 | ||
913 | /* movm reg_list, (sp) */ | |
d2523010 JL |
914 | void OP_CF00 (insn, extension) |
915 | unsigned long insn, extension; | |
05ccbdfd | 916 | { |
1f3bea21 JL |
917 | unsigned long sp = State.regs[REG_SP]; |
918 | unsigned long mask; | |
919 | ||
920 | mask = insn & 0xff; | |
921 | ||
922 | if (mask & 0x80) | |
923 | { | |
924 | sp -= 4; | |
003c91be | 925 | store_word (sp, State.regs[REG_D0 + 2]); |
1f3bea21 JL |
926 | } |
927 | ||
928 | if (mask & 0x40) | |
929 | { | |
930 | sp -= 4; | |
003c91be | 931 | store_word (sp, State.regs[REG_D0 + 3]); |
1f3bea21 JL |
932 | } |
933 | ||
934 | if (mask & 0x20) | |
935 | { | |
936 | sp -= 4; | |
003c91be | 937 | store_word (sp, State.regs[REG_A0 + 2]); |
1f3bea21 JL |
938 | } |
939 | ||
940 | if (mask & 0x10) | |
941 | { | |
942 | sp -= 4; | |
003c91be | 943 | store_word (sp, State.regs[REG_A0 + 3]); |
1f3bea21 JL |
944 | } |
945 | ||
946 | if (mask & 0x8) | |
947 | { | |
948 | sp -= 4; | |
003c91be | 949 | store_word (sp, State.regs[REG_D0]); |
1f3bea21 | 950 | sp -= 4; |
003c91be | 951 | store_word (sp, State.regs[REG_D0 + 1]); |
1f3bea21 | 952 | sp -= 4; |
003c91be | 953 | store_word (sp, State.regs[REG_A0]); |
1f3bea21 | 954 | sp -= 4; |
003c91be | 955 | store_word (sp, State.regs[REG_A0 + 1]); |
1f3bea21 | 956 | sp -= 4; |
003c91be | 957 | store_word (sp, State.regs[REG_MDR]); |
1f3bea21 | 958 | sp -= 4; |
003c91be | 959 | store_word (sp, State.regs[REG_LIR]); |
1f3bea21 | 960 | sp -= 4; |
003c91be | 961 | store_word (sp, State.regs[REG_LAR]); |
1f3bea21 JL |
962 | sp -= 4; |
963 | } | |
964 | ||
965 | /* And make sure to update the stack pointer. */ | |
966 | State.regs[REG_SP] = sp; | |
05ccbdfd JL |
967 | } |
968 | ||
73e65298 | 969 | /* clr dn */ |
d2523010 JL |
970 | void OP_0 (insn, extension) |
971 | unsigned long insn, extension; | |
05ccbdfd | 972 | { |
9f4a551e | 973 | State.regs[REG_D0 + REG1 (insn)] = 0; |
73e65298 JL |
974 | |
975 | PSW |= PSW_Z; | |
976 | PSW &= ~(PSW_V | PSW_C | PSW_N); | |
05ccbdfd JL |
977 | } |
978 | ||
de0dce7c | 979 | /* add dm,dn */ |
d2523010 JL |
980 | void OP_E0 (insn, extension) |
981 | unsigned long insn, extension; | |
05ccbdfd | 982 | { |
73e65298 JL |
983 | int z, c, n, v; |
984 | unsigned long reg1, reg2, value; | |
985 | ||
9f4a551e JL |
986 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
987 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
73e65298 | 988 | value = reg1 + reg2; |
9f4a551e | 989 | State.regs[REG_D0 + REG0 (insn)] = value; |
73e65298 JL |
990 | |
991 | z = (value == 0); | |
992 | n = (value & 0x80000000); | |
0ade484f | 993 | c = (value < reg1) || (value < reg2); |
d657034d | 994 | v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) |
b7b89deb | 995 | && (reg2 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
996 | |
997 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
998 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
999 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1000 | } |
1001 | ||
73e65298 | 1002 | /* add dm, an */ |
d2523010 JL |
1003 | void OP_F160 (insn, extension) |
1004 | unsigned long insn, extension; | |
05ccbdfd | 1005 | { |
73e65298 JL |
1006 | int z, c, n, v; |
1007 | unsigned long reg1, reg2, value; | |
1008 | ||
9f4a551e JL |
1009 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
1010 | reg2 = State.regs[REG_A0 + REG0 (insn)]; | |
73e65298 | 1011 | value = reg1 + reg2; |
9f4a551e | 1012 | State.regs[REG_A0 + REG0 (insn)] = value; |
73e65298 JL |
1013 | |
1014 | z = (value == 0); | |
1015 | n = (value & 0x80000000); | |
0ade484f | 1016 | c = (value < reg1) || (value < reg2); |
d657034d | 1017 | v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) |
b7b89deb | 1018 | && (reg2 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1019 | |
1020 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1021 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1022 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1023 | } |
1024 | ||
de0dce7c | 1025 | /* add am, dn */ |
d2523010 JL |
1026 | void OP_F150 (insn, extension) |
1027 | unsigned long insn, extension; | |
05ccbdfd | 1028 | { |
73e65298 JL |
1029 | int z, c, n, v; |
1030 | unsigned long reg1, reg2, value; | |
1031 | ||
9f4a551e JL |
1032 | reg1 = State.regs[REG_A0 + REG1 (insn)]; |
1033 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
73e65298 | 1034 | value = reg1 + reg2; |
9f4a551e | 1035 | State.regs[REG_D0 + REG0 (insn)] = value; |
73e65298 JL |
1036 | |
1037 | z = (value == 0); | |
1038 | n = (value & 0x80000000); | |
0ade484f | 1039 | c = (value < reg1) || (value < reg2); |
d657034d | 1040 | v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) |
b7b89deb | 1041 | && (reg2 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1042 | |
1043 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1044 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1045 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1046 | } |
1047 | ||
73e65298 | 1048 | /* add am,an */ |
d2523010 JL |
1049 | void OP_F170 (insn, extension) |
1050 | unsigned long insn, extension; | |
05ccbdfd | 1051 | { |
73e65298 JL |
1052 | int z, c, n, v; |
1053 | unsigned long reg1, reg2, value; | |
1054 | ||
9f4a551e JL |
1055 | reg1 = State.regs[REG_A0 + REG1 (insn)]; |
1056 | reg2 = State.regs[REG_A0 + REG0 (insn)]; | |
73e65298 | 1057 | value = reg1 + reg2; |
9f4a551e | 1058 | State.regs[REG_A0 + REG0 (insn)] = value; |
73e65298 JL |
1059 | |
1060 | z = (value == 0); | |
1061 | n = (value & 0x80000000); | |
0ade484f | 1062 | c = (value < reg1) || (value < reg2); |
d657034d | 1063 | v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) |
b7b89deb | 1064 | && (reg2 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1065 | |
1066 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1067 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1068 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1069 | } |
1070 | ||
73e65298 | 1071 | /* add imm8, dn */ |
d2523010 JL |
1072 | void OP_2800 (insn, extension) |
1073 | unsigned long insn, extension; | |
05ccbdfd | 1074 | { |
73e65298 JL |
1075 | int z, c, n, v; |
1076 | unsigned long reg1, imm, value; | |
1077 | ||
9f4a551e | 1078 | reg1 = State.regs[REG_D0 + REG0_8 (insn)]; |
73e65298 JL |
1079 | imm = SEXT8 (insn & 0xff); |
1080 | value = reg1 + imm; | |
9f4a551e | 1081 | State.regs[REG_D0 + REG0_8 (insn)] = value; |
73e65298 JL |
1082 | |
1083 | z = (value == 0); | |
1084 | n = (value & 0x80000000); | |
0ade484f | 1085 | c = (value < reg1) || (value < imm); |
d657034d | 1086 | v = ((reg1 & 0x80000000) == (imm & 0x80000000) |
b7b89deb | 1087 | && (reg1 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1088 | |
1089 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1090 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1091 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1092 | } |
1093 | ||
73e65298 | 1094 | /* add imm16, dn */ |
d2523010 JL |
1095 | void OP_FAC00000 (insn, extension) |
1096 | unsigned long insn, extension; | |
05ccbdfd | 1097 | { |
73e65298 JL |
1098 | int z, c, n, v; |
1099 | unsigned long reg1, imm, value; | |
1100 | ||
9f4a551e | 1101 | reg1 = State.regs[REG_D0 + REG0_16 (insn)]; |
73e65298 JL |
1102 | imm = SEXT16 (insn & 0xffff); |
1103 | value = reg1 + imm; | |
9f4a551e | 1104 | State.regs[REG_D0 + REG0_16 (insn)] = value; |
73e65298 JL |
1105 | |
1106 | z = (value == 0); | |
1107 | n = (value & 0x80000000); | |
0ade484f | 1108 | c = (value < reg1) || (value < imm); |
d657034d | 1109 | v = ((reg1 & 0x80000000) == (imm & 0x80000000) |
b7b89deb | 1110 | && (reg1 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1111 | |
1112 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1113 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1114 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1115 | } |
1116 | ||
73e65298 | 1117 | /* add imm32,dn */ |
d2523010 JL |
1118 | void OP_FCC00000 (insn, extension) |
1119 | unsigned long insn, extension; | |
05ccbdfd | 1120 | { |
73e65298 JL |
1121 | int z, c, n, v; |
1122 | unsigned long reg1, imm, value; | |
1123 | ||
9f4a551e | 1124 | reg1 = State.regs[REG_D0 + REG0_16 (insn)]; |
7c52bf32 | 1125 | imm = ((insn & 0xffff) << 16) + extension; |
73e65298 | 1126 | value = reg1 + imm; |
9f4a551e | 1127 | State.regs[REG_D0 + REG0_16 (insn)] = value; |
73e65298 JL |
1128 | |
1129 | z = (value == 0); | |
1130 | n = (value & 0x80000000); | |
0ade484f | 1131 | c = (value < reg1) || (value < imm); |
d657034d | 1132 | v = ((reg1 & 0x80000000) == (imm & 0x80000000) |
b7b89deb | 1133 | && (reg1 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1134 | |
1135 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1136 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1137 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1138 | } |
1139 | ||
73e65298 | 1140 | /* add imm8, an */ |
d2523010 JL |
1141 | void OP_2000 (insn, extension) |
1142 | unsigned long insn, extension; | |
05ccbdfd | 1143 | { |
73e65298 JL |
1144 | int z, c, n, v; |
1145 | unsigned long reg1, imm, value; | |
1146 | ||
9f4a551e | 1147 | reg1 = State.regs[REG_A0 + REG0_8 (insn)]; |
6e7a01c1 | 1148 | imm = SEXT8 (insn & 0xff); |
73e65298 | 1149 | value = reg1 + imm; |
9f4a551e | 1150 | State.regs[REG_A0 + REG0_8 (insn)] = value; |
73e65298 JL |
1151 | |
1152 | z = (value == 0); | |
1153 | n = (value & 0x80000000); | |
0ade484f | 1154 | c = (value < reg1) || (value < imm); |
d657034d | 1155 | v = ((reg1 & 0x80000000) == (imm & 0x80000000) |
b7b89deb | 1156 | && (reg1 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1157 | |
1158 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1159 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1160 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1161 | } |
1162 | ||
73e65298 | 1163 | /* add imm16, an */ |
d2523010 JL |
1164 | void OP_FAD00000 (insn, extension) |
1165 | unsigned long insn, extension; | |
05ccbdfd | 1166 | { |
73e65298 JL |
1167 | int z, c, n, v; |
1168 | unsigned long reg1, imm, value; | |
1169 | ||
9f4a551e | 1170 | reg1 = State.regs[REG_A0 + REG0_16 (insn)]; |
6e7a01c1 | 1171 | imm = SEXT16 (insn & 0xffff); |
73e65298 | 1172 | value = reg1 + imm; |
9f4a551e | 1173 | State.regs[REG_A0 + REG0_16 (insn)] = value; |
73e65298 JL |
1174 | |
1175 | z = (value == 0); | |
1176 | n = (value & 0x80000000); | |
0ade484f | 1177 | c = (value < reg1) || (value < imm); |
d657034d | 1178 | v = ((reg1 & 0x80000000) == (imm & 0x80000000) |
b7b89deb | 1179 | && (reg1 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1180 | |
1181 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1182 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1183 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1184 | } |
1185 | ||
73e65298 | 1186 | /* add imm32, an */ |
d2523010 JL |
1187 | void OP_FCD00000 (insn, extension) |
1188 | unsigned long insn, extension; | |
05ccbdfd | 1189 | { |
73e65298 JL |
1190 | int z, c, n, v; |
1191 | unsigned long reg1, imm, value; | |
1192 | ||
9f4a551e | 1193 | reg1 = State.regs[REG_A0 + REG0_16 (insn)]; |
7c52bf32 | 1194 | imm = ((insn & 0xffff) << 16) + extension; |
73e65298 | 1195 | value = reg1 + imm; |
9f4a551e | 1196 | State.regs[REG_A0 + REG0_16 (insn)] = value; |
73e65298 JL |
1197 | |
1198 | z = (value == 0); | |
1199 | n = (value & 0x80000000); | |
0ade484f | 1200 | c = (value < reg1) || (value < imm); |
d657034d | 1201 | v = ((reg1 & 0x80000000) == (imm & 0x80000000) |
b7b89deb | 1202 | && (reg1 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1203 | |
1204 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1205 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1206 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1207 | } |
1208 | ||
de0dce7c | 1209 | /* add imm8, sp */ |
d2523010 JL |
1210 | void OP_F8FE00 (insn, extension) |
1211 | unsigned long insn, extension; | |
05ccbdfd | 1212 | { |
73e65298 JL |
1213 | unsigned long reg1, imm, value; |
1214 | ||
1215 | reg1 = State.regs[REG_SP]; | |
1216 | imm = SEXT8 (insn & 0xff); | |
1217 | value = reg1 + imm; | |
1218 | State.regs[REG_SP] = value; | |
05ccbdfd JL |
1219 | } |
1220 | ||
73e65298 | 1221 | /* add imm16,sp */ |
d2523010 JL |
1222 | void OP_FAFE0000 (insn, extension) |
1223 | unsigned long insn, extension; | |
05ccbdfd | 1224 | { |
73e65298 JL |
1225 | unsigned long reg1, imm, value; |
1226 | ||
1227 | reg1 = State.regs[REG_SP]; | |
1228 | imm = SEXT16 (insn & 0xffff); | |
1229 | value = reg1 + imm; | |
1230 | State.regs[REG_SP] = value; | |
05ccbdfd JL |
1231 | } |
1232 | ||
de0dce7c | 1233 | /* add imm32, sp */ |
d2523010 JL |
1234 | void OP_FCFE0000 (insn, extension) |
1235 | unsigned long insn, extension; | |
05ccbdfd | 1236 | { |
73e65298 JL |
1237 | unsigned long reg1, imm, value; |
1238 | ||
1239 | reg1 = State.regs[REG_SP]; | |
7c52bf32 | 1240 | imm = ((insn & 0xffff) << 16) + extension; |
73e65298 JL |
1241 | value = reg1 + imm; |
1242 | State.regs[REG_SP] = value; | |
05ccbdfd JL |
1243 | } |
1244 | ||
de0dce7c | 1245 | /* addc dm,dn */ |
d2523010 JL |
1246 | void OP_F140 (insn, extension) |
1247 | unsigned long insn, extension; | |
05ccbdfd | 1248 | { |
73e65298 JL |
1249 | int z, c, n, v; |
1250 | unsigned long reg1, reg2, value; | |
1251 | ||
9f4a551e JL |
1252 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
1253 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
73e65298 | 1254 | value = reg1 + reg2 + ((PSW & PSW_C) != 0); |
9f4a551e | 1255 | State.regs[REG_D0 + REG0 (insn)] = value; |
73e65298 JL |
1256 | |
1257 | z = (value == 0); | |
1258 | n = (value & 0x80000000); | |
0ade484f | 1259 | c = (value < reg1) || (value < reg2); |
d657034d | 1260 | v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) |
b7b89deb | 1261 | && (reg2 & 0x80000000) != (value & 0x80000000)); |
73e65298 JL |
1262 | |
1263 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1264 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1265 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1266 | } |
1267 | ||
707641f6 | 1268 | /* sub dm, dn */ |
d2523010 JL |
1269 | void OP_F100 (insn, extension) |
1270 | unsigned long insn, extension; | |
05ccbdfd | 1271 | { |
707641f6 JL |
1272 | int z, c, n, v; |
1273 | unsigned long reg1, reg2, value; | |
1274 | ||
9f4a551e JL |
1275 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
1276 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
707641f6 | 1277 | value = reg2 - reg1; |
65b784d8 | 1278 | State.regs[REG_D0 + REG0 (insn)] = value; |
707641f6 JL |
1279 | |
1280 | z = (value == 0); | |
1281 | n = (value & 0x80000000); | |
216e6557 | 1282 | c = (reg1 > reg2); |
b7b89deb JL |
1283 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1284 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
707641f6 JL |
1285 | |
1286 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1287 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1288 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1289 | } |
1290 | ||
707641f6 | 1291 | /* sub dm, an */ |
d2523010 JL |
1292 | void OP_F120 (insn, extension) |
1293 | unsigned long insn, extension; | |
05ccbdfd | 1294 | { |
707641f6 JL |
1295 | int z, c, n, v; |
1296 | unsigned long reg1, reg2, value; | |
1297 | ||
9f4a551e JL |
1298 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
1299 | reg2 = State.regs[REG_A0 + REG0 (insn)]; | |
707641f6 | 1300 | value = reg2 - reg1; |
65b784d8 | 1301 | State.regs[REG_A0 + REG0 (insn)] = value; |
707641f6 JL |
1302 | |
1303 | z = (value == 0); | |
1304 | n = (value & 0x80000000); | |
216e6557 | 1305 | c = (reg1 > reg2); |
b7b89deb JL |
1306 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1307 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
707641f6 JL |
1308 | |
1309 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1310 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1311 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1312 | } |
1313 | ||
707641f6 | 1314 | /* sub am, dn */ |
d2523010 JL |
1315 | void OP_F110 (insn, extension) |
1316 | unsigned long insn, extension; | |
05ccbdfd | 1317 | { |
707641f6 JL |
1318 | int z, c, n, v; |
1319 | unsigned long reg1, reg2, value; | |
1320 | ||
9f4a551e JL |
1321 | reg1 = State.regs[REG_A0 + REG1 (insn)]; |
1322 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
707641f6 | 1323 | value = reg2 - reg1; |
65b784d8 | 1324 | State.regs[REG_D0 + REG0 (insn)] = value; |
707641f6 JL |
1325 | |
1326 | z = (value == 0); | |
1327 | n = (value & 0x80000000); | |
216e6557 | 1328 | c = (reg1 > reg2); |
b7b89deb JL |
1329 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1330 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
707641f6 JL |
1331 | |
1332 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1333 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1334 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1335 | } |
1336 | ||
707641f6 | 1337 | /* sub am, an */ |
d2523010 JL |
1338 | void OP_F130 (insn, extension) |
1339 | unsigned long insn, extension; | |
05ccbdfd | 1340 | { |
707641f6 JL |
1341 | int z, c, n, v; |
1342 | unsigned long reg1, reg2, value; | |
1343 | ||
9f4a551e JL |
1344 | reg1 = State.regs[REG_A0 + REG1 (insn)]; |
1345 | reg2 = State.regs[REG_A0 + REG0 (insn)]; | |
707641f6 | 1346 | value = reg2 - reg1; |
65b784d8 | 1347 | State.regs[REG_A0 + REG0 (insn)] = value; |
707641f6 JL |
1348 | |
1349 | z = (value == 0); | |
1350 | n = (value & 0x80000000); | |
216e6557 | 1351 | c = (reg1 > reg2); |
b7b89deb JL |
1352 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1353 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
707641f6 JL |
1354 | |
1355 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1356 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1357 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1358 | } |
1359 | ||
de0dce7c | 1360 | /* sub imm32, dn */ |
d2523010 JL |
1361 | void OP_FCC40000 (insn, extension) |
1362 | unsigned long insn, extension; | |
05ccbdfd | 1363 | { |
707641f6 JL |
1364 | int z, c, n, v; |
1365 | unsigned long reg1, imm, value; | |
1366 | ||
9f4a551e | 1367 | reg1 = State.regs[REG_D0 + REG0_16 (insn)]; |
7c52bf32 | 1368 | imm = ((insn & 0xffff) << 16) + extension; |
707641f6 | 1369 | value = reg1 - imm; |
65b784d8 | 1370 | State.regs[REG_D0 + REG0_16 (insn)] = value; |
707641f6 JL |
1371 | |
1372 | z = (value == 0); | |
1373 | n = (value & 0x80000000); | |
1374 | c = (reg1 < imm); | |
b7b89deb JL |
1375 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1376 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
707641f6 JL |
1377 | |
1378 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1379 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1380 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1381 | } |
1382 | ||
de0dce7c | 1383 | /* sub imm32, an */ |
d2523010 JL |
1384 | void OP_FCD40000 (insn, extension) |
1385 | unsigned long insn, extension; | |
05ccbdfd | 1386 | { |
707641f6 JL |
1387 | int z, c, n, v; |
1388 | unsigned long reg1, imm, value; | |
1389 | ||
9f4a551e | 1390 | reg1 = State.regs[REG_A0 + REG0_16 (insn)]; |
7c52bf32 | 1391 | imm = ((insn & 0xffff) << 16) + extension; |
707641f6 | 1392 | value = reg1 - imm; |
65b784d8 | 1393 | State.regs[REG_A0 + REG0_16 (insn)] = value; |
707641f6 JL |
1394 | |
1395 | z = (value == 0); | |
1396 | n = (value & 0x80000000); | |
1397 | c = (reg1 < imm); | |
b7b89deb JL |
1398 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1399 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
707641f6 JL |
1400 | |
1401 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1402 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1403 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1404 | } |
1405 | ||
de0dce7c | 1406 | /* subc dm, dn */ |
d2523010 JL |
1407 | void OP_F180 (insn, extension) |
1408 | unsigned long insn, extension; | |
05ccbdfd | 1409 | { |
707641f6 JL |
1410 | int z, c, n, v; |
1411 | unsigned long reg1, reg2, value; | |
1412 | ||
9f4a551e JL |
1413 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
1414 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
707641f6 | 1415 | value = reg2 - reg1 - ((PSW & PSW_C) != 0); |
65b784d8 | 1416 | State.regs[REG_D0 + REG0 (insn)] = value; |
707641f6 JL |
1417 | |
1418 | z = (value == 0); | |
1419 | n = (value & 0x80000000); | |
216e6557 | 1420 | c = (reg1 > reg2); |
b7b89deb JL |
1421 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1422 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
707641f6 JL |
1423 | |
1424 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1425 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1426 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1427 | } |
1428 | ||
de0dce7c | 1429 | /* mul dm, dn */ |
d2523010 JL |
1430 | void OP_F240 (insn, extension) |
1431 | unsigned long insn, extension; | |
05ccbdfd | 1432 | { |
707641f6 JL |
1433 | unsigned long long temp; |
1434 | int n, z; | |
1435 | ||
097e6924 JL |
1436 | temp = ((signed64)(signed32)State.regs[REG_D0 + REG0 (insn)] |
1437 | * (signed64)(signed32)State.regs[REG_D0 + REG1 (insn)]); | |
9f4a551e | 1438 | State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; |
65b784d8 | 1439 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;; |
9f4a551e JL |
1440 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); |
1441 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1442 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1443 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1444 | } |
1445 | ||
de0dce7c | 1446 | /* mulu dm, dn */ |
d2523010 JL |
1447 | void OP_F250 (insn, extension) |
1448 | unsigned long insn, extension; | |
05ccbdfd | 1449 | { |
707641f6 JL |
1450 | unsigned long long temp; |
1451 | int n, z; | |
1452 | ||
0983e650 JL |
1453 | temp = ((unsigned64)State.regs[REG_D0 + REG0 (insn)] |
1454 | * (unsigned64)State.regs[REG_D0 + REG1 (insn)]); | |
9f4a551e | 1455 | State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; |
65b784d8 | 1456 | State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; |
9f4a551e JL |
1457 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); |
1458 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1459 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1460 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1461 | } |
1462 | ||
de0dce7c | 1463 | /* div dm, dn */ |
d2523010 JL |
1464 | void OP_F260 (insn, extension) |
1465 | unsigned long insn, extension; | |
05ccbdfd | 1466 | { |
707641f6 JL |
1467 | long long temp; |
1468 | int n, z; | |
1469 | ||
1470 | temp = State.regs[REG_MDR]; | |
1471 | temp <<= 32; | |
9f4a551e JL |
1472 | temp |= State.regs[REG_D0 + REG0 (insn)]; |
1473 | State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + REG1 (insn)]; | |
1474 | temp /= (long)State.regs[REG_D0 + REG1 (insn)]; | |
1475 | State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; | |
9f4a551e JL |
1476 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); |
1477 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1478 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1479 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1480 | } |
1481 | ||
de0dce7c | 1482 | /* divu dm, dn */ |
d2523010 JL |
1483 | void OP_F270 (insn, extension) |
1484 | unsigned long insn, extension; | |
05ccbdfd | 1485 | { |
707641f6 JL |
1486 | unsigned long long temp; |
1487 | int n, z; | |
1488 | ||
1489 | temp = State.regs[REG_MDR]; | |
1490 | temp <<= 32; | |
9f4a551e JL |
1491 | temp |= State.regs[REG_D0 + REG0 (insn)]; |
1492 | State.regs[REG_MDR] = temp % State.regs[REG_D0 + REG1 (insn)]; | |
1493 | temp /= State.regs[REG_D0 + REG1 (insn)]; | |
1494 | State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; | |
9f4a551e JL |
1495 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); |
1496 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1497 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1498 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1499 | } |
1500 | ||
73e65298 | 1501 | /* inc dn */ |
d2523010 JL |
1502 | void OP_40 (insn, extension) |
1503 | unsigned long insn, extension; | |
05ccbdfd | 1504 | { |
61ecca95 | 1505 | int z,n,c,v; |
4d8ced6c | 1506 | unsigned int value, imm, reg1; |
61ecca95 | 1507 | |
9f4a551e | 1508 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
4d8ced6c JL |
1509 | imm = 1; |
1510 | value = reg1 + imm; | |
9f4a551e | 1511 | State.regs[REG_D0 + REG1 (insn)] = value; |
61ecca95 JL |
1512 | |
1513 | z = (value == 0); | |
1514 | n = (value & 0x80000000); | |
3406569f | 1515 | c = (value < imm); |
d657034d | 1516 | v = ((reg1 & 0x80000000) == (imm & 0x80000000) |
4d8ced6c | 1517 | && (reg1 & 0x80000000) != (value & 0x80000000)); |
61ecca95 JL |
1518 | |
1519 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1520 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1521 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1522 | } |
1523 | ||
73e65298 | 1524 | /* inc an */ |
d2523010 JL |
1525 | void OP_41 (insn, extension) |
1526 | unsigned long insn, extension; | |
05ccbdfd | 1527 | { |
9f4a551e | 1528 | State.regs[REG_A0 + REG1 (insn)] += 1; |
05ccbdfd JL |
1529 | } |
1530 | ||
92284aaa | 1531 | /* inc4 an */ |
d2523010 JL |
1532 | void OP_50 (insn, extension) |
1533 | unsigned long insn, extension; | |
05ccbdfd | 1534 | { |
9f4a551e | 1535 | State.regs[REG_A0 + REG0 (insn)] += 4; |
05ccbdfd JL |
1536 | } |
1537 | ||
92284aaa | 1538 | /* cmp imm8, dn */ |
d2523010 JL |
1539 | void OP_A000 (insn, extension) |
1540 | unsigned long insn, extension; | |
05ccbdfd | 1541 | { |
92284aaa JL |
1542 | int z, c, n, v; |
1543 | unsigned long reg1, imm, value; | |
1544 | ||
9f4a551e | 1545 | reg1 = State.regs[REG_D0 + REG0_8 (insn)]; |
92284aaa JL |
1546 | imm = SEXT8 (insn & 0xff); |
1547 | value = reg1 - imm; | |
1548 | ||
1549 | z = (value == 0); | |
1550 | n = (value & 0x80000000); | |
1551 | c = (reg1 < imm); | |
b7b89deb JL |
1552 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1553 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1554 | |
1555 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1556 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1557 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1558 | } |
1559 | ||
92284aaa | 1560 | /* cmp dm, dn */ |
d2523010 JL |
1561 | void OP_A0 (insn, extension) |
1562 | unsigned long insn, extension; | |
05ccbdfd | 1563 | { |
92284aaa JL |
1564 | int z, c, n, v; |
1565 | unsigned long reg1, reg2, value; | |
1566 | ||
9f4a551e JL |
1567 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
1568 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
707641f6 | 1569 | value = reg2 - reg1; |
92284aaa JL |
1570 | |
1571 | z = (value == 0); | |
1572 | n = (value & 0x80000000); | |
216e6557 | 1573 | c = (reg1 > reg2); |
b7b89deb JL |
1574 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1575 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1576 | |
1577 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1578 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1579 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1580 | } |
1581 | ||
92284aaa | 1582 | /* cmp dm, an */ |
d2523010 JL |
1583 | void OP_F1A0 (insn, extension) |
1584 | unsigned long insn, extension; | |
05ccbdfd | 1585 | { |
92284aaa JL |
1586 | int z, c, n, v; |
1587 | unsigned long reg1, reg2, value; | |
1588 | ||
9f4a551e JL |
1589 | reg1 = State.regs[REG_D0 + REG1 (insn)]; |
1590 | reg2 = State.regs[REG_A0 + REG0 (insn)]; | |
707641f6 | 1591 | value = reg2 - reg1; |
92284aaa JL |
1592 | |
1593 | z = (value == 0); | |
1594 | n = (value & 0x80000000); | |
216e6557 | 1595 | c = (reg1 > reg2); |
b7b89deb JL |
1596 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1597 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1598 | |
1599 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1600 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1601 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1602 | } |
1603 | ||
92284aaa | 1604 | /* cmp am, dn */ |
d2523010 JL |
1605 | void OP_F190 (insn, extension) |
1606 | unsigned long insn, extension; | |
05ccbdfd | 1607 | { |
92284aaa JL |
1608 | int z, c, n, v; |
1609 | unsigned long reg1, reg2, value; | |
1610 | ||
9f4a551e JL |
1611 | reg1 = State.regs[REG_A0 + REG1 (insn)]; |
1612 | reg2 = State.regs[REG_D0 + REG0 (insn)]; | |
707641f6 | 1613 | value = reg2 - reg1; |
92284aaa JL |
1614 | |
1615 | z = (value == 0); | |
1616 | n = (value & 0x80000000); | |
216e6557 | 1617 | c = (reg1 > reg2); |
b7b89deb JL |
1618 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1619 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1620 | |
1621 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1622 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1623 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1624 | } |
1625 | ||
92284aaa | 1626 | /* cmp imm8, an */ |
d2523010 JL |
1627 | void OP_B000 (insn, extension) |
1628 | unsigned long insn, extension; | |
05ccbdfd | 1629 | { |
92284aaa JL |
1630 | int z, c, n, v; |
1631 | unsigned long reg1, imm, value; | |
1632 | ||
9f4a551e | 1633 | reg1 = State.regs[REG_A0 + REG0_8 (insn)]; |
92284aaa JL |
1634 | imm = insn & 0xff; |
1635 | value = reg1 - imm; | |
1636 | ||
1637 | z = (value == 0); | |
1638 | n = (value & 0x80000000); | |
1639 | c = (reg1 < imm); | |
b7b89deb JL |
1640 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1641 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1642 | |
1643 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1644 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1645 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1646 | } |
1647 | ||
707641f6 | 1648 | /* cmp am, an */ |
d2523010 JL |
1649 | void OP_B0 (insn, extension) |
1650 | unsigned long insn, extension; | |
05ccbdfd | 1651 | { |
73e65298 JL |
1652 | int z, c, n, v; |
1653 | unsigned long reg1, reg2, value; | |
1654 | ||
9f4a551e JL |
1655 | reg1 = State.regs[REG_A0 + REG1 (insn)]; |
1656 | reg2 = State.regs[REG_A0 + REG0 (insn)]; | |
707641f6 | 1657 | value = reg2 - reg1; |
73e65298 JL |
1658 | |
1659 | z = (value == 0); | |
1660 | n = (value & 0x80000000); | |
216e6557 | 1661 | c = (reg1 > reg2); |
b7b89deb JL |
1662 | v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) |
1663 | && (reg2 & 0x80000000) != (value & 0x80000000)); | |
73e65298 JL |
1664 | |
1665 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1666 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1667 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1668 | } |
1669 | ||
707641f6 | 1670 | /* cmp imm16, dn */ |
d2523010 JL |
1671 | void OP_FAC80000 (insn, extension) |
1672 | unsigned long insn, extension; | |
05ccbdfd | 1673 | { |
92284aaa JL |
1674 | int z, c, n, v; |
1675 | unsigned long reg1, imm, value; | |
1676 | ||
9f4a551e | 1677 | reg1 = State.regs[REG_D0 + REG0_16 (insn)]; |
92284aaa JL |
1678 | imm = SEXT16 (insn & 0xffff); |
1679 | value = reg1 - imm; | |
1680 | ||
1681 | z = (value == 0); | |
1682 | n = (value & 0x80000000); | |
1683 | c = (reg1 < imm); | |
b7b89deb JL |
1684 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1685 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1686 | |
1687 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1688 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1689 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1690 | } |
1691 | ||
707641f6 | 1692 | /* cmp imm32, dn */ |
d2523010 JL |
1693 | void OP_FCC80000 (insn, extension) |
1694 | unsigned long insn, extension; | |
05ccbdfd | 1695 | { |
92284aaa JL |
1696 | int z, c, n, v; |
1697 | unsigned long reg1, imm, value; | |
1698 | ||
9f4a551e | 1699 | reg1 = State.regs[REG_D0 + REG0_16 (insn)]; |
7c52bf32 | 1700 | imm = ((insn & 0xffff) << 16) + extension; |
92284aaa JL |
1701 | value = reg1 - imm; |
1702 | ||
1703 | z = (value == 0); | |
1704 | n = (value & 0x80000000); | |
1705 | c = (reg1 < imm); | |
b7b89deb JL |
1706 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1707 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1708 | |
1709 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1710 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1711 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1712 | } |
1713 | ||
707641f6 | 1714 | /* cmp imm16, an */ |
d2523010 JL |
1715 | void OP_FAD80000 (insn, extension) |
1716 | unsigned long insn, extension; | |
05ccbdfd | 1717 | { |
92284aaa JL |
1718 | int z, c, n, v; |
1719 | unsigned long reg1, imm, value; | |
1720 | ||
9f4a551e | 1721 | reg1 = State.regs[REG_A0 + REG0_16 (insn)]; |
92284aaa JL |
1722 | imm = insn & 0xffff; |
1723 | value = reg1 - imm; | |
1724 | ||
1725 | z = (value == 0); | |
1726 | n = (value & 0x80000000); | |
1727 | c = (reg1 < imm); | |
b7b89deb JL |
1728 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1729 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1730 | |
1731 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1732 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1733 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1734 | } |
1735 | ||
707641f6 | 1736 | /* cmp imm32, an */ |
d2523010 JL |
1737 | void OP_FCD80000 (insn, extension) |
1738 | unsigned long insn, extension; | |
05ccbdfd | 1739 | { |
92284aaa JL |
1740 | int z, c, n, v; |
1741 | unsigned long reg1, imm, value; | |
1742 | ||
9f4a551e | 1743 | reg1 = State.regs[REG_A0 + REG0_16 (insn)]; |
7c52bf32 | 1744 | imm = ((insn & 0xffff) << 16) + extension; |
92284aaa JL |
1745 | value = reg1 - imm; |
1746 | ||
1747 | z = (value == 0); | |
1748 | n = (value & 0x80000000); | |
1749 | c = (reg1 < imm); | |
b7b89deb JL |
1750 | v = ((reg1 & 0x80000000) != (imm & 0x80000000) |
1751 | && (reg1 & 0x80000000) != (value & 0x80000000)); | |
92284aaa JL |
1752 | |
1753 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1754 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
1755 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
05ccbdfd JL |
1756 | } |
1757 | ||
707641f6 | 1758 | /* and dm, dn */ |
d2523010 JL |
1759 | void OP_F200 (insn, extension) |
1760 | unsigned long insn, extension; | |
05ccbdfd | 1761 | { |
707641f6 JL |
1762 | int n, z; |
1763 | ||
9f4a551e JL |
1764 | State.regs[REG_D0 + REG0 (insn)] &= State.regs[REG_D0 + REG1 (insn)]; |
1765 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
1766 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1767 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1768 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1769 | } |
1770 | ||
2e35551c | 1771 | /* and imm8, dn */ |
d2523010 JL |
1772 | void OP_F8E000 (insn, extension) |
1773 | unsigned long insn, extension; | |
05ccbdfd | 1774 | { |
2e35551c JL |
1775 | int n, z; |
1776 | ||
9f4a551e JL |
1777 | State.regs[REG_D0 + REG0_8 (insn)] &= (insn & 0xff); |
1778 | z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); | |
1779 | n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; | |
2e35551c JL |
1780 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1781 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1782 | } |
1783 | ||
ecb4b5a3 | 1784 | /* and imm16, dn */ |
d2523010 JL |
1785 | void OP_FAE00000 (insn, extension) |
1786 | unsigned long insn, extension; | |
05ccbdfd | 1787 | { |
ecb4b5a3 JL |
1788 | int n, z; |
1789 | ||
9f4a551e JL |
1790 | State.regs[REG_D0 + REG0_16 (insn)] &= (insn & 0xffff); |
1791 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); | |
1792 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
ecb4b5a3 JL |
1793 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1794 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1795 | } |
1796 | ||
de0dce7c | 1797 | /* and imm32, dn */ |
d2523010 JL |
1798 | void OP_FCE00000 (insn, extension) |
1799 | unsigned long insn, extension; | |
05ccbdfd | 1800 | { |
de0dce7c JL |
1801 | int n, z; |
1802 | ||
9f4a551e | 1803 | State.regs[REG_D0 + REG0_16 (insn)] |
7c52bf32 | 1804 | &= ((insn & 0xffff) << 16) + extension; |
9f4a551e JL |
1805 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); |
1806 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
de0dce7c JL |
1807 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1808 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1809 | } |
1810 | ||
ecb4b5a3 | 1811 | /* and imm16, psw */ |
d2523010 JL |
1812 | void OP_FAFC0000 (insn, extension) |
1813 | unsigned long insn, extension; | |
05ccbdfd | 1814 | { |
ecb4b5a3 | 1815 | PSW &= (insn & 0xffff); |
05ccbdfd JL |
1816 | } |
1817 | ||
707641f6 | 1818 | /* or dm, dn*/ |
d2523010 JL |
1819 | void OP_F210 (insn, extension) |
1820 | unsigned long insn, extension; | |
05ccbdfd | 1821 | { |
707641f6 JL |
1822 | int n, z; |
1823 | ||
9f4a551e JL |
1824 | State.regs[REG_D0 + REG0 (insn)] |= State.regs[REG_D0 + REG1 (insn)]; |
1825 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
1826 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1827 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1828 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1829 | } |
1830 | ||
2e35551c | 1831 | /* or imm8, dn */ |
d2523010 JL |
1832 | void OP_F8E400 (insn, extension) |
1833 | unsigned long insn, extension; | |
05ccbdfd | 1834 | { |
2e35551c JL |
1835 | int n, z; |
1836 | ||
9f4a551e JL |
1837 | State.regs[REG_D0 + REG0_8 (insn)] |= insn & 0xff; |
1838 | z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); | |
1839 | n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; | |
2e35551c JL |
1840 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1841 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1842 | } |
1843 | ||
ecb4b5a3 | 1844 | /* or imm16, dn*/ |
d2523010 JL |
1845 | void OP_FAE40000 (insn, extension) |
1846 | unsigned long insn, extension; | |
05ccbdfd | 1847 | { |
ecb4b5a3 JL |
1848 | int n, z; |
1849 | ||
9f4a551e JL |
1850 | State.regs[REG_D0 + REG0_16 (insn)] |= insn & 0xffff; |
1851 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); | |
1852 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
ecb4b5a3 JL |
1853 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1854 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1855 | } |
1856 | ||
de0dce7c | 1857 | /* or imm32, dn */ |
d2523010 JL |
1858 | void OP_FCE40000 (insn, extension) |
1859 | unsigned long insn, extension; | |
05ccbdfd | 1860 | { |
de0dce7c JL |
1861 | int n, z; |
1862 | ||
9f4a551e | 1863 | State.regs[REG_D0 + REG0_16 (insn)] |
7c52bf32 | 1864 | |= ((insn & 0xffff) << 16) + extension; |
9f4a551e JL |
1865 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); |
1866 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
de0dce7c JL |
1867 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1868 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1869 | } |
1870 | ||
ecb4b5a3 | 1871 | /* or imm16,psw */ |
d2523010 JL |
1872 | void OP_FAFD0000 (insn, extension) |
1873 | unsigned long insn, extension; | |
05ccbdfd | 1874 | { |
ecb4b5a3 | 1875 | PSW |= (insn & 0xffff); |
05ccbdfd JL |
1876 | } |
1877 | ||
65b784d8 | 1878 | /* xor dm, dn */ |
d2523010 JL |
1879 | void OP_F220 (insn, extension) |
1880 | unsigned long insn, extension; | |
05ccbdfd | 1881 | { |
707641f6 JL |
1882 | int n, z; |
1883 | ||
9f4a551e JL |
1884 | State.regs[REG_D0 + REG0 (insn)] ^= State.regs[REG_D0 + REG1 (insn)]; |
1885 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
1886 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1887 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1888 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1889 | } |
1890 | ||
ecb4b5a3 | 1891 | /* xor imm16, dn */ |
d2523010 JL |
1892 | void OP_FAE80000 (insn, extension) |
1893 | unsigned long insn, extension; | |
05ccbdfd | 1894 | { |
ecb4b5a3 JL |
1895 | int n, z; |
1896 | ||
9f4a551e JL |
1897 | State.regs[REG_D0 + REG0_16 (insn)] ^= insn & 0xffff; |
1898 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); | |
1899 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
ecb4b5a3 JL |
1900 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1901 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1902 | } |
1903 | ||
de0dce7c | 1904 | /* xor imm32, dn */ |
d2523010 JL |
1905 | void OP_FCE80000 (insn, extension) |
1906 | unsigned long insn, extension; | |
05ccbdfd | 1907 | { |
de0dce7c JL |
1908 | int n, z; |
1909 | ||
9f4a551e | 1910 | State.regs[REG_D0 + REG0_16 (insn)] |
7c52bf32 | 1911 | ^= ((insn & 0xffff) << 16) + extension; |
9f4a551e JL |
1912 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); |
1913 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
de0dce7c JL |
1914 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1915 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1916 | } |
1917 | ||
de0dce7c | 1918 | /* not dn */ |
d2523010 JL |
1919 | void OP_F230 (insn, extension) |
1920 | unsigned long insn, extension; | |
05ccbdfd | 1921 | { |
707641f6 JL |
1922 | int n, z; |
1923 | ||
9f4a551e JL |
1924 | State.regs[REG_D0 + REG0 (insn)] = ~State.regs[REG_D0 + REG0 (insn)]; |
1925 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
1926 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
1927 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
1928 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
1929 | } |
1930 | ||
2e35551c | 1931 | /* btst imm8, dn */ |
d2523010 JL |
1932 | void OP_F8EC00 (insn, extension) |
1933 | unsigned long insn, extension; | |
05ccbdfd | 1934 | { |
2e35551c JL |
1935 | unsigned long temp; |
1936 | int z, n; | |
1937 | ||
9f4a551e | 1938 | temp = State.regs[REG_D0 + REG0_8 (insn)]; |
2e35551c JL |
1939 | temp &= (insn & 0xff); |
1940 | n = (temp & 0x80000000) != 0; | |
1941 | z = (temp == 0); | |
1942 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1943 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
05ccbdfd JL |
1944 | } |
1945 | ||
ecb4b5a3 | 1946 | /* btst imm16, dn */ |
d2523010 JL |
1947 | void OP_FAEC0000 (insn, extension) |
1948 | unsigned long insn, extension; | |
05ccbdfd | 1949 | { |
ecb4b5a3 JL |
1950 | unsigned long temp; |
1951 | int z, n; | |
1952 | ||
9f4a551e | 1953 | temp = State.regs[REG_D0 + REG0_16 (insn)]; |
ecb4b5a3 JL |
1954 | temp &= (insn & 0xffff); |
1955 | n = (temp & 0x80000000) != 0; | |
1956 | z = (temp == 0); | |
1957 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1958 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
05ccbdfd JL |
1959 | } |
1960 | ||
de0dce7c | 1961 | /* btst imm32, dn */ |
d2523010 JL |
1962 | void OP_FCEC0000 (insn, extension) |
1963 | unsigned long insn, extension; | |
05ccbdfd | 1964 | { |
de0dce7c JL |
1965 | unsigned long temp; |
1966 | int z, n; | |
1967 | ||
9f4a551e | 1968 | temp = State.regs[REG_D0 + REG0_16 (insn)]; |
7c52bf32 | 1969 | temp &= ((insn & 0xffff) << 16) + extension; |
de0dce7c JL |
1970 | n = (temp & 0x80000000) != 0; |
1971 | z = (temp == 0); | |
1972 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1973 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
05ccbdfd JL |
1974 | } |
1975 | ||
de0dce7c | 1976 | /* btst imm8,(abs32) */ |
d2523010 JL |
1977 | void OP_FE020000 (insn, extension) |
1978 | unsigned long insn, extension; | |
05ccbdfd | 1979 | { |
de0dce7c JL |
1980 | unsigned long temp; |
1981 | int n, z; | |
1982 | ||
003c91be | 1983 | temp = load_byte (((insn & 0xffff) << 16) | (extension >> 8)); |
de0dce7c JL |
1984 | temp &= (extension & 0xff); |
1985 | n = (temp & 0x80000000) != 0; | |
1986 | z = (temp == 0); | |
1987 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
1988 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
05ccbdfd JL |
1989 | } |
1990 | ||
ecb4b5a3 | 1991 | /* btst imm8,(d8,an) */ |
d2523010 JL |
1992 | void OP_FAF80000 (insn, extension) |
1993 | unsigned long insn, extension; | |
05ccbdfd | 1994 | { |
ecb4b5a3 JL |
1995 | unsigned long temp; |
1996 | int n, z; | |
1997 | ||
003c91be JL |
1998 | temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)] |
1999 | + SEXT8 ((insn & 0xff00) >> 8))); | |
ecb4b5a3 JL |
2000 | temp &= (insn & 0xff); |
2001 | n = (temp & 0x80000000) != 0; | |
2002 | z = (temp == 0); | |
2003 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
2004 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
05ccbdfd JL |
2005 | } |
2006 | ||
707641f6 | 2007 | /* bset dm, (an) */ |
d2523010 JL |
2008 | void OP_F080 (insn, extension) |
2009 | unsigned long insn, extension; | |
05ccbdfd | 2010 | { |
707641f6 JL |
2011 | unsigned long temp; |
2012 | int z; | |
2013 | ||
003c91be | 2014 | temp = load_byte (State.regs[REG_A0 + REG0 (insn)]); |
9f4a551e JL |
2015 | z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0; |
2016 | temp |= State.regs[REG_D0 + REG1 (insn)]; | |
003c91be | 2017 | store_byte (State.regs[REG_A0 + REG0 (insn)], temp); |
707641f6 JL |
2018 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
2019 | PSW |= (z ? PSW_Z : 0); | |
05ccbdfd JL |
2020 | } |
2021 | ||
de0dce7c | 2022 | /* bset imm8, (abs32) */ |
d2523010 JL |
2023 | void OP_FE000000 (insn, extension) |
2024 | unsigned long insn, extension; | |
05ccbdfd | 2025 | { |
de0dce7c JL |
2026 | unsigned long temp; |
2027 | int z; | |
2028 | ||
003c91be | 2029 | temp = load_byte (((insn & 0xffff) << 16 | (extension >> 8))); |
de0dce7c JL |
2030 | z = (temp & (extension & 0xff)) == 0; |
2031 | temp |= (extension & 0xff); | |
003c91be | 2032 | store_byte ((((insn & 0xffff) << 16) | (extension >> 8)), temp); |
de0dce7c JL |
2033 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
2034 | PSW |= (z ? PSW_Z : 0); | |
05ccbdfd JL |
2035 | } |
2036 | ||
ecb4b5a3 | 2037 | /* bset imm8,(d8,an) */ |
d2523010 JL |
2038 | void OP_FAF00000 (insn, extension) |
2039 | unsigned long insn, extension; | |
05ccbdfd | 2040 | { |
ecb4b5a3 JL |
2041 | unsigned long temp; |
2042 | int z; | |
2043 | ||
003c91be JL |
2044 | temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)] |
2045 | + SEXT8 ((insn & 0xff00) >> 8))); | |
ecb4b5a3 JL |
2046 | z = (temp & (insn & 0xff)) == 0; |
2047 | temp |= (insn & 0xff); | |
003c91be JL |
2048 | store_byte ((State.regs[REG_A0 + REG0_16 (insn)] |
2049 | + SEXT8 ((insn & 0xff00) >> 8)), temp); | |
ecb4b5a3 JL |
2050 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
2051 | PSW |= (z ? PSW_Z : 0); | |
05ccbdfd JL |
2052 | } |
2053 | ||
707641f6 | 2054 | /* bclr dm, (an) */ |
d2523010 JL |
2055 | void OP_F090 (insn, extension) |
2056 | unsigned long insn, extension; | |
05ccbdfd | 2057 | { |
707641f6 JL |
2058 | unsigned long temp; |
2059 | int z; | |
2060 | ||
003c91be | 2061 | temp = load_byte (State.regs[REG_A0 + REG0 (insn)]); |
9f4a551e | 2062 | z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0; |
09eef8af | 2063 | temp = temp & ~State.regs[REG_D0 + REG1 (insn)]; |
003c91be | 2064 | store_byte (State.regs[REG_A0 + REG0 (insn)], temp); |
707641f6 JL |
2065 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
2066 | PSW |= (z ? PSW_Z : 0); | |
05ccbdfd JL |
2067 | } |
2068 | ||
de0dce7c | 2069 | /* bclr imm8, (abs32) */ |
d2523010 JL |
2070 | void OP_FE010000 (insn, extension) |
2071 | unsigned long insn, extension; | |
05ccbdfd | 2072 | { |
de0dce7c JL |
2073 | unsigned long temp; |
2074 | int z; | |
2075 | ||
003c91be | 2076 | temp = load_byte (((insn & 0xffff) << 16) | (extension >> 8)); |
de0dce7c | 2077 | z = (temp & (extension & 0xff)) == 0; |
09eef8af | 2078 | temp = temp & ~(extension & 0xff); |
003c91be | 2079 | store_byte (((insn & 0xffff) << 16) | (extension >> 8), temp); |
de0dce7c JL |
2080 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
2081 | PSW |= (z ? PSW_Z : 0); | |
05ccbdfd JL |
2082 | } |
2083 | ||
ecb4b5a3 | 2084 | /* bclr imm8,(d8,an) */ |
d2523010 JL |
2085 | void OP_FAF40000 (insn, extension) |
2086 | unsigned long insn, extension; | |
05ccbdfd | 2087 | { |
ecb4b5a3 JL |
2088 | unsigned long temp; |
2089 | int z; | |
2090 | ||
003c91be JL |
2091 | temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)] |
2092 | + SEXT8 ((insn & 0xff00) >> 8))); | |
ecb4b5a3 | 2093 | z = (temp & (insn & 0xff)) == 0; |
09eef8af | 2094 | temp = temp & ~(insn & 0xff); |
003c91be JL |
2095 | store_byte ((State.regs[REG_A0 + REG0_16 (insn)] |
2096 | + SEXT8 ((insn & 0xff00) >> 8)), temp); | |
ecb4b5a3 JL |
2097 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
2098 | PSW |= (z ? PSW_Z : 0); | |
05ccbdfd JL |
2099 | } |
2100 | ||
2e35551c | 2101 | /* asr dm, dn */ |
d2523010 JL |
2102 | void OP_F2B0 (insn, extension) |
2103 | unsigned long insn, extension; | |
05ccbdfd | 2104 | { |
707641f6 JL |
2105 | long temp; |
2106 | int z, n, c; | |
2107 | ||
9f4a551e | 2108 | temp = State.regs[REG_D0 + REG0 (insn)]; |
707641f6 | 2109 | c = temp & 1; |
9f4a551e JL |
2110 | temp >>= State.regs[REG_D0 + REG1 (insn)]; |
2111 | State.regs[REG_D0 + REG0 (insn)] = temp; | |
2112 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
2113 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
2114 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
2115 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
05ccbdfd JL |
2116 | } |
2117 | ||
2e35551c | 2118 | /* asr imm8, dn */ |
d2523010 JL |
2119 | void OP_F8C800 (insn, extension) |
2120 | unsigned long insn, extension; | |
05ccbdfd | 2121 | { |
2e35551c JL |
2122 | long temp; |
2123 | int z, n, c; | |
2124 | ||
9f4a551e | 2125 | temp = State.regs[REG_D0 + REG0_8 (insn)]; |
2e35551c JL |
2126 | c = temp & 1; |
2127 | temp >>= (insn & 0xff); | |
9f4a551e JL |
2128 | State.regs[REG_D0 + REG0_8 (insn)] = temp; |
2129 | z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); | |
2130 | n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; | |
2e35551c JL |
2131 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
2132 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
05ccbdfd JL |
2133 | } |
2134 | ||
2e35551c | 2135 | /* lsr dm, dn */ |
d2523010 JL |
2136 | void OP_F2A0 (insn, extension) |
2137 | unsigned long insn, extension; | |
05ccbdfd | 2138 | { |
707641f6 JL |
2139 | int z, n, c; |
2140 | ||
9f4a551e JL |
2141 | c = State.regs[REG_D0 + REG0 (insn)] & 1; |
2142 | State.regs[REG_D0 + REG0 (insn)] | |
2143 | >>= State.regs[REG_D0 + REG1 (insn)]; | |
2144 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
2145 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
2146 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
2147 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
05ccbdfd JL |
2148 | } |
2149 | ||
43eb4bed | 2150 | /* lsr imm8, dn */ |
d2523010 JL |
2151 | void OP_F8C400 (insn, extension) |
2152 | unsigned long insn, extension; | |
05ccbdfd | 2153 | { |
2e35551c JL |
2154 | int z, n, c; |
2155 | ||
9f4a551e JL |
2156 | c = State.regs[REG_D0 + REG0_8 (insn)] & 1; |
2157 | State.regs[REG_D0 + REG0_8 (insn)] >>= (insn & 0xff); | |
43eb4bed JL |
2158 | z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); |
2159 | n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; | |
2e35551c JL |
2160 | PSW &= ~(PSW_Z | PSW_N | PSW_C); |
2161 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
05ccbdfd JL |
2162 | } |
2163 | ||
2e35551c | 2164 | /* asl dm, dn */ |
d2523010 JL |
2165 | void OP_F290 (insn, extension) |
2166 | unsigned long insn, extension; | |
05ccbdfd | 2167 | { |
707641f6 JL |
2168 | int n, z; |
2169 | ||
9f4a551e JL |
2170 | State.regs[REG_D0 + REG0 (insn)] |
2171 | <<= State.regs[REG_D0 + REG1 (insn)]; | |
2172 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
2173 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
2174 | PSW &= ~(PSW_Z | PSW_N); |
2175 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
2176 | } |
2177 | ||
2e35551c | 2178 | /* asl imm8, dn */ |
d2523010 JL |
2179 | void OP_F8C000 (insn, extension) |
2180 | unsigned long insn, extension; | |
05ccbdfd | 2181 | { |
2e35551c JL |
2182 | int n, z; |
2183 | ||
9f4a551e JL |
2184 | State.regs[REG_D0 + REG0_8 (insn)] <<= (insn & 0xff); |
2185 | z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); | |
2186 | n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; | |
2e35551c JL |
2187 | PSW &= ~(PSW_Z | PSW_N); |
2188 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
2189 | } |
2190 | ||
707641f6 | 2191 | /* asl2 dn */ |
d2523010 JL |
2192 | void OP_54 (insn, extension) |
2193 | unsigned long insn, extension; | |
05ccbdfd | 2194 | { |
707641f6 JL |
2195 | int n, z; |
2196 | ||
9f4a551e JL |
2197 | State.regs[REG_D0 + REG0 (insn)] <<= 2; |
2198 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
2199 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
707641f6 JL |
2200 | PSW &= ~(PSW_Z | PSW_N); |
2201 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
2202 | } |
2203 | ||
707641f6 | 2204 | /* ror dn */ |
d2523010 JL |
2205 | void OP_F284 (insn, extension) |
2206 | unsigned long insn, extension; | |
05ccbdfd | 2207 | { |
707641f6 JL |
2208 | unsigned long value; |
2209 | int c,n,z; | |
2210 | ||
9f4a551e | 2211 | value = State.regs[REG_D0 + REG0 (insn)]; |
7c52bf32 | 2212 | c = (value & 0x1); |
707641f6 JL |
2213 | |
2214 | value >>= 1; | |
f95251f0 | 2215 | value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0; |
9f4a551e | 2216 | State.regs[REG_D0 + REG0 (insn)] = value; |
707641f6 | 2217 | z = (value == 0); |
b7b89deb | 2218 | n = (value & 0x80000000) != 0; |
707641f6 JL |
2219 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
2220 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
05ccbdfd JL |
2221 | } |
2222 | ||
707641f6 | 2223 | /* rol dn */ |
d2523010 JL |
2224 | void OP_F280 (insn, extension) |
2225 | unsigned long insn, extension; | |
05ccbdfd | 2226 | { |
707641f6 JL |
2227 | unsigned long value; |
2228 | int c,n,z; | |
2229 | ||
9f4a551e | 2230 | value = State.regs[REG_D0 + REG0 (insn)]; |
7c52bf32 | 2231 | c = (value & 0x80000000) ? 1 : 0; |
707641f6 JL |
2232 | |
2233 | value <<= 1; | |
f95251f0 | 2234 | value |= ((PSW & PSW_C) != 0); |
9f4a551e | 2235 | State.regs[REG_D0 + REG0 (insn)] = value; |
707641f6 | 2236 | z = (value == 0); |
b7b89deb | 2237 | n = (value & 0x80000000) != 0; |
707641f6 JL |
2238 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
2239 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); | |
05ccbdfd JL |
2240 | } |
2241 | ||
f5f13c1d | 2242 | /* beq label:8 */ |
d2523010 JL |
2243 | void OP_C800 (insn, extension) |
2244 | unsigned long insn, extension; | |
05ccbdfd | 2245 | { |
73e65298 JL |
2246 | /* The dispatching code will add 2 after we return, so |
2247 | we subtract two here to make things right. */ | |
2248 | if (PSW & PSW_Z) | |
b774c0e4 | 2249 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2250 | } |
2251 | ||
f5f13c1d | 2252 | /* bne label:8 */ |
d2523010 JL |
2253 | void OP_C900 (insn, extension) |
2254 | unsigned long insn, extension; | |
05ccbdfd | 2255 | { |
73e65298 JL |
2256 | /* The dispatching code will add 2 after we return, so |
2257 | we subtract two here to make things right. */ | |
2258 | if (!(PSW & PSW_Z)) | |
b774c0e4 | 2259 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2260 | } |
2261 | ||
f5f13c1d | 2262 | /* bgt label:8 */ |
d2523010 JL |
2263 | void OP_C100 (insn, extension) |
2264 | unsigned long insn, extension; | |
05ccbdfd | 2265 | { |
f5f13c1d JL |
2266 | /* The dispatching code will add 2 after we return, so |
2267 | we subtract two here to make things right. */ | |
2268 | if (!((PSW & PSW_Z) | |
7c52bf32 | 2269 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))) |
b774c0e4 | 2270 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2271 | } |
2272 | ||
f5f13c1d | 2273 | /* bge label:8 */ |
d2523010 JL |
2274 | void OP_C200 (insn, extension) |
2275 | unsigned long insn, extension; | |
05ccbdfd | 2276 | { |
f5f13c1d JL |
2277 | /* The dispatching code will add 2 after we return, so |
2278 | we subtract two here to make things right. */ | |
7c52bf32 | 2279 | if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) |
b774c0e4 | 2280 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2281 | } |
2282 | ||
f5f13c1d | 2283 | /* ble label:8 */ |
d2523010 JL |
2284 | void OP_C300 (insn, extension) |
2285 | unsigned long insn, extension; | |
05ccbdfd | 2286 | { |
f5f13c1d JL |
2287 | /* The dispatching code will add 2 after we return, so |
2288 | we subtract two here to make things right. */ | |
2289 | if ((PSW & PSW_Z) | |
7c52bf32 | 2290 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) |
b774c0e4 | 2291 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2292 | } |
2293 | ||
f5f13c1d | 2294 | /* blt label:8 */ |
d2523010 JL |
2295 | void OP_C000 (insn, extension) |
2296 | unsigned long insn, extension; | |
05ccbdfd | 2297 | { |
f5f13c1d JL |
2298 | /* The dispatching code will add 2 after we return, so |
2299 | we subtract two here to make things right. */ | |
7c52bf32 | 2300 | if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)) |
b774c0e4 | 2301 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2302 | } |
2303 | ||
f5f13c1d | 2304 | /* bhi label:8 */ |
d2523010 JL |
2305 | void OP_C500 (insn, extension) |
2306 | unsigned long insn, extension; | |
05ccbdfd | 2307 | { |
f5f13c1d JL |
2308 | /* The dispatching code will add 2 after we return, so |
2309 | we subtract two here to make things right. */ | |
2310 | if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)) | |
b774c0e4 | 2311 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2312 | } |
2313 | ||
f5f13c1d | 2314 | /* bcc label:8 */ |
d2523010 JL |
2315 | void OP_C600 (insn, extension) |
2316 | unsigned long insn, extension; | |
05ccbdfd | 2317 | { |
f5f13c1d JL |
2318 | /* The dispatching code will add 2 after we return, so |
2319 | we subtract two here to make things right. */ | |
2320 | if (!(PSW & PSW_C)) | |
b774c0e4 | 2321 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2322 | } |
2323 | ||
f5f13c1d | 2324 | /* bls label:8 */ |
d2523010 JL |
2325 | void OP_C700 (insn, extension) |
2326 | unsigned long insn, extension; | |
05ccbdfd | 2327 | { |
f5f13c1d JL |
2328 | /* The dispatching code will add 2 after we return, so |
2329 | we subtract two here to make things right. */ | |
2330 | if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0) | |
b774c0e4 | 2331 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2332 | } |
2333 | ||
f5f13c1d | 2334 | /* bcs label:8 */ |
d2523010 JL |
2335 | void OP_C400 (insn, extension) |
2336 | unsigned long insn, extension; | |
05ccbdfd | 2337 | { |
f5f13c1d JL |
2338 | /* The dispatching code will add 2 after we return, so |
2339 | we subtract two here to make things right. */ | |
2340 | if (PSW & PSW_C) | |
b774c0e4 | 2341 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2342 | } |
2343 | ||
f5f13c1d | 2344 | /* bvc label:8 */ |
d2523010 JL |
2345 | void OP_F8E800 (insn, extension) |
2346 | unsigned long insn, extension; | |
05ccbdfd | 2347 | { |
f5f13c1d JL |
2348 | /* The dispatching code will add 3 after we return, so |
2349 | we subtract two here to make things right. */ | |
2350 | if (!(PSW & PSW_V)) | |
b774c0e4 | 2351 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3; |
05ccbdfd JL |
2352 | } |
2353 | ||
f5f13c1d | 2354 | /* bvs label:8 */ |
d2523010 JL |
2355 | void OP_F8E900 (insn, extension) |
2356 | unsigned long insn, extension; | |
05ccbdfd | 2357 | { |
f5f13c1d JL |
2358 | /* The dispatching code will add 3 after we return, so |
2359 | we subtract two here to make things right. */ | |
2360 | if (PSW & PSW_V) | |
b774c0e4 | 2361 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3; |
05ccbdfd JL |
2362 | } |
2363 | ||
f5f13c1d | 2364 | /* bnc label:8 */ |
d2523010 JL |
2365 | void OP_F8EA00 (insn, extension) |
2366 | unsigned long insn, extension; | |
05ccbdfd | 2367 | { |
f5f13c1d JL |
2368 | /* The dispatching code will add 3 after we return, so |
2369 | we subtract two here to make things right. */ | |
2370 | if (!(PSW & PSW_N)) | |
b774c0e4 | 2371 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3; |
05ccbdfd JL |
2372 | } |
2373 | ||
f5f13c1d | 2374 | /* bns label:8 */ |
d2523010 JL |
2375 | void OP_F8EB00 (insn, extension) |
2376 | unsigned long insn, extension; | |
05ccbdfd | 2377 | { |
f5f13c1d JL |
2378 | /* The dispatching code will add 3 after we return, so |
2379 | we subtract two here to make things right. */ | |
2380 | if (PSW & PSW_N) | |
b774c0e4 | 2381 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3; |
05ccbdfd JL |
2382 | } |
2383 | ||
f5f13c1d | 2384 | /* bra label:8 */ |
d2523010 JL |
2385 | void OP_CA00 (insn, extension) |
2386 | unsigned long insn, extension; | |
05ccbdfd | 2387 | { |
f5f13c1d JL |
2388 | /* The dispatching code will add 2 after we return, so |
2389 | we subtract two here to make things right. */ | |
b774c0e4 | 2390 | State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; |
05ccbdfd JL |
2391 | } |
2392 | ||
2393 | /* leq */ | |
d2523010 JL |
2394 | void OP_D8 (insn, extension) |
2395 | unsigned long insn, extension; | |
05ccbdfd | 2396 | { |
65b784d8 JL |
2397 | /* The dispatching code will add 1 after we return, so |
2398 | we subtract one here to make things right. */ | |
2399 | if (PSW & PSW_Z) | |
2400 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2401 | } |
2402 | ||
2403 | /* lne */ | |
d2523010 JL |
2404 | void OP_D9 (insn, extension) |
2405 | unsigned long insn, extension; | |
05ccbdfd | 2406 | { |
65b784d8 JL |
2407 | /* The dispatching code will add 1 after we return, so |
2408 | we subtract one here to make things right. */ | |
2409 | if (!(PSW & PSW_Z)) | |
2410 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2411 | } |
2412 | ||
2413 | /* lgt */ | |
d2523010 JL |
2414 | void OP_D1 (insn, extension) |
2415 | unsigned long insn, extension; | |
05ccbdfd | 2416 | { |
65b784d8 JL |
2417 | /* The dispatching code will add 1 after we return, so |
2418 | we subtract one here to make things right. */ | |
2419 | if (!((PSW & PSW_Z) | |
2420 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))) | |
2421 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2422 | } |
2423 | ||
2424 | /* lge */ | |
d2523010 JL |
2425 | void OP_D2 (insn, extension) |
2426 | unsigned long insn, extension; | |
05ccbdfd | 2427 | { |
65b784d8 JL |
2428 | /* The dispatching code will add 1 after we return, so |
2429 | we subtract one here to make things right. */ | |
2430 | if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) | |
2431 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2432 | } |
2433 | ||
2434 | /* lle */ | |
d2523010 JL |
2435 | void OP_D3 (insn, extension) |
2436 | unsigned long insn, extension; | |
05ccbdfd | 2437 | { |
65b784d8 JL |
2438 | /* The dispatching code will add 1 after we return, so |
2439 | we subtract one here to make things right. */ | |
2440 | if ((PSW & PSW_Z) | |
2441 | || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) | |
2442 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2443 | } |
2444 | ||
2445 | /* llt */ | |
d2523010 JL |
2446 | void OP_D0 (insn, extension) |
2447 | unsigned long insn, extension; | |
05ccbdfd | 2448 | { |
65b784d8 JL |
2449 | /* The dispatching code will add 1 after we return, so |
2450 | we subtract one here to make things right. */ | |
2451 | if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)) | |
2452 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2453 | } |
2454 | ||
2455 | /* lhi */ | |
d2523010 JL |
2456 | void OP_D5 (insn, extension) |
2457 | unsigned long insn, extension; | |
05ccbdfd | 2458 | { |
65b784d8 JL |
2459 | /* The dispatching code will add 1 after we return, so |
2460 | we subtract one here to make things right. */ | |
2461 | if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)) | |
2462 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2463 | } |
2464 | ||
2465 | /* lcc */ | |
d2523010 JL |
2466 | void OP_D6 (insn, extension) |
2467 | unsigned long insn, extension; | |
05ccbdfd | 2468 | { |
65b784d8 JL |
2469 | /* The dispatching code will add 1 after we return, so |
2470 | we subtract one here to make things right. */ | |
2471 | if (!(PSW & PSW_C)) | |
2472 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2473 | } |
2474 | ||
2475 | /* lls */ | |
d2523010 JL |
2476 | void OP_D7 (insn, extension) |
2477 | unsigned long insn, extension; | |
05ccbdfd | 2478 | { |
65b784d8 JL |
2479 | /* The dispatching code will add 1 after we return, so |
2480 | we subtract one here to make things right. */ | |
2481 | if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0) | |
2482 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2483 | } |
2484 | ||
2485 | /* lcs */ | |
d2523010 JL |
2486 | void OP_D4 (insn, extension) |
2487 | unsigned long insn, extension; | |
05ccbdfd | 2488 | { |
65b784d8 JL |
2489 | /* The dispatching code will add 1 after we return, so |
2490 | we subtract one here to make things right. */ | |
2491 | if (PSW & PSW_C) | |
2492 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; | |
05ccbdfd JL |
2493 | } |
2494 | ||
2495 | /* lra */ | |
d2523010 JL |
2496 | void OP_DA (insn, extension) |
2497 | unsigned long insn, extension; | |
05ccbdfd | 2498 | { |
65b784d8 | 2499 | State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; |
05ccbdfd JL |
2500 | } |
2501 | ||
2502 | /* setlb */ | |
d2523010 JL |
2503 | void OP_DB (insn, extension) |
2504 | unsigned long insn, extension; | |
05ccbdfd | 2505 | { |
65b784d8 JL |
2506 | State.regs[REG_LIR] = load_mem_big (State.regs[REG_PC] + 1, 4); |
2507 | State.regs[REG_LAR] = State.regs[REG_PC] + 5; | |
05ccbdfd JL |
2508 | } |
2509 | ||
707641f6 | 2510 | /* jmp (an) */ |
d2523010 JL |
2511 | void OP_F0F4 (insn, extension) |
2512 | unsigned long insn, extension; | |
05ccbdfd | 2513 | { |
b774c0e4 | 2514 | State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2; |
05ccbdfd JL |
2515 | } |
2516 | ||
707641f6 | 2517 | /* jmp label:16 */ |
d2523010 JL |
2518 | void OP_CC0000 (insn, extension) |
2519 | unsigned long insn, extension; | |
05ccbdfd | 2520 | { |
b774c0e4 | 2521 | State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 3; |
05ccbdfd JL |
2522 | } |
2523 | ||
707641f6 | 2524 | /* jmp label:32 */ |
d2523010 JL |
2525 | void OP_DC000000 (insn, extension) |
2526 | unsigned long insn, extension; | |
05ccbdfd | 2527 | { |
b774c0e4 | 2528 | State.regs[REG_PC] += (((insn & 0xffffff) << 8) + extension) - 5; |
05ccbdfd JL |
2529 | } |
2530 | ||
707641f6 | 2531 | /* call label:16,reg_list,imm8 */ |
d2523010 JL |
2532 | void OP_CD000000 (insn, extension) |
2533 | unsigned long insn, extension; | |
05ccbdfd | 2534 | { |
dbdb5bd8 | 2535 | unsigned int next_pc, sp; |
707641f6 JL |
2536 | unsigned long mask; |
2537 | ||
2538 | sp = State.regs[REG_SP]; | |
0a8fa63c | 2539 | next_pc = State.regs[REG_PC] + 5; |
707641f6 | 2540 | State.mem[sp] = next_pc & 0xff; |
3bb3fe44 JL |
2541 | State.mem[sp+1] = (next_pc & 0xff00) >> 8; |
2542 | State.mem[sp+2] = (next_pc & 0xff0000) >> 16; | |
2543 | State.mem[sp+3] = (next_pc & 0xff000000) >> 24; | |
707641f6 JL |
2544 | |
2545 | mask = insn & 0xff; | |
2546 | ||
707641f6 JL |
2547 | if (mask & 0x80) |
2548 | { | |
dbdb5bd8 JL |
2549 | sp -= 4; |
2550 | store_word (sp, State.regs[REG_D0 + 2]); | |
707641f6 JL |
2551 | } |
2552 | ||
2553 | if (mask & 0x40) | |
2554 | { | |
dbdb5bd8 JL |
2555 | sp -= 4; |
2556 | store_word (sp, State.regs[REG_D0 + 3]); | |
707641f6 JL |
2557 | } |
2558 | ||
2559 | if (mask & 0x20) | |
2560 | { | |
dbdb5bd8 JL |
2561 | sp -= 4; |
2562 | store_word (sp, State.regs[REG_A0 + 2]); | |
707641f6 JL |
2563 | } |
2564 | ||
2565 | if (mask & 0x10) | |
2566 | { | |
dbdb5bd8 JL |
2567 | sp -= 4; |
2568 | store_word (sp, State.regs[REG_A0 + 3]); | |
707641f6 JL |
2569 | } |
2570 | ||
2571 | if (mask & 0x8) | |
2572 | { | |
dbdb5bd8 JL |
2573 | sp -= 4; |
2574 | store_word (sp, State.regs[REG_D0]); | |
2575 | sp -= 4; | |
2576 | store_word (sp, State.regs[REG_D0 + 1]); | |
2577 | sp -= 4; | |
2578 | store_word (sp, State.regs[REG_A0]); | |
2579 | sp -= 4; | |
2580 | store_word (sp, State.regs[REG_A0 + 1]); | |
2581 | sp -= 4; | |
2582 | store_word (sp, State.regs[REG_MDR]); | |
2583 | sp -= 4; | |
2584 | store_word (sp, State.regs[REG_LIR]); | |
2585 | sp -= 4; | |
2586 | store_word (sp, State.regs[REG_LAR]); | |
2587 | sp -= 4; | |
707641f6 JL |
2588 | } |
2589 | ||
fc615b0b JL |
2590 | /* Update the stack pointer, note that the register saves to do not |
2591 | modify SP. The SP adjustment is derived totally from the imm8 | |
2592 | field. */ | |
2593 | State.regs[REG_SP] -= extension; | |
707641f6 | 2594 | State.regs[REG_MDR] = next_pc; |
b774c0e4 | 2595 | State.regs[REG_PC] += SEXT16 ((insn & 0xffff00) >> 8) - 5; |
05ccbdfd JL |
2596 | } |
2597 | ||
707641f6 | 2598 | /* call label:32,reg_list,imm8*/ |
d2523010 JL |
2599 | void OP_DD000000 (insn, extension) |
2600 | unsigned long insn, extension; | |
05ccbdfd | 2601 | { |
707641f6 JL |
2602 | unsigned int next_pc, sp, adjust; |
2603 | unsigned long mask; | |
2604 | ||
2605 | sp = State.regs[REG_SP]; | |
0a8fa63c | 2606 | next_pc = State.regs[REG_PC] + 7; |
707641f6 | 2607 | State.mem[sp] = next_pc & 0xff; |
3bb3fe44 JL |
2608 | State.mem[sp+1] = (next_pc & 0xff00) >> 8; |
2609 | State.mem[sp+2] = (next_pc & 0xff0000) >> 16; | |
2610 | State.mem[sp+3] = (next_pc & 0xff000000) >> 24; | |
707641f6 JL |
2611 | |
2612 | mask = (extension & 0xff00) >> 8; | |
2613 | ||
707641f6 JL |
2614 | if (mask & 0x80) |
2615 | { | |
dbdb5bd8 JL |
2616 | sp -= 4; |
2617 | store_word (sp, State.regs[REG_D0 + 2]); | |
707641f6 JL |
2618 | } |
2619 | ||
2620 | if (mask & 0x40) | |
2621 | { | |
dbdb5bd8 JL |
2622 | sp -= 4; |
2623 | store_word (sp, State.regs[REG_D0 + 3]); | |
707641f6 JL |
2624 | } |
2625 | ||
2626 | if (mask & 0x20) | |
2627 | { | |
dbdb5bd8 JL |
2628 | sp -= 4; |
2629 | store_word (sp, State.regs[REG_A0 + 2]); | |
707641f6 JL |
2630 | } |
2631 | ||
2632 | if (mask & 0x10) | |
2633 | { | |
dbdb5bd8 JL |
2634 | sp -= 4; |
2635 | store_word (sp, State.regs[REG_A0 + 3]); | |
707641f6 JL |
2636 | } |
2637 | ||
2638 | if (mask & 0x8) | |
2639 | { | |
dbdb5bd8 JL |
2640 | sp -= 4; |
2641 | store_word (sp, State.regs[REG_D0]); | |
2642 | sp -= 4; | |
2643 | store_word (sp, State.regs[REG_D0 + 1]); | |
2644 | sp -= 4; | |
2645 | store_word (sp, State.regs[REG_A0]); | |
2646 | sp -= 4; | |
2647 | store_word (sp, State.regs[REG_A0 + 1]); | |
2648 | sp -= 4; | |
2649 | store_word (sp, State.regs[REG_MDR]); | |
2650 | sp -= 4; | |
2651 | store_word (sp, State.regs[REG_LIR]); | |
2652 | sp -= 4; | |
2653 | store_word (sp, State.regs[REG_LAR]); | |
2654 | sp -= 4; | |
707641f6 JL |
2655 | } |
2656 | ||
fc615b0b JL |
2657 | /* Update the stack pointer, note that the register saves to do not |
2658 | modify SP. The SP adjustment is derived totally from the imm8 | |
2659 | field. */ | |
2660 | State.regs[REG_SP] -= (extension & 0xff); | |
707641f6 | 2661 | State.regs[REG_MDR] = next_pc; |
b774c0e4 | 2662 | State.regs[REG_PC] += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7; |
05ccbdfd JL |
2663 | } |
2664 | ||
707641f6 | 2665 | /* calls (an) */ |
d2523010 JL |
2666 | void OP_F0F0 (insn, extension) |
2667 | unsigned long insn, extension; | |
05ccbdfd | 2668 | { |
92284aaa JL |
2669 | unsigned int next_pc, sp; |
2670 | ||
2671 | sp = State.regs[REG_SP]; | |
b774c0e4 | 2672 | next_pc = State.regs[REG_PC] + 2; |
92284aaa | 2673 | State.mem[sp] = next_pc & 0xff; |
3bb3fe44 JL |
2674 | State.mem[sp+1] = (next_pc & 0xff00) >> 8; |
2675 | State.mem[sp+2] = (next_pc & 0xff0000) >> 16; | |
2676 | State.mem[sp+3] = (next_pc & 0xff000000) >> 24; | |
92284aaa | 2677 | State.regs[REG_MDR] = next_pc; |
b774c0e4 | 2678 | State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2; |
05ccbdfd JL |
2679 | } |
2680 | ||
707641f6 | 2681 | /* calls label:16 */ |
d2523010 JL |
2682 | void OP_FAFF0000 (insn, extension) |
2683 | unsigned long insn, extension; | |
05ccbdfd | 2684 | { |
92284aaa JL |
2685 | unsigned int next_pc, sp; |
2686 | ||
2687 | sp = State.regs[REG_SP]; | |
b774c0e4 | 2688 | next_pc = State.regs[REG_PC] + 4; |
92284aaa | 2689 | State.mem[sp] = next_pc & 0xff; |
3bb3fe44 JL |
2690 | State.mem[sp+1] = (next_pc & 0xff00) >> 8; |
2691 | State.mem[sp+2] = (next_pc & 0xff0000) >> 16; | |
2692 | State.mem[sp+3] = (next_pc & 0xff000000) >> 24; | |
92284aaa | 2693 | State.regs[REG_MDR] = next_pc; |
b774c0e4 | 2694 | State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 4; |
05ccbdfd JL |
2695 | } |
2696 | ||
707641f6 | 2697 | /* calls label:32 */ |
d2523010 JL |
2698 | void OP_FCFF0000 (insn, extension) |
2699 | unsigned long insn, extension; | |
05ccbdfd | 2700 | { |
92284aaa JL |
2701 | unsigned int next_pc, sp; |
2702 | ||
2703 | sp = State.regs[REG_SP]; | |
b774c0e4 | 2704 | next_pc = State.regs[REG_PC] + 6; |
92284aaa | 2705 | State.mem[sp] = next_pc & 0xff; |
3bb3fe44 JL |
2706 | State.mem[sp+1] = (next_pc & 0xff00) >> 8; |
2707 | State.mem[sp+2] = (next_pc & 0xff0000) >> 16; | |
2708 | State.mem[sp+3] = (next_pc & 0xff000000) >> 24; | |
92284aaa | 2709 | State.regs[REG_MDR] = next_pc; |
b774c0e4 | 2710 | State.regs[REG_PC] += (((insn & 0xffff) << 16) + extension) - 6; |
05ccbdfd JL |
2711 | } |
2712 | ||
de0dce7c | 2713 | /* ret reg_list, imm8 */ |
d2523010 JL |
2714 | void OP_DF0000 (insn, extension) |
2715 | unsigned long insn, extension; | |
05ccbdfd | 2716 | { |
f4ab2b2f | 2717 | unsigned int sp, offset; |
707641f6 JL |
2718 | unsigned long mask; |
2719 | ||
2720 | State.regs[REG_SP] += insn & 0xff; | |
707641f6 JL |
2721 | sp = State.regs[REG_SP]; |
2722 | ||
f4ab2b2f | 2723 | offset = -4; |
707641f6 JL |
2724 | mask = (insn & 0xff00) >> 8; |
2725 | ||
f4ab2b2f | 2726 | if (mask & 0x80) |
707641f6 | 2727 | { |
f4ab2b2f JL |
2728 | State.regs[REG_D0 + 2] = load_word (sp + offset); |
2729 | offset -= 4; | |
707641f6 JL |
2730 | } |
2731 | ||
f4ab2b2f | 2732 | if (mask & 0x40) |
707641f6 | 2733 | { |
f4ab2b2f JL |
2734 | State.regs[REG_D0 + 3] = load_word (sp + offset); |
2735 | offset -= 4; | |
707641f6 JL |
2736 | } |
2737 | ||
2738 | if (mask & 0x20) | |
2739 | { | |
f4ab2b2f JL |
2740 | State.regs[REG_A0 + 2] = load_word (sp + offset); |
2741 | offset -= 4; | |
707641f6 JL |
2742 | } |
2743 | ||
f4ab2b2f | 2744 | if (mask & 0x10) |
707641f6 | 2745 | { |
f4ab2b2f JL |
2746 | State.regs[REG_A0 + 3] = load_word (sp + offset); |
2747 | offset -= 4; | |
707641f6 JL |
2748 | } |
2749 | ||
f4ab2b2f | 2750 | if (mask & 0x8) |
707641f6 | 2751 | { |
f4ab2b2f JL |
2752 | State.regs[REG_D0] = load_word (sp + offset); |
2753 | offset -= 4; | |
2754 | State.regs[REG_D0 + 1] = load_word (sp + offset); | |
2755 | offset -= 4; | |
2756 | State.regs[REG_A0] = load_word (sp + offset); | |
2757 | offset -= 4; | |
2758 | State.regs[REG_A0 + 1] = load_word (sp + offset); | |
2759 | offset -= 4; | |
2760 | State.regs[REG_MDR] = load_word (sp + offset); | |
2761 | offset -= 4; | |
2762 | State.regs[REG_LIR] = load_word (sp + offset); | |
2763 | offset -= 4; | |
2764 | State.regs[REG_LAR] = load_word (sp + offset); | |
2765 | offset -= 4; | |
707641f6 | 2766 | } |
16d2e2b6 | 2767 | |
16d2e2b6 | 2768 | /* Restore the PC value. */ |
b774c0e4 | 2769 | State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8) |
16d2e2b6 | 2770 | | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24)); |
b774c0e4 | 2771 | State.regs[REG_PC] -= 3; |
05ccbdfd JL |
2772 | } |
2773 | ||
707641f6 | 2774 | /* retf reg_list,imm8 */ |
d2523010 JL |
2775 | void OP_DE0000 (insn, extension) |
2776 | unsigned long insn, extension; | |
05ccbdfd | 2777 | { |
f4ab2b2f | 2778 | unsigned int sp, offset; |
707641f6 JL |
2779 | unsigned long mask; |
2780 | ||
f4ab2b2f | 2781 | State.regs[REG_SP] += (insn & 0xff); |
707641f6 | 2782 | sp = State.regs[REG_SP]; |
f4ab2b2f | 2783 | State.regs[REG_PC] = State.regs[REG_MDR] - 3; |
707641f6 | 2784 | |
f4ab2b2f | 2785 | offset = -4; |
707641f6 JL |
2786 | mask = (insn & 0xff00) >> 8; |
2787 | ||
f4ab2b2f | 2788 | if (mask & 0x80) |
707641f6 | 2789 | { |
f4ab2b2f JL |
2790 | State.regs[REG_D0 + 2] = load_word (sp + offset); |
2791 | offset -= 4; | |
707641f6 JL |
2792 | } |
2793 | ||
f4ab2b2f | 2794 | if (mask & 0x40) |
707641f6 | 2795 | { |
f4ab2b2f JL |
2796 | State.regs[REG_D0 + 3] = load_word (sp + offset); |
2797 | offset -= 4; | |
707641f6 JL |
2798 | } |
2799 | ||
2800 | if (mask & 0x20) | |
2801 | { | |
f4ab2b2f JL |
2802 | State.regs[REG_A0 + 2] = load_word (sp + offset); |
2803 | offset -= 4; | |
707641f6 JL |
2804 | } |
2805 | ||
f4ab2b2f | 2806 | if (mask & 0x10) |
707641f6 | 2807 | { |
f4ab2b2f JL |
2808 | State.regs[REG_A0 + 3] = load_word (sp + offset); |
2809 | offset -= 4; | |
707641f6 JL |
2810 | } |
2811 | ||
f4ab2b2f | 2812 | if (mask & 0x8) |
707641f6 | 2813 | { |
f4ab2b2f JL |
2814 | State.regs[REG_D0] = load_word (sp + offset); |
2815 | offset -= 4; | |
2816 | State.regs[REG_D0 + 1] = load_word (sp + offset); | |
2817 | offset -= 4; | |
2818 | State.regs[REG_A0] = load_word (sp + offset); | |
2819 | offset -= 4; | |
2820 | State.regs[REG_A0 + 1] = load_word (sp + offset); | |
2821 | offset -= 4; | |
2822 | State.regs[REG_MDR] = load_word (sp + offset); | |
2823 | offset -= 4; | |
2824 | State.regs[REG_LIR] = load_word (sp + offset); | |
2825 | offset -= 4; | |
2826 | State.regs[REG_LAR] = load_word (sp + offset); | |
2827 | offset -= 4; | |
707641f6 | 2828 | } |
05ccbdfd JL |
2829 | } |
2830 | ||
2831 | /* rets */ | |
d2523010 JL |
2832 | void OP_F0FC (insn, extension) |
2833 | unsigned long insn, extension; | |
05ccbdfd | 2834 | { |
92284aaa JL |
2835 | unsigned int sp; |
2836 | ||
2837 | sp = State.regs[REG_SP]; | |
b774c0e4 | 2838 | State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8) |
92284aaa | 2839 | | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24)); |
b774c0e4 | 2840 | State.regs[REG_PC] -= 2; |
05ccbdfd JL |
2841 | } |
2842 | ||
2843 | /* rti */ | |
d2523010 JL |
2844 | void OP_F0FD (insn, extension) |
2845 | unsigned long insn, extension; | |
05ccbdfd | 2846 | { |
65b784d8 JL |
2847 | unsigned int sp, next_pc; |
2848 | ||
52ef605e | 2849 | sp = State.regs[REG_SP]; |
65b784d8 JL |
2850 | PSW = State.mem[sp] | (State.mem[sp + 1] << 8); |
2851 | State.regs[REG_PC] = (State.mem[sp+4] | (State.mem[sp+5] << 8) | |
2852 | | (State.mem[sp+6] << 16) | (State.mem[sp+7] << 24)); | |
2853 | State.regs[REG_SP] += 8; | |
05ccbdfd JL |
2854 | } |
2855 | ||
2856 | /* trap */ | |
d2523010 JL |
2857 | void OP_F0FE (insn, extension) |
2858 | unsigned long insn, extension; | |
0915c843 | 2859 | { |
65b784d8 JL |
2860 | unsigned int sp, next_pc; |
2861 | ||
2862 | sp = State.regs[REG_SP]; | |
2863 | next_pc = State.regs[REG_PC] + 2; | |
2864 | State.mem[sp] = next_pc & 0xff; | |
2865 | State.mem[sp+1] = (next_pc & 0xff00) >> 8; | |
2866 | State.mem[sp+2] = (next_pc & 0xff0000) >> 16; | |
2867 | State.mem[sp+3] = (next_pc & 0xff000000) >> 24; | |
2868 | State.regs[REG_PC] = 0x40000010 - 2; | |
0915c843 JL |
2869 | } |
2870 | ||
2871 | /* syscall */ | |
7c8a2969 | 2872 | void OP_F0C0 (insn, extension) |
0915c843 | 2873 | unsigned long insn, extension; |
05ccbdfd | 2874 | { |
3bb3fe44 JL |
2875 | /* We use this for simulated system calls; we may need to change |
2876 | it to a reserved instruction if we conflict with uses at | |
2877 | Matsushita. */ | |
2878 | int save_errno = errno; | |
2879 | errno = 0; | |
2880 | ||
2881 | /* Registers passed to trap 0 */ | |
2882 | ||
2883 | /* Function number. */ | |
81f13ed1 | 2884 | #define FUNC (State.regs[0]) |
3bb3fe44 JL |
2885 | |
2886 | /* Parameters. */ | |
81f13ed1 | 2887 | #define PARM1 (State.regs[1]) |
003c91be JL |
2888 | #define PARM2 (load_word (State.regs[REG_SP] + 12)) |
2889 | #define PARM3 (load_word (State.regs[REG_SP] + 16)) | |
3bb3fe44 JL |
2890 | |
2891 | /* Registers set by trap 0 */ | |
2892 | ||
2893 | #define RETVAL State.regs[0] /* return value */ | |
2894 | #define RETERR State.regs[1] /* return error code */ | |
2895 | ||
2896 | /* Turn a pointer in a register into a pointer into real memory. */ | |
2897 | ||
2898 | #define MEMPTR(x) (State.mem + x) | |
2899 | ||
2900 | switch (FUNC) | |
2901 | { | |
2902 | #if !defined(__GO32__) && !defined(_WIN32) | |
a9faef12 MA |
2903 | #ifdef TARGET_SYS_fork |
2904 | case TARGET_SYS_fork: | |
3bb3fe44 JL |
2905 | RETVAL = fork (); |
2906 | break; | |
a9faef12 MA |
2907 | #endif |
2908 | #ifdef TARGET_SYS_execve | |
2909 | case TARGET_SYS_execve: | |
3bb3fe44 JL |
2910 | RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), |
2911 | (char **)MEMPTR (PARM3)); | |
2912 | break; | |
a9faef12 MA |
2913 | #endif |
2914 | #ifdef TARGET_SYS_execv | |
2915 | case TARGET_SYS_execv: | |
3bb3fe44 JL |
2916 | RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL); |
2917 | break; | |
87e43259 | 2918 | #endif |
a9faef12 | 2919 | #endif /* ! GO32 and ! WIN32 */ |
3bb3fe44 | 2920 | |
a9faef12 | 2921 | case TARGET_SYS_read: |
3bb3fe44 JL |
2922 | RETVAL = mn10300_callback->read (mn10300_callback, PARM1, |
2923 | MEMPTR (PARM2), PARM3); | |
2924 | break; | |
a9faef12 | 2925 | case TARGET_SYS_write: |
4df7aeb3 JL |
2926 | RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1, |
2927 | MEMPTR (PARM2), PARM3); | |
3bb3fe44 | 2928 | break; |
a9faef12 | 2929 | case TARGET_SYS_lseek: |
3bb3fe44 JL |
2930 | RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3); |
2931 | break; | |
a9faef12 | 2932 | case TARGET_SYS_close: |
3bb3fe44 JL |
2933 | RETVAL = mn10300_callback->close (mn10300_callback, PARM1); |
2934 | break; | |
a9faef12 | 2935 | case TARGET_SYS_open: |
3bb3fe44 JL |
2936 | RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2); |
2937 | break; | |
a9faef12 | 2938 | case TARGET_SYS_exit: |
3bb3fe44 JL |
2939 | /* EXIT - caller can look in PARM1 to work out the |
2940 | reason */ | |
003c91be | 2941 | if (PARM1 == 0xdead) |
3bb3fe44 JL |
2942 | State.exception = SIGABRT; |
2943 | else | |
2944 | State.exception = SIGQUIT; | |
d05b86b7 | 2945 | State.exited = 1; |
3bb3fe44 JL |
2946 | break; |
2947 | ||
a9faef12 | 2948 | case TARGET_SYS_stat: /* added at hmsi */ |
3bb3fe44 JL |
2949 | /* stat system call */ |
2950 | { | |
2951 | struct stat host_stat; | |
2952 | reg_t buf; | |
2953 | ||
2954 | RETVAL = stat (MEMPTR (PARM1), &host_stat); | |
2955 | ||
2956 | buf = PARM2; | |
2957 | ||
2958 | /* Just wild-assed guesses. */ | |
003c91be JL |
2959 | store_half (buf, host_stat.st_dev); |
2960 | store_half (buf + 2, host_stat.st_ino); | |
2961 | store_word (buf + 4, host_stat.st_mode); | |
2962 | store_half (buf + 8, host_stat.st_nlink); | |
2963 | store_half (buf + 10, host_stat.st_uid); | |
2964 | store_half (buf + 12, host_stat.st_gid); | |
2965 | store_half (buf + 14, host_stat.st_rdev); | |
2966 | store_word (buf + 16, host_stat.st_size); | |
2967 | store_word (buf + 20, host_stat.st_atime); | |
2968 | store_word (buf + 28, host_stat.st_mtime); | |
2969 | store_word (buf + 36, host_stat.st_ctime); | |
3bb3fe44 JL |
2970 | } |
2971 | break; | |
2972 | ||
a9faef12 MA |
2973 | #ifdef TARGET_SYS_chown |
2974 | case TARGET_SYS_chown: | |
3bb3fe44 JL |
2975 | RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3); |
2976 | break; | |
a9faef12 MA |
2977 | #endif |
2978 | case TARGET_SYS_chmod: | |
3bb3fe44 JL |
2979 | RETVAL = chmod (MEMPTR (PARM1), PARM2); |
2980 | break; | |
a9faef12 MA |
2981 | #ifdef TARGET_SYS_time |
2982 | case TARGET_SYS_time: | |
87e43259 | 2983 | RETVAL = time ((void*) MEMPTR (PARM1)); |
3bb3fe44 | 2984 | break; |
87e43259 | 2985 | #endif |
a9faef12 MA |
2986 | #ifdef TARGET_SYS_times |
2987 | case TARGET_SYS_times: | |
3bb3fe44 JL |
2988 | { |
2989 | struct tms tms; | |
2990 | RETVAL = times (&tms); | |
003c91be JL |
2991 | store_word (PARM1, tms.tms_utime); |
2992 | store_word (PARM1 + 4, tms.tms_stime); | |
2993 | store_word (PARM1 + 8, tms.tms_cutime); | |
2994 | store_word (PARM1 + 12, tms.tms_cstime); | |
3bb3fe44 JL |
2995 | break; |
2996 | } | |
87e43259 | 2997 | #endif |
a9faef12 MA |
2998 | #ifdef TARGET_SYS_gettimeofday |
2999 | case TARGET_SYS_gettimeofday: | |
3bb3fe44 JL |
3000 | { |
3001 | struct timeval t; | |
3002 | struct timezone tz; | |
3003 | RETVAL = gettimeofday (&t, &tz); | |
003c91be JL |
3004 | store_word (PARM1, t.tv_sec); |
3005 | store_word (PARM1 + 4, t.tv_usec); | |
3006 | store_word (PARM2, tz.tz_minuteswest); | |
3007 | store_word (PARM2 + 4, tz.tz_dsttime); | |
3bb3fe44 JL |
3008 | break; |
3009 | } | |
a9faef12 MA |
3010 | #endif |
3011 | #ifdef TARGET_SYS_utime | |
3012 | case TARGET_SYS_utime: | |
3bb3fe44 JL |
3013 | /* Cast the second argument to void *, to avoid type mismatch |
3014 | if a prototype is present. */ | |
3015 | RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)); | |
3016 | break; | |
87e43259 | 3017 | #endif |
3bb3fe44 JL |
3018 | default: |
3019 | abort (); | |
3020 | } | |
3021 | RETERR = errno; | |
3022 | errno = save_errno; | |
05ccbdfd JL |
3023 | } |
3024 | ||
3025 | /* rtm */ | |
d2523010 JL |
3026 | void OP_F0FF (insn, extension) |
3027 | unsigned long insn, extension; | |
05ccbdfd | 3028 | { |
f5f13c1d | 3029 | abort (); |
05ccbdfd JL |
3030 | } |
3031 | ||
3032 | /* nop */ | |
d2523010 JL |
3033 | void OP_CB (insn, extension) |
3034 | unsigned long insn, extension; | |
05ccbdfd JL |
3035 | { |
3036 | } | |
3037 | ||
26e9f63c | 3038 | /* putx dm,dm */ |
d2523010 JL |
3039 | void OP_F500 (insn, extension) |
3040 | unsigned long insn, extension; | |
05ccbdfd | 3041 | { |
26e9f63c | 3042 | State.regs[REG_MDRQ] = State.regs[REG_D0 + REG0 (insn)]; |
05ccbdfd JL |
3043 | } |
3044 | ||
26e9f63c | 3045 | /* getx dm,dm */ |
d2523010 JL |
3046 | void OP_F6F0 (insn, extension) |
3047 | unsigned long insn, extension; | |
05ccbdfd | 3048 | { |
26e9f63c JL |
3049 | int z, n; |
3050 | z = (State.regs[REG_MDRQ] == 0); | |
3051 | n = ((State.regs[REG_MDRQ] & 0x80000000) != 0); | |
3052 | State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDRQ]; | |
3053 | ||
3054 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3055 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
05ccbdfd JL |
3056 | } |
3057 | ||
26e9f63c | 3058 | /* mulq dm,dn */ |
d2523010 JL |
3059 | void OP_F600 (insn, extension) |
3060 | unsigned long insn, extension; | |
05ccbdfd | 3061 | { |
26e9f63c JL |
3062 | unsigned long long temp; |
3063 | int n, z; | |
3064 | ||
097e6924 JL |
3065 | temp = ((signed64)(signed32)State.regs[REG_D0 + REG0 (insn)] |
3066 | * (signed64)(signed32)State.regs[REG_D0 + REG1 (insn)]); | |
26e9f63c JL |
3067 | State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; |
3068 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3069 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
3070 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
3071 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3072 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3073 | } |
3074 | ||
26e9f63c | 3075 | /* mulq imm8,dn */ |
d2523010 JL |
3076 | void OP_F90000 (insn, extension) |
3077 | unsigned long insn, extension; | |
05ccbdfd | 3078 | { |
26e9f63c JL |
3079 | unsigned long long temp; |
3080 | int n, z; | |
3081 | ||
097e6924 JL |
3082 | temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_8 (insn)] |
3083 | * (signed64)(signed32)SEXT8 (insn & 0xff)); | |
26e9f63c JL |
3084 | State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff; |
3085 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3086 | z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); | |
3087 | n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; | |
3088 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3089 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3090 | } |
3091 | ||
26e9f63c | 3092 | /* mulq imm16,dn */ |
d2523010 JL |
3093 | void OP_FB000000 (insn, extension) |
3094 | unsigned long insn, extension; | |
05ccbdfd | 3095 | { |
26e9f63c JL |
3096 | unsigned long long temp; |
3097 | int n, z; | |
3098 | ||
097e6924 JL |
3099 | temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_16 (insn)] |
3100 | * (signed64)(signed32)SEXT16 (insn & 0xffff)); | |
26e9f63c JL |
3101 | State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff; |
3102 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3103 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); | |
3104 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
3105 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3106 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3107 | } |
3108 | ||
26e9f63c | 3109 | /* mulq imm32,dn */ |
d2523010 JL |
3110 | void OP_FD000000 (insn, extension) |
3111 | unsigned long insn, extension; | |
05ccbdfd | 3112 | { |
26e9f63c JL |
3113 | unsigned long long temp; |
3114 | int n, z; | |
3115 | ||
097e6924 JL |
3116 | temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_16 (insn)] |
3117 | * (signed64)(signed32)(((insn & 0xffff) << 16) + extension)); | |
26e9f63c JL |
3118 | State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff; |
3119 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3120 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); | |
3121 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
3122 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3123 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3124 | } |
3125 | ||
26e9f63c | 3126 | /* mulqu dm,dn */ |
d2523010 JL |
3127 | void OP_F610 (insn, extension) |
3128 | unsigned long insn, extension; | |
05ccbdfd | 3129 | { |
26e9f63c JL |
3130 | unsigned long long temp; |
3131 | int n, z; | |
3132 | ||
0983e650 JL |
3133 | temp = ((unsigned64) State.regs[REG_D0 + REG0 (insn)] |
3134 | * (unsigned64) State.regs[REG_D0 + REG1 (insn)]); | |
26e9f63c JL |
3135 | State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; |
3136 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3137 | z = (State.regs[REG_D0 + REG0 (insn)] == 0); | |
3138 | n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; | |
3139 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3140 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3141 | } |
3142 | ||
26e9f63c | 3143 | /* mulqu imm8,dn */ |
d2523010 JL |
3144 | void OP_F91400 (insn, extension) |
3145 | unsigned long insn, extension; | |
05ccbdfd | 3146 | { |
26e9f63c JL |
3147 | unsigned long long temp; |
3148 | int n, z; | |
3149 | ||
0983e650 JL |
3150 | temp = ((unsigned64)State.regs[REG_D0 + REG0_8 (insn)] |
3151 | * (unsigned64)SEXT8 (insn & 0xff)); | |
26e9f63c JL |
3152 | State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff; |
3153 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3154 | z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); | |
3155 | n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; | |
3156 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3157 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3158 | } |
3159 | ||
26e9f63c | 3160 | /* mulqu imm16,dn */ |
d2523010 JL |
3161 | void OP_FB140000 (insn, extension) |
3162 | unsigned long insn, extension; | |
05ccbdfd | 3163 | { |
26e9f63c JL |
3164 | unsigned long long temp; |
3165 | int n, z; | |
3166 | ||
0983e650 JL |
3167 | temp = ((unsigned64)State.regs[REG_D0 + REG0_16 (insn)] |
3168 | * (unsigned64) SEXT16 (insn & 0xffff)); | |
26e9f63c JL |
3169 | State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff; |
3170 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3171 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); | |
3172 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
3173 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3174 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3175 | } |
3176 | ||
26e9f63c | 3177 | /* mulqu imm32,dn */ |
d2523010 JL |
3178 | void OP_FD140000 (insn, extension) |
3179 | unsigned long insn, extension; | |
05ccbdfd | 3180 | { |
26e9f63c JL |
3181 | unsigned long long temp; |
3182 | int n, z; | |
3183 | ||
0983e650 JL |
3184 | temp = ((unsigned64)State.regs[REG_D0 + REG0_16 (insn)] |
3185 | * (unsigned64)(((insn & 0xffff) << 16) + extension)); | |
26e9f63c JL |
3186 | State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff; |
3187 | State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; | |
3188 | z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); | |
3189 | n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; | |
3190 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
3191 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
05ccbdfd JL |
3192 | } |
3193 | ||
26e9f63c | 3194 | /* sat16 dm,dn */ |
d2523010 JL |
3195 | void OP_F640 (insn, extension) |
3196 | unsigned long insn, extension; | |
05ccbdfd | 3197 | { |
26e9f63c JL |
3198 | int temp; |
3199 | ||
3200 | temp = State.regs[REG_D0 + REG1 (insn)]; | |
3201 | temp = (temp > 0x7fff ? 0x7fff : temp); | |
3202 | temp = (temp < -0x8000 ? -0x8000 : temp); | |
3203 | State.regs[REG_D0 + REG0 (insn)] = temp; | |
05ccbdfd JL |
3204 | } |
3205 | ||
26e9f63c | 3206 | /* sat24 dm,dn */ |
d2523010 JL |
3207 | void OP_F650 (insn, extension) |
3208 | unsigned long insn, extension; | |
05ccbdfd | 3209 | { |
26e9f63c JL |
3210 | int temp; |
3211 | ||
3212 | temp = State.regs[REG_D0 + REG1 (insn)]; | |
3213 | temp = (temp > 0x7fffff ? 0x7fffff : temp); | |
3214 | temp = (temp < -0x800000 ? -0x800000 : temp); | |
3215 | State.regs[REG_D0 + REG0 (insn)] = temp; | |
05ccbdfd JL |
3216 | } |
3217 | ||
26e9f63c | 3218 | /* bsch dm,dn */ |
d2523010 JL |
3219 | void OP_F670 (insn, extension) |
3220 | unsigned long insn, extension; | |
05ccbdfd | 3221 | { |
26e9f63c JL |
3222 | int temp, c; |
3223 | ||
3224 | temp = State.regs[REG_D0 + REG1 (insn)]; | |
3225 | temp <<= (State.regs[REG_D0 + REG0 (insn)] & 0x1f); | |
3226 | c = (temp != 0 ? 1 : 0); | |
3227 | PSW &= ~(PSW_C); | |
3228 | PSW |= (c ? PSW_C : 0); | |
05ccbdfd | 3229 | } |
093e9a32 JL |
3230 | |
3231 | /* breakpoint */ | |
3232 | void | |
3233 | OP_FF (insn, extension) | |
3234 | unsigned long insn, extension; | |
3235 | { | |
3236 | State.exception = SIGTRAP; | |
3237 | PC -= 1; | |
3238 | } | |
3239 |