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* simops.c (REG0_16): Fix typo.
[deliverable/binutils-gdb.git] / sim / mn10300 / simops.c
CommitLineData
05ccbdfd
JL		 1#include "config.h"
2
3#include <signal.h>
4#ifdef HAVE_UNISTD_H
5#include <unistd.h>
6#endif
7#include "mn10300_sim.h"
8#include "simops.h"
9#include "sys/syscall.h"
10#include "bfd.h"
11#include <errno.h>
12#include <sys/stat.h>
13#include <sys/times.h>
14#include <sys/time.h>
15
9f4a551e
JL		 16#define REG0(X) ((X) & 0x3)
17#define REG1(X) (((X) & 0xc) >> 2)
18#define REG0_8(X) (((X) & 0x300) >> 8)
19#define REG1_8(X) (((X) & 0xc00) >> 10)
2e8f4133 20#define REG0_16(X) (((X) & 0x30000) >> 16)
9f4a551e 21#define REG1_16(X) (((X) & 0xc0000) >> 18)
05ccbdfd 22\f
707641f6 23/* mov imm8, dn */
d2523010
JL		 24void OP_8000 (insn, extension)
25 unsigned long insn, extension;
05ccbdfd 26{
9f4a551e 27 State.regs[REG_D0 + REG0_8 (insn)] = SEXT8 (insn & 0xff);
05ccbdfd
JL		 28}
29
707641f6 30/* mov dm, dn */
d2523010
JL		 31void OP_80 (insn, extension)
32 unsigned long insn, extension;
05ccbdfd 33{
9f4a551e 34 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
05ccbdfd
JL		 35}
36
707641f6 37/* mov dm, an */
d2523010
JL		 38void OP_F1E0 (insn, extension)
39 unsigned long insn, extension;
05ccbdfd 40{
9f4a551e 41 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
05ccbdfd
JL		 42}
43
707641f6 44/* mov am, dn */
d2523010
JL		 45void OP_F1D0 (insn, extension)
46 unsigned long insn, extension;
05ccbdfd 47{
9f4a551e 48 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
05ccbdfd
JL		 49}
50
707641f6 51/* mov imm8, an */
d2523010
JL		 52void OP_9000 (insn, extension)
53 unsigned long insn, extension;
05ccbdfd 54{
9f4a551e 55 State.regs[REG_A0 + REG0_8 (insn)] = insn & 0xff;
05ccbdfd
JL		 56}
57
707641f6 58/* mov am, an */
d2523010
JL		 59void OP_90 (insn, extension)
60 unsigned long insn, extension;
05ccbdfd 61{
9f4a551e 62 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
05ccbdfd
JL		 63}
64
1f3bea21 65/* mov sp, an */
d2523010
JL		 66void OP_3C (insn, extension)
67 unsigned long insn, extension;
05ccbdfd 68{
9f4a551e 69 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_SP];
05ccbdfd
JL		 70}
71
1f3bea21 72/* mov am, sp */
d2523010
JL		 73void OP_F2F0 (insn, extension)
74 unsigned long insn, extension;
05ccbdfd 75{
9f4a551e 76 State.regs[REG_SP] = State.regs[REG_A0 + REG1 (insn)];
05ccbdfd
JL		 77}
78
707641f6 79/* mov psw, dn */
d2523010
JL		 80void OP_F2E4 (insn, extension)
81 unsigned long insn, extension;
05ccbdfd 82{
9f4a551e 83 State.regs[REG_D0 + REG0 (insn)] = PSW;
05ccbdfd
JL		 84}
85
707641f6 86/* mov dm, psw */
d2523010
JL		 87void OP_F2F3 (insn, extension)
88 unsigned long insn, extension;
05ccbdfd 89{
9f4a551e 90 PSW = State.regs[REG_D0 + REG1 (insn)];
05ccbdfd
JL		 91}
92
707641f6 93/* mov mdr, dn */
d2523010
JL		 94void OP_F2E0 (insn, extension)
95 unsigned long insn, extension;
05ccbdfd 96{
9f4a551e 97 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDR];
05ccbdfd
JL		 98}
99
707641f6 100/* mov dm, mdr */
d2523010
JL		 101void OP_F2F2 (insn, extension)
102 unsigned long insn, extension;
05ccbdfd 103{
9f4a551e 104 State.regs[REG_MDR] = State.regs[REG_D0 + REG1 (insn)];
05ccbdfd
JL		 105}
106
2e35551c 107/* mov (am), dn */
d2523010
JL		 108void OP_70 (insn, extension)
109 unsigned long insn, extension;
05ccbdfd 110{
9f4a551e
JL		 111 State.regs[REG_D0 + REG1 (insn)]
112 = load_mem (State.regs[REG_A0 + REG0 (insn)], 4);
05ccbdfd
JL		 113}
114
2e35551c 115/* mov (d8,am), dn */
d2523010
JL		 116void OP_F80000 (insn, extension)
117 unsigned long insn, extension;
05ccbdfd 118{
9f4a551e
JL		 119 State.regs[REG_D0 + REG1_8 (insn)]
120 = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
2e35551c 121 + SEXT8 (insn & 0xff)), 4);
05ccbdfd
JL		 122}
123
ecb4b5a3 124/* mov (d16,am), dn */
d2523010
JL		 125void OP_FA000000 (insn, extension)
126 unsigned long insn, extension;
05ccbdfd 127{
9f4a551e
JL		 128 State.regs[REG_D0 + REG1_16 (insn)]
129 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
ecb4b5a3 130 + SEXT16 (insn & 0xffff)), 4);
05ccbdfd
JL		 131}
132
de0dce7c 133/* mov (d32,am), dn */
d2523010
JL		 134void OP_FC000000 (insn, extension)
135 unsigned long insn, extension;
05ccbdfd 136{
9f4a551e
JL		 137 State.regs[REG_D0 + REG1_16 (insn)]
138 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
7c52bf32 139 + ((insn & 0xffff) << 16) + extension), 4);
05ccbdfd
JL		 140}
141
707641f6 142/* mov (d8,sp), dn */
d2523010
JL		 143void OP_5800 (insn, extension)
144 unsigned long insn, extension;
05ccbdfd 145{
9f4a551e 146 State.regs[REG_D0 + REG0_8 (insn)]
ecb4b5a3 147 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
05ccbdfd
JL		 148}
149
ecb4b5a3 150/* mov (d16,sp), dn */
d2523010
JL		 151void OP_FAB40000 (insn, extension)
152 unsigned long insn, extension;
05ccbdfd 153{
9f4a551e 154 State.regs[REG_D0 + REG0_16 (insn)]
ecb4b5a3 155 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
05ccbdfd
JL		 156}
157
de0dce7c 158/* mov (d32,sp), dn */
d2523010
JL		 159void OP_FCB40000 (insn, extension)
160 unsigned long insn, extension;
05ccbdfd 161{
9f4a551e 162 State.regs[REG_D0 + REG0_16 (insn)]
de0dce7c 163 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
05ccbdfd
JL		 164}
165
f5f13c1d 166/* mov (di,am), dn */
d2523010
JL		 167void OP_F300 (insn, extension)
168 unsigned long insn, extension;
05ccbdfd 169{
9f4a551e
JL		 170 State.regs[REG_D0 + REG0_8 (insn)]
171 = load_mem ((State.regs[REG_A0 + REG0 (insn)]
172 + State.regs[REG_D0 + REG1 (insn)]), 4);
05ccbdfd
JL		 173}
174
707641f6 175/* mov (abs16), dn */
d2523010
JL		 176void OP_300000 (insn, extension)
177 unsigned long insn, extension;
05ccbdfd 178{
9f4a551e 179 State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 4);
05ccbdfd
JL		 180}
181
de0dce7c 182/* mov (abs32), dn */
d2523010
JL		 183void OP_FCA40000 (insn, extension)
184 unsigned long insn, extension;
05ccbdfd 185{
9f4a551e 186 State.regs[REG_D0 + REG0_16 (insn)]
de0dce7c 187 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
05ccbdfd
JL		 188}
189
707641f6 190/* mov (am), an */
d2523010
JL		 191void OP_F000 (insn, extension)
192 unsigned long insn, extension;
05ccbdfd 193{
9f4a551e
JL		 194 State.regs[REG_A0 + REG1 (insn)]
195 = load_mem (State.regs[REG_A0 + REG0 (insn)], 4);
05ccbdfd
JL		 196}
197
2e35551c 198/* mov (d8,am), an */
d2523010
JL		 199void OP_F82000 (insn, extension)
200 unsigned long insn, extension;
05ccbdfd 201{
9f4a551e
JL		 202 State.regs[REG_A0 + REG1_8 (insn)]
203 = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
2e35551c 204 + SEXT8 (insn & 0xff)), 4);
05ccbdfd
JL		 205}
206
ecb4b5a3 207/* mov (d16,am), an */
d2523010
JL		 208void OP_FA200000 (insn, extension)
209 unsigned long insn, extension;
05ccbdfd 210{
9f4a551e
JL		 211 State.regs[REG_A0 + REG1_16 (insn)]
212 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
ecb4b5a3 213 + SEXT16 (insn & 0xffff)), 4);
05ccbdfd
JL		 214}
215
de0dce7c 216/* mov (d32,am), an */
d2523010
JL		 217void OP_FC200000 (insn, extension)
218 unsigned long insn, extension;
05ccbdfd 219{
9f4a551e
JL		 220 State.regs[REG_A0 + REG1_16 (insn)]
221 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
de0dce7c 222 + ((insn & 0xffff) << 16) + extension), 4);
05ccbdfd
JL		 223}
224
707641f6 225/* mov (d8,sp), an */
d2523010
JL		 226void OP_5C00 (insn, extension)
227 unsigned long insn, extension;
05ccbdfd 228{
9f4a551e 229 State.regs[REG_A0 + REG0_8 (insn)]
ecb4b5a3 230 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
05ccbdfd
JL		 231}
232
ecb4b5a3 233/* mov (d16,sp), an */
d2523010
JL		 234void OP_FAB00000 (insn, extension)
235 unsigned long insn, extension;
05ccbdfd 236{
9f4a551e 237 State.regs[REG_A0 + REG0_16 (insn)]
ecb4b5a3 238 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
05ccbdfd
JL		 239}
240
de0dce7c 241/* mov (d32,sp), an */
d2523010
JL		 242void OP_FCB00000 (insn, extension)
243 unsigned long insn, extension;
05ccbdfd 244{
9f4a551e 245 State.regs[REG_A0 + REG0_16 (insn)]
de0dce7c 246 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
05ccbdfd
JL		 247}
248
de0dce7c 249/* mov (di,am), an */
d2523010
JL		 250void OP_F380 (insn, extension)
251 unsigned long insn, extension;
05ccbdfd 252{
9f4a551e
JL		 253 State.regs[REG_A0 + REG0_8 (insn)]
254 = load_mem ((State.regs[REG_A0 + REG0 (insn)]
255 + State.regs[REG_D0 + REG1 (insn)]), 4);
05ccbdfd
JL		 256}
257
ecb4b5a3 258/* mov (abs16), an */
d2523010
JL		 259void OP_FAA00000 (insn, extension)
260 unsigned long insn, extension;
05ccbdfd 261{
9f4a551e 262 State.regs[REG_A0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 4);
05ccbdfd
JL		 263}
264
de0dce7c 265/* mov (abs32), an */
d2523010
JL		 266void OP_FCA00000 (insn, extension)
267 unsigned long insn, extension;
05ccbdfd 268{
9f4a551e 269 State.regs[REG_A0 + REG0_16 (insn)]
de0dce7c 270 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
05ccbdfd
JL		 271}
272
2e35551c 273/* mov (d8,am), sp */
d2523010
JL		 274void OP_F8F000 (insn, extension)
275 unsigned long insn, extension;
05ccbdfd 276{
2e35551c 277 State.regs[REG_SP]
9f4a551e 278 = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
2e35551c 279 + SEXT8 (insn & 0xff)), 4);
05ccbdfd
JL		 280}
281
707641f6 282/* mov dm, (an) */
d2523010
JL		 283void OP_60 (insn, extension)
284 unsigned long insn, extension;
05ccbdfd 285{
9f4a551e
JL		 286 store_mem (State.regs[REG_A0 + REG0 (insn)], 4,
287 State.regs[REG_D0 + REG1 (insn)]);
05ccbdfd
JL		 288}
289
2e35551c 290/* mov dm, (d8,an) */
d2523010
JL		 291void OP_F81000 (insn, extension)
292 unsigned long insn, extension;
05ccbdfd 293{
9f4a551e 294 store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
2e35551c 295 + SEXT8 (insn & 0xff)), 4,
9f4a551e 296 State.regs[REG_D0 + REG1_8 (insn)]);
05ccbdfd
JL		 297}
298
ecb4b5a3 299/* mov dm (d16,an) */
d2523010
JL		 300void OP_FA100000 (insn, extension)
301 unsigned long insn, extension;
05ccbdfd 302{
9f4a551e 303 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
ecb4b5a3 304 + SEXT16 (insn & 0xffff)), 4,
9f4a551e 305 State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 306}
307
de0dce7c 308/* mov dm (d32,an) */
d2523010
JL		 309void OP_FC100000 (insn, extension)
310 unsigned long insn, extension;
05ccbdfd 311{
9f4a551e 312 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
de0dce7c 313 + ((insn & 0xffff) << 16) + extension), 4,
9f4a551e 314 State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 315}
316
707641f6 317/* mov dm, (d8,sp) */
d2523010
JL		 318void OP_4200 (insn, extension)
319 unsigned long insn, extension;
05ccbdfd 320{
ecb4b5a3 321 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
9f4a551e 322 State.regs[REG_D0 + REG1_8 (insn)]);
05ccbdfd
JL		 323}
324
ecb4b5a3 325/* mov dm, (d16,sp) */
d2523010
JL		 326void OP_FA910000 (insn, extension)
327 unsigned long insn, extension;
05ccbdfd 328{
ecb4b5a3 329 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
9f4a551e 330 State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 331}
332
de0dce7c 333/* mov dm, (d32,sp) */
d2523010
JL		 334void OP_FC910000 (insn, extension)
335 unsigned long insn, extension;
05ccbdfd 336{
de0dce7c 337 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
9f4a551e 338 State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 339}
340
f5f13c1d 341/* mov dm, (di,an) */
d2523010
JL		 342void OP_F340 (insn, extension)
343 unsigned long insn, extension;
05ccbdfd 344{
9f4a551e
JL		 345 store_mem ((State.regs[REG_A0 + REG0 (insn)]
346 + State.regs[REG_D0 + REG1 (insn)]), 4,
347 State.regs[REG_D0 + REG0_8 (insn)]);
05ccbdfd
JL		 348}
349
707641f6 350/* mov dm, (abs16) */
d2523010
JL		 351void OP_10000 (insn, extension)
352 unsigned long insn, extension;
05ccbdfd 353{
9f4a551e 354 store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 355}
356
de0dce7c 357/* mov dm, (abs32) */
d2523010
JL		 358void OP_FC810000 (insn, extension)
359 unsigned long insn, extension;
05ccbdfd 360{
9f4a551e 361 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 362}
363
707641f6 364/* mov am, (an) */
d2523010
JL		 365void OP_F010 (insn, extension)
366 unsigned long insn, extension;
05ccbdfd 367{
9f4a551e
JL		 368 store_mem (State.regs[REG_A0 + REG0 (insn)], 4,
369 State.regs[REG_A0 + REG1 (insn)]);
05ccbdfd
JL		 370}
371
2e35551c 372/* mov am, (d8,an) */
d2523010
JL		 373void OP_F83000 (insn, extension)
374 unsigned long insn, extension;
05ccbdfd 375{
9f4a551e 376 store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
2e35551c 377 + SEXT8 (insn & 0xff)), 4,
9f4a551e 378 State.regs[REG_A0 + REG1_8 (insn)]);
05ccbdfd
JL		 379}
380
de0dce7c 381/* mov am, (d16,an) */
d2523010
JL		 382void OP_FA300000 (insn, extension)
383 unsigned long insn, extension;
05ccbdfd 384{
9f4a551e 385 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
ecb4b5a3 386 + SEXT16 (insn & 0xffff)), 4,
9f4a551e 387 State.regs[REG_A0 + REG1_16 (insn)]);
05ccbdfd
JL		 388}
389
de0dce7c 390/* mov am, (d32,an) */
d2523010
JL		 391void OP_FC300000 (insn, extension)
392 unsigned long insn, extension;
05ccbdfd 393{
9f4a551e 394 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
de0dce7c 395 + ((insn & 0xffff) << 16) + extension), 4,
9f4a551e 396 State.regs[REG_A0 + REG1_16 (insn)]);
05ccbdfd
JL		 397}
398
707641f6 399/* mov am, (d8,sp) */
d2523010
JL		 400void OP_4300 (insn, extension)
401 unsigned long insn, extension;
05ccbdfd 402{
ecb4b5a3 403 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
9f4a551e 404 State.regs[REG_A0 + REG1_8 (insn)]);
05ccbdfd
JL		 405}
406
ecb4b5a3 407/* mov am, (d16,sp) */
d2523010
JL		 408void OP_FA900000 (insn, extension)
409 unsigned long insn, extension;
05ccbdfd 410{
ecb4b5a3 411 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
9f4a551e 412 State.regs[REG_A0 + REG1_16 (insn)]);
05ccbdfd
JL		 413}
414
de0dce7c 415/* mov am, (d32,sp) */
d2523010
JL		 416void OP_FC900000 (insn, extension)
417 unsigned long insn, extension;
05ccbdfd 418{
de0dce7c 419 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
9f4a551e 420 State.regs[REG_A0 + REG1_16 (insn)]);
05ccbdfd
JL		 421}
422
f5f13c1d 423/* mov am, (di,an) */
d2523010
JL		 424void OP_F3C0 (insn, extension)
425 unsigned long insn, extension;
05ccbdfd 426{
9f4a551e
JL		 427 store_mem ((State.regs[REG_A0 + REG0 (insn)]
428 + State.regs[REG_D0 + REG1 (insn)]), 4,
429 State.regs[REG_A0 + REG0_8 (insn)]);
05ccbdfd
JL		 430}
431
ecb4b5a3 432/* mov am, (abs16) */
d2523010
JL		 433void OP_FA800000 (insn, extension)
434 unsigned long insn, extension;
05ccbdfd 435{
9f4a551e 436 store_mem ((insn & 0xffff), 4, State.regs[REG_A0 + REG1_16 (insn)]);
05ccbdfd
JL		 437}
438
de0dce7c 439/* mov am, (abs32) */
d2523010
JL		 440void OP_FC800000 (insn, extension)
441 unsigned long insn, extension;
05ccbdfd 442{
9f4a551e 443 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_A0 + REG1_16 (insn)]);
05ccbdfd
JL		 444}
445
2e35551c 446/* mov sp, (d8,an) */
d2523010
JL		 447void OP_F8F400 (insn, extension)
448 unsigned long insn, extension;
05ccbdfd 449{
9f4a551e 450 store_mem (State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff),
2e35551c 451 4, State.regs[REG_SP]);
05ccbdfd
JL		 452}
453
707641f6 454/* mov imm16, dn */
d2523010
JL		 455void OP_2C0000 (insn, extension)
456 unsigned long insn, extension;
05ccbdfd 457{
707641f6
JL		 458 unsigned long value;
459
460 value = SEXT16 (insn & 0xffff);
9f4a551e 461 State.regs[REG_D0 + REG0_16 (insn)] = value;
05ccbdfd
JL		 462}
463
de0dce7c 464/* mov imm32,dn */
d2523010
JL		 465void OP_FCCC0000 (insn, extension)
466 unsigned long insn, extension;
05ccbdfd 467{
de0dce7c
JL		 468 unsigned long value;
469
7c52bf32 470 value = ((insn & 0xffff) << 16) + extension;
9f4a551e 471 State.regs[REG_D0 + REG0_16 (insn)] = value;
05ccbdfd
JL		 472}
473
707641f6 474/* mov imm16, an */
d2523010
JL		 475void OP_240000 (insn, extension)
476 unsigned long insn, extension;
05ccbdfd 477{
707641f6
JL		 478 unsigned long value;
479
480 value = insn & 0xffff;
9f4a551e 481 State.regs[REG_A0 + REG0_16 (insn)] = value;
05ccbdfd
JL		 482}
483
de0dce7c 484/* mov imm32, an */
d2523010
JL		 485void OP_FCDC0000 (insn, extension)
486 unsigned long insn, extension;
05ccbdfd 487{
73e65298
JL		 488 unsigned long value;
489
7c52bf32 490 value = ((insn & 0xffff) << 16) + extension;
9f4a551e 491 State.regs[REG_A0 + REG0_16 (insn)] = value;
05ccbdfd
JL		 492}
493
707641f6 494/* movbu (am), dn */
d2523010
JL		 495void OP_F040 (insn, extension)
496 unsigned long insn, extension;
05ccbdfd 497{
9f4a551e
JL		 498 State.regs[REG_D0 + REG1 (insn)]
499 = load_mem (State.regs[REG_A0 + REG0 (insn)], 1);
05ccbdfd
JL		 500}
501
2e35551c 502/* movbu (d8,am), dn */
d2523010
JL		 503void OP_F84000 (insn, extension)
504 unsigned long insn, extension;
05ccbdfd 505{
9f4a551e
JL		 506 State.regs[REG_D0 + REG1_8 (insn)]
507 = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
2e35551c 508 + SEXT8 (insn & 0xff)), 1);
05ccbdfd
JL		 509}
510
ecb4b5a3 511/* movbu (d16,am), dn */
d2523010
JL		 512void OP_FA400000 (insn, extension)
513 unsigned long insn, extension;
05ccbdfd 514{
9f4a551e
JL		 515 State.regs[REG_D0 + REG1_16 (insn)]
516 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
ecb4b5a3 517 + SEXT16 (insn & 0xffff)), 1);
05ccbdfd
JL		 518}
519
de0dce7c 520/* movbu (d32,am), dn */
d2523010
JL		 521void OP_FC400000 (insn, extension)
522 unsigned long insn, extension;
05ccbdfd 523{
9f4a551e
JL		 524 State.regs[REG_D0 + REG1_16 (insn)]
525 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
de0dce7c 526 + ((insn & 0xffff) << 16) + extension), 1);
05ccbdfd
JL		 527}
528
2e35551c 529/* movbu (d8,sp), dn */
d2523010
JL		 530void OP_F8B800 (insn, extension)
531 unsigned long insn, extension;
05ccbdfd 532{
9f4a551e 533 State.regs[REG_D0 + REG0_8 (insn)]
ecb4b5a3 534 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 1);
05ccbdfd
JL		 535}
536
ecb4b5a3 537/* movbu (d16,sp), dn */
d2523010
JL		 538void OP_FAB80000 (insn, extension)
539 unsigned long insn, extension;
05ccbdfd 540{
9f4a551e 541 State.regs[REG_D0 + REG0_16 (insn)]
ecb4b5a3 542 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 1);
05ccbdfd
JL		 543}
544
de0dce7c 545/* movbu (d32,sp), dn */
d2523010
JL		 546void OP_FCB80000 (insn, extension)
547 unsigned long insn, extension;
05ccbdfd 548{
9f4a551e 549 State.regs[REG_D0 + REG0_16 (insn)]
de0dce7c 550 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 1);
05ccbdfd
JL		 551}
552
f5f13c1d 553/* movbu (di,am), dn */
d2523010
JL		 554void OP_F400 (insn, extension)
555 unsigned long insn, extension;
05ccbdfd 556{
9f4a551e
JL		 557 State.regs[REG_D0 + REG0_8 (insn)]
558 = load_mem ((State.regs[REG_A0 + REG0 (insn)]
559 + State.regs[REG_D0 + REG1 (insn)]), 1);
05ccbdfd
JL		 560}
561
707641f6 562/* movbu (abs16), dn */
d2523010
JL		 563void OP_340000 (insn, extension)
564 unsigned long insn, extension;
05ccbdfd 565{
9f4a551e 566 State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 1);
05ccbdfd
JL		 567}
568
de0dce7c 569/* movbu (abs32), dn */
d2523010
JL		 570void OP_FCA80000 (insn, extension)
571 unsigned long insn, extension;
05ccbdfd 572{
9f4a551e 573 State.regs[REG_D0 + REG0_16 (insn)]
de0dce7c 574 = load_mem ((((insn & 0xffff) << 16) + extension), 1);
05ccbdfd
JL		 575}
576
707641f6 577/* movbu dm, (an) */
d2523010
JL		 578void OP_F050 (insn, extension)
579 unsigned long insn, extension;
05ccbdfd 580{
9f4a551e
JL		 581 store_mem (State.regs[REG_A0 + REG0 (insn)], 1,
582 State.regs[REG_D0 + REG1 (insn)]);
05ccbdfd
JL		 583}
584
2e35551c 585/* movbu dm, (d8,an) */
d2523010
JL		 586void OP_F85000 (insn, extension)
587 unsigned long insn, extension;
05ccbdfd 588{
9f4a551e 589 store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
2e35551c 590 + SEXT8 (insn & 0xff)), 1,
9f4a551e 591 State.regs[REG_D0 + REG1_8 (insn)]);
05ccbdfd
JL		 592}
593
ecb4b5a3 594/* movbu dm, (d16,an) */
d2523010
JL		 595void OP_FA500000 (insn, extension)
596 unsigned long insn, extension;
05ccbdfd 597{
9f4a551e 598 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
de0dce7c 599 + SEXT16 (insn & 0xffff)), 1,
9f4a551e 600 State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 601}
602
de0dce7c 603/* movbu dm, (d32,an) */
d2523010
JL		 604void OP_FC500000 (insn, extension)
605 unsigned long insn, extension;
05ccbdfd 606{
9f4a551e 607 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
de0dce7c 608 + ((insn & 0xffff) << 16) + extension), 1,
9f4a551e 609 State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 610}
611
2e35551c 612/* movbu dm, (d8,sp) */
d2523010
JL		 613void OP_F89200 (insn, extension)
614 unsigned long insn, extension;
05ccbdfd 615{
ecb4b5a3 616 store_mem (State.regs[REG_SP] + (insn & 0xff), 1,
9f4a551e 617 State.regs[REG_D0 + REG1_8 (insn)]);
05ccbdfd
JL		 618}
619
ecb4b5a3 620/* movbu dm, (d16,sp) */
d2523010
JL		 621void OP_FA920000 (insn, extension)
622 unsigned long insn, extension;
05ccbdfd 623{
ecb4b5a3 624 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
9f4a551e 625 State.regs[REG_D0 + REG1_8 (insn)]);
05ccbdfd
JL		 626}
627
de0dce7c 628/* movbu dm (d32,sp) */
d2523010
JL		 629void OP_FC920000 (insn, extension)
630 unsigned long insn, extension;
05ccbdfd 631{
de0dce7c 632 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
9f4a551e 633 State.regs[REG_D0 + REG1_8 (insn)]);
05ccbdfd
JL		 634}
635
f5f13c1d 636/* movbu dm, (di,an) */
d2523010
JL		 637void OP_F440 (insn, extension)
638 unsigned long insn, extension;
05ccbdfd 639{
9f4a551e
JL		 640 store_mem ((State.regs[REG_A0 + REG0 (insn)]
641 + State.regs[REG_D0 + REG1 (insn)]), 1,
642 State.regs[REG_D0 + REG0_8 (insn)]);
05ccbdfd
JL		 643}
644
707641f6 645/* movbu dm, (abs16) */
d2523010
JL		 646void OP_20000 (insn, extension)
647 unsigned long insn, extension;
05ccbdfd 648{
9f4a551e 649 store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 650}
651
de0dce7c 652/* movbu dm, (abs32) */
d2523010
JL		 653void OP_FC820000 (insn, extension)
654 unsigned long insn, extension;
05ccbdfd 655{
9f4a551e 656 store_mem ((((insn & 0xffff) << 16) + extension), 1, State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 657}
658
707641f6 659/* movhu (am), dn */
d2523010
JL		 660void OP_F060 (insn, extension)
661 unsigned long insn, extension;
05ccbdfd 662{
9f4a551e
JL		 663 State.regs[REG_D0 + REG1 (insn)]
664 = load_mem (State.regs[REG_A0 + REG0 (insn)], 2);
05ccbdfd
JL		 665}
666
2e35551c 667/* movhu (d8,am), dn */
d2523010
JL		 668void OP_F86000 (insn, extension)
669 unsigned long insn, extension;
05ccbdfd 670{
9f4a551e
JL		 671 State.regs[REG_D0 + REG1_8 (insn)]
672 = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
2e35551c 673 + SEXT8 (insn & 0xff)), 2);
05ccbdfd
JL		 674}
675
ecb4b5a3 676/* movhu (d16,am), dn */
d2523010
JL		 677void OP_FA600000 (insn, extension)
678 unsigned long insn, extension;
05ccbdfd 679{
9f4a551e
JL		 680 State.regs[REG_D0 + REG1_16 (insn)]
681 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
ecb4b5a3 682 + SEXT16 (insn & 0xffff)), 2);
05ccbdfd
JL		 683}
684
de0dce7c 685/* movhu (d32,am), dn */
d2523010
JL		 686void OP_FC600000 (insn, extension)
687 unsigned long insn, extension;
05ccbdfd 688{
9f4a551e
JL		 689 State.regs[REG_D0 + REG1_16 (insn)]
690 = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
de0dce7c 691 + ((insn & 0xffff) << 16) + extension), 2);
05ccbdfd
JL		 692}
693
2e35551c 694/* movhu (d8,sp) dn */
d2523010
JL		 695void OP_F8BC00 (insn, extension)
696 unsigned long insn, extension;
05ccbdfd 697{
9f4a551e 698 State.regs[REG_D0 + REG0_8 (insn)]
ecb4b5a3 699 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 2);
05ccbdfd
JL		 700}
701
ecb4b5a3 702/* movhu (d16,sp), dn */
d2523010
JL		 703void OP_FABC0000 (insn, extension)
704 unsigned long insn, extension;
05ccbdfd 705{
9f4a551e 706 State.regs[REG_D0 + REG0_16 (insn)]
ecb4b5a3 707 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 2);
05ccbdfd
JL		 708}
709
de0dce7c 710/* movhu (d32,sp), dn */
d2523010
JL		 711void OP_FCBC0000 (insn, extension)
712 unsigned long insn, extension;
05ccbdfd 713{
9f4a551e 714 State.regs[REG_D0 + REG0_16 (insn)]
de0dce7c 715 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2);
05ccbdfd
JL		 716}
717
f5f13c1d 718/* movhu (di,am), dn */
d2523010
JL		 719void OP_F480 (insn, extension)
720 unsigned long insn, extension;
05ccbdfd 721{
9f4a551e
JL		 722 State.regs[REG_D0 + REG0_8 (insn)]
723 = load_mem ((State.regs[REG_A0 + REG0 (insn)]
724 + State.regs[REG_D0 + REG1 (insn)]), 2);
05ccbdfd
JL		 725}
726
707641f6 727/* movhu (abs16), dn */
d2523010
JL		 728void OP_380000 (insn, extension)
729 unsigned long insn, extension;
05ccbdfd 730{
9f4a551e 731 State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 2);
05ccbdfd
JL		 732}
733
de0dce7c 734/* movhu (abs32), dn */
d2523010
JL		 735void OP_FCAC0000 (insn, extension)
736 unsigned long insn, extension;
05ccbdfd 737{
9f4a551e 738 State.regs[REG_D0 + REG0_16 (insn)]
de0dce7c 739 = load_mem ((((insn & 0xffff) << 16) + extension), 2);
05ccbdfd
JL		 740}
741
707641f6 742/* movhu dm, (an) */
d2523010
JL		 743void OP_F070 (insn, extension)
744 unsigned long insn, extension;
05ccbdfd 745{
9f4a551e
JL		 746 store_mem (State.regs[REG_A0 + REG0 (insn)], 2,
747 State.regs[REG_D0 + REG1 (insn)]);
05ccbdfd
JL		 748}
749
2e35551c 750/* movhu dm, (d8,an) */
d2523010
JL		 751void OP_F87000 (insn, extension)
752 unsigned long insn, extension;
05ccbdfd 753{
9f4a551e 754 store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
2e35551c 755 + SEXT8 (insn & 0xff)), 2,
9f4a551e 756 State.regs[REG_D0 + REG1_8 (insn)]);
05ccbdfd
JL		 757}
758
ecb4b5a3 759/* movhu dm, (d16,an) */
d2523010
JL		 760void OP_FA700000 (insn, extension)
761 unsigned long insn, extension;
05ccbdfd 762{
9f4a551e 763 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
ecb4b5a3 764 + SEXT16 (insn & 0xffff)), 2,
9f4a551e 765 State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 766}
767
de0dce7c 768/* movhu dm, (d32,an) */
d2523010
JL		 769void OP_FC700000 (insn, extension)
770 unsigned long insn, extension;
05ccbdfd 771{
9f4a551e 772 store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
de0dce7c 773 + ((insn & 0xffff) << 16) + extension), 2,
9f4a551e 774 State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 775}
776
2e35551c 777/* movhu dm,(d8,sp) */
d2523010
JL		 778void OP_F89300 (insn, extension)
779 unsigned long insn, extension;
05ccbdfd 780{
ecb4b5a3 781 store_mem (State.regs[REG_SP] + (insn & 0xff), 2,
9f4a551e 782 State.regs[REG_D0 + REG1_8 (insn)]);
05ccbdfd
JL		 783}
784
ecb4b5a3 785/* movhu dm,(d16,sp) */
d2523010
JL		 786void OP_FA930000 (insn, extension)
787 unsigned long insn, extension;
05ccbdfd 788{
ecb4b5a3 789 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
9f4a551e 790 State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 791}
792
de0dce7c 793/* movhu dm,(d32,sp) */
d2523010
JL		 794void OP_FC930000 (insn, extension)
795 unsigned long insn, extension;
05ccbdfd 796{
de0dce7c 797 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
9f4a551e 798 State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 799}
800
f5f13c1d 801/* movhu dm, (di,an) */
d2523010
JL		 802void OP_F4C0 (insn, extension)
803 unsigned long insn, extension;
05ccbdfd 804{
9f4a551e
JL		 805 store_mem ((State.regs[REG_A0 + REG0 (insn)]
806 + State.regs[REG_D0 + REG1 (insn)]), 2,
807 State.regs[REG_D0 + REG0_8 (insn)]);
05ccbdfd
JL		 808}
809
707641f6 810/* movhu dm, (abs16) */
d2523010
JL		 811void OP_30000 (insn, extension)
812 unsigned long insn, extension;
05ccbdfd 813{
9f4a551e 814 store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 815}
816
de0dce7c 817/* movhu dm, (abs32) */
d2523010
JL		 818void OP_FC830000 (insn, extension)
819 unsigned long insn, extension;
05ccbdfd 820{
9f4a551e 821 store_mem ((((insn & 0xffff) << 16) + extension), 2, State.regs[REG_D0 + REG1_16 (insn)]);
05ccbdfd
JL		 822}
823
707641f6 824/* ext dn */
d2523010
JL		 825void OP_F2D0 (insn, extension)
826 unsigned long insn, extension;
05ccbdfd 827{
9f4a551e 828 if (State.regs[REG_D0 + REG0 (insn)] & 0x80000000)
707641f6
JL		 829 State.regs[REG_MDR] = -1;
830 else
831 State.regs[REG_MDR] = 0;
05ccbdfd
JL		 832}
833
707641f6 834/* extb dn */
d2523010
JL		 835void OP_10 (insn, extension)
836 unsigned long insn, extension;
05ccbdfd 837{
9f4a551e 838 State.regs[REG_D0 + REG0 (insn)] = SEXT8 (State.regs[REG_D0 + REG0 (insn)]);
05ccbdfd
JL		 839}
840
707641f6 841/* extbu dn */
d2523010
JL		 842void OP_14 (insn, extension)
843 unsigned long insn, extension;
05ccbdfd 844{
9f4a551e 845 State.regs[REG_D0 + REG0 (insn)] &= 0xff;
05ccbdfd
JL		 846}
847
707641f6 848/* exth dn */
d2523010
JL		 849void OP_18 (insn, extension)
850 unsigned long insn, extension;
05ccbdfd 851{
9f4a551e
JL		 852 State.regs[REG_D0 + REG0 (insn)]
853 = SEXT16 (State.regs[REG_D0 + REG0 (insn)]);
05ccbdfd
JL		 854}
855
707641f6 856/* exthu dn */
d2523010
JL		 857void OP_1C (insn, extension)
858 unsigned long insn, extension;
05ccbdfd 859{
9f4a551e 860 State.regs[REG_D0 + REG0 (insn)] &= 0xffff;
05ccbdfd
JL		 861}
862
1f3bea21 863/* movm (sp), reg_list */
d2523010
JL		 864void OP_CE00 (insn, extension)
865 unsigned long insn, extension;
05ccbdfd 866{
1f3bea21
JL		 867 unsigned long sp = State.regs[REG_SP];
868 unsigned long mask;
869
870 mask = insn & 0xff;
871
872 if (mask & 0x8)
873 {
874 sp += 4;
875 State.regs[REG_LAR] = load_mem (sp, 4);
876 sp += 4;
877 State.regs[REG_LIR] = load_mem (sp, 4);
878 sp += 4;
879 State.regs[REG_MDR] = load_mem (sp, 4);
880 sp += 4;
881 State.regs[REG_A0 + 1] = load_mem (sp, 4);
882 sp += 4;
883 State.regs[REG_A0] = load_mem (sp, 4);
884 sp += 4;
885 State.regs[REG_D0 + 1] = load_mem (sp, 4);
886 sp += 4;
887 State.regs[REG_D0] = load_mem (sp, 4);
888 sp += 4;
889 }
890
891 if (mask & 0x10)
892 {
893 State.regs[REG_A0 + 3] = load_mem (sp, 4);
894 sp += 4;
895 }
896
897 if (mask & 0x20)
898 {
899 State.regs[REG_A0 + 2] = load_mem (sp, 4);
900 sp += 4;
901 }
902
903 if (mask & 0x40)
904 {
905 State.regs[REG_D0 + 3] = load_mem (sp, 4);
906 sp += 4;
907 }
908
909 if (mask & 0x80)
910 {
911 State.regs[REG_D0 + 2] = load_mem (sp, 4);
912 sp += 4;
913 }
914
915 /* And make sure to update the stack pointer. */
916 State.regs[REG_SP] = sp;
917}
918
919/* movm reg_list, (sp) */
d2523010
JL		 920void OP_CF00 (insn, extension)
921 unsigned long insn, extension;
05ccbdfd 922{
1f3bea21
JL		 923 unsigned long sp = State.regs[REG_SP];
924 unsigned long mask;
925
926 mask = insn & 0xff;
927
928 if (mask & 0x80)
929 {
930 sp -= 4;
6e7a01c1 931 store_mem (sp, 4, State.regs[REG_D0 + 2]);
1f3bea21
JL		 932 }
933
934 if (mask & 0x40)
935 {
936 sp -= 4;
6e7a01c1 937 store_mem (sp, 4, State.regs[REG_D0 + 3]);
1f3bea21
JL		 938 }
939
940 if (mask & 0x20)
941 {
942 sp -= 4;
6e7a01c1 943 store_mem (sp, 4, State.regs[REG_A0 + 2]);
1f3bea21
JL		 944 }
945
946 if (mask & 0x10)
947 {
948 sp -= 4;
6e7a01c1 949 store_mem (sp, 4, State.regs[REG_A0 + 3]);
1f3bea21
JL		 950 }
951
952 if (mask & 0x8)
953 {
954 sp -= 4;
6e7a01c1 955 store_mem (sp, 4, State.regs[REG_D0]);
1f3bea21 956 sp -= 4;
6e7a01c1 957 store_mem (sp, 4, State.regs[REG_D0 + 1]);
1f3bea21 958 sp -= 4;
6e7a01c1 959 store_mem (sp, 4, State.regs[REG_A0]);
1f3bea21 960 sp -= 4;
6e7a01c1 961 store_mem (sp, 4, State.regs[REG_A0 + 1]);
1f3bea21 962 sp -= 4;
6e7a01c1 963 store_mem (sp, 4, State.regs[REG_MDR]);
1f3bea21 964 sp -= 4;
6e7a01c1 965 store_mem (sp, 4, State.regs[REG_LIR]);
1f3bea21 966 sp -= 4;
6e7a01c1 967 store_mem (sp, 4, State.regs[REG_LAR]);
1f3bea21
JL		 968 sp -= 4;
969 }
970
971 /* And make sure to update the stack pointer. */
972 State.regs[REG_SP] = sp;
05ccbdfd
JL		 973}
974
73e65298 975/* clr dn */
d2523010
JL		 976void OP_0 (insn, extension)
977 unsigned long insn, extension;
05ccbdfd 978{
9f4a551e 979 State.regs[REG_D0 + REG1 (insn)] = 0;
73e65298
JL		 980
981 PSW |= PSW_Z;
982 PSW &= ~(PSW_V | PSW_C | PSW_N);
05ccbdfd
JL		 983}
984
de0dce7c 985/* add dm,dn */
d2523010
JL		 986void OP_E0 (insn, extension)
987 unsigned long insn, extension;
05ccbdfd 988{
73e65298
JL		 989 int z, c, n, v;
990 unsigned long reg1, reg2, value;
991
9f4a551e
JL		 992 reg1 = State.regs[REG_D0 + REG1 (insn)];
993 reg2 = State.regs[REG_D0 + REG0 (insn)];
73e65298 994 value = reg1 + reg2;
9f4a551e 995 State.regs[REG_D0 + REG0 (insn)] = value;
73e65298
JL		 996
997 z = (value == 0);
998 n = (value & 0x80000000);
999 c = (reg1 < reg2);
b7b89deb
JL		 1000 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1001 && (reg2 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1002
1003 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1004 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1005 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1006}
1007
73e65298 1008/* add dm, an */
d2523010
JL		 1009void OP_F160 (insn, extension)
1010 unsigned long insn, extension;
05ccbdfd 1011{
73e65298
JL		 1012 int z, c, n, v;
1013 unsigned long reg1, reg2, value;
1014
9f4a551e
JL		 1015 reg1 = State.regs[REG_D0 + REG1 (insn)];
1016 reg2 = State.regs[REG_A0 + REG0 (insn)];
73e65298 1017 value = reg1 + reg2;
9f4a551e 1018 State.regs[REG_A0 + REG0 (insn)] = value;
73e65298
JL		 1019
1020 z = (value == 0);
1021 n = (value & 0x80000000);
1022 c = (reg1 < reg2);
b7b89deb
JL		 1023 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1024 && (reg2 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1025
1026 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1027 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1028 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1029}
1030
de0dce7c 1031/* add am, dn */
d2523010
JL		 1032void OP_F150 (insn, extension)
1033 unsigned long insn, extension;
05ccbdfd 1034{
73e65298
JL		 1035 int z, c, n, v;
1036 unsigned long reg1, reg2, value;
1037
9f4a551e
JL		 1038 reg1 = State.regs[REG_A0 + REG1 (insn)];
1039 reg2 = State.regs[REG_D0 + REG0 (insn)];
73e65298 1040 value = reg1 + reg2;
9f4a551e 1041 State.regs[REG_D0 + REG0 (insn)] = value;
73e65298
JL		 1042
1043 z = (value == 0);
1044 n = (value & 0x80000000);
1045 c = (reg1 < reg2);
b7b89deb
JL		 1046 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1047 && (reg2 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1048
1049 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1050 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1051 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1052}
1053
73e65298 1054/* add am,an */
d2523010
JL		 1055void OP_F170 (insn, extension)
1056 unsigned long insn, extension;
05ccbdfd 1057{
73e65298
JL		 1058 int z, c, n, v;
1059 unsigned long reg1, reg2, value;
1060
9f4a551e
JL		 1061 reg1 = State.regs[REG_A0 + REG1 (insn)];
1062 reg2 = State.regs[REG_A0 + REG0 (insn)];
73e65298 1063 value = reg1 + reg2;
9f4a551e 1064 State.regs[REG_A0 + REG0 (insn)] = value;
73e65298
JL		 1065
1066 z = (value == 0);
1067 n = (value & 0x80000000);
1068 c = (reg1 < reg2);
b7b89deb
JL		 1069 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1070 && (reg2 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1071
1072 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1073 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1074 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1075}
1076
73e65298 1077/* add imm8, dn */
d2523010
JL		 1078void OP_2800 (insn, extension)
1079 unsigned long insn, extension;
05ccbdfd 1080{
73e65298
JL		 1081 int z, c, n, v;
1082 unsigned long reg1, imm, value;
1083
9f4a551e 1084 reg1 = State.regs[REG_D0 + REG0_8 (insn)];
73e65298
JL		 1085 imm = SEXT8 (insn & 0xff);
1086 value = reg1 + imm;
9f4a551e 1087 State.regs[REG_D0 + REG0_8 (insn)] = value;
73e65298
JL		 1088
1089 z = (value == 0);
1090 n = (value & 0x80000000);
1091 c = (reg1 < imm);
b7b89deb
JL		 1092 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1093 && (reg1 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1094
1095 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1096 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1097 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1098}
1099
73e65298 1100/* add imm16, dn */
d2523010
JL		 1101void OP_FAC00000 (insn, extension)
1102 unsigned long insn, extension;
05ccbdfd 1103{
73e65298
JL		 1104 int z, c, n, v;
1105 unsigned long reg1, imm, value;
1106
9f4a551e 1107 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
73e65298
JL		 1108 imm = SEXT16 (insn & 0xffff);
1109 value = reg1 + imm;
9f4a551e 1110 State.regs[REG_D0 + REG0_16 (insn)] = value;
73e65298
JL		 1111
1112 z = (value == 0);
1113 n = (value & 0x80000000);
1114 c = (reg1 < imm);
b7b89deb
JL		 1115 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1116 && (reg1 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1117
1118 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1119 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1120 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1121}
1122
73e65298 1123/* add imm32,dn */
d2523010
JL		 1124void OP_FCC00000 (insn, extension)
1125 unsigned long insn, extension;
05ccbdfd 1126{
73e65298
JL		 1127 int z, c, n, v;
1128 unsigned long reg1, imm, value;
1129
9f4a551e 1130 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
7c52bf32 1131 imm = ((insn & 0xffff) << 16) + extension;
73e65298 1132 value = reg1 + imm;
9f4a551e 1133 State.regs[REG_D0 + REG0_16 (insn)] = value;
73e65298
JL		 1134
1135 z = (value == 0);
1136 n = (value & 0x80000000);
1137 c = (reg1 < imm);
b7b89deb
JL		 1138 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1139 && (reg1 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1140
1141 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1142 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1143 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1144}
1145
73e65298 1146/* add imm8, an */
d2523010
JL		 1147void OP_2000 (insn, extension)
1148 unsigned long insn, extension;
05ccbdfd 1149{
73e65298
JL		 1150 int z, c, n, v;
1151 unsigned long reg1, imm, value;
1152
9f4a551e 1153 reg1 = State.regs[REG_A0 + REG0_8 (insn)];
6e7a01c1 1154 imm = SEXT8 (insn & 0xff);
73e65298 1155 value = reg1 + imm;
9f4a551e 1156 State.regs[REG_A0 + REG0_8 (insn)] = value;
73e65298
JL		 1157
1158 z = (value == 0);
1159 n = (value & 0x80000000);
1160 c = (reg1 < imm);
b7b89deb
JL		 1161 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1162 && (reg1 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1163
1164 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1165 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1166 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1167}
1168
73e65298 1169/* add imm16, an */
d2523010
JL		 1170void OP_FAD00000 (insn, extension)
1171 unsigned long insn, extension;
05ccbdfd 1172{
73e65298
JL		 1173 int z, c, n, v;
1174 unsigned long reg1, imm, value;
1175
9f4a551e 1176 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
6e7a01c1 1177 imm = SEXT16 (insn & 0xffff);
73e65298 1178 value = reg1 + imm;
9f4a551e 1179 State.regs[REG_A0 + REG0_16 (insn)] = value;
73e65298
JL		 1180
1181 z = (value == 0);
1182 n = (value & 0x80000000);
1183 c = (reg1 < imm);
b7b89deb
JL		 1184 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1185 && (reg1 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1186
1187 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1188 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1189 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1190}
1191
73e65298 1192/* add imm32, an */
d2523010
JL		 1193void OP_FCD00000 (insn, extension)
1194 unsigned long insn, extension;
05ccbdfd 1195{
73e65298
JL		 1196 int z, c, n, v;
1197 unsigned long reg1, imm, value;
1198
9f4a551e 1199 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
7c52bf32 1200 imm = ((insn & 0xffff) << 16) + extension;
73e65298 1201 value = reg1 + imm;
9f4a551e 1202 State.regs[REG_A0 + REG0_16 (insn)] = value;
73e65298
JL		 1203
1204 z = (value == 0);
1205 n = (value & 0x80000000);
1206 c = (reg1 < imm);
b7b89deb
JL		 1207 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1208 && (reg1 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1209
1210 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1211 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1212 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1213}
1214
de0dce7c 1215/* add imm8, sp */
d2523010
JL		 1216void OP_F8FE00 (insn, extension)
1217 unsigned long insn, extension;
05ccbdfd 1218{
73e65298
JL		 1219 unsigned long reg1, imm, value;
1220
1221 reg1 = State.regs[REG_SP];
1222 imm = SEXT8 (insn & 0xff);
1223 value = reg1 + imm;
1224 State.regs[REG_SP] = value;
05ccbdfd
JL		 1225}
1226
73e65298 1227/* add imm16,sp */
d2523010
JL		 1228void OP_FAFE0000 (insn, extension)
1229 unsigned long insn, extension;
05ccbdfd 1230{
73e65298
JL		 1231 unsigned long reg1, imm, value;
1232
1233 reg1 = State.regs[REG_SP];
1234 imm = SEXT16 (insn & 0xffff);
1235 value = reg1 + imm;
1236 State.regs[REG_SP] = value;
05ccbdfd
JL		 1237}
1238
de0dce7c 1239/* add imm32, sp */
d2523010
JL		 1240void OP_FCFE0000 (insn, extension)
1241 unsigned long insn, extension;
05ccbdfd 1242{
73e65298
JL		 1243 unsigned long reg1, imm, value;
1244
1245 reg1 = State.regs[REG_SP];
7c52bf32 1246 imm = ((insn & 0xffff) << 16) + extension;
73e65298
JL		 1247 value = reg1 + imm;
1248 State.regs[REG_SP] = value;
05ccbdfd
JL		 1249}
1250
de0dce7c 1251/* addc dm,dn */
d2523010
JL		 1252void OP_F140 (insn, extension)
1253 unsigned long insn, extension;
05ccbdfd 1254{
73e65298
JL		 1255 int z, c, n, v;
1256 unsigned long reg1, reg2, value;
1257
9f4a551e
JL		 1258 reg1 = State.regs[REG_D0 + REG1 (insn)];
1259 reg2 = State.regs[REG_D0 + REG0 (insn)];
73e65298 1260 value = reg1 + reg2 + ((PSW & PSW_C) != 0);
9f4a551e 1261 State.regs[REG_D0 + REG0 (insn)] = value;
73e65298
JL		 1262
1263 z = (value == 0);
1264 n = (value & 0x80000000);
1265 c = (reg1 < reg2);
b7b89deb
JL		 1266 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1267 && (reg2 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1268
1269 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1270 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1271 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1272}
1273
707641f6 1274/* sub dm, dn */
d2523010
JL		 1275void OP_F100 (insn, extension)
1276 unsigned long insn, extension;
05ccbdfd 1277{
707641f6
JL		 1278 int z, c, n, v;
1279 unsigned long reg1, reg2, value;
1280
9f4a551e
JL		 1281 reg1 = State.regs[REG_D0 + REG1 (insn)];
1282 reg2 = State.regs[REG_D0 + REG0 (insn)];
707641f6
JL		 1283 value = reg2 - reg1;
1284
1285 z = (value == 0);
1286 n = (value & 0x80000000);
216e6557 1287 c = (reg1 > reg2);
b7b89deb
JL		 1288 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1289 && (reg2 & 0x80000000) != (value & 0x80000000));
707641f6
JL		 1290
1291 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1292 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1293 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
9f4a551e 1294 State.regs[REG_D0 + REG0 (insn)] = value;
05ccbdfd
JL		 1295}
1296
707641f6 1297/* sub dm, an */
d2523010
JL		 1298void OP_F120 (insn, extension)
1299 unsigned long insn, extension;
05ccbdfd 1300{
707641f6
JL		 1301 int z, c, n, v;
1302 unsigned long reg1, reg2, value;
1303
9f4a551e
JL		 1304 reg1 = State.regs[REG_D0 + REG1 (insn)];
1305 reg2 = State.regs[REG_A0 + REG0 (insn)];
707641f6
JL		 1306 value = reg2 - reg1;
1307
1308 z = (value == 0);
1309 n = (value & 0x80000000);
216e6557 1310 c = (reg1 > reg2);
b7b89deb
JL		 1311 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1312 && (reg2 & 0x80000000) != (value & 0x80000000));
707641f6
JL		 1313
1314 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1315 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1316 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
9f4a551e 1317 State.regs[REG_A0 + REG0 (insn)] = value;
05ccbdfd
JL		 1318}
1319
707641f6 1320/* sub am, dn */
d2523010
JL		 1321void OP_F110 (insn, extension)
1322 unsigned long insn, extension;
05ccbdfd 1323{
707641f6
JL		 1324 int z, c, n, v;
1325 unsigned long reg1, reg2, value;
1326
9f4a551e
JL		 1327 reg1 = State.regs[REG_A0 + REG1 (insn)];
1328 reg2 = State.regs[REG_D0 + REG0 (insn)];
707641f6
JL		 1329 value = reg2 - reg1;
1330
1331 z = (value == 0);
1332 n = (value & 0x80000000);
216e6557 1333 c = (reg1 > reg2);
b7b89deb
JL		 1334 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1335 && (reg2 & 0x80000000) != (value & 0x80000000));
707641f6
JL		 1336
1337 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1338 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1339 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
9f4a551e 1340 State.regs[REG_D0 + REG0 (insn)] = value;
05ccbdfd
JL		 1341}
1342
707641f6 1343/* sub am, an */
d2523010
JL		 1344void OP_F130 (insn, extension)
1345 unsigned long insn, extension;
05ccbdfd 1346{
707641f6
JL		 1347 int z, c, n, v;
1348 unsigned long reg1, reg2, value;
1349
9f4a551e
JL		 1350 reg1 = State.regs[REG_A0 + REG1 (insn)];
1351 reg2 = State.regs[REG_A0 + REG0 (insn)];
707641f6
JL		 1352 value = reg2 - reg1;
1353
1354 z = (value == 0);
1355 n = (value & 0x80000000);
216e6557 1356 c = (reg1 > reg2);
b7b89deb
JL		 1357 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1358 && (reg2 & 0x80000000) != (value & 0x80000000));
707641f6
JL		 1359
1360 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1361 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1362 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
9f4a551e 1363 State.regs[REG_A0 + REG0 (insn)] = value;
05ccbdfd
JL		 1364}
1365
de0dce7c 1366/* sub imm32, dn */
d2523010
JL		 1367void OP_FCC40000 (insn, extension)
1368 unsigned long insn, extension;
05ccbdfd 1369{
707641f6
JL		 1370 int z, c, n, v;
1371 unsigned long reg1, imm, value;
1372
9f4a551e 1373 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
7c52bf32 1374 imm = ((insn & 0xffff) << 16) + extension;
707641f6
JL		 1375 value = reg1 - imm;
1376
1377 z = (value == 0);
1378 n = (value & 0x80000000);
1379 c = (reg1 < imm);
b7b89deb
JL		 1380 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1381 && (reg1 & 0x80000000) != (value & 0x80000000));
707641f6
JL		 1382
1383 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1384 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1385 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
9f4a551e 1386 State.regs[REG_D0 + REG0_16 (insn)] = value;
05ccbdfd
JL		 1387}
1388
de0dce7c 1389/* sub imm32, an */
d2523010
JL		 1390void OP_FCD40000 (insn, extension)
1391 unsigned long insn, extension;
05ccbdfd 1392{
707641f6
JL		 1393 int z, c, n, v;
1394 unsigned long reg1, imm, value;
1395
9f4a551e 1396 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
7c52bf32 1397 imm = ((insn & 0xffff) << 16) + extension;
707641f6
JL		 1398 value = reg1 - imm;
1399
1400 z = (value == 0);
1401 n = (value & 0x80000000);
1402 c = (reg1 < imm);
b7b89deb
JL		 1403 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1404 && (reg1 & 0x80000000) != (value & 0x80000000));
707641f6
JL		 1405
1406 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1407 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1408 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
9f4a551e 1409 State.regs[REG_A0 + REG0_16 (insn)] = value;
05ccbdfd
JL		 1410}
1411
de0dce7c 1412/* subc dm, dn */
d2523010
JL		 1413void OP_F180 (insn, extension)
1414 unsigned long insn, extension;
05ccbdfd 1415{
707641f6
JL		 1416 int z, c, n, v;
1417 unsigned long reg1, reg2, value;
1418
9f4a551e
JL		 1419 reg1 = State.regs[REG_D0 + REG1 (insn)];
1420 reg2 = State.regs[REG_D0 + REG0 (insn)];
707641f6
JL		 1421 value = reg2 - reg1 - ((PSW & PSW_C) != 0);
1422
1423 z = (value == 0);
1424 n = (value & 0x80000000);
216e6557 1425 c = (reg1 > reg2);
b7b89deb
JL		 1426 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1427 && (reg2 & 0x80000000) != (value & 0x80000000));
707641f6
JL		 1428
1429 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1430 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1431 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
9f4a551e 1432 State.regs[REG_D0 + REG0 (insn)] = value;
05ccbdfd
JL		 1433}
1434
de0dce7c 1435/* mul dm, dn */
d2523010
JL		 1436void OP_F240 (insn, extension)
1437 unsigned long insn, extension;
05ccbdfd 1438{
707641f6
JL		 1439 unsigned long long temp;
1440 int n, z;
1441
9f4a551e
JL		 1442 temp = (State.regs[REG_D0 + REG0 (insn)]
1443 * State.regs[REG_D0 + REG1 (insn)]);
1444 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
707641f6 1445 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
9f4a551e
JL		 1446 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1447 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
707641f6
JL		 1448 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1449 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1450}
1451
de0dce7c 1452/* mulu dm, dn */
d2523010
JL		 1453void OP_F250 (insn, extension)
1454 unsigned long insn, extension;
05ccbdfd 1455{
707641f6
JL		 1456 unsigned long long temp;
1457 int n, z;
1458
9f4a551e
JL		 1459 temp = (State.regs[REG_D0 + REG0 (insn)]
1460 * State.regs[REG_D0 + REG1 (insn)]);
1461 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
707641f6 1462 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
9f4a551e
JL		 1463 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1464 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
707641f6
JL		 1465 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1466 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1467}
1468
de0dce7c 1469/* div dm, dn */
d2523010
JL		 1470void OP_F260 (insn, extension)
1471 unsigned long insn, extension;
05ccbdfd 1472{
707641f6
JL		 1473 long long temp;
1474 int n, z;
1475
1476 temp = State.regs[REG_MDR];
1477 temp <<= 32;
9f4a551e
JL		 1478 temp |= State.regs[REG_D0 + REG0 (insn)];
1479 State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + REG1 (insn)];
1480 temp /= (long)State.regs[REG_D0 + REG1 (insn)];
1481 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
707641f6 1482 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
9f4a551e
JL		 1483 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1484 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
707641f6
JL		 1485 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1486 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1487}
1488
de0dce7c 1489/* divu dm, dn */
d2523010
JL		 1490void OP_F270 (insn, extension)
1491 unsigned long insn, extension;
05ccbdfd 1492{
707641f6
JL		 1493 unsigned long long temp;
1494 int n, z;
1495
1496 temp = State.regs[REG_MDR];
1497 temp <<= 32;
9f4a551e
JL		 1498 temp |= State.regs[REG_D0 + REG0 (insn)];
1499 State.regs[REG_MDR] = temp % State.regs[REG_D0 + REG1 (insn)];
1500 temp /= State.regs[REG_D0 + REG1 (insn)];
1501 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
707641f6 1502 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
9f4a551e
JL		 1503 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1504 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
707641f6
JL		 1505 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1506 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1507}
1508
73e65298 1509/* inc dn */
d2523010
JL		 1510void OP_40 (insn, extension)
1511 unsigned long insn, extension;
05ccbdfd 1512{
61ecca95 1513 int z,n,c,v;
4d8ced6c 1514 unsigned int value, imm, reg1;
61ecca95 1515
9f4a551e 1516 reg1 = State.regs[REG_D0 + REG1 (insn)];
4d8ced6c
JL		 1517 imm = 1;
1518 value = reg1 + imm;
9f4a551e 1519 State.regs[REG_D0 + REG1 (insn)] = value;
61ecca95
JL		 1520
1521 z = (value == 0);
1522 n = (value & 0x80000000);
4d8ced6c
JL		 1523 c = (reg1 < imm);
1524 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1525 && (reg1 & 0x80000000) != (value & 0x80000000));
61ecca95
JL		 1526
1527 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1528 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1529 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1530}
1531
73e65298 1532/* inc an */
d2523010
JL		 1533void OP_41 (insn, extension)
1534 unsigned long insn, extension;
05ccbdfd 1535{
9f4a551e 1536 State.regs[REG_A0 + REG1 (insn)] += 1;
05ccbdfd
JL		 1537}
1538
92284aaa 1539/* inc4 an */
d2523010
JL		 1540void OP_50 (insn, extension)
1541 unsigned long insn, extension;
05ccbdfd 1542{
9f4a551e 1543 State.regs[REG_A0 + REG0 (insn)] += 4;
05ccbdfd
JL		 1544}
1545
92284aaa 1546/* cmp imm8, dn */
d2523010
JL		 1547void OP_A000 (insn, extension)
1548 unsigned long insn, extension;
05ccbdfd 1549{
92284aaa
JL		 1550 int z, c, n, v;
1551 unsigned long reg1, imm, value;
1552
9f4a551e 1553 reg1 = State.regs[REG_D0 + REG0_8 (insn)];
92284aaa
JL		 1554 imm = SEXT8 (insn & 0xff);
1555 value = reg1 - imm;
1556
1557 z = (value == 0);
1558 n = (value & 0x80000000);
1559 c = (reg1 < imm);
b7b89deb
JL		 1560 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1561 && (reg1 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1562
1563 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1564 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1565 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1566}
1567
92284aaa 1568/* cmp dm, dn */
d2523010
JL		 1569void OP_A0 (insn, extension)
1570 unsigned long insn, extension;
05ccbdfd 1571{
92284aaa
JL		 1572 int z, c, n, v;
1573 unsigned long reg1, reg2, value;
1574
9f4a551e
JL		 1575 reg1 = State.regs[REG_D0 + REG1 (insn)];
1576 reg2 = State.regs[REG_D0 + REG0 (insn)];
707641f6 1577 value = reg2 - reg1;
92284aaa
JL		 1578
1579 z = (value == 0);
1580 n = (value & 0x80000000);
216e6557 1581 c = (reg1 > reg2);
b7b89deb
JL		 1582 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1583 && (reg2 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1584
1585 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1586 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1587 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1588}
1589
92284aaa 1590/* cmp dm, an */
d2523010
JL		 1591void OP_F1A0 (insn, extension)
1592 unsigned long insn, extension;
05ccbdfd 1593{
92284aaa
JL		 1594 int z, c, n, v;
1595 unsigned long reg1, reg2, value;
1596
9f4a551e
JL		 1597 reg1 = State.regs[REG_D0 + REG1 (insn)];
1598 reg2 = State.regs[REG_A0 + REG0 (insn)];
707641f6 1599 value = reg2 - reg1;
92284aaa
JL		 1600
1601 z = (value == 0);
1602 n = (value & 0x80000000);
216e6557 1603 c = (reg1 > reg2);
b7b89deb
JL		 1604 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1605 && (reg2 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1606
1607 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1608 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1609 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1610}
1611
92284aaa 1612/* cmp am, dn */
d2523010
JL		 1613void OP_F190 (insn, extension)
1614 unsigned long insn, extension;
05ccbdfd 1615{
92284aaa
JL		 1616 int z, c, n, v;
1617 unsigned long reg1, reg2, value;
1618
9f4a551e
JL		 1619 reg1 = State.regs[REG_A0 + REG1 (insn)];
1620 reg2 = State.regs[REG_D0 + REG0 (insn)];
707641f6 1621 value = reg2 - reg1;
92284aaa
JL		 1622
1623 z = (value == 0);
1624 n = (value & 0x80000000);
216e6557 1625 c = (reg1 > reg2);
b7b89deb
JL		 1626 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1627 && (reg2 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1628
1629 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1630 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1631 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1632}
1633
92284aaa 1634/* cmp imm8, an */
d2523010
JL		 1635void OP_B000 (insn, extension)
1636 unsigned long insn, extension;
05ccbdfd 1637{
92284aaa
JL		 1638 int z, c, n, v;
1639 unsigned long reg1, imm, value;
1640
9f4a551e 1641 reg1 = State.regs[REG_A0 + REG0_8 (insn)];
92284aaa
JL		 1642 imm = insn & 0xff;
1643 value = reg1 - imm;
1644
1645 z = (value == 0);
1646 n = (value & 0x80000000);
1647 c = (reg1 < imm);
b7b89deb
JL		 1648 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1649 && (reg1 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1650
1651 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1652 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1653 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1654}
1655
707641f6 1656/* cmp am, an */
d2523010
JL		 1657void OP_B0 (insn, extension)
1658 unsigned long insn, extension;
05ccbdfd 1659{
73e65298
JL		 1660 int z, c, n, v;
1661 unsigned long reg1, reg2, value;
1662
9f4a551e
JL		 1663 reg1 = State.regs[REG_A0 + REG1 (insn)];
1664 reg2 = State.regs[REG_A0 + REG0 (insn)];
707641f6 1665 value = reg2 - reg1;
73e65298
JL		 1666
1667 z = (value == 0);
1668 n = (value & 0x80000000);
216e6557 1669 c = (reg1 > reg2);
b7b89deb
JL		 1670 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1671 && (reg2 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1672
1673 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1674 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1675 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1676}
1677
707641f6 1678/* cmp imm16, dn */
d2523010
JL		 1679void OP_FAC80000 (insn, extension)
1680 unsigned long insn, extension;
05ccbdfd 1681{
92284aaa
JL		 1682 int z, c, n, v;
1683 unsigned long reg1, imm, value;
1684
9f4a551e 1685 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
92284aaa
JL		 1686 imm = SEXT16 (insn & 0xffff);
1687 value = reg1 - imm;
1688
1689 z = (value == 0);
1690 n = (value & 0x80000000);
1691 c = (reg1 < imm);
b7b89deb
JL		 1692 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1693 && (reg1 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1694
1695 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1696 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1697 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1698}
1699
707641f6 1700/* cmp imm32, dn */
d2523010
JL		 1701void OP_FCC80000 (insn, extension)
1702 unsigned long insn, extension;
05ccbdfd 1703{
92284aaa
JL		 1704 int z, c, n, v;
1705 unsigned long reg1, imm, value;
1706
9f4a551e 1707 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
7c52bf32 1708 imm = ((insn & 0xffff) << 16) + extension;
92284aaa
JL		 1709 value = reg1 - imm;
1710
1711 z = (value == 0);
1712 n = (value & 0x80000000);
1713 c = (reg1 < imm);
b7b89deb
JL		 1714 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1715 && (reg1 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1716
1717 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1718 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1719 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1720}
1721
707641f6 1722/* cmp imm16, an */
d2523010
JL		 1723void OP_FAD80000 (insn, extension)
1724 unsigned long insn, extension;
05ccbdfd 1725{
92284aaa
JL		 1726 int z, c, n, v;
1727 unsigned long reg1, imm, value;
1728
9f4a551e 1729 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
92284aaa
JL		 1730 imm = insn & 0xffff;
1731 value = reg1 - imm;
1732
1733 z = (value == 0);
1734 n = (value & 0x80000000);
1735 c = (reg1 < imm);
b7b89deb
JL		 1736 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1737 && (reg1 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1738
1739 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1740 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1741 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1742}
1743
707641f6 1744/* cmp imm32, an */
d2523010
JL		 1745void OP_FCD80000 (insn, extension)
1746 unsigned long insn, extension;
05ccbdfd 1747{
92284aaa
JL		 1748 int z, c, n, v;
1749 unsigned long reg1, imm, value;
1750
9f4a551e 1751 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
7c52bf32 1752 imm = ((insn & 0xffff) << 16) + extension;
92284aaa
JL		 1753 value = reg1 - imm;
1754
1755 z = (value == 0);
1756 n = (value & 0x80000000);
1757 c = (reg1 < imm);
b7b89deb
JL		 1758 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1759 && (reg1 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1760
1761 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1762 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1763 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1764}
1765
707641f6 1766/* and dm, dn */
d2523010
JL		 1767void OP_F200 (insn, extension)
1768 unsigned long insn, extension;
05ccbdfd 1769{
707641f6
JL		 1770 int n, z;
1771
9f4a551e
JL		 1772 State.regs[REG_D0 + REG0 (insn)] &= State.regs[REG_D0 + REG1 (insn)];
1773 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1774 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
707641f6
JL		 1775 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1776 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1777}
1778
2e35551c 1779/* and imm8, dn */
d2523010
JL		 1780void OP_F8E000 (insn, extension)
1781 unsigned long insn, extension;
05ccbdfd 1782{
2e35551c
JL		 1783 int n, z;
1784
9f4a551e
JL		 1785 State.regs[REG_D0 + REG0_8 (insn)] &= (insn & 0xff);
1786 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
1787 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
2e35551c
JL		 1788 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1789 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1790}
1791
ecb4b5a3 1792/* and imm16, dn */
d2523010
JL		 1793void OP_FAE00000 (insn, extension)
1794 unsigned long insn, extension;
05ccbdfd 1795{
ecb4b5a3
JL		 1796 int n, z;
1797
9f4a551e
JL		 1798 State.regs[REG_D0 + REG0_16 (insn)] &= (insn & 0xffff);
1799 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1800 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
ecb4b5a3
JL		 1801 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1802 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1803}
1804
de0dce7c 1805/* and imm32, dn */
d2523010
JL		 1806void OP_FCE00000 (insn, extension)
1807 unsigned long insn, extension;
05ccbdfd 1808{
de0dce7c
JL		 1809 int n, z;
1810
9f4a551e 1811 State.regs[REG_D0 + REG0_16 (insn)]
7c52bf32 1812 &= ((insn & 0xffff) << 16) + extension;
9f4a551e
JL		 1813 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1814 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
de0dce7c
JL		 1815 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1816 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1817}
1818
ecb4b5a3 1819/* and imm16, psw */
d2523010
JL		 1820void OP_FAFC0000 (insn, extension)
1821 unsigned long insn, extension;
05ccbdfd 1822{
ecb4b5a3 1823 PSW &= (insn & 0xffff);
05ccbdfd
JL		 1824}
1825
707641f6 1826/* or dm, dn*/
d2523010
JL		 1827void OP_F210 (insn, extension)
1828 unsigned long insn, extension;
05ccbdfd 1829{
707641f6
JL		 1830 int n, z;
1831
9f4a551e
JL		 1832 State.regs[REG_D0 + REG0 (insn)] |= State.regs[REG_D0 + REG1 (insn)];
1833 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1834 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
707641f6
JL		 1835 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1836 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1837}
1838
2e35551c 1839/* or imm8, dn */
d2523010
JL		 1840void OP_F8E400 (insn, extension)
1841 unsigned long insn, extension;
05ccbdfd 1842{
2e35551c
JL		 1843 int n, z;
1844
9f4a551e
JL		 1845 State.regs[REG_D0 + REG0_8 (insn)] |= insn & 0xff;
1846 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
1847 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
2e35551c
JL		 1848 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1849 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1850}
1851
ecb4b5a3 1852/* or imm16, dn*/
d2523010
JL		 1853void OP_FAE40000 (insn, extension)
1854 unsigned long insn, extension;
05ccbdfd 1855{
ecb4b5a3
JL		 1856 int n, z;
1857
9f4a551e
JL		 1858 State.regs[REG_D0 + REG0_16 (insn)] |= insn & 0xffff;
1859 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1860 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
ecb4b5a3
JL		 1861 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1862 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1863}
1864
de0dce7c 1865/* or imm32, dn */
d2523010
JL		 1866void OP_FCE40000 (insn, extension)
1867 unsigned long insn, extension;
05ccbdfd 1868{
de0dce7c
JL		 1869 int n, z;
1870
9f4a551e 1871 State.regs[REG_D0 + REG0_16 (insn)]
7c52bf32 1872 |= ((insn & 0xffff) << 16) + extension;
9f4a551e
JL		 1873 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1874 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
de0dce7c
JL		 1875 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1876 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1877}
1878
ecb4b5a3 1879/* or imm16,psw */
d2523010
JL		 1880void OP_FAFD0000 (insn, extension)
1881 unsigned long insn, extension;
05ccbdfd 1882{
ecb4b5a3 1883 PSW |= (insn & 0xffff);
05ccbdfd
JL		 1884}
1885
707641f6 1886/* xor dm, dn*/
d2523010
JL		 1887void OP_F220 (insn, extension)
1888 unsigned long insn, extension;
05ccbdfd 1889{
707641f6
JL		 1890 int n, z;
1891
9f4a551e
JL		 1892 State.regs[REG_D0 + REG0 (insn)] ^= State.regs[REG_D0 + REG1 (insn)];
1893 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1894 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
707641f6
JL		 1895 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1896 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1897}
1898
ecb4b5a3 1899/* xor imm16, dn */
d2523010
JL		 1900void OP_FAE80000 (insn, extension)
1901 unsigned long insn, extension;
05ccbdfd 1902{
ecb4b5a3
JL		 1903 int n, z;
1904
9f4a551e
JL		 1905 State.regs[REG_D0 + REG0_16 (insn)] ^= insn & 0xffff;
1906 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1907 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
ecb4b5a3
JL		 1908 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1909 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1910}
1911
de0dce7c 1912/* xor imm32, dn */
d2523010
JL		 1913void OP_FCE80000 (insn, extension)
1914 unsigned long insn, extension;
05ccbdfd 1915{
de0dce7c
JL		 1916 int n, z;
1917
9f4a551e 1918 State.regs[REG_D0 + REG0_16 (insn)]
7c52bf32 1919 ^= ((insn & 0xffff) << 16) + extension;
9f4a551e
JL		 1920 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1921 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
de0dce7c
JL		 1922 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1923 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1924}
1925
de0dce7c 1926/* not dn */
d2523010
JL		 1927void OP_F230 (insn, extension)
1928 unsigned long insn, extension;
05ccbdfd 1929{
707641f6
JL		 1930 int n, z;
1931
9f4a551e
JL		 1932 State.regs[REG_D0 + REG0 (insn)] = ~State.regs[REG_D0 + REG0 (insn)];
1933 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1934 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
707641f6
JL		 1935 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1936 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1937}
1938
2e35551c 1939/* btst imm8, dn */
d2523010
JL		 1940void OP_F8EC00 (insn, extension)
1941 unsigned long insn, extension;
05ccbdfd 1942{
2e35551c
JL		 1943 unsigned long temp;
1944 int z, n;
1945
9f4a551e 1946 temp = State.regs[REG_D0 + REG0_8 (insn)];
2e35551c
JL		 1947 temp &= (insn & 0xff);
1948 n = (temp & 0x80000000) != 0;
1949 z = (temp == 0);
1950 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1951 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
05ccbdfd
JL		 1952}
1953
ecb4b5a3 1954/* btst imm16, dn */
d2523010
JL		 1955void OP_FAEC0000 (insn, extension)
1956 unsigned long insn, extension;
05ccbdfd 1957{
ecb4b5a3
JL		 1958 unsigned long temp;
1959 int z, n;
1960
9f4a551e 1961 temp = State.regs[REG_D0 + REG0_16 (insn)];
ecb4b5a3
JL		 1962 temp &= (insn & 0xffff);
1963 n = (temp & 0x80000000) != 0;
1964 z = (temp == 0);
1965 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1966 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
05ccbdfd
JL		 1967}
1968
de0dce7c 1969/* btst imm32, dn */
d2523010
JL		 1970void OP_FCEC0000 (insn, extension)
1971 unsigned long insn, extension;
05ccbdfd 1972{
de0dce7c
JL		 1973 unsigned long temp;
1974 int z, n;
1975
9f4a551e 1976 temp = State.regs[REG_D0 + REG0_16 (insn)];
7c52bf32 1977 temp &= ((insn & 0xffff) << 16) + extension;
de0dce7c
JL		 1978 n = (temp & 0x80000000) != 0;
1979 z = (temp == 0);
1980 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1981 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
05ccbdfd
JL		 1982}
1983
de0dce7c 1984/* btst imm8,(abs32) */
d2523010
JL		 1985void OP_FE020000 (insn, extension)
1986 unsigned long insn, extension;
05ccbdfd 1987{
de0dce7c
JL		 1988 unsigned long temp;
1989 int n, z;
1990
1991 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
1992 temp &= (extension & 0xff);
1993 n = (temp & 0x80000000) != 0;
1994 z = (temp == 0);
1995 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1996 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
05ccbdfd
JL		 1997}
1998
ecb4b5a3 1999/* btst imm8,(d8,an) */
d2523010
JL		 2000void OP_FAF80000 (insn, extension)
2001 unsigned long insn, extension;
05ccbdfd 2002{
ecb4b5a3
JL		 2003 unsigned long temp;
2004 int n, z;
2005
9f4a551e 2006 temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
ecb4b5a3
JL		 2007 + SEXT8 ((insn & 0xff00) >> 8)), 1);
2008 temp &= (insn & 0xff);
2009 n = (temp & 0x80000000) != 0;
2010 z = (temp == 0);
2011 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2012 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
05ccbdfd
JL		 2013}
2014
707641f6 2015/* bset dm, (an) */
d2523010
JL		 2016void OP_F080 (insn, extension)
2017 unsigned long insn, extension;
05ccbdfd 2018{
707641f6
JL		 2019 unsigned long temp;
2020 int z;
2021
2022 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
9f4a551e
JL		 2023 z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
2024 temp |= State.regs[REG_D0 + REG1 (insn)];
707641f6
JL		 2025 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
2026 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2027 PSW |= (z ? PSW_Z : 0);
05ccbdfd
JL		 2028}
2029
de0dce7c 2030/* bset imm8, (abs32) */
d2523010
JL		 2031void OP_FE000000 (insn, extension)
2032 unsigned long insn, extension;
05ccbdfd 2033{
de0dce7c
JL		 2034 unsigned long temp;
2035 int z;
2036
2037 temp = load_mem (((insn & 0xffff) << 16 | (extension >> 8)), 1);
2038 z = (temp & (extension & 0xff)) == 0;
2039 temp |= (extension & 0xff);
2040 store_mem ((((insn & 0xffff) << 16) | (extension >> 8)), 1, temp);
2041 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2042 PSW |= (z ? PSW_Z : 0);
05ccbdfd
JL		 2043}
2044
ecb4b5a3 2045/* bset imm8,(d8,an) */
d2523010
JL		 2046void OP_FAF00000 (insn, extension)
2047 unsigned long insn, extension;
05ccbdfd 2048{
ecb4b5a3
JL		 2049 unsigned long temp;
2050 int z;
2051
9f4a551e 2052 temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
ecb4b5a3
JL		 2053 + SEXT8 ((insn & 0xff00) >> 8)), 1);
2054 z = (temp & (insn & 0xff)) == 0;
2055 temp |= (insn & 0xff);
2056 store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
2057 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2058 PSW |= (z ? PSW_Z : 0);
05ccbdfd
JL		 2059}
2060
707641f6 2061/* bclr dm, (an) */
d2523010
JL		 2062void OP_F090 (insn, extension)
2063 unsigned long insn, extension;
05ccbdfd 2064{
707641f6
JL		 2065 unsigned long temp;
2066 int z;
2067
2068 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
9f4a551e
JL		 2069 z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
2070 temp = ~temp & State.regs[REG_D0 + REG1 (insn)];
707641f6
JL		 2071 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
2072 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2073 PSW |= (z ? PSW_Z : 0);
05ccbdfd
JL		 2074}
2075
de0dce7c 2076/* bclr imm8, (abs32) */
d2523010
JL		 2077void OP_FE010000 (insn, extension)
2078 unsigned long insn, extension;
05ccbdfd 2079{
de0dce7c
JL		 2080 unsigned long temp;
2081 int z;
2082
2083 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
2084 z = (temp & (extension & 0xff)) == 0;
2085 temp = ~temp & (extension & 0xff);
2086 store_mem (((insn & 0xffff) << 16) | (extension >> 8), 1, temp);
2087 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2088 PSW |= (z ? PSW_Z : 0);
05ccbdfd
JL		 2089}
2090
ecb4b5a3 2091/* bclr imm8,(d8,an) */
d2523010
JL		 2092void OP_FAF40000 (insn, extension)
2093 unsigned long insn, extension;
05ccbdfd 2094{
ecb4b5a3
JL		 2095 unsigned long temp;
2096 int z;
2097
9f4a551e 2098 temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
ecb4b5a3
JL		 2099 + SEXT8 ((insn & 0xff00) >> 8)), 1);
2100 z = (temp & (insn & 0xff)) == 0;
2101 temp = ~temp & (insn & 0xff);
9f4a551e 2102 store_mem (State.regs[REG_A0 + REG0_16 (insn)], 1, temp);
ecb4b5a3
JL		 2103 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2104 PSW |= (z ? PSW_Z : 0);
05ccbdfd
JL		 2105}
2106
2e35551c 2107/* asr dm, dn */
d2523010
JL		 2108void OP_F2B0 (insn, extension)
2109 unsigned long insn, extension;
05ccbdfd 2110{
707641f6
JL		 2111 long temp;
2112 int z, n, c;
2113
9f4a551e 2114 temp = State.regs[REG_D0 + REG0 (insn)];
707641f6 2115 c = temp & 1;
9f4a551e
JL		 2116 temp >>= State.regs[REG_D0 + REG1 (insn)];
2117 State.regs[REG_D0 + REG0 (insn)] = temp;
2118 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2119 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
707641f6
JL		 2120 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2121 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
05ccbdfd
JL		 2122}
2123
2e35551c 2124/* asr imm8, dn */
d2523010
JL		 2125void OP_F8C800 (insn, extension)
2126 unsigned long insn, extension;
05ccbdfd 2127{
2e35551c
JL		 2128 long temp;
2129 int z, n, c;
2130
9f4a551e 2131 temp = State.regs[REG_D0 + REG0_8 (insn)];
2e35551c
JL		 2132 c = temp & 1;
2133 temp >>= (insn & 0xff);
9f4a551e
JL		 2134 State.regs[REG_D0 + REG0_8 (insn)] = temp;
2135 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
2136 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
2e35551c
JL		 2137 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2138 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
05ccbdfd
JL		 2139}
2140
2e35551c 2141/* lsr dm, dn */
d2523010
JL		 2142void OP_F2A0 (insn, extension)
2143 unsigned long insn, extension;
05ccbdfd 2144{
707641f6
JL		 2145 int z, n, c;
2146
9f4a551e
JL		 2147 c = State.regs[REG_D0 + REG0 (insn)] & 1;
2148 State.regs[REG_D0 + REG0 (insn)]
2149 >>= State.regs[REG_D0 + REG1 (insn)];
2150 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2151 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
707641f6
JL		 2152 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2153 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
05ccbdfd
JL		 2154}
2155
2e35551c 2156/* lsr dm, dn */
d2523010
JL		 2157void OP_F8C400 (insn, extension)
2158 unsigned long insn, extension;
05ccbdfd 2159{
2e35551c
JL		 2160 int z, n, c;
2161
9f4a551e
JL		 2162 c = State.regs[REG_D0 + REG0_8 (insn)] & 1;
2163 State.regs[REG_D0 + REG0_8 (insn)] >>= (insn & 0xff);
2164 z = (State.regs[REG_D0 + (REG0 (insn) >> 8)] == 0);
2165 n = (State.regs[REG_D0 + (REG0 (insn) >> 8)] & 0x80000000) != 0;
2e35551c
JL		 2166 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2167 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
05ccbdfd
JL		 2168}
2169
2e35551c 2170/* asl dm, dn */
d2523010
JL		 2171void OP_F290 (insn, extension)
2172 unsigned long insn, extension;
05ccbdfd 2173{
707641f6
JL		 2174 int n, z;
2175
9f4a551e
JL		 2176 State.regs[REG_D0 + REG0 (insn)]
2177 <<= State.regs[REG_D0 + REG1 (insn)];
2178 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2179 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
707641f6
JL		 2180 PSW &= ~(PSW_Z | PSW_N);
2181 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 2182}
2183
2e35551c 2184/* asl imm8, dn */
d2523010
JL		 2185void OP_F8C000 (insn, extension)
2186 unsigned long insn, extension;
05ccbdfd 2187{
2e35551c
JL		 2188 int n, z;
2189
9f4a551e
JL		 2190 State.regs[REG_D0 + REG0_8 (insn)] <<= (insn & 0xff);
2191 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
2192 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
2e35551c
JL		 2193 PSW &= ~(PSW_Z | PSW_N);
2194 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 2195}
2196
707641f6 2197/* asl2 dn */
d2523010
JL		 2198void OP_54 (insn, extension)
2199 unsigned long insn, extension;
05ccbdfd 2200{
707641f6
JL		 2201 int n, z;
2202
9f4a551e
JL		 2203 State.regs[REG_D0 + REG0 (insn)] <<= 2;
2204 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2205 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
707641f6
JL		 2206 PSW &= ~(PSW_Z | PSW_N);
2207 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 2208}
2209
707641f6 2210/* ror dn */
d2523010
JL		 2211void OP_F284 (insn, extension)
2212 unsigned long insn, extension;
05ccbdfd 2213{
707641f6
JL		 2214 unsigned long value;
2215 int c,n,z;
2216
9f4a551e 2217 value = State.regs[REG_D0 + REG0 (insn)];
7c52bf32 2218 c = (value & 0x1);
707641f6
JL		 2219
2220 value >>= 1;
2221 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
9f4a551e 2222 State.regs[REG_D0 + REG0 (insn)] = value;
707641f6 2223 z = (value == 0);
b7b89deb 2224 n = (value & 0x80000000) != 0;
707641f6
JL		 2225 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2226 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
05ccbdfd
JL		 2227}
2228
707641f6 2229/* rol dn */
d2523010
JL		 2230void OP_F280 (insn, extension)
2231 unsigned long insn, extension;
05ccbdfd 2232{
707641f6
JL		 2233 unsigned long value;
2234 int c,n,z;
2235
9f4a551e 2236 value = State.regs[REG_D0 + REG0 (insn)];
7c52bf32 2237 c = (value & 0x80000000) ? 1 : 0;
707641f6
JL		 2238
2239 value <<= 1;
2240 value |= ((PSW & PSW_C) != 0);
9f4a551e 2241 State.regs[REG_D0 + REG0 (insn)] = value;
707641f6 2242 z = (value == 0);
b7b89deb 2243 n = (value & 0x80000000) != 0;
707641f6
JL		 2244 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2245 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
05ccbdfd
JL		 2246}
2247
f5f13c1d 2248/* beq label:8 */
d2523010
JL		 2249void OP_C800 (insn, extension)
2250 unsigned long insn, extension;
05ccbdfd 2251{
73e65298
JL		 2252 /* The dispatching code will add 2 after we return, so
2253 we subtract two here to make things right. */
2254 if (PSW & PSW_Z)
2255 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2256}
2257
f5f13c1d 2258/* bne label:8 */
d2523010
JL		 2259void OP_C900 (insn, extension)
2260 unsigned long insn, extension;
05ccbdfd 2261{
73e65298
JL		 2262 /* The dispatching code will add 2 after we return, so
2263 we subtract two here to make things right. */
2264 if (!(PSW & PSW_Z))
2265 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2266}
2267
f5f13c1d 2268/* bgt label:8 */
d2523010
JL		 2269void OP_C100 (insn, extension)
2270 unsigned long insn, extension;
05ccbdfd 2271{
f5f13c1d
JL		 2272 /* The dispatching code will add 2 after we return, so
2273 we subtract two here to make things right. */
2274 if (!((PSW & PSW_Z)
7c52bf32 2275 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
f5f13c1d 2276 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2277}
2278
f5f13c1d 2279/* bge label:8 */
d2523010
JL		 2280void OP_C200 (insn, extension)
2281 unsigned long insn, extension;
05ccbdfd 2282{
f5f13c1d
JL		 2283 /* The dispatching code will add 2 after we return, so
2284 we subtract two here to make things right. */
7c52bf32 2285 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
f5f13c1d 2286 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2287}
2288
f5f13c1d 2289/* ble label:8 */
d2523010
JL		 2290void OP_C300 (insn, extension)
2291 unsigned long insn, extension;
05ccbdfd 2292{
f5f13c1d
JL		 2293 /* The dispatching code will add 2 after we return, so
2294 we subtract two here to make things right. */
2295 if ((PSW & PSW_Z)
7c52bf32 2296 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
f5f13c1d 2297 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2298}
2299
f5f13c1d 2300/* blt label:8 */
d2523010
JL		 2301void OP_C000 (insn, extension)
2302 unsigned long insn, extension;
05ccbdfd 2303{
f5f13c1d
JL		 2304 /* The dispatching code will add 2 after we return, so
2305 we subtract two here to make things right. */
7c52bf32 2306 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
f5f13c1d 2307 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2308}
2309
f5f13c1d 2310/* bhi label:8 */
d2523010
JL		 2311void OP_C500 (insn, extension)
2312 unsigned long insn, extension;
05ccbdfd 2313{
f5f13c1d
JL		 2314 /* The dispatching code will add 2 after we return, so
2315 we subtract two here to make things right. */
2316 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2317 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2318}
2319
f5f13c1d 2320/* bcc label:8 */
d2523010
JL		 2321void OP_C600 (insn, extension)
2322 unsigned long insn, extension;
05ccbdfd 2323{
f5f13c1d
JL		 2324 /* The dispatching code will add 2 after we return, so
2325 we subtract two here to make things right. */
2326 if (!(PSW & PSW_C))
2327 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2328}
2329
f5f13c1d 2330/* bls label:8 */
d2523010
JL		 2331void OP_C700 (insn, extension)
2332 unsigned long insn, extension;
05ccbdfd 2333{
f5f13c1d
JL		 2334 /* The dispatching code will add 2 after we return, so
2335 we subtract two here to make things right. */
2336 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2337 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2338}
2339
f5f13c1d 2340/* bcs label:8 */
d2523010
JL		 2341void OP_C400 (insn, extension)
2342 unsigned long insn, extension;
05ccbdfd 2343{
f5f13c1d
JL		 2344 /* The dispatching code will add 2 after we return, so
2345 we subtract two here to make things right. */
2346 if (PSW & PSW_C)
2347 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2348}
2349
f5f13c1d 2350/* bvc label:8 */
d2523010
JL		 2351void OP_F8E800 (insn, extension)
2352 unsigned long insn, extension;
05ccbdfd 2353{
f5f13c1d
JL		 2354 /* The dispatching code will add 3 after we return, so
2355 we subtract two here to make things right. */
2356 if (!(PSW & PSW_V))
2357 State.pc += SEXT8 (insn & 0xff) - 3;
05ccbdfd
JL		 2358}
2359
f5f13c1d 2360/* bvs label:8 */
d2523010
JL		 2361void OP_F8E900 (insn, extension)
2362 unsigned long insn, extension;
05ccbdfd 2363{
f5f13c1d
JL		 2364 /* The dispatching code will add 3 after we return, so
2365 we subtract two here to make things right. */
2366 if (PSW & PSW_V)
2367 State.pc += SEXT8 (insn & 0xff) - 3;
05ccbdfd
JL		 2368}
2369
f5f13c1d 2370/* bnc label:8 */
d2523010
JL		 2371void OP_F8EA00 (insn, extension)
2372 unsigned long insn, extension;
05ccbdfd 2373{
f5f13c1d
JL		 2374 /* The dispatching code will add 3 after we return, so
2375 we subtract two here to make things right. */
2376 if (!(PSW & PSW_N))
2377 State.pc += SEXT8 (insn & 0xff) - 3;
05ccbdfd
JL		 2378}
2379
f5f13c1d 2380/* bns label:8 */
d2523010
JL		 2381void OP_F8EB00 (insn, extension)
2382 unsigned long insn, extension;
05ccbdfd 2383{
f5f13c1d
JL		 2384 /* The dispatching code will add 3 after we return, so
2385 we subtract two here to make things right. */
2386 if (PSW & PSW_N)
2387 State.pc += SEXT8 (insn & 0xff) - 3;
05ccbdfd
JL		 2388}
2389
f5f13c1d 2390/* bra label:8 */
d2523010
JL		 2391void OP_CA00 (insn, extension)
2392 unsigned long insn, extension;
05ccbdfd 2393{
f5f13c1d
JL		 2394 /* The dispatching code will add 2 after we return, so
2395 we subtract two here to make things right. */
2396 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2397}
2398
2399/* leq */
d2523010
JL		 2400void OP_D8 (insn, extension)
2401 unsigned long insn, extension;
05ccbdfd 2402{
f5f13c1d 2403 abort ();
05ccbdfd
JL		 2404}
2405
2406/* lne */
d2523010
JL		 2407void OP_D9 (insn, extension)
2408 unsigned long insn, extension;
05ccbdfd 2409{
f5f13c1d 2410 abort ();
05ccbdfd
JL		 2411}
2412
2413/* lgt */
d2523010
JL		 2414void OP_D1 (insn, extension)
2415 unsigned long insn, extension;
05ccbdfd 2416{
f5f13c1d 2417 abort ();
05ccbdfd
JL		 2418}
2419
2420/* lge */
d2523010
JL		 2421void OP_D2 (insn, extension)
2422 unsigned long insn, extension;
05ccbdfd 2423{
f5f13c1d 2424 abort ();
05ccbdfd
JL		 2425}
2426
2427/* lle */
d2523010
JL		 2428void OP_D3 (insn, extension)
2429 unsigned long insn, extension;
05ccbdfd 2430{
f5f13c1d 2431 abort ();
05ccbdfd
JL		 2432}
2433
2434/* llt */
d2523010
JL		 2435void OP_D0 (insn, extension)
2436 unsigned long insn, extension;
05ccbdfd 2437{
f5f13c1d 2438 abort ();
05ccbdfd
JL		 2439}
2440
2441/* lhi */
d2523010
JL		 2442void OP_D5 (insn, extension)
2443 unsigned long insn, extension;
05ccbdfd 2444{
f5f13c1d 2445 abort ();
05ccbdfd
JL		 2446}
2447
2448/* lcc */
d2523010
JL		 2449void OP_D6 (insn, extension)
2450 unsigned long insn, extension;
05ccbdfd 2451{
f5f13c1d 2452 abort ();
05ccbdfd
JL		 2453}
2454
2455/* lls */
d2523010
JL		 2456void OP_D7 (insn, extension)
2457 unsigned long insn, extension;
05ccbdfd 2458{
f5f13c1d 2459 abort ();
05ccbdfd
JL		 2460}
2461
2462/* lcs */
d2523010
JL		 2463void OP_D4 (insn, extension)
2464 unsigned long insn, extension;
05ccbdfd 2465{
f5f13c1d 2466 abort ();
05ccbdfd
JL		 2467}
2468
2469/* lra */
d2523010
JL		 2470void OP_DA (insn, extension)
2471 unsigned long insn, extension;
05ccbdfd 2472{
f5f13c1d 2473 abort ();
05ccbdfd
JL		 2474}
2475
2476/* setlb */
d2523010
JL		 2477void OP_DB (insn, extension)
2478 unsigned long insn, extension;
05ccbdfd 2479{
f5f13c1d 2480 abort ();
05ccbdfd
JL		 2481}
2482
707641f6 2483/* jmp (an) */
d2523010
JL		 2484void OP_F0F4 (insn, extension)
2485 unsigned long insn, extension;
05ccbdfd 2486{
9f4a551e 2487 State.pc = State.regs[REG_A0 + REG0 (insn)] - 2;
05ccbdfd
JL		 2488}
2489
707641f6 2490/* jmp label:16 */
d2523010
JL		 2491void OP_CC0000 (insn, extension)
2492 unsigned long insn, extension;
05ccbdfd 2493{
92284aaa 2494 State.pc += SEXT16 (insn & 0xffff) - 3;
05ccbdfd
JL		 2495}
2496
707641f6 2497/* jmp label:32 */
d2523010
JL		 2498void OP_DC000000 (insn, extension)
2499 unsigned long insn, extension;
05ccbdfd 2500{
7c52bf32 2501 State.pc += (((insn & 0xffffff) << 8) + extension) - 5;
05ccbdfd
JL		 2502}
2503
707641f6 2504/* call label:16,reg_list,imm8 */
d2523010
JL		 2505void OP_CD000000 (insn, extension)
2506 unsigned long insn, extension;
05ccbdfd 2507{
707641f6
JL		 2508 unsigned int next_pc, sp, adjust;
2509 unsigned long mask;
2510
2511 sp = State.regs[REG_SP];
2512 next_pc = State.pc + 2;
2513 State.mem[sp] = next_pc & 0xff;
3bb3fe44
JL		 2514 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2515 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2516 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
707641f6
JL		 2517
2518 mask = insn & 0xff;
2519
2520 adjust = 0;
2521 if (mask & 0x80)
2522 {
2523 adjust -= 4;
2524 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2525 }
2526
2527 if (mask & 0x40)
2528 {
2529 adjust -= 4;
2530 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2531 }
2532
2533 if (mask & 0x20)
2534 {
2535 adjust -= 4;
2536 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2537 }
2538
2539 if (mask & 0x10)
2540 {
2541 adjust -= 4;
2542 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2543 }
2544
2545 if (mask & 0x8)
2546 {
2547 adjust -= 4;
2548 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2549 adjust -= 4;
2550 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2551 adjust -= 4;
2552 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2553 adjust -= 4;
2554 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2555 adjust -= 4;
2556 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2557 adjust -= 4;
2558 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2559 adjust -= 4;
2560 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2561 adjust -= 4;
2562 }
2563
2564 /* And make sure to update the stack pointer. */
2565 State.regs[REG_SP] -= extension;
2566 State.regs[REG_MDR] = next_pc;
2567 State.pc += SEXT16 ((insn & 0xffff00) >> 8) - 5;
05ccbdfd
JL		 2568}
2569
707641f6 2570/* call label:32,reg_list,imm8*/
d2523010
JL		 2571void OP_DD000000 (insn, extension)
2572 unsigned long insn, extension;
05ccbdfd 2573{
707641f6
JL		 2574 unsigned int next_pc, sp, adjust;
2575 unsigned long mask;
2576
2577 sp = State.regs[REG_SP];
2578 next_pc = State.pc + 2;
2579 State.mem[sp] = next_pc & 0xff;
3bb3fe44
JL		 2580 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2581 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2582 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
707641f6
JL		 2583
2584 mask = (extension & 0xff00) >> 8;
2585
2586 adjust = 0;
2587 if (mask & 0x80)
2588 {
2589 adjust -= 4;
2590 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2591 }
2592
2593 if (mask & 0x40)
2594 {
2595 adjust -= 4;
2596 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2597 }
2598
2599 if (mask & 0x20)
2600 {
2601 adjust -= 4;
2602 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2603 }
2604
2605 if (mask & 0x10)
2606 {
2607 adjust -= 4;
2608 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2609 }
2610
2611 if (mask & 0x8)
2612 {
2613 adjust -= 4;
2614 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2615 adjust -= 4;
2616 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2617 adjust -= 4;
2618 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2619 adjust -= 4;
2620 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2621 adjust -= 4;
2622 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2623 adjust -= 4;
2624 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2625 adjust -= 4;
2626 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2627 adjust -= 4;
2628 }
2629
2630 /* And make sure to update the stack pointer. */
2631 State.regs[REG_SP] -= (extension & 0xff);
2632 State.regs[REG_MDR] = next_pc;
2633 State.pc += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
05ccbdfd
JL		 2634}
2635
707641f6 2636/* calls (an) */
d2523010
JL		 2637void OP_F0F0 (insn, extension)
2638 unsigned long insn, extension;
05ccbdfd 2639{
92284aaa
JL		 2640 unsigned int next_pc, sp;
2641
2642 sp = State.regs[REG_SP];
2643 next_pc = State.pc + 2;
2644 State.mem[sp] = next_pc & 0xff;
3bb3fe44
JL		 2645 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2646 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2647 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
92284aaa 2648 State.regs[REG_MDR] = next_pc;
9f4a551e 2649 State.pc = State.regs[REG_A0 + REG0 (insn)] - 2;
05ccbdfd
JL		 2650}
2651
707641f6 2652/* calls label:16 */
d2523010
JL		 2653void OP_FAFF0000 (insn, extension)
2654 unsigned long insn, extension;
05ccbdfd 2655{
92284aaa
JL		 2656 unsigned int next_pc, sp;
2657
2658 sp = State.regs[REG_SP];
2659 next_pc = State.pc + 4;
2660 State.mem[sp] = next_pc & 0xff;
3bb3fe44
JL		 2661 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2662 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2663 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
92284aaa
JL		 2664 State.regs[REG_MDR] = next_pc;
2665 State.pc += SEXT16 (insn & 0xffff) - 4;
05ccbdfd
JL		 2666}
2667
707641f6 2668/* calls label:32 */
d2523010
JL		 2669void OP_FCFF0000 (insn, extension)
2670 unsigned long insn, extension;
05ccbdfd 2671{
92284aaa
JL		 2672 unsigned int next_pc, sp;
2673
2674 sp = State.regs[REG_SP];
2675 next_pc = State.pc + 6;
2676 State.mem[sp] = next_pc & 0xff;
3bb3fe44
JL		 2677 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2678 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2679 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
92284aaa 2680 State.regs[REG_MDR] = next_pc;
7c52bf32 2681 State.pc += (((insn & 0xffff) << 16) + extension) - 6;
05ccbdfd
JL		 2682}
2683
de0dce7c 2684/* ret reg_list, imm8 */
d2523010
JL		 2685void OP_DF0000 (insn, extension)
2686 unsigned long insn, extension;
05ccbdfd 2687{
707641f6
JL		 2688 unsigned int sp;
2689 unsigned long mask;
2690
2691 State.regs[REG_SP] += insn & 0xff;
2692 State.pc = State.regs[REG_MDR] - 3;
2693 sp = State.regs[REG_SP];
2694
2695 mask = (insn & 0xff00) >> 8;
2696
2697 if (mask & 0x8)
2698 {
2699 sp += 4;
2700 State.regs[REG_LAR] = load_mem (sp, 4);
2701 sp += 4;
2702 State.regs[REG_LIR] = load_mem (sp, 4);
2703 sp += 4;
2704 State.regs[REG_MDR] = load_mem (sp, 4);
2705 sp += 4;
2706 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2707 sp += 4;
2708 State.regs[REG_A0] = load_mem (sp, 4);
2709 sp += 4;
2710 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2711 sp += 4;
2712 State.regs[REG_D0] = load_mem (sp, 4);
2713 sp += 4;
2714 }
2715
2716 if (mask & 0x10)
2717 {
2718 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2719 sp += 4;
2720 }
2721
2722 if (mask & 0x20)
2723 {
2724 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2725 sp += 4;
2726 }
2727
2728 if (mask & 0x40)
2729 {
2730 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2731 sp += 4;
2732 }
2733
2734 if (mask & 0x80)
2735 {
2736 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2737 sp += 4;
2738 }
05ccbdfd
JL		 2739}
2740
707641f6 2741/* retf reg_list,imm8 */
d2523010
JL		 2742void OP_DE0000 (insn, extension)
2743 unsigned long insn, extension;
05ccbdfd 2744{
707641f6
JL		 2745 unsigned int sp;
2746 unsigned long mask;
2747
7c52bf32
JL		 2748 sp = State.regs[REG_SP] + (insn & 0xff);
2749 State.regs[REG_SP] = sp;
707641f6
JL		 2750 State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2751 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2752 State.pc -= 3;
2753
2754 sp = State.regs[REG_SP];
2755
2756 mask = (insn & 0xff00) >> 8;
2757
2758 if (mask & 0x8)
2759 {
2760 sp += 4;
2761 State.regs[REG_LAR] = load_mem (sp, 4);
2762 sp += 4;
2763 State.regs[REG_LIR] = load_mem (sp, 4);
2764 sp += 4;
2765 State.regs[REG_MDR] = load_mem (sp, 4);
2766 sp += 4;
2767 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2768 sp += 4;
2769 State.regs[REG_A0] = load_mem (sp, 4);
2770 sp += 4;
2771 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2772 sp += 4;
2773 State.regs[REG_D0] = load_mem (sp, 4);
2774 sp += 4;
2775 }
2776
2777 if (mask & 0x10)
2778 {
2779 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2780 sp += 4;
2781 }
2782
2783 if (mask & 0x20)
2784 {
2785 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2786 sp += 4;
2787 }
2788
2789 if (mask & 0x40)
2790 {
2791 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2792 sp += 4;
2793 }
2794
2795 if (mask & 0x80)
2796 {
2797 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2798 sp += 4;
2799 }
05ccbdfd
JL		 2800}
2801
2802/* rets */
d2523010
JL		 2803void OP_F0FC (insn, extension)
2804 unsigned long insn, extension;
05ccbdfd 2805{
92284aaa
JL		 2806 unsigned int sp;
2807
2808 sp = State.regs[REG_SP];
2809 State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2810 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2811 State.pc -= 2;
05ccbdfd
JL		 2812}
2813
2814/* rti */
d2523010
JL		 2815void OP_F0FD (insn, extension)
2816 unsigned long insn, extension;
05ccbdfd 2817{
f5f13c1d 2818 abort ();
05ccbdfd
JL		 2819}
2820
2821/* trap */
d2523010
JL		 2822void OP_F0FE (insn, extension)
2823 unsigned long insn, extension;
05ccbdfd 2824{
3bb3fe44
JL		 2825 /* We use this for simulated system calls; we may need to change
2826 it to a reserved instruction if we conflict with uses at
2827 Matsushita. */
2828 int save_errno = errno;
2829 errno = 0;
2830
2831/* Registers passed to trap 0 */
2832
2833/* Function number. */
2834#define FUNC (load_mem (State.regs[REG_SP] + 4, 4))
2835
2836/* Parameters. */
2837#define PARM1 (load_mem (State.regs[REG_SP] + 8, 4))
2838#define PARM2 (load_mem (State.regs[REG_SP] + 12, 4))
2839#define PARM3 (load_mem (State.regs[REG_SP] + 16, 4))
2840
2841/* Registers set by trap 0 */
2842
2843#define RETVAL State.regs[0] /* return value */
2844#define RETERR State.regs[1] /* return error code */
2845
2846/* Turn a pointer in a register into a pointer into real memory. */
2847
2848#define MEMPTR(x) (State.mem + x)
2849
2850 switch (FUNC)
2851 {
2852#if !defined(__GO32__) && !defined(_WIN32)
2853 case SYS_fork:
2854 RETVAL = fork ();
2855 break;
2856 case SYS_execve:
2857 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2858 (char **)MEMPTR (PARM3));
2859 break;
2860 case SYS_execv:
2861 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2862 break;
2863#endif
2864
2865 case SYS_read:
2866 RETVAL = mn10300_callback->read (mn10300_callback, PARM1,
2867 MEMPTR (PARM2), PARM3);
2868 break;
2869 case SYS_write:
2870 if (PARM1 == 1)
2871 RETVAL = (int)mn10300_callback->write_stdout (mn10300_callback,
2872 MEMPTR (PARM2), PARM3);
2873 else
2874 RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1,
2875 MEMPTR (PARM2), PARM3);
2876 break;
2877 case SYS_lseek:
2878 RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3);
2879 break;
2880 case SYS_close:
2881 RETVAL = mn10300_callback->close (mn10300_callback, PARM1);
2882 break;
2883 case SYS_open:
2884 RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2);
2885 break;
2886 case SYS_exit:
2887 /* EXIT - caller can look in PARM1 to work out the
2888 reason */
2889 if (PARM1 == 0xdead || PARM1 == 0x1)
2890 State.exception = SIGABRT;
2891 else
2892 State.exception = SIGQUIT;
2893 break;
2894
2895 case SYS_stat: /* added at hmsi */
2896 /* stat system call */
2897 {
2898 struct stat host_stat;
2899 reg_t buf;
2900
2901 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2902
2903 buf = PARM2;
2904
2905 /* Just wild-assed guesses. */
2906 store_mem (buf, 2, host_stat.st_dev);
2907 store_mem (buf + 2, 2, host_stat.st_ino);
2908 store_mem (buf + 4, 4, host_stat.st_mode);
2909 store_mem (buf + 8, 2, host_stat.st_nlink);
2910 store_mem (buf + 10, 2, host_stat.st_uid);
2911 store_mem (buf + 12, 2, host_stat.st_gid);
2912 store_mem (buf + 14, 2, host_stat.st_rdev);
2913 store_mem (buf + 16, 4, host_stat.st_size);
2914 store_mem (buf + 20, 4, host_stat.st_atime);
2915 store_mem (buf + 28, 4, host_stat.st_mtime);
2916 store_mem (buf + 36, 4, host_stat.st_ctime);
2917 }
2918 break;
2919
2920 case SYS_chown:
2921 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2922 break;
2923 case SYS_chmod:
2924 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2925 break;
2926 case SYS_time:
2927 RETVAL = time (MEMPTR (PARM1));
2928 break;
2929 case SYS_times:
2930 {
2931 struct tms tms;
2932 RETVAL = times (&tms);
2933 store_mem (PARM1, 4, tms.tms_utime);
2934 store_mem (PARM1 + 4, 4, tms.tms_stime);
2935 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2936 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2937 break;
2938 }
2939 case SYS_gettimeofday:
2940 {
2941 struct timeval t;
2942 struct timezone tz;
2943 RETVAL = gettimeofday (&t, &tz);
2944 store_mem (PARM1, 4, t.tv_sec);
2945 store_mem (PARM1 + 4, 4, t.tv_usec);
2946 store_mem (PARM2, 4, tz.tz_minuteswest);
2947 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2948 break;
2949 }
2950 case SYS_utime:
2951 /* Cast the second argument to void *, to avoid type mismatch
2952 if a prototype is present. */
2953 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2954 break;
2955 default:
2956 abort ();
2957 }
2958 RETERR = errno;
2959 errno = save_errno;
05ccbdfd
JL		 2960}
2961
2962/* rtm */
d2523010
JL		 2963void OP_F0FF (insn, extension)
2964 unsigned long insn, extension;
05ccbdfd 2965{
f5f13c1d 2966 abort ();
05ccbdfd
JL		 2967}
2968
2969/* nop */
d2523010
JL		 2970void OP_CB (insn, extension)
2971 unsigned long insn, extension;
05ccbdfd
JL		 2972{
2973}
2974
2975/* putx */
d2523010
JL		 2976void OP_F500 (insn, extension)
2977 unsigned long insn, extension;
05ccbdfd 2978{
5084d8e5 2979 abort ();
05ccbdfd
JL		 2980}
2981
2982/* getx */
d2523010
JL		 2983void OP_F6F0 (insn, extension)
2984 unsigned long insn, extension;
05ccbdfd 2985{
5084d8e5 2986 abort ();
05ccbdfd
JL		 2987}
2988
2989/* mulq */
d2523010
JL		 2990void OP_F600 (insn, extension)
2991 unsigned long insn, extension;
05ccbdfd 2992{
5084d8e5 2993 abort ();
05ccbdfd
JL		 2994}
2995
2996/* mulq */
d2523010
JL		 2997void OP_F90000 (insn, extension)
2998 unsigned long insn, extension;
05ccbdfd 2999{
5084d8e5 3000 abort ();
05ccbdfd
JL		 3001}
3002
3003/* mulq */
d2523010
JL		 3004void OP_FB000000 (insn, extension)
3005 unsigned long insn, extension;
05ccbdfd 3006{
5084d8e5 3007 abort ();
05ccbdfd
JL		 3008}
3009
3010/* mulq */
d2523010
JL		 3011void OP_FD000000 (insn, extension)
3012 unsigned long insn, extension;
05ccbdfd 3013{
5084d8e5 3014 abort ();
05ccbdfd
JL		 3015}
3016
3017/* mulqu */
d2523010
JL		 3018void OP_F610 (insn, extension)
3019 unsigned long insn, extension;
05ccbdfd 3020{
5084d8e5 3021 abort ();
05ccbdfd
JL		 3022}
3023
3024/* mulqu */
d2523010
JL		 3025void OP_F91400 (insn, extension)
3026 unsigned long insn, extension;
05ccbdfd 3027{
5084d8e5 3028 abort ();
05ccbdfd
JL		 3029}
3030
3031/* mulqu */
d2523010
JL		 3032void OP_FB140000 (insn, extension)
3033 unsigned long insn, extension;
05ccbdfd 3034{
5084d8e5 3035 abort ();
05ccbdfd
JL		 3036}
3037
3038/* mulqu */
d2523010
JL		 3039void OP_FD140000 (insn, extension)
3040 unsigned long insn, extension;
05ccbdfd 3041{
5084d8e5 3042 abort ();
05ccbdfd
JL		 3043}
3044
3045/* sat16 */
d2523010
JL		 3046void OP_F640 (insn, extension)
3047 unsigned long insn, extension;
05ccbdfd 3048{
5084d8e5 3049 abort ();
05ccbdfd
JL		 3050}
3051
3052/* sat24 */
d2523010
JL		 3053void OP_F650 (insn, extension)
3054 unsigned long insn, extension;
05ccbdfd 3055{
5084d8e5 3056 abort ();
05ccbdfd
JL		 3057}
3058
3059/* bsch */
d2523010
JL		 3060void OP_F670 (insn, extension)
3061 unsigned long insn, extension;
05ccbdfd 3062{
5084d8e5 3063 abort ();
05ccbdfd 3064}
GDB Binutils - Deliverables
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