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3346cfda NC |
1 | /* Simulator for TI MSP430 and MSP430X |
2 | ||
ecd75fc8 | 3 | Copyright (C) 2013-2014 Free Software Foundation, Inc. |
3346cfda NC |
4 | Contributed by Red Hat. |
5 | Based on sim/bfin/bfin-sim.c which was contributed by Analog Devices, Inc. | |
6 | ||
7 | This file is part of simulators. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #include "config.h" | |
23 | #include <stdio.h> | |
24 | #include <stdlib.h> | |
25 | #include <string.h> | |
26 | #include <inttypes.h> | |
27 | #include <assert.h> | |
28 | #include "bfd.h" | |
29 | #include "opcode/msp430-decode.h" | |
30 | #include "sim-main.h" | |
31 | #include "dis-asm.h" | |
32 | #include "targ-vals.h" | |
33 | ||
34 | static int | |
35 | loader_write_mem (SIM_DESC sd, | |
36 | SIM_ADDR taddr, | |
37 | const unsigned char *buf, | |
38 | int bytes) | |
39 | { | |
40 | SIM_CPU *cpu = MSP430_CPU (sd); | |
41 | return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); | |
42 | } | |
43 | ||
44 | static sim_cia | |
45 | msp430_pc_fetch (SIM_CPU *cpu) | |
46 | { | |
47 | return cpu->state.regs[0]; | |
48 | } | |
49 | ||
50 | static void | |
51 | msp430_pc_store (SIM_CPU *cpu, sim_cia newpc) | |
52 | { | |
53 | cpu->state.regs[0] = newpc; | |
54 | } | |
55 | ||
56 | static long | |
57 | lookup_symbol (SIM_DESC sd, const char *name) | |
58 | { | |
59 | struct bfd *abfd = STATE_PROG_BFD (sd); | |
60 | asymbol **symbol_table = STATE_SYMBOL_TABLE (sd); | |
61 | long number_of_symbols = STATE_NUM_SYMBOLS (sd); | |
62 | long i; | |
63 | ||
64 | if (symbol_table == NULL) | |
65 | { | |
66 | long storage_needed; | |
67 | ||
68 | storage_needed = bfd_get_symtab_upper_bound (abfd); | |
69 | if (storage_needed <= 0) | |
70 | return -1; | |
71 | ||
72 | STATE_SYMBOL_TABLE (sd) = symbol_table = xmalloc (storage_needed); | |
73 | STATE_NUM_SYMBOLS (sd) = number_of_symbols = | |
74 | bfd_canonicalize_symtab (abfd, symbol_table); | |
75 | } | |
76 | ||
77 | for (i = 0; i < number_of_symbols; i++) | |
78 | if (strcmp (symbol_table[i]->name, name) == 0) | |
79 | { | |
80 | long val = symbol_table[i]->section->vma + symbol_table[i]->value; | |
81 | return val; | |
82 | } | |
83 | return -1; | |
84 | } | |
85 | ||
86 | static int | |
87 | msp430_reg_fetch (SIM_CPU *cpu, int regno, unsigned char *buf, int len) | |
88 | { | |
89 | if (0 <= regno && regno < 16) | |
90 | { | |
91 | if (len == 2) | |
92 | { | |
93 | int val = cpu->state.regs[regno]; | |
94 | buf[0] = val & 0xff; | |
95 | buf[1] = (val >> 8) & 0xff; | |
96 | return 0; | |
97 | } | |
98 | else if (len == 4) | |
99 | { | |
100 | int val = cpu->state.regs[regno]; | |
101 | buf[0] = val & 0xff; | |
102 | buf[1] = (val >> 8) & 0xff; | |
103 | buf[2] = (val >> 16) & 0x0f; /* Registers are only 20 bits wide. */ | |
104 | buf[3] = 0; | |
105 | return 0; | |
106 | } | |
107 | else | |
108 | return -1; | |
109 | } | |
110 | else | |
111 | return -1; | |
112 | } | |
113 | ||
114 | static int | |
115 | msp430_reg_store (SIM_CPU *cpu, int regno, unsigned char *buf, int len) | |
116 | { | |
117 | if (0 <= regno && regno < 16) | |
118 | { | |
119 | if (len == 2) | |
120 | { | |
121 | cpu->state.regs[regno] = (buf[1] << 8) | buf[0]; | |
122 | return len; | |
123 | } | |
124 | ||
125 | if (len == 4) | |
126 | { | |
127 | cpu->state.regs[regno] = ((buf[2] << 16) & 0xf0000) | |
128 | | (buf[1] << 8) | buf[0]; | |
129 | return len; | |
130 | } | |
131 | } | |
132 | ||
133 | return -1; | |
134 | } | |
135 | ||
136 | static inline void | |
137 | msp430_initialize_cpu (SIM_DESC sd, SIM_CPU *cpu) | |
138 | { | |
139 | memset (&cpu->state, 0, sizeof (cpu->state)); | |
140 | } | |
141 | ||
142 | SIM_DESC | |
143 | sim_open (SIM_OPEN_KIND kind, | |
144 | struct host_callback_struct *callback, | |
145 | struct bfd *abfd, | |
146 | char **argv) | |
147 | { | |
148 | SIM_DESC sd = sim_state_alloc (kind, callback); | |
149 | char c; | |
150 | struct bfd *prog_bfd; | |
151 | ||
152 | /* Initialise the simulator. */ | |
153 | ||
154 | if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK) | |
155 | { | |
156 | sim_state_free (sd); | |
157 | return 0; | |
158 | } | |
159 | ||
160 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
161 | { | |
162 | sim_state_free (sd); | |
163 | return 0; | |
164 | } | |
165 | ||
166 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
167 | { | |
168 | sim_state_free (sd); | |
169 | return 0; | |
170 | } | |
171 | ||
172 | CPU_PC_FETCH (MSP430_CPU (sd)) = msp430_pc_fetch; | |
173 | CPU_PC_STORE (MSP430_CPU (sd)) = msp430_pc_store; | |
174 | CPU_REG_FETCH (MSP430_CPU (sd)) = msp430_reg_fetch; | |
175 | CPU_REG_STORE (MSP430_CPU (sd)) = msp430_reg_store; | |
176 | ||
177 | /* Allocate memory if none specified by user. */ | |
8969934d NC |
178 | if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0x130, 1) == 0) |
179 | sim_do_commandf (sd, "memory-region 0,0x20"); | |
3346cfda | 180 | if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0x200, 1) == 0) |
8969934d | 181 | sim_do_commandf (sd, "memory-region 0x200,0xffe00"); |
3346cfda NC |
182 | if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0xfffe, 1) == 0) |
183 | sim_do_commandf (sd, "memory-region 0xfffe,2"); | |
184 | if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0x10000, 1) == 0) | |
185 | sim_do_commandf (sd, "memory-region 0x10000,0x100000"); | |
186 | ||
187 | /* Check for/establish the a reference program image. */ | |
188 | if (sim_analyze_program (sd, | |
189 | (STATE_PROG_ARGV (sd) != NULL | |
190 | ? *STATE_PROG_ARGV (sd) | |
191 | : NULL), abfd) != SIM_RC_OK) | |
192 | { | |
193 | sim_state_free (sd); | |
194 | return 0; | |
195 | } | |
196 | ||
197 | prog_bfd = sim_load_file (sd, argv[0], callback, | |
198 | "the program", | |
199 | STATE_PROG_BFD (sd), | |
200 | 0 /* verbose */, | |
201 | 1 /* use LMA instead of VMA */, | |
202 | loader_write_mem); | |
203 | if (prog_bfd == NULL) | |
204 | { | |
205 | sim_state_free (sd); | |
206 | return 0; | |
207 | } | |
208 | ||
209 | /* Establish any remaining configuration options. */ | |
210 | if (sim_config (sd) != SIM_RC_OK) | |
211 | { | |
212 | sim_state_free (sd); | |
213 | return 0; | |
214 | } | |
215 | ||
216 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
217 | { | |
218 | sim_state_free (sd); | |
219 | return 0; | |
220 | } | |
221 | ||
222 | /* CPU specific initialization. */ | |
223 | assert (MAX_NR_PROCESSORS == 1); | |
224 | msp430_initialize_cpu (sd, MSP430_CPU (sd)); | |
225 | ||
226 | msp430_trace_init (STATE_PROG_BFD (sd)); | |
227 | ||
228 | MSP430_CPU (sd)->state.cio_breakpoint = lookup_symbol (sd, "C$$IO$$"); | |
229 | MSP430_CPU (sd)->state.cio_buffer = lookup_symbol (sd, "__CIOBUF__"); | |
230 | if (MSP430_CPU (sd)->state.cio_buffer == -1) | |
231 | MSP430_CPU (sd)->state.cio_buffer = lookup_symbol (sd, "_CIOBUF_"); | |
232 | ||
233 | return sd; | |
234 | } | |
235 | ||
236 | void | |
237 | sim_close (SIM_DESC sd, | |
238 | int quitting) | |
239 | { | |
240 | free (STATE_SYMBOL_TABLE (sd)); | |
241 | sim_state_free (sd); | |
242 | } | |
243 | ||
244 | SIM_RC | |
245 | sim_create_inferior (SIM_DESC sd, | |
246 | struct bfd *abfd, | |
247 | char **argv, | |
248 | char **env) | |
249 | { | |
250 | unsigned char resetv[2]; | |
251 | int c; | |
252 | int new_pc; | |
253 | ||
7b0278dc | 254 | /* Set the PC to the default reset vector if available. */ |
3346cfda | 255 | c = sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, resetv, 0xfffe, 2); |
3346cfda | 256 | new_pc = resetv[0] + 256 * resetv[1]; |
7b0278dc MF |
257 | |
258 | /* If the reset vector isn't initialized, then use the ELF entry. */ | |
259 | if (abfd != NULL && !new_pc) | |
260 | new_pc = bfd_get_start_address (abfd); | |
261 | ||
3346cfda NC |
262 | sim_pc_set (MSP430_CPU (sd), new_pc); |
263 | msp430_pc_store (MSP430_CPU (sd), new_pc); | |
264 | ||
265 | return SIM_RC_OK; | |
266 | } | |
267 | ||
268 | typedef struct | |
269 | { | |
270 | SIM_DESC sd; | |
271 | int gb_addr; | |
272 | } Get_Byte_Local_Data; | |
273 | ||
274 | static int | |
275 | msp430_getbyte (void *vld) | |
276 | { | |
277 | Get_Byte_Local_Data *ld = (Get_Byte_Local_Data *)vld; | |
278 | char buf[1]; | |
279 | SIM_DESC sd = ld->sd; | |
280 | ||
281 | sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, ld->gb_addr, 1); | |
282 | ld->gb_addr ++; | |
283 | return buf[0]; | |
284 | } | |
285 | ||
286 | #define REG(N) MSP430_CPU (sd)->state.regs[(N)] | |
287 | #define PC REG(MSR_PC) | |
288 | #define SP REG(MSR_SP) | |
289 | #define SR REG(MSR_SR) | |
290 | ||
291 | static const char * | |
292 | register_names[] = | |
293 | { | |
294 | "PC", "SP", "SR", "CG", "R4", "R5", "R6", "R7", "R8", | |
295 | "R9", "R10", "R11", "R12", "R13", "R14", "R15" | |
296 | }; | |
297 | ||
298 | static void | |
299 | trace_reg_put (SIM_DESC sd, int n, unsigned int v) | |
300 | { | |
301 | if (TRACE_VPU_P (MSP430_CPU (sd))) | |
302 | trace_generic (sd, MSP430_CPU (sd), TRACE_VPU_IDX, | |
303 | "PUT: %#x -> %s", v, register_names [n]); | |
304 | REG (n) = v; | |
305 | } | |
306 | ||
307 | static unsigned int | |
308 | trace_reg_get (SIM_DESC sd, int n) | |
309 | { | |
310 | if (TRACE_VPU_P (MSP430_CPU (sd))) | |
311 | trace_generic (sd, MSP430_CPU (sd), TRACE_VPU_IDX, | |
312 | "GET: %s -> %#x", register_names [n], REG (n)); | |
313 | return REG (n); | |
314 | } | |
315 | ||
316 | #define REG_PUT(N,V) trace_reg_put (sd, N, V) | |
317 | #define REG_GET(N) trace_reg_get (sd, N) | |
318 | ||
8969934d NC |
319 | /* Hardware multiply (and accumulate) support. */ |
320 | static enum { UNSIGN_32, SIGN_32, UNSIGN_MAC_32, SIGN_MAC_32 } hwmult_type; | |
321 | static unsigned32 hwmult_op1; | |
322 | static unsigned32 hwmult_op2; | |
323 | static unsigned32 hwmult_result; | |
324 | static signed32 hwmult_signed_result; | |
325 | static unsigned32 hwmult_accumulator; | |
326 | static signed32 hwmult_signed_accumulator; | |
327 | ||
328 | static enum { UNSIGN_64, SIGN_64 } hw32mult_type; | |
329 | static unsigned64 hw32mult_op1; | |
330 | static unsigned64 hw32mult_op2; | |
331 | static unsigned64 hw32mult_result; | |
332 | ||
333 | static unsigned int | |
334 | zero_ext (unsigned int v, unsigned int bits) | |
335 | { | |
336 | v &= ((1 << bits) - 1); | |
337 | return v; | |
338 | } | |
339 | ||
340 | static signed int | |
341 | sign_ext (signed int v, unsigned int bits) | |
342 | { | |
343 | int sb = 1 << (bits-1); /* Sign bit. */ | |
344 | int mb = (1 << (bits-1)) - 1; /* Mantissa bits. */ | |
345 | ||
346 | if (v & sb) | |
347 | v = v | ~mb; | |
348 | else | |
349 | v = v & mb; | |
350 | return v; | |
351 | } | |
352 | ||
3346cfda NC |
353 | static int |
354 | get_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n) | |
355 | { | |
356 | MSP430_Opcode_Operand *op = opc->op + n; | |
357 | int rv; | |
358 | int addr; | |
359 | unsigned char buf[4]; | |
360 | int incval = 0; | |
361 | ||
362 | switch (op->type) | |
363 | { | |
364 | case MSP430_Operand_Immediate: | |
365 | rv = op->addend; | |
366 | break; | |
367 | case MSP430_Operand_Register: | |
368 | rv = REG_GET (op->reg); | |
369 | break; | |
370 | case MSP430_Operand_Indirect: | |
371 | case MSP430_Operand_Indirect_Postinc: | |
372 | addr = op->addend; | |
373 | if (op->reg != MSR_None) | |
374 | { | |
375 | int reg; | |
376 | /* Index values are signed, but the sum is limited to 16 | |
377 | bits if the register < 64k, for MSP430 compatibility in | |
378 | MSP430X chips. */ | |
379 | if (addr & 0x8000) | |
380 | addr |= -1 << 16; | |
381 | reg = REG_GET (op->reg); | |
382 | addr += reg; | |
383 | if (reg < 0x10000 && ! opc->ofs_430x) | |
384 | addr &= 0xffff; | |
385 | } | |
386 | addr &= 0xfffff; | |
387 | switch (opc->size) | |
388 | { | |
389 | case 8: | |
390 | sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, addr, 1); | |
391 | rv = buf[0]; | |
392 | break; | |
393 | case 16: | |
394 | sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, addr, 2); | |
395 | rv = buf[0] | (buf[1] << 8); | |
396 | break; | |
397 | case 20: | |
398 | case 32: | |
399 | sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, addr, 4); | |
400 | rv = buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24); | |
401 | break; | |
402 | default: | |
403 | assert (! opc->size); | |
404 | break; | |
405 | } | |
406 | #if 0 | |
407 | /* Hack - MSP430X5438 serial port status register. */ | |
408 | if (addr == 0x5dd) | |
409 | rv = 2; | |
410 | #endif | |
8969934d NC |
411 | if (addr >= 0x130 && addr <= 0x15B) |
412 | { | |
413 | switch (addr) | |
414 | { | |
415 | case 0x13A: | |
416 | rv = zero_ext (hwmult_result, 16); | |
417 | break; | |
418 | ||
419 | case 0x13C: | |
420 | switch (hwmult_type) | |
421 | { | |
422 | case UNSIGN_32: | |
423 | rv = zero_ext (hwmult_result >> 16, 16); | |
424 | break; | |
425 | ||
426 | case SIGN_32: | |
427 | rv = sign_ext (hwmult_signed_result >> 16, 16); | |
428 | break; | |
429 | } | |
430 | break; | |
431 | ||
432 | case 0x13E: | |
433 | switch (hwmult_type) | |
434 | { | |
435 | case UNSIGN_32: | |
436 | rv = 0; | |
437 | break; | |
438 | case SIGN_32: | |
439 | rv = hwmult_signed_result < 0 ? -1 : 0; | |
440 | break; | |
441 | case UNSIGN_MAC_32: | |
442 | rv = 0; /* FIXME: Should be carry of last accumulate. */ | |
443 | break; | |
444 | case SIGN_MAC_32: | |
445 | rv = hwmult_signed_accumulator < 0 ? -1 : 0; | |
446 | break; | |
447 | } | |
448 | break; | |
449 | ||
450 | case 0x154: | |
451 | rv = zero_ext (hw32mult_result, 16); | |
452 | break; | |
453 | ||
454 | case 0x156: | |
455 | rv = zero_ext (hw32mult_result >> 16, 16); | |
456 | break; | |
457 | ||
458 | case 0x158: | |
459 | rv = zero_ext (hw32mult_result >> 32, 16); | |
460 | break; | |
461 | ||
462 | case 0x15A: | |
463 | switch (hw32mult_type) | |
464 | { | |
465 | case UNSIGN_64: rv = zero_ext (hw32mult_result >> 48, 16); break; | |
466 | case SIGN_64: rv = sign_ext (hw32mult_result >> 48, 16); break; | |
467 | } | |
468 | break; | |
469 | ||
470 | default: | |
471 | fprintf (stderr, "unimplemented HW MULT read!\n"); | |
472 | break; | |
473 | } | |
474 | } | |
475 | ||
3346cfda NC |
476 | if (TRACE_MEMORY_P (MSP430_CPU (sd))) |
477 | trace_generic (sd, MSP430_CPU (sd), TRACE_MEMORY_IDX, | |
478 | "GET: [%#x].%d -> %#x", addr, opc->size, rv); | |
479 | break; | |
480 | default: | |
481 | fprintf (stderr, "invalid operand %d type %d\n", n, op->type); | |
482 | abort (); | |
483 | } | |
484 | ||
485 | switch (opc->size) | |
486 | { | |
487 | case 8: | |
488 | rv &= 0xff; | |
489 | incval = 1; | |
490 | break; | |
491 | case 16: | |
492 | rv &= 0xffff; | |
493 | incval = 2; | |
494 | break; | |
495 | case 20: | |
496 | rv &= 0xfffff; | |
497 | incval = 4; | |
498 | break; | |
499 | case 32: | |
500 | rv &= 0xffffffff; | |
501 | incval = 4; | |
502 | break; | |
503 | } | |
504 | ||
505 | if (op->type == MSP430_Operand_Indirect_Postinc) | |
506 | REG_PUT (op->reg, REG_GET (op->reg) + incval); | |
507 | ||
508 | return rv; | |
509 | } | |
510 | ||
511 | static int | |
512 | put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val) | |
513 | { | |
514 | MSP430_Opcode_Operand *op = opc->op + n; | |
515 | int rv; | |
516 | int addr; | |
517 | unsigned char buf[4]; | |
518 | int incval = 0; | |
519 | ||
520 | switch (opc->size) | |
521 | { | |
522 | case 8: | |
523 | val &= 0xff; | |
524 | break; | |
525 | case 16: | |
526 | val &= 0xffff; | |
527 | break; | |
528 | case 20: | |
529 | val &= 0xfffff; | |
530 | break; | |
531 | case 32: | |
532 | val &= 0xffffffff; | |
533 | break; | |
534 | } | |
535 | ||
536 | switch (op->type) | |
537 | { | |
538 | case MSP430_Operand_Register: | |
539 | REG (op->reg) = val; | |
540 | REG_PUT (op->reg, val); | |
541 | break; | |
542 | case MSP430_Operand_Indirect: | |
543 | case MSP430_Operand_Indirect_Postinc: | |
544 | addr = op->addend; | |
545 | if (op->reg != MSR_None) | |
546 | { | |
547 | int reg; | |
548 | /* Index values are signed, but the sum is limited to 16 | |
549 | bits if the register < 64k, for MSP430 compatibility in | |
550 | MSP430X chips. */ | |
551 | if (addr & 0x8000) | |
552 | addr |= -1 << 16; | |
553 | reg = REG_GET (op->reg); | |
554 | addr += reg; | |
555 | if (reg < 0x10000) | |
556 | addr &= 0xffff; | |
557 | } | |
558 | addr &= 0xfffff; | |
559 | ||
560 | if (TRACE_MEMORY_P (MSP430_CPU (sd))) | |
561 | trace_generic (sd, MSP430_CPU (sd), TRACE_MEMORY_IDX, | |
562 | "PUT: [%#x].%d <- %#x", addr, opc->size, val); | |
563 | #if 0 | |
564 | /* Hack - MSP430X5438 serial port transmit register. */ | |
565 | if (addr == 0x5ce) | |
566 | putchar (val); | |
567 | #endif | |
8969934d NC |
568 | if (addr >= 0x130 && addr <= 0x15B) |
569 | { | |
570 | signed int a,b; | |
571 | ||
572 | /* Hardware Multiply emulation. */ | |
573 | assert (opc->size == 16); | |
574 | ||
575 | switch (addr) | |
576 | { | |
577 | case 0x130: hwmult_op1 = val; hwmult_type = UNSIGN_32; break; | |
578 | case 0x132: hwmult_op1 = val; hwmult_type = SIGN_32; break; | |
579 | case 0x134: hwmult_op1 = val; hwmult_type = UNSIGN_MAC_32; break; | |
580 | case 0x136: hwmult_op1 = val; hwmult_type = SIGN_MAC_32; break; | |
581 | ||
582 | case 0x138: hwmult_op2 = val; | |
583 | switch (hwmult_type) | |
584 | { | |
585 | case UNSIGN_32: | |
586 | hwmult_result = hwmult_op1 * hwmult_op2; | |
587 | hwmult_signed_result = (signed) hwmult_result; | |
588 | hwmult_accumulator = hwmult_signed_accumulator = 0; | |
589 | break; | |
590 | ||
591 | case SIGN_32: | |
592 | a = sign_ext (hwmult_op1, 16); | |
593 | b = sign_ext (hwmult_op2, 16); | |
594 | hwmult_signed_result = a * b; | |
595 | hwmult_result = (unsigned) hwmult_signed_result; | |
596 | hwmult_accumulator = hwmult_signed_accumulator = 0; | |
597 | break; | |
598 | ||
599 | case UNSIGN_MAC_32: | |
600 | hwmult_accumulator += hwmult_op1 * hwmult_op2; | |
601 | hwmult_signed_accumulator += hwmult_op1 * hwmult_op2; | |
602 | hwmult_result = hwmult_signed_result = 0; | |
603 | break; | |
604 | ||
605 | case SIGN_MAC_32: | |
606 | a = sign_ext (hwmult_op1, 16); | |
607 | b = sign_ext (hwmult_op2, 16); | |
608 | hwmult_accumulator += a * b; | |
609 | hwmult_signed_accumulator += a * b; | |
610 | hwmult_result = hwmult_signed_result = 0; | |
611 | break; | |
612 | } | |
613 | break; | |
614 | ||
615 | case 0x140: hw32mult_op1 = val; hw32mult_type = UNSIGN_64; break; | |
616 | case 0x142: hw32mult_op1 = (hw32mult_op1 & 0xFFFF) | (val << 16); break; | |
617 | case 0x144: hw32mult_op1 = val; hw32mult_type = SIGN_64; break; | |
618 | case 0x146: hw32mult_op1 = (hw32mult_op1 & 0xFFFF) | (val << 16); break; | |
619 | case 0x150: hw32mult_op2 = val; break; | |
620 | ||
621 | case 0x152: hw32mult_op2 = (hw32mult_op2 & 0xFFFF) | (val << 16); | |
622 | switch (hw32mult_type) | |
623 | { | |
624 | case UNSIGN_64: | |
625 | hw32mult_result = hw32mult_op1 * hw32mult_op2; | |
626 | break; | |
627 | case SIGN_64: | |
628 | hw32mult_result = sign_ext (hw32mult_op1, 32) * sign_ext (hw32mult_op2, 32); | |
629 | break; | |
630 | } | |
631 | break; | |
632 | ||
633 | default: | |
634 | fprintf (stderr, "unimplemented HW MULT write to %x!\n", addr); | |
635 | break; | |
636 | } | |
637 | } | |
638 | ||
3346cfda NC |
639 | switch (opc->size) |
640 | { | |
641 | case 8: | |
642 | buf[0] = val; | |
643 | sim_core_write_buffer (sd, MSP430_CPU (sd), write_map, buf, addr, 1); | |
644 | break; | |
645 | case 16: | |
646 | buf[0] = val; | |
647 | buf[1] = val >> 8; | |
648 | sim_core_write_buffer (sd, MSP430_CPU (sd), write_map, buf, addr, 2); | |
649 | break; | |
650 | case 20: | |
651 | case 32: | |
652 | buf[0] = val; | |
653 | buf[1] = val >> 8; | |
654 | buf[2] = val >> 16; | |
655 | buf[3] = val >> 24; | |
656 | sim_core_write_buffer (sd, MSP430_CPU (sd), write_map, buf, addr, 4); | |
657 | break; | |
658 | default: | |
659 | assert (! opc->size); | |
660 | break; | |
661 | } | |
662 | break; | |
663 | default: | |
664 | fprintf (stderr, "invalid operand %d type %d\n", n, op->type); | |
665 | abort (); | |
666 | } | |
667 | ||
668 | switch (opc->size) | |
669 | { | |
670 | case 8: | |
671 | rv &= 0xff; | |
672 | incval = 1; | |
673 | break; | |
674 | case 16: | |
675 | rv &= 0xffff; | |
676 | incval = 2; | |
677 | break; | |
678 | case 20: | |
679 | rv &= 0xfffff; | |
680 | incval = 4; | |
681 | break; | |
682 | case 32: | |
683 | rv &= 0xffffffff; | |
684 | incval = 4; | |
685 | break; | |
686 | } | |
687 | ||
688 | if (op->type == MSP430_Operand_Indirect_Postinc) | |
689 | { | |
690 | int new_val = REG_GET (op->reg) + incval; | |
691 | /* SP is always word-aligned. */ | |
692 | if (op->reg == MSR_SP && (new_val & 1)) | |
693 | new_val ++; | |
694 | REG_PUT (op->reg, new_val); | |
695 | } | |
696 | ||
697 | return rv; | |
698 | } | |
699 | ||
700 | static void | |
701 | mem_put_val (SIM_DESC sd, int addr, int val, int bits) | |
702 | { | |
703 | MSP430_Opcode_Decoded opc; | |
704 | ||
705 | opc.size = bits; | |
706 | opc.op[0].type = MSP430_Operand_Indirect; | |
707 | opc.op[0].addend = addr; | |
708 | opc.op[0].reg = MSR_None; | |
709 | put_op (sd, &opc, 0, val); | |
710 | } | |
711 | ||
712 | static int | |
713 | mem_get_val (SIM_DESC sd, int addr, int bits) | |
714 | { | |
715 | MSP430_Opcode_Decoded opc; | |
716 | ||
717 | opc.size = bits; | |
718 | opc.op[0].type = MSP430_Operand_Indirect; | |
719 | opc.op[0].addend = addr; | |
720 | opc.op[0].reg = MSR_None; | |
721 | return get_op (sd, &opc, 0); | |
722 | } | |
723 | ||
724 | #define CIO_OPEN (0xF0) | |
725 | #define CIO_CLOSE (0xF1) | |
726 | #define CIO_READ (0xF2) | |
727 | #define CIO_WRITE (0xF3) | |
728 | #define CIO_LSEEK (0xF4) | |
729 | #define CIO_UNLINK (0xF5) | |
730 | #define CIO_GETENV (0xF6) | |
731 | #define CIO_RENAME (0xF7) | |
732 | #define CIO_GETTIME (0xF8) | |
733 | #define CIO_GETCLK (0xF9) | |
734 | #define CIO_SYNC (0xFF) | |
735 | ||
736 | #define CIO_I(n) (parms[(n)] + parms[(n)+1] * 256) | |
737 | #define CIO_L(n) (parms[(n)] + parms[(n)+1] * 256 \ | |
738 | + parms[(n)+2] * 65536 + parms[(n)+3] * 16777216) | |
739 | ||
740 | static void | |
741 | msp430_cio (SIM_DESC sd) | |
742 | { | |
743 | /* A block of data at __CIOBUF__ describes the I/O operation to | |
744 | perform. */ | |
745 | ||
746 | unsigned char raw_parms[13]; | |
747 | unsigned char parms[8]; | |
748 | long length; | |
749 | int command; | |
750 | unsigned char buffer[512]; | |
751 | long ret_buflen = 0; | |
752 | long fd, addr, len, rv; | |
753 | ||
754 | sim_core_read_buffer (sd, MSP430_CPU (sd), 0, parms, | |
755 | MSP430_CPU (sd)->state.cio_buffer, 5); | |
756 | length = CIO_I (0); | |
757 | command = parms[2]; | |
758 | ||
759 | sim_core_read_buffer (sd, MSP430_CPU (sd), 0, parms, | |
760 | MSP430_CPU (sd)->state.cio_buffer + 3, 8); | |
761 | ||
762 | sim_core_read_buffer (sd, MSP430_CPU (sd), 0, buffer, | |
763 | MSP430_CPU (sd)->state.cio_buffer + 11, length); | |
764 | ||
765 | switch (command) | |
766 | { | |
767 | case CIO_WRITE: | |
768 | fd = CIO_I (0); | |
769 | len = CIO_I (2); | |
770 | ||
771 | rv = write (fd, buffer, len); | |
772 | parms[0] = rv & 0xff; | |
773 | parms[1] = rv >> 8; | |
774 | ||
775 | break; | |
776 | } | |
777 | ||
778 | sim_core_write_buffer (sd, MSP430_CPU (sd), 0, parms, | |
779 | MSP430_CPU (sd)->state.cio_buffer + 4, 8); | |
780 | if (ret_buflen) | |
781 | sim_core_write_buffer (sd, MSP430_CPU (sd), 0, buffer, | |
782 | MSP430_CPU (sd)->state.cio_buffer + 12, ret_buflen); | |
783 | } | |
784 | ||
785 | #define SRC get_op (sd, opcode, 1) | |
786 | #define DSRC get_op (sd, opcode, 0) | |
787 | #define DEST(V) put_op (sd, opcode, 0, (V)) | |
788 | ||
789 | static int | |
790 | msp430_dis_read (bfd_vma memaddr, | |
791 | bfd_byte *myaddr, | |
792 | unsigned int length, | |
793 | struct disassemble_info *dinfo) | |
794 | { | |
795 | SIM_DESC sd = dinfo->private_data; | |
796 | sim_core_read_buffer (sd, MSP430_CPU (sd), 0, myaddr, memaddr, length); | |
797 | return 0; | |
798 | } | |
799 | ||
800 | #define DO_ALU(OP,SOP,MORE) \ | |
801 | { \ | |
802 | int s1 = DSRC; \ | |
803 | int s2 = SRC; \ | |
804 | int result = s1 OP s2 MORE; \ | |
805 | if (TRACE_ALU_P (MSP430_CPU (sd))) \ | |
806 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, \ | |
807 | "ALU: %#x %s %#x %s = %#x", s1, SOP, s2, #MORE, result); \ | |
808 | DEST (result); \ | |
809 | } | |
810 | ||
811 | #define SIGN (1 << (opcode->size - 1)) | |
812 | #define POS(x) (((x) & SIGN) ? 0 : 1) | |
813 | #define NEG(x) (((x) & SIGN) ? 1 : 0) | |
814 | ||
3346cfda NC |
815 | #define SX(v) sign_ext (v, opcode->size) |
816 | #define ZX(v) zero_ext (v, opcode->size) | |
817 | ||
818 | static char * | |
819 | flags2string (int f) | |
820 | { | |
821 | static char buf[2][6]; | |
822 | static int bi = 0; | |
823 | char *bp = buf[bi]; | |
824 | ||
825 | bi = (bi + 1) % 2; | |
826 | ||
827 | bp[0] = f & MSP430_FLAG_V ? 'V' : '-'; | |
828 | bp[1] = f & MSP430_FLAG_N ? 'N' : '-'; | |
829 | bp[2] = f & MSP430_FLAG_Z ? 'Z' : '-'; | |
830 | bp[3] = f & MSP430_FLAG_C ? 'C' : '-'; | |
831 | bp[4] = 0; | |
832 | return bp; | |
833 | } | |
834 | ||
835 | /* Random number that won't show up in our usual logic. */ | |
836 | #define MAGIC_OVERFLOW 0x55000F | |
837 | ||
838 | static void | |
839 | do_flags (SIM_DESC sd, | |
840 | MSP430_Opcode_Decoded *opcode, | |
841 | int vnz_val, /* Signed result. */ | |
842 | int carry, | |
843 | int overflow) | |
844 | { | |
845 | int f = SR; | |
846 | int new_f = 0; | |
847 | int signbit = 1 << (opcode->size - 1); | |
848 | ||
849 | f &= ~opcode->flags_0; | |
850 | f &= ~opcode->flags_set; | |
851 | f |= opcode->flags_1; | |
852 | ||
853 | if (vnz_val & signbit) | |
854 | new_f |= MSP430_FLAG_N; | |
855 | if (! (vnz_val & ((signbit << 1) - 1))) | |
856 | new_f |= MSP430_FLAG_Z; | |
857 | if (overflow == MAGIC_OVERFLOW) | |
858 | { | |
859 | if (vnz_val != SX (vnz_val)) | |
860 | new_f |= MSP430_FLAG_V; | |
861 | } | |
862 | else | |
863 | if (overflow) | |
864 | new_f |= MSP430_FLAG_V; | |
865 | if (carry) | |
866 | new_f |= MSP430_FLAG_C; | |
867 | ||
868 | new_f = f | (new_f & opcode->flags_set); | |
869 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
870 | { | |
871 | if (SR != new_f) | |
872 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
873 | "FLAGS: %s -> %s", flags2string (SR), | |
874 | flags2string (new_f)); | |
875 | else | |
876 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
877 | "FLAGS: %s", flags2string (new_f)); | |
878 | } | |
879 | SR = new_f; | |
880 | } | |
881 | ||
882 | #define FLAGS(vnz,c) do_flags (sd, opcode, vnz, c, MAGIC_OVERFLOW) | |
883 | #define FLAGSV(vnz,c,v) do_flags (sd, opcode, vnz, c, v) | |
884 | ||
885 | /* These two assume unsigned 16-bit (four digit) words. | |
886 | Mask off unwanted bits for byte operations. */ | |
887 | ||
888 | static int | |
889 | bcd_to_binary (int v) | |
890 | { | |
891 | int r = ( ((v >> 0) & 0xf) * 1 | |
892 | + ((v >> 4) & 0xf) * 10 | |
893 | + ((v >> 8) & 0xf) * 100 | |
894 | + ((v >> 12) & 0xf) * 1000); | |
895 | return r; | |
896 | } | |
897 | ||
898 | static int | |
899 | binary_to_bcd (int v) | |
900 | { | |
901 | int r = ( ((v / 1) % 10) << 0 | |
902 | | ((v / 10) % 10) << 4 | |
903 | | ((v / 100) % 10) << 8 | |
904 | | ((v / 1000) % 10) << 12); | |
905 | return r; | |
906 | } | |
907 | ||
908 | static int | |
909 | syscall_read_mem (host_callback *cb, struct cb_syscall *sc, | |
910 | unsigned long taddr, char *buf, int bytes) | |
911 | { | |
912 | SIM_DESC sd = (SIM_DESC) sc->p1; | |
913 | SIM_CPU *cpu = (SIM_CPU *) sc->p2; | |
914 | ||
915 | return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); | |
916 | } | |
917 | ||
918 | static int | |
919 | syscall_write_mem (host_callback *cb, struct cb_syscall *sc, | |
920 | unsigned long taddr, const char *buf, int bytes) | |
921 | { | |
922 | SIM_DESC sd = (SIM_DESC) sc->p1; | |
923 | SIM_CPU *cpu = (SIM_CPU *) sc->p2; | |
924 | ||
925 | return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); | |
926 | } | |
927 | ||
928 | static const char * | |
929 | cond_string (int cond) | |
930 | { | |
931 | switch (cond) | |
932 | { | |
933 | case MSC_nz: | |
934 | return "NZ"; | |
935 | case MSC_z: | |
936 | return "Z"; | |
937 | case MSC_nc: | |
938 | return "NC"; | |
939 | case MSC_c: | |
940 | return "C"; | |
941 | case MSC_n: | |
942 | return "N"; | |
943 | case MSC_ge: | |
944 | return "GE"; | |
945 | case MSC_l: | |
946 | return "L"; | |
947 | case MSC_true: | |
948 | return "MP"; | |
949 | default: | |
950 | return "??"; | |
951 | } | |
952 | } | |
953 | ||
954 | /* Checks a CALL to address CALL_ADDR. If this is a special | |
955 | syscall address then the call is simulated and non-zero is | |
956 | returned. Otherwise 0 is returned. */ | |
957 | ||
958 | static int | |
959 | maybe_perform_syscall (SIM_DESC sd, int call_addr) | |
960 | { | |
961 | if (call_addr == 0x00160) | |
962 | { | |
963 | int i; | |
964 | ||
965 | for (i = 0; i < 16; i++) | |
966 | { | |
967 | if (i % 4 == 0) | |
968 | fprintf (stderr, "\t"); | |
969 | fprintf (stderr, "R%-2d %05x ", i, MSP430_CPU (sd)->state.regs[i]); | |
970 | if (i % 4 == 3) | |
971 | { | |
972 | int sp = SP + (3 - (i / 4)) * 2; | |
973 | unsigned char buf[2]; | |
974 | ||
975 | sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, sp, 2); | |
976 | ||
977 | fprintf (stderr, "\tSP%+d: %04x", sp - SP, | |
978 | buf[0] + buf[1] * 256); | |
979 | ||
980 | if (i / 4 == 0) | |
981 | { | |
982 | int flags = SR; | |
983 | ||
984 | fprintf (stderr, flags & 0x100 ? " V" : " -"); | |
985 | fprintf (stderr, flags & 0x004 ? "N" : "-"); | |
986 | fprintf (stderr, flags & 0x002 ? "Z" : "-"); | |
987 | fprintf (stderr, flags & 0x001 ? "C" : "-"); | |
988 | } | |
989 | ||
990 | fprintf (stderr, "\n"); | |
991 | } | |
992 | } | |
993 | return 1; | |
994 | } | |
995 | ||
996 | if ((call_addr & ~0x3f) == 0x00180) | |
997 | { | |
998 | /* Syscall! */ | |
999 | int syscall_num = call_addr & 0x3f; | |
1000 | host_callback *cb = STATE_CALLBACK (sd); | |
1001 | CB_SYSCALL sc; | |
1002 | ||
1003 | CB_SYSCALL_INIT (&sc); | |
1004 | ||
1005 | sc.func = syscall_num; | |
1006 | sc.arg1 = MSP430_CPU (sd)->state.regs[12]; | |
1007 | sc.arg2 = MSP430_CPU (sd)->state.regs[13]; | |
1008 | sc.arg3 = MSP430_CPU (sd)->state.regs[14]; | |
1009 | sc.arg4 = MSP430_CPU (sd)->state.regs[15]; | |
1010 | ||
1011 | if (TRACE_SYSCALL_P (MSP430_CPU (sd))) | |
1012 | { | |
1013 | const char *syscall_name = "*unknown*"; | |
1014 | ||
1015 | switch (syscall_num) | |
1016 | { | |
1017 | case TARGET_SYS_exit: | |
1018 | syscall_name = "exit(%d)"; | |
1019 | break; | |
1020 | case TARGET_SYS_open: | |
1021 | syscall_name = "open(%#x,%#x)"; | |
1022 | break; | |
1023 | case TARGET_SYS_close: | |
1024 | syscall_name = "close(%d)"; | |
1025 | break; | |
1026 | case TARGET_SYS_read: | |
1027 | syscall_name = "read(%d,%#x,%d)"; | |
1028 | break; | |
1029 | case TARGET_SYS_write: | |
1030 | syscall_name = "write(%d,%#x,%d)"; | |
1031 | break; | |
1032 | } | |
1033 | trace_generic (sd, MSP430_CPU (sd), TRACE_SYSCALL_IDX, | |
1034 | syscall_name, sc.arg1, sc.arg2, sc.arg3, sc.arg4); | |
1035 | } | |
1036 | ||
1037 | /* Handle SYS_exit here. */ | |
1038 | if (syscall_num == 1) | |
1039 | { | |
1040 | sim_engine_halt (sd, MSP430_CPU (sd), NULL, | |
1041 | MSP430_CPU (sd)->state.regs[0], | |
1042 | sim_exited, sc.arg1); | |
1043 | return 1; | |
1044 | } | |
1045 | ||
1046 | sc.p1 = sd; | |
1047 | sc.p2 = MSP430_CPU (sd); | |
1048 | sc.read_mem = syscall_read_mem; | |
1049 | sc.write_mem = syscall_write_mem; | |
1050 | ||
1051 | cb_syscall (cb, &sc); | |
1052 | ||
1053 | if (TRACE_SYSCALL_P (MSP430_CPU (sd))) | |
1054 | trace_generic (sd, MSP430_CPU (sd), TRACE_SYSCALL_IDX, | |
a3271a3e | 1055 | "returns %ld", sc.result); |
3346cfda NC |
1056 | |
1057 | MSP430_CPU (sd)->state.regs[12] = sc.result; | |
1058 | return 1; | |
1059 | } | |
1060 | ||
1061 | return 0; | |
1062 | } | |
1063 | ||
1064 | static void | |
1065 | msp430_step_once (SIM_DESC sd) | |
1066 | { | |
1067 | Get_Byte_Local_Data ld; | |
1068 | unsigned char buf[100]; | |
1069 | int i; | |
1070 | int opsize; | |
1071 | unsigned int opcode_pc; | |
1072 | MSP430_Opcode_Decoded opcode_buf; | |
1073 | MSP430_Opcode_Decoded *opcode = &opcode_buf; | |
1074 | int s1, s2, result; | |
1075 | int u1, u2, uresult; | |
1076 | int c, reg; | |
1077 | int sp; | |
1078 | int carry_to_use; | |
1079 | int n_repeats; | |
1080 | int rept; | |
1081 | int op_bytes, op_bits; | |
1082 | ||
1083 | PC &= 0xfffff; | |
1084 | opcode_pc = PC; | |
1085 | ||
1086 | if (opcode_pc < 0x10) | |
1087 | { | |
1088 | fprintf (stderr, "Fault: PC(%#x) is less than 0x10\n", opcode_pc); | |
1089 | sim_engine_halt (sd, MSP430_CPU (sd), NULL, | |
1090 | MSP430_CPU (sd)->state.regs[0], | |
1091 | sim_exited, -1); | |
1092 | return; | |
1093 | } | |
1094 | ||
1095 | if (PC == MSP430_CPU (sd)->state.cio_breakpoint | |
1096 | && STATE_OPEN_KIND (sd) != SIM_OPEN_DEBUG) | |
1097 | msp430_cio (sd); | |
1098 | ||
1099 | ld.sd = sd; | |
1100 | ld.gb_addr = PC; | |
1101 | opsize = msp430_decode_opcode (MSP430_CPU (sd)->state.regs[0], | |
1102 | opcode, msp430_getbyte, &ld); | |
1103 | PC += opsize; | |
1104 | if (opsize <= 0) | |
1105 | { | |
1106 | fprintf (stderr, "Fault: undecodable opcode at %#x\n", opcode_pc); | |
1107 | sim_engine_halt (sd, MSP430_CPU (sd), NULL, | |
1108 | MSP430_CPU (sd)->state.regs[0], | |
1109 | sim_exited, -1); | |
1110 | return; | |
1111 | } | |
1112 | ||
1113 | if (opcode->repeat_reg) | |
1114 | n_repeats = (MSP430_CPU (sd)->state.regs[opcode->repeats] & 0x000f) + 1; | |
1115 | else | |
1116 | n_repeats = opcode->repeats + 1; | |
1117 | ||
1118 | op_bits = opcode->size; | |
1119 | switch (op_bits) | |
1120 | { | |
1121 | case 8: | |
1122 | op_bytes = 1; | |
1123 | break; | |
1124 | case 16: | |
1125 | op_bytes = 2; | |
1126 | break; | |
1127 | case 20: | |
1128 | case 32: | |
1129 | op_bytes = 4; | |
1130 | break; | |
1131 | } | |
1132 | ||
1133 | if (TRACE_INSN_P (MSP430_CPU (sd))) | |
1134 | { | |
1135 | disassemble_info info; | |
1136 | unsigned char b[10]; | |
1137 | ||
1138 | msp430_trace_one (opcode_pc); | |
1139 | ||
1140 | sim_core_read_buffer (sd, MSP430_CPU (sd), 0, b, opcode_pc, opsize); | |
1141 | ||
a3271a3e | 1142 | init_disassemble_info (&info, stderr, (fprintf_ftype) fprintf); |
3346cfda NC |
1143 | info.private_data = sd; |
1144 | info.read_memory_func = msp430_dis_read; | |
1145 | fprintf (stderr, "%#8x ", opcode_pc); | |
1146 | for (i = 0; i < opsize; i += 2) | |
1147 | fprintf (stderr, " %02x%02x", b[i+1], b[i]); | |
1148 | for (; i < 6; i += 2) | |
1149 | fprintf (stderr, " "); | |
1150 | fprintf (stderr, " "); | |
1151 | print_insn_msp430 (opcode_pc, &info); | |
1152 | fprintf (stderr, "\n"); | |
1153 | fflush (stdout); | |
1154 | } | |
1155 | ||
1156 | if (TRACE_ANY_P (MSP430_CPU (sd))) | |
1157 | trace_prefix (sd, MSP430_CPU (sd), NULL_CIA, opcode_pc, | |
1158 | TRACE_LINENUM_P (MSP430_CPU (sd)), NULL, 0, ""); | |
1159 | ||
1160 | carry_to_use = 0; | |
1161 | switch (opcode->id) | |
1162 | { | |
1163 | case MSO_unknown: | |
1164 | break; | |
1165 | ||
1166 | /* Double-operand instructions. */ | |
1167 | case MSO_mov: | |
1168 | if (opcode->n_bytes == 2 | |
1169 | && opcode->op[0].type == MSP430_Operand_Register | |
1170 | && opcode->op[0].reg == MSR_CG | |
1171 | && opcode->op[1].type == MSP430_Operand_Immediate | |
1172 | && opcode->op[1].addend == 0 | |
1173 | /* A 16-bit write of #0 is a NOP; an 8-bit write is a BRK. */ | |
1174 | && opcode->size == 8) | |
1175 | { | |
1176 | /* This is the designated software breakpoint instruction. */ | |
1177 | PC -= opsize; | |
1178 | sim_engine_halt (sd, MSP430_CPU (sd), NULL, | |
1179 | MSP430_CPU (sd)->state.regs[0], | |
1180 | sim_stopped, SIM_SIGTRAP); | |
1181 | ||
1182 | } | |
1183 | else | |
1184 | { | |
1185 | /* Otherwise, do the move. */ | |
1186 | for (rept = 0; rept < n_repeats; rept ++) | |
1187 | { | |
1188 | DEST (SRC); | |
1189 | } | |
1190 | } | |
1191 | break; | |
1192 | ||
1193 | case MSO_addc: | |
1194 | for (rept = 0; rept < n_repeats; rept ++) | |
1195 | { | |
1196 | carry_to_use = (SR & MSP430_FLAG_C) ? 1 : 0; | |
1197 | u1 = DSRC; | |
1198 | u2 = SRC; | |
1199 | s1 = SX (u1); | |
1200 | s2 = SX (u2); | |
1201 | uresult = u1 + u2 + carry_to_use; | |
1202 | result = s1 + s2 + carry_to_use; | |
1203 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1204 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1205 | "ADDC: %#x + %#x + %d = %#x", | |
1206 | u1, u2, carry_to_use, uresult); | |
1207 | DEST (result); | |
1208 | FLAGS (result, uresult != ZX (uresult)); | |
1209 | } | |
1210 | break; | |
1211 | ||
1212 | case MSO_add: | |
1213 | for (rept = 0; rept < n_repeats; rept ++) | |
1214 | { | |
1215 | u1 = DSRC; | |
1216 | u2 = SRC; | |
1217 | s1 = SX (u1); | |
1218 | s2 = SX (u2); | |
1219 | uresult = u1 + u2; | |
1220 | result = s1 + s2; | |
1221 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1222 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1223 | "ADD: %#x + %#x = %#x", | |
1224 | u1, u2, uresult); | |
1225 | DEST (result); | |
1226 | FLAGS (result, uresult != ZX (uresult)); | |
1227 | } | |
1228 | break; | |
1229 | ||
1230 | case MSO_subc: | |
1231 | for (rept = 0; rept < n_repeats; rept ++) | |
1232 | { | |
1233 | carry_to_use = (SR & MSP430_FLAG_C) ? 1 : 0; | |
1234 | u1 = DSRC; | |
1235 | u2 = SRC; | |
1236 | s1 = SX (u1); | |
1237 | s2 = SX (u2); | |
1238 | uresult = ZX (~u2) + u1 + carry_to_use; | |
1239 | result = s1 - s2 + (carry_to_use - 1); | |
1240 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1241 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1242 | "SUBC: %#x - %#x + %d = %#x", | |
1243 | u1, u2, carry_to_use, uresult); | |
1244 | DEST (result); | |
1245 | FLAGS (result, uresult != ZX (uresult)); | |
1246 | } | |
1247 | break; | |
1248 | ||
1249 | case MSO_sub: | |
1250 | for (rept = 0; rept < n_repeats; rept ++) | |
1251 | { | |
1252 | u1 = DSRC; | |
1253 | u2 = SRC; | |
1254 | s1 = SX (u1); | |
1255 | s2 = SX (u2); | |
1256 | uresult = ZX (~u2) + u1 + 1; | |
1257 | result = SX (uresult); | |
1258 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1259 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1260 | "SUB: %#x - %#x = %#x", | |
1261 | u1, u2, uresult); | |
1262 | DEST (result); | |
1263 | FLAGS (result, uresult != ZX (uresult)); | |
1264 | } | |
1265 | break; | |
1266 | ||
1267 | case MSO_cmp: | |
1268 | for (rept = 0; rept < n_repeats; rept ++) | |
1269 | { | |
1270 | u1 = DSRC; | |
1271 | u2 = SRC; | |
1272 | s1 = SX (u1); | |
1273 | s2 = SX (u2); | |
1274 | uresult = ZX (~u2) + u1 + 1; | |
1275 | result = s1 - s2; | |
1276 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1277 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1278 | "CMP: %#x - %#x = %x", | |
1279 | u1, u2, uresult); | |
1280 | FLAGS (result, uresult != ZX (uresult)); | |
1281 | } | |
1282 | break; | |
1283 | ||
1284 | case MSO_dadd: | |
1285 | for (rept = 0; rept < n_repeats; rept ++) | |
1286 | { | |
1287 | carry_to_use = (SR & MSP430_FLAG_C) ? 1 : 0; | |
1288 | u1 = DSRC; | |
1289 | u2 = SRC; | |
1290 | uresult = bcd_to_binary (u1) + bcd_to_binary (u2) + carry_to_use; | |
1291 | result = binary_to_bcd (uresult); | |
1292 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1293 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1294 | "DADD: %#x + %#x + %d = %#x", | |
1295 | u1, u2, carry_to_use, result); | |
1296 | DEST (result); | |
1297 | FLAGS (result, uresult > ((opcode->size == 8) ? 99 : 9999)); | |
1298 | } | |
1299 | break; | |
1300 | ||
1301 | case MSO_and: | |
1302 | for (rept = 0; rept < n_repeats; rept ++) | |
1303 | { | |
1304 | u1 = DSRC; | |
1305 | u2 = SRC; | |
1306 | uresult = u1 & u2; | |
1307 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1308 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1309 | "AND: %#x & %#x = %#x", | |
1310 | u1, u2, uresult); | |
1311 | DEST (uresult); | |
1312 | FLAGS (uresult, uresult != 0); | |
1313 | } | |
1314 | break; | |
1315 | ||
1316 | case MSO_bit: | |
1317 | for (rept = 0; rept < n_repeats; rept ++) | |
1318 | { | |
1319 | u1 = DSRC; | |
1320 | u2 = SRC; | |
1321 | uresult = u1 & u2; | |
1322 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1323 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1324 | "BIT: %#x & %#x -> %#x", | |
1325 | u1, u2, uresult); | |
1326 | FLAGS (uresult, uresult != 0); | |
1327 | } | |
1328 | break; | |
1329 | ||
1330 | case MSO_bic: | |
1331 | for (rept = 0; rept < n_repeats; rept ++) | |
1332 | { | |
1333 | u1 = DSRC; | |
1334 | u2 = SRC; | |
1335 | uresult = u1 & ~ u2; | |
1336 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1337 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1338 | "BIC: %#x & ~ %#x = %#x", | |
1339 | u1, u2, uresult); | |
1340 | DEST (uresult); | |
1341 | } | |
1342 | break; | |
1343 | ||
1344 | case MSO_bis: | |
1345 | for (rept = 0; rept < n_repeats; rept ++) | |
1346 | { | |
1347 | u1 = DSRC; | |
1348 | u2 = SRC; | |
1349 | uresult = u1 | u2; | |
1350 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1351 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1352 | "BIS: %#x | %#x = %#x", | |
1353 | u1, u2, uresult); | |
1354 | DEST (uresult); | |
1355 | } | |
1356 | break; | |
1357 | ||
1358 | case MSO_xor: | |
1359 | for (rept = 0; rept < n_repeats; rept ++) | |
1360 | { | |
1361 | s1 = 1 << (opcode->size - 1); | |
1362 | u1 = DSRC; | |
1363 | u2 = SRC; | |
1364 | uresult = u1 ^ u2; | |
1365 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1366 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1367 | "XOR: %#x & %#x = %#x", | |
1368 | u1, u2, uresult); | |
1369 | DEST (uresult); | |
1370 | FLAGSV (uresult, uresult != 0, (u1 & s1) && (u2 & s1)); | |
1371 | } | |
1372 | break; | |
1373 | ||
1374 | /* Single-operand instructions. Note: the decoder puts the same | |
1375 | operand in SRC as in DEST, for our convenience. */ | |
1376 | ||
1377 | case MSO_rrc: | |
1378 | for (rept = 0; rept < n_repeats; rept ++) | |
1379 | { | |
1380 | u1 = SRC; | |
1381 | carry_to_use = u1 & 1; | |
1382 | uresult = u1 >> 1; | |
1383 | if (SR & MSP430_FLAG_C) | |
1384 | uresult |= (1 << (opcode->size - 1)); | |
1385 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1386 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1387 | "RRC: %#x >>= %#x", | |
1388 | u1, uresult); | |
1389 | DEST (uresult); | |
1390 | FLAGS (uresult, carry_to_use); | |
1391 | } | |
1392 | break; | |
1393 | ||
1394 | case MSO_swpb: | |
1395 | for (rept = 0; rept < n_repeats; rept ++) | |
1396 | { | |
1397 | u1 = SRC; | |
1398 | uresult = ((u1 >> 8) & 0x00ff) | ((u1 << 8) & 0xff00); | |
1399 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1400 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1401 | "SWPB: %#x -> %#x", | |
1402 | u1, uresult); | |
1403 | DEST (uresult); | |
1404 | } | |
1405 | break; | |
1406 | ||
1407 | case MSO_rra: | |
1408 | for (rept = 0; rept < n_repeats; rept ++) | |
1409 | { | |
1410 | u1 = SRC; | |
1411 | c = u1 & 1; | |
1412 | s1 = 1 << (opcode->size - 1); | |
1413 | uresult = (u1 >> 1) | (u1 & s1); | |
1414 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1415 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1416 | "RRA: %#x >>= %#x", | |
1417 | u1, uresult); | |
1418 | DEST (uresult); | |
1419 | FLAGS (uresult, c); | |
1420 | } | |
1421 | break; | |
1422 | ||
1423 | case MSO_rru: | |
1424 | for (rept = 0; rept < n_repeats; rept ++) | |
1425 | { | |
1426 | u1 = SRC; | |
1427 | c = u1 & 1; | |
1428 | uresult = (u1 >> 1); | |
1429 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1430 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1431 | "RRU: %#x >>= %#x", | |
1432 | u1, uresult); | |
1433 | DEST (uresult); | |
1434 | FLAGS (uresult, c); | |
1435 | } | |
1436 | break; | |
1437 | ||
1438 | case MSO_sxt: | |
1439 | for (rept = 0; rept < n_repeats; rept ++) | |
1440 | { | |
1441 | u1 = SRC; | |
1442 | if (u1 & 0x80) | |
1443 | uresult = u1 | 0xfff00; | |
1444 | else | |
1445 | uresult = u1 & 0x000ff; | |
1446 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1447 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1448 | "SXT: %#x -> %#x", | |
1449 | u1, uresult); | |
1450 | DEST (uresult); | |
1451 | FLAGS (uresult, c); | |
1452 | } | |
1453 | break; | |
1454 | ||
1455 | case MSO_push: | |
1456 | for (rept = 0; rept < n_repeats; rept ++) | |
1457 | { | |
1458 | int new_sp; | |
1459 | ||
1460 | new_sp = REG_GET (MSR_SP) - op_bytes; | |
1461 | /* SP is always word-aligned. */ | |
1462 | if (new_sp & 1) | |
1463 | new_sp --; | |
1464 | REG_PUT (MSR_SP, new_sp); | |
1465 | u1 = SRC; | |
1466 | mem_put_val (sd, SP, u1, op_bits); | |
1467 | if (opcode->op[1].type == MSP430_Operand_Register) | |
1468 | opcode->op[1].reg --; | |
1469 | } | |
1470 | break; | |
1471 | ||
1472 | case MSO_pop: | |
1473 | for (rept = 0; rept < n_repeats; rept ++) | |
1474 | { | |
1475 | int new_sp; | |
1476 | ||
1477 | u1 = mem_get_val (sd, SP, op_bits); | |
1478 | DEST (u1); | |
1479 | if (opcode->op[0].type == MSP430_Operand_Register) | |
1480 | opcode->op[0].reg ++; | |
1481 | new_sp = REG_GET (MSR_SP) + op_bytes; | |
1482 | /* SP is always word-aligned. */ | |
1483 | if (new_sp & 1) | |
1484 | new_sp ++; | |
1485 | REG_PUT (MSR_SP, new_sp); | |
1486 | } | |
1487 | break; | |
1488 | ||
1489 | case MSO_call: | |
1490 | u1 = SRC; | |
1491 | ||
1492 | if (maybe_perform_syscall (sd, u1)) | |
1493 | break; | |
1494 | ||
1495 | REG_PUT (MSR_SP, REG_GET (MSR_SP) - op_bytes); | |
1496 | mem_put_val (sd, SP, PC, op_bits); | |
1497 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1498 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1499 | "CALL: func %#x ret %#x, sp %#x", | |
1500 | u1, PC, SP); | |
1501 | REG_PUT (MSR_PC, u1); | |
1502 | break; | |
1503 | ||
1504 | case MSO_reti: | |
8969934d NC |
1505 | u1 = mem_get_val (sd, SP, 16); |
1506 | SR = u1 & 0xFF; | |
3346cfda | 1507 | SP += 2; |
8969934d | 1508 | PC = mem_get_val (sd, SP, 16); |
3346cfda | 1509 | SP += 2; |
8969934d NC |
1510 | /* Emulate the RETI action of the 20-bit CPUX architecure. |
1511 | This is safe for 16-bit CPU architectures as well, since the top | |
1512 | 8-bits of SR will have been written to the stack here, and will | |
1513 | have been read as 0. */ | |
1514 | PC |= (u1 & 0xF000) << 4; | |
3346cfda NC |
1515 | if (TRACE_ALU_P (MSP430_CPU (sd))) |
1516 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1517 | "RETI: pc %#x sr %#x", | |
1518 | PC, SR); | |
1519 | break; | |
1520 | ||
1521 | /* Jumps. */ | |
1522 | ||
1523 | case MSO_jmp: | |
1524 | i = SRC; | |
1525 | switch (opcode->cond) | |
1526 | { | |
1527 | case MSC_nz: | |
1528 | u1 = (SR & MSP430_FLAG_Z) ? 0 : 1; | |
1529 | break; | |
1530 | case MSC_z: | |
1531 | u1 = (SR & MSP430_FLAG_Z) ? 1 : 0; | |
1532 | break; | |
1533 | case MSC_nc: | |
1534 | u1 = (SR & MSP430_FLAG_C) ? 0 : 1; | |
1535 | break; | |
1536 | case MSC_c: | |
1537 | u1 = (SR & MSP430_FLAG_C) ? 1 : 0; | |
1538 | break; | |
1539 | case MSC_n: | |
1540 | u1 = (SR & MSP430_FLAG_N) ? 1 : 0; | |
1541 | break; | |
1542 | case MSC_ge: | |
1543 | u1 = (!!(SR & MSP430_FLAG_N) == !!(SR & MSP430_FLAG_V)) ? 1 : 0; | |
1544 | break; | |
1545 | case MSC_l: | |
1546 | u1 = (!!(SR & MSP430_FLAG_N) == !!(SR & MSP430_FLAG_V)) ? 0 : 1; | |
1547 | break; | |
1548 | case MSC_true: | |
1549 | u1 = 1; | |
1550 | break; | |
1551 | } | |
1552 | ||
1553 | if (u1) | |
1554 | { | |
1555 | if (TRACE_BRANCH_P (MSP430_CPU (sd))) | |
1556 | trace_generic (sd, MSP430_CPU (sd), TRACE_BRANCH_IDX, | |
1557 | "J%s: pc %#x -> %#x sr %#x, taken", | |
1558 | cond_string (opcode->cond), PC, i, SR); | |
1559 | PC = i; | |
1560 | if (PC == opcode_pc) | |
1561 | exit (0); | |
1562 | } | |
1563 | else | |
1564 | if (TRACE_BRANCH_P (MSP430_CPU (sd))) | |
1565 | trace_generic (sd, MSP430_CPU (sd), TRACE_BRANCH_IDX, | |
1566 | "J%s: pc %#x to %#x sr %#x, not taken", | |
1567 | cond_string (opcode->cond), PC, i, SR); | |
1568 | break; | |
1569 | ||
1570 | default: | |
1571 | fprintf (stderr, "error: unexpected opcode id %d\n", opcode->id); | |
1572 | exit (1); | |
1573 | } | |
1574 | } | |
1575 | ||
1576 | void | |
1577 | sim_engine_run (SIM_DESC sd, | |
1578 | int next_cpu_nr, | |
1579 | int nr_cpus, | |
1580 | int siggnal) | |
1581 | { | |
1582 | while (1) | |
1583 | { | |
1584 | msp430_step_once (sd); | |
1585 | if (sim_events_tick (sd)) | |
1586 | sim_events_process (sd); | |
1587 | } | |
1588 | } |