Commit | Line | Data |
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3346cfda NC |
1 | /* Simulator for TI MSP430 and MSP430X |
2 | ||
ecd75fc8 | 3 | Copyright (C) 2013-2014 Free Software Foundation, Inc. |
3346cfda NC |
4 | Contributed by Red Hat. |
5 | Based on sim/bfin/bfin-sim.c which was contributed by Analog Devices, Inc. | |
6 | ||
7 | This file is part of simulators. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #include "config.h" | |
23 | #include <stdio.h> | |
24 | #include <stdlib.h> | |
25 | #include <string.h> | |
26 | #include <inttypes.h> | |
27 | #include <assert.h> | |
28 | #include "bfd.h" | |
29 | #include "opcode/msp430-decode.h" | |
30 | #include "sim-main.h" | |
31 | #include "dis-asm.h" | |
32 | #include "targ-vals.h" | |
33 | ||
34 | static int | |
35 | loader_write_mem (SIM_DESC sd, | |
36 | SIM_ADDR taddr, | |
37 | const unsigned char *buf, | |
38 | int bytes) | |
39 | { | |
40 | SIM_CPU *cpu = MSP430_CPU (sd); | |
41 | return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); | |
42 | } | |
43 | ||
44 | static sim_cia | |
45 | msp430_pc_fetch (SIM_CPU *cpu) | |
46 | { | |
47 | return cpu->state.regs[0]; | |
48 | } | |
49 | ||
50 | static void | |
51 | msp430_pc_store (SIM_CPU *cpu, sim_cia newpc) | |
52 | { | |
53 | cpu->state.regs[0] = newpc; | |
54 | } | |
55 | ||
56 | static long | |
57 | lookup_symbol (SIM_DESC sd, const char *name) | |
58 | { | |
59 | struct bfd *abfd = STATE_PROG_BFD (sd); | |
60 | asymbol **symbol_table = STATE_SYMBOL_TABLE (sd); | |
61 | long number_of_symbols = STATE_NUM_SYMBOLS (sd); | |
62 | long i; | |
63 | ||
64 | if (symbol_table == NULL) | |
65 | { | |
66 | long storage_needed; | |
67 | ||
68 | storage_needed = bfd_get_symtab_upper_bound (abfd); | |
69 | if (storage_needed <= 0) | |
70 | return -1; | |
71 | ||
72 | STATE_SYMBOL_TABLE (sd) = symbol_table = xmalloc (storage_needed); | |
73 | STATE_NUM_SYMBOLS (sd) = number_of_symbols = | |
74 | bfd_canonicalize_symtab (abfd, symbol_table); | |
75 | } | |
76 | ||
77 | for (i = 0; i < number_of_symbols; i++) | |
78 | if (strcmp (symbol_table[i]->name, name) == 0) | |
79 | { | |
80 | long val = symbol_table[i]->section->vma + symbol_table[i]->value; | |
81 | return val; | |
82 | } | |
83 | return -1; | |
84 | } | |
85 | ||
86 | static int | |
87 | msp430_reg_fetch (SIM_CPU *cpu, int regno, unsigned char *buf, int len) | |
88 | { | |
89 | if (0 <= regno && regno < 16) | |
90 | { | |
91 | if (len == 2) | |
92 | { | |
93 | int val = cpu->state.regs[regno]; | |
94 | buf[0] = val & 0xff; | |
95 | buf[1] = (val >> 8) & 0xff; | |
96 | return 0; | |
97 | } | |
98 | else if (len == 4) | |
99 | { | |
100 | int val = cpu->state.regs[regno]; | |
101 | buf[0] = val & 0xff; | |
102 | buf[1] = (val >> 8) & 0xff; | |
103 | buf[2] = (val >> 16) & 0x0f; /* Registers are only 20 bits wide. */ | |
104 | buf[3] = 0; | |
105 | return 0; | |
106 | } | |
107 | else | |
108 | return -1; | |
109 | } | |
110 | else | |
111 | return -1; | |
112 | } | |
113 | ||
114 | static int | |
115 | msp430_reg_store (SIM_CPU *cpu, int regno, unsigned char *buf, int len) | |
116 | { | |
117 | if (0 <= regno && regno < 16) | |
118 | { | |
119 | if (len == 2) | |
120 | { | |
121 | cpu->state.regs[regno] = (buf[1] << 8) | buf[0]; | |
122 | return len; | |
123 | } | |
124 | ||
125 | if (len == 4) | |
126 | { | |
127 | cpu->state.regs[regno] = ((buf[2] << 16) & 0xf0000) | |
128 | | (buf[1] << 8) | buf[0]; | |
129 | return len; | |
130 | } | |
131 | } | |
132 | ||
133 | return -1; | |
134 | } | |
135 | ||
136 | static inline void | |
137 | msp430_initialize_cpu (SIM_DESC sd, SIM_CPU *cpu) | |
138 | { | |
139 | memset (&cpu->state, 0, sizeof (cpu->state)); | |
140 | } | |
141 | ||
142 | SIM_DESC | |
143 | sim_open (SIM_OPEN_KIND kind, | |
144 | struct host_callback_struct *callback, | |
145 | struct bfd *abfd, | |
146 | char **argv) | |
147 | { | |
148 | SIM_DESC sd = sim_state_alloc (kind, callback); | |
149 | char c; | |
150 | struct bfd *prog_bfd; | |
151 | ||
152 | /* Initialise the simulator. */ | |
153 | ||
154 | if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK) | |
155 | { | |
156 | sim_state_free (sd); | |
157 | return 0; | |
158 | } | |
159 | ||
160 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
161 | { | |
162 | sim_state_free (sd); | |
163 | return 0; | |
164 | } | |
165 | ||
166 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
167 | { | |
168 | sim_state_free (sd); | |
169 | return 0; | |
170 | } | |
171 | ||
172 | CPU_PC_FETCH (MSP430_CPU (sd)) = msp430_pc_fetch; | |
173 | CPU_PC_STORE (MSP430_CPU (sd)) = msp430_pc_store; | |
174 | CPU_REG_FETCH (MSP430_CPU (sd)) = msp430_reg_fetch; | |
175 | CPU_REG_STORE (MSP430_CPU (sd)) = msp430_reg_store; | |
176 | ||
177 | /* Allocate memory if none specified by user. */ | |
8969934d NC |
178 | if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0x130, 1) == 0) |
179 | sim_do_commandf (sd, "memory-region 0,0x20"); | |
3346cfda | 180 | if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0x200, 1) == 0) |
8969934d | 181 | sim_do_commandf (sd, "memory-region 0x200,0xffe00"); |
3346cfda NC |
182 | if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0xfffe, 1) == 0) |
183 | sim_do_commandf (sd, "memory-region 0xfffe,2"); | |
184 | if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0x10000, 1) == 0) | |
185 | sim_do_commandf (sd, "memory-region 0x10000,0x100000"); | |
186 | ||
187 | /* Check for/establish the a reference program image. */ | |
188 | if (sim_analyze_program (sd, | |
189 | (STATE_PROG_ARGV (sd) != NULL | |
190 | ? *STATE_PROG_ARGV (sd) | |
191 | : NULL), abfd) != SIM_RC_OK) | |
192 | { | |
193 | sim_state_free (sd); | |
194 | return 0; | |
195 | } | |
196 | ||
197 | prog_bfd = sim_load_file (sd, argv[0], callback, | |
198 | "the program", | |
199 | STATE_PROG_BFD (sd), | |
200 | 0 /* verbose */, | |
201 | 1 /* use LMA instead of VMA */, | |
202 | loader_write_mem); | |
203 | if (prog_bfd == NULL) | |
204 | { | |
205 | sim_state_free (sd); | |
206 | return 0; | |
207 | } | |
208 | ||
209 | /* Establish any remaining configuration options. */ | |
210 | if (sim_config (sd) != SIM_RC_OK) | |
211 | { | |
212 | sim_state_free (sd); | |
213 | return 0; | |
214 | } | |
215 | ||
216 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
217 | { | |
218 | sim_state_free (sd); | |
219 | return 0; | |
220 | } | |
221 | ||
222 | /* CPU specific initialization. */ | |
223 | assert (MAX_NR_PROCESSORS == 1); | |
224 | msp430_initialize_cpu (sd, MSP430_CPU (sd)); | |
225 | ||
226 | msp430_trace_init (STATE_PROG_BFD (sd)); | |
227 | ||
228 | MSP430_CPU (sd)->state.cio_breakpoint = lookup_symbol (sd, "C$$IO$$"); | |
229 | MSP430_CPU (sd)->state.cio_buffer = lookup_symbol (sd, "__CIOBUF__"); | |
230 | if (MSP430_CPU (sd)->state.cio_buffer == -1) | |
231 | MSP430_CPU (sd)->state.cio_buffer = lookup_symbol (sd, "_CIOBUF_"); | |
232 | ||
233 | return sd; | |
234 | } | |
235 | ||
236 | void | |
237 | sim_close (SIM_DESC sd, | |
238 | int quitting) | |
239 | { | |
240 | free (STATE_SYMBOL_TABLE (sd)); | |
241 | sim_state_free (sd); | |
242 | } | |
243 | ||
244 | SIM_RC | |
245 | sim_create_inferior (SIM_DESC sd, | |
246 | struct bfd *abfd, | |
247 | char **argv, | |
248 | char **env) | |
249 | { | |
250 | unsigned char resetv[2]; | |
251 | int c; | |
252 | int new_pc; | |
253 | ||
7b0278dc | 254 | /* Set the PC to the default reset vector if available. */ |
3346cfda | 255 | c = sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, resetv, 0xfffe, 2); |
3346cfda | 256 | new_pc = resetv[0] + 256 * resetv[1]; |
7b0278dc MF |
257 | |
258 | /* If the reset vector isn't initialized, then use the ELF entry. */ | |
259 | if (abfd != NULL && !new_pc) | |
260 | new_pc = bfd_get_start_address (abfd); | |
261 | ||
3346cfda NC |
262 | sim_pc_set (MSP430_CPU (sd), new_pc); |
263 | msp430_pc_store (MSP430_CPU (sd), new_pc); | |
264 | ||
265 | return SIM_RC_OK; | |
266 | } | |
267 | ||
268 | typedef struct | |
269 | { | |
270 | SIM_DESC sd; | |
271 | int gb_addr; | |
272 | } Get_Byte_Local_Data; | |
273 | ||
274 | static int | |
275 | msp430_getbyte (void *vld) | |
276 | { | |
277 | Get_Byte_Local_Data *ld = (Get_Byte_Local_Data *)vld; | |
278 | char buf[1]; | |
279 | SIM_DESC sd = ld->sd; | |
280 | ||
281 | sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, ld->gb_addr, 1); | |
282 | ld->gb_addr ++; | |
283 | return buf[0]; | |
284 | } | |
285 | ||
286 | #define REG(N) MSP430_CPU (sd)->state.regs[(N)] | |
287 | #define PC REG(MSR_PC) | |
288 | #define SP REG(MSR_SP) | |
289 | #define SR REG(MSR_SR) | |
290 | ||
291 | static const char * | |
292 | register_names[] = | |
293 | { | |
294 | "PC", "SP", "SR", "CG", "R4", "R5", "R6", "R7", "R8", | |
295 | "R9", "R10", "R11", "R12", "R13", "R14", "R15" | |
296 | }; | |
297 | ||
298 | static void | |
299 | trace_reg_put (SIM_DESC sd, int n, unsigned int v) | |
300 | { | |
301 | if (TRACE_VPU_P (MSP430_CPU (sd))) | |
302 | trace_generic (sd, MSP430_CPU (sd), TRACE_VPU_IDX, | |
303 | "PUT: %#x -> %s", v, register_names [n]); | |
304 | REG (n) = v; | |
305 | } | |
306 | ||
307 | static unsigned int | |
308 | trace_reg_get (SIM_DESC sd, int n) | |
309 | { | |
310 | if (TRACE_VPU_P (MSP430_CPU (sd))) | |
311 | trace_generic (sd, MSP430_CPU (sd), TRACE_VPU_IDX, | |
312 | "GET: %s -> %#x", register_names [n], REG (n)); | |
313 | return REG (n); | |
314 | } | |
315 | ||
316 | #define REG_PUT(N,V) trace_reg_put (sd, N, V) | |
317 | #define REG_GET(N) trace_reg_get (sd, N) | |
318 | ||
8969934d | 319 | /* Hardware multiply (and accumulate) support. */ |
8969934d NC |
320 | |
321 | static unsigned int | |
322 | zero_ext (unsigned int v, unsigned int bits) | |
323 | { | |
324 | v &= ((1 << bits) - 1); | |
325 | return v; | |
326 | } | |
327 | ||
a7da346e DD |
328 | static signed long long |
329 | sign_ext (signed long long v, unsigned int bits) | |
8969934d | 330 | { |
a7da346e DD |
331 | signed long long sb = 1LL << (bits-1); /* Sign bit. */ |
332 | signed long long mb = (1LL << (bits-1)) - 1LL; /* Mantissa bits. */ | |
8969934d NC |
333 | |
334 | if (v & sb) | |
335 | v = v | ~mb; | |
336 | else | |
337 | v = v & mb; | |
338 | return v; | |
339 | } | |
340 | ||
3346cfda NC |
341 | static int |
342 | get_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n) | |
343 | { | |
344 | MSP430_Opcode_Operand *op = opc->op + n; | |
345 | int rv; | |
346 | int addr; | |
347 | unsigned char buf[4]; | |
348 | int incval = 0; | |
349 | ||
350 | switch (op->type) | |
351 | { | |
352 | case MSP430_Operand_Immediate: | |
353 | rv = op->addend; | |
354 | break; | |
355 | case MSP430_Operand_Register: | |
356 | rv = REG_GET (op->reg); | |
357 | break; | |
358 | case MSP430_Operand_Indirect: | |
359 | case MSP430_Operand_Indirect_Postinc: | |
360 | addr = op->addend; | |
361 | if (op->reg != MSR_None) | |
362 | { | |
363 | int reg; | |
364 | /* Index values are signed, but the sum is limited to 16 | |
365 | bits if the register < 64k, for MSP430 compatibility in | |
366 | MSP430X chips. */ | |
367 | if (addr & 0x8000) | |
368 | addr |= -1 << 16; | |
369 | reg = REG_GET (op->reg); | |
370 | addr += reg; | |
371 | if (reg < 0x10000 && ! opc->ofs_430x) | |
372 | addr &= 0xffff; | |
373 | } | |
374 | addr &= 0xfffff; | |
375 | switch (opc->size) | |
376 | { | |
377 | case 8: | |
378 | sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, addr, 1); | |
379 | rv = buf[0]; | |
380 | break; | |
381 | case 16: | |
382 | sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, addr, 2); | |
383 | rv = buf[0] | (buf[1] << 8); | |
384 | break; | |
385 | case 20: | |
386 | case 32: | |
387 | sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, addr, 4); | |
388 | rv = buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24); | |
389 | break; | |
390 | default: | |
391 | assert (! opc->size); | |
392 | break; | |
393 | } | |
394 | #if 0 | |
395 | /* Hack - MSP430X5438 serial port status register. */ | |
396 | if (addr == 0x5dd) | |
397 | rv = 2; | |
398 | #endif | |
8969934d NC |
399 | if (addr >= 0x130 && addr <= 0x15B) |
400 | { | |
401 | switch (addr) | |
402 | { | |
403 | case 0x13A: | |
180eb063 | 404 | switch (HWMULT (sd, hwmult_type)) |
aef392c4 NC |
405 | { |
406 | case UNSIGN_MAC_32: | |
180eb063 NC |
407 | case UNSIGN_32: |
408 | rv = zero_ext (HWMULT (sd, hwmult_result), 16); | |
409 | break; | |
aef392c4 | 410 | case SIGN_MAC_32: |
180eb063 NC |
411 | case SIGN_32: |
412 | rv = sign_ext (HWMULT (sd, hwmult_signed_result), 16); | |
413 | break; | |
aef392c4 | 414 | } |
8969934d NC |
415 | break; |
416 | ||
417 | case 0x13C: | |
180eb063 | 418 | switch (HWMULT (sd, hwmult_type)) |
8969934d | 419 | { |
aef392c4 | 420 | case UNSIGN_MAC_32: |
8969934d | 421 | case UNSIGN_32: |
180eb063 | 422 | rv = zero_ext (HWMULT (sd, hwmult_result) >> 16, 16); |
8969934d NC |
423 | break; |
424 | ||
aef392c4 | 425 | case SIGN_MAC_32: |
8969934d | 426 | case SIGN_32: |
180eb063 | 427 | rv = sign_ext (HWMULT (sd, hwmult_signed_result) >> 16, 16); |
8969934d NC |
428 | break; |
429 | } | |
430 | break; | |
431 | ||
432 | case 0x13E: | |
180eb063 | 433 | switch (HWMULT (sd, hwmult_type)) |
8969934d NC |
434 | { |
435 | case UNSIGN_32: | |
436 | rv = 0; | |
437 | break; | |
438 | case SIGN_32: | |
180eb063 | 439 | rv = HWMULT (sd, hwmult_signed_result) < 0 ? -1 : 0; |
8969934d NC |
440 | break; |
441 | case UNSIGN_MAC_32: | |
442 | rv = 0; /* FIXME: Should be carry of last accumulate. */ | |
443 | break; | |
444 | case SIGN_MAC_32: | |
180eb063 | 445 | rv = HWMULT (sd, hwmult_signed_accumulator) < 0 ? -1 : 0; |
8969934d NC |
446 | break; |
447 | } | |
448 | break; | |
449 | ||
450 | case 0x154: | |
180eb063 | 451 | rv = zero_ext (HWMULT (sd, hw32mult_result), 16); |
8969934d NC |
452 | break; |
453 | ||
454 | case 0x156: | |
180eb063 | 455 | rv = zero_ext (HWMULT (sd, hw32mult_result) >> 16, 16); |
8969934d NC |
456 | break; |
457 | ||
458 | case 0x158: | |
180eb063 | 459 | rv = zero_ext (HWMULT (sd, hw32mult_result) >> 32, 16); |
8969934d NC |
460 | break; |
461 | ||
462 | case 0x15A: | |
180eb063 | 463 | switch (HWMULT (sd, hw32mult_type)) |
8969934d | 464 | { |
180eb063 NC |
465 | case UNSIGN_64: rv = zero_ext (HWMULT (sd, hw32mult_result) >> 48, 16); break; |
466 | case SIGN_64: rv = sign_ext (HWMULT (sd, hw32mult_result) >> 48, 16); break; | |
8969934d NC |
467 | } |
468 | break; | |
469 | ||
470 | default: | |
471 | fprintf (stderr, "unimplemented HW MULT read!\n"); | |
472 | break; | |
473 | } | |
474 | } | |
475 | ||
3346cfda NC |
476 | if (TRACE_MEMORY_P (MSP430_CPU (sd))) |
477 | trace_generic (sd, MSP430_CPU (sd), TRACE_MEMORY_IDX, | |
478 | "GET: [%#x].%d -> %#x", addr, opc->size, rv); | |
479 | break; | |
480 | default: | |
481 | fprintf (stderr, "invalid operand %d type %d\n", n, op->type); | |
482 | abort (); | |
483 | } | |
484 | ||
485 | switch (opc->size) | |
486 | { | |
487 | case 8: | |
488 | rv &= 0xff; | |
489 | incval = 1; | |
490 | break; | |
491 | case 16: | |
492 | rv &= 0xffff; | |
493 | incval = 2; | |
494 | break; | |
495 | case 20: | |
496 | rv &= 0xfffff; | |
497 | incval = 4; | |
498 | break; | |
499 | case 32: | |
500 | rv &= 0xffffffff; | |
501 | incval = 4; | |
502 | break; | |
503 | } | |
504 | ||
505 | if (op->type == MSP430_Operand_Indirect_Postinc) | |
506 | REG_PUT (op->reg, REG_GET (op->reg) + incval); | |
507 | ||
508 | return rv; | |
509 | } | |
510 | ||
511 | static int | |
512 | put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val) | |
513 | { | |
514 | MSP430_Opcode_Operand *op = opc->op + n; | |
515 | int rv; | |
516 | int addr; | |
517 | unsigned char buf[4]; | |
518 | int incval = 0; | |
519 | ||
520 | switch (opc->size) | |
521 | { | |
522 | case 8: | |
523 | val &= 0xff; | |
524 | break; | |
525 | case 16: | |
526 | val &= 0xffff; | |
527 | break; | |
528 | case 20: | |
529 | val &= 0xfffff; | |
530 | break; | |
531 | case 32: | |
532 | val &= 0xffffffff; | |
533 | break; | |
534 | } | |
535 | ||
536 | switch (op->type) | |
537 | { | |
538 | case MSP430_Operand_Register: | |
539 | REG (op->reg) = val; | |
540 | REG_PUT (op->reg, val); | |
541 | break; | |
542 | case MSP430_Operand_Indirect: | |
543 | case MSP430_Operand_Indirect_Postinc: | |
544 | addr = op->addend; | |
545 | if (op->reg != MSR_None) | |
546 | { | |
547 | int reg; | |
548 | /* Index values are signed, but the sum is limited to 16 | |
549 | bits if the register < 64k, for MSP430 compatibility in | |
550 | MSP430X chips. */ | |
551 | if (addr & 0x8000) | |
552 | addr |= -1 << 16; | |
553 | reg = REG_GET (op->reg); | |
554 | addr += reg; | |
555 | if (reg < 0x10000) | |
556 | addr &= 0xffff; | |
557 | } | |
558 | addr &= 0xfffff; | |
559 | ||
560 | if (TRACE_MEMORY_P (MSP430_CPU (sd))) | |
561 | trace_generic (sd, MSP430_CPU (sd), TRACE_MEMORY_IDX, | |
562 | "PUT: [%#x].%d <- %#x", addr, opc->size, val); | |
563 | #if 0 | |
564 | /* Hack - MSP430X5438 serial port transmit register. */ | |
565 | if (addr == 0x5ce) | |
566 | putchar (val); | |
567 | #endif | |
8969934d NC |
568 | if (addr >= 0x130 && addr <= 0x15B) |
569 | { | |
570 | signed int a,b; | |
571 | ||
572 | /* Hardware Multiply emulation. */ | |
573 | assert (opc->size == 16); | |
574 | ||
575 | switch (addr) | |
576 | { | |
180eb063 NC |
577 | case 0x130: HWMULT (sd, hwmult_op1) = val; HWMULT (sd, hwmult_type) = UNSIGN_32; break; |
578 | case 0x132: HWMULT (sd, hwmult_op1) = val; HWMULT (sd, hwmult_type) = SIGN_32; break; | |
579 | case 0x134: HWMULT (sd, hwmult_op1) = val; HWMULT (sd, hwmult_type) = UNSIGN_MAC_32; break; | |
580 | case 0x136: HWMULT (sd, hwmult_op1) = val; HWMULT (sd, hwmult_type) = SIGN_MAC_32; break; | |
8969934d | 581 | |
180eb063 NC |
582 | case 0x138: HWMULT (sd, hwmult_op2) = val; |
583 | switch (HWMULT (sd, hwmult_type)) | |
8969934d NC |
584 | { |
585 | case UNSIGN_32: | |
180eb063 NC |
586 | HWMULT (sd, hwmult_result) = HWMULT (sd, hwmult_op1) * HWMULT (sd, hwmult_op2); |
587 | HWMULT (sd, hwmult_signed_result) = (signed) HWMULT (sd, hwmult_result); | |
588 | HWMULT (sd, hwmult_accumulator) = HWMULT (sd, hwmult_signed_accumulator) = 0; | |
8969934d NC |
589 | break; |
590 | ||
591 | case SIGN_32: | |
180eb063 NC |
592 | a = sign_ext (HWMULT (sd, hwmult_op1), 16); |
593 | b = sign_ext (HWMULT (sd, hwmult_op2), 16); | |
594 | HWMULT (sd, hwmult_signed_result) = a * b; | |
595 | HWMULT (sd, hwmult_result) = (unsigned) HWMULT (sd, hwmult_signed_result); | |
596 | HWMULT (sd, hwmult_accumulator) = HWMULT (sd, hwmult_signed_accumulator) = 0; | |
8969934d NC |
597 | break; |
598 | ||
599 | case UNSIGN_MAC_32: | |
180eb063 NC |
600 | HWMULT (sd, hwmult_accumulator) += HWMULT (sd, hwmult_op1) * HWMULT (sd, hwmult_op2); |
601 | HWMULT (sd, hwmult_signed_accumulator) += HWMULT (sd, hwmult_op1) * HWMULT (sd, hwmult_op2); | |
602 | HWMULT (sd, hwmult_result) = HWMULT (sd, hwmult_accumulator); | |
603 | HWMULT (sd, hwmult_signed_result) = HWMULT (sd, hwmult_signed_accumulator); | |
8969934d NC |
604 | break; |
605 | ||
606 | case SIGN_MAC_32: | |
180eb063 NC |
607 | a = sign_ext (HWMULT (sd, hwmult_op1), 16); |
608 | b = sign_ext (HWMULT (sd, hwmult_op2), 16); | |
609 | HWMULT (sd, hwmult_accumulator) += a * b; | |
610 | HWMULT (sd, hwmult_signed_accumulator) += a * b; | |
611 | HWMULT (sd, hwmult_result) = HWMULT (sd, hwmult_accumulator); | |
612 | HWMULT (sd, hwmult_signed_result) = HWMULT (sd, hwmult_signed_accumulator); | |
8969934d NC |
613 | break; |
614 | } | |
615 | break; | |
616 | ||
aef392c4 NC |
617 | case 0x13a: |
618 | /* Copy into LOW result... */ | |
180eb063 | 619 | switch (HWMULT (sd, hwmult_type)) |
aef392c4 NC |
620 | { |
621 | case UNSIGN_MAC_32: | |
622 | case UNSIGN_32: | |
180eb063 NC |
623 | HWMULT (sd, hwmult_accumulator) = HWMULT (sd, hwmult_result) = zero_ext (val, 16); |
624 | HWMULT (sd, hwmult_signed_accumulator) = sign_ext (val, 16); | |
aef392c4 NC |
625 | break; |
626 | case SIGN_MAC_32: | |
627 | case SIGN_32: | |
180eb063 NC |
628 | HWMULT (sd, hwmult_signed_accumulator) = HWMULT (sd, hwmult_result) = sign_ext (val, 16); |
629 | HWMULT (sd, hwmult_accumulator) = zero_ext (val, 16); | |
aef392c4 NC |
630 | break; |
631 | } | |
632 | break; | |
633 | ||
180eb063 NC |
634 | case 0x140: |
635 | HWMULT (sd, hw32mult_op1) = val; | |
636 | HWMULT (sd, hw32mult_type) = UNSIGN_64; | |
637 | break; | |
638 | case 0x142: | |
639 | HWMULT (sd, hw32mult_op1) = (HWMULT (sd, hw32mult_op1) & 0xFFFF) | (val << 16); | |
640 | break; | |
641 | case 0x144: | |
642 | HWMULT (sd, hw32mult_op1) = val; | |
643 | HWMULT (sd, hw32mult_type) = SIGN_64; | |
644 | break; | |
645 | case 0x146: | |
646 | HWMULT (sd, hw32mult_op1) = (HWMULT (sd, hw32mult_op1) & 0xFFFF) | (val << 16); | |
647 | break; | |
648 | case 0x150: | |
649 | HWMULT (sd, hw32mult_op2) = val; | |
650 | break; | |
651 | ||
652 | case 0x152: | |
653 | HWMULT (sd, hw32mult_op2) = (HWMULT (sd, hw32mult_op2) & 0xFFFF) | (val << 16); | |
654 | switch (HWMULT (sd, hw32mult_type)) | |
8969934d NC |
655 | { |
656 | case UNSIGN_64: | |
180eb063 | 657 | HWMULT (sd, hw32mult_result) = HWMULT (sd, hw32mult_op1) * HWMULT (sd, hw32mult_op2); |
8969934d NC |
658 | break; |
659 | case SIGN_64: | |
180eb063 NC |
660 | HWMULT (sd, hw32mult_result) = sign_ext (HWMULT (sd, hw32mult_op1), 32) |
661 | * sign_ext (HWMULT (sd, hw32mult_op2), 32); | |
8969934d NC |
662 | break; |
663 | } | |
664 | break; | |
665 | ||
666 | default: | |
667 | fprintf (stderr, "unimplemented HW MULT write to %x!\n", addr); | |
668 | break; | |
669 | } | |
670 | } | |
671 | ||
3346cfda NC |
672 | switch (opc->size) |
673 | { | |
674 | case 8: | |
675 | buf[0] = val; | |
676 | sim_core_write_buffer (sd, MSP430_CPU (sd), write_map, buf, addr, 1); | |
677 | break; | |
678 | case 16: | |
679 | buf[0] = val; | |
680 | buf[1] = val >> 8; | |
681 | sim_core_write_buffer (sd, MSP430_CPU (sd), write_map, buf, addr, 2); | |
682 | break; | |
683 | case 20: | |
684 | case 32: | |
685 | buf[0] = val; | |
686 | buf[1] = val >> 8; | |
687 | buf[2] = val >> 16; | |
688 | buf[3] = val >> 24; | |
689 | sim_core_write_buffer (sd, MSP430_CPU (sd), write_map, buf, addr, 4); | |
690 | break; | |
691 | default: | |
692 | assert (! opc->size); | |
693 | break; | |
694 | } | |
695 | break; | |
696 | default: | |
697 | fprintf (stderr, "invalid operand %d type %d\n", n, op->type); | |
698 | abort (); | |
699 | } | |
700 | ||
701 | switch (opc->size) | |
702 | { | |
703 | case 8: | |
704 | rv &= 0xff; | |
705 | incval = 1; | |
706 | break; | |
707 | case 16: | |
708 | rv &= 0xffff; | |
709 | incval = 2; | |
710 | break; | |
711 | case 20: | |
712 | rv &= 0xfffff; | |
713 | incval = 4; | |
714 | break; | |
715 | case 32: | |
716 | rv &= 0xffffffff; | |
717 | incval = 4; | |
718 | break; | |
719 | } | |
720 | ||
721 | if (op->type == MSP430_Operand_Indirect_Postinc) | |
722 | { | |
723 | int new_val = REG_GET (op->reg) + incval; | |
724 | /* SP is always word-aligned. */ | |
725 | if (op->reg == MSR_SP && (new_val & 1)) | |
726 | new_val ++; | |
727 | REG_PUT (op->reg, new_val); | |
728 | } | |
729 | ||
730 | return rv; | |
731 | } | |
732 | ||
733 | static void | |
734 | mem_put_val (SIM_DESC sd, int addr, int val, int bits) | |
735 | { | |
736 | MSP430_Opcode_Decoded opc; | |
737 | ||
738 | opc.size = bits; | |
739 | opc.op[0].type = MSP430_Operand_Indirect; | |
740 | opc.op[0].addend = addr; | |
741 | opc.op[0].reg = MSR_None; | |
742 | put_op (sd, &opc, 0, val); | |
743 | } | |
744 | ||
745 | static int | |
746 | mem_get_val (SIM_DESC sd, int addr, int bits) | |
747 | { | |
748 | MSP430_Opcode_Decoded opc; | |
749 | ||
750 | opc.size = bits; | |
751 | opc.op[0].type = MSP430_Operand_Indirect; | |
752 | opc.op[0].addend = addr; | |
753 | opc.op[0].reg = MSR_None; | |
754 | return get_op (sd, &opc, 0); | |
755 | } | |
756 | ||
757 | #define CIO_OPEN (0xF0) | |
758 | #define CIO_CLOSE (0xF1) | |
759 | #define CIO_READ (0xF2) | |
760 | #define CIO_WRITE (0xF3) | |
761 | #define CIO_LSEEK (0xF4) | |
762 | #define CIO_UNLINK (0xF5) | |
763 | #define CIO_GETENV (0xF6) | |
764 | #define CIO_RENAME (0xF7) | |
765 | #define CIO_GETTIME (0xF8) | |
766 | #define CIO_GETCLK (0xF9) | |
767 | #define CIO_SYNC (0xFF) | |
768 | ||
769 | #define CIO_I(n) (parms[(n)] + parms[(n)+1] * 256) | |
770 | #define CIO_L(n) (parms[(n)] + parms[(n)+1] * 256 \ | |
771 | + parms[(n)+2] * 65536 + parms[(n)+3] * 16777216) | |
772 | ||
773 | static void | |
774 | msp430_cio (SIM_DESC sd) | |
775 | { | |
776 | /* A block of data at __CIOBUF__ describes the I/O operation to | |
777 | perform. */ | |
778 | ||
779 | unsigned char raw_parms[13]; | |
780 | unsigned char parms[8]; | |
781 | long length; | |
782 | int command; | |
783 | unsigned char buffer[512]; | |
784 | long ret_buflen = 0; | |
785 | long fd, addr, len, rv; | |
786 | ||
787 | sim_core_read_buffer (sd, MSP430_CPU (sd), 0, parms, | |
788 | MSP430_CPU (sd)->state.cio_buffer, 5); | |
789 | length = CIO_I (0); | |
790 | command = parms[2]; | |
791 | ||
792 | sim_core_read_buffer (sd, MSP430_CPU (sd), 0, parms, | |
793 | MSP430_CPU (sd)->state.cio_buffer + 3, 8); | |
794 | ||
795 | sim_core_read_buffer (sd, MSP430_CPU (sd), 0, buffer, | |
796 | MSP430_CPU (sd)->state.cio_buffer + 11, length); | |
797 | ||
798 | switch (command) | |
799 | { | |
800 | case CIO_WRITE: | |
801 | fd = CIO_I (0); | |
802 | len = CIO_I (2); | |
803 | ||
804 | rv = write (fd, buffer, len); | |
805 | parms[0] = rv & 0xff; | |
806 | parms[1] = rv >> 8; | |
807 | ||
808 | break; | |
809 | } | |
810 | ||
811 | sim_core_write_buffer (sd, MSP430_CPU (sd), 0, parms, | |
812 | MSP430_CPU (sd)->state.cio_buffer + 4, 8); | |
813 | if (ret_buflen) | |
814 | sim_core_write_buffer (sd, MSP430_CPU (sd), 0, buffer, | |
815 | MSP430_CPU (sd)->state.cio_buffer + 12, ret_buflen); | |
816 | } | |
817 | ||
818 | #define SRC get_op (sd, opcode, 1) | |
819 | #define DSRC get_op (sd, opcode, 0) | |
820 | #define DEST(V) put_op (sd, opcode, 0, (V)) | |
821 | ||
822 | static int | |
823 | msp430_dis_read (bfd_vma memaddr, | |
824 | bfd_byte *myaddr, | |
825 | unsigned int length, | |
826 | struct disassemble_info *dinfo) | |
827 | { | |
828 | SIM_DESC sd = dinfo->private_data; | |
829 | sim_core_read_buffer (sd, MSP430_CPU (sd), 0, myaddr, memaddr, length); | |
830 | return 0; | |
831 | } | |
832 | ||
833 | #define DO_ALU(OP,SOP,MORE) \ | |
834 | { \ | |
835 | int s1 = DSRC; \ | |
836 | int s2 = SRC; \ | |
837 | int result = s1 OP s2 MORE; \ | |
838 | if (TRACE_ALU_P (MSP430_CPU (sd))) \ | |
839 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, \ | |
840 | "ALU: %#x %s %#x %s = %#x", s1, SOP, s2, #MORE, result); \ | |
841 | DEST (result); \ | |
842 | } | |
843 | ||
844 | #define SIGN (1 << (opcode->size - 1)) | |
845 | #define POS(x) (((x) & SIGN) ? 0 : 1) | |
846 | #define NEG(x) (((x) & SIGN) ? 1 : 0) | |
847 | ||
3346cfda NC |
848 | #define SX(v) sign_ext (v, opcode->size) |
849 | #define ZX(v) zero_ext (v, opcode->size) | |
850 | ||
851 | static char * | |
852 | flags2string (int f) | |
853 | { | |
854 | static char buf[2][6]; | |
855 | static int bi = 0; | |
856 | char *bp = buf[bi]; | |
857 | ||
858 | bi = (bi + 1) % 2; | |
859 | ||
860 | bp[0] = f & MSP430_FLAG_V ? 'V' : '-'; | |
861 | bp[1] = f & MSP430_FLAG_N ? 'N' : '-'; | |
862 | bp[2] = f & MSP430_FLAG_Z ? 'Z' : '-'; | |
863 | bp[3] = f & MSP430_FLAG_C ? 'C' : '-'; | |
864 | bp[4] = 0; | |
865 | return bp; | |
866 | } | |
867 | ||
868 | /* Random number that won't show up in our usual logic. */ | |
869 | #define MAGIC_OVERFLOW 0x55000F | |
870 | ||
871 | static void | |
872 | do_flags (SIM_DESC sd, | |
873 | MSP430_Opcode_Decoded *opcode, | |
874 | int vnz_val, /* Signed result. */ | |
875 | int carry, | |
876 | int overflow) | |
877 | { | |
878 | int f = SR; | |
879 | int new_f = 0; | |
880 | int signbit = 1 << (opcode->size - 1); | |
881 | ||
882 | f &= ~opcode->flags_0; | |
883 | f &= ~opcode->flags_set; | |
884 | f |= opcode->flags_1; | |
885 | ||
886 | if (vnz_val & signbit) | |
887 | new_f |= MSP430_FLAG_N; | |
888 | if (! (vnz_val & ((signbit << 1) - 1))) | |
889 | new_f |= MSP430_FLAG_Z; | |
890 | if (overflow == MAGIC_OVERFLOW) | |
891 | { | |
892 | if (vnz_val != SX (vnz_val)) | |
893 | new_f |= MSP430_FLAG_V; | |
894 | } | |
895 | else | |
896 | if (overflow) | |
897 | new_f |= MSP430_FLAG_V; | |
898 | if (carry) | |
899 | new_f |= MSP430_FLAG_C; | |
900 | ||
901 | new_f = f | (new_f & opcode->flags_set); | |
902 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
903 | { | |
904 | if (SR != new_f) | |
905 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
906 | "FLAGS: %s -> %s", flags2string (SR), | |
907 | flags2string (new_f)); | |
908 | else | |
909 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
910 | "FLAGS: %s", flags2string (new_f)); | |
911 | } | |
912 | SR = new_f; | |
913 | } | |
914 | ||
915 | #define FLAGS(vnz,c) do_flags (sd, opcode, vnz, c, MAGIC_OVERFLOW) | |
916 | #define FLAGSV(vnz,c,v) do_flags (sd, opcode, vnz, c, v) | |
917 | ||
918 | /* These two assume unsigned 16-bit (four digit) words. | |
919 | Mask off unwanted bits for byte operations. */ | |
920 | ||
921 | static int | |
922 | bcd_to_binary (int v) | |
923 | { | |
924 | int r = ( ((v >> 0) & 0xf) * 1 | |
925 | + ((v >> 4) & 0xf) * 10 | |
926 | + ((v >> 8) & 0xf) * 100 | |
927 | + ((v >> 12) & 0xf) * 1000); | |
928 | return r; | |
929 | } | |
930 | ||
931 | static int | |
932 | binary_to_bcd (int v) | |
933 | { | |
934 | int r = ( ((v / 1) % 10) << 0 | |
935 | | ((v / 10) % 10) << 4 | |
936 | | ((v / 100) % 10) << 8 | |
937 | | ((v / 1000) % 10) << 12); | |
938 | return r; | |
939 | } | |
940 | ||
941 | static int | |
942 | syscall_read_mem (host_callback *cb, struct cb_syscall *sc, | |
943 | unsigned long taddr, char *buf, int bytes) | |
944 | { | |
945 | SIM_DESC sd = (SIM_DESC) sc->p1; | |
946 | SIM_CPU *cpu = (SIM_CPU *) sc->p2; | |
947 | ||
948 | return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); | |
949 | } | |
950 | ||
951 | static int | |
952 | syscall_write_mem (host_callback *cb, struct cb_syscall *sc, | |
953 | unsigned long taddr, const char *buf, int bytes) | |
954 | { | |
955 | SIM_DESC sd = (SIM_DESC) sc->p1; | |
956 | SIM_CPU *cpu = (SIM_CPU *) sc->p2; | |
957 | ||
958 | return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); | |
959 | } | |
960 | ||
961 | static const char * | |
962 | cond_string (int cond) | |
963 | { | |
964 | switch (cond) | |
965 | { | |
966 | case MSC_nz: | |
967 | return "NZ"; | |
968 | case MSC_z: | |
969 | return "Z"; | |
970 | case MSC_nc: | |
971 | return "NC"; | |
972 | case MSC_c: | |
973 | return "C"; | |
974 | case MSC_n: | |
975 | return "N"; | |
976 | case MSC_ge: | |
977 | return "GE"; | |
978 | case MSC_l: | |
979 | return "L"; | |
980 | case MSC_true: | |
981 | return "MP"; | |
982 | default: | |
983 | return "??"; | |
984 | } | |
985 | } | |
986 | ||
987 | /* Checks a CALL to address CALL_ADDR. If this is a special | |
988 | syscall address then the call is simulated and non-zero is | |
989 | returned. Otherwise 0 is returned. */ | |
990 | ||
991 | static int | |
992 | maybe_perform_syscall (SIM_DESC sd, int call_addr) | |
993 | { | |
994 | if (call_addr == 0x00160) | |
995 | { | |
996 | int i; | |
997 | ||
998 | for (i = 0; i < 16; i++) | |
999 | { | |
1000 | if (i % 4 == 0) | |
1001 | fprintf (stderr, "\t"); | |
1002 | fprintf (stderr, "R%-2d %05x ", i, MSP430_CPU (sd)->state.regs[i]); | |
1003 | if (i % 4 == 3) | |
1004 | { | |
1005 | int sp = SP + (3 - (i / 4)) * 2; | |
1006 | unsigned char buf[2]; | |
1007 | ||
1008 | sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, sp, 2); | |
1009 | ||
1010 | fprintf (stderr, "\tSP%+d: %04x", sp - SP, | |
1011 | buf[0] + buf[1] * 256); | |
1012 | ||
1013 | if (i / 4 == 0) | |
1014 | { | |
1015 | int flags = SR; | |
1016 | ||
1017 | fprintf (stderr, flags & 0x100 ? " V" : " -"); | |
1018 | fprintf (stderr, flags & 0x004 ? "N" : "-"); | |
1019 | fprintf (stderr, flags & 0x002 ? "Z" : "-"); | |
1020 | fprintf (stderr, flags & 0x001 ? "C" : "-"); | |
1021 | } | |
1022 | ||
1023 | fprintf (stderr, "\n"); | |
1024 | } | |
1025 | } | |
1026 | return 1; | |
1027 | } | |
1028 | ||
1029 | if ((call_addr & ~0x3f) == 0x00180) | |
1030 | { | |
1031 | /* Syscall! */ | |
1032 | int syscall_num = call_addr & 0x3f; | |
1033 | host_callback *cb = STATE_CALLBACK (sd); | |
1034 | CB_SYSCALL sc; | |
1035 | ||
1036 | CB_SYSCALL_INIT (&sc); | |
1037 | ||
1038 | sc.func = syscall_num; | |
1039 | sc.arg1 = MSP430_CPU (sd)->state.regs[12]; | |
1040 | sc.arg2 = MSP430_CPU (sd)->state.regs[13]; | |
1041 | sc.arg3 = MSP430_CPU (sd)->state.regs[14]; | |
1042 | sc.arg4 = MSP430_CPU (sd)->state.regs[15]; | |
1043 | ||
1044 | if (TRACE_SYSCALL_P (MSP430_CPU (sd))) | |
1045 | { | |
1046 | const char *syscall_name = "*unknown*"; | |
1047 | ||
1048 | switch (syscall_num) | |
1049 | { | |
1050 | case TARGET_SYS_exit: | |
1051 | syscall_name = "exit(%d)"; | |
1052 | break; | |
1053 | case TARGET_SYS_open: | |
1054 | syscall_name = "open(%#x,%#x)"; | |
1055 | break; | |
1056 | case TARGET_SYS_close: | |
1057 | syscall_name = "close(%d)"; | |
1058 | break; | |
1059 | case TARGET_SYS_read: | |
1060 | syscall_name = "read(%d,%#x,%d)"; | |
1061 | break; | |
1062 | case TARGET_SYS_write: | |
1063 | syscall_name = "write(%d,%#x,%d)"; | |
1064 | break; | |
1065 | } | |
1066 | trace_generic (sd, MSP430_CPU (sd), TRACE_SYSCALL_IDX, | |
1067 | syscall_name, sc.arg1, sc.arg2, sc.arg3, sc.arg4); | |
1068 | } | |
1069 | ||
1070 | /* Handle SYS_exit here. */ | |
1071 | if (syscall_num == 1) | |
1072 | { | |
1073 | sim_engine_halt (sd, MSP430_CPU (sd), NULL, | |
1074 | MSP430_CPU (sd)->state.regs[0], | |
1075 | sim_exited, sc.arg1); | |
1076 | return 1; | |
1077 | } | |
1078 | ||
1079 | sc.p1 = sd; | |
1080 | sc.p2 = MSP430_CPU (sd); | |
1081 | sc.read_mem = syscall_read_mem; | |
1082 | sc.write_mem = syscall_write_mem; | |
1083 | ||
1084 | cb_syscall (cb, &sc); | |
1085 | ||
1086 | if (TRACE_SYSCALL_P (MSP430_CPU (sd))) | |
1087 | trace_generic (sd, MSP430_CPU (sd), TRACE_SYSCALL_IDX, | |
a3271a3e | 1088 | "returns %ld", sc.result); |
3346cfda NC |
1089 | |
1090 | MSP430_CPU (sd)->state.regs[12] = sc.result; | |
1091 | return 1; | |
1092 | } | |
1093 | ||
1094 | return 0; | |
1095 | } | |
1096 | ||
1097 | static void | |
1098 | msp430_step_once (SIM_DESC sd) | |
1099 | { | |
1100 | Get_Byte_Local_Data ld; | |
1101 | unsigned char buf[100]; | |
1102 | int i; | |
1103 | int opsize; | |
1104 | unsigned int opcode_pc; | |
1105 | MSP430_Opcode_Decoded opcode_buf; | |
1106 | MSP430_Opcode_Decoded *opcode = &opcode_buf; | |
1107 | int s1, s2, result; | |
1108 | int u1, u2, uresult; | |
1109 | int c, reg; | |
1110 | int sp; | |
1111 | int carry_to_use; | |
1112 | int n_repeats; | |
1113 | int rept; | |
1114 | int op_bytes, op_bits; | |
1115 | ||
1116 | PC &= 0xfffff; | |
1117 | opcode_pc = PC; | |
1118 | ||
1119 | if (opcode_pc < 0x10) | |
1120 | { | |
1121 | fprintf (stderr, "Fault: PC(%#x) is less than 0x10\n", opcode_pc); | |
1122 | sim_engine_halt (sd, MSP430_CPU (sd), NULL, | |
1123 | MSP430_CPU (sd)->state.regs[0], | |
1124 | sim_exited, -1); | |
1125 | return; | |
1126 | } | |
1127 | ||
1128 | if (PC == MSP430_CPU (sd)->state.cio_breakpoint | |
1129 | && STATE_OPEN_KIND (sd) != SIM_OPEN_DEBUG) | |
1130 | msp430_cio (sd); | |
1131 | ||
1132 | ld.sd = sd; | |
1133 | ld.gb_addr = PC; | |
1134 | opsize = msp430_decode_opcode (MSP430_CPU (sd)->state.regs[0], | |
1135 | opcode, msp430_getbyte, &ld); | |
1136 | PC += opsize; | |
1137 | if (opsize <= 0) | |
1138 | { | |
1139 | fprintf (stderr, "Fault: undecodable opcode at %#x\n", opcode_pc); | |
1140 | sim_engine_halt (sd, MSP430_CPU (sd), NULL, | |
1141 | MSP430_CPU (sd)->state.regs[0], | |
1142 | sim_exited, -1); | |
1143 | return; | |
1144 | } | |
1145 | ||
1146 | if (opcode->repeat_reg) | |
1147 | n_repeats = (MSP430_CPU (sd)->state.regs[opcode->repeats] & 0x000f) + 1; | |
1148 | else | |
1149 | n_repeats = opcode->repeats + 1; | |
1150 | ||
1151 | op_bits = opcode->size; | |
1152 | switch (op_bits) | |
1153 | { | |
1154 | case 8: | |
1155 | op_bytes = 1; | |
1156 | break; | |
1157 | case 16: | |
1158 | op_bytes = 2; | |
1159 | break; | |
1160 | case 20: | |
1161 | case 32: | |
1162 | op_bytes = 4; | |
1163 | break; | |
1164 | } | |
1165 | ||
1166 | if (TRACE_INSN_P (MSP430_CPU (sd))) | |
1167 | { | |
1168 | disassemble_info info; | |
1169 | unsigned char b[10]; | |
1170 | ||
1171 | msp430_trace_one (opcode_pc); | |
1172 | ||
1173 | sim_core_read_buffer (sd, MSP430_CPU (sd), 0, b, opcode_pc, opsize); | |
1174 | ||
a3271a3e | 1175 | init_disassemble_info (&info, stderr, (fprintf_ftype) fprintf); |
3346cfda NC |
1176 | info.private_data = sd; |
1177 | info.read_memory_func = msp430_dis_read; | |
1178 | fprintf (stderr, "%#8x ", opcode_pc); | |
1179 | for (i = 0; i < opsize; i += 2) | |
1180 | fprintf (stderr, " %02x%02x", b[i+1], b[i]); | |
1181 | for (; i < 6; i += 2) | |
1182 | fprintf (stderr, " "); | |
1183 | fprintf (stderr, " "); | |
1184 | print_insn_msp430 (opcode_pc, &info); | |
1185 | fprintf (stderr, "\n"); | |
1186 | fflush (stdout); | |
1187 | } | |
1188 | ||
1189 | if (TRACE_ANY_P (MSP430_CPU (sd))) | |
1190 | trace_prefix (sd, MSP430_CPU (sd), NULL_CIA, opcode_pc, | |
1191 | TRACE_LINENUM_P (MSP430_CPU (sd)), NULL, 0, ""); | |
1192 | ||
1193 | carry_to_use = 0; | |
1194 | switch (opcode->id) | |
1195 | { | |
1196 | case MSO_unknown: | |
1197 | break; | |
1198 | ||
1199 | /* Double-operand instructions. */ | |
1200 | case MSO_mov: | |
1201 | if (opcode->n_bytes == 2 | |
1202 | && opcode->op[0].type == MSP430_Operand_Register | |
1203 | && opcode->op[0].reg == MSR_CG | |
1204 | && opcode->op[1].type == MSP430_Operand_Immediate | |
1205 | && opcode->op[1].addend == 0 | |
1206 | /* A 16-bit write of #0 is a NOP; an 8-bit write is a BRK. */ | |
1207 | && opcode->size == 8) | |
1208 | { | |
1209 | /* This is the designated software breakpoint instruction. */ | |
1210 | PC -= opsize; | |
1211 | sim_engine_halt (sd, MSP430_CPU (sd), NULL, | |
1212 | MSP430_CPU (sd)->state.regs[0], | |
1213 | sim_stopped, SIM_SIGTRAP); | |
1214 | ||
1215 | } | |
1216 | else | |
1217 | { | |
1218 | /* Otherwise, do the move. */ | |
1219 | for (rept = 0; rept < n_repeats; rept ++) | |
1220 | { | |
1221 | DEST (SRC); | |
1222 | } | |
1223 | } | |
1224 | break; | |
1225 | ||
1226 | case MSO_addc: | |
1227 | for (rept = 0; rept < n_repeats; rept ++) | |
1228 | { | |
1229 | carry_to_use = (SR & MSP430_FLAG_C) ? 1 : 0; | |
1230 | u1 = DSRC; | |
1231 | u2 = SRC; | |
1232 | s1 = SX (u1); | |
1233 | s2 = SX (u2); | |
1234 | uresult = u1 + u2 + carry_to_use; | |
1235 | result = s1 + s2 + carry_to_use; | |
1236 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1237 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1238 | "ADDC: %#x + %#x + %d = %#x", | |
1239 | u1, u2, carry_to_use, uresult); | |
1240 | DEST (result); | |
1241 | FLAGS (result, uresult != ZX (uresult)); | |
1242 | } | |
1243 | break; | |
1244 | ||
1245 | case MSO_add: | |
1246 | for (rept = 0; rept < n_repeats; rept ++) | |
1247 | { | |
1248 | u1 = DSRC; | |
1249 | u2 = SRC; | |
1250 | s1 = SX (u1); | |
1251 | s2 = SX (u2); | |
1252 | uresult = u1 + u2; | |
1253 | result = s1 + s2; | |
1254 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1255 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1256 | "ADD: %#x + %#x = %#x", | |
1257 | u1, u2, uresult); | |
1258 | DEST (result); | |
1259 | FLAGS (result, uresult != ZX (uresult)); | |
1260 | } | |
1261 | break; | |
1262 | ||
1263 | case MSO_subc: | |
1264 | for (rept = 0; rept < n_repeats; rept ++) | |
1265 | { | |
1266 | carry_to_use = (SR & MSP430_FLAG_C) ? 1 : 0; | |
1267 | u1 = DSRC; | |
1268 | u2 = SRC; | |
1269 | s1 = SX (u1); | |
1270 | s2 = SX (u2); | |
1271 | uresult = ZX (~u2) + u1 + carry_to_use; | |
1272 | result = s1 - s2 + (carry_to_use - 1); | |
1273 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1274 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1275 | "SUBC: %#x - %#x + %d = %#x", | |
1276 | u1, u2, carry_to_use, uresult); | |
1277 | DEST (result); | |
1278 | FLAGS (result, uresult != ZX (uresult)); | |
1279 | } | |
1280 | break; | |
1281 | ||
1282 | case MSO_sub: | |
1283 | for (rept = 0; rept < n_repeats; rept ++) | |
1284 | { | |
1285 | u1 = DSRC; | |
1286 | u2 = SRC; | |
1287 | s1 = SX (u1); | |
1288 | s2 = SX (u2); | |
1289 | uresult = ZX (~u2) + u1 + 1; | |
1290 | result = SX (uresult); | |
1291 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1292 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1293 | "SUB: %#x - %#x = %#x", | |
1294 | u1, u2, uresult); | |
1295 | DEST (result); | |
1296 | FLAGS (result, uresult != ZX (uresult)); | |
1297 | } | |
1298 | break; | |
1299 | ||
1300 | case MSO_cmp: | |
1301 | for (rept = 0; rept < n_repeats; rept ++) | |
1302 | { | |
1303 | u1 = DSRC; | |
1304 | u2 = SRC; | |
1305 | s1 = SX (u1); | |
1306 | s2 = SX (u2); | |
1307 | uresult = ZX (~u2) + u1 + 1; | |
1308 | result = s1 - s2; | |
1309 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1310 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1311 | "CMP: %#x - %#x = %x", | |
1312 | u1, u2, uresult); | |
1313 | FLAGS (result, uresult != ZX (uresult)); | |
1314 | } | |
1315 | break; | |
1316 | ||
1317 | case MSO_dadd: | |
1318 | for (rept = 0; rept < n_repeats; rept ++) | |
1319 | { | |
1320 | carry_to_use = (SR & MSP430_FLAG_C) ? 1 : 0; | |
1321 | u1 = DSRC; | |
1322 | u2 = SRC; | |
1323 | uresult = bcd_to_binary (u1) + bcd_to_binary (u2) + carry_to_use; | |
1324 | result = binary_to_bcd (uresult); | |
1325 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1326 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1327 | "DADD: %#x + %#x + %d = %#x", | |
1328 | u1, u2, carry_to_use, result); | |
1329 | DEST (result); | |
1330 | FLAGS (result, uresult > ((opcode->size == 8) ? 99 : 9999)); | |
1331 | } | |
1332 | break; | |
1333 | ||
1334 | case MSO_and: | |
1335 | for (rept = 0; rept < n_repeats; rept ++) | |
1336 | { | |
1337 | u1 = DSRC; | |
1338 | u2 = SRC; | |
1339 | uresult = u1 & u2; | |
1340 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1341 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1342 | "AND: %#x & %#x = %#x", | |
1343 | u1, u2, uresult); | |
1344 | DEST (uresult); | |
1345 | FLAGS (uresult, uresult != 0); | |
1346 | } | |
1347 | break; | |
1348 | ||
1349 | case MSO_bit: | |
1350 | for (rept = 0; rept < n_repeats; rept ++) | |
1351 | { | |
1352 | u1 = DSRC; | |
1353 | u2 = SRC; | |
1354 | uresult = u1 & u2; | |
1355 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1356 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1357 | "BIT: %#x & %#x -> %#x", | |
1358 | u1, u2, uresult); | |
1359 | FLAGS (uresult, uresult != 0); | |
1360 | } | |
1361 | break; | |
1362 | ||
1363 | case MSO_bic: | |
1364 | for (rept = 0; rept < n_repeats; rept ++) | |
1365 | { | |
1366 | u1 = DSRC; | |
1367 | u2 = SRC; | |
1368 | uresult = u1 & ~ u2; | |
1369 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1370 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1371 | "BIC: %#x & ~ %#x = %#x", | |
1372 | u1, u2, uresult); | |
1373 | DEST (uresult); | |
1374 | } | |
1375 | break; | |
1376 | ||
1377 | case MSO_bis: | |
1378 | for (rept = 0; rept < n_repeats; rept ++) | |
1379 | { | |
1380 | u1 = DSRC; | |
1381 | u2 = SRC; | |
1382 | uresult = u1 | u2; | |
1383 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1384 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1385 | "BIS: %#x | %#x = %#x", | |
1386 | u1, u2, uresult); | |
1387 | DEST (uresult); | |
1388 | } | |
1389 | break; | |
1390 | ||
1391 | case MSO_xor: | |
1392 | for (rept = 0; rept < n_repeats; rept ++) | |
1393 | { | |
1394 | s1 = 1 << (opcode->size - 1); | |
1395 | u1 = DSRC; | |
1396 | u2 = SRC; | |
1397 | uresult = u1 ^ u2; | |
1398 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1399 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1400 | "XOR: %#x & %#x = %#x", | |
1401 | u1, u2, uresult); | |
1402 | DEST (uresult); | |
1403 | FLAGSV (uresult, uresult != 0, (u1 & s1) && (u2 & s1)); | |
1404 | } | |
1405 | break; | |
1406 | ||
1407 | /* Single-operand instructions. Note: the decoder puts the same | |
1408 | operand in SRC as in DEST, for our convenience. */ | |
1409 | ||
1410 | case MSO_rrc: | |
1411 | for (rept = 0; rept < n_repeats; rept ++) | |
1412 | { | |
1413 | u1 = SRC; | |
1414 | carry_to_use = u1 & 1; | |
1415 | uresult = u1 >> 1; | |
1416 | if (SR & MSP430_FLAG_C) | |
1417 | uresult |= (1 << (opcode->size - 1)); | |
1418 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1419 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1420 | "RRC: %#x >>= %#x", | |
1421 | u1, uresult); | |
1422 | DEST (uresult); | |
1423 | FLAGS (uresult, carry_to_use); | |
1424 | } | |
1425 | break; | |
1426 | ||
1427 | case MSO_swpb: | |
1428 | for (rept = 0; rept < n_repeats; rept ++) | |
1429 | { | |
1430 | u1 = SRC; | |
1431 | uresult = ((u1 >> 8) & 0x00ff) | ((u1 << 8) & 0xff00); | |
1432 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1433 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1434 | "SWPB: %#x -> %#x", | |
1435 | u1, uresult); | |
1436 | DEST (uresult); | |
1437 | } | |
1438 | break; | |
1439 | ||
1440 | case MSO_rra: | |
1441 | for (rept = 0; rept < n_repeats; rept ++) | |
1442 | { | |
1443 | u1 = SRC; | |
1444 | c = u1 & 1; | |
1445 | s1 = 1 << (opcode->size - 1); | |
1446 | uresult = (u1 >> 1) | (u1 & s1); | |
1447 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1448 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1449 | "RRA: %#x >>= %#x", | |
1450 | u1, uresult); | |
1451 | DEST (uresult); | |
1452 | FLAGS (uresult, c); | |
1453 | } | |
1454 | break; | |
1455 | ||
1456 | case MSO_rru: | |
1457 | for (rept = 0; rept < n_repeats; rept ++) | |
1458 | { | |
1459 | u1 = SRC; | |
1460 | c = u1 & 1; | |
1461 | uresult = (u1 >> 1); | |
1462 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1463 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1464 | "RRU: %#x >>= %#x", | |
1465 | u1, uresult); | |
1466 | DEST (uresult); | |
1467 | FLAGS (uresult, c); | |
1468 | } | |
1469 | break; | |
1470 | ||
1471 | case MSO_sxt: | |
1472 | for (rept = 0; rept < n_repeats; rept ++) | |
1473 | { | |
1474 | u1 = SRC; | |
1475 | if (u1 & 0x80) | |
1476 | uresult = u1 | 0xfff00; | |
1477 | else | |
1478 | uresult = u1 & 0x000ff; | |
1479 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1480 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1481 | "SXT: %#x -> %#x", | |
1482 | u1, uresult); | |
1483 | DEST (uresult); | |
1484 | FLAGS (uresult, c); | |
1485 | } | |
1486 | break; | |
1487 | ||
1488 | case MSO_push: | |
1489 | for (rept = 0; rept < n_repeats; rept ++) | |
1490 | { | |
1491 | int new_sp; | |
1492 | ||
1493 | new_sp = REG_GET (MSR_SP) - op_bytes; | |
1494 | /* SP is always word-aligned. */ | |
1495 | if (new_sp & 1) | |
1496 | new_sp --; | |
1497 | REG_PUT (MSR_SP, new_sp); | |
1498 | u1 = SRC; | |
1499 | mem_put_val (sd, SP, u1, op_bits); | |
1500 | if (opcode->op[1].type == MSP430_Operand_Register) | |
1501 | opcode->op[1].reg --; | |
1502 | } | |
1503 | break; | |
1504 | ||
1505 | case MSO_pop: | |
1506 | for (rept = 0; rept < n_repeats; rept ++) | |
1507 | { | |
1508 | int new_sp; | |
1509 | ||
1510 | u1 = mem_get_val (sd, SP, op_bits); | |
1511 | DEST (u1); | |
1512 | if (opcode->op[0].type == MSP430_Operand_Register) | |
1513 | opcode->op[0].reg ++; | |
1514 | new_sp = REG_GET (MSR_SP) + op_bytes; | |
1515 | /* SP is always word-aligned. */ | |
1516 | if (new_sp & 1) | |
1517 | new_sp ++; | |
1518 | REG_PUT (MSR_SP, new_sp); | |
1519 | } | |
1520 | break; | |
1521 | ||
1522 | case MSO_call: | |
1523 | u1 = SRC; | |
1524 | ||
1525 | if (maybe_perform_syscall (sd, u1)) | |
1526 | break; | |
1527 | ||
1528 | REG_PUT (MSR_SP, REG_GET (MSR_SP) - op_bytes); | |
1529 | mem_put_val (sd, SP, PC, op_bits); | |
1530 | if (TRACE_ALU_P (MSP430_CPU (sd))) | |
1531 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1532 | "CALL: func %#x ret %#x, sp %#x", | |
1533 | u1, PC, SP); | |
1534 | REG_PUT (MSR_PC, u1); | |
1535 | break; | |
1536 | ||
1537 | case MSO_reti: | |
8969934d NC |
1538 | u1 = mem_get_val (sd, SP, 16); |
1539 | SR = u1 & 0xFF; | |
3346cfda | 1540 | SP += 2; |
8969934d | 1541 | PC = mem_get_val (sd, SP, 16); |
3346cfda | 1542 | SP += 2; |
8969934d NC |
1543 | /* Emulate the RETI action of the 20-bit CPUX architecure. |
1544 | This is safe for 16-bit CPU architectures as well, since the top | |
1545 | 8-bits of SR will have been written to the stack here, and will | |
1546 | have been read as 0. */ | |
1547 | PC |= (u1 & 0xF000) << 4; | |
3346cfda NC |
1548 | if (TRACE_ALU_P (MSP430_CPU (sd))) |
1549 | trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, | |
1550 | "RETI: pc %#x sr %#x", | |
1551 | PC, SR); | |
1552 | break; | |
1553 | ||
1554 | /* Jumps. */ | |
1555 | ||
1556 | case MSO_jmp: | |
1557 | i = SRC; | |
1558 | switch (opcode->cond) | |
1559 | { | |
1560 | case MSC_nz: | |
1561 | u1 = (SR & MSP430_FLAG_Z) ? 0 : 1; | |
1562 | break; | |
1563 | case MSC_z: | |
1564 | u1 = (SR & MSP430_FLAG_Z) ? 1 : 0; | |
1565 | break; | |
1566 | case MSC_nc: | |
1567 | u1 = (SR & MSP430_FLAG_C) ? 0 : 1; | |
1568 | break; | |
1569 | case MSC_c: | |
1570 | u1 = (SR & MSP430_FLAG_C) ? 1 : 0; | |
1571 | break; | |
1572 | case MSC_n: | |
1573 | u1 = (SR & MSP430_FLAG_N) ? 1 : 0; | |
1574 | break; | |
1575 | case MSC_ge: | |
1576 | u1 = (!!(SR & MSP430_FLAG_N) == !!(SR & MSP430_FLAG_V)) ? 1 : 0; | |
1577 | break; | |
1578 | case MSC_l: | |
1579 | u1 = (!!(SR & MSP430_FLAG_N) == !!(SR & MSP430_FLAG_V)) ? 0 : 1; | |
1580 | break; | |
1581 | case MSC_true: | |
1582 | u1 = 1; | |
1583 | break; | |
1584 | } | |
1585 | ||
1586 | if (u1) | |
1587 | { | |
1588 | if (TRACE_BRANCH_P (MSP430_CPU (sd))) | |
1589 | trace_generic (sd, MSP430_CPU (sd), TRACE_BRANCH_IDX, | |
1590 | "J%s: pc %#x -> %#x sr %#x, taken", | |
1591 | cond_string (opcode->cond), PC, i, SR); | |
1592 | PC = i; | |
1593 | if (PC == opcode_pc) | |
1594 | exit (0); | |
1595 | } | |
1596 | else | |
1597 | if (TRACE_BRANCH_P (MSP430_CPU (sd))) | |
1598 | trace_generic (sd, MSP430_CPU (sd), TRACE_BRANCH_IDX, | |
1599 | "J%s: pc %#x to %#x sr %#x, not taken", | |
1600 | cond_string (opcode->cond), PC, i, SR); | |
1601 | break; | |
1602 | ||
1603 | default: | |
1604 | fprintf (stderr, "error: unexpected opcode id %d\n", opcode->id); | |
1605 | exit (1); | |
1606 | } | |
1607 | } | |
1608 | ||
1609 | void | |
1610 | sim_engine_run (SIM_DESC sd, | |
1611 | int next_cpu_nr, | |
1612 | int nr_cpus, | |
1613 | int siggnal) | |
1614 | { | |
1615 | while (1) | |
1616 | { | |
1617 | msp430_step_once (sd); | |
1618 | if (sim_events_tick (sd)) | |
1619 | sim_events_process (sd); | |
1620 | } | |
1621 | } |