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1 | /* Simulator for TI MSP430 and MSP430X processors. |
2 | ||
32d0add0 | 3 | Copyright (C) 2012-2015 Free Software Foundation, Inc. |
3346cfda NC |
4 | Contributed by Red Hat, Inc. |
5 | ||
6 | This file is part of simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #ifndef _MSP430_MAIN_SIM_H_ | |
22 | #define _MSP430_MAIN_SIM_H_ | |
23 | ||
24 | #include "sim-basics.h" | |
25 | #include "sim-signal.h" | |
3346cfda NC |
26 | #include "msp430-sim.h" |
27 | #include "sim-base.h" | |
28 | ||
29 | struct _sim_cpu | |
30 | { | |
31 | /* Simulator specific members. */ | |
32 | struct msp430_cpu_state state; | |
33 | sim_cpu_base base; | |
34 | }; | |
35 | ||
36 | struct sim_state | |
37 | { | |
38 | sim_cpu *cpu[MAX_NR_PROCESSORS]; | |
39 | ||
3346cfda NC |
40 | asymbol **symbol_table; |
41 | long number_of_symbols; | |
42 | #define STATE_SYMBOL_TABLE(sd) ((sd)->symbol_table) | |
43 | #define STATE_NUM_SYMBOLS(sd) ((sd)->number_of_symbols) | |
44 | ||
45 | /* Simulator specific members. */ | |
46 | sim_state_base base; | |
47 | }; | |
48 | ||
49 | #define MSP430_CPU(sd) (STATE_CPU ((sd), 0)) | |
50 | #define MSP430_CPU_STATE(sd) (MSP430_CPU ((sd)->state)) | |
51 | ||
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52 | #include "sim-config.h" |
53 | #include "sim-types.h" | |
54 | #include "sim-engine.h" | |
55 | #include "sim-options.h" | |
3346cfda NC |
56 | |
57 | #define MAYBE_TRACE(type, cpu, fmt, ...) \ | |
58 | do \ | |
59 | { \ | |
60 | if (TRACE_##type##_P (cpu)) \ | |
61 | trace_generic (CPU_STATE (cpu), cpu, TRACE_##type##_IDX, \ | |
62 | fmt, ## __VA_ARGS__); \ | |
63 | } \ | |
64 | while (0) | |
65 | ||
66 | #define TRACE_INSN(cpu, fmt, ...) MAYBE_TRACE (INSN, cpu, fmt, ## __VA_ARGS__) | |
67 | #define TRACE_DECODE(cpu, fmt, ...) MAYBE_TRACE (DECODE, cpu, fmt, ## __VA_ARGS__) | |
68 | #define TRACE_EXTRACT(cpu, fmt, ...) MAYBE_TRACE (EXTRACT, cpu, fmt, ## __VA_ARGS__) | |
69 | #define TRACE_SYSCALL(cpu, fmt, ...) MAYBE_TRACE (SYSCALL, cpu, fmt, ## __VA_ARGS__) | |
70 | ||
71 | #define TRACE_CORE(cpu, addr, size, map, val) \ | |
72 | do \ | |
73 | { \ | |
74 | MAYBE_TRACE (CORE, cpu, "%cBUS %s %i bytes @ 0x%08x: 0x%0*x", \ | |
75 | map == exec_map ? 'I' : 'D', \ | |
76 | map == write_map ? "STORE" : "FETCH", \ | |
77 | size, addr, size * 2, val); \ | |
78 | PROFILE_COUNT_CORE (cpu, addr, size, map); \ | |
79 | } \ | |
80 | while (0) | |
81 | ||
82 | #define TRACE_EVENTS(cpu, fmt, ...) MAYBE_TRACE (EVENTS, cpu, fmt, ## __VA_ARGS__) | |
83 | ||
84 | #define TRACE_BRANCH(cpu, oldpc, newpc, fmt, ...) \ | |
85 | do \ | |
86 | { \ | |
87 | MAYBE_TRACE (BRANCH, cpu, fmt " to %#x", ## __VA_ARGS__, newpc); \ | |
88 | } \ | |
89 | while (0) | |
90 | ||
91 | extern void trace_register (SIM_DESC, sim_cpu *, const char *, ...) | |
92 | __attribute__((format (printf, 3, 4))); | |
93 | ||
94 | #define TRACE_REGISTER(cpu, fmt, ...) \ | |
95 | do \ | |
96 | { \ | |
97 | if (TRACE_CORE_P (cpu)) \ | |
98 | trace_register (CPU_STATE (cpu), cpu, fmt, ## __VA_ARGS__); \ | |
99 | } \ | |
100 | while (0) | |
101 | ||
102 | #define TRACE_REG(cpu, reg, val) \ | |
103 | TRACE_REGISTER (cpu, "wrote R%d = %#x", reg, val) | |
104 | ||
105 | #endif /* _MSP430_MAIN_SIM_H_ */ |