Commit | Line | Data |
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6e51bfa7 SH |
1 | /* Simulator instruction semantics for or1k32bf. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
b811d2c2 | 5 | Copyright (C) 1996-2020 Free Software Foundation, Inc. |
6e51bfa7 SH |
6 | |
7 | This file is part of the GNU simulators. | |
8 | ||
9 | This file is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
13 | ||
14 | It is distributed in the hope that it will be useful, but WITHOUT | |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #define WANT_CPU or1k32bf | |
26 | #define WANT_CPU_OR1K32BF | |
27 | ||
28 | #include "sim-main.h" | |
29 | #include "cgen-mem.h" | |
30 | #include "cgen-ops.h" | |
31 | ||
32 | #undef GET_ATTR | |
33 | #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) | |
34 | ||
35 | /* This is used so that we can compile two copies of the semantic code, | |
36 | one with full feature support and one without that runs fast(er). | |
37 | FAST_P, when desired, is defined on the command line, -DFAST_P=1. */ | |
38 | #if FAST_P | |
39 | #define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn) | |
40 | #undef CGEN_TRACE_RESULT | |
41 | #define CGEN_TRACE_RESULT(cpu, abuf, name, type, val) | |
42 | #else | |
43 | #define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn) | |
44 | #endif | |
45 | ||
46 | /* x-invalid: --invalid-- */ | |
47 | ||
48 | static SEM_PC | |
49 | SEM_FN_NAME (or1k32bf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
50 | { | |
51 | #define FLD(f) abuf->fields.sfmt_empty.f | |
52 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
53 | int UNUSED written = 0; | |
54 | IADDR UNUSED pc = abuf->addr; | |
55 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
56 | ||
57 | { | |
58 | /* Update the recorded pc in the cpu state struct. | |
59 | Only necessary for WITH_SCACHE case, but to avoid the | |
60 | conditional compilation .... */ | |
61 | SET_H_PC (pc); | |
62 | /* Virtual insns have zero size. Overwrite vpc with address of next insn | |
63 | using the default-insn-bitsize spec. When executing insns in parallel | |
64 | we may want to queue the fault and continue execution. */ | |
65 | vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
66 | vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); | |
67 | } | |
68 | ||
69 | return vpc; | |
70 | #undef FLD | |
71 | } | |
72 | ||
73 | /* x-after: --after-- */ | |
74 | ||
75 | static SEM_PC | |
76 | SEM_FN_NAME (or1k32bf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
77 | { | |
78 | #define FLD(f) abuf->fields.sfmt_empty.f | |
79 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
80 | int UNUSED written = 0; | |
81 | IADDR UNUSED pc = abuf->addr; | |
82 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
83 | ||
84 | { | |
85 | #if WITH_SCACHE_PBB_OR1K32BF | |
86 | or1k32bf_pbb_after (current_cpu, sem_arg); | |
87 | #endif | |
88 | } | |
89 | ||
90 | return vpc; | |
91 | #undef FLD | |
92 | } | |
93 | ||
94 | /* x-before: --before-- */ | |
95 | ||
96 | static SEM_PC | |
97 | SEM_FN_NAME (or1k32bf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
98 | { | |
99 | #define FLD(f) abuf->fields.sfmt_empty.f | |
100 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
101 | int UNUSED written = 0; | |
102 | IADDR UNUSED pc = abuf->addr; | |
103 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
104 | ||
105 | { | |
106 | #if WITH_SCACHE_PBB_OR1K32BF | |
107 | or1k32bf_pbb_before (current_cpu, sem_arg); | |
108 | #endif | |
109 | } | |
110 | ||
111 | return vpc; | |
112 | #undef FLD | |
113 | } | |
114 | ||
115 | /* x-cti-chain: --cti-chain-- */ | |
116 | ||
117 | static SEM_PC | |
118 | SEM_FN_NAME (or1k32bf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
119 | { | |
120 | #define FLD(f) abuf->fields.sfmt_empty.f | |
121 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
122 | int UNUSED written = 0; | |
123 | IADDR UNUSED pc = abuf->addr; | |
124 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
125 | ||
126 | { | |
127 | #if WITH_SCACHE_PBB_OR1K32BF | |
128 | #ifdef DEFINE_SWITCH | |
129 | vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg, | |
130 | pbb_br_type, pbb_br_npc); | |
131 | BREAK (sem); | |
132 | #else | |
133 | /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ | |
134 | vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg, | |
135 | CPU_PBB_BR_TYPE (current_cpu), | |
136 | CPU_PBB_BR_NPC (current_cpu)); | |
137 | #endif | |
138 | #endif | |
139 | } | |
140 | ||
141 | return vpc; | |
142 | #undef FLD | |
143 | } | |
144 | ||
145 | /* x-chain: --chain-- */ | |
146 | ||
147 | static SEM_PC | |
148 | SEM_FN_NAME (or1k32bf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
149 | { | |
150 | #define FLD(f) abuf->fields.sfmt_empty.f | |
151 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
152 | int UNUSED written = 0; | |
153 | IADDR UNUSED pc = abuf->addr; | |
154 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
155 | ||
156 | { | |
157 | #if WITH_SCACHE_PBB_OR1K32BF | |
158 | vpc = or1k32bf_pbb_chain (current_cpu, sem_arg); | |
159 | #ifdef DEFINE_SWITCH | |
160 | BREAK (sem); | |
161 | #endif | |
162 | #endif | |
163 | } | |
164 | ||
165 | return vpc; | |
166 | #undef FLD | |
167 | } | |
168 | ||
169 | /* x-begin: --begin-- */ | |
170 | ||
171 | static SEM_PC | |
172 | SEM_FN_NAME (or1k32bf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
173 | { | |
174 | #define FLD(f) abuf->fields.sfmt_empty.f | |
175 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
176 | int UNUSED written = 0; | |
177 | IADDR UNUSED pc = abuf->addr; | |
178 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); | |
179 | ||
180 | { | |
181 | #if WITH_SCACHE_PBB_OR1K32BF | |
182 | #if defined DEFINE_SWITCH || defined FAST_P | |
183 | /* In the switch case FAST_P is a constant, allowing several optimizations | |
184 | in any called inline functions. */ | |
185 | vpc = or1k32bf_pbb_begin (current_cpu, FAST_P); | |
186 | #else | |
187 | #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ | |
188 | vpc = or1k32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); | |
189 | #else | |
190 | vpc = or1k32bf_pbb_begin (current_cpu, 0); | |
191 | #endif | |
192 | #endif | |
193 | #endif | |
194 | } | |
195 | ||
196 | return vpc; | |
197 | #undef FLD | |
198 | } | |
199 | ||
200 | /* l-j: l.j ${disp26} */ | |
201 | ||
202 | static SEM_PC | |
203 | SEM_FN_NAME (or1k32bf,l_j) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
204 | { | |
205 | #define FLD(f) abuf->fields.sfmt_l_j.f | |
206 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
207 | int UNUSED written = 0; | |
208 | IADDR UNUSED pc = abuf->addr; | |
209 | SEM_BRANCH_INIT | |
210 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
211 | ||
212 | { | |
213 | { | |
214 | { | |
215 | USI opval = FLD (i_disp26); | |
216 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
217 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
218 | } | |
219 | } | |
220 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
221 | if (1) | |
222 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
223 | } | |
224 | } | |
225 | ||
226 | SEM_BRANCH_FINI (vpc); | |
227 | return vpc; | |
228 | #undef FLD | |
229 | } | |
230 | ||
07f5f4c6 RH |
231 | /* l-adrp: l.adrp $rD,${disp21} */ |
232 | ||
233 | static SEM_PC | |
234 | SEM_FN_NAME (or1k32bf,l_adrp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
235 | { | |
236 | #define FLD(f) abuf->fields.sfmt_l_adrp.f | |
237 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
238 | int UNUSED written = 0; | |
239 | IADDR UNUSED pc = abuf->addr; | |
240 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
241 | ||
242 | { | |
243 | USI opval = FLD (i_disp21); | |
244 | SET_H_GPR (FLD (f_r1), opval); | |
245 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
246 | } | |
247 | ||
248 | return vpc; | |
249 | #undef FLD | |
250 | } | |
251 | ||
6e51bfa7 SH |
252 | /* l-jal: l.jal ${disp26} */ |
253 | ||
254 | static SEM_PC | |
255 | SEM_FN_NAME (or1k32bf,l_jal) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
256 | { | |
257 | #define FLD(f) abuf->fields.sfmt_l_j.f | |
258 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
259 | int UNUSED written = 0; | |
260 | IADDR UNUSED pc = abuf->addr; | |
261 | SEM_BRANCH_INIT | |
262 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
263 | ||
264 | { | |
265 | { | |
266 | USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8))); | |
267 | SET_H_GPR (((UINT) 9), opval); | |
268 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
269 | } | |
270 | { | |
271 | { | |
272 | { | |
273 | USI opval = FLD (i_disp26); | |
274 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
275 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
276 | } | |
277 | } | |
278 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
279 | if (1) | |
280 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
281 | } | |
282 | } | |
283 | } | |
284 | ||
285 | SEM_BRANCH_FINI (vpc); | |
286 | return vpc; | |
287 | #undef FLD | |
288 | } | |
289 | ||
290 | /* l-jr: l.jr $rB */ | |
291 | ||
292 | static SEM_PC | |
293 | SEM_FN_NAME (or1k32bf,l_jr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
294 | { | |
295 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
296 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
297 | int UNUSED written = 0; | |
298 | IADDR UNUSED pc = abuf->addr; | |
299 | SEM_BRANCH_INIT | |
300 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
301 | ||
302 | { | |
303 | { | |
304 | { | |
305 | USI opval = GET_H_GPR (FLD (f_r3)); | |
306 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
307 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
308 | } | |
309 | } | |
310 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
311 | if (1) | |
312 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
313 | } | |
314 | } | |
315 | ||
316 | SEM_BRANCH_FINI (vpc); | |
317 | return vpc; | |
318 | #undef FLD | |
319 | } | |
320 | ||
321 | /* l-jalr: l.jalr $rB */ | |
322 | ||
323 | static SEM_PC | |
324 | SEM_FN_NAME (or1k32bf,l_jalr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
325 | { | |
326 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
327 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
328 | int UNUSED written = 0; | |
329 | IADDR UNUSED pc = abuf->addr; | |
330 | SEM_BRANCH_INIT | |
331 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
332 | ||
333 | { | |
334 | { | |
335 | USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8))); | |
336 | SET_H_GPR (((UINT) 9), opval); | |
337 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
338 | } | |
339 | { | |
340 | { | |
341 | { | |
342 | USI opval = GET_H_GPR (FLD (f_r3)); | |
343 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
344 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
345 | } | |
346 | } | |
347 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
348 | if (1) | |
349 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
350 | } | |
351 | } | |
352 | } | |
353 | ||
354 | SEM_BRANCH_FINI (vpc); | |
355 | return vpc; | |
356 | #undef FLD | |
357 | } | |
358 | ||
359 | /* l-bnf: l.bnf ${disp26} */ | |
360 | ||
361 | static SEM_PC | |
362 | SEM_FN_NAME (or1k32bf,l_bnf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
363 | { | |
364 | #define FLD(f) abuf->fields.sfmt_l_j.f | |
365 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
366 | int UNUSED written = 0; | |
367 | IADDR UNUSED pc = abuf->addr; | |
368 | SEM_BRANCH_INIT | |
369 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
370 | ||
371 | { | |
372 | if (NOTSI (GET_H_SYS_SR_F ())) { | |
373 | { | |
374 | { | |
375 | USI opval = FLD (i_disp26); | |
376 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
377 | written |= (1 << 4); | |
378 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
379 | } | |
380 | } | |
381 | } else { | |
382 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
383 | { | |
384 | { | |
385 | USI opval = ADDSI (pc, 4); | |
386 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
387 | written |= (1 << 4); | |
388 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
389 | } | |
390 | } | |
391 | } | |
392 | } | |
393 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
394 | if (1) | |
395 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
396 | } | |
397 | } | |
398 | ||
399 | abuf->written = written; | |
400 | SEM_BRANCH_FINI (vpc); | |
401 | return vpc; | |
402 | #undef FLD | |
403 | } | |
404 | ||
405 | /* l-bf: l.bf ${disp26} */ | |
406 | ||
407 | static SEM_PC | |
408 | SEM_FN_NAME (or1k32bf,l_bf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
409 | { | |
410 | #define FLD(f) abuf->fields.sfmt_l_j.f | |
411 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
412 | int UNUSED written = 0; | |
413 | IADDR UNUSED pc = abuf->addr; | |
414 | SEM_BRANCH_INIT | |
415 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
416 | ||
417 | { | |
418 | if (GET_H_SYS_SR_F ()) { | |
419 | { | |
420 | { | |
421 | USI opval = FLD (i_disp26); | |
422 | SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); | |
423 | written |= (1 << 4); | |
424 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
425 | } | |
426 | } | |
427 | } else { | |
428 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
429 | { | |
430 | { | |
431 | USI opval = ADDSI (pc, 4); | |
432 | SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); | |
433 | written |= (1 << 4); | |
434 | CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); | |
435 | } | |
436 | } | |
437 | } | |
438 | } | |
439 | if (GET_H_SYS_CPUCFGR_ND ()) { | |
440 | if (1) | |
441 | SEM_SKIP_INSN (current_cpu, sem_arg, vpc); | |
442 | } | |
443 | } | |
444 | ||
445 | abuf->written = written; | |
446 | SEM_BRANCH_FINI (vpc); | |
447 | return vpc; | |
448 | #undef FLD | |
449 | } | |
450 | ||
451 | /* l-trap: l.trap ${uimm16} */ | |
452 | ||
453 | static SEM_PC | |
454 | SEM_FN_NAME (or1k32bf,l_trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
455 | { | |
456 | #define FLD(f) abuf->fields.sfmt_empty.f | |
457 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
458 | int UNUSED written = 0; | |
459 | IADDR UNUSED pc = abuf->addr; | |
460 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
461 | ||
462 | or1k32bf_exception (current_cpu, pc, EXCEPT_TRAP); | |
463 | ||
464 | return vpc; | |
465 | #undef FLD | |
466 | } | |
467 | ||
468 | /* l-sys: l.sys ${uimm16} */ | |
469 | ||
470 | static SEM_PC | |
471 | SEM_FN_NAME (or1k32bf,l_sys) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
472 | { | |
473 | #define FLD(f) abuf->fields.sfmt_empty.f | |
474 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
475 | int UNUSED written = 0; | |
476 | IADDR UNUSED pc = abuf->addr; | |
477 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
478 | ||
479 | or1k32bf_exception (current_cpu, pc, EXCEPT_SYSCALL); | |
480 | ||
481 | return vpc; | |
482 | #undef FLD | |
483 | } | |
484 | ||
485 | /* l-msync: l.msync */ | |
486 | ||
487 | static SEM_PC | |
488 | SEM_FN_NAME (or1k32bf,l_msync) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
489 | { | |
490 | #define FLD(f) abuf->fields.sfmt_empty.f | |
491 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
492 | int UNUSED written = 0; | |
493 | IADDR UNUSED pc = abuf->addr; | |
494 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
495 | ||
496 | ((void) 0); /*nop*/ | |
497 | ||
498 | return vpc; | |
499 | #undef FLD | |
500 | } | |
501 | ||
502 | /* l-psync: l.psync */ | |
503 | ||
504 | static SEM_PC | |
505 | SEM_FN_NAME (or1k32bf,l_psync) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
506 | { | |
507 | #define FLD(f) abuf->fields.sfmt_empty.f | |
508 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
509 | int UNUSED written = 0; | |
510 | IADDR UNUSED pc = abuf->addr; | |
511 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
512 | ||
513 | ((void) 0); /*nop*/ | |
514 | ||
515 | return vpc; | |
516 | #undef FLD | |
517 | } | |
518 | ||
519 | /* l-csync: l.csync */ | |
520 | ||
521 | static SEM_PC | |
522 | SEM_FN_NAME (or1k32bf,l_csync) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
523 | { | |
524 | #define FLD(f) abuf->fields.sfmt_empty.f | |
525 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
526 | int UNUSED written = 0; | |
527 | IADDR UNUSED pc = abuf->addr; | |
528 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
529 | ||
530 | ((void) 0); /*nop*/ | |
531 | ||
532 | return vpc; | |
533 | #undef FLD | |
534 | } | |
535 | ||
536 | /* l-rfe: l.rfe */ | |
537 | ||
538 | static SEM_PC | |
539 | SEM_FN_NAME (or1k32bf,l_rfe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
540 | { | |
541 | #define FLD(f) abuf->fields.sfmt_empty.f | |
542 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
543 | int UNUSED written = 0; | |
544 | IADDR UNUSED pc = abuf->addr; | |
545 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
546 | ||
547 | or1k32bf_rfe (current_cpu); | |
548 | ||
549 | return vpc; | |
550 | #undef FLD | |
551 | } | |
552 | ||
553 | /* l-nop-imm: l.nop ${uimm16} */ | |
554 | ||
555 | static SEM_PC | |
556 | SEM_FN_NAME (or1k32bf,l_nop_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
557 | { | |
558 | #define FLD(f) abuf->fields.sfmt_l_mfspr.f | |
559 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
560 | int UNUSED written = 0; | |
561 | IADDR UNUSED pc = abuf->addr; | |
562 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
563 | ||
564 | or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16))); | |
565 | ||
566 | return vpc; | |
567 | #undef FLD | |
568 | } | |
569 | ||
570 | /* l-movhi: l.movhi $rD,$uimm16 */ | |
571 | ||
572 | static SEM_PC | |
573 | SEM_FN_NAME (or1k32bf,l_movhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
574 | { | |
575 | #define FLD(f) abuf->fields.sfmt_l_mfspr.f | |
576 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
577 | int UNUSED written = 0; | |
578 | IADDR UNUSED pc = abuf->addr; | |
579 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
580 | ||
581 | { | |
582 | USI opval = SLLSI (ZEXTSISI (FLD (f_uimm16)), 16); | |
583 | SET_H_GPR (FLD (f_r1), opval); | |
584 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
585 | } | |
586 | ||
587 | return vpc; | |
588 | #undef FLD | |
589 | } | |
590 | ||
591 | /* l-macrc: l.macrc $rD */ | |
592 | ||
593 | static SEM_PC | |
594 | SEM_FN_NAME (or1k32bf,l_macrc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
595 | { | |
07f5f4c6 | 596 | #define FLD(f) abuf->fields.sfmt_l_adrp.f |
6e51bfa7 SH |
597 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
598 | int UNUSED written = 0; | |
599 | IADDR UNUSED pc = abuf->addr; | |
600 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
601 | ||
602 | { | |
603 | { | |
604 | USI opval = GET_H_MAC_MACLO (); | |
605 | SET_H_GPR (FLD (f_r1), opval); | |
606 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
607 | } | |
608 | { | |
609 | USI opval = 0; | |
610 | SET_H_MAC_MACLO (opval); | |
611 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
612 | } | |
613 | { | |
614 | USI opval = 0; | |
615 | SET_H_MAC_MACHI (opval); | |
616 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
617 | } | |
618 | } | |
619 | ||
620 | return vpc; | |
621 | #undef FLD | |
622 | } | |
623 | ||
624 | /* l-mfspr: l.mfspr $rD,$rA,${uimm16} */ | |
625 | ||
626 | static SEM_PC | |
627 | SEM_FN_NAME (or1k32bf,l_mfspr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
628 | { | |
629 | #define FLD(f) abuf->fields.sfmt_l_mfspr.f | |
630 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
631 | int UNUSED written = 0; | |
632 | IADDR UNUSED pc = abuf->addr; | |
633 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
634 | ||
635 | { | |
636 | USI opval = or1k32bf_mfspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)))); | |
637 | SET_H_GPR (FLD (f_r1), opval); | |
638 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
639 | } | |
640 | ||
641 | return vpc; | |
642 | #undef FLD | |
643 | } | |
644 | ||
645 | /* l-mtspr: l.mtspr $rA,$rB,${uimm16-split} */ | |
646 | ||
647 | static SEM_PC | |
648 | SEM_FN_NAME (or1k32bf,l_mtspr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
649 | { | |
650 | #define FLD(f) abuf->fields.sfmt_l_mtspr.f | |
651 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
652 | int UNUSED written = 0; | |
653 | IADDR UNUSED pc = abuf->addr; | |
654 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
655 | ||
656 | or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3))); | |
657 | ||
658 | return vpc; | |
659 | #undef FLD | |
660 | } | |
661 | ||
662 | /* l-lwz: l.lwz $rD,${simm16}($rA) */ | |
663 | ||
664 | static SEM_PC | |
665 | SEM_FN_NAME (or1k32bf,l_lwz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
666 | { | |
667 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
668 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
669 | int UNUSED written = 0; | |
670 | IADDR UNUSED pc = abuf->addr; | |
671 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
672 | ||
673 | { | |
674 | USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4))); | |
675 | SET_H_GPR (FLD (f_r1), opval); | |
676 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
677 | } | |
678 | ||
679 | return vpc; | |
680 | #undef FLD | |
681 | } | |
682 | ||
683 | /* l-lws: l.lws $rD,${simm16}($rA) */ | |
684 | ||
685 | static SEM_PC | |
686 | SEM_FN_NAME (or1k32bf,l_lws) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
687 | { | |
688 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
689 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
690 | int UNUSED written = 0; | |
691 | IADDR UNUSED pc = abuf->addr; | |
692 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
693 | ||
694 | { | |
695 | SI opval = EXTSISI (GETMEMSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4))); | |
696 | SET_H_GPR (FLD (f_r1), opval); | |
697 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
698 | } | |
699 | ||
700 | return vpc; | |
701 | #undef FLD | |
702 | } | |
703 | ||
704 | /* l-lwa: l.lwa $rD,${simm16}($rA) */ | |
705 | ||
706 | static SEM_PC | |
707 | SEM_FN_NAME (or1k32bf,l_lwa) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
708 | { | |
709 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
710 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
711 | int UNUSED written = 0; | |
712 | IADDR UNUSED pc = abuf->addr; | |
713 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
714 | ||
715 | { | |
716 | { | |
717 | USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4))); | |
718 | SET_H_GPR (FLD (f_r1), opval); | |
719 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
720 | } | |
721 | { | |
722 | BI opval = 1; | |
723 | CPU (h_atomic_reserve) = opval; | |
724 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval); | |
725 | } | |
726 | { | |
727 | SI opval = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4); | |
728 | CPU (h_atomic_address) = opval; | |
729 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-address", 'x', opval); | |
730 | } | |
731 | } | |
732 | ||
733 | return vpc; | |
734 | #undef FLD | |
735 | } | |
736 | ||
737 | /* l-lbz: l.lbz $rD,${simm16}($rA) */ | |
738 | ||
739 | static SEM_PC | |
740 | SEM_FN_NAME (or1k32bf,l_lbz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
741 | { | |
742 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
743 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
744 | int UNUSED written = 0; | |
745 | IADDR UNUSED pc = abuf->addr; | |
746 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
747 | ||
748 | { | |
749 | USI opval = ZEXTQISI (GETMEMUQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1))); | |
750 | SET_H_GPR (FLD (f_r1), opval); | |
751 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
752 | } | |
753 | ||
754 | return vpc; | |
755 | #undef FLD | |
756 | } | |
757 | ||
758 | /* l-lbs: l.lbs $rD,${simm16}($rA) */ | |
759 | ||
760 | static SEM_PC | |
761 | SEM_FN_NAME (or1k32bf,l_lbs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
762 | { | |
763 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
764 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
765 | int UNUSED written = 0; | |
766 | IADDR UNUSED pc = abuf->addr; | |
767 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
768 | ||
769 | { | |
770 | SI opval = EXTQISI (GETMEMQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1))); | |
771 | SET_H_GPR (FLD (f_r1), opval); | |
772 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
773 | } | |
774 | ||
775 | return vpc; | |
776 | #undef FLD | |
777 | } | |
778 | ||
779 | /* l-lhz: l.lhz $rD,${simm16}($rA) */ | |
780 | ||
781 | static SEM_PC | |
782 | SEM_FN_NAME (or1k32bf,l_lhz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
783 | { | |
784 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
785 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
786 | int UNUSED written = 0; | |
787 | IADDR UNUSED pc = abuf->addr; | |
788 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
789 | ||
790 | { | |
791 | USI opval = ZEXTHISI (GETMEMUHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2))); | |
792 | SET_H_GPR (FLD (f_r1), opval); | |
793 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
794 | } | |
795 | ||
796 | return vpc; | |
797 | #undef FLD | |
798 | } | |
799 | ||
800 | /* l-lhs: l.lhs $rD,${simm16}($rA) */ | |
801 | ||
802 | static SEM_PC | |
803 | SEM_FN_NAME (or1k32bf,l_lhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
804 | { | |
805 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
806 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
807 | int UNUSED written = 0; | |
808 | IADDR UNUSED pc = abuf->addr; | |
809 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
810 | ||
811 | { | |
812 | SI opval = EXTHISI (GETMEMHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2))); | |
813 | SET_H_GPR (FLD (f_r1), opval); | |
814 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
815 | } | |
816 | ||
817 | return vpc; | |
818 | #undef FLD | |
819 | } | |
820 | ||
821 | /* l-sw: l.sw ${simm16-split}($rA),$rB */ | |
822 | ||
823 | static SEM_PC | |
824 | SEM_FN_NAME (or1k32bf,l_sw) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
825 | { | |
826 | #define FLD(f) abuf->fields.sfmt_l_sw.f | |
827 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
828 | int UNUSED written = 0; | |
829 | IADDR UNUSED pc = abuf->addr; | |
830 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
831 | ||
832 | { | |
833 | SI tmp_addr; | |
834 | tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4); | |
835 | { | |
836 | USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3))); | |
837 | SETMEMUSI (current_cpu, pc, tmp_addr, opval); | |
838 | CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
839 | } | |
840 | if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) { | |
841 | { | |
842 | BI opval = 0; | |
843 | CPU (h_atomic_reserve) = opval; | |
844 | written |= (1 << 4); | |
845 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval); | |
846 | } | |
847 | } | |
848 | } | |
849 | ||
850 | abuf->written = written; | |
851 | return vpc; | |
852 | #undef FLD | |
853 | } | |
854 | ||
855 | /* l-sb: l.sb ${simm16-split}($rA),$rB */ | |
856 | ||
857 | static SEM_PC | |
858 | SEM_FN_NAME (or1k32bf,l_sb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
859 | { | |
860 | #define FLD(f) abuf->fields.sfmt_l_sw.f | |
861 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
862 | int UNUSED written = 0; | |
863 | IADDR UNUSED pc = abuf->addr; | |
864 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
865 | ||
866 | { | |
867 | SI tmp_addr; | |
868 | tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1); | |
869 | { | |
870 | UQI opval = TRUNCSIQI (GET_H_GPR (FLD (f_r3))); | |
871 | SETMEMUQI (current_cpu, pc, tmp_addr, opval); | |
872 | CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
873 | } | |
874 | if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) { | |
875 | { | |
876 | BI opval = 0; | |
877 | CPU (h_atomic_reserve) = opval; | |
878 | written |= (1 << 4); | |
879 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval); | |
880 | } | |
881 | } | |
882 | } | |
883 | ||
884 | abuf->written = written; | |
885 | return vpc; | |
886 | #undef FLD | |
887 | } | |
888 | ||
889 | /* l-sh: l.sh ${simm16-split}($rA),$rB */ | |
890 | ||
891 | static SEM_PC | |
892 | SEM_FN_NAME (or1k32bf,l_sh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
893 | { | |
894 | #define FLD(f) abuf->fields.sfmt_l_sw.f | |
895 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
896 | int UNUSED written = 0; | |
897 | IADDR UNUSED pc = abuf->addr; | |
898 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
899 | ||
900 | { | |
901 | SI tmp_addr; | |
902 | tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2); | |
903 | { | |
904 | UHI opval = TRUNCSIHI (GET_H_GPR (FLD (f_r3))); | |
905 | SETMEMUHI (current_cpu, pc, tmp_addr, opval); | |
906 | CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
907 | } | |
908 | if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) { | |
909 | { | |
910 | BI opval = 0; | |
911 | CPU (h_atomic_reserve) = opval; | |
912 | written |= (1 << 4); | |
913 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval); | |
914 | } | |
915 | } | |
916 | } | |
917 | ||
918 | abuf->written = written; | |
919 | return vpc; | |
920 | #undef FLD | |
921 | } | |
922 | ||
923 | /* l-swa: l.swa ${simm16-split}($rA),$rB */ | |
924 | ||
925 | static SEM_PC | |
926 | SEM_FN_NAME (or1k32bf,l_swa) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
927 | { | |
928 | #define FLD(f) abuf->fields.sfmt_l_sw.f | |
929 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
930 | int UNUSED written = 0; | |
931 | IADDR UNUSED pc = abuf->addr; | |
932 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
933 | ||
934 | { | |
935 | SI tmp_addr; | |
936 | BI tmp_flag; | |
937 | tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4); | |
938 | { | |
939 | USI opval = ANDBI (CPU (h_atomic_reserve), EQSI (tmp_addr, CPU (h_atomic_address))); | |
940 | SET_H_SYS_SR_F (opval); | |
941 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
942 | } | |
943 | if (GET_H_SYS_SR_F ()) { | |
944 | { | |
945 | USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3))); | |
946 | SETMEMUSI (current_cpu, pc, tmp_addr, opval); | |
947 | written |= (1 << 7); | |
948 | CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); | |
949 | } | |
950 | } | |
951 | { | |
952 | BI opval = 0; | |
953 | CPU (h_atomic_reserve) = opval; | |
954 | CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval); | |
955 | } | |
956 | } | |
957 | ||
958 | abuf->written = written; | |
959 | return vpc; | |
960 | #undef FLD | |
961 | } | |
962 | ||
963 | /* l-sll: l.sll $rD,$rA,$rB */ | |
964 | ||
965 | static SEM_PC | |
966 | SEM_FN_NAME (or1k32bf,l_sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
967 | { | |
968 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
969 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
970 | int UNUSED written = 0; | |
971 | IADDR UNUSED pc = abuf->addr; | |
972 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
973 | ||
974 | { | |
975 | USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
976 | SET_H_GPR (FLD (f_r1), opval); | |
977 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
978 | } | |
979 | ||
980 | return vpc; | |
981 | #undef FLD | |
982 | } | |
983 | ||
984 | /* l-slli: l.slli $rD,$rA,${uimm6} */ | |
985 | ||
986 | static SEM_PC | |
987 | SEM_FN_NAME (or1k32bf,l_slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
988 | { | |
989 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
990 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
991 | int UNUSED written = 0; | |
992 | IADDR UNUSED pc = abuf->addr; | |
993 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
994 | ||
995 | { | |
996 | USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6)); | |
997 | SET_H_GPR (FLD (f_r1), opval); | |
998 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
999 | } | |
1000 | ||
1001 | return vpc; | |
1002 | #undef FLD | |
1003 | } | |
1004 | ||
1005 | /* l-srl: l.srl $rD,$rA,$rB */ | |
1006 | ||
1007 | static SEM_PC | |
1008 | SEM_FN_NAME (or1k32bf,l_srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1009 | { | |
1010 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1011 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1012 | int UNUSED written = 0; | |
1013 | IADDR UNUSED pc = abuf->addr; | |
1014 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1015 | ||
1016 | { | |
1017 | USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1018 | SET_H_GPR (FLD (f_r1), opval); | |
1019 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1020 | } | |
1021 | ||
1022 | return vpc; | |
1023 | #undef FLD | |
1024 | } | |
1025 | ||
1026 | /* l-srli: l.srli $rD,$rA,${uimm6} */ | |
1027 | ||
1028 | static SEM_PC | |
1029 | SEM_FN_NAME (or1k32bf,l_srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1030 | { | |
1031 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1032 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1033 | int UNUSED written = 0; | |
1034 | IADDR UNUSED pc = abuf->addr; | |
1035 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1036 | ||
1037 | { | |
1038 | USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6)); | |
1039 | SET_H_GPR (FLD (f_r1), opval); | |
1040 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1041 | } | |
1042 | ||
1043 | return vpc; | |
1044 | #undef FLD | |
1045 | } | |
1046 | ||
1047 | /* l-sra: l.sra $rD,$rA,$rB */ | |
1048 | ||
1049 | static SEM_PC | |
1050 | SEM_FN_NAME (or1k32bf,l_sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1051 | { | |
1052 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1053 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1054 | int UNUSED written = 0; | |
1055 | IADDR UNUSED pc = abuf->addr; | |
1056 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1057 | ||
1058 | { | |
1059 | USI opval = SRASI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1060 | SET_H_GPR (FLD (f_r1), opval); | |
1061 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1062 | } | |
1063 | ||
1064 | return vpc; | |
1065 | #undef FLD | |
1066 | } | |
1067 | ||
1068 | /* l-srai: l.srai $rD,$rA,${uimm6} */ | |
1069 | ||
1070 | static SEM_PC | |
1071 | SEM_FN_NAME (or1k32bf,l_srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1072 | { | |
1073 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1074 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1075 | int UNUSED written = 0; | |
1076 | IADDR UNUSED pc = abuf->addr; | |
1077 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1078 | ||
1079 | { | |
1080 | USI opval = SRASI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6)); | |
1081 | SET_H_GPR (FLD (f_r1), opval); | |
1082 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1083 | } | |
1084 | ||
1085 | return vpc; | |
1086 | #undef FLD | |
1087 | } | |
1088 | ||
1089 | /* l-ror: l.ror $rD,$rA,$rB */ | |
1090 | ||
1091 | static SEM_PC | |
1092 | SEM_FN_NAME (or1k32bf,l_ror) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1093 | { | |
1094 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1095 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1096 | int UNUSED written = 0; | |
1097 | IADDR UNUSED pc = abuf->addr; | |
1098 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1099 | ||
1100 | { | |
1101 | USI opval = RORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1102 | SET_H_GPR (FLD (f_r1), opval); | |
1103 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1104 | } | |
1105 | ||
1106 | return vpc; | |
1107 | #undef FLD | |
1108 | } | |
1109 | ||
1110 | /* l-rori: l.rori $rD,$rA,${uimm6} */ | |
1111 | ||
1112 | static SEM_PC | |
1113 | SEM_FN_NAME (or1k32bf,l_rori) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1114 | { | |
1115 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1116 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1117 | int UNUSED written = 0; | |
1118 | IADDR UNUSED pc = abuf->addr; | |
1119 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1120 | ||
1121 | { | |
1122 | USI opval = RORSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6)); | |
1123 | SET_H_GPR (FLD (f_r1), opval); | |
1124 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1125 | } | |
1126 | ||
1127 | return vpc; | |
1128 | #undef FLD | |
1129 | } | |
1130 | ||
1131 | /* l-and: l.and $rD,$rA,$rB */ | |
1132 | ||
1133 | static SEM_PC | |
1134 | SEM_FN_NAME (or1k32bf,l_and) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1135 | { | |
1136 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1137 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1138 | int UNUSED written = 0; | |
1139 | IADDR UNUSED pc = abuf->addr; | |
1140 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1141 | ||
1142 | { | |
1143 | USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1144 | SET_H_GPR (FLD (f_r1), opval); | |
1145 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1146 | } | |
1147 | ||
1148 | return vpc; | |
1149 | #undef FLD | |
1150 | } | |
1151 | ||
1152 | /* l-or: l.or $rD,$rA,$rB */ | |
1153 | ||
1154 | static SEM_PC | |
1155 | SEM_FN_NAME (or1k32bf,l_or) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1156 | { | |
1157 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1158 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1159 | int UNUSED written = 0; | |
1160 | IADDR UNUSED pc = abuf->addr; | |
1161 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1162 | ||
1163 | { | |
1164 | USI opval = ORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1165 | SET_H_GPR (FLD (f_r1), opval); | |
1166 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1167 | } | |
1168 | ||
1169 | return vpc; | |
1170 | #undef FLD | |
1171 | } | |
1172 | ||
1173 | /* l-xor: l.xor $rD,$rA,$rB */ | |
1174 | ||
1175 | static SEM_PC | |
1176 | SEM_FN_NAME (or1k32bf,l_xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1177 | { | |
1178 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1179 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1180 | int UNUSED written = 0; | |
1181 | IADDR UNUSED pc = abuf->addr; | |
1182 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1183 | ||
1184 | { | |
1185 | USI opval = XORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1186 | SET_H_GPR (FLD (f_r1), opval); | |
1187 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1188 | } | |
1189 | ||
1190 | return vpc; | |
1191 | #undef FLD | |
1192 | } | |
1193 | ||
1194 | /* l-add: l.add $rD,$rA,$rB */ | |
1195 | ||
1196 | static SEM_PC | |
1197 | SEM_FN_NAME (or1k32bf,l_add) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1198 | { | |
1199 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1200 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1201 | int UNUSED written = 0; | |
1202 | IADDR UNUSED pc = abuf->addr; | |
1203 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1204 | ||
1205 | { | |
1206 | { | |
1207 | { | |
1208 | BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0); | |
1209 | SET_H_SYS_SR_CY (opval); | |
1210 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
1211 | } | |
1212 | { | |
1213 | BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0); | |
1214 | SET_H_SYS_SR_OV (opval); | |
1215 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
1216 | } | |
1217 | { | |
1218 | USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1219 | SET_H_GPR (FLD (f_r1), opval); | |
1220 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1221 | } | |
1222 | } | |
1223 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
1224 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
1225 | } | |
1226 | } | |
1227 | ||
1228 | return vpc; | |
1229 | #undef FLD | |
1230 | } | |
1231 | ||
1232 | /* l-sub: l.sub $rD,$rA,$rB */ | |
1233 | ||
1234 | static SEM_PC | |
1235 | SEM_FN_NAME (or1k32bf,l_sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1236 | { | |
1237 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1238 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1239 | int UNUSED written = 0; | |
1240 | IADDR UNUSED pc = abuf->addr; | |
1241 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1242 | ||
1243 | { | |
1244 | { | |
1245 | { | |
1246 | BI opval = SUBCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0); | |
1247 | SET_H_SYS_SR_CY (opval); | |
1248 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
1249 | } | |
1250 | { | |
1251 | BI opval = SUBOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0); | |
1252 | SET_H_SYS_SR_OV (opval); | |
1253 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
1254 | } | |
1255 | { | |
1256 | USI opval = SUBSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1257 | SET_H_GPR (FLD (f_r1), opval); | |
1258 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1259 | } | |
1260 | } | |
1261 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
1262 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
1263 | } | |
1264 | } | |
1265 | ||
1266 | return vpc; | |
1267 | #undef FLD | |
1268 | } | |
1269 | ||
1270 | /* l-addc: l.addc $rD,$rA,$rB */ | |
1271 | ||
1272 | static SEM_PC | |
1273 | SEM_FN_NAME (or1k32bf,l_addc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1274 | { | |
1275 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1276 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1277 | int UNUSED written = 0; | |
1278 | IADDR UNUSED pc = abuf->addr; | |
1279 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1280 | ||
1281 | { | |
1282 | { | |
1283 | BI tmp_tmp_sys_sr_cy; | |
1284 | tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY (); | |
1285 | { | |
1286 | BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy); | |
1287 | SET_H_SYS_SR_CY (opval); | |
1288 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
1289 | } | |
1290 | { | |
1291 | BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy); | |
1292 | SET_H_SYS_SR_OV (opval); | |
1293 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
1294 | } | |
1295 | { | |
1296 | USI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy); | |
1297 | SET_H_GPR (FLD (f_r1), opval); | |
1298 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1299 | } | |
1300 | } | |
1301 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
1302 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
1303 | } | |
1304 | } | |
1305 | ||
1306 | return vpc; | |
1307 | #undef FLD | |
1308 | } | |
1309 | ||
1310 | /* l-mul: l.mul $rD,$rA,$rB */ | |
1311 | ||
1312 | static SEM_PC | |
1313 | SEM_FN_NAME (or1k32bf,l_mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1314 | { | |
1315 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1316 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1317 | int UNUSED written = 0; | |
1318 | IADDR UNUSED pc = abuf->addr; | |
1319 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1320 | ||
1321 | { | |
1322 | { | |
1323 | { | |
1324 | BI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1325 | SET_H_SYS_SR_OV (opval); | |
1326 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
1327 | } | |
6e51bfa7 SH |
1328 | { |
1329 | USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1330 | SET_H_GPR (FLD (f_r1), opval); | |
1331 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1332 | } | |
1333 | } | |
1334 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
1335 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
1336 | } | |
1337 | } | |
1338 | ||
1339 | return vpc; | |
1340 | #undef FLD | |
1341 | } | |
1342 | ||
07f5f4c6 RH |
1343 | /* l-muld: l.muld $rA,$rB */ |
1344 | ||
1345 | static SEM_PC | |
1346 | SEM_FN_NAME (or1k32bf,l_muld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1347 | { | |
1348 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1349 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1350 | int UNUSED written = 0; | |
1351 | IADDR UNUSED pc = abuf->addr; | |
1352 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1353 | ||
1354 | { | |
1355 | DI tmp_result; | |
1356 | tmp_result = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3)))); | |
1357 | { | |
1358 | SI opval = SUBWORDDISI (tmp_result, 0); | |
1359 | SET_H_MAC_MACHI (opval); | |
1360 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
1361 | } | |
1362 | { | |
1363 | SI opval = SUBWORDDISI (tmp_result, 1); | |
1364 | SET_H_MAC_MACLO (opval); | |
1365 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
1366 | } | |
1367 | } | |
1368 | ||
1369 | return vpc; | |
1370 | #undef FLD | |
1371 | } | |
1372 | ||
6e51bfa7 SH |
1373 | /* l-mulu: l.mulu $rD,$rA,$rB */ |
1374 | ||
1375 | static SEM_PC | |
1376 | SEM_FN_NAME (or1k32bf,l_mulu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1377 | { | |
1378 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1379 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1380 | int UNUSED written = 0; | |
1381 | IADDR UNUSED pc = abuf->addr; | |
1382 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1383 | ||
1384 | { | |
1385 | { | |
6e51bfa7 SH |
1386 | { |
1387 | BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1388 | SET_H_SYS_SR_CY (opval); | |
1389 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
1390 | } | |
1391 | { | |
1392 | USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1393 | SET_H_GPR (FLD (f_r1), opval); | |
1394 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1395 | } | |
1396 | } | |
07f5f4c6 | 1397 | if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { |
6e51bfa7 SH |
1398 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
1399 | } | |
1400 | } | |
1401 | ||
1402 | return vpc; | |
1403 | #undef FLD | |
1404 | } | |
1405 | ||
07f5f4c6 RH |
1406 | /* l-muldu: l.muldu $rA,$rB */ |
1407 | ||
1408 | static SEM_PC | |
1409 | SEM_FN_NAME (or1k32bf,l_muldu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1410 | { | |
1411 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1412 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1413 | int UNUSED written = 0; | |
1414 | IADDR UNUSED pc = abuf->addr; | |
1415 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1416 | ||
1417 | { | |
1418 | DI tmp_result; | |
1419 | tmp_result = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3)))); | |
1420 | { | |
1421 | SI opval = SUBWORDDISI (tmp_result, 0); | |
1422 | SET_H_MAC_MACHI (opval); | |
1423 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
1424 | } | |
1425 | { | |
1426 | SI opval = SUBWORDDISI (tmp_result, 1); | |
1427 | SET_H_MAC_MACLO (opval); | |
1428 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
1429 | } | |
1430 | } | |
1431 | ||
1432 | return vpc; | |
1433 | #undef FLD | |
1434 | } | |
1435 | ||
6e51bfa7 SH |
1436 | /* l-div: l.div $rD,$rA,$rB */ |
1437 | ||
1438 | static SEM_PC | |
1439 | SEM_FN_NAME (or1k32bf,l_div) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1440 | { | |
1441 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1442 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1443 | int UNUSED written = 0; | |
1444 | IADDR UNUSED pc = abuf->addr; | |
1445 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1446 | ||
6e51bfa7 SH |
1447 | if (NESI (GET_H_GPR (FLD (f_r3)), 0)) { |
1448 | { | |
1449 | { | |
1450 | BI opval = 0; | |
07f5f4c6 RH |
1451 | SET_H_SYS_SR_OV (opval); |
1452 | written |= (1 << 5); | |
1453 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
6e51bfa7 SH |
1454 | } |
1455 | { | |
1456 | SI opval = DIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1457 | SET_H_GPR (FLD (f_r1), opval); | |
07f5f4c6 | 1458 | written |= (1 << 4); |
6e51bfa7 SH |
1459 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
1460 | } | |
1461 | } | |
1462 | } else { | |
07f5f4c6 | 1463 | { |
6e51bfa7 SH |
1464 | { |
1465 | BI opval = 1; | |
6e51bfa7 | 1466 | SET_H_SYS_SR_OV (opval); |
07f5f4c6 | 1467 | written |= (1 << 5); |
6e51bfa7 SH |
1468 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); |
1469 | } | |
07f5f4c6 | 1470 | if (GET_H_SYS_SR_OVE ()) { |
6e51bfa7 SH |
1471 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
1472 | } | |
07f5f4c6 | 1473 | } |
6e51bfa7 SH |
1474 | } |
1475 | ||
1476 | abuf->written = written; | |
1477 | return vpc; | |
1478 | #undef FLD | |
1479 | } | |
1480 | ||
1481 | /* l-divu: l.divu $rD,$rA,$rB */ | |
1482 | ||
1483 | static SEM_PC | |
1484 | SEM_FN_NAME (or1k32bf,l_divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1485 | { | |
1486 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1487 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1488 | int UNUSED written = 0; | |
1489 | IADDR UNUSED pc = abuf->addr; | |
1490 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1491 | ||
6e51bfa7 SH |
1492 | if (NESI (GET_H_GPR (FLD (f_r3)), 0)) { |
1493 | { | |
1494 | { | |
1495 | BI opval = 0; | |
1496 | SET_H_SYS_SR_CY (opval); | |
07f5f4c6 | 1497 | written |= (1 << 5); |
6e51bfa7 SH |
1498 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); |
1499 | } | |
1500 | { | |
1501 | USI opval = UDIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1502 | SET_H_GPR (FLD (f_r1), opval); | |
07f5f4c6 | 1503 | written |= (1 << 4); |
6e51bfa7 SH |
1504 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); |
1505 | } | |
1506 | } | |
1507 | } else { | |
07f5f4c6 | 1508 | { |
6e51bfa7 SH |
1509 | { |
1510 | BI opval = 1; | |
1511 | SET_H_SYS_SR_CY (opval); | |
07f5f4c6 | 1512 | written |= (1 << 5); |
6e51bfa7 SH |
1513 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); |
1514 | } | |
07f5f4c6 | 1515 | if (GET_H_SYS_SR_OVE ()) { |
6e51bfa7 SH |
1516 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); |
1517 | } | |
07f5f4c6 | 1518 | } |
6e51bfa7 SH |
1519 | } |
1520 | ||
1521 | abuf->written = written; | |
1522 | return vpc; | |
1523 | #undef FLD | |
1524 | } | |
1525 | ||
1526 | /* l-ff1: l.ff1 $rD,$rA */ | |
1527 | ||
1528 | static SEM_PC | |
1529 | SEM_FN_NAME (or1k32bf,l_ff1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1530 | { | |
1531 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1532 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1533 | int UNUSED written = 0; | |
1534 | IADDR UNUSED pc = abuf->addr; | |
1535 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1536 | ||
1537 | { | |
1538 | USI opval = or1k32bf_ff1 (current_cpu, GET_H_GPR (FLD (f_r2))); | |
1539 | SET_H_GPR (FLD (f_r1), opval); | |
1540 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1541 | } | |
1542 | ||
1543 | return vpc; | |
1544 | #undef FLD | |
1545 | } | |
1546 | ||
1547 | /* l-fl1: l.fl1 $rD,$rA */ | |
1548 | ||
1549 | static SEM_PC | |
1550 | SEM_FN_NAME (or1k32bf,l_fl1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1551 | { | |
1552 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1553 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1554 | int UNUSED written = 0; | |
1555 | IADDR UNUSED pc = abuf->addr; | |
1556 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1557 | ||
1558 | { | |
1559 | USI opval = or1k32bf_fl1 (current_cpu, GET_H_GPR (FLD (f_r2))); | |
1560 | SET_H_GPR (FLD (f_r1), opval); | |
1561 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1562 | } | |
1563 | ||
1564 | return vpc; | |
1565 | #undef FLD | |
1566 | } | |
1567 | ||
1568 | /* l-andi: l.andi $rD,$rA,$uimm16 */ | |
1569 | ||
1570 | static SEM_PC | |
1571 | SEM_FN_NAME (or1k32bf,l_andi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1572 | { | |
1573 | #define FLD(f) abuf->fields.sfmt_l_mfspr.f | |
1574 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1575 | int UNUSED written = 0; | |
1576 | IADDR UNUSED pc = abuf->addr; | |
1577 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1578 | ||
1579 | { | |
1580 | USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))); | |
1581 | SET_H_GPR (FLD (f_r1), opval); | |
1582 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1583 | } | |
1584 | ||
1585 | return vpc; | |
1586 | #undef FLD | |
1587 | } | |
1588 | ||
1589 | /* l-ori: l.ori $rD,$rA,$uimm16 */ | |
1590 | ||
1591 | static SEM_PC | |
1592 | SEM_FN_NAME (or1k32bf,l_ori) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1593 | { | |
1594 | #define FLD(f) abuf->fields.sfmt_l_mfspr.f | |
1595 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1596 | int UNUSED written = 0; | |
1597 | IADDR UNUSED pc = abuf->addr; | |
1598 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1599 | ||
1600 | { | |
1601 | USI opval = ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))); | |
1602 | SET_H_GPR (FLD (f_r1), opval); | |
1603 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1604 | } | |
1605 | ||
1606 | return vpc; | |
1607 | #undef FLD | |
1608 | } | |
1609 | ||
1610 | /* l-xori: l.xori $rD,$rA,$simm16 */ | |
1611 | ||
1612 | static SEM_PC | |
1613 | SEM_FN_NAME (or1k32bf,l_xori) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1614 | { | |
1615 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
1616 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1617 | int UNUSED written = 0; | |
1618 | IADDR UNUSED pc = abuf->addr; | |
1619 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1620 | ||
1621 | { | |
1622 | USI opval = XORSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
1623 | SET_H_GPR (FLD (f_r1), opval); | |
1624 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1625 | } | |
1626 | ||
1627 | return vpc; | |
1628 | #undef FLD | |
1629 | } | |
1630 | ||
1631 | /* l-addi: l.addi $rD,$rA,$simm16 */ | |
1632 | ||
1633 | static SEM_PC | |
1634 | SEM_FN_NAME (or1k32bf,l_addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1635 | { | |
1636 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
1637 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1638 | int UNUSED written = 0; | |
1639 | IADDR UNUSED pc = abuf->addr; | |
1640 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1641 | ||
1642 | { | |
1643 | { | |
1644 | { | |
1645 | BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0); | |
1646 | SET_H_SYS_SR_CY (opval); | |
1647 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
1648 | } | |
1649 | { | |
1650 | BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0); | |
1651 | SET_H_SYS_SR_OV (opval); | |
1652 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
1653 | } | |
1654 | { | |
1655 | USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
1656 | SET_H_GPR (FLD (f_r1), opval); | |
1657 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1658 | } | |
1659 | } | |
1660 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
1661 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
1662 | } | |
1663 | } | |
1664 | ||
1665 | return vpc; | |
1666 | #undef FLD | |
1667 | } | |
1668 | ||
1669 | /* l-addic: l.addic $rD,$rA,$simm16 */ | |
1670 | ||
1671 | static SEM_PC | |
1672 | SEM_FN_NAME (or1k32bf,l_addic) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1673 | { | |
1674 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
1675 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1676 | int UNUSED written = 0; | |
1677 | IADDR UNUSED pc = abuf->addr; | |
1678 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1679 | ||
1680 | { | |
1681 | { | |
1682 | BI tmp_tmp_sys_sr_cy; | |
1683 | tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY (); | |
1684 | { | |
1685 | BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy); | |
1686 | SET_H_SYS_SR_CY (opval); | |
1687 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
1688 | } | |
1689 | { | |
1690 | BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy); | |
1691 | SET_H_SYS_SR_OV (opval); | |
1692 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
1693 | } | |
1694 | { | |
1695 | SI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy); | |
1696 | SET_H_GPR (FLD (f_r1), opval); | |
1697 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1698 | } | |
1699 | } | |
1700 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
1701 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
1702 | } | |
1703 | } | |
1704 | ||
1705 | return vpc; | |
1706 | #undef FLD | |
1707 | } | |
1708 | ||
1709 | /* l-muli: l.muli $rD,$rA,$simm16 */ | |
1710 | ||
1711 | static SEM_PC | |
1712 | SEM_FN_NAME (or1k32bf,l_muli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1713 | { | |
1714 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
1715 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1716 | int UNUSED written = 0; | |
1717 | IADDR UNUSED pc = abuf->addr; | |
1718 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1719 | ||
1720 | { | |
1721 | { | |
1722 | { | |
1723 | USI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
1724 | SET_H_SYS_SR_OV (opval); | |
1725 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
1726 | } | |
6e51bfa7 SH |
1727 | { |
1728 | USI opval = MULSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
1729 | SET_H_GPR (FLD (f_r1), opval); | |
1730 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1731 | } | |
1732 | } | |
1733 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
1734 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
1735 | } | |
1736 | } | |
1737 | ||
1738 | return vpc; | |
1739 | #undef FLD | |
1740 | } | |
1741 | ||
1742 | /* l-exths: l.exths $rD,$rA */ | |
1743 | ||
1744 | static SEM_PC | |
1745 | SEM_FN_NAME (or1k32bf,l_exths) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1746 | { | |
1747 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1748 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1749 | int UNUSED written = 0; | |
1750 | IADDR UNUSED pc = abuf->addr; | |
1751 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1752 | ||
1753 | { | |
1754 | USI opval = EXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2)))); | |
1755 | SET_H_GPR (FLD (f_r1), opval); | |
1756 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1757 | } | |
1758 | ||
1759 | return vpc; | |
1760 | #undef FLD | |
1761 | } | |
1762 | ||
1763 | /* l-extbs: l.extbs $rD,$rA */ | |
1764 | ||
1765 | static SEM_PC | |
1766 | SEM_FN_NAME (or1k32bf,l_extbs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1767 | { | |
1768 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1769 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1770 | int UNUSED written = 0; | |
1771 | IADDR UNUSED pc = abuf->addr; | |
1772 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1773 | ||
1774 | { | |
1775 | USI opval = EXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2)))); | |
1776 | SET_H_GPR (FLD (f_r1), opval); | |
1777 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1778 | } | |
1779 | ||
1780 | return vpc; | |
1781 | #undef FLD | |
1782 | } | |
1783 | ||
1784 | /* l-exthz: l.exthz $rD,$rA */ | |
1785 | ||
1786 | static SEM_PC | |
1787 | SEM_FN_NAME (or1k32bf,l_exthz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1788 | { | |
1789 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1790 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1791 | int UNUSED written = 0; | |
1792 | IADDR UNUSED pc = abuf->addr; | |
1793 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1794 | ||
1795 | { | |
1796 | USI opval = ZEXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2)))); | |
1797 | SET_H_GPR (FLD (f_r1), opval); | |
1798 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1799 | } | |
1800 | ||
1801 | return vpc; | |
1802 | #undef FLD | |
1803 | } | |
1804 | ||
1805 | /* l-extbz: l.extbz $rD,$rA */ | |
1806 | ||
1807 | static SEM_PC | |
1808 | SEM_FN_NAME (or1k32bf,l_extbz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1809 | { | |
1810 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1811 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1812 | int UNUSED written = 0; | |
1813 | IADDR UNUSED pc = abuf->addr; | |
1814 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1815 | ||
1816 | { | |
1817 | USI opval = ZEXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2)))); | |
1818 | SET_H_GPR (FLD (f_r1), opval); | |
1819 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1820 | } | |
1821 | ||
1822 | return vpc; | |
1823 | #undef FLD | |
1824 | } | |
1825 | ||
1826 | /* l-extws: l.extws $rD,$rA */ | |
1827 | ||
1828 | static SEM_PC | |
1829 | SEM_FN_NAME (or1k32bf,l_extws) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1830 | { | |
1831 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1832 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1833 | int UNUSED written = 0; | |
1834 | IADDR UNUSED pc = abuf->addr; | |
1835 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1836 | ||
1837 | { | |
1838 | USI opval = EXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2)))); | |
1839 | SET_H_GPR (FLD (f_r1), opval); | |
1840 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1841 | } | |
1842 | ||
1843 | return vpc; | |
1844 | #undef FLD | |
1845 | } | |
1846 | ||
1847 | /* l-extwz: l.extwz $rD,$rA */ | |
1848 | ||
1849 | static SEM_PC | |
1850 | SEM_FN_NAME (or1k32bf,l_extwz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1851 | { | |
1852 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
1853 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1854 | int UNUSED written = 0; | |
1855 | IADDR UNUSED pc = abuf->addr; | |
1856 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1857 | ||
1858 | { | |
1859 | USI opval = ZEXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2)))); | |
1860 | SET_H_GPR (FLD (f_r1), opval); | |
1861 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1862 | } | |
1863 | ||
1864 | return vpc; | |
1865 | #undef FLD | |
1866 | } | |
1867 | ||
1868 | /* l-cmov: l.cmov $rD,$rA,$rB */ | |
1869 | ||
1870 | static SEM_PC | |
1871 | SEM_FN_NAME (or1k32bf,l_cmov) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1872 | { | |
1873 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1874 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1875 | int UNUSED written = 0; | |
1876 | IADDR UNUSED pc = abuf->addr; | |
1877 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1878 | ||
1879 | if (GET_H_SYS_SR_F ()) { | |
1880 | { | |
1881 | USI opval = GET_H_GPR (FLD (f_r2)); | |
1882 | SET_H_GPR (FLD (f_r1), opval); | |
1883 | written |= (1 << 3); | |
1884 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1885 | } | |
1886 | } else { | |
1887 | { | |
1888 | USI opval = GET_H_GPR (FLD (f_r3)); | |
1889 | SET_H_GPR (FLD (f_r1), opval); | |
1890 | written |= (1 << 3); | |
1891 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
1892 | } | |
1893 | } | |
1894 | ||
1895 | abuf->written = written; | |
1896 | return vpc; | |
1897 | #undef FLD | |
1898 | } | |
1899 | ||
1900 | /* l-sfgts: l.sfgts $rA,$rB */ | |
1901 | ||
1902 | static SEM_PC | |
1903 | SEM_FN_NAME (or1k32bf,l_sfgts) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1904 | { | |
1905 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1906 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1907 | int UNUSED written = 0; | |
1908 | IADDR UNUSED pc = abuf->addr; | |
1909 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1910 | ||
1911 | { | |
1912 | USI opval = GTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1913 | SET_H_SYS_SR_F (opval); | |
1914 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
1915 | } | |
1916 | ||
1917 | return vpc; | |
1918 | #undef FLD | |
1919 | } | |
1920 | ||
1921 | /* l-sfgtsi: l.sfgtsi $rA,$simm16 */ | |
1922 | ||
1923 | static SEM_PC | |
1924 | SEM_FN_NAME (or1k32bf,l_sfgtsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1925 | { | |
1926 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
1927 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1928 | int UNUSED written = 0; | |
1929 | IADDR UNUSED pc = abuf->addr; | |
1930 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1931 | ||
1932 | { | |
1933 | USI opval = GTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
1934 | SET_H_SYS_SR_F (opval); | |
1935 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
1936 | } | |
1937 | ||
1938 | return vpc; | |
1939 | #undef FLD | |
1940 | } | |
1941 | ||
1942 | /* l-sfgtu: l.sfgtu $rA,$rB */ | |
1943 | ||
1944 | static SEM_PC | |
1945 | SEM_FN_NAME (or1k32bf,l_sfgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1946 | { | |
1947 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1948 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1949 | int UNUSED written = 0; | |
1950 | IADDR UNUSED pc = abuf->addr; | |
1951 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1952 | ||
1953 | { | |
1954 | USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1955 | SET_H_SYS_SR_F (opval); | |
1956 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
1957 | } | |
1958 | ||
1959 | return vpc; | |
1960 | #undef FLD | |
1961 | } | |
1962 | ||
1963 | /* l-sfgtui: l.sfgtui $rA,$simm16 */ | |
1964 | ||
1965 | static SEM_PC | |
1966 | SEM_FN_NAME (or1k32bf,l_sfgtui) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1967 | { | |
1968 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
1969 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1970 | int UNUSED written = 0; | |
1971 | IADDR UNUSED pc = abuf->addr; | |
1972 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1973 | ||
1974 | { | |
1975 | USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
1976 | SET_H_SYS_SR_F (opval); | |
1977 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
1978 | } | |
1979 | ||
1980 | return vpc; | |
1981 | #undef FLD | |
1982 | } | |
1983 | ||
1984 | /* l-sfges: l.sfges $rA,$rB */ | |
1985 | ||
1986 | static SEM_PC | |
1987 | SEM_FN_NAME (or1k32bf,l_sfges) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
1988 | { | |
1989 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
1990 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
1991 | int UNUSED written = 0; | |
1992 | IADDR UNUSED pc = abuf->addr; | |
1993 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
1994 | ||
1995 | { | |
1996 | USI opval = GESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
1997 | SET_H_SYS_SR_F (opval); | |
1998 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
1999 | } | |
2000 | ||
2001 | return vpc; | |
2002 | #undef FLD | |
2003 | } | |
2004 | ||
2005 | /* l-sfgesi: l.sfgesi $rA,$simm16 */ | |
2006 | ||
2007 | static SEM_PC | |
2008 | SEM_FN_NAME (or1k32bf,l_sfgesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2009 | { | |
2010 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2011 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2012 | int UNUSED written = 0; | |
2013 | IADDR UNUSED pc = abuf->addr; | |
2014 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2015 | ||
2016 | { | |
2017 | USI opval = GESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2018 | SET_H_SYS_SR_F (opval); | |
2019 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2020 | } | |
2021 | ||
2022 | return vpc; | |
2023 | #undef FLD | |
2024 | } | |
2025 | ||
2026 | /* l-sfgeu: l.sfgeu $rA,$rB */ | |
2027 | ||
2028 | static SEM_PC | |
2029 | SEM_FN_NAME (or1k32bf,l_sfgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2030 | { | |
2031 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2032 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2033 | int UNUSED written = 0; | |
2034 | IADDR UNUSED pc = abuf->addr; | |
2035 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2036 | ||
2037 | { | |
2038 | USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
2039 | SET_H_SYS_SR_F (opval); | |
2040 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2041 | } | |
2042 | ||
2043 | return vpc; | |
2044 | #undef FLD | |
2045 | } | |
2046 | ||
2047 | /* l-sfgeui: l.sfgeui $rA,$simm16 */ | |
2048 | ||
2049 | static SEM_PC | |
2050 | SEM_FN_NAME (or1k32bf,l_sfgeui) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2051 | { | |
2052 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2053 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2054 | int UNUSED written = 0; | |
2055 | IADDR UNUSED pc = abuf->addr; | |
2056 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2057 | ||
2058 | { | |
2059 | USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2060 | SET_H_SYS_SR_F (opval); | |
2061 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2062 | } | |
2063 | ||
2064 | return vpc; | |
2065 | #undef FLD | |
2066 | } | |
2067 | ||
2068 | /* l-sflts: l.sflts $rA,$rB */ | |
2069 | ||
2070 | static SEM_PC | |
2071 | SEM_FN_NAME (or1k32bf,l_sflts) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2072 | { | |
2073 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2074 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2075 | int UNUSED written = 0; | |
2076 | IADDR UNUSED pc = abuf->addr; | |
2077 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2078 | ||
2079 | { | |
2080 | USI opval = LTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
2081 | SET_H_SYS_SR_F (opval); | |
2082 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2083 | } | |
2084 | ||
2085 | return vpc; | |
2086 | #undef FLD | |
2087 | } | |
2088 | ||
2089 | /* l-sfltsi: l.sfltsi $rA,$simm16 */ | |
2090 | ||
2091 | static SEM_PC | |
2092 | SEM_FN_NAME (or1k32bf,l_sfltsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2093 | { | |
2094 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2095 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2096 | int UNUSED written = 0; | |
2097 | IADDR UNUSED pc = abuf->addr; | |
2098 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2099 | ||
2100 | { | |
2101 | USI opval = LTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2102 | SET_H_SYS_SR_F (opval); | |
2103 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2104 | } | |
2105 | ||
2106 | return vpc; | |
2107 | #undef FLD | |
2108 | } | |
2109 | ||
2110 | /* l-sfltu: l.sfltu $rA,$rB */ | |
2111 | ||
2112 | static SEM_PC | |
2113 | SEM_FN_NAME (or1k32bf,l_sfltu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2114 | { | |
2115 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2116 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2117 | int UNUSED written = 0; | |
2118 | IADDR UNUSED pc = abuf->addr; | |
2119 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2120 | ||
2121 | { | |
2122 | USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
2123 | SET_H_SYS_SR_F (opval); | |
2124 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2125 | } | |
2126 | ||
2127 | return vpc; | |
2128 | #undef FLD | |
2129 | } | |
2130 | ||
2131 | /* l-sfltui: l.sfltui $rA,$simm16 */ | |
2132 | ||
2133 | static SEM_PC | |
2134 | SEM_FN_NAME (or1k32bf,l_sfltui) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2135 | { | |
2136 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2137 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2138 | int UNUSED written = 0; | |
2139 | IADDR UNUSED pc = abuf->addr; | |
2140 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2141 | ||
2142 | { | |
2143 | USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2144 | SET_H_SYS_SR_F (opval); | |
2145 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2146 | } | |
2147 | ||
2148 | return vpc; | |
2149 | #undef FLD | |
2150 | } | |
2151 | ||
2152 | /* l-sfles: l.sfles $rA,$rB */ | |
2153 | ||
2154 | static SEM_PC | |
2155 | SEM_FN_NAME (or1k32bf,l_sfles) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2156 | { | |
2157 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2158 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2159 | int UNUSED written = 0; | |
2160 | IADDR UNUSED pc = abuf->addr; | |
2161 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2162 | ||
2163 | { | |
2164 | USI opval = LESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
2165 | SET_H_SYS_SR_F (opval); | |
2166 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2167 | } | |
2168 | ||
2169 | return vpc; | |
2170 | #undef FLD | |
2171 | } | |
2172 | ||
2173 | /* l-sflesi: l.sflesi $rA,$simm16 */ | |
2174 | ||
2175 | static SEM_PC | |
2176 | SEM_FN_NAME (or1k32bf,l_sflesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2177 | { | |
2178 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2179 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2180 | int UNUSED written = 0; | |
2181 | IADDR UNUSED pc = abuf->addr; | |
2182 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2183 | ||
2184 | { | |
2185 | USI opval = LESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2186 | SET_H_SYS_SR_F (opval); | |
2187 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2188 | } | |
2189 | ||
2190 | return vpc; | |
2191 | #undef FLD | |
2192 | } | |
2193 | ||
2194 | /* l-sfleu: l.sfleu $rA,$rB */ | |
2195 | ||
2196 | static SEM_PC | |
2197 | SEM_FN_NAME (or1k32bf,l_sfleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2198 | { | |
2199 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2200 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2201 | int UNUSED written = 0; | |
2202 | IADDR UNUSED pc = abuf->addr; | |
2203 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2204 | ||
2205 | { | |
2206 | USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
2207 | SET_H_SYS_SR_F (opval); | |
2208 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2209 | } | |
2210 | ||
2211 | return vpc; | |
2212 | #undef FLD | |
2213 | } | |
2214 | ||
2215 | /* l-sfleui: l.sfleui $rA,$simm16 */ | |
2216 | ||
2217 | static SEM_PC | |
2218 | SEM_FN_NAME (or1k32bf,l_sfleui) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2219 | { | |
2220 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2221 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2222 | int UNUSED written = 0; | |
2223 | IADDR UNUSED pc = abuf->addr; | |
2224 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2225 | ||
2226 | { | |
2227 | USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2228 | SET_H_SYS_SR_F (opval); | |
2229 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2230 | } | |
2231 | ||
2232 | return vpc; | |
2233 | #undef FLD | |
2234 | } | |
2235 | ||
2236 | /* l-sfeq: l.sfeq $rA,$rB */ | |
2237 | ||
2238 | static SEM_PC | |
2239 | SEM_FN_NAME (or1k32bf,l_sfeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2240 | { | |
2241 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2242 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2243 | int UNUSED written = 0; | |
2244 | IADDR UNUSED pc = abuf->addr; | |
2245 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2246 | ||
2247 | { | |
2248 | USI opval = EQSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
2249 | SET_H_SYS_SR_F (opval); | |
2250 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2251 | } | |
2252 | ||
2253 | return vpc; | |
2254 | #undef FLD | |
2255 | } | |
2256 | ||
2257 | /* l-sfeqi: l.sfeqi $rA,$simm16 */ | |
2258 | ||
2259 | static SEM_PC | |
2260 | SEM_FN_NAME (or1k32bf,l_sfeqi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2261 | { | |
2262 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2263 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2264 | int UNUSED written = 0; | |
2265 | IADDR UNUSED pc = abuf->addr; | |
2266 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2267 | ||
2268 | { | |
2269 | USI opval = EQSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2270 | SET_H_SYS_SR_F (opval); | |
2271 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2272 | } | |
2273 | ||
2274 | return vpc; | |
2275 | #undef FLD | |
2276 | } | |
2277 | ||
2278 | /* l-sfne: l.sfne $rA,$rB */ | |
2279 | ||
2280 | static SEM_PC | |
2281 | SEM_FN_NAME (or1k32bf,l_sfne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2282 | { | |
2283 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2284 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2285 | int UNUSED written = 0; | |
2286 | IADDR UNUSED pc = abuf->addr; | |
2287 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2288 | ||
2289 | { | |
2290 | USI opval = NESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); | |
2291 | SET_H_SYS_SR_F (opval); | |
2292 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2293 | } | |
2294 | ||
2295 | return vpc; | |
2296 | #undef FLD | |
2297 | } | |
2298 | ||
2299 | /* l-sfnei: l.sfnei $rA,$simm16 */ | |
2300 | ||
2301 | static SEM_PC | |
2302 | SEM_FN_NAME (or1k32bf,l_sfnei) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2303 | { | |
2304 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2305 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2306 | int UNUSED written = 0; | |
2307 | IADDR UNUSED pc = abuf->addr; | |
2308 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2309 | ||
2310 | { | |
2311 | USI opval = NESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); | |
2312 | SET_H_SYS_SR_F (opval); | |
2313 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2314 | } | |
2315 | ||
2316 | return vpc; | |
2317 | #undef FLD | |
2318 | } | |
2319 | ||
2320 | /* l-mac: l.mac $rA,$rB */ | |
2321 | ||
2322 | static SEM_PC | |
2323 | SEM_FN_NAME (or1k32bf,l_mac) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2324 | { | |
2325 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2326 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2327 | int UNUSED written = 0; | |
2328 | IADDR UNUSED pc = abuf->addr; | |
2329 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2330 | ||
2331 | { | |
07f5f4c6 RH |
2332 | { |
2333 | DI tmp_prod; | |
2334 | DI tmp_mac; | |
6e51bfa7 | 2335 | DI tmp_result; |
07f5f4c6 RH |
2336 | tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3)))); |
2337 | tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); | |
2338 | tmp_result = ADDDI (tmp_prod, tmp_mac); | |
6e51bfa7 SH |
2339 | { |
2340 | SI opval = SUBWORDDISI (tmp_result, 0); | |
2341 | SET_H_MAC_MACHI (opval); | |
2342 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
2343 | } | |
2344 | { | |
2345 | SI opval = SUBWORDDISI (tmp_result, 1); | |
2346 | SET_H_MAC_MACLO (opval); | |
2347 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
2348 | } | |
07f5f4c6 RH |
2349 | { |
2350 | BI opval = ADDOFDI (tmp_prod, tmp_mac, 0); | |
2351 | SET_H_SYS_SR_OV (opval); | |
2352 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
2353 | } | |
2354 | } | |
2355 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
2356 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
2357 | } | |
2358 | } | |
2359 | ||
2360 | return vpc; | |
2361 | #undef FLD | |
2362 | } | |
2363 | ||
2364 | /* l-maci: l.maci $rA,${simm16} */ | |
2365 | ||
2366 | static SEM_PC | |
2367 | SEM_FN_NAME (or1k32bf,l_maci) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2368 | { | |
2369 | #define FLD(f) abuf->fields.sfmt_l_lwz.f | |
2370 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2371 | int UNUSED written = 0; | |
2372 | IADDR UNUSED pc = abuf->addr; | |
2373 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2374 | ||
2375 | { | |
2376 | { | |
2377 | DI tmp_prod; | |
2378 | DI tmp_mac; | |
2379 | DI tmp_result; | |
2380 | tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (FLD (f_simm16))); | |
2381 | tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); | |
2382 | tmp_result = ADDDI (tmp_mac, tmp_prod); | |
2383 | { | |
2384 | SI opval = SUBWORDDISI (tmp_result, 0); | |
2385 | SET_H_MAC_MACHI (opval); | |
2386 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
2387 | } | |
2388 | { | |
2389 | SI opval = SUBWORDDISI (tmp_result, 1); | |
2390 | SET_H_MAC_MACLO (opval); | |
2391 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
2392 | } | |
2393 | { | |
2394 | BI opval = ADDOFDI (tmp_prod, tmp_mac, 0); | |
2395 | SET_H_SYS_SR_OV (opval); | |
2396 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
2397 | } | |
2398 | } | |
2399 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
2400 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
2401 | } | |
2402 | } | |
2403 | ||
2404 | return vpc; | |
2405 | #undef FLD | |
2406 | } | |
2407 | ||
2408 | /* l-macu: l.macu $rA,$rB */ | |
2409 | ||
2410 | static SEM_PC | |
2411 | SEM_FN_NAME (or1k32bf,l_macu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2412 | { | |
2413 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2414 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2415 | int UNUSED written = 0; | |
2416 | IADDR UNUSED pc = abuf->addr; | |
2417 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2418 | ||
2419 | { | |
2420 | { | |
2421 | DI tmp_prod; | |
2422 | DI tmp_mac; | |
2423 | DI tmp_result; | |
2424 | tmp_prod = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3)))); | |
2425 | tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); | |
2426 | tmp_result = ADDDI (tmp_prod, tmp_mac); | |
2427 | { | |
2428 | SI opval = SUBWORDDISI (tmp_result, 0); | |
2429 | SET_H_MAC_MACHI (opval); | |
2430 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
2431 | } | |
2432 | { | |
2433 | SI opval = SUBWORDDISI (tmp_result, 1); | |
2434 | SET_H_MAC_MACLO (opval); | |
2435 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
2436 | } | |
2437 | { | |
2438 | BI opval = ADDCFDI (tmp_prod, tmp_mac, 0); | |
2439 | SET_H_SYS_SR_CY (opval); | |
2440 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
2441 | } | |
2442 | } | |
2443 | if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { | |
2444 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
2445 | } | |
6e51bfa7 SH |
2446 | } |
2447 | ||
2448 | return vpc; | |
2449 | #undef FLD | |
2450 | } | |
2451 | ||
2452 | /* l-msb: l.msb $rA,$rB */ | |
2453 | ||
2454 | static SEM_PC | |
2455 | SEM_FN_NAME (or1k32bf,l_msb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2456 | { | |
2457 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2458 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2459 | int UNUSED written = 0; | |
2460 | IADDR UNUSED pc = abuf->addr; | |
2461 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2462 | ||
2463 | { | |
07f5f4c6 RH |
2464 | { |
2465 | DI tmp_prod; | |
2466 | DI tmp_mac; | |
6e51bfa7 | 2467 | DI tmp_result; |
07f5f4c6 RH |
2468 | tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3)))); |
2469 | tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); | |
2470 | tmp_result = SUBDI (tmp_mac, tmp_prod); | |
6e51bfa7 SH |
2471 | { |
2472 | SI opval = SUBWORDDISI (tmp_result, 0); | |
2473 | SET_H_MAC_MACHI (opval); | |
2474 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
2475 | } | |
2476 | { | |
2477 | SI opval = SUBWORDDISI (tmp_result, 1); | |
2478 | SET_H_MAC_MACLO (opval); | |
2479 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
2480 | } | |
07f5f4c6 RH |
2481 | { |
2482 | BI opval = SUBOFDI (tmp_mac, tmp_result, 0); | |
2483 | SET_H_SYS_SR_OV (opval); | |
2484 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); | |
2485 | } | |
2486 | } | |
2487 | if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { | |
2488 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
2489 | } | |
6e51bfa7 SH |
2490 | } |
2491 | ||
2492 | return vpc; | |
2493 | #undef FLD | |
2494 | } | |
2495 | ||
07f5f4c6 | 2496 | /* l-msbu: l.msbu $rA,$rB */ |
6e51bfa7 SH |
2497 | |
2498 | static SEM_PC | |
07f5f4c6 | 2499 | SEM_FN_NAME (or1k32bf,l_msbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) |
6e51bfa7 | 2500 | { |
07f5f4c6 | 2501 | #define FLD(f) abuf->fields.sfmt_l_sll.f |
6e51bfa7 SH |
2502 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); |
2503 | int UNUSED written = 0; | |
2504 | IADDR UNUSED pc = abuf->addr; | |
2505 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2506 | ||
2507 | { | |
07f5f4c6 RH |
2508 | { |
2509 | DI tmp_prod; | |
2510 | DI tmp_mac; | |
6e51bfa7 | 2511 | DI tmp_result; |
07f5f4c6 RH |
2512 | tmp_prod = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3)))); |
2513 | tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); | |
2514 | tmp_result = SUBDI (tmp_mac, tmp_prod); | |
6e51bfa7 SH |
2515 | { |
2516 | SI opval = SUBWORDDISI (tmp_result, 0); | |
2517 | SET_H_MAC_MACHI (opval); | |
2518 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); | |
2519 | } | |
2520 | { | |
2521 | SI opval = SUBWORDDISI (tmp_result, 1); | |
2522 | SET_H_MAC_MACLO (opval); | |
2523 | CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); | |
2524 | } | |
07f5f4c6 RH |
2525 | { |
2526 | BI opval = SUBCFDI (tmp_mac, tmp_result, 0); | |
2527 | SET_H_SYS_SR_CY (opval); | |
2528 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); | |
2529 | } | |
2530 | } | |
2531 | if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { | |
2532 | or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); | |
2533 | } | |
6e51bfa7 SH |
2534 | } |
2535 | ||
2536 | return vpc; | |
2537 | #undef FLD | |
2538 | } | |
2539 | ||
2540 | /* l-cust1: l.cust1 */ | |
2541 | ||
2542 | static SEM_PC | |
2543 | SEM_FN_NAME (or1k32bf,l_cust1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2544 | { | |
2545 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2546 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2547 | int UNUSED written = 0; | |
2548 | IADDR UNUSED pc = abuf->addr; | |
2549 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2550 | ||
2551 | ((void) 0); /*nop*/ | |
2552 | ||
2553 | return vpc; | |
2554 | #undef FLD | |
2555 | } | |
2556 | ||
2557 | /* l-cust2: l.cust2 */ | |
2558 | ||
2559 | static SEM_PC | |
2560 | SEM_FN_NAME (or1k32bf,l_cust2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2561 | { | |
2562 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2563 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2564 | int UNUSED written = 0; | |
2565 | IADDR UNUSED pc = abuf->addr; | |
2566 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2567 | ||
2568 | ((void) 0); /*nop*/ | |
2569 | ||
2570 | return vpc; | |
2571 | #undef FLD | |
2572 | } | |
2573 | ||
2574 | /* l-cust3: l.cust3 */ | |
2575 | ||
2576 | static SEM_PC | |
2577 | SEM_FN_NAME (or1k32bf,l_cust3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2578 | { | |
2579 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2580 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2581 | int UNUSED written = 0; | |
2582 | IADDR UNUSED pc = abuf->addr; | |
2583 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2584 | ||
2585 | ((void) 0); /*nop*/ | |
2586 | ||
2587 | return vpc; | |
2588 | #undef FLD | |
2589 | } | |
2590 | ||
2591 | /* l-cust4: l.cust4 */ | |
2592 | ||
2593 | static SEM_PC | |
2594 | SEM_FN_NAME (or1k32bf,l_cust4) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2595 | { | |
2596 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2597 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2598 | int UNUSED written = 0; | |
2599 | IADDR UNUSED pc = abuf->addr; | |
2600 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2601 | ||
2602 | ((void) 0); /*nop*/ | |
2603 | ||
2604 | return vpc; | |
2605 | #undef FLD | |
2606 | } | |
2607 | ||
2608 | /* l-cust5: l.cust5 */ | |
2609 | ||
2610 | static SEM_PC | |
2611 | SEM_FN_NAME (or1k32bf,l_cust5) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2612 | { | |
2613 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2614 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2615 | int UNUSED written = 0; | |
2616 | IADDR UNUSED pc = abuf->addr; | |
2617 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2618 | ||
2619 | ((void) 0); /*nop*/ | |
2620 | ||
2621 | return vpc; | |
2622 | #undef FLD | |
2623 | } | |
2624 | ||
2625 | /* l-cust6: l.cust6 */ | |
2626 | ||
2627 | static SEM_PC | |
2628 | SEM_FN_NAME (or1k32bf,l_cust6) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2629 | { | |
2630 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2631 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2632 | int UNUSED written = 0; | |
2633 | IADDR UNUSED pc = abuf->addr; | |
2634 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2635 | ||
2636 | ((void) 0); /*nop*/ | |
2637 | ||
2638 | return vpc; | |
2639 | #undef FLD | |
2640 | } | |
2641 | ||
2642 | /* l-cust7: l.cust7 */ | |
2643 | ||
2644 | static SEM_PC | |
2645 | SEM_FN_NAME (or1k32bf,l_cust7) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2646 | { | |
2647 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2648 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2649 | int UNUSED written = 0; | |
2650 | IADDR UNUSED pc = abuf->addr; | |
2651 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2652 | ||
2653 | ((void) 0); /*nop*/ | |
2654 | ||
2655 | return vpc; | |
2656 | #undef FLD | |
2657 | } | |
2658 | ||
2659 | /* l-cust8: l.cust8 */ | |
2660 | ||
2661 | static SEM_PC | |
2662 | SEM_FN_NAME (or1k32bf,l_cust8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2663 | { | |
2664 | #define FLD(f) abuf->fields.sfmt_empty.f | |
2665 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2666 | int UNUSED written = 0; | |
2667 | IADDR UNUSED pc = abuf->addr; | |
2668 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2669 | ||
2670 | ((void) 0); /*nop*/ | |
2671 | ||
2672 | return vpc; | |
2673 | #undef FLD | |
2674 | } | |
2675 | ||
2676 | /* lf-add-s: lf.add.s $rDSF,$rASF,$rBSF */ | |
2677 | ||
2678 | static SEM_PC | |
2679 | SEM_FN_NAME (or1k32bf,lf_add_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2680 | { | |
2681 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2682 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2683 | int UNUSED written = 0; | |
2684 | IADDR UNUSED pc = abuf->addr; | |
2685 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2686 | ||
2687 | { | |
2688 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2689 | SET_H_FSR (FLD (f_r1), opval); | |
2690 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); | |
2691 | } | |
2692 | ||
2693 | return vpc; | |
2694 | #undef FLD | |
2695 | } | |
2696 | ||
7ccbb443 SH |
2697 | /* lf-add-d32: lf.add.d $rDD32F,$rAD32F,$rBD32F */ |
2698 | ||
2699 | static SEM_PC | |
2700 | SEM_FN_NAME (or1k32bf,lf_add_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2701 | { | |
2702 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
2703 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2704 | int UNUSED written = 0; | |
2705 | IADDR UNUSED pc = abuf->addr; | |
2706 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2707 | ||
2708 | { | |
2709 | DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); | |
2710 | SET_H_FD32R (FLD (f_rdd32), opval); | |
2711 | CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval); | |
2712 | } | |
2713 | ||
2714 | return vpc; | |
2715 | #undef FLD | |
2716 | } | |
2717 | ||
6e51bfa7 SH |
2718 | /* lf-sub-s: lf.sub.s $rDSF,$rASF,$rBSF */ |
2719 | ||
2720 | static SEM_PC | |
2721 | SEM_FN_NAME (or1k32bf,lf_sub_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2722 | { | |
2723 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2724 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2725 | int UNUSED written = 0; | |
2726 | IADDR UNUSED pc = abuf->addr; | |
2727 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2728 | ||
2729 | { | |
2730 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2731 | SET_H_FSR (FLD (f_r1), opval); | |
2732 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); | |
2733 | } | |
2734 | ||
2735 | return vpc; | |
2736 | #undef FLD | |
2737 | } | |
2738 | ||
7ccbb443 SH |
2739 | /* lf-sub-d32: lf.sub.d $rDD32F,$rAD32F,$rBD32F */ |
2740 | ||
2741 | static SEM_PC | |
2742 | SEM_FN_NAME (or1k32bf,lf_sub_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2743 | { | |
2744 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
2745 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2746 | int UNUSED written = 0; | |
2747 | IADDR UNUSED pc = abuf->addr; | |
2748 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2749 | ||
2750 | { | |
2751 | DF opval = CGEN_CPU_FPU (current_cpu)->ops->subdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); | |
2752 | SET_H_FD32R (FLD (f_rdd32), opval); | |
2753 | CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval); | |
2754 | } | |
2755 | ||
2756 | return vpc; | |
2757 | #undef FLD | |
2758 | } | |
2759 | ||
6e51bfa7 SH |
2760 | /* lf-mul-s: lf.mul.s $rDSF,$rASF,$rBSF */ |
2761 | ||
2762 | static SEM_PC | |
2763 | SEM_FN_NAME (or1k32bf,lf_mul_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2764 | { | |
2765 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2766 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2767 | int UNUSED written = 0; | |
2768 | IADDR UNUSED pc = abuf->addr; | |
2769 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2770 | ||
2771 | { | |
2772 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2773 | SET_H_FSR (FLD (f_r1), opval); | |
2774 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); | |
2775 | } | |
2776 | ||
2777 | return vpc; | |
2778 | #undef FLD | |
2779 | } | |
2780 | ||
7ccbb443 SH |
2781 | /* lf-mul-d32: lf.mul.d $rDD32F,$rAD32F,$rBD32F */ |
2782 | ||
2783 | static SEM_PC | |
2784 | SEM_FN_NAME (or1k32bf,lf_mul_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2785 | { | |
2786 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
2787 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2788 | int UNUSED written = 0; | |
2789 | IADDR UNUSED pc = abuf->addr; | |
2790 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2791 | ||
2792 | { | |
2793 | DF opval = CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); | |
2794 | SET_H_FD32R (FLD (f_rdd32), opval); | |
2795 | CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval); | |
2796 | } | |
2797 | ||
2798 | return vpc; | |
2799 | #undef FLD | |
2800 | } | |
2801 | ||
6e51bfa7 SH |
2802 | /* lf-div-s: lf.div.s $rDSF,$rASF,$rBSF */ |
2803 | ||
2804 | static SEM_PC | |
2805 | SEM_FN_NAME (or1k32bf,lf_div_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2806 | { | |
2807 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2808 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2809 | int UNUSED written = 0; | |
2810 | IADDR UNUSED pc = abuf->addr; | |
2811 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2812 | ||
2813 | { | |
2814 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2815 | SET_H_FSR (FLD (f_r1), opval); | |
2816 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); | |
2817 | } | |
2818 | ||
2819 | return vpc; | |
2820 | #undef FLD | |
2821 | } | |
2822 | ||
7ccbb443 SH |
2823 | /* lf-div-d32: lf.div.d $rDD32F,$rAD32F,$rBD32F */ |
2824 | ||
2825 | static SEM_PC | |
2826 | SEM_FN_NAME (or1k32bf,lf_div_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2827 | { | |
2828 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
2829 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2830 | int UNUSED written = 0; | |
2831 | IADDR UNUSED pc = abuf->addr; | |
2832 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2833 | ||
2834 | { | |
2835 | DF opval = CGEN_CPU_FPU (current_cpu)->ops->divdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); | |
2836 | SET_H_FD32R (FLD (f_rdd32), opval); | |
2837 | CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval); | |
2838 | } | |
2839 | ||
2840 | return vpc; | |
2841 | #undef FLD | |
2842 | } | |
2843 | ||
6e51bfa7 SH |
2844 | /* lf-rem-s: lf.rem.s $rDSF,$rASF,$rBSF */ |
2845 | ||
2846 | static SEM_PC | |
2847 | SEM_FN_NAME (or1k32bf,lf_rem_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2848 | { | |
2849 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2850 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2851 | int UNUSED written = 0; | |
2852 | IADDR UNUSED pc = abuf->addr; | |
2853 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2854 | ||
2855 | { | |
2856 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->remsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2857 | SET_H_FSR (FLD (f_r1), opval); | |
2858 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); | |
2859 | } | |
2860 | ||
2861 | return vpc; | |
2862 | #undef FLD | |
2863 | } | |
2864 | ||
7ccbb443 SH |
2865 | /* lf-rem-d32: lf.rem.d $rDD32F,$rAD32F,$rBD32F */ |
2866 | ||
2867 | static SEM_PC | |
2868 | SEM_FN_NAME (or1k32bf,lf_rem_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2869 | { | |
2870 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
2871 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2872 | int UNUSED written = 0; | |
2873 | IADDR UNUSED pc = abuf->addr; | |
2874 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2875 | ||
2876 | { | |
2877 | DF opval = CGEN_CPU_FPU (current_cpu)->ops->remdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); | |
2878 | SET_H_FD32R (FLD (f_rdd32), opval); | |
2879 | CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval); | |
2880 | } | |
2881 | ||
2882 | return vpc; | |
2883 | #undef FLD | |
2884 | } | |
2885 | ||
6e51bfa7 SH |
2886 | /* lf-itof-s: lf.itof.s $rDSF,$rA */ |
2887 | ||
2888 | static SEM_PC | |
2889 | SEM_FN_NAME (or1k32bf,lf_itof_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2890 | { | |
2891 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
2892 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2893 | int UNUSED written = 0; | |
2894 | IADDR UNUSED pc = abuf->addr; | |
2895 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2896 | ||
2897 | { | |
2898 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), TRUNCSISI (GET_H_GPR (FLD (f_r2)))); | |
2899 | SET_H_FSR (FLD (f_r1), opval); | |
2900 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); | |
2901 | } | |
2902 | ||
2903 | return vpc; | |
2904 | #undef FLD | |
2905 | } | |
2906 | ||
7ccbb443 SH |
2907 | /* lf-itof-d32: lf.itof.d $rDD32F,$rADI */ |
2908 | ||
2909 | static SEM_PC | |
2910 | SEM_FN_NAME (or1k32bf,lf_itof_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2911 | { | |
2912 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
2913 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2914 | int UNUSED written = 0; | |
2915 | IADDR UNUSED pc = abuf->addr; | |
2916 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2917 | ||
2918 | { | |
2919 | DF opval = CGEN_CPU_FPU (current_cpu)->ops->floatdidf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_I64R (FLD (f_rad32))); | |
2920 | SET_H_FD32R (FLD (f_rdd32), opval); | |
2921 | CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval); | |
2922 | } | |
2923 | ||
2924 | return vpc; | |
2925 | #undef FLD | |
2926 | } | |
2927 | ||
6e51bfa7 SH |
2928 | /* lf-ftoi-s: lf.ftoi.s $rD,$rASF */ |
2929 | ||
2930 | static SEM_PC | |
2931 | SEM_FN_NAME (or1k32bf,lf_ftoi_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2932 | { | |
2933 | #define FLD(f) abuf->fields.sfmt_l_slli.f | |
2934 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2935 | int UNUSED written = 0; | |
2936 | IADDR UNUSED pc = abuf->addr; | |
2937 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2938 | ||
2939 | { | |
2940 | SI opval = EXTSISI (CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FSR (FLD (f_r2)))); | |
2941 | SET_H_GPR (FLD (f_r1), opval); | |
2942 | CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); | |
2943 | } | |
2944 | ||
2945 | return vpc; | |
2946 | #undef FLD | |
2947 | } | |
2948 | ||
7ccbb443 SH |
2949 | /* lf-ftoi-d32: lf.ftoi.d $rDDI,$rAD32F */ |
2950 | ||
2951 | static SEM_PC | |
2952 | SEM_FN_NAME (or1k32bf,lf_ftoi_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
2953 | { | |
2954 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
2955 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2956 | int UNUSED written = 0; | |
2957 | IADDR UNUSED pc = abuf->addr; | |
2958 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2959 | ||
2960 | { | |
2961 | DI opval = CGEN_CPU_FPU (current_cpu)->ops->fixdfdi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FD32R (FLD (f_rad32))); | |
2962 | SET_H_I64R (FLD (f_rdd32), opval); | |
2963 | CGEN_TRACE_RESULT (current_cpu, abuf, "i64r", 'D', opval); | |
2964 | } | |
2965 | ||
2966 | return vpc; | |
2967 | #undef FLD | |
2968 | } | |
2969 | ||
2970 | /* lf-sfeq-s: lf.sfeq.s $rASF,$rBSF */ | |
6e51bfa7 SH |
2971 | |
2972 | static SEM_PC | |
7ccbb443 | 2973 | SEM_FN_NAME (or1k32bf,lf_sfeq_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) |
6e51bfa7 SH |
2974 | { |
2975 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
2976 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2977 | int UNUSED written = 0; | |
2978 | IADDR UNUSED pc = abuf->addr; | |
2979 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
2980 | ||
2981 | { | |
2982 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
2983 | SET_H_SYS_SR_F (opval); | |
2984 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
2985 | } | |
2986 | ||
2987 | return vpc; | |
2988 | #undef FLD | |
2989 | } | |
2990 | ||
7ccbb443 | 2991 | /* lf-sfeq-d32: lf.sfeq.d $rAD32F,$rBD32F */ |
6e51bfa7 SH |
2992 | |
2993 | static SEM_PC | |
7ccbb443 SH |
2994 | SEM_FN_NAME (or1k32bf,lf_sfeq_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) |
2995 | { | |
2996 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
2997 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
2998 | int UNUSED written = 0; | |
2999 | IADDR UNUSED pc = abuf->addr; | |
3000 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3001 | ||
3002 | { | |
3003 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); | |
3004 | SET_H_SYS_SR_F (opval); | |
3005 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3006 | } | |
3007 | ||
3008 | return vpc; | |
3009 | #undef FLD | |
3010 | } | |
3011 | ||
3012 | /* lf-sfne-s: lf.sfne.s $rASF,$rBSF */ | |
3013 | ||
3014 | static SEM_PC | |
3015 | SEM_FN_NAME (or1k32bf,lf_sfne_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
6e51bfa7 SH |
3016 | { |
3017 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
3018 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3019 | int UNUSED written = 0; | |
3020 | IADDR UNUSED pc = abuf->addr; | |
3021 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3022 | ||
3023 | { | |
3024 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
3025 | SET_H_SYS_SR_F (opval); | |
3026 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3027 | } | |
3028 | ||
3029 | return vpc; | |
3030 | #undef FLD | |
3031 | } | |
3032 | ||
7ccbb443 SH |
3033 | /* lf-sfne-d32: lf.sfne.d $rAD32F,$rBD32F */ |
3034 | ||
3035 | static SEM_PC | |
3036 | SEM_FN_NAME (or1k32bf,lf_sfne_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3037 | { | |
3038 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
3039 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3040 | int UNUSED written = 0; | |
3041 | IADDR UNUSED pc = abuf->addr; | |
3042 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3043 | ||
3044 | { | |
3045 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); | |
3046 | SET_H_SYS_SR_F (opval); | |
3047 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3048 | } | |
3049 | ||
3050 | return vpc; | |
3051 | #undef FLD | |
3052 | } | |
3053 | ||
3054 | /* lf-sfge-s: lf.sfge.s $rASF,$rBSF */ | |
6e51bfa7 SH |
3055 | |
3056 | static SEM_PC | |
7ccbb443 | 3057 | SEM_FN_NAME (or1k32bf,lf_sfge_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) |
6e51bfa7 SH |
3058 | { |
3059 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
3060 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3061 | int UNUSED written = 0; | |
3062 | IADDR UNUSED pc = abuf->addr; | |
3063 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3064 | ||
3065 | { | |
3066 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
3067 | SET_H_SYS_SR_F (opval); | |
3068 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3069 | } | |
3070 | ||
3071 | return vpc; | |
3072 | #undef FLD | |
3073 | } | |
3074 | ||
7ccbb443 SH |
3075 | /* lf-sfge-d32: lf.sfge.d $rAD32F,$rBD32F */ |
3076 | ||
3077 | static SEM_PC | |
3078 | SEM_FN_NAME (or1k32bf,lf_sfge_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3079 | { | |
3080 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
3081 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3082 | int UNUSED written = 0; | |
3083 | IADDR UNUSED pc = abuf->addr; | |
3084 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3085 | ||
3086 | { | |
3087 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); | |
3088 | SET_H_SYS_SR_F (opval); | |
3089 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3090 | } | |
3091 | ||
3092 | return vpc; | |
3093 | #undef FLD | |
3094 | } | |
3095 | ||
3096 | /* lf-sfgt-s: lf.sfgt.s $rASF,$rBSF */ | |
6e51bfa7 SH |
3097 | |
3098 | static SEM_PC | |
7ccbb443 | 3099 | SEM_FN_NAME (or1k32bf,lf_sfgt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) |
6e51bfa7 SH |
3100 | { |
3101 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
3102 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3103 | int UNUSED written = 0; | |
3104 | IADDR UNUSED pc = abuf->addr; | |
3105 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3106 | ||
3107 | { | |
3108 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
3109 | SET_H_SYS_SR_F (opval); | |
3110 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3111 | } | |
3112 | ||
3113 | return vpc; | |
3114 | #undef FLD | |
3115 | } | |
3116 | ||
7ccbb443 SH |
3117 | /* lf-sfgt-d32: lf.sfgt.d $rAD32F,$rBD32F */ |
3118 | ||
3119 | static SEM_PC | |
3120 | SEM_FN_NAME (or1k32bf,lf_sfgt_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3121 | { | |
3122 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
3123 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3124 | int UNUSED written = 0; | |
3125 | IADDR UNUSED pc = abuf->addr; | |
3126 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3127 | ||
3128 | { | |
3129 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); | |
3130 | SET_H_SYS_SR_F (opval); | |
3131 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3132 | } | |
3133 | ||
3134 | return vpc; | |
3135 | #undef FLD | |
3136 | } | |
3137 | ||
3138 | /* lf-sflt-s: lf.sflt.s $rASF,$rBSF */ | |
6e51bfa7 SH |
3139 | |
3140 | static SEM_PC | |
7ccbb443 | 3141 | SEM_FN_NAME (or1k32bf,lf_sflt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) |
6e51bfa7 SH |
3142 | { |
3143 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
3144 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3145 | int UNUSED written = 0; | |
3146 | IADDR UNUSED pc = abuf->addr; | |
3147 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3148 | ||
3149 | { | |
3150 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
3151 | SET_H_SYS_SR_F (opval); | |
3152 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3153 | } | |
3154 | ||
3155 | return vpc; | |
3156 | #undef FLD | |
3157 | } | |
3158 | ||
7ccbb443 SH |
3159 | /* lf-sflt-d32: lf.sflt.d $rAD32F,$rBD32F */ |
3160 | ||
3161 | static SEM_PC | |
3162 | SEM_FN_NAME (or1k32bf,lf_sflt_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3163 | { | |
3164 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
3165 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3166 | int UNUSED written = 0; | |
3167 | IADDR UNUSED pc = abuf->addr; | |
3168 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3169 | ||
3170 | { | |
3171 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); | |
3172 | SET_H_SYS_SR_F (opval); | |
3173 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3174 | } | |
3175 | ||
3176 | return vpc; | |
3177 | #undef FLD | |
3178 | } | |
3179 | ||
3180 | /* lf-sfle-s: lf.sfle.s $rASF,$rBSF */ | |
6e51bfa7 SH |
3181 | |
3182 | static SEM_PC | |
7ccbb443 | 3183 | SEM_FN_NAME (or1k32bf,lf_sfle_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) |
6e51bfa7 SH |
3184 | { |
3185 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
3186 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3187 | int UNUSED written = 0; | |
3188 | IADDR UNUSED pc = abuf->addr; | |
3189 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3190 | ||
3191 | { | |
3192 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
3193 | SET_H_SYS_SR_F (opval); | |
3194 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3195 | } | |
3196 | ||
3197 | return vpc; | |
3198 | #undef FLD | |
3199 | } | |
3200 | ||
7ccbb443 SH |
3201 | /* lf-sfle-d32: lf.sfle.d $rAD32F,$rBD32F */ |
3202 | ||
3203 | static SEM_PC | |
3204 | SEM_FN_NAME (or1k32bf,lf_sfle_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3205 | { | |
3206 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
3207 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3208 | int UNUSED written = 0; | |
3209 | IADDR UNUSED pc = abuf->addr; | |
3210 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3211 | ||
3212 | { | |
3213 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); | |
3214 | SET_H_SYS_SR_F (opval); | |
3215 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3216 | } | |
3217 | ||
3218 | return vpc; | |
3219 | #undef FLD | |
3220 | } | |
3221 | ||
3222 | /* lf-sfueq-s: lf.sfueq.s $rASF,$rBSF */ | |
3223 | ||
3224 | static SEM_PC | |
3225 | SEM_FN_NAME (or1k32bf,lf_sfueq_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3226 | { | |
3227 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
3228 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3229 | int UNUSED written = 0; | |
3230 | IADDR UNUSED pc = abuf->addr; | |
3231 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3232 | ||
3233 | { | |
3234 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)))); | |
3235 | SET_H_SYS_SR_F (opval); | |
3236 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3237 | } | |
3238 | ||
3239 | return vpc; | |
3240 | #undef FLD | |
3241 | } | |
3242 | ||
3243 | /* lf-sfueq-d32: lf.sfueq.d $rAD32F,$rBD32F */ | |
3244 | ||
3245 | static SEM_PC | |
3246 | SEM_FN_NAME (or1k32bf,lf_sfueq_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3247 | { | |
3248 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
3249 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3250 | int UNUSED written = 0; | |
3251 | IADDR UNUSED pc = abuf->addr; | |
3252 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3253 | ||
3254 | { | |
3255 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)))); | |
3256 | SET_H_SYS_SR_F (opval); | |
3257 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3258 | } | |
3259 | ||
3260 | return vpc; | |
3261 | #undef FLD | |
3262 | } | |
3263 | ||
3264 | /* lf-sfune-s: lf.sfune.s $rASF,$rBSF */ | |
3265 | ||
3266 | static SEM_PC | |
3267 | SEM_FN_NAME (or1k32bf,lf_sfune_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3268 | { | |
3269 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
3270 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3271 | int UNUSED written = 0; | |
3272 | IADDR UNUSED pc = abuf->addr; | |
3273 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3274 | ||
3275 | { | |
3276 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)))); | |
3277 | SET_H_SYS_SR_F (opval); | |
3278 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3279 | } | |
3280 | ||
3281 | return vpc; | |
3282 | #undef FLD | |
3283 | } | |
3284 | ||
3285 | /* lf-sfune-d32: lf.sfune.d $rAD32F,$rBD32F */ | |
3286 | ||
3287 | static SEM_PC | |
3288 | SEM_FN_NAME (or1k32bf,lf_sfune_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3289 | { | |
3290 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
3291 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3292 | int UNUSED written = 0; | |
3293 | IADDR UNUSED pc = abuf->addr; | |
3294 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3295 | ||
3296 | { | |
3297 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)))); | |
3298 | SET_H_SYS_SR_F (opval); | |
3299 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3300 | } | |
3301 | ||
3302 | return vpc; | |
3303 | #undef FLD | |
3304 | } | |
3305 | ||
3306 | /* lf-sfugt-s: lf.sfugt.s $rASF,$rBSF */ | |
3307 | ||
3308 | static SEM_PC | |
3309 | SEM_FN_NAME (or1k32bf,lf_sfugt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3310 | { | |
3311 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
3312 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3313 | int UNUSED written = 0; | |
3314 | IADDR UNUSED pc = abuf->addr; | |
3315 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3316 | ||
3317 | { | |
3318 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)))); | |
3319 | SET_H_SYS_SR_F (opval); | |
3320 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3321 | } | |
3322 | ||
3323 | return vpc; | |
3324 | #undef FLD | |
3325 | } | |
3326 | ||
3327 | /* lf-sfugt-d32: lf.sfugt.d $rAD32F,$rBD32F */ | |
3328 | ||
3329 | static SEM_PC | |
3330 | SEM_FN_NAME (or1k32bf,lf_sfugt_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3331 | { | |
3332 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
3333 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3334 | int UNUSED written = 0; | |
3335 | IADDR UNUSED pc = abuf->addr; | |
3336 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3337 | ||
3338 | { | |
3339 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)))); | |
3340 | SET_H_SYS_SR_F (opval); | |
3341 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3342 | } | |
3343 | ||
3344 | return vpc; | |
3345 | #undef FLD | |
3346 | } | |
3347 | ||
3348 | /* lf-sfuge-s: lf.sfuge.s $rASF,$rBSF */ | |
3349 | ||
3350 | static SEM_PC | |
3351 | SEM_FN_NAME (or1k32bf,lf_sfuge_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3352 | { | |
3353 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
3354 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3355 | int UNUSED written = 0; | |
3356 | IADDR UNUSED pc = abuf->addr; | |
3357 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3358 | ||
3359 | { | |
3360 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)))); | |
3361 | SET_H_SYS_SR_F (opval); | |
3362 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3363 | } | |
3364 | ||
3365 | return vpc; | |
3366 | #undef FLD | |
3367 | } | |
3368 | ||
3369 | /* lf-sfuge-d32: lf.sfuge.d $rAD32F,$rBD32F */ | |
3370 | ||
3371 | static SEM_PC | |
3372 | SEM_FN_NAME (or1k32bf,lf_sfuge_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3373 | { | |
3374 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
3375 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3376 | int UNUSED written = 0; | |
3377 | IADDR UNUSED pc = abuf->addr; | |
3378 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3379 | ||
3380 | { | |
3381 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)))); | |
3382 | SET_H_SYS_SR_F (opval); | |
3383 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3384 | } | |
3385 | ||
3386 | return vpc; | |
3387 | #undef FLD | |
3388 | } | |
3389 | ||
3390 | /* lf-sfult-s: lf.sfult.s $rASF,$rBSF */ | |
3391 | ||
3392 | static SEM_PC | |
3393 | SEM_FN_NAME (or1k32bf,lf_sfult_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3394 | { | |
3395 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
3396 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3397 | int UNUSED written = 0; | |
3398 | IADDR UNUSED pc = abuf->addr; | |
3399 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3400 | ||
3401 | { | |
3402 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)))); | |
3403 | SET_H_SYS_SR_F (opval); | |
3404 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3405 | } | |
3406 | ||
3407 | return vpc; | |
3408 | #undef FLD | |
3409 | } | |
3410 | ||
3411 | /* lf-sfult-d32: lf.sfult.d $rAD32F,$rBD32F */ | |
3412 | ||
3413 | static SEM_PC | |
3414 | SEM_FN_NAME (or1k32bf,lf_sfult_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3415 | { | |
3416 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
3417 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3418 | int UNUSED written = 0; | |
3419 | IADDR UNUSED pc = abuf->addr; | |
3420 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3421 | ||
3422 | { | |
3423 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)))); | |
3424 | SET_H_SYS_SR_F (opval); | |
3425 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3426 | } | |
3427 | ||
3428 | return vpc; | |
3429 | #undef FLD | |
3430 | } | |
3431 | ||
3432 | /* lf-sfule-s: lf.sfule.s $rASF,$rBSF */ | |
3433 | ||
3434 | static SEM_PC | |
3435 | SEM_FN_NAME (or1k32bf,lf_sfule_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3436 | { | |
3437 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
3438 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3439 | int UNUSED written = 0; | |
3440 | IADDR UNUSED pc = abuf->addr; | |
3441 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3442 | ||
3443 | { | |
3444 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)))); | |
3445 | SET_H_SYS_SR_F (opval); | |
3446 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3447 | } | |
3448 | ||
3449 | return vpc; | |
3450 | #undef FLD | |
3451 | } | |
3452 | ||
3453 | /* lf-sfule-d32: lf.sfule.d $rAD32F,$rBD32F */ | |
3454 | ||
3455 | static SEM_PC | |
3456 | SEM_FN_NAME (or1k32bf,lf_sfule_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3457 | { | |
3458 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
3459 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3460 | int UNUSED written = 0; | |
3461 | IADDR UNUSED pc = abuf->addr; | |
3462 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3463 | ||
3464 | { | |
3465 | BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)))); | |
3466 | SET_H_SYS_SR_F (opval); | |
3467 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3468 | } | |
3469 | ||
3470 | return vpc; | |
3471 | #undef FLD | |
3472 | } | |
3473 | ||
3474 | /* lf-sfun-s: lf.sfun.s $rASF,$rBSF */ | |
3475 | ||
3476 | static SEM_PC | |
3477 | SEM_FN_NAME (or1k32bf,lf_sfun_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3478 | { | |
3479 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
3480 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3481 | int UNUSED written = 0; | |
3482 | IADDR UNUSED pc = abuf->addr; | |
3483 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3484 | ||
3485 | { | |
3486 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))); | |
3487 | SET_H_SYS_SR_F (opval); | |
3488 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3489 | } | |
3490 | ||
3491 | return vpc; | |
3492 | #undef FLD | |
3493 | } | |
3494 | ||
3495 | /* lf-sfun-d32: lf.sfun.d $rAD32F,$rBD32F */ | |
3496 | ||
3497 | static SEM_PC | |
3498 | SEM_FN_NAME (or1k32bf,lf_sfun_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3499 | { | |
3500 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
3501 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3502 | int UNUSED written = 0; | |
3503 | IADDR UNUSED pc = abuf->addr; | |
3504 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3505 | ||
3506 | { | |
3507 | BI opval = CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))); | |
3508 | SET_H_SYS_SR_F (opval); | |
3509 | CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval); | |
3510 | } | |
3511 | ||
3512 | return vpc; | |
3513 | #undef FLD | |
3514 | } | |
3515 | ||
6e51bfa7 SH |
3516 | /* lf-madd-s: lf.madd.s $rDSF,$rASF,$rBSF */ |
3517 | ||
3518 | static SEM_PC | |
3519 | SEM_FN_NAME (or1k32bf,lf_madd_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3520 | { | |
3521 | #define FLD(f) abuf->fields.sfmt_l_sll.f | |
3522 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3523 | int UNUSED written = 0; | |
3524 | IADDR UNUSED pc = abuf->addr; | |
3525 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3526 | ||
3527 | { | |
3528 | SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), GET_H_FSR (FLD (f_r1))); | |
3529 | SET_H_FSR (FLD (f_r1), opval); | |
3530 | CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval); | |
3531 | } | |
3532 | ||
3533 | return vpc; | |
3534 | #undef FLD | |
3535 | } | |
3536 | ||
7ccbb443 SH |
3537 | /* lf-madd-d32: lf.madd.d $rDD32F,$rAD32F,$rBD32F */ |
3538 | ||
3539 | static SEM_PC | |
3540 | SEM_FN_NAME (or1k32bf,lf_madd_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3541 | { | |
3542 | #define FLD(f) abuf->fields.sfmt_lf_add_d32.f | |
3543 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3544 | int UNUSED written = 0; | |
3545 | IADDR UNUSED pc = abuf->addr; | |
3546 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3547 | ||
3548 | { | |
3549 | DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), GET_H_FD32R (FLD (f_rdd32))); | |
3550 | SET_H_FD32R (FLD (f_rdd32), opval); | |
3551 | CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval); | |
3552 | } | |
3553 | ||
3554 | return vpc; | |
3555 | #undef FLD | |
3556 | } | |
3557 | ||
6e51bfa7 SH |
3558 | /* lf-cust1-s: lf.cust1.s $rASF,$rBSF */ |
3559 | ||
3560 | static SEM_PC | |
3561 | SEM_FN_NAME (or1k32bf,lf_cust1_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3562 | { | |
3563 | #define FLD(f) abuf->fields.sfmt_empty.f | |
3564 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3565 | int UNUSED written = 0; | |
3566 | IADDR UNUSED pc = abuf->addr; | |
3567 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3568 | ||
3569 | ((void) 0); /*nop*/ | |
3570 | ||
3571 | return vpc; | |
3572 | #undef FLD | |
3573 | } | |
3574 | ||
7ccbb443 SH |
3575 | /* lf-cust1-d32: lf.cust1.d */ |
3576 | ||
3577 | static SEM_PC | |
3578 | SEM_FN_NAME (or1k32bf,lf_cust1_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) | |
3579 | { | |
3580 | #define FLD(f) abuf->fields.sfmt_empty.f | |
3581 | ARGBUF *abuf = SEM_ARGBUF (sem_arg); | |
3582 | int UNUSED written = 0; | |
3583 | IADDR UNUSED pc = abuf->addr; | |
3584 | SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); | |
3585 | ||
3586 | ((void) 0); /*nop*/ | |
3587 | ||
3588 | return vpc; | |
3589 | #undef FLD | |
3590 | } | |
3591 | ||
6e51bfa7 SH |
3592 | /* Table of all semantic fns. */ |
3593 | ||
3594 | static const struct sem_fn_desc sem_fns[] = { | |
3595 | { OR1K32BF_INSN_X_INVALID, SEM_FN_NAME (or1k32bf,x_invalid) }, | |
3596 | { OR1K32BF_INSN_X_AFTER, SEM_FN_NAME (or1k32bf,x_after) }, | |
3597 | { OR1K32BF_INSN_X_BEFORE, SEM_FN_NAME (or1k32bf,x_before) }, | |
3598 | { OR1K32BF_INSN_X_CTI_CHAIN, SEM_FN_NAME (or1k32bf,x_cti_chain) }, | |
3599 | { OR1K32BF_INSN_X_CHAIN, SEM_FN_NAME (or1k32bf,x_chain) }, | |
3600 | { OR1K32BF_INSN_X_BEGIN, SEM_FN_NAME (or1k32bf,x_begin) }, | |
3601 | { OR1K32BF_INSN_L_J, SEM_FN_NAME (or1k32bf,l_j) }, | |
07f5f4c6 | 3602 | { OR1K32BF_INSN_L_ADRP, SEM_FN_NAME (or1k32bf,l_adrp) }, |
6e51bfa7 SH |
3603 | { OR1K32BF_INSN_L_JAL, SEM_FN_NAME (or1k32bf,l_jal) }, |
3604 | { OR1K32BF_INSN_L_JR, SEM_FN_NAME (or1k32bf,l_jr) }, | |
3605 | { OR1K32BF_INSN_L_JALR, SEM_FN_NAME (or1k32bf,l_jalr) }, | |
3606 | { OR1K32BF_INSN_L_BNF, SEM_FN_NAME (or1k32bf,l_bnf) }, | |
3607 | { OR1K32BF_INSN_L_BF, SEM_FN_NAME (or1k32bf,l_bf) }, | |
3608 | { OR1K32BF_INSN_L_TRAP, SEM_FN_NAME (or1k32bf,l_trap) }, | |
3609 | { OR1K32BF_INSN_L_SYS, SEM_FN_NAME (or1k32bf,l_sys) }, | |
3610 | { OR1K32BF_INSN_L_MSYNC, SEM_FN_NAME (or1k32bf,l_msync) }, | |
3611 | { OR1K32BF_INSN_L_PSYNC, SEM_FN_NAME (or1k32bf,l_psync) }, | |
3612 | { OR1K32BF_INSN_L_CSYNC, SEM_FN_NAME (or1k32bf,l_csync) }, | |
3613 | { OR1K32BF_INSN_L_RFE, SEM_FN_NAME (or1k32bf,l_rfe) }, | |
3614 | { OR1K32BF_INSN_L_NOP_IMM, SEM_FN_NAME (or1k32bf,l_nop_imm) }, | |
3615 | { OR1K32BF_INSN_L_MOVHI, SEM_FN_NAME (or1k32bf,l_movhi) }, | |
3616 | { OR1K32BF_INSN_L_MACRC, SEM_FN_NAME (or1k32bf,l_macrc) }, | |
3617 | { OR1K32BF_INSN_L_MFSPR, SEM_FN_NAME (or1k32bf,l_mfspr) }, | |
3618 | { OR1K32BF_INSN_L_MTSPR, SEM_FN_NAME (or1k32bf,l_mtspr) }, | |
3619 | { OR1K32BF_INSN_L_LWZ, SEM_FN_NAME (or1k32bf,l_lwz) }, | |
3620 | { OR1K32BF_INSN_L_LWS, SEM_FN_NAME (or1k32bf,l_lws) }, | |
3621 | { OR1K32BF_INSN_L_LWA, SEM_FN_NAME (or1k32bf,l_lwa) }, | |
3622 | { OR1K32BF_INSN_L_LBZ, SEM_FN_NAME (or1k32bf,l_lbz) }, | |
3623 | { OR1K32BF_INSN_L_LBS, SEM_FN_NAME (or1k32bf,l_lbs) }, | |
3624 | { OR1K32BF_INSN_L_LHZ, SEM_FN_NAME (or1k32bf,l_lhz) }, | |
3625 | { OR1K32BF_INSN_L_LHS, SEM_FN_NAME (or1k32bf,l_lhs) }, | |
3626 | { OR1K32BF_INSN_L_SW, SEM_FN_NAME (or1k32bf,l_sw) }, | |
3627 | { OR1K32BF_INSN_L_SB, SEM_FN_NAME (or1k32bf,l_sb) }, | |
3628 | { OR1K32BF_INSN_L_SH, SEM_FN_NAME (or1k32bf,l_sh) }, | |
3629 | { OR1K32BF_INSN_L_SWA, SEM_FN_NAME (or1k32bf,l_swa) }, | |
3630 | { OR1K32BF_INSN_L_SLL, SEM_FN_NAME (or1k32bf,l_sll) }, | |
3631 | { OR1K32BF_INSN_L_SLLI, SEM_FN_NAME (or1k32bf,l_slli) }, | |
3632 | { OR1K32BF_INSN_L_SRL, SEM_FN_NAME (or1k32bf,l_srl) }, | |
3633 | { OR1K32BF_INSN_L_SRLI, SEM_FN_NAME (or1k32bf,l_srli) }, | |
3634 | { OR1K32BF_INSN_L_SRA, SEM_FN_NAME (or1k32bf,l_sra) }, | |
3635 | { OR1K32BF_INSN_L_SRAI, SEM_FN_NAME (or1k32bf,l_srai) }, | |
3636 | { OR1K32BF_INSN_L_ROR, SEM_FN_NAME (or1k32bf,l_ror) }, | |
3637 | { OR1K32BF_INSN_L_RORI, SEM_FN_NAME (or1k32bf,l_rori) }, | |
3638 | { OR1K32BF_INSN_L_AND, SEM_FN_NAME (or1k32bf,l_and) }, | |
3639 | { OR1K32BF_INSN_L_OR, SEM_FN_NAME (or1k32bf,l_or) }, | |
3640 | { OR1K32BF_INSN_L_XOR, SEM_FN_NAME (or1k32bf,l_xor) }, | |
3641 | { OR1K32BF_INSN_L_ADD, SEM_FN_NAME (or1k32bf,l_add) }, | |
3642 | { OR1K32BF_INSN_L_SUB, SEM_FN_NAME (or1k32bf,l_sub) }, | |
3643 | { OR1K32BF_INSN_L_ADDC, SEM_FN_NAME (or1k32bf,l_addc) }, | |
3644 | { OR1K32BF_INSN_L_MUL, SEM_FN_NAME (or1k32bf,l_mul) }, | |
07f5f4c6 | 3645 | { OR1K32BF_INSN_L_MULD, SEM_FN_NAME (or1k32bf,l_muld) }, |
6e51bfa7 | 3646 | { OR1K32BF_INSN_L_MULU, SEM_FN_NAME (or1k32bf,l_mulu) }, |
07f5f4c6 | 3647 | { OR1K32BF_INSN_L_MULDU, SEM_FN_NAME (or1k32bf,l_muldu) }, |
6e51bfa7 SH |
3648 | { OR1K32BF_INSN_L_DIV, SEM_FN_NAME (or1k32bf,l_div) }, |
3649 | { OR1K32BF_INSN_L_DIVU, SEM_FN_NAME (or1k32bf,l_divu) }, | |
3650 | { OR1K32BF_INSN_L_FF1, SEM_FN_NAME (or1k32bf,l_ff1) }, | |
3651 | { OR1K32BF_INSN_L_FL1, SEM_FN_NAME (or1k32bf,l_fl1) }, | |
3652 | { OR1K32BF_INSN_L_ANDI, SEM_FN_NAME (or1k32bf,l_andi) }, | |
3653 | { OR1K32BF_INSN_L_ORI, SEM_FN_NAME (or1k32bf,l_ori) }, | |
3654 | { OR1K32BF_INSN_L_XORI, SEM_FN_NAME (or1k32bf,l_xori) }, | |
3655 | { OR1K32BF_INSN_L_ADDI, SEM_FN_NAME (or1k32bf,l_addi) }, | |
3656 | { OR1K32BF_INSN_L_ADDIC, SEM_FN_NAME (or1k32bf,l_addic) }, | |
3657 | { OR1K32BF_INSN_L_MULI, SEM_FN_NAME (or1k32bf,l_muli) }, | |
3658 | { OR1K32BF_INSN_L_EXTHS, SEM_FN_NAME (or1k32bf,l_exths) }, | |
3659 | { OR1K32BF_INSN_L_EXTBS, SEM_FN_NAME (or1k32bf,l_extbs) }, | |
3660 | { OR1K32BF_INSN_L_EXTHZ, SEM_FN_NAME (or1k32bf,l_exthz) }, | |
3661 | { OR1K32BF_INSN_L_EXTBZ, SEM_FN_NAME (or1k32bf,l_extbz) }, | |
3662 | { OR1K32BF_INSN_L_EXTWS, SEM_FN_NAME (or1k32bf,l_extws) }, | |
3663 | { OR1K32BF_INSN_L_EXTWZ, SEM_FN_NAME (or1k32bf,l_extwz) }, | |
3664 | { OR1K32BF_INSN_L_CMOV, SEM_FN_NAME (or1k32bf,l_cmov) }, | |
3665 | { OR1K32BF_INSN_L_SFGTS, SEM_FN_NAME (or1k32bf,l_sfgts) }, | |
3666 | { OR1K32BF_INSN_L_SFGTSI, SEM_FN_NAME (or1k32bf,l_sfgtsi) }, | |
3667 | { OR1K32BF_INSN_L_SFGTU, SEM_FN_NAME (or1k32bf,l_sfgtu) }, | |
3668 | { OR1K32BF_INSN_L_SFGTUI, SEM_FN_NAME (or1k32bf,l_sfgtui) }, | |
3669 | { OR1K32BF_INSN_L_SFGES, SEM_FN_NAME (or1k32bf,l_sfges) }, | |
3670 | { OR1K32BF_INSN_L_SFGESI, SEM_FN_NAME (or1k32bf,l_sfgesi) }, | |
3671 | { OR1K32BF_INSN_L_SFGEU, SEM_FN_NAME (or1k32bf,l_sfgeu) }, | |
3672 | { OR1K32BF_INSN_L_SFGEUI, SEM_FN_NAME (or1k32bf,l_sfgeui) }, | |
3673 | { OR1K32BF_INSN_L_SFLTS, SEM_FN_NAME (or1k32bf,l_sflts) }, | |
3674 | { OR1K32BF_INSN_L_SFLTSI, SEM_FN_NAME (or1k32bf,l_sfltsi) }, | |
3675 | { OR1K32BF_INSN_L_SFLTU, SEM_FN_NAME (or1k32bf,l_sfltu) }, | |
3676 | { OR1K32BF_INSN_L_SFLTUI, SEM_FN_NAME (or1k32bf,l_sfltui) }, | |
3677 | { OR1K32BF_INSN_L_SFLES, SEM_FN_NAME (or1k32bf,l_sfles) }, | |
3678 | { OR1K32BF_INSN_L_SFLESI, SEM_FN_NAME (or1k32bf,l_sflesi) }, | |
3679 | { OR1K32BF_INSN_L_SFLEU, SEM_FN_NAME (or1k32bf,l_sfleu) }, | |
3680 | { OR1K32BF_INSN_L_SFLEUI, SEM_FN_NAME (or1k32bf,l_sfleui) }, | |
3681 | { OR1K32BF_INSN_L_SFEQ, SEM_FN_NAME (or1k32bf,l_sfeq) }, | |
3682 | { OR1K32BF_INSN_L_SFEQI, SEM_FN_NAME (or1k32bf,l_sfeqi) }, | |
3683 | { OR1K32BF_INSN_L_SFNE, SEM_FN_NAME (or1k32bf,l_sfne) }, | |
3684 | { OR1K32BF_INSN_L_SFNEI, SEM_FN_NAME (or1k32bf,l_sfnei) }, | |
3685 | { OR1K32BF_INSN_L_MAC, SEM_FN_NAME (or1k32bf,l_mac) }, | |
6e51bfa7 | 3686 | { OR1K32BF_INSN_L_MACI, SEM_FN_NAME (or1k32bf,l_maci) }, |
07f5f4c6 RH |
3687 | { OR1K32BF_INSN_L_MACU, SEM_FN_NAME (or1k32bf,l_macu) }, |
3688 | { OR1K32BF_INSN_L_MSB, SEM_FN_NAME (or1k32bf,l_msb) }, | |
3689 | { OR1K32BF_INSN_L_MSBU, SEM_FN_NAME (or1k32bf,l_msbu) }, | |
6e51bfa7 SH |
3690 | { OR1K32BF_INSN_L_CUST1, SEM_FN_NAME (or1k32bf,l_cust1) }, |
3691 | { OR1K32BF_INSN_L_CUST2, SEM_FN_NAME (or1k32bf,l_cust2) }, | |
3692 | { OR1K32BF_INSN_L_CUST3, SEM_FN_NAME (or1k32bf,l_cust3) }, | |
3693 | { OR1K32BF_INSN_L_CUST4, SEM_FN_NAME (or1k32bf,l_cust4) }, | |
3694 | { OR1K32BF_INSN_L_CUST5, SEM_FN_NAME (or1k32bf,l_cust5) }, | |
3695 | { OR1K32BF_INSN_L_CUST6, SEM_FN_NAME (or1k32bf,l_cust6) }, | |
3696 | { OR1K32BF_INSN_L_CUST7, SEM_FN_NAME (or1k32bf,l_cust7) }, | |
3697 | { OR1K32BF_INSN_L_CUST8, SEM_FN_NAME (or1k32bf,l_cust8) }, | |
3698 | { OR1K32BF_INSN_LF_ADD_S, SEM_FN_NAME (or1k32bf,lf_add_s) }, | |
7ccbb443 | 3699 | { OR1K32BF_INSN_LF_ADD_D32, SEM_FN_NAME (or1k32bf,lf_add_d32) }, |
6e51bfa7 | 3700 | { OR1K32BF_INSN_LF_SUB_S, SEM_FN_NAME (or1k32bf,lf_sub_s) }, |
7ccbb443 | 3701 | { OR1K32BF_INSN_LF_SUB_D32, SEM_FN_NAME (or1k32bf,lf_sub_d32) }, |
6e51bfa7 | 3702 | { OR1K32BF_INSN_LF_MUL_S, SEM_FN_NAME (or1k32bf,lf_mul_s) }, |
7ccbb443 | 3703 | { OR1K32BF_INSN_LF_MUL_D32, SEM_FN_NAME (or1k32bf,lf_mul_d32) }, |
6e51bfa7 | 3704 | { OR1K32BF_INSN_LF_DIV_S, SEM_FN_NAME (or1k32bf,lf_div_s) }, |
7ccbb443 | 3705 | { OR1K32BF_INSN_LF_DIV_D32, SEM_FN_NAME (or1k32bf,lf_div_d32) }, |
6e51bfa7 | 3706 | { OR1K32BF_INSN_LF_REM_S, SEM_FN_NAME (or1k32bf,lf_rem_s) }, |
7ccbb443 | 3707 | { OR1K32BF_INSN_LF_REM_D32, SEM_FN_NAME (or1k32bf,lf_rem_d32) }, |
6e51bfa7 | 3708 | { OR1K32BF_INSN_LF_ITOF_S, SEM_FN_NAME (or1k32bf,lf_itof_s) }, |
7ccbb443 | 3709 | { OR1K32BF_INSN_LF_ITOF_D32, SEM_FN_NAME (or1k32bf,lf_itof_d32) }, |
6e51bfa7 | 3710 | { OR1K32BF_INSN_LF_FTOI_S, SEM_FN_NAME (or1k32bf,lf_ftoi_s) }, |
7ccbb443 SH |
3711 | { OR1K32BF_INSN_LF_FTOI_D32, SEM_FN_NAME (or1k32bf,lf_ftoi_d32) }, |
3712 | { OR1K32BF_INSN_LF_SFEQ_S, SEM_FN_NAME (or1k32bf,lf_sfeq_s) }, | |
3713 | { OR1K32BF_INSN_LF_SFEQ_D32, SEM_FN_NAME (or1k32bf,lf_sfeq_d32) }, | |
3714 | { OR1K32BF_INSN_LF_SFNE_S, SEM_FN_NAME (or1k32bf,lf_sfne_s) }, | |
3715 | { OR1K32BF_INSN_LF_SFNE_D32, SEM_FN_NAME (or1k32bf,lf_sfne_d32) }, | |
3716 | { OR1K32BF_INSN_LF_SFGE_S, SEM_FN_NAME (or1k32bf,lf_sfge_s) }, | |
3717 | { OR1K32BF_INSN_LF_SFGE_D32, SEM_FN_NAME (or1k32bf,lf_sfge_d32) }, | |
3718 | { OR1K32BF_INSN_LF_SFGT_S, SEM_FN_NAME (or1k32bf,lf_sfgt_s) }, | |
3719 | { OR1K32BF_INSN_LF_SFGT_D32, SEM_FN_NAME (or1k32bf,lf_sfgt_d32) }, | |
3720 | { OR1K32BF_INSN_LF_SFLT_S, SEM_FN_NAME (or1k32bf,lf_sflt_s) }, | |
3721 | { OR1K32BF_INSN_LF_SFLT_D32, SEM_FN_NAME (or1k32bf,lf_sflt_d32) }, | |
3722 | { OR1K32BF_INSN_LF_SFLE_S, SEM_FN_NAME (or1k32bf,lf_sfle_s) }, | |
3723 | { OR1K32BF_INSN_LF_SFLE_D32, SEM_FN_NAME (or1k32bf,lf_sfle_d32) }, | |
3724 | { OR1K32BF_INSN_LF_SFUEQ_S, SEM_FN_NAME (or1k32bf,lf_sfueq_s) }, | |
3725 | { OR1K32BF_INSN_LF_SFUEQ_D32, SEM_FN_NAME (or1k32bf,lf_sfueq_d32) }, | |
3726 | { OR1K32BF_INSN_LF_SFUNE_S, SEM_FN_NAME (or1k32bf,lf_sfune_s) }, | |
3727 | { OR1K32BF_INSN_LF_SFUNE_D32, SEM_FN_NAME (or1k32bf,lf_sfune_d32) }, | |
3728 | { OR1K32BF_INSN_LF_SFUGT_S, SEM_FN_NAME (or1k32bf,lf_sfugt_s) }, | |
3729 | { OR1K32BF_INSN_LF_SFUGT_D32, SEM_FN_NAME (or1k32bf,lf_sfugt_d32) }, | |
3730 | { OR1K32BF_INSN_LF_SFUGE_S, SEM_FN_NAME (or1k32bf,lf_sfuge_s) }, | |
3731 | { OR1K32BF_INSN_LF_SFUGE_D32, SEM_FN_NAME (or1k32bf,lf_sfuge_d32) }, | |
3732 | { OR1K32BF_INSN_LF_SFULT_S, SEM_FN_NAME (or1k32bf,lf_sfult_s) }, | |
3733 | { OR1K32BF_INSN_LF_SFULT_D32, SEM_FN_NAME (or1k32bf,lf_sfult_d32) }, | |
3734 | { OR1K32BF_INSN_LF_SFULE_S, SEM_FN_NAME (or1k32bf,lf_sfule_s) }, | |
3735 | { OR1K32BF_INSN_LF_SFULE_D32, SEM_FN_NAME (or1k32bf,lf_sfule_d32) }, | |
3736 | { OR1K32BF_INSN_LF_SFUN_S, SEM_FN_NAME (or1k32bf,lf_sfun_s) }, | |
3737 | { OR1K32BF_INSN_LF_SFUN_D32, SEM_FN_NAME (or1k32bf,lf_sfun_d32) }, | |
6e51bfa7 | 3738 | { OR1K32BF_INSN_LF_MADD_S, SEM_FN_NAME (or1k32bf,lf_madd_s) }, |
7ccbb443 | 3739 | { OR1K32BF_INSN_LF_MADD_D32, SEM_FN_NAME (or1k32bf,lf_madd_d32) }, |
6e51bfa7 | 3740 | { OR1K32BF_INSN_LF_CUST1_S, SEM_FN_NAME (or1k32bf,lf_cust1_s) }, |
7ccbb443 | 3741 | { OR1K32BF_INSN_LF_CUST1_D32, SEM_FN_NAME (or1k32bf,lf_cust1_d32) }, |
6e51bfa7 SH |
3742 | { 0, 0 } |
3743 | }; | |
3744 | ||
3745 | /* Add the semantic fns to IDESC_TABLE. */ | |
3746 | ||
3747 | void | |
3748 | SEM_FN_NAME (or1k32bf,init_idesc_table) (SIM_CPU *current_cpu) | |
3749 | { | |
3750 | IDESC *idesc_table = CPU_IDESC (current_cpu); | |
3751 | const struct sem_fn_desc *sf; | |
3752 | int mach_num = MACH_NUM (CPU_MACH (current_cpu)); | |
3753 | ||
3754 | for (sf = &sem_fns[0]; sf->fn != 0; ++sf) | |
3755 | { | |
3756 | const CGEN_INSN *insn = idesc_table[sf->index].idata; | |
3757 | int valid_p = (CGEN_INSN_VIRTUAL_P (insn) | |
3758 | || CGEN_INSN_MACH_HAS_P (insn, mach_num)); | |
3759 | #if FAST_P | |
3760 | if (valid_p) | |
3761 | idesc_table[sf->index].sem_fast = sf->fn; | |
3762 | else | |
3763 | idesc_table[sf->index].sem_fast = SEM_FN_NAME (or1k32bf,x_invalid); | |
3764 | #else | |
3765 | if (valid_p) | |
3766 | idesc_table[sf->index].sem_full = sf->fn; | |
3767 | else | |
3768 | idesc_table[sf->index].sem_full = SEM_FN_NAME (or1k32bf,x_invalid); | |
3769 | #endif | |
3770 | } | |
3771 | } | |
3772 |